system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17refCounter_kernelPjS_S_S_jjjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0011e80000004800 */
/*0040*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ I2F.U32.RP R4, c[0x0][0x18c] ; /* 0x0000630000047b06 */
/* 0x001e220000209000 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0080*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x18c], PT ; /* 0x00006300ff007a0c */
/* 0x000fe20003f25070 */
/*0090*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0a7624 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc400078e00ff */
/*00c0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*00e0*/ LOP3.LUT R13, R10.reuse, 0x2, RZ, 0xc0, !PT ; /* 0x000000020a0d7812 */
/* 0x040fe200078ec0ff */
/*00f0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e280000001000 */
/*0100*/ IMAD.IADD R12, R10, 0x1, -R13 ; /* 0x000000010a0c7824 */
/* 0x000fe200078e0a0d */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0120*/ IMAD R4, R5, c[0x0][0x0], R0 ; /* 0x0000000005047a24 */
/* 0x002fc600078e0200 */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R7, R7, c[0x0][0x18c], RZ ; /* 0x0000630007077a24 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0180*/ IADD3 R2, R10, -0x1, RZ ; /* 0xffffffff0a027810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P2, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f46070 */
/*01a0*/ IMAD.HI.U32 R3, R3, R5, RZ ; /* 0x0000000503037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R3, R6, c[0x0][0x18c], R5 ; /* 0x0000630006037a24 */
/* 0x000fca00078e0205 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IADD3 R3, R3, -c[0x0][0x18c], RZ ; /* 0x8000630003030a10 */
/* 0x000fc80007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x18c], PT ; /* 0x0000630003007a0c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IADD3 R3, R3, -c[0x0][0x18c], RZ ; /* 0x8000630003030a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x18c], RZ, 0x33, !PT ; /* 0x00006300ff039a12 */
/* 0x000fca00078e33ff */
/*0220*/ IMAD R8, R3, c[0x0][0x190], R0 ; /* 0x0000640003087a24 */
/* 0x000fe400078e0200 */
/*0230*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0009 */
/*0240*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0009 */
/*0250*/ IMAD.WIDE.U32 R6, R8, R9, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x000fc800078e0009 */
/*0260*/ IMAD.WIDE.U32 R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fc800078e0009 */
/*0270*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0280*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1 ; /* 0x00000001ff0f7424 */
/* 0x009fe200078e00ff */
/*0290*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*02a0*/ RED.E.ADD.STRONG.GPU [R6.64], R15 ; /* 0x0000000f0600798e */
/* 0x0001e2000c10e184 */
/*02b0*/ ISETP.GE.U32.AND P1, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fc60003f26070 */
/*02c0*/ RED.E.ADD.STRONG.GPU [R8.64], R15 ; /* 0x0000000f0800798e */
/* 0x0001e6000c10e184 */
/*02d0*/ @!P0 BRA 0xc50 ; /* 0x0000097000008947 */
/* 0x006fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*02f0*/ @!P2 BRA 0xbb0 ; /* 0x000008b00000a947 */
/* 0x000fea0003800000 */
/*0300*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f04270 */
/*0310*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fd400078e000c */
/*0330*/ @!P0 BRA 0xa70 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.GT.AND P3, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe40003f64270 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0360*/ @!P3 BRA 0x7f0 ; /* 0x000004800000b947 */
/* 0x000fea0003800000 */
/*0370*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0380*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e620000004800 */
/*0390*/ IADD3 R16, R16, -0x10, RZ ; /* 0xfffffff010107810 */
/* 0x000fc80007ffe0ff */
/*03a0*/ ISETP.GT.AND P3, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe20003f64270 */
/*03b0*/ IMAD.IADD R17, R17, 0x1, R14 ; /* 0x0000000111117824 */
/* 0x002fca00078e020e */
/*03c0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0003e80000004800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*03e0*/ IADD3 R17, R14, 0x4, RZ ; /* 0x000000040e117810 */
/* 0x002fca0007ffe0ff */
/*03f0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0400*/ IADD3 R19, R14, 0x1, R19 ; /* 0x000000010e137810 */
/* 0x002fca0007ffe013 */
/*0410*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0440*/ IADD3 R21, R14, 0x2, R21 ; /* 0x000000020e157810 */
/* 0x002fca0007ffe015 */
/*0450*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0480*/ IADD3 R23, R14, 0x3, R23 ; /* 0x000000030e177810 */
/* 0x002fca0007ffe017 */
/*0490*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*04a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04b0*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*04c0*/ IMAD.IADD R19, R17, 0x1, R18 ; /* 0x0000000111137824 */
/* 0x002fca00078e0212 */
/*04d0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04f0*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0500*/ IADD3 R21, R17, 0x1, R18 ; /* 0x0000000111157810 */
/* 0x002fca0007ffe012 */
/*0510*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0540*/ IADD3 R23, R17, 0x2, R18 ; /* 0x0000000211177810 */
/* 0x002fca0007ffe012 */
/*0550*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0570*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0580*/ IADD3 R17, R17, 0x3, R18 ; /* 0x0000000311117810 */
/* 0x002fc40007ffe012 */
/*0590*/ IADD3 R18, R14, 0x8, RZ ; /* 0x000000080e127810 */
/* 0x000fc60007ffe0ff */
/*05a0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*05b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05c0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*05d0*/ IMAD.IADD R19, R18, 0x1, R19 ; /* 0x0000000112137824 */
/* 0x002fca00078e0213 */
/*05e0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*05f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0600*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0610*/ IADD3 R21, R18, 0x1, R21 ; /* 0x0000000112157810 */
/* 0x002fca0007ffe015 */
/*0620*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e640000004800 */
/*0650*/ IADD3 R17, R18, 0x2, R17 ; /* 0x0000000212117810 */
/* 0x002fca0007ffe011 */
/*0660*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0690*/ IADD3 R23, R18, 0x3, R23 ; /* 0x0000000312177810 */
/* 0x002fc40007ffe017 */
/*06a0*/ IADD3 R18, R14.reuse, 0xc, RZ ; /* 0x0000000c0e127810 */
/* 0x040fe40007ffe0ff */
/*06b0*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*06d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06e0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*06f0*/ IMAD.IADD R19, R18, 0x1, R19 ; /* 0x0000000112137824 */
/* 0x002fca00078e0213 */
/*0700*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0710*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0720*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e640000004800 */
/*0730*/ IADD3 R17, R18, 0x1, R17 ; /* 0x0000000112117810 */
/* 0x002fca0007ffe011 */
/*0740*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0770*/ IADD3 R21, R18, 0x2, R21 ; /* 0x0000000212157810 */
/* 0x002fca0007ffe015 */
/*0780*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0790*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07a0*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*07b0*/ IADD3 R23, R18, 0x3, R23 ; /* 0x0000000312177810 */
/* 0x002fca0007ffe017 */
/*07c0*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x0003e80000004800 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07e0*/ @P3 BRA 0x380 ; /* 0xfffffb9000003947 */
/* 0x002fea000383ffff */
/*07f0*/ ISETP.GT.AND P3, PT, R16, 0x4, PT ; /* 0x000000041000780c */
/* 0x000fda0003f64270 */
/*0800*/ @!P3 BRA 0xa50 ; /* 0x000002400000b947 */
/* 0x000fea0003800000 */
/*0810*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x000e620000004800 */
/*0820*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0830*/ IADD3 R16, R16, -0x8, RZ ; /* 0xfffffff810107810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD.IADD R17, R14, 0x1, R17 ; /* 0x000000010e117824 */
/* 0x002fca00078e0211 */
/*0850*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0003e80000004800 */
/*0860*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0870*/ IADD3 R17, R14, 0x4, RZ ; /* 0x000000040e117810 */
/* 0x002fca0007ffe0ff */
/*0880*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0890*/ IADD3 R19, R14, 0x1, R19 ; /* 0x000000010e137810 */
/* 0x002fca0007ffe013 */
/*08a0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*08b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08c0*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*08d0*/ IADD3 R21, R14, 0x2, R21 ; /* 0x000000020e157810 */
/* 0x002fca0007ffe015 */
/*08e0*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*08f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0900*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0910*/ IADD3 R23, R14, 0x3, R23 ; /* 0x000000030e177810 */
/* 0x002fc40007ffe017 */
/*0920*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fc60007ffe0ff */
/*0930*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0960*/ IMAD.IADD R19, R17, 0x1, R18 ; /* 0x0000000111137824 */
/* 0x002fca00078e0212 */
/*0970*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0990*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*09a0*/ IADD3 R21, R17, 0x1, R18 ; /* 0x0000000111157810 */
/* 0x002fca0007ffe012 */
/*09b0*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*09c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09d0*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*09e0*/ IADD3 R23, R17, 0x2, R18 ; /* 0x0000000211177810 */
/* 0x002fca0007ffe012 */
/*09f0*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x000fe80000004800 */
/*0a00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a10*/ LDS R18, [R0.X4] ; /* 0x0000000000127984 */
/* 0x000e640000004800 */
/*0a20*/ IADD3 R17, R17, 0x3, R18 ; /* 0x0000000311117810 */
/* 0x002fca0007ffe012 */
/*0a30*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x0003e80000004800 */
/*0a40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a50*/ ISETP.NE.OR P0, PT, R16, RZ, P0 ; /* 0x000000ff1000720c */
/* 0x000fda0000705670 */
/*0a60*/ @!P0 BRA 0xbb0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0a70*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x002e620000004800 */
/*0a80*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f05270 */
/*0aa0*/ IMAD.IADD R17, R17, 0x1, R14 ; /* 0x0000000111117824 */
/* 0x002fca00078e020e */
/*0ab0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0ac0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ad0*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0ae0*/ IADD3 R19, R14, 0x1, R19 ; /* 0x000000010e137810 */
/* 0x002fca0007ffe013 */
/*0af0*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x000fe80000004800 */
/*0b00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b10*/ LDS R21, [R0.X4] ; /* 0x0000000000157984 */
/* 0x000e640000004800 */
/*0b20*/ IADD3 R21, R14, 0x2, R21 ; /* 0x000000020e157810 */
/* 0x002fca0007ffe015 */
/*0b30*/ STS [R0.X4], R21 ; /* 0x0000001500007388 */
/* 0x000fe80000004800 */
/*0b40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b50*/ LDS R23, [R0.X4] ; /* 0x0000000000177984 */
/* 0x000e640000004800 */
/*0b60*/ IADD3 R23, R14, 0x3, R23 ; /* 0x000000030e177810 */
/* 0x002fc40007ffe017 */
/*0b70*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fc60007ffe0ff */
/*0b80*/ STS [R0.X4], R23 ; /* 0x0000001700007388 */
/* 0x0003e80000004800 */
/*0b90*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ba0*/ @P0 BRA 0xa70 ; /* 0xfffffec000000947 */
/* 0x003fea000383ffff */
/*0bb0*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fda0003f05270 */
/*0bc0*/ @!P0 BRA 0xc50 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0bd0*/ LDS R17, [R0.X4] ; /* 0x0000000000117984 */
/* 0x002e640000004800 */
/*0be0*/ IMAD.IADD R17, R17, 0x1, R14 ; /* 0x0000000111117824 */
/* 0x002fca00078e020e */
/*0bf0*/ STS [R0.X4], R17 ; /* 0x0000001100007388 */
/* 0x000fe80000004800 */
/*0c00*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c10*/ LDS R19, [R0.X4] ; /* 0x0000000000137984 */
/* 0x000e640000004800 */
/*0c20*/ IADD3 R19, R19, 0x1, R14 ; /* 0x0000000113137810 */
/* 0x002fca0007ffe00e */
/*0c30*/ STS [R0.X4], R19 ; /* 0x0000001300007388 */
/* 0x0003e80000004800 */
/*0c40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c50*/ IMAD.MOV.U32 R17, RZ, RZ, 0x3b9aca00 ; /* 0x3b9aca00ff117424 */
/* 0x002fca00078e00ff */
/*0c60*/ ATOMG.E.DEC.STRONG.GPU PT, R16, [R6.64], R17 ; /* 0x00000011061079a8 */
/* 0x000362000a1ee1c4 */
/*0c70*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*0c80*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0c90*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0ca0*/ ATOMG.E.DEC.STRONG.GPU PT, R14, [R8.64], R17 ; /* 0x00000011080e79a8 */
/* 0x000562000a1ee1c4 */
/*0cb0*/ MEMBAR.SC.GPU ; /* 0x0000000000007992 */
/* 0x000fec0000002000 */
/*0cc0*/ ERRBAR; /* 0x00000000000079ab */
/* 0x000fc00000000000 */
/*0cd0*/ ISETP.GT.U32.AND P0, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x020fe20003f04070 */
/*0ce0*/ CCTL.IVALL ; /* 0x00000000ff00798f */
/* 0x000fca0002000000 */
/*0cf0*/ ISETP.GT.U32.AND P3, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fce0003f64070 */
/*0d00*/ @!P0 STG.E [R2.64], R15 ; /* 0x0000000f02008986 */
/* 0x0007ec000c101904 */
/*0d10*/ @!P3 STG.E [R4.64], R15 ; /* 0x0000000f0400b986 */
/* 0x0007e2000c101904 */
/*0d20*/ @!P1 BRA 0x270 ; /* 0xfffff54000009947 */
/* 0x000fea000383ffff */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17refCounter_kernelPjS_S_S_jjjjj
.globl _Z17refCounter_kernelPjS_S_S_jjjjj
.p2align 8
.type _Z17refCounter_kernelPjS_S_S_jjjjj,@function
_Z17refCounter_kernelPjS_S_S_jjjjj:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x20
s_mov_b64 s[2:3], src_shared_base
s_add_u32 s2, s0, 56
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v3, 0x4f7ffffe, v1 :: v_dual_lshlrev_b32 v2, 2, v0
v_cmp_ne_u32_e32 vcc_lo, -1, v2
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_3)
v_cvt_u32_f32_e32 v3, v3
v_cndmask_b32_e32 v1, 0, v2, vcc_lo
v_cndmask_b32_e64 v2, 0, s3, vcc_lo
s_addc_u32 s3, s1, 0
s_cmp_eq_u32 s4, 0
v_readfirstlane_b32 s6, v3
flat_store_b32 v[1:2], v4 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_10
s_load_b32 s2, s[2:3], 0xc
s_sub_i32 s3, 0, s5
s_load_b32 s7, s[0:1], 0x30
s_mul_i32 s3, s3, s6
s_load_b256 s[16:23], s[0:1], 0x0
s_mul_hi_u32 s3, s6, s3
v_mov_b32_e32 v11, 0x3b9aca00
s_add_i32 s6, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s15, s6
s_mul_i32 s3, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s3, s15, s3
s_sub_i32 s6, s3, s5
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_ge_u32 s3, s5
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
s_cselect_b32 s3, s6, s3
s_mov_b32 s2, 0
s_sub_i32 s0, s3, s5
s_cmp_ge_u32 s3, s5
s_cselect_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, s0, s7, v[0:1]
v_mov_b32_e32 v4, 0
s_lshl_b32 s0, s4, 1
v_mov_b32_e32 v0, 1
s_cmp_lg_u32 s0, 0
v_mov_b32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_cselect_b32 s1, -1, 0
v_lshlrev_b64 v[9:10], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s16, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s17, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s18, v7
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s20, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s21, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s22, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s23, v10, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, s4
s_cbranch_scc1 .LBB0_10
.LBB0_3:
global_atomic_add_u32 v[3:4], v0, off
global_atomic_add_u32 v[5:6], v0, off
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_6
s_mov_b32 s3, 0
.LBB0_5:
flat_load_b32 v12, v[1:2] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v12, s3, v12
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, s3
flat_store_b32 v[1:2], v12 dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_6:
global_atomic_dec_u32 v13, v[3:4], v11, off glc
s_waitcnt vmcnt(0)
s_waitcnt_vscnt null, 0x0
buffer_gl1_inv
buffer_gl0_inv
global_atomic_dec_u32 v12, v[5:6], v11, off glc
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v13
s_cbranch_execz .LBB0_8
global_store_b32 v[7:8], v0, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e32 2, v12
s_cbranch_execz .LBB0_2
global_store_b32 v[9:10], v0, off
s_branch .LBB0_2
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17refCounter_kernelPjS_S_S_jjjjj
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17refCounter_kernelPjS_S_S_jjjjj, .Lfunc_end0-_Z17refCounter_kernelPjS_S_S_jjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17refCounter_kernelPjS_S_S_jjjjj
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z17refCounter_kernelPjS_S_S_jjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a1184_00000000-6_refCounter_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj
.type _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj, @function
_Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17refCounter_kernelPjS_S_S_jjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj, .-_Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj
.globl _Z17refCounter_kernelPjS_S_S_jjjjj
.type _Z17refCounter_kernelPjS_S_S_jjjjj, @function
_Z17refCounter_kernelPjS_S_S_jjjjj:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z17refCounter_kernelPjS_S_S_jjjjjPjS_S_S_jjjjj
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17refCounter_kernelPjS_S_S_jjjjj, .-_Z17refCounter_kernelPjS_S_S_jjjjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17refCounter_kernelPjS_S_S_jjjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17refCounter_kernelPjS_S_S_jjjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "refCounter_kernel.hip"
.globl _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj # -- Begin function _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.p2align 4, 0x90
.type _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj,@function
_Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj: # @_Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17refCounter_kernelPjS_S_S_jjjjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj, .Lfunc_end0-_Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17refCounter_kernelPjS_S_S_jjjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17refCounter_kernelPjS_S_S_jjjjj,@object # @_Z17refCounter_kernelPjS_S_S_jjjjj
.section .rodata,"a",@progbits
.globl _Z17refCounter_kernelPjS_S_S_jjjjj
.p2align 3, 0x0
_Z17refCounter_kernelPjS_S_S_jjjjj:
.quad _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.size _Z17refCounter_kernelPjS_S_S_jjjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17refCounter_kernelPjS_S_S_jjjjj"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__refCounter_kernelPjS_S_S_jjjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17refCounter_kernelPjS_S_S_jjjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research //
// //
//Copyright (c) <2012>, Anthony Morse //
//All rights reserved. //
// //
//Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: //
// //
// - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. //
// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR //
//A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT //
//LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR //
//TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
// //
//The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted //
//as representing official policies,either expressed or implied, of the FreeBSD Project. //
//##############################################################################################################################################################################################################//
//this is just to stop compiler warning about this file being empty, you can remove this function once you have add any kernels
void esnEmptyKernel(){}; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research //
// //
//Copyright (c) <2012>, Anthony Morse //
//All rights reserved. //
// //
//Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: //
// //
// - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. //
// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR //
//A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT //
//LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR //
//TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
// //
//The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted //
//as representing official policies,either expressed or implied, of the FreeBSD Project. //
//##############################################################################################################################################################################################################//
//this is just to stop compiler warning about this file being empty, you can remove this function once you have add any kernels
void esnEmptyKernel(){}; | .file "tmpxft_0010a923_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14esnEmptyKernelv
.type _Z14esnEmptyKernelv, @function
_Z14esnEmptyKernelv:
.LFB2027:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2027:
.size _Z14esnEmptyKernelv, .-_Z14esnEmptyKernelv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research //
// //
//Copyright (c) <2012>, Anthony Morse //
//All rights reserved. //
// //
//Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: //
// //
// - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. //
// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR //
//A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT //
//LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR //
//TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
// //
//The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted //
//as representing official policies,either expressed or implied, of the FreeBSD Project. //
//##############################################################################################################################################################################################################//
//this is just to stop compiler warning about this file being empty, you can remove this function once you have add any kernels
void esnEmptyKernel(){}; | #include <hip/hip_runtime.h>
//##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research //
// //
//Copyright (c) <2012>, Anthony Morse //
//All rights reserved. //
// //
//Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: //
// //
// - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. //
// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR //
//A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT //
//LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR //
//TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
// //
//The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted //
//as representing official policies,either expressed or implied, of the FreeBSD Project. //
//##############################################################################################################################################################################################################//
//this is just to stop compiler warning about this file being empty, you can remove this function once you have add any kernels
void esnEmptyKernel(){}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research //
// //
//Copyright (c) <2012>, Anthony Morse //
//All rights reserved. //
// //
//Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: //
// //
// - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. //
// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR //
//A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT //
//LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR //
//TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
// //
//The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted //
//as representing official policies,either expressed or implied, of the FreeBSD Project. //
//##############################################################################################################################################################################################################//
//this is just to stop compiler warning about this file being empty, you can remove this function once you have add any kernels
void esnEmptyKernel(){}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//##############################################################################################################################################################################################################//
//Aquila - An Open-Source GPU-Accelerated Toolkit for Cognitive and Neuro-Robotics Research //
// //
//Copyright (c) <2012>, Anthony Morse //
//All rights reserved. //
// //
//Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: //
// //
// - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. //
// - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. //
// //
//THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR //
//A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT //
//LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR //
//TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
// //
//The views and conclusions contained in the software and documentation are those of the authors and should not be interpreted //
//as representing official policies,either expressed or implied, of the FreeBSD Project. //
//##############################################################################################################################################################################################################//
//this is just to stop compiler warning about this file being empty, you can remove this function once you have add any kernels
void esnEmptyKernel(){}; | .text
.file "kernels.hip"
.globl _Z14esnEmptyKernelv # -- Begin function _Z14esnEmptyKernelv
.p2align 4, 0x90
.type _Z14esnEmptyKernelv,@function
_Z14esnEmptyKernelv: # @_Z14esnEmptyKernelv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z14esnEmptyKernelv, .Lfunc_end0-_Z14esnEmptyKernelv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010a923_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14esnEmptyKernelv
.type _Z14esnEmptyKernelv, @function
_Z14esnEmptyKernelv:
.LFB2027:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2027:
.size _Z14esnEmptyKernelv, .-_Z14esnEmptyKernelv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z14esnEmptyKernelv # -- Begin function _Z14esnEmptyKernelv
.p2align 4, 0x90
.type _Z14esnEmptyKernelv,@function
_Z14esnEmptyKernelv: # @_Z14esnEmptyKernelv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z14esnEmptyKernelv, .Lfunc_end0-_Z14esnEmptyKernelv
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
y[i] = x[i] + y[i];
}
void testTrush(){
// H has storage for 4 integers
thrust::host_vector<float*> H(2);
// initialize individual elements
// print contents of H
for(int i = 0; i < H.size(); i++){
H[i] = (float*)malloc(2*sizeof(float));
H[i][0] = 0;H[i][1] = 1;
std::cout << "H[" << i << "] = " << H[i][0] <<"--"<<H[i][1]<< std::endl;
}
// float test[3];
// *test = {.0f, .0f, .0f};
// for(int i=0;i<3;i++)
// cout<<test[i]<<endl;
//
// // resize H
// H.resize(2);
//
// std::cout << "H now has size " << H.size() << std::endl;
//
// // Copy host_vector H to device_vector D
// thrust::device_vector<int> D = H;
//
// // elements of D can be modified
// D[0] = 99;
// D[1] = 88;
//
// // print contents of D
// for(int i = 0; i < D.size(); i++)
// std::cout << "D[" << i << "] = " << D[i] << std::endl;
}
int main()
{
testTrush();
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numOfBlocks = (N+blockSize-1)/blockSize;
// Run kernel on 1M elements on the GPU
add<<<numOfBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
y[i] = x[i] + y[i];
}
void testTrush(){
// H has storage for 4 integers
thrust::host_vector<float*> H(2);
// initialize individual elements
// print contents of H
for(int i = 0; i < H.size(); i++){
H[i] = (float*)malloc(2*sizeof(float));
H[i][0] = 0;H[i][1] = 1;
std::cout << "H[" << i << "] = " << H[i][0] <<"--"<<H[i][1]<< std::endl;
}
// float test[3];
// *test = {.0f, .0f, .0f};
// for(int i=0;i<3;i++)
// cout<<test[i]<<endl;
//
// // resize H
// H.resize(2);
//
// std::cout << "H now has size " << H.size() << std::endl;
//
// // Copy host_vector H to device_vector D
// thrust::device_vector<int> D = H;
//
// // elements of D can be modified
// D[0] = 99;
// D[1] = 88;
//
// // print contents of D
// for(int i = 0; i < D.size(); i++)
// std::cout << "D[" << i << "] = " << D[i] << std::endl;
}
int main()
{
testTrush();
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N*sizeof(float));
cudaMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numOfBlocks = (N+blockSize-1)/blockSize;
// Run kernel on 1M elements on the GPU
add<<<numOfBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
y[i] = x[i] + y[i];
}
void testTrush(){
// H has storage for 4 integers
thrust::host_vector<float*> H(2);
// initialize individual elements
// print contents of H
for(int i = 0; i < H.size(); i++){
H[i] = (float*)malloc(2*sizeof(float));
H[i][0] = 0;H[i][1] = 1;
std::cout << "H[" << i << "] = " << H[i][0] <<"--"<<H[i][1]<< std::endl;
}
// float test[3];
// *test = {.0f, .0f, .0f};
// for(int i=0;i<3;i++)
// cout<<test[i]<<endl;
//
// // resize H
// H.resize(2);
//
// std::cout << "H now has size " << H.size() << std::endl;
//
// // Copy host_vector H to device_vector D
// thrust::device_vector<int> D = H;
//
// // elements of D can be modified
// D[0] = 99;
// D[1] = 88;
//
// // print contents of D
// for(int i = 0; i < D.size(); i++)
// std::cout << "D[" << i << "] = " << D[i] << std::endl;
}
int main()
{
testTrush();
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numOfBlocks = (N+blockSize-1)/blockSize;
// Run kernel on 1M elements on the GPU
add<<<numOfBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
y[i] = x[i] + y[i];
}
void testTrush(){
// H has storage for 4 integers
thrust::host_vector<float*> H(2);
// initialize individual elements
// print contents of H
for(int i = 0; i < H.size(); i++){
H[i] = (float*)malloc(2*sizeof(float));
H[i][0] = 0;H[i][1] = 1;
std::cout << "H[" << i << "] = " << H[i][0] <<"--"<<H[i][1]<< std::endl;
}
// float test[3];
// *test = {.0f, .0f, .0f};
// for(int i=0;i<3;i++)
// cout<<test[i]<<endl;
//
// // resize H
// H.resize(2);
//
// std::cout << "H now has size " << H.size() << std::endl;
//
// // Copy host_vector H to device_vector D
// thrust::device_vector<int> D = H;
//
// // elements of D can be modified
// D[0] = 99;
// D[1] = 88;
//
// // print contents of D
// for(int i = 0; i < D.size(); i++)
// std::cout << "D[" << i << "] = " << D[i] << std::endl;
}
int main()
{
testTrush();
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numOfBlocks = (N+blockSize-1)/blockSize;
// Run kernel on 1M elements on the GPU
add<<<numOfBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
// Kernel function to add the elements of two arrays
__global__
void add(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
y[i] = x[i] + y[i];
}
void testTrush(){
// H has storage for 4 integers
thrust::host_vector<float*> H(2);
// initialize individual elements
// print contents of H
for(int i = 0; i < H.size(); i++){
H[i] = (float*)malloc(2*sizeof(float));
H[i][0] = 0;H[i][1] = 1;
std::cout << "H[" << i << "] = " << H[i][0] <<"--"<<H[i][1]<< std::endl;
}
// float test[3];
// *test = {.0f, .0f, .0f};
// for(int i=0;i<3;i++)
// cout<<test[i]<<endl;
//
// // resize H
// H.resize(2);
//
// std::cout << "H now has size " << H.size() << std::endl;
//
// // Copy host_vector H to device_vector D
// thrust::device_vector<int> D = H;
//
// // elements of D can be modified
// D[0] = 99;
// D[1] = 88;
//
// // print contents of D
// for(int i = 0; i < D.size(); i++)
// std::cout << "D[" << i << "] = " << D[i] << std::endl;
}
int main()
{
testTrush();
int N = 1<<20;
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N*sizeof(float));
hipMallocManaged(&y, N*sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
int blockSize = 256;
int numOfBlocks = (N+blockSize-1)/blockSize;
// Run kernel on 1M elements on the GPU
add<<<numOfBlocks, blockSize>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i]-3.0f));
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "naive.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.globl _Z9testTrushv # -- Begin function _Z9testTrushv
.p2align 4, 0x90
.type _Z9testTrushv,@function
_Z9testTrushv: # @_Z9testTrushv
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZN6thrust11host_vectorIPfSaIS1_EEC2Em.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $16, %edi
callq _Znwm
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
xorl %r14d, %r14d
movabsq $4575657221408423936, %r13 # imm = 0x3F80000000000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $8, %edi
callq malloc
movq %rax, (%rbx,%r14,8)
movq %r13, (%rax)
.Ltmp0:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.2: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_1 Depth=1
.Ltmp2:
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp3:
# %bb.3: # in Loop: Header=BB1_1 Depth=1
.Ltmp4:
movq %rax, %r15
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp5:
# %bb.4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit12
# in Loop: Header=BB1_1 Depth=1
movq (%rbx,%r14,8), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp6:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp7:
# %bb.5: # %_ZNSolsEf.exit
# in Loop: Header=BB1_1 Depth=1
.Ltmp8:
movq %rax, %r15
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp9:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit13
# in Loop: Header=BB1_1 Depth=1
movq (%rbx,%r14,8), %rax
movss 4(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp10:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp11:
# %bb.7: # %_ZNSolsEf.exit14
# in Loop: Header=BB1_1 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_8
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%r12)
je .LBB1_15
# %bb.14: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_1 Depth=1
.Ltmp12:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp13:
# %bb.16: # %.noexc16
# in Loop: Header=BB1_1 Depth=1
movq (%r12), %rax
.Ltmp14:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp15:
.LBB1_17: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB1_1 Depth=1
.Ltmp16:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp17:
# %bb.18: # %.noexc18
# in Loop: Header=BB1_1 Depth=1
.Ltmp18:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp19:
# %bb.19: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_1 Depth=1
incq %r14
cmpq $1, %r14
je .LBB1_1
# %bb.20: # %_ZN6thrust6detail11vector_baseIPfSaIS2_EED2Ev.exit
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _ZdlPv # TAILCALL
.LBB1_8:
.cfi_def_cfa_offset 48
.Ltmp21:
callq _ZSt16__throw_bad_castv
.Ltmp22:
# %bb.12: # %.noexc
.LBB1_10: # %_ZN6thrust6detail11vector_baseIPfSaIS2_EED2Ev.exit11.loopexit.split-lp
.Ltmp23:
jmp .LBB1_11
.LBB1_9: # %_ZN6thrust6detail11vector_baseIPfSaIS2_EED2Ev.exit11.loopexit
.Ltmp20:
.LBB1_11: # %_ZN6thrust6detail11vector_baseIPfSaIS2_EED2Ev.exit11
movq %rax, %r14
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z9testTrushv, .Lfunc_end1-_Z9testTrushv
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp19-.Ltmp0 # Call between .Ltmp0 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end1-.Ltmp22 # Call between .Ltmp22 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq _Z9testTrushv
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB2_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI2_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB2_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB2_10
.LBB2_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "H["
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "] = "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "--"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Max error: "
.size .L.str.3, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a02 */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fe20000000f00 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x0000a2000c1e1900 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x002fd400000001ff */
/*0340*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R6, R3, R6, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fe200078e0206 */
/*0360*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0370*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0390*/ FADD R17, R2, R9 ; /* 0x0000000902117221 */
/* 0x004fe40000000000 */
/*03a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*03f0*/ FADD R19, R2, R13 ; /* 0x0000000d02137221 */
/* 0x004fe40000000000 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0208 */
/*0410*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x001fc800078e020e */
/*0450*/ FADD R21, R2, R5 ; /* 0x0000000502157221 */
/* 0x004fe40000000000 */
/*0460*/ IMAD.WIDE R4, R0, 0x4, R12 ; /* 0x0000000400047825 */
/* 0x000fc600078e020c */
/*0470*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*04e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0003ee000c101904 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define BLOCK_SIZE 1024
#define N 1024
#define MAXELEMS 200000
#define FREQBANDWIDTH 50
#define MAXSONGS 10
__device__ char nthdigit(int x, int n);
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e);
__device__ void four1(float* data, int nn);
__global__ void calc_scores(int * hash_songs, int * songscores_d)
{
__shared__ int data[MAXSONGS+1];
if (threadIdx.x < MAXSONGS+1) data[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x*blockDim.x;
int hashsongs_base_index = i*(MAXSONGS+1);
int temp;
if(i<MAXELEMS && hash_songs[hashsongs_base_index]>0)
{
int n;
for(n = 1; n <= MAXSONGS; n++)
{
temp = (hash_songs[hashsongs_base_index+n]>=hash_songs[hashsongs_base_index]) ? hash_songs[hashsongs_base_index] : hash_songs[hashsongs_base_index+n];
atomicAdd(&(data[n]),temp);
}
}
__syncthreads();
if (threadIdx.x < MAXSONGS+1) atomicAdd(&(songscores_d[threadIdx.x]),data[threadIdx.x]);
}
__device__ char nthdigit(int x, int n)
{
int powersof10[] = {1, 10, 100, 1000};
return ((x / powersof10[n]) % 10) + '0';
}
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e)
{
int i = 0;
if(buffer == NULL) return 0;
//Process first int
if(a >= 10) buffer[i++] = nthdigit(a,1);
else buffer[i++] = nthdigit(a,0);
//Second int
if(b >= 100) buffer[i++] = nthdigit(b,0);
else if(b >= 10) buffer[i++] = nthdigit(b,1);
else buffer[i++] = nthdigit(b,2);
//Third int
if(c >= 100) buffer[i++] = nthdigit(c,0);
else if(c >= 10) buffer[i++] = nthdigit(c,1);
else buffer[i++] = nthdigit(c,2);
//Fourth int
if(d >= 100) buffer[i++] = nthdigit(d,0);
else if(d >= 10) buffer[i++] = nthdigit(d,1);
else buffer[i++] = nthdigit(d,2);
//Fifth int
if(e >= 100) buffer[i++] = nthdigit(e,0);
else if(e >= 10) buffer[i++] = nthdigit(e,1);
else buffer[i++] = nthdigit(e,2);
return i;
}
__global__ void parallelhash(float* in, int n, int* hash_table, int song_id)
{
int i, k;
float freq1, freq2, freq3, freq4, freq5;
float tempfreq, magnitude;
int pt1,pt2,pt3,pt4, pt5, key;
i = threadIdx.x + blockIdx.x*blockDim.x; //My chunk
if(i < n){ //if my chunk ID < total number of chunks we may continue
//Point Z to the right chunk location in the song
float* Z = &in[N*i];
four1(Z,N);
freq1 = freq2 = freq3 = freq4 = freq5 = 0;
pt1 = pt2 = pt3 = pt4 = pt5 = 0;
//Filter Frequency Bands
for(k=FREQBANDWIDTH; k<FREQBANDWIDTH*6; k++){
tempfreq = abs(Z[2*k]);
magnitude = log10(tempfreq+1);
if(k>=FREQBANDWIDTH && k<FREQBANDWIDTH*2 && magnitude>freq1) {freq1 = magnitude; pt1=k;}
else if(k>=FREQBANDWIDTH*2 && k<FREQBANDWIDTH*3 && magnitude>freq2) {freq2 = magnitude; pt2=k;}
else if(k>=FREQBANDWIDTH*3 && k<FREQBANDWIDTH*4 && magnitude>freq3) {freq3 = magnitude; pt3=k;}
else if(k>=FREQBANDWIDTH*4 && k<FREQBANDWIDTH*5 && magnitude>freq4) {freq4 = magnitude; pt4=k;}
else if(k>=FREQBANDWIDTH*5 && k<FREQBANDWIDTH*6 && magnitude>freq5) {freq5 = magnitude; pt5=k;}
}
//Hash the result inline
unsigned long long int hashresult = 0;
char buffer [15];
int k = 0, j = 0;
for(k = 0; k < 15; k ++) buffer[0] = 0;
j = generate_hash_string (buffer, pt1,pt2,pt3,pt4,pt5);
unsigned long long int hash = 5381;
k = 0;
for(k = 0; k < j; k ++)
hash = ((hash << 5) + hash) + buffer[k]; /* hash * 33 + c */
hashresult = hash % MAXELEMS;
//Write result to hash table
key = (int) hashresult;
atomicAdd(&(hash_table[(key*(MAXSONGS+1))+(song_id)]),1);
}
}
__device__ void four1(float* data, int nn)
{
int n, mmax, m, j, istep, i;
float wtemp, wr, wpr, wpi, wi, theta;
float tempr, tempi;
// reverse-binary reindexing
n = nn<<1;
j=1;
for (i=1; i<n; i+=2)
{
if (j>i) //data swap should be parallelizeable
{
float temp = data[j-1];
data[j-1] = data[i-1];
data[i-1] = temp;
temp = data[j];
data[j] = data[i];
data[i] = temp;
}
m = nn;
while (m>=2 && j>m)
{
j -= m;
m >>= 1;
}
j += m;
}
// here begins the Danielson-Lanczos section
mmax=2;
while (n>mmax) {
istep = mmax<<1;
theta = -(2*M_PI/mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1; m < mmax; m += 2) {
for (i=m; i <= n; i += istep) {
j=i+mmax;
tempr = wr*data[j-1] - wi*data[j];
tempi = wr * data[j] + wi*data[j-1];
data[j-1] = data[i-1] - tempr;
data[j] = data[i] - tempi;
data[i-1] += tempr;
data[i] += tempi;
}
wtemp=wr;
wr += wr*wpr - wi*wpi;
wi += wi*wpr + wtemp*wpi;
}
mmax=istep;
}
} | .file "tmpxft_001631ae_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8nthdigitii
.type _Z8nthdigitii, @function
_Z8nthdigitii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8nthdigitii, .-_Z8nthdigitii
.globl _Z20generate_hash_stringPciiiii
.type _Z20generate_hash_stringPciiiii, @function
_Z20generate_hash_stringPciiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z20generate_hash_stringPciiiii, .-_Z20generate_hash_stringPciiiii
.globl _Z5four1Pfi
.type _Z5four1Pfi, @function
_Z5four1Pfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5four1Pfi, .-_Z5four1Pfi
.globl _Z33__device_stub__Z11calc_scoresPiS_PiS_
.type _Z33__device_stub__Z11calc_scoresPiS_PiS_, @function
_Z33__device_stub__Z11calc_scoresPiS_PiS_:
.LFB2054:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11calc_scoresPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z33__device_stub__Z11calc_scoresPiS_PiS_, .-_Z33__device_stub__Z11calc_scoresPiS_PiS_
.globl _Z11calc_scoresPiS_
.type _Z11calc_scoresPiS_, @function
_Z11calc_scoresPiS_:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11calc_scoresPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z11calc_scoresPiS_, .-_Z11calc_scoresPiS_
.globl _Z36__device_stub__Z12parallelhashPfiPiiPfiPii
.type _Z36__device_stub__Z12parallelhashPfiPiiPfiPii, @function
_Z36__device_stub__Z12parallelhashPfiPiiPfiPii:
.LFB2056:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12parallelhashPfiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z36__device_stub__Z12parallelhashPfiPiiPfiPii, .-_Z36__device_stub__Z12parallelhashPfiPiiPfiPii
.globl _Z12parallelhashPfiPii
.type _Z12parallelhashPfiPii, @function
_Z12parallelhashPfiPii:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12parallelhashPfiPiiPfiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12parallelhashPfiPii, .-_Z12parallelhashPfiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12parallelhashPfiPii"
.LC1:
.string "_Z11calc_scoresPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12parallelhashPfiPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calc_scoresPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define BLOCK_SIZE 1024
#define N 1024
#define MAXELEMS 200000
#define FREQBANDWIDTH 50
#define MAXSONGS 10
__device__ char nthdigit(int x, int n);
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e);
__device__ void four1(float* data, int nn);
__global__ void calc_scores(int * hash_songs, int * songscores_d)
{
__shared__ int data[MAXSONGS+1];
if (threadIdx.x < MAXSONGS+1) data[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x*blockDim.x;
int hashsongs_base_index = i*(MAXSONGS+1);
int temp;
if(i<MAXELEMS && hash_songs[hashsongs_base_index]>0)
{
int n;
for(n = 1; n <= MAXSONGS; n++)
{
temp = (hash_songs[hashsongs_base_index+n]>=hash_songs[hashsongs_base_index]) ? hash_songs[hashsongs_base_index] : hash_songs[hashsongs_base_index+n];
atomicAdd(&(data[n]),temp);
}
}
__syncthreads();
if (threadIdx.x < MAXSONGS+1) atomicAdd(&(songscores_d[threadIdx.x]),data[threadIdx.x]);
}
__device__ char nthdigit(int x, int n)
{
int powersof10[] = {1, 10, 100, 1000};
return ((x / powersof10[n]) % 10) + '0';
}
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e)
{
int i = 0;
if(buffer == NULL) return 0;
//Process first int
if(a >= 10) buffer[i++] = nthdigit(a,1);
else buffer[i++] = nthdigit(a,0);
//Second int
if(b >= 100) buffer[i++] = nthdigit(b,0);
else if(b >= 10) buffer[i++] = nthdigit(b,1);
else buffer[i++] = nthdigit(b,2);
//Third int
if(c >= 100) buffer[i++] = nthdigit(c,0);
else if(c >= 10) buffer[i++] = nthdigit(c,1);
else buffer[i++] = nthdigit(c,2);
//Fourth int
if(d >= 100) buffer[i++] = nthdigit(d,0);
else if(d >= 10) buffer[i++] = nthdigit(d,1);
else buffer[i++] = nthdigit(d,2);
//Fifth int
if(e >= 100) buffer[i++] = nthdigit(e,0);
else if(e >= 10) buffer[i++] = nthdigit(e,1);
else buffer[i++] = nthdigit(e,2);
return i;
}
__global__ void parallelhash(float* in, int n, int* hash_table, int song_id)
{
int i, k;
float freq1, freq2, freq3, freq4, freq5;
float tempfreq, magnitude;
int pt1,pt2,pt3,pt4, pt5, key;
i = threadIdx.x + blockIdx.x*blockDim.x; //My chunk
if(i < n){ //if my chunk ID < total number of chunks we may continue
//Point Z to the right chunk location in the song
float* Z = &in[N*i];
four1(Z,N);
freq1 = freq2 = freq3 = freq4 = freq5 = 0;
pt1 = pt2 = pt3 = pt4 = pt5 = 0;
//Filter Frequency Bands
for(k=FREQBANDWIDTH; k<FREQBANDWIDTH*6; k++){
tempfreq = abs(Z[2*k]);
magnitude = log10(tempfreq+1);
if(k>=FREQBANDWIDTH && k<FREQBANDWIDTH*2 && magnitude>freq1) {freq1 = magnitude; pt1=k;}
else if(k>=FREQBANDWIDTH*2 && k<FREQBANDWIDTH*3 && magnitude>freq2) {freq2 = magnitude; pt2=k;}
else if(k>=FREQBANDWIDTH*3 && k<FREQBANDWIDTH*4 && magnitude>freq3) {freq3 = magnitude; pt3=k;}
else if(k>=FREQBANDWIDTH*4 && k<FREQBANDWIDTH*5 && magnitude>freq4) {freq4 = magnitude; pt4=k;}
else if(k>=FREQBANDWIDTH*5 && k<FREQBANDWIDTH*6 && magnitude>freq5) {freq5 = magnitude; pt5=k;}
}
//Hash the result inline
unsigned long long int hashresult = 0;
char buffer [15];
int k = 0, j = 0;
for(k = 0; k < 15; k ++) buffer[0] = 0;
j = generate_hash_string (buffer, pt1,pt2,pt3,pt4,pt5);
unsigned long long int hash = 5381;
k = 0;
for(k = 0; k < j; k ++)
hash = ((hash << 5) + hash) + buffer[k]; /* hash * 33 + c */
hashresult = hash % MAXELEMS;
//Write result to hash table
key = (int) hashresult;
atomicAdd(&(hash_table[(key*(MAXSONGS+1))+(song_id)]),1);
}
}
__device__ void four1(float* data, int nn)
{
int n, mmax, m, j, istep, i;
float wtemp, wr, wpr, wpi, wi, theta;
float tempr, tempi;
// reverse-binary reindexing
n = nn<<1;
j=1;
for (i=1; i<n; i+=2)
{
if (j>i) //data swap should be parallelizeable
{
float temp = data[j-1];
data[j-1] = data[i-1];
data[i-1] = temp;
temp = data[j];
data[j] = data[i];
data[i] = temp;
}
m = nn;
while (m>=2 && j>m)
{
j -= m;
m >>= 1;
}
j += m;
}
// here begins the Danielson-Lanczos section
mmax=2;
while (n>mmax) {
istep = mmax<<1;
theta = -(2*M_PI/mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1; m < mmax; m += 2) {
for (i=m; i <= n; i += istep) {
j=i+mmax;
tempr = wr*data[j-1] - wi*data[j];
tempi = wr * data[j] + wi*data[j-1];
data[j-1] = data[i-1] - tempr;
data[j] = data[i] - tempi;
data[i-1] += tempr;
data[i] += tempi;
}
wtemp=wr;
wr += wr*wpr - wi*wpi;
wi += wi*wpr + wtemp*wpi;
}
mmax=istep;
}
} | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 1024
#define N 1024
#define MAXELEMS 200000
#define FREQBANDWIDTH 50
#define MAXSONGS 10
__device__ char nthdigit(int x, int n);
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e);
__device__ void four1(float* data, int nn);
__global__ void calc_scores(int * hash_songs, int * songscores_d)
{
__shared__ int data[MAXSONGS+1];
if (threadIdx.x < MAXSONGS+1) data[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x*blockDim.x;
int hashsongs_base_index = i*(MAXSONGS+1);
int temp;
if(i<MAXELEMS && hash_songs[hashsongs_base_index]>0)
{
int n;
for(n = 1; n <= MAXSONGS; n++)
{
temp = (hash_songs[hashsongs_base_index+n]>=hash_songs[hashsongs_base_index]) ? hash_songs[hashsongs_base_index] : hash_songs[hashsongs_base_index+n];
atomicAdd(&(data[n]),temp);
}
}
__syncthreads();
if (threadIdx.x < MAXSONGS+1) atomicAdd(&(songscores_d[threadIdx.x]),data[threadIdx.x]);
}
__device__ char nthdigit(int x, int n)
{
int powersof10[] = {1, 10, 100, 1000};
return ((x / powersof10[n]) % 10) + '0';
}
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e)
{
int i = 0;
if(buffer == NULL) return 0;
//Process first int
if(a >= 10) buffer[i++] = nthdigit(a,1);
else buffer[i++] = nthdigit(a,0);
//Second int
if(b >= 100) buffer[i++] = nthdigit(b,0);
else if(b >= 10) buffer[i++] = nthdigit(b,1);
else buffer[i++] = nthdigit(b,2);
//Third int
if(c >= 100) buffer[i++] = nthdigit(c,0);
else if(c >= 10) buffer[i++] = nthdigit(c,1);
else buffer[i++] = nthdigit(c,2);
//Fourth int
if(d >= 100) buffer[i++] = nthdigit(d,0);
else if(d >= 10) buffer[i++] = nthdigit(d,1);
else buffer[i++] = nthdigit(d,2);
//Fifth int
if(e >= 100) buffer[i++] = nthdigit(e,0);
else if(e >= 10) buffer[i++] = nthdigit(e,1);
else buffer[i++] = nthdigit(e,2);
return i;
}
__global__ void parallelhash(float* in, int n, int* hash_table, int song_id)
{
int i, k;
float freq1, freq2, freq3, freq4, freq5;
float tempfreq, magnitude;
int pt1,pt2,pt3,pt4, pt5, key;
i = threadIdx.x + blockIdx.x*blockDim.x; //My chunk
if(i < n){ //if my chunk ID < total number of chunks we may continue
//Point Z to the right chunk location in the song
float* Z = &in[N*i];
four1(Z,N);
freq1 = freq2 = freq3 = freq4 = freq5 = 0;
pt1 = pt2 = pt3 = pt4 = pt5 = 0;
//Filter Frequency Bands
for(k=FREQBANDWIDTH; k<FREQBANDWIDTH*6; k++){
tempfreq = abs(Z[2*k]);
magnitude = log10(tempfreq+1);
if(k>=FREQBANDWIDTH && k<FREQBANDWIDTH*2 && magnitude>freq1) {freq1 = magnitude; pt1=k;}
else if(k>=FREQBANDWIDTH*2 && k<FREQBANDWIDTH*3 && magnitude>freq2) {freq2 = magnitude; pt2=k;}
else if(k>=FREQBANDWIDTH*3 && k<FREQBANDWIDTH*4 && magnitude>freq3) {freq3 = magnitude; pt3=k;}
else if(k>=FREQBANDWIDTH*4 && k<FREQBANDWIDTH*5 && magnitude>freq4) {freq4 = magnitude; pt4=k;}
else if(k>=FREQBANDWIDTH*5 && k<FREQBANDWIDTH*6 && magnitude>freq5) {freq5 = magnitude; pt5=k;}
}
//Hash the result inline
unsigned long long int hashresult = 0;
char buffer [15];
int k = 0, j = 0;
for(k = 0; k < 15; k ++) buffer[0] = 0;
j = generate_hash_string (buffer, pt1,pt2,pt3,pt4,pt5);
unsigned long long int hash = 5381;
k = 0;
for(k = 0; k < j; k ++)
hash = ((hash << 5) + hash) + buffer[k]; /* hash * 33 + c */
hashresult = hash % MAXELEMS;
//Write result to hash table
key = (int) hashresult;
atomicAdd(&(hash_table[(key*(MAXSONGS+1))+(song_id)]),1);
}
}
__device__ void four1(float* data, int nn)
{
int n, mmax, m, j, istep, i;
float wtemp, wr, wpr, wpi, wi, theta;
float tempr, tempi;
// reverse-binary reindexing
n = nn<<1;
j=1;
for (i=1; i<n; i+=2)
{
if (j>i) //data swap should be parallelizeable
{
float temp = data[j-1];
data[j-1] = data[i-1];
data[i-1] = temp;
temp = data[j];
data[j] = data[i];
data[i] = temp;
}
m = nn;
while (m>=2 && j>m)
{
j -= m;
m >>= 1;
}
j += m;
}
// here begins the Danielson-Lanczos section
mmax=2;
while (n>mmax) {
istep = mmax<<1;
theta = -(2*M_PI/mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1; m < mmax; m += 2) {
for (i=m; i <= n; i += istep) {
j=i+mmax;
tempr = wr*data[j-1] - wi*data[j];
tempi = wr * data[j] + wi*data[j-1];
data[j-1] = data[i-1] - tempr;
data[j] = data[i] - tempi;
data[i-1] += tempr;
data[i] += tempi;
}
wtemp=wr;
wr += wr*wpr - wi*wpi;
wi += wi*wpr + wtemp*wpi;
}
mmax=istep;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define BLOCK_SIZE 1024
#define N 1024
#define MAXELEMS 200000
#define FREQBANDWIDTH 50
#define MAXSONGS 10
__device__ char nthdigit(int x, int n);
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e);
__device__ void four1(float* data, int nn);
__global__ void calc_scores(int * hash_songs, int * songscores_d)
{
__shared__ int data[MAXSONGS+1];
if (threadIdx.x < MAXSONGS+1) data[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x*blockDim.x;
int hashsongs_base_index = i*(MAXSONGS+1);
int temp;
if(i<MAXELEMS && hash_songs[hashsongs_base_index]>0)
{
int n;
for(n = 1; n <= MAXSONGS; n++)
{
temp = (hash_songs[hashsongs_base_index+n]>=hash_songs[hashsongs_base_index]) ? hash_songs[hashsongs_base_index] : hash_songs[hashsongs_base_index+n];
atomicAdd(&(data[n]),temp);
}
}
__syncthreads();
if (threadIdx.x < MAXSONGS+1) atomicAdd(&(songscores_d[threadIdx.x]),data[threadIdx.x]);
}
__device__ char nthdigit(int x, int n)
{
int powersof10[] = {1, 10, 100, 1000};
return ((x / powersof10[n]) % 10) + '0';
}
__device__ int generate_hash_string (char* buffer, int a, int b, int c, int d, int e)
{
int i = 0;
if(buffer == NULL) return 0;
//Process first int
if(a >= 10) buffer[i++] = nthdigit(a,1);
else buffer[i++] = nthdigit(a,0);
//Second int
if(b >= 100) buffer[i++] = nthdigit(b,0);
else if(b >= 10) buffer[i++] = nthdigit(b,1);
else buffer[i++] = nthdigit(b,2);
//Third int
if(c >= 100) buffer[i++] = nthdigit(c,0);
else if(c >= 10) buffer[i++] = nthdigit(c,1);
else buffer[i++] = nthdigit(c,2);
//Fourth int
if(d >= 100) buffer[i++] = nthdigit(d,0);
else if(d >= 10) buffer[i++] = nthdigit(d,1);
else buffer[i++] = nthdigit(d,2);
//Fifth int
if(e >= 100) buffer[i++] = nthdigit(e,0);
else if(e >= 10) buffer[i++] = nthdigit(e,1);
else buffer[i++] = nthdigit(e,2);
return i;
}
__global__ void parallelhash(float* in, int n, int* hash_table, int song_id)
{
int i, k;
float freq1, freq2, freq3, freq4, freq5;
float tempfreq, magnitude;
int pt1,pt2,pt3,pt4, pt5, key;
i = threadIdx.x + blockIdx.x*blockDim.x; //My chunk
if(i < n){ //if my chunk ID < total number of chunks we may continue
//Point Z to the right chunk location in the song
float* Z = &in[N*i];
four1(Z,N);
freq1 = freq2 = freq3 = freq4 = freq5 = 0;
pt1 = pt2 = pt3 = pt4 = pt5 = 0;
//Filter Frequency Bands
for(k=FREQBANDWIDTH; k<FREQBANDWIDTH*6; k++){
tempfreq = abs(Z[2*k]);
magnitude = log10(tempfreq+1);
if(k>=FREQBANDWIDTH && k<FREQBANDWIDTH*2 && magnitude>freq1) {freq1 = magnitude; pt1=k;}
else if(k>=FREQBANDWIDTH*2 && k<FREQBANDWIDTH*3 && magnitude>freq2) {freq2 = magnitude; pt2=k;}
else if(k>=FREQBANDWIDTH*3 && k<FREQBANDWIDTH*4 && magnitude>freq3) {freq3 = magnitude; pt3=k;}
else if(k>=FREQBANDWIDTH*4 && k<FREQBANDWIDTH*5 && magnitude>freq4) {freq4 = magnitude; pt4=k;}
else if(k>=FREQBANDWIDTH*5 && k<FREQBANDWIDTH*6 && magnitude>freq5) {freq5 = magnitude; pt5=k;}
}
//Hash the result inline
unsigned long long int hashresult = 0;
char buffer [15];
int k = 0, j = 0;
for(k = 0; k < 15; k ++) buffer[0] = 0;
j = generate_hash_string (buffer, pt1,pt2,pt3,pt4,pt5);
unsigned long long int hash = 5381;
k = 0;
for(k = 0; k < j; k ++)
hash = ((hash << 5) + hash) + buffer[k]; /* hash * 33 + c */
hashresult = hash % MAXELEMS;
//Write result to hash table
key = (int) hashresult;
atomicAdd(&(hash_table[(key*(MAXSONGS+1))+(song_id)]),1);
}
}
__device__ void four1(float* data, int nn)
{
int n, mmax, m, j, istep, i;
float wtemp, wr, wpr, wpi, wi, theta;
float tempr, tempi;
// reverse-binary reindexing
n = nn<<1;
j=1;
for (i=1; i<n; i+=2)
{
if (j>i) //data swap should be parallelizeable
{
float temp = data[j-1];
data[j-1] = data[i-1];
data[i-1] = temp;
temp = data[j];
data[j] = data[i];
data[i] = temp;
}
m = nn;
while (m>=2 && j>m)
{
j -= m;
m >>= 1;
}
j += m;
}
// here begins the Danielson-Lanczos section
mmax=2;
while (n>mmax) {
istep = mmax<<1;
theta = -(2*M_PI/mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1; m < mmax; m += 2) {
for (i=m; i <= n; i += istep) {
j=i+mmax;
tempr = wr*data[j-1] - wi*data[j];
tempi = wr * data[j] + wi*data[j-1];
data[j-1] = data[i-1] - tempr;
data[j] = data[i] - tempi;
data[i-1] += tempr;
data[i] += tempi;
}
wtemp=wr;
wr += wr*wpr - wi*wpi;
wi += wi*wpr + wtemp*wpi;
}
mmax=istep;
}
} | .text
.file "kernel.hip"
.globl _Z26__device_stub__calc_scoresPiS_ # -- Begin function _Z26__device_stub__calc_scoresPiS_
.p2align 4, 0x90
.type _Z26__device_stub__calc_scoresPiS_,@function
_Z26__device_stub__calc_scoresPiS_: # @_Z26__device_stub__calc_scoresPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11calc_scoresPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__calc_scoresPiS_, .Lfunc_end0-_Z26__device_stub__calc_scoresPiS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__parallelhashPfiPii # -- Begin function _Z27__device_stub__parallelhashPfiPii
.p2align 4, 0x90
.type _Z27__device_stub__parallelhashPfiPii,@function
_Z27__device_stub__parallelhashPfiPii: # @_Z27__device_stub__parallelhashPfiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12parallelhashPfiPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__parallelhashPfiPii, .Lfunc_end1-_Z27__device_stub__parallelhashPfiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calc_scoresPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12parallelhashPfiPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11calc_scoresPiS_,@object # @_Z11calc_scoresPiS_
.section .rodata,"a",@progbits
.globl _Z11calc_scoresPiS_
.p2align 3, 0x0
_Z11calc_scoresPiS_:
.quad _Z26__device_stub__calc_scoresPiS_
.size _Z11calc_scoresPiS_, 8
.type _Z12parallelhashPfiPii,@object # @_Z12parallelhashPfiPii
.globl _Z12parallelhashPfiPii
.p2align 3, 0x0
_Z12parallelhashPfiPii:
.quad _Z27__device_stub__parallelhashPfiPii
.size _Z12parallelhashPfiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11calc_scoresPiS_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12parallelhashPfiPii"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__calc_scoresPiS_
.addrsig_sym _Z27__device_stub__parallelhashPfiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11calc_scoresPiS_
.addrsig_sym _Z12parallelhashPfiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001631ae_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8nthdigitii
.type _Z8nthdigitii, @function
_Z8nthdigitii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8nthdigitii, .-_Z8nthdigitii
.globl _Z20generate_hash_stringPciiiii
.type _Z20generate_hash_stringPciiiii, @function
_Z20generate_hash_stringPciiiii:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z20generate_hash_stringPciiiii, .-_Z20generate_hash_stringPciiiii
.globl _Z5four1Pfi
.type _Z5four1Pfi, @function
_Z5four1Pfi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z5four1Pfi, .-_Z5four1Pfi
.globl _Z33__device_stub__Z11calc_scoresPiS_PiS_
.type _Z33__device_stub__Z11calc_scoresPiS_PiS_, @function
_Z33__device_stub__Z11calc_scoresPiS_PiS_:
.LFB2054:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11calc_scoresPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z33__device_stub__Z11calc_scoresPiS_PiS_, .-_Z33__device_stub__Z11calc_scoresPiS_PiS_
.globl _Z11calc_scoresPiS_
.type _Z11calc_scoresPiS_, @function
_Z11calc_scoresPiS_:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11calc_scoresPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z11calc_scoresPiS_, .-_Z11calc_scoresPiS_
.globl _Z36__device_stub__Z12parallelhashPfiPiiPfiPii
.type _Z36__device_stub__Z12parallelhashPfiPiiPfiPii, @function
_Z36__device_stub__Z12parallelhashPfiPiiPfiPii:
.LFB2056:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12parallelhashPfiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z36__device_stub__Z12parallelhashPfiPiiPfiPii, .-_Z36__device_stub__Z12parallelhashPfiPiiPfiPii
.globl _Z12parallelhashPfiPii
.type _Z12parallelhashPfiPii, @function
_Z12parallelhashPfiPii:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12parallelhashPfiPiiPfiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12parallelhashPfiPii, .-_Z12parallelhashPfiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12parallelhashPfiPii"
.LC1:
.string "_Z11calc_scoresPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12parallelhashPfiPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calc_scoresPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z26__device_stub__calc_scoresPiS_ # -- Begin function _Z26__device_stub__calc_scoresPiS_
.p2align 4, 0x90
.type _Z26__device_stub__calc_scoresPiS_,@function
_Z26__device_stub__calc_scoresPiS_: # @_Z26__device_stub__calc_scoresPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11calc_scoresPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__calc_scoresPiS_, .Lfunc_end0-_Z26__device_stub__calc_scoresPiS_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__parallelhashPfiPii # -- Begin function _Z27__device_stub__parallelhashPfiPii
.p2align 4, 0x90
.type _Z27__device_stub__parallelhashPfiPii,@function
_Z27__device_stub__parallelhashPfiPii: # @_Z27__device_stub__parallelhashPfiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12parallelhashPfiPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__parallelhashPfiPii, .Lfunc_end1-_Z27__device_stub__parallelhashPfiPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calc_scoresPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12parallelhashPfiPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11calc_scoresPiS_,@object # @_Z11calc_scoresPiS_
.section .rodata,"a",@progbits
.globl _Z11calc_scoresPiS_
.p2align 3, 0x0
_Z11calc_scoresPiS_:
.quad _Z26__device_stub__calc_scoresPiS_
.size _Z11calc_scoresPiS_, 8
.type _Z12parallelhashPfiPii,@object # @_Z12parallelhashPfiPii
.globl _Z12parallelhashPfiPii
.p2align 3, 0x0
_Z12parallelhashPfiPii:
.quad _Z27__device_stub__parallelhashPfiPii
.size _Z12parallelhashPfiPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11calc_scoresPiS_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12parallelhashPfiPii"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__calc_scoresPiS_
.addrsig_sym _Z27__device_stub__parallelhashPfiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11calc_scoresPiS_
.addrsig_sym _Z12parallelhashPfiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
if (comp < (var_1 / (var_2 + var_3))) {
if (comp == ldexpf(powf(var_4 + (-0.0f - (-1.5613E-41f * var_5)), (var_6 / (+1.1736E-2f / var_7 / cosf((-1.8611E-27f + -1.1853E-44f - var_8))))), 2)) {
comp += floorf(+1.2703E-4f / sinf((-1.1071E-35f / acosf((+1.8437E36f / +0.0f * +1.2212E14f)))));
if (comp == (+1.7207E-42f - +1.3187E-43f / var_9 + var_10 * sqrtf(var_11 + (-1.2206E-35f / var_12)))) {
comp += -1.2395E-42f * +1.1947E29f - var_13;
float tmp_1 = var_14 - var_15;
comp = tmp_1 * (-1.7753E-24f - cosf((+1.1999E-44f - +1.0404E35f - -0.0f)));
}
if (comp >= powf((-1.0831E-44f - (-1.6197E-37f * (var_16 + var_17))), var_18 - var_19)) {
comp += +1.8563E-37f / (+1.1762E-36f / (var_20 - (+1.3362E-44f / expf(-0.0f - -0.0f))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0018b5c1_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
.type _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, @function
_Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 296
pushq 40(%rsp)
.cfi_def_cfa_offset 304
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computefffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, .-_Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
.globl _Z7computefffffffffffffffffffff
.type _Z7computefffffffffffffffffffff, @function
_Z7computefffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss 224(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffffffffffffffffffff, .-_Z7computefffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $208, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 196(%rsp), %rdx
movl $1, %ecx
movq 184(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 168(%rsp), %xmm0
subq $112, %rsp
.cfi_def_cfa_offset 336
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 224(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 232(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 240(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 248(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 256(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 264(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
addq $112, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
if (comp < (var_1 / (var_2 + var_3))) {
if (comp == ldexpf(powf(var_4 + (-0.0f - (-1.5613E-41f * var_5)), (var_6 / (+1.1736E-2f / var_7 / cosf((-1.8611E-27f + -1.1853E-44f - var_8))))), 2)) {
comp += floorf(+1.2703E-4f / sinf((-1.1071E-35f / acosf((+1.8437E36f / +0.0f * +1.2212E14f)))));
if (comp == (+1.7207E-42f - +1.3187E-43f / var_9 + var_10 * sqrtf(var_11 + (-1.2206E-35f / var_12)))) {
comp += -1.2395E-42f * +1.1947E29f - var_13;
float tmp_1 = var_14 - var_15;
comp = tmp_1 * (-1.7753E-24f - cosf((+1.1999E-44f - +1.0404E35f - -0.0f)));
}
if (comp >= powf((-1.0831E-44f - (-1.6197E-37f * (var_16 + var_17))), var_18 - var_19)) {
comp += +1.8563E-37f / (+1.1762E-36f / (var_20 - (+1.3362E-44f / expf(-0.0f - -0.0f))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
if (comp < (var_1 / (var_2 + var_3))) {
if (comp == ldexpf(powf(var_4 + (-0.0f - (-1.5613E-41f * var_5)), (var_6 / (+1.1736E-2f / var_7 / cosf((-1.8611E-27f + -1.1853E-44f - var_8))))), 2)) {
comp += floorf(+1.2703E-4f / sinf((-1.1071E-35f / acosf((+1.8437E36f / +0.0f * +1.2212E14f)))));
if (comp == (+1.7207E-42f - +1.3187E-43f / var_9 + var_10 * sqrtf(var_11 + (-1.2206E-35f / var_12)))) {
comp += -1.2395E-42f * +1.1947E29f - var_13;
float tmp_1 = var_14 - var_15;
comp = tmp_1 * (-1.7753E-24f - cosf((+1.1999E-44f - +1.0404E35f - -0.0f)));
}
if (comp >= powf((-1.0831E-44f - (-1.6197E-37f * (var_16 + var_17))), var_18 - var_19)) {
comp += +1.8563E-37f / (+1.1762E-36f / (var_20 - (+1.3362E-44f / expf(-0.0f - -0.0f))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20) {
if (comp < (var_1 / (var_2 + var_3))) {
if (comp == ldexpf(powf(var_4 + (-0.0f - (-1.5613E-41f * var_5)), (var_6 / (+1.1736E-2f / var_7 / cosf((-1.8611E-27f + -1.1853E-44f - var_8))))), 2)) {
comp += floorf(+1.2703E-4f / sinf((-1.1071E-35f / acosf((+1.8437E36f / +0.0f * +1.2212E14f)))));
if (comp == (+1.7207E-42f - +1.3187E-43f / var_9 + var_10 * sqrtf(var_11 + (-1.2206E-35f / var_12)))) {
comp += -1.2395E-42f * +1.1947E29f - var_13;
float tmp_1 = var_14 - var_15;
comp = tmp_1 * (-1.7753E-24f - cosf((+1.1999E-44f - +1.0404E35f - -0.0f)));
}
if (comp >= powf((-1.0831E-44f - (-1.6197E-37f * (var_16 + var_17))), var_18 - var_19)) {
comp += +1.8563E-37f / (+1.1762E-36f / (var_20 - (+1.3362E-44f / expf(-0.0f - -0.0f))));
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefffffffffffffffffffff # -- Begin function _Z22__device_stub__computefffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefffffffffffffffffffff,@function
_Z22__device_stub__computefffffffffffffffffffff: # @_Z22__device_stub__computefffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computefffffffffffffffffffff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 40(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 48(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 56(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 64(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 72(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 88(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 96(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 104(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 112(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 120(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 128(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 136(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 144(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 152(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 160(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 168(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 96(%rsp)
movss %xmm9, 88(%rsp)
movss %xmm10, 80(%rsp)
movss %xmm11, 72(%rsp)
movss %xmm12, 64(%rsp)
movss %xmm13, 56(%rsp)
movss %xmm14, 48(%rsp)
movss %xmm15, 40(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 24(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 8(%rsp)
movss 104(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movss 136(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 128(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffffffffffffffffffff,@object # @_Z7computefffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefffffffffffffffffffff
.p2align 3, 0x0
_Z7computefffffffffffffffffffff:
.quad _Z22__device_stub__computefffffffffffffffffffff
.size _Z7computefffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffffffffffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018b5c1_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
.type _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, @function
_Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 296
pushq 40(%rsp)
.cfi_def_cfa_offset 304
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7computefffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff, .-_Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
.globl _Z7computefffffffffffffffffffff
.type _Z7computefffffffffffffffffffff, @function
_Z7computefffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss 224(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffffffffffffffffffff, .-_Z7computefffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $208, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 196(%rsp), %rdx
movl $1, %ecx
movq 184(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 168(%rsp), %xmm0
subq $112, %rsp
.cfi_def_cfa_offset 336
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 224(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 232(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 240(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 248(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 256(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 264(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
call _Z45__device_stub__Z7computeffffffffffffffffffffffffffffffffffffffffff
addq $112, %rsp
.cfi_def_cfa_offset 224
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefffffffffffffffffffff # -- Begin function _Z22__device_stub__computefffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefffffffffffffffffffff,@function
_Z22__device_stub__computefffffffffffffffffffff: # @_Z22__device_stub__computefffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 352(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computefffffffffffffffffffff, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 24(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 40(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 48(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 56(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 64(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 72(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 88(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 96(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 104(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 112(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 120(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 128(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 136(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 144(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 152(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 160(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 168(%rbx), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 104(%rsp) # 4-byte Spill
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 96(%rsp)
movss %xmm9, 88(%rsp)
movss %xmm10, 80(%rsp)
movss %xmm11, 72(%rsp)
movss %xmm12, 64(%rsp)
movss %xmm13, 56(%rsp)
movss %xmm14, 48(%rsp)
movss %xmm15, 40(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 24(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 8(%rsp)
movss 104(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movss 136(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 128(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 120(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $272, %rsp # imm = 0x110
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffffffffffffffffffff,@object # @_Z7computefffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefffffffffffffffffffff
.p2align 3, 0x0
_Z7computefffffffffffffffffffff:
.quad _Z22__device_stub__computefffffffffffffffffffff
.size _Z7computefffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffffffffffffffffffff"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/time.h>
void genRandomString(char *str,int length)
{
for(int i=0;i<length-1;++i)
{
str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
void genRandomSubString(char *str,int length,int sub_len)
{
for(int i=0;i<length-1;++i)
{
if(i>0 && ((i+1)%sub_len==0)) str[i] = '\0';
else str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
/*__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
char *sub = &sub_string[id*sub_len];
char *string = str;
char *a,*b;
b = sub;
printf("in GPU string is %s sub is %s\n",string,b);
for(;*string != '\0';++string){
a = string;
if(*a == *b){
printf("thread %d find a possible sub %s\n",id,b);
while(*(++a) == *(++b)){
printf("thread %d find a more and more possible sub %s\n",id,b);
if(*(b+1) == '\0'){
printf("thread %d find a sub %s\n",id,b);
position[id] = string;
printf("sting match in %s\n",position[id]);
}
}
}
b = sub;
}
}*/
char * my_strstr(char *str,char *sub,int str_len,int sub_len)
{
if(str_len < sub_len) return NULL;
if(str_len != 0 && sub_len == 0) return NULL;
if(str_len == 0 && sub_len == 0) return NULL;
int m, n;
for(int i=0;i<str_len;++i){
m = 0;
n = i;
if(str[n]==sub[m]){
while(str[++n] == sub[++m]){
if(sub[m+1] == '\0') return str+i;
}
}
}
return NULL;
}
__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
//char *sub = &sub_string[id*sub_len];
char *result = NULL;
char sub[24];
//load sub in register,great improve
for(int i=0;i<sub_len;++i){
sub[i] = sub_string[id*sub_len+i];}
//best case using Shared memory
extern __shared__ char s_string[];
//every thread has to fetch how many values from global memory to shared memory
int each_num = str_len/blockDim.x;
for(int i=0;i<each_num;++i){
s_string[i*blockDim.x+id] = str[i*blockDim.x+id];}
if( ((each_num*blockDim.x+id) < str_len) && (blockDim.x > each_num) )
s_string[each_num*blockDim.x+id] = str[each_num*blockDim.x+id];
char *string = s_string;
char *a,*b;
//b point to the sub address in register rather than in global memory
b = sub;
//result == NULL to judge if we find a match;rather than use goto or break in loop which harm the calculation
for(int i = 0;(*string != '\0')&&(result == NULL);i++){
//printf("i am %d\n",id);
a = string;
while(*a++ == *b++){
if(*(b+1) == '\0'){
result = string;
}
}
b = sub;
++string;
}
//coalesced global memory store, no effect since we only store once
position[id] = result;
}
int main()
{
int LENGTH = 4096, len = 24, num_sub = 100;
int num_block,num_thread;
if(num_sub < 512){
num_block = 1;
num_thread = num_sub;
}
else{
num_block = num_sub / 512;
num_thread = 512;
}
char haystack[LENGTH];
char subs[num_sub*len];
char *position[num_sub];
char *h_position[num_sub];
genRandomString(haystack,LENGTH);
genRandomSubString(subs,len*num_sub,len);
char *d_string,*d_subs;
char **d_position;
cudaMalloc((void**)&d_string,sizeof(char)*LENGTH);
cudaMalloc((void**)&d_subs,sizeof(char)*num_sub*len);
cudaMalloc((void***)&d_position,sizeof(char*)*num_sub);
cudaMemset(d_position,0,sizeof(char*)*num_sub);
memset(h_position,0,sizeof(char*)*num_sub);
const size_t smem = sizeof(char)*LENGTH;
char h_subs[num_sub][len];
for(int i=0;i<num_sub;++i){
for(int j=0;j<len;++j){
h_subs[i][j] = subs[i*len+j];
}
}
/*CPU*/
char *ret;
struct timeval start,end;
gettimeofday(&start, NULL );
for(int i=0;i<num_sub;++i)
{
ret = my_strstr(haystack,h_subs[i],LENGTH,len);
if(ret != NULL){
printf("find one sub string in %d sub\n",i);
printf("%s\n",ret);
}
position[i] = ret;
}
gettimeofday(&end, NULL );
float timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("CPU time=%f\n",timeuse /1000.0);
/*GPU*/
gettimeofday(&start, NULL );
for(int i=0;i<50;++i)
{
cudaMemcpy(d_string,haystack,sizeof(char)*LENGTH,cudaMemcpyHostToDevice);
cudaMemcpy(d_subs,subs,sizeof(char)*num_sub*len,cudaMemcpyHostToDevice);
my_strstr<<<num_block,num_thread,smem>>>(d_string,d_subs,d_position,LENGTH,len,num_sub);
cudaDeviceSynchronize();
cudaMemcpy(h_position,d_position,sizeof(char*)*num_sub,cudaMemcpyDeviceToHost);
}
gettimeofday(&end, NULL );
timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("GPU time=%f\n",timeuse /1000.0/50);
/*check*/
//in small size GPU works well
/*for(int i=0;i<num_sub;++i){
if(h_position[i] == position[i]){
printf("ok in %d sub\n",i);
if(position[i] != NULL){
printf("%s\n",position[i]);
}
}
else{
printf("error !!!!!!");
if(position[i] != NULL){
printf("CPU find match %s\n",position[i]);}
//because h_position[i] point to the address in GPU , causing segment error
if(h_position[i] != NULL){
printf("GPU find match %s\n",h_position[i]);}
}
}*/
return(0);
} | .file "tmpxft_00064c8b_00000000-6_v1_match.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15genRandomStringPci
.type _Z15genRandomStringPci, @function
_Z15genRandomStringPci:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movl %esi, %r12d
cmpl $1, %esi
jle .L4
movq %rdi, %rbx
leal -2(%rsi), %eax
leaq 1(%rdi,%rax), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %edx
subl %edx, %eax
addl $97, %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
movslq %r12d, %r12
movb $0, -1(%r13,%r12)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15genRandomStringPci, .-_Z15genRandomStringPci
.globl _Z18genRandomSubStringPcii
.type _Z18genRandomSubStringPcii, @function
_Z18genRandomSubStringPcii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %r14d
cmpl $1, %esi
jle .L9
movl %edx, %ebp
leal -1(%rsi), %r13d
movl $0, %ebx
movl $0, %r15d
jmp .L12
.L10:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %edx
subl %edx, %eax
addl $97, %eax
.L11:
movb %al, (%r12,%rbx)
addq $1, %rbx
cmpq %r13, %rbx
je .L9
.L12:
testl %ebx, %ebx
jle .L10
leal 1(%rbx), %eax
cltd
idivl %ebp
movl %r15d, %eax
testl %edx, %edx
je .L11
jmp .L10
.L9:
movslq %r14d, %r14
movb $0, -1(%r12,%r14)
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z18genRandomSubStringPcii, .-_Z18genRandomSubStringPcii
.globl _Z9my_strstrPcS_ii
.type _Z9my_strstrPcS_ii, @function
_Z9my_strstrPcS_ii:
.LFB2059:
.cfi_startproc
endbr64
cmpl %ecx, %edx
jl .L23
testl %edx, %edx
je .L28
movl $0, %r8d
testl %ecx, %ecx
je .L16
.L28:
orl %edx, %ecx
je .L25
testl %edx, %edx
jle .L26
movzbl (%rsi), %r9d
movl $0, %ecx
jmp .L22
.L20:
addl $1, %ecx
addq $1, %rdi
cmpl %ecx, %edx
je .L30
.L22:
movq %rdi, %r8
cmpb %r9b, (%rdi)
jne .L20
movl $1, %eax
.L19:
movzbl (%rsi,%rax), %r10d
cmpb %r10b, (%r8,%rax)
jne .L20
addq $1, %rax
cmpb $0, (%rsi,%rax)
jne .L19
.L16:
movq %r8, %rax
ret
.L30:
movl $0, %r8d
jmp .L16
.L23:
movl $0, %r8d
jmp .L16
.L25:
movl $0, %r8d
jmp .L16
.L26:
movl $0, %r8d
jmp .L16
.cfi_endproc
.LFE2059:
.size _Z9my_strstrPcS_ii, .-_Z9my_strstrPcS_ii
.globl _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
.type _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii, @function
_Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9my_strstrPcS_PS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii, .-_Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
.globl _Z9my_strstrPcS_PS_iii
.type _Z9my_strstrPcS_PS_iii, @function
_Z9my_strstrPcS_PS_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9my_strstrPcS_PS_iii, .-_Z9my_strstrPcS_PS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "find one sub string in %d sub\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s\n"
.LC3:
.string "CPU time=%f\n"
.LC5:
.string "GPU time=%f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -4096(%rsp), %rax
.L40:
cmpq %rax, %rsp
je .L41
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L40
.L41:
movq %rsp, %r15
movq %rsp, %rax
.L43:
cmpq %rax, %rsp
je .L44
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L43
.L44:
subq $2400, %rsp
orq $0, 2392(%rsp)
movq %rsp, %r12
movq %rsp, %rax
.L46:
cmpq %rax, %rsp
je .L47
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L46
.L47:
subq $800, %rsp
orq $0, 792(%rsp)
movq %rsp, -152(%rbp)
movq %rsp, %rax
.L49:
cmpq %rax, %rsp
je .L50
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L49
.L50:
subq $800, %rsp
orq $0, 792(%rsp)
movq %rsp, %rbx
movq %rbx, -160(%rbp)
movl $4096, %esi
movq %r15, %rdi
call _Z15genRandomStringPci
movl $24, %edx
movl $2400, %esi
movq %r12, %rdi
call _Z18genRandomSubStringPcii
leaq -144(%rbp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq -136(%rbp), %rdi
movl $2400, %esi
call cudaMalloc@PLT
leaq -128(%rbp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $800, %edx
movl $0, %esi
movq -128(%rbp), %rdi
call cudaMemset@PLT
movl $100, %ecx
movl $0, %eax
movq %rbx, %rdi
rep stosq
movq %rsp, %rax
.L52:
cmpq %rax, %rsp
je .L53
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L52
.L53:
subq $2400, %rsp
orq $0, 2392(%rsp)
movq %rsp, %rbx
movl $24, %ecx
movl $0, %esi
jmp .L55
.L67:
addq $24, %rsi
addq $24, %rcx
cmpq $2424, %rcx
je .L57
.L55:
movq %rsi, %rax
.L56:
movzbl (%r12,%rax), %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L56
jmp .L67
.L57:
leaq -96(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %r14d
jmp .L59
.L58:
movq -152(%rbp), %rax
movq %r13, (%rax,%r14,8)
addq $1, %r14
addq $24, %rbx
cmpq $100, %r14
je .L68
.L59:
movl $24, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq %r15, %rdi
call _Z9my_strstrPcS_ii
movq %rax, %r13
testq %rax, %rax
je .L58
movl %r14d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L58
.L68:
leaq -80(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax
addq -72(%rbp), %rax
subq -88(%rbp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq -96(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $50, %ebx
jmp .L61
.L60:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $800, %edx
movq -128(%rbp), %rsi
movq -160(%rbp), %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L69
.L61:
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq -144(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2400, %edx
movq %r12, %rsi
movq -136(%rbp), %rdi
call cudaMemcpy@PLT
movl $100, -108(%rbp)
movl $1, -104(%rbp)
movl $1, -120(%rbp)
movl $1, -116(%rbp)
movl $0, %r9d
movl $4096, %r8d
movq -108(%rbp), %rdx
movl $1, %ecx
movq -120(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L60
movl $100, %r9d
movl $24, %r8d
movl $4096, %ecx
movq -128(%rbp), %rdx
movq -136(%rbp), %rsi
movq -144(%rbp), %rdi
call _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
jmp .L60
.L69:
leaq -80(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax
addq -72(%rbp), %rax
subq -88(%rbp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC2(%rip), %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L70:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9my_strstrPcS_PS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_strstrPcS_PS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.align 8
.LC4:
.long 0
.long 1078525952
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/time.h>
void genRandomString(char *str,int length)
{
for(int i=0;i<length-1;++i)
{
str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
void genRandomSubString(char *str,int length,int sub_len)
{
for(int i=0;i<length-1;++i)
{
if(i>0 && ((i+1)%sub_len==0)) str[i] = '\0';
else str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
/*__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
char *sub = &sub_string[id*sub_len];
char *string = str;
char *a,*b;
b = sub;
printf("in GPU string is %s sub is %s\n",string,b);
for(;*string != '\0';++string){
a = string;
if(*a == *b){
printf("thread %d find a possible sub %s\n",id,b);
while(*(++a) == *(++b)){
printf("thread %d find a more and more possible sub %s\n",id,b);
if(*(b+1) == '\0'){
printf("thread %d find a sub %s\n",id,b);
position[id] = string;
printf("sting match in %s\n",position[id]);
}
}
}
b = sub;
}
}*/
char * my_strstr(char *str,char *sub,int str_len,int sub_len)
{
if(str_len < sub_len) return NULL;
if(str_len != 0 && sub_len == 0) return NULL;
if(str_len == 0 && sub_len == 0) return NULL;
int m, n;
for(int i=0;i<str_len;++i){
m = 0;
n = i;
if(str[n]==sub[m]){
while(str[++n] == sub[++m]){
if(sub[m+1] == '\0') return str+i;
}
}
}
return NULL;
}
__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
//char *sub = &sub_string[id*sub_len];
char *result = NULL;
char sub[24];
//load sub in register,great improve
for(int i=0;i<sub_len;++i){
sub[i] = sub_string[id*sub_len+i];}
//best case using Shared memory
extern __shared__ char s_string[];
//every thread has to fetch how many values from global memory to shared memory
int each_num = str_len/blockDim.x;
for(int i=0;i<each_num;++i){
s_string[i*blockDim.x+id] = str[i*blockDim.x+id];}
if( ((each_num*blockDim.x+id) < str_len) && (blockDim.x > each_num) )
s_string[each_num*blockDim.x+id] = str[each_num*blockDim.x+id];
char *string = s_string;
char *a,*b;
//b point to the sub address in register rather than in global memory
b = sub;
//result == NULL to judge if we find a match;rather than use goto or break in loop which harm the calculation
for(int i = 0;(*string != '\0')&&(result == NULL);i++){
//printf("i am %d\n",id);
a = string;
while(*a++ == *b++){
if(*(b+1) == '\0'){
result = string;
}
}
b = sub;
++string;
}
//coalesced global memory store, no effect since we only store once
position[id] = result;
}
int main()
{
int LENGTH = 4096, len = 24, num_sub = 100;
int num_block,num_thread;
if(num_sub < 512){
num_block = 1;
num_thread = num_sub;
}
else{
num_block = num_sub / 512;
num_thread = 512;
}
char haystack[LENGTH];
char subs[num_sub*len];
char *position[num_sub];
char *h_position[num_sub];
genRandomString(haystack,LENGTH);
genRandomSubString(subs,len*num_sub,len);
char *d_string,*d_subs;
char **d_position;
cudaMalloc((void**)&d_string,sizeof(char)*LENGTH);
cudaMalloc((void**)&d_subs,sizeof(char)*num_sub*len);
cudaMalloc((void***)&d_position,sizeof(char*)*num_sub);
cudaMemset(d_position,0,sizeof(char*)*num_sub);
memset(h_position,0,sizeof(char*)*num_sub);
const size_t smem = sizeof(char)*LENGTH;
char h_subs[num_sub][len];
for(int i=0;i<num_sub;++i){
for(int j=0;j<len;++j){
h_subs[i][j] = subs[i*len+j];
}
}
/*CPU*/
char *ret;
struct timeval start,end;
gettimeofday(&start, NULL );
for(int i=0;i<num_sub;++i)
{
ret = my_strstr(haystack,h_subs[i],LENGTH,len);
if(ret != NULL){
printf("find one sub string in %d sub\n",i);
printf("%s\n",ret);
}
position[i] = ret;
}
gettimeofday(&end, NULL );
float timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("CPU time=%f\n",timeuse /1000.0);
/*GPU*/
gettimeofday(&start, NULL );
for(int i=0;i<50;++i)
{
cudaMemcpy(d_string,haystack,sizeof(char)*LENGTH,cudaMemcpyHostToDevice);
cudaMemcpy(d_subs,subs,sizeof(char)*num_sub*len,cudaMemcpyHostToDevice);
my_strstr<<<num_block,num_thread,smem>>>(d_string,d_subs,d_position,LENGTH,len,num_sub);
cudaDeviceSynchronize();
cudaMemcpy(h_position,d_position,sizeof(char*)*num_sub,cudaMemcpyDeviceToHost);
}
gettimeofday(&end, NULL );
timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("GPU time=%f\n",timeuse /1000.0/50);
/*check*/
//in small size GPU works well
/*for(int i=0;i<num_sub;++i){
if(h_position[i] == position[i]){
printf("ok in %d sub\n",i);
if(position[i] != NULL){
printf("%s\n",position[i]);
}
}
else{
printf("error !!!!!!");
if(position[i] != NULL){
printf("CPU find match %s\n",position[i]);}
//because h_position[i] point to the address in GPU , causing segment error
if(h_position[i] != NULL){
printf("GPU find match %s\n",h_position[i]);}
}
}*/
return(0);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/time.h>
void genRandomString(char *str,int length)
{
for(int i=0;i<length-1;++i)
{
str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
void genRandomSubString(char *str,int length,int sub_len)
{
for(int i=0;i<length-1;++i)
{
if(i>0 && ((i+1)%sub_len==0)) str[i] = '\0';
else str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
/*__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
char *sub = &sub_string[id*sub_len];
char *string = str;
char *a,*b;
b = sub;
printf("in GPU string is %s sub is %s\n",string,b);
for(;*string != '\0';++string){
a = string;
if(*a == *b){
printf("thread %d find a possible sub %s\n",id,b);
while(*(++a) == *(++b)){
printf("thread %d find a more and more possible sub %s\n",id,b);
if(*(b+1) == '\0'){
printf("thread %d find a sub %s\n",id,b);
position[id] = string;
printf("sting match in %s\n",position[id]);
}
}
}
b = sub;
}
}*/
char * my_strstr(char *str,char *sub,int str_len,int sub_len)
{
if(str_len < sub_len) return NULL;
if(str_len != 0 && sub_len == 0) return NULL;
if(str_len == 0 && sub_len == 0) return NULL;
int m, n;
for(int i=0;i<str_len;++i){
m = 0;
n = i;
if(str[n]==sub[m]){
while(str[++n] == sub[++m]){
if(sub[m+1] == '\0') return str+i;
}
}
}
return NULL;
}
__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
//char *sub = &sub_string[id*sub_len];
char *result = NULL;
char sub[24];
//load sub in register,great improve
for(int i=0;i<sub_len;++i){
sub[i] = sub_string[id*sub_len+i];}
//best case using Shared memory
extern __shared__ char s_string[];
//every thread has to fetch how many values from global memory to shared memory
int each_num = str_len/blockDim.x;
for(int i=0;i<each_num;++i){
s_string[i*blockDim.x+id] = str[i*blockDim.x+id];}
if( ((each_num*blockDim.x+id) < str_len) && (blockDim.x > each_num) )
s_string[each_num*blockDim.x+id] = str[each_num*blockDim.x+id];
char *string = s_string;
char *a,*b;
//b point to the sub address in register rather than in global memory
b = sub;
//result == NULL to judge if we find a match;rather than use goto or break in loop which harm the calculation
for(int i = 0;(*string != '\0')&&(result == NULL);i++){
//printf("i am %d\n",id);
a = string;
while(*a++ == *b++){
if(*(b+1) == '\0'){
result = string;
}
}
b = sub;
++string;
}
//coalesced global memory store, no effect since we only store once
position[id] = result;
}
int main()
{
int LENGTH = 4096, len = 24, num_sub = 100;
int num_block,num_thread;
if(num_sub < 512){
num_block = 1;
num_thread = num_sub;
}
else{
num_block = num_sub / 512;
num_thread = 512;
}
char haystack[LENGTH];
char subs[num_sub*len];
char *position[num_sub];
char *h_position[num_sub];
genRandomString(haystack,LENGTH);
genRandomSubString(subs,len*num_sub,len);
char *d_string,*d_subs;
char **d_position;
hipMalloc((void**)&d_string,sizeof(char)*LENGTH);
hipMalloc((void**)&d_subs,sizeof(char)*num_sub*len);
hipMalloc((void***)&d_position,sizeof(char*)*num_sub);
hipMemset(d_position,0,sizeof(char*)*num_sub);
memset(h_position,0,sizeof(char*)*num_sub);
const size_t smem = sizeof(char)*LENGTH;
char h_subs[num_sub][len];
for(int i=0;i<num_sub;++i){
for(int j=0;j<len;++j){
h_subs[i][j] = subs[i*len+j];
}
}
/*CPU*/
char *ret;
struct timeval start,end;
gettimeofday(&start, NULL );
for(int i=0;i<num_sub;++i)
{
ret = my_strstr(haystack,h_subs[i],LENGTH,len);
if(ret != NULL){
printf("find one sub string in %d sub\n",i);
printf("%s\n",ret);
}
position[i] = ret;
}
gettimeofday(&end, NULL );
float timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("CPU time=%f\n",timeuse /1000.0);
/*GPU*/
gettimeofday(&start, NULL );
for(int i=0;i<50;++i)
{
hipMemcpy(d_string,haystack,sizeof(char)*LENGTH,hipMemcpyHostToDevice);
hipMemcpy(d_subs,subs,sizeof(char)*num_sub*len,hipMemcpyHostToDevice);
my_strstr<<<num_block,num_thread,smem>>>(d_string,d_subs,d_position,LENGTH,len,num_sub);
hipDeviceSynchronize();
hipMemcpy(h_position,d_position,sizeof(char*)*num_sub,hipMemcpyDeviceToHost);
}
gettimeofday(&end, NULL );
timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("GPU time=%f\n",timeuse /1000.0/50);
/*check*/
//in small size GPU works well
/*for(int i=0;i<num_sub;++i){
if(h_position[i] == position[i]){
printf("ok in %d sub\n",i);
if(position[i] != NULL){
printf("%s\n",position[i]);
}
}
else{
printf("error !!!!!!");
if(position[i] != NULL){
printf("CPU find match %s\n",position[i]);}
//because h_position[i] point to the address in GPU , causing segment error
if(h_position[i] != NULL){
printf("GPU find match %s\n",h_position[i]);}
}
}*/
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/time.h>
void genRandomString(char *str,int length)
{
for(int i=0;i<length-1;++i)
{
str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
void genRandomSubString(char *str,int length,int sub_len)
{
for(int i=0;i<length-1;++i)
{
if(i>0 && ((i+1)%sub_len==0)) str[i] = '\0';
else str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
/*__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
char *sub = &sub_string[id*sub_len];
char *string = str;
char *a,*b;
b = sub;
printf("in GPU string is %s sub is %s\n",string,b);
for(;*string != '\0';++string){
a = string;
if(*a == *b){
printf("thread %d find a possible sub %s\n",id,b);
while(*(++a) == *(++b)){
printf("thread %d find a more and more possible sub %s\n",id,b);
if(*(b+1) == '\0'){
printf("thread %d find a sub %s\n",id,b);
position[id] = string;
printf("sting match in %s\n",position[id]);
}
}
}
b = sub;
}
}*/
char * my_strstr(char *str,char *sub,int str_len,int sub_len)
{
if(str_len < sub_len) return NULL;
if(str_len != 0 && sub_len == 0) return NULL;
if(str_len == 0 && sub_len == 0) return NULL;
int m, n;
for(int i=0;i<str_len;++i){
m = 0;
n = i;
if(str[n]==sub[m]){
while(str[++n] == sub[++m]){
if(sub[m+1] == '\0') return str+i;
}
}
}
return NULL;
}
__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
//char *sub = &sub_string[id*sub_len];
char *result = NULL;
char sub[24];
//load sub in register,great improve
for(int i=0;i<sub_len;++i){
sub[i] = sub_string[id*sub_len+i];}
//best case using Shared memory
extern __shared__ char s_string[];
//every thread has to fetch how many values from global memory to shared memory
int each_num = str_len/blockDim.x;
for(int i=0;i<each_num;++i){
s_string[i*blockDim.x+id] = str[i*blockDim.x+id];}
if( ((each_num*blockDim.x+id) < str_len) && (blockDim.x > each_num) )
s_string[each_num*blockDim.x+id] = str[each_num*blockDim.x+id];
char *string = s_string;
char *a,*b;
//b point to the sub address in register rather than in global memory
b = sub;
//result == NULL to judge if we find a match;rather than use goto or break in loop which harm the calculation
for(int i = 0;(*string != '\0')&&(result == NULL);i++){
//printf("i am %d\n",id);
a = string;
while(*a++ == *b++){
if(*(b+1) == '\0'){
result = string;
}
}
b = sub;
++string;
}
//coalesced global memory store, no effect since we only store once
position[id] = result;
}
int main()
{
int LENGTH = 4096, len = 24, num_sub = 100;
int num_block,num_thread;
if(num_sub < 512){
num_block = 1;
num_thread = num_sub;
}
else{
num_block = num_sub / 512;
num_thread = 512;
}
char haystack[LENGTH];
char subs[num_sub*len];
char *position[num_sub];
char *h_position[num_sub];
genRandomString(haystack,LENGTH);
genRandomSubString(subs,len*num_sub,len);
char *d_string,*d_subs;
char **d_position;
hipMalloc((void**)&d_string,sizeof(char)*LENGTH);
hipMalloc((void**)&d_subs,sizeof(char)*num_sub*len);
hipMalloc((void***)&d_position,sizeof(char*)*num_sub);
hipMemset(d_position,0,sizeof(char*)*num_sub);
memset(h_position,0,sizeof(char*)*num_sub);
const size_t smem = sizeof(char)*LENGTH;
char h_subs[num_sub][len];
for(int i=0;i<num_sub;++i){
for(int j=0;j<len;++j){
h_subs[i][j] = subs[i*len+j];
}
}
/*CPU*/
char *ret;
struct timeval start,end;
gettimeofday(&start, NULL );
for(int i=0;i<num_sub;++i)
{
ret = my_strstr(haystack,h_subs[i],LENGTH,len);
if(ret != NULL){
printf("find one sub string in %d sub\n",i);
printf("%s\n",ret);
}
position[i] = ret;
}
gettimeofday(&end, NULL );
float timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("CPU time=%f\n",timeuse /1000.0);
/*GPU*/
gettimeofday(&start, NULL );
for(int i=0;i<50;++i)
{
hipMemcpy(d_string,haystack,sizeof(char)*LENGTH,hipMemcpyHostToDevice);
hipMemcpy(d_subs,subs,sizeof(char)*num_sub*len,hipMemcpyHostToDevice);
my_strstr<<<num_block,num_thread,smem>>>(d_string,d_subs,d_position,LENGTH,len,num_sub);
hipDeviceSynchronize();
hipMemcpy(h_position,d_position,sizeof(char*)*num_sub,hipMemcpyDeviceToHost);
}
gettimeofday(&end, NULL );
timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("GPU time=%f\n",timeuse /1000.0/50);
/*check*/
//in small size GPU works well
/*for(int i=0;i<num_sub;++i){
if(h_position[i] == position[i]){
printf("ok in %d sub\n",i);
if(position[i] != NULL){
printf("%s\n",position[i]);
}
}
else{
printf("error !!!!!!");
if(position[i] != NULL){
printf("CPU find match %s\n",position[i]);}
//because h_position[i] point to the address in GPU , causing segment error
if(h_position[i] != NULL){
printf("GPU find match %s\n",h_position[i]);}
}
}*/
return(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9my_strstrPcS_PS_iii
.globl _Z9my_strstrPcS_PS_iii
.p2align 8
.type _Z9my_strstrPcS_PS_iii,@function
_Z9my_strstrPcS_PS_iii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
v_mul_lo_u32 v1, v0, s2
v_mov_b32_e32 v3, 16
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s3, s4, v1
v_add_co_ci_u32_e64 v2, null, s5, 0, s3
.LBB0_2:
global_load_u8 v4, v[1:2], off
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
scratch_store_b8 v3, v4, off
v_add_nc_u32_e32 v3, 1, v3
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s5, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s3, 0, s4
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_mul_hi_u32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s2, s3
s_load_b64 s[2:3], s[0:1], 0x0
s_mul_hi_u32 s6, s5, s6
s_mul_i32 s7, s6, s4
s_add_i32 s8, s6, 1
s_sub_i32 s7, s5, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s4
s_cmp_ge_u32 s7, s4
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s4
s_mov_b32 s7, 0
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB0_6
v_mov_b32_e32 v1, v0
.LBB0_5:
s_waitcnt lgkmcnt(0)
global_load_u8 v2, v1, s[2:3]
v_add_nc_u32_e32 v3, 0, v1
v_add_nc_u32_e32 v1, s4, v1
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s7, s6
s_waitcnt vmcnt(0)
ds_store_b8 v3, v2
s_cbranch_scc0 .LBB0_5
.LBB0_6:
v_mad_u64_u32 v[1:2], null, s6, s4, v[0:1]
s_cmp_lt_u32 s6, s4
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s5, v1
s_and_b32 s5, s4, vcc_lo
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_8
s_waitcnt lgkmcnt(0)
global_load_u8 v2, v1, s[2:3]
v_add_nc_u32_e32 v1, 0, v1
s_waitcnt vmcnt(0)
ds_store_b8 v1, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v1, 0
s_mov_b32 s4, 0
ds_load_u8 v1, v1
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_16
scratch_load_u8 v1, off, off offset:16
s_mov_b32 s5, 0
s_mov_b64 s[2:3], src_shared_base
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0xff, v1
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v4, s4
v_cmp_ne_u64_e32 vcc_lo, 0, v[1:2]
s_add_i32 s4, s4, 1
ds_load_u8 v4, v4 offset:1
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s2, 0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, vcc_lo
s_and_b32 s2, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, s2, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_15
.LBB0_11:
v_mov_b32_e32 v1, s4
s_mov_b32 s6, exec_lo
ds_load_u8 v4, v1
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_cmpx_eq_u16_e64 v4, v3
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_cmp_lg_u32 s4, -1
s_mov_b32 s7, 0
s_cselect_b32 s8, s3, 0
s_cselect_b32 s9, s4, 0
s_mov_b32 s10, 0
.p2align 6
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e64 v4, s10, 16
s_add_i32 s2, s4, s10
s_add_i32 s10, s10, 1
v_dual_mov_b32 v6, s2 :: v_dual_add_nc_u32 v5, 2, v4
v_add_nc_u32_e32 v4, 1, v4
s_clause 0x1
scratch_load_u8 v5, v5, off
scratch_load_u8 v4, v4, off
ds_load_u8 v6, v6 offset:1
s_waitcnt vmcnt(1)
v_cmp_eq_u16_e32 vcc_lo, 0, v5
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u16_e64 s2, v6, v4
v_cndmask_b32_e64 v2, v2, s8, vcc_lo
v_cndmask_b32_e64 v1, v1, s9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s7, s2, s7
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_13
s_or_b32 exec_lo, exec_lo, s7
s_branch .LBB0_10
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s5
s_branch .LBB0_17
.LBB0_16:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_17:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9my_strstrPcS_PS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 48
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9my_strstrPcS_PS_iii, .Lfunc_end0-_Z9my_strstrPcS_PS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym s_string
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9my_strstrPcS_PS_iii
.private_segment_fixed_size: 48
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: _Z9my_strstrPcS_PS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <sys/time.h>
void genRandomString(char *str,int length)
{
for(int i=0;i<length-1;++i)
{
str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
void genRandomSubString(char *str,int length,int sub_len)
{
for(int i=0;i<length-1;++i)
{
if(i>0 && ((i+1)%sub_len==0)) str[i] = '\0';
else str[i] = 'a' + rand()%26;
}
str[length-1] = '\0';
}
/*__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
char *sub = &sub_string[id*sub_len];
char *string = str;
char *a,*b;
b = sub;
printf("in GPU string is %s sub is %s\n",string,b);
for(;*string != '\0';++string){
a = string;
if(*a == *b){
printf("thread %d find a possible sub %s\n",id,b);
while(*(++a) == *(++b)){
printf("thread %d find a more and more possible sub %s\n",id,b);
if(*(b+1) == '\0'){
printf("thread %d find a sub %s\n",id,b);
position[id] = string;
printf("sting match in %s\n",position[id]);
}
}
}
b = sub;
}
}*/
char * my_strstr(char *str,char *sub,int str_len,int sub_len)
{
if(str_len < sub_len) return NULL;
if(str_len != 0 && sub_len == 0) return NULL;
if(str_len == 0 && sub_len == 0) return NULL;
int m, n;
for(int i=0;i<str_len;++i){
m = 0;
n = i;
if(str[n]==sub[m]){
while(str[++n] == sub[++m]){
if(sub[m+1] == '\0') return str+i;
}
}
}
return NULL;
}
__global__ void my_strstr(char *str,char *sub_string,char ** position,int str_len,int sub_len,int num_sub)
{
int id = threadIdx.x;
//char *sub = &sub_string[id*sub_len];
char *result = NULL;
char sub[24];
//load sub in register,great improve
for(int i=0;i<sub_len;++i){
sub[i] = sub_string[id*sub_len+i];}
//best case using Shared memory
extern __shared__ char s_string[];
//every thread has to fetch how many values from global memory to shared memory
int each_num = str_len/blockDim.x;
for(int i=0;i<each_num;++i){
s_string[i*blockDim.x+id] = str[i*blockDim.x+id];}
if( ((each_num*blockDim.x+id) < str_len) && (blockDim.x > each_num) )
s_string[each_num*blockDim.x+id] = str[each_num*blockDim.x+id];
char *string = s_string;
char *a,*b;
//b point to the sub address in register rather than in global memory
b = sub;
//result == NULL to judge if we find a match;rather than use goto or break in loop which harm the calculation
for(int i = 0;(*string != '\0')&&(result == NULL);i++){
//printf("i am %d\n",id);
a = string;
while(*a++ == *b++){
if(*(b+1) == '\0'){
result = string;
}
}
b = sub;
++string;
}
//coalesced global memory store, no effect since we only store once
position[id] = result;
}
int main()
{
int LENGTH = 4096, len = 24, num_sub = 100;
int num_block,num_thread;
if(num_sub < 512){
num_block = 1;
num_thread = num_sub;
}
else{
num_block = num_sub / 512;
num_thread = 512;
}
char haystack[LENGTH];
char subs[num_sub*len];
char *position[num_sub];
char *h_position[num_sub];
genRandomString(haystack,LENGTH);
genRandomSubString(subs,len*num_sub,len);
char *d_string,*d_subs;
char **d_position;
hipMalloc((void**)&d_string,sizeof(char)*LENGTH);
hipMalloc((void**)&d_subs,sizeof(char)*num_sub*len);
hipMalloc((void***)&d_position,sizeof(char*)*num_sub);
hipMemset(d_position,0,sizeof(char*)*num_sub);
memset(h_position,0,sizeof(char*)*num_sub);
const size_t smem = sizeof(char)*LENGTH;
char h_subs[num_sub][len];
for(int i=0;i<num_sub;++i){
for(int j=0;j<len;++j){
h_subs[i][j] = subs[i*len+j];
}
}
/*CPU*/
char *ret;
struct timeval start,end;
gettimeofday(&start, NULL );
for(int i=0;i<num_sub;++i)
{
ret = my_strstr(haystack,h_subs[i],LENGTH,len);
if(ret != NULL){
printf("find one sub string in %d sub\n",i);
printf("%s\n",ret);
}
position[i] = ret;
}
gettimeofday(&end, NULL );
float timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("CPU time=%f\n",timeuse /1000.0);
/*GPU*/
gettimeofday(&start, NULL );
for(int i=0;i<50;++i)
{
hipMemcpy(d_string,haystack,sizeof(char)*LENGTH,hipMemcpyHostToDevice);
hipMemcpy(d_subs,subs,sizeof(char)*num_sub*len,hipMemcpyHostToDevice);
my_strstr<<<num_block,num_thread,smem>>>(d_string,d_subs,d_position,LENGTH,len,num_sub);
hipDeviceSynchronize();
hipMemcpy(h_position,d_position,sizeof(char*)*num_sub,hipMemcpyDeviceToHost);
}
gettimeofday(&end, NULL );
timeuse =1000000 * ( end.tv_sec - start.tv_sec ) + end.tv_usec - start.tv_usec;
printf("GPU time=%f\n",timeuse /1000.0/50);
/*check*/
//in small size GPU works well
/*for(int i=0;i<num_sub;++i){
if(h_position[i] == position[i]){
printf("ok in %d sub\n",i);
if(position[i] != NULL){
printf("%s\n",position[i]);
}
}
else{
printf("error !!!!!!");
if(position[i] != NULL){
printf("CPU find match %s\n",position[i]);}
//because h_position[i] point to the address in GPU , causing segment error
if(h_position[i] != NULL){
printf("GPU find match %s\n",h_position[i]);}
}
}*/
return(0);
} | .text
.file "v1_match.hip"
.globl _Z15genRandomStringPci # -- Begin function _Z15genRandomStringPci
.p2align 4, 0x90
.type _Z15genRandomStringPci,@function
_Z15genRandomStringPci: # @_Z15genRandomStringPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, %rbx
leal -1(%rsi), %ebp
cmpl $2, %esi
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
movb %al, (%rbx,%r15)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movslq %ebp, %rax
movb $0, (%rbx,%rax)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15genRandomStringPci, .Lfunc_end0-_Z15genRandomStringPci
.cfi_endproc
# -- End function
.globl _Z18genRandomSubStringPcii # -- Begin function _Z18genRandomSubStringPcii
.p2align 4, 0x90
.type _Z18genRandomSubStringPcii,@function
_Z18genRandomSubStringPcii: # @_Z18genRandomSubStringPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, %rbx
leal -1(%rsi), %r14d
cmpl $2, %esi
jl .LBB1_7
# %bb.1: # %.lr.ph.preheader
movl %edx, %ebp
movl %r14d, %r15d
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
shrq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
.LBB1_6: # in Loop: Header=BB1_2 Depth=1
movb %al, (%rbx,%r12)
incq %r12
cmpq %r12, %r15
je .LBB1_7
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testq %r12, %r12
je .LBB1_5
# %bb.3: # in Loop: Header=BB1_2 Depth=1
leal 1(%r12), %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
xorl %eax, %eax
jmp .LBB1_6
.LBB1_7: # %._crit_edge
movslq %r14d, %rax
movb $0, (%rbx,%rax)
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18genRandomSubStringPcii, .Lfunc_end1-_Z18genRandomSubStringPcii
.cfi_endproc
# -- End function
.globl _Z9my_strstrPcS_ii # -- Begin function _Z9my_strstrPcS_ii
.p2align 4, 0x90
.type _Z9my_strstrPcS_ii,@function
_Z9my_strstrPcS_ii: # @_Z9my_strstrPcS_ii
.cfi_startproc
# %bb.0:
cmpl %ecx, %edx
jge .LBB2_3
# %bb.1:
xorl %eax, %eax
.LBB2_2: # %.loopexit35
retq
.LBB2_3:
testl %edx, %edx
setne %r8b
testl %ecx, %ecx
sete %r9b
xorl %eax, %eax
testl %edx, %edx
jle .LBB2_2
# %bb.4:
andb %r9b, %r8b
jne .LBB2_2
# %bb.5:
orl %edx, %ecx
je .LBB2_2
# %bb.6: # %.lr.ph
movzbl (%rsi), %ecx
movl %edx, %edx
xorl %eax, %eax
movq %rdi, %r9
xorl %r8d, %r8d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_12: # %.loopexit
# in Loop: Header=BB2_7 Depth=1
incq %r8
incq %r9
cmpq %rdx, %r8
je .LBB2_2
.LBB2_7: # =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
cmpb %cl, (%rdi,%r8)
jne .LBB2_12
# %bb.8: # %.preheader.preheader
# in Loop: Header=BB2_7 Depth=1
movl $1, %r10d
.p2align 4, 0x90
.LBB2_9: # %.preheader
# Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r9,%r10), %r11d
cmpb (%rsi,%r10), %r11b
jne .LBB2_12
# %bb.10: # in Loop: Header=BB2_9 Depth=2
cmpb $0, 1(%rsi,%r10)
leaq 1(%r10), %r10
jne .LBB2_9
# %bb.11: # %.loopexit33
addq %r8, %rdi
movq %rdi, %rax
retq
.Lfunc_end2:
.size _Z9my_strstrPcS_ii, .Lfunc_end2-_Z9my_strstrPcS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__my_strstrPcS_PS_iii # -- Begin function _Z24__device_stub__my_strstrPcS_PS_iii
.p2align 4, 0x90
.type _Z24__device_stub__my_strstrPcS_PS_iii,@function
_Z24__device_stub__my_strstrPcS_PS_iii: # @_Z24__device_stub__my_strstrPcS_PS_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9my_strstrPcS_PS_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z24__device_stub__my_strstrPcS_PS_iii, .Lfunc_end3-_Z24__device_stub__my_strstrPcS_PS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x408f400000000000 # double 1000
.LCPI4_1:
.quad 0x4049000000000000 # double 50
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $7496, %rsp # imm = 0x1D48
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
movb %al, -7536(%rbp,%rbx)
incq %rbx
cmpq $4095, %rbx # imm = 0xFFF
jne .LBB4_1
# %bb.2: # %_Z15genRandomStringPci.exit
movb $0, -3441(%rbp)
movl $1, %ebx
xorl %r14d, %r14d
movl $2863311531, %r15d # imm = 0xAAAAAAAB
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_6: # in Loop: Header=BB4_3 Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
shrq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
.LBB4_7: # in Loop: Header=BB4_3 Depth=1
movb %al, -3440(%rbp,%r14)
incq %r14
incl %ebx
cmpq $2399, %r14 # imm = 0x95F
je .LBB4_8
.LBB4_3: # %.lr.ph.i68
# =>This Inner Loop Header: Depth=1
testq %r14, %r14
je .LBB4_6
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $36, %rax
leal (%rax,%rax,2), %eax
leal -8(,%rax,8), %eax
orq $7, %rax
cmpl %r14d, %eax
jne .LBB4_6
# %bb.5: # in Loop: Header=BB4_3 Depth=1
xorl %eax, %eax
jmp .LBB4_7
.LBB4_8: # %_Z18genRandomSubStringPcii.exit
movb $0, -1041(%rbp)
leaq -112(%rbp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -104(%rbp), %rdi
movl $2400, %esi # imm = 0x960
callq hipMalloc
leaq -48(%rbp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq -48(%rbp), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq hipMemset
leaq -1040(%rbp), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq memset@PLT
movq %rsp, %r12
leaq -2400(%r12), %rbx
movq %rbx, %rsp
leaq -3440(%rbp), %rsi
movl $2400, %edx # imm = 0x960
movq %rbx, %rdi
callq memcpy@PLT
leaq -96(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
addq $-2399, %r12 # imm = 0xF6A1
leaq -7536(%rbp), %r13
xorl %r14d, %r14d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_19: # in Loop: Header=BB4_9 Depth=1
incq %r14
addq $24, %r12
cmpq $100, %r14
je .LBB4_20
.LBB4_9: # =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
# Child Loop BB4_12 Depth 3
leaq (%r14,%r14,2), %rax
movzbl (%rbx,%rax,8), %eax
movq %r13, %rdx
xorl %ecx, %ecx
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_15: # %.loopexit.i
# in Loop: Header=BB4_10 Depth=2
incq %rcx
incq %rdx
cmpq $4096, %rcx # imm = 0x1000
je .LBB4_16
.LBB4_10: # Parent Loop BB4_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_12 Depth 3
cmpb %al, -7536(%rbp,%rcx)
jne .LBB4_15
# %bb.11: # %.preheader.i.preheader
# in Loop: Header=BB4_10 Depth=2
movl $1, %esi
.p2align 4, 0x90
.LBB4_12: # %.preheader.i
# Parent Loop BB4_9 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%rdx,%rsi), %edi
cmpb -1(%r12,%rsi), %dil
jne .LBB4_15
# %bb.13: # in Loop: Header=BB4_12 Depth=3
cmpb $0, (%r12,%rsi)
leaq 1(%rsi), %rsi
jne .LBB4_12
# %bb.14: # %_Z9my_strstrPcS_ii.exit.loopexit
# in Loop: Header=BB4_9 Depth=1
leaq (%rcx,%rbp), %r15
addq $-7536, %r15 # imm = 0xE290
testq %r15, %r15
je .LBB4_19
.LBB4_18: # in Loop: Header=BB4_9 Depth=1
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq puts@PLT
jmp .LBB4_19
.LBB4_16: # in Loop: Header=BB4_9 Depth=1
xorl %r15d, %r15d
testq %r15, %r15
jne .LBB4_18
jmp .LBB4_19
.LBB4_20:
movabsq $4294967297, %r12 # imm = 0x100000001
leaq -80(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq -72(%rbp), %rax
subq -88(%rbp), %rax
cvtsi2ss %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
leaq -96(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $50, %ebx
leaq -3440(%rbp), %r15
movq %r12, %r14
addq $99, %r12
leaq -1040(%rbp), %r13
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_23: # in Loop: Header=BB4_21 Depth=1
callq hipDeviceSynchronize
movq -48(%rbp), %rsi
movl $800, %edx # imm = 0x320
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
decl %ebx
je .LBB4_24
.LBB4_21: # =>This Inner Loop Header: Depth=1
movq -112(%rbp), %rdi
movl $4096, %edx # imm = 0x1000
leaq -7536(%rbp), %rsi
movl $1, %ecx
callq hipMemcpy
movq -104(%rbp), %rdi
movl $2400, %edx # imm = 0x960
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4096, %r8d # imm = 0x1000
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22: # in Loop: Header=BB4_21 Depth=1
movq -112(%rbp), %rax
movq -104(%rbp), %rcx
movq -48(%rbp), %rdx
movq %rax, -184(%rbp)
movq %rcx, -176(%rbp)
movq %rdx, -168(%rbp)
movl $4096, -60(%rbp) # imm = 0x1000
movl $24, -56(%rbp)
movl $100, -52(%rbp)
leaq -184(%rbp), %rax
movq %rax, -240(%rbp)
leaq -176(%rbp), %rax
movq %rax, -232(%rbp)
leaq -168(%rbp), %rax
movq %rax, -224(%rbp)
leaq -60(%rbp), %rax
movq %rax, -216(%rbp)
leaq -56(%rbp), %rax
movq %rax, -208(%rbp)
leaq -52(%rbp), %rax
movq %rax, -200(%rbp)
leaq -160(%rbp), %rdi
leaq -144(%rbp), %rsi
leaq -128(%rbp), %rdx
leaq -120(%rbp), %rcx
callq __hipPopCallConfiguration
movq -160(%rbp), %rsi
movl -152(%rbp), %edx
movq -144(%rbp), %rcx
movl -136(%rbp), %r8d
movl $_Z9my_strstrPcS_PS_iii, %edi
leaq -240(%rbp), %r9
pushq -120(%rbp)
pushq -128(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB4_23
.LBB4_24:
leaq -80(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq -72(%rbp), %rax
subq -88(%rbp), %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_strstrPcS_PS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9my_strstrPcS_PS_iii,@object # @_Z9my_strstrPcS_PS_iii
.section .rodata,"a",@progbits
.globl _Z9my_strstrPcS_PS_iii
.p2align 3, 0x0
_Z9my_strstrPcS_PS_iii:
.quad _Z24__device_stub__my_strstrPcS_PS_iii
.size _Z9my_strstrPcS_PS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "find one sub string in %d sub\n"
.size .L.str, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU time=%f\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU time=%f\n"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_strstrPcS_PS_iii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_strstrPcS_PS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9my_strstrPcS_PS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00064c8b_00000000-6_v1_match.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15genRandomStringPci
.type _Z15genRandomStringPci, @function
_Z15genRandomStringPci:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movl %esi, %r12d
cmpl $1, %esi
jle .L4
movq %rdi, %rbx
leal -2(%rsi), %eax
leaq 1(%rdi,%rax), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %edx
subl %edx, %eax
addl $97, %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
movslq %r12d, %r12
movb $0, -1(%r13,%r12)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z15genRandomStringPci, .-_Z15genRandomStringPci
.globl _Z18genRandomSubStringPcii
.type _Z18genRandomSubStringPcii, @function
_Z18genRandomSubStringPcii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl %esi, %r14d
cmpl $1, %esi
jle .L9
movl %edx, %ebp
leal -1(%rsi), %r13d
movl $0, %ebx
movl $0, %r15d
jmp .L12
.L10:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %edx
subl %edx, %eax
addl $97, %eax
.L11:
movb %al, (%r12,%rbx)
addq $1, %rbx
cmpq %r13, %rbx
je .L9
.L12:
testl %ebx, %ebx
jle .L10
leal 1(%rbx), %eax
cltd
idivl %ebp
movl %r15d, %eax
testl %edx, %edx
je .L11
jmp .L10
.L9:
movslq %r14d, %r14
movb $0, -1(%r12,%r14)
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z18genRandomSubStringPcii, .-_Z18genRandomSubStringPcii
.globl _Z9my_strstrPcS_ii
.type _Z9my_strstrPcS_ii, @function
_Z9my_strstrPcS_ii:
.LFB2059:
.cfi_startproc
endbr64
cmpl %ecx, %edx
jl .L23
testl %edx, %edx
je .L28
movl $0, %r8d
testl %ecx, %ecx
je .L16
.L28:
orl %edx, %ecx
je .L25
testl %edx, %edx
jle .L26
movzbl (%rsi), %r9d
movl $0, %ecx
jmp .L22
.L20:
addl $1, %ecx
addq $1, %rdi
cmpl %ecx, %edx
je .L30
.L22:
movq %rdi, %r8
cmpb %r9b, (%rdi)
jne .L20
movl $1, %eax
.L19:
movzbl (%rsi,%rax), %r10d
cmpb %r10b, (%r8,%rax)
jne .L20
addq $1, %rax
cmpb $0, (%rsi,%rax)
jne .L19
.L16:
movq %r8, %rax
ret
.L30:
movl $0, %r8d
jmp .L16
.L23:
movl $0, %r8d
jmp .L16
.L25:
movl $0, %r8d
jmp .L16
.L26:
movl $0, %r8d
jmp .L16
.cfi_endproc
.LFE2059:
.size _Z9my_strstrPcS_ii, .-_Z9my_strstrPcS_ii
.globl _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
.type _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii, @function
_Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9my_strstrPcS_PS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii, .-_Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
.globl _Z9my_strstrPcS_PS_iii
.type _Z9my_strstrPcS_PS_iii, @function
_Z9my_strstrPcS_PS_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9my_strstrPcS_PS_iii, .-_Z9my_strstrPcS_PS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "find one sub string in %d sub\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s\n"
.LC3:
.string "CPU time=%f\n"
.LC5:
.string "GPU time=%f\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $120, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -4096(%rsp), %rax
.L40:
cmpq %rax, %rsp
je .L41
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L40
.L41:
movq %rsp, %r15
movq %rsp, %rax
.L43:
cmpq %rax, %rsp
je .L44
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L43
.L44:
subq $2400, %rsp
orq $0, 2392(%rsp)
movq %rsp, %r12
movq %rsp, %rax
.L46:
cmpq %rax, %rsp
je .L47
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L46
.L47:
subq $800, %rsp
orq $0, 792(%rsp)
movq %rsp, -152(%rbp)
movq %rsp, %rax
.L49:
cmpq %rax, %rsp
je .L50
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L49
.L50:
subq $800, %rsp
orq $0, 792(%rsp)
movq %rsp, %rbx
movq %rbx, -160(%rbp)
movl $4096, %esi
movq %r15, %rdi
call _Z15genRandomStringPci
movl $24, %edx
movl $2400, %esi
movq %r12, %rdi
call _Z18genRandomSubStringPcii
leaq -144(%rbp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq -136(%rbp), %rdi
movl $2400, %esi
call cudaMalloc@PLT
leaq -128(%rbp), %rdi
movl $800, %esi
call cudaMalloc@PLT
movl $800, %edx
movl $0, %esi
movq -128(%rbp), %rdi
call cudaMemset@PLT
movl $100, %ecx
movl $0, %eax
movq %rbx, %rdi
rep stosq
movq %rsp, %rax
.L52:
cmpq %rax, %rsp
je .L53
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L52
.L53:
subq $2400, %rsp
orq $0, 2392(%rsp)
movq %rsp, %rbx
movl $24, %ecx
movl $0, %esi
jmp .L55
.L67:
addq $24, %rsi
addq $24, %rcx
cmpq $2424, %rcx
je .L57
.L55:
movq %rsi, %rax
.L56:
movzbl (%r12,%rax), %edx
movb %dl, (%rbx,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L56
jmp .L67
.L57:
leaq -96(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %r14d
jmp .L59
.L58:
movq -152(%rbp), %rax
movq %r13, (%rax,%r14,8)
addq $1, %r14
addq $24, %rbx
cmpq $100, %r14
je .L68
.L59:
movl $24, %ecx
movl $4096, %edx
movq %rbx, %rsi
movq %r15, %rdi
call _Z9my_strstrPcS_ii
movq %rax, %r13
testq %rax, %rax
je .L58
movl %r14d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L58
.L68:
leaq -80(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax
addq -72(%rbp), %rax
subq -88(%rbp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC2(%rip), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq -96(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $50, %ebx
jmp .L61
.L60:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $800, %edx
movq -128(%rbp), %rsi
movq -160(%rbp), %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L69
.L61:
movl $1, %ecx
movl $4096, %edx
movq %r15, %rsi
movq -144(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2400, %edx
movq %r12, %rsi
movq -136(%rbp), %rdi
call cudaMemcpy@PLT
movl $100, -108(%rbp)
movl $1, -104(%rbp)
movl $1, -120(%rbp)
movl $1, -116(%rbp)
movl $0, %r9d
movl $4096, %r8d
movq -108(%rbp), %rdx
movl $1, %ecx
movq -120(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L60
movl $100, %r9d
movl $24, %r8d
movl $4096, %ecx
movq -128(%rbp), %rdx
movq -136(%rbp), %rsi
movq -144(%rbp), %rdi
call _Z36__device_stub__Z9my_strstrPcS_PS_iiiPcS_PS_iii
jmp .L60
.L69:
leaq -80(%rbp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax
addq -72(%rbp), %rax
subq -88(%rbp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC2(%rip), %xmm0
divsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L70:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9my_strstrPcS_PS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_strstrPcS_PS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1083129856
.align 8
.LC4:
.long 0
.long 1078525952
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "v1_match.hip"
.globl _Z15genRandomStringPci # -- Begin function _Z15genRandomStringPci
.p2align 4, 0x90
.type _Z15genRandomStringPci,@function
_Z15genRandomStringPci: # @_Z15genRandomStringPci
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, %rbx
leal -1(%rsi), %ebp
cmpl $2, %esi
jl .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
movb %al, (%rbx,%r15)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movslq %ebp, %rax
movb $0, (%rbx,%rax)
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15genRandomStringPci, .Lfunc_end0-_Z15genRandomStringPci
.cfi_endproc
# -- End function
.globl _Z18genRandomSubStringPcii # -- Begin function _Z18genRandomSubStringPcii
.p2align 4, 0x90
.type _Z18genRandomSubStringPcii,@function
_Z18genRandomSubStringPcii: # @_Z18genRandomSubStringPcii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $esi killed $esi def $rsi
movq %rdi, %rbx
leal -1(%rsi), %r14d
cmpl $2, %esi
jl .LBB1_7
# %bb.1: # %.lr.ph.preheader
movl %edx, %ebp
movl %r14d, %r15d
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
shrq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
.LBB1_6: # in Loop: Header=BB1_2 Depth=1
movb %al, (%rbx,%r12)
incq %r12
cmpq %r12, %r15
je .LBB1_7
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testq %r12, %r12
je .LBB1_5
# %bb.3: # in Loop: Header=BB1_2 Depth=1
leal 1(%r12), %eax
cltd
idivl %ebp
testl %edx, %edx
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
xorl %eax, %eax
jmp .LBB1_6
.LBB1_7: # %._crit_edge
movslq %r14d, %rax
movb $0, (%rbx,%rax)
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18genRandomSubStringPcii, .Lfunc_end1-_Z18genRandomSubStringPcii
.cfi_endproc
# -- End function
.globl _Z9my_strstrPcS_ii # -- Begin function _Z9my_strstrPcS_ii
.p2align 4, 0x90
.type _Z9my_strstrPcS_ii,@function
_Z9my_strstrPcS_ii: # @_Z9my_strstrPcS_ii
.cfi_startproc
# %bb.0:
cmpl %ecx, %edx
jge .LBB2_3
# %bb.1:
xorl %eax, %eax
.LBB2_2: # %.loopexit35
retq
.LBB2_3:
testl %edx, %edx
setne %r8b
testl %ecx, %ecx
sete %r9b
xorl %eax, %eax
testl %edx, %edx
jle .LBB2_2
# %bb.4:
andb %r9b, %r8b
jne .LBB2_2
# %bb.5:
orl %edx, %ecx
je .LBB2_2
# %bb.6: # %.lr.ph
movzbl (%rsi), %ecx
movl %edx, %edx
xorl %eax, %eax
movq %rdi, %r9
xorl %r8d, %r8d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_12: # %.loopexit
# in Loop: Header=BB2_7 Depth=1
incq %r8
incq %r9
cmpq %rdx, %r8
je .LBB2_2
.LBB2_7: # =>This Loop Header: Depth=1
# Child Loop BB2_9 Depth 2
cmpb %cl, (%rdi,%r8)
jne .LBB2_12
# %bb.8: # %.preheader.preheader
# in Loop: Header=BB2_7 Depth=1
movl $1, %r10d
.p2align 4, 0x90
.LBB2_9: # %.preheader
# Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r9,%r10), %r11d
cmpb (%rsi,%r10), %r11b
jne .LBB2_12
# %bb.10: # in Loop: Header=BB2_9 Depth=2
cmpb $0, 1(%rsi,%r10)
leaq 1(%r10), %r10
jne .LBB2_9
# %bb.11: # %.loopexit33
addq %r8, %rdi
movq %rdi, %rax
retq
.Lfunc_end2:
.size _Z9my_strstrPcS_ii, .Lfunc_end2-_Z9my_strstrPcS_ii
.cfi_endproc
# -- End function
.globl _Z24__device_stub__my_strstrPcS_PS_iii # -- Begin function _Z24__device_stub__my_strstrPcS_PS_iii
.p2align 4, 0x90
.type _Z24__device_stub__my_strstrPcS_PS_iii,@function
_Z24__device_stub__my_strstrPcS_PS_iii: # @_Z24__device_stub__my_strstrPcS_PS_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9my_strstrPcS_PS_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z24__device_stub__my_strstrPcS_PS_iii, .Lfunc_end3-_Z24__device_stub__my_strstrPcS_PS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x408f400000000000 # double 1000
.LCPI4_1:
.quad 0x4049000000000000 # double 50
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $7496, %rsp # imm = 0x1D48
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
sarq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
movb %al, -7536(%rbp,%rbx)
incq %rbx
cmpq $4095, %rbx # imm = 0xFFF
jne .LBB4_1
# %bb.2: # %_Z15genRandomStringPci.exit
movb $0, -3441(%rbp)
movl $1, %ebx
xorl %r14d, %r14d
movl $2863311531, %r15d # imm = 0xAAAAAAAB
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_6: # in Loop: Header=BB4_3 Depth=1
callq rand
cltq
imulq $1321528399, %rax, %rcx # imm = 0x4EC4EC4F
movq %rcx, %rdx
shrq $63, %rdx
shrq $35, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rdx,%rdx,4), %edx
addl %ecx, %edx
subl %edx, %eax
addb $97, %al
.LBB4_7: # in Loop: Header=BB4_3 Depth=1
movb %al, -3440(%rbp,%r14)
incq %r14
incl %ebx
cmpq $2399, %r14 # imm = 0x95F
je .LBB4_8
.LBB4_3: # %.lr.ph.i68
# =>This Inner Loop Header: Depth=1
testq %r14, %r14
je .LBB4_6
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movl %ebx, %eax
imulq %r15, %rax
shrq $36, %rax
leal (%rax,%rax,2), %eax
leal -8(,%rax,8), %eax
orq $7, %rax
cmpl %r14d, %eax
jne .LBB4_6
# %bb.5: # in Loop: Header=BB4_3 Depth=1
xorl %eax, %eax
jmp .LBB4_7
.LBB4_8: # %_Z18genRandomSubStringPcii.exit
movb $0, -1041(%rbp)
leaq -112(%rbp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq -104(%rbp), %rdi
movl $2400, %esi # imm = 0x960
callq hipMalloc
leaq -48(%rbp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq -48(%rbp), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq hipMemset
leaq -1040(%rbp), %rdi
movl $800, %edx # imm = 0x320
xorl %esi, %esi
callq memset@PLT
movq %rsp, %r12
leaq -2400(%r12), %rbx
movq %rbx, %rsp
leaq -3440(%rbp), %rsi
movl $2400, %edx # imm = 0x960
movq %rbx, %rdi
callq memcpy@PLT
leaq -96(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
addq $-2399, %r12 # imm = 0xF6A1
leaq -7536(%rbp), %r13
xorl %r14d, %r14d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_19: # in Loop: Header=BB4_9 Depth=1
incq %r14
addq $24, %r12
cmpq $100, %r14
je .LBB4_20
.LBB4_9: # =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
# Child Loop BB4_12 Depth 3
leaq (%r14,%r14,2), %rax
movzbl (%rbx,%rax,8), %eax
movq %r13, %rdx
xorl %ecx, %ecx
jmp .LBB4_10
.p2align 4, 0x90
.LBB4_15: # %.loopexit.i
# in Loop: Header=BB4_10 Depth=2
incq %rcx
incq %rdx
cmpq $4096, %rcx # imm = 0x1000
je .LBB4_16
.LBB4_10: # Parent Loop BB4_9 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_12 Depth 3
cmpb %al, -7536(%rbp,%rcx)
jne .LBB4_15
# %bb.11: # %.preheader.i.preheader
# in Loop: Header=BB4_10 Depth=2
movl $1, %esi
.p2align 4, 0x90
.LBB4_12: # %.preheader.i
# Parent Loop BB4_9 Depth=1
# Parent Loop BB4_10 Depth=2
# => This Inner Loop Header: Depth=3
movzbl (%rdx,%rsi), %edi
cmpb -1(%r12,%rsi), %dil
jne .LBB4_15
# %bb.13: # in Loop: Header=BB4_12 Depth=3
cmpb $0, (%r12,%rsi)
leaq 1(%rsi), %rsi
jne .LBB4_12
# %bb.14: # %_Z9my_strstrPcS_ii.exit.loopexit
# in Loop: Header=BB4_9 Depth=1
leaq (%rcx,%rbp), %r15
addq $-7536, %r15 # imm = 0xE290
testq %r15, %r15
je .LBB4_19
.LBB4_18: # in Loop: Header=BB4_9 Depth=1
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq puts@PLT
jmp .LBB4_19
.LBB4_16: # in Loop: Header=BB4_9 Depth=1
xorl %r15d, %r15d
testq %r15, %r15
jne .LBB4_18
jmp .LBB4_19
.LBB4_20:
movabsq $4294967297, %r12 # imm = 0x100000001
leaq -80(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq -72(%rbp), %rax
subq -88(%rbp), %rax
cvtsi2ss %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
leaq -96(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $50, %ebx
leaq -3440(%rbp), %r15
movq %r12, %r14
addq $99, %r12
leaq -1040(%rbp), %r13
jmp .LBB4_21
.p2align 4, 0x90
.LBB4_23: # in Loop: Header=BB4_21 Depth=1
callq hipDeviceSynchronize
movq -48(%rbp), %rsi
movl $800, %edx # imm = 0x320
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
decl %ebx
je .LBB4_24
.LBB4_21: # =>This Inner Loop Header: Depth=1
movq -112(%rbp), %rdi
movl $4096, %edx # imm = 0x1000
leaq -7536(%rbp), %rsi
movl $1, %ecx
callq hipMemcpy
movq -104(%rbp), %rdi
movl $2400, %edx # imm = 0x960
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $4096, %r8d # imm = 0x1000
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22: # in Loop: Header=BB4_21 Depth=1
movq -112(%rbp), %rax
movq -104(%rbp), %rcx
movq -48(%rbp), %rdx
movq %rax, -184(%rbp)
movq %rcx, -176(%rbp)
movq %rdx, -168(%rbp)
movl $4096, -60(%rbp) # imm = 0x1000
movl $24, -56(%rbp)
movl $100, -52(%rbp)
leaq -184(%rbp), %rax
movq %rax, -240(%rbp)
leaq -176(%rbp), %rax
movq %rax, -232(%rbp)
leaq -168(%rbp), %rax
movq %rax, -224(%rbp)
leaq -60(%rbp), %rax
movq %rax, -216(%rbp)
leaq -56(%rbp), %rax
movq %rax, -208(%rbp)
leaq -52(%rbp), %rax
movq %rax, -200(%rbp)
leaq -160(%rbp), %rdi
leaq -144(%rbp), %rsi
leaq -128(%rbp), %rdx
leaq -120(%rbp), %rcx
callq __hipPopCallConfiguration
movq -160(%rbp), %rsi
movl -152(%rbp), %edx
movq -144(%rbp), %rcx
movl -136(%rbp), %r8d
movl $_Z9my_strstrPcS_PS_iii, %edi
leaq -240(%rbp), %r9
pushq -120(%rbp)
pushq -128(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB4_23
.LBB4_24:
leaq -80(%rbp), %rdi
xorl %esi, %esi
callq gettimeofday
movq -80(%rbp), %rax
subq -96(%rbp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
addq -72(%rbp), %rax
subq -88(%rbp), %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_0(%rip), %xmm0
divsd .LCPI4_1(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_strstrPcS_PS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9my_strstrPcS_PS_iii,@object # @_Z9my_strstrPcS_PS_iii
.section .rodata,"a",@progbits
.globl _Z9my_strstrPcS_PS_iii
.p2align 3, 0x0
_Z9my_strstrPcS_PS_iii:
.quad _Z24__device_stub__my_strstrPcS_PS_iii
.size _Z9my_strstrPcS_PS_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "find one sub string in %d sub\n"
.size .L.str, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CPU time=%f\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU time=%f\n"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_strstrPcS_PS_iii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_strstrPcS_PS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9my_strstrPcS_PS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
/* experiment with N */
/* how large can it be? */
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void vector_add(int *a, int *b, int *c)
{
/* insert code to calculate the index properly using blockIdx.x, blockDim.x, threadIdx.x */
int index = int(blockIdx.x) * int(blockDim.x) + int(threadIdx.x);
//printf("block dim:%d,%d,blockid:%d,threadidx.x:%d\n",blockDim.x,blockDim.y,blockIdx.x,threadIdx.x);
//printf("index:%d\n",index);
c[index] = a[index] + b[index];
if(index >= N - 1)
{
printf("%d\n",index);
printf("%d,%d,%d\n",a[index],b[index],c[index]);
}
}
int main()
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof( int );
/* allocate space for device copies of a, b, c */
cudaMalloc( (void **) &d_a, size );
cudaMalloc( (void **) &d_b, size );
cudaMalloc( (void **) &d_c, size );
/* allocate space for host copies of a, b, c and setup input values */
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for( int i = 0; i < N; i++ )
{
a[i] = b[i] = i;
c[i] = 0;
}
/* copy inputs to device */
/* fix the parameters needed to copy data to the device */
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
/* launch the kernel on the GPU */
/* insert the launch parameters to launch the kernel properly using blocks and threads */
vector_add<<< N/THREADS_PER_BLOCK, THREADS_PER_BLOCK >>>( d_a, d_b, d_c );
/* copy result back to host */
/* fix the parameters needed to copy data back to the host */
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
printf( "c[0] = %d\n",c[0] );
printf( "c[%d] = %d\n",N-1, c[N-1] );
/* clean up */
{
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr != cudaSuccess)
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
}
free(a);
free(b);
free(c);
cudaFree( d_a );
cudaFree( d_b );
cudaFree( d_c );
return 0;
} /* end main */ | code for sm_80
Function : _Z10vector_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD.WIDE R18, R0, R17, c[0x0][0x168] ; /* 0x00005a0000127625 */
/* 0x000fc800078e0211 */
/*0080*/ IMAD.WIDE R22, R0.reuse, R17.reuse, c[0x0][0x160] ; /* 0x0000580000167625 */
/* 0x0c0fe200078e0211 */
/*0090*/ LDG.E R2, [R18.64] ; /* 0x0000002412027981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R3, [R22.64] ; /* 0x0000002416037981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ ISETP.GE.AND P0, PT, R0.reuse, 0x3fffff, PT ; /* 0x003fffff0000780c */
/* 0x040fe20003f06270 */
/*00c0*/ IMAD.WIDE R16, R0, R17, c[0x0][0x170] ; /* 0x00005c0000107625 */
/* 0x000fe200078e0211 */
/*00d0*/ IADD3 R24, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001187a10 */
/* 0x000fc60007f3e0ff */
/*00e0*/ IMAD.IADD R3, R2, 0x1, R3 ; /* 0x0000000102037824 */
/* 0x004fca00078e0203 */
/*00f0*/ STG.E [R16.64], R3 ; /* 0x0000000310007986 */
/* 0x0001e6000c101924 */
/*0100*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0110*/ MOV R25, 0x0 ; /* 0x0000000000197802 */
/* 0x000fe20000000f00 */
/*0120*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100800 */
/*0130*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff027624 */
/* 0x000fe400008e06ff */
/*0140*/ LDC.64 R8, c[0x4][R25] ; /* 0x0100000019087b82 */
/* 0x0002a20000000a00 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0018 */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0190*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fca0000000000 */
/*01a0*/ MOV R3, 0x210 ; /* 0x0000021000037802 */
/* 0x001fe40000000f00 */
/*01b0*/ MOV R20, 0x190 ; /* 0x0000019000147802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*01e0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01f0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0200*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0210*/ LDG.E R10, [R22.64] ; /* 0x00000024160a7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R11, [R18.64] ; /* 0x00000024120b7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R16, [R16.64] ; /* 0x0000002410107981 */
/* 0x000ee2000c1e1900 */
/*0240*/ LDC.64 R8, c[0x4][R25] ; /* 0x0100000019087b82 */
/* 0x0000620000000a00 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0018 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0270*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0290*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0041e80000100a00 */
/*02a0*/ STL [R1+0x8], R16 ; /* 0x0000081001007387 */
/* 0x0081e40000100800 */
/*02b0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe40000000000 */
/*02c0*/ MOV R11, 0x330 ; /* 0x00000330000b7802 */
/* 0x001fe40000000f00 */
/*02d0*/ MOV R20, 0x2b0 ; /* 0x000002b000147802 */
/* 0x000fc40000000f00 */
/*02e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0300*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0310*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0320*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0330*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
/* experiment with N */
/* how large can it be? */
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void vector_add(int *a, int *b, int *c)
{
/* insert code to calculate the index properly using blockIdx.x, blockDim.x, threadIdx.x */
int index = int(blockIdx.x) * int(blockDim.x) + int(threadIdx.x);
//printf("block dim:%d,%d,blockid:%d,threadidx.x:%d\n",blockDim.x,blockDim.y,blockIdx.x,threadIdx.x);
//printf("index:%d\n",index);
c[index] = a[index] + b[index];
if(index >= N - 1)
{
printf("%d\n",index);
printf("%d,%d,%d\n",a[index],b[index],c[index]);
}
}
int main()
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof( int );
/* allocate space for device copies of a, b, c */
cudaMalloc( (void **) &d_a, size );
cudaMalloc( (void **) &d_b, size );
cudaMalloc( (void **) &d_c, size );
/* allocate space for host copies of a, b, c and setup input values */
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for( int i = 0; i < N; i++ )
{
a[i] = b[i] = i;
c[i] = 0;
}
/* copy inputs to device */
/* fix the parameters needed to copy data to the device */
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
/* launch the kernel on the GPU */
/* insert the launch parameters to launch the kernel properly using blocks and threads */
vector_add<<< N/THREADS_PER_BLOCK, THREADS_PER_BLOCK >>>( d_a, d_b, d_c );
/* copy result back to host */
/* fix the parameters needed to copy data back to the host */
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
printf( "c[0] = %d\n",c[0] );
printf( "c[%d] = %d\n",N-1, c[N-1] );
/* clean up */
{
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr != cudaSuccess)
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
}
free(a);
free(b);
free(c);
cudaFree( d_a );
cudaFree( d_b );
cudaFree( d_c );
return 0;
} /* end main */ | .file "tmpxft_00122e7f_00000000-6_addVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.type _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, @function
_Z34__device_stub__Z10vector_addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, .-_Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.globl _Z10vector_addPiS_S_
.type _Z10vector_addPiS_S_, @function
_Z10vector_addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPiS_S_, .-_Z10vector_addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[0] = %d\n"
.LC1:
.string "c[%d] = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "kernel launch failed with error \"%s\".\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%r12,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16777212(%rbx), %ecx
movl $4194303, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L19
.L14:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
jmp .L13
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
/* experiment with N */
/* how large can it be? */
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void vector_add(int *a, int *b, int *c)
{
/* insert code to calculate the index properly using blockIdx.x, blockDim.x, threadIdx.x */
int index = int(blockIdx.x) * int(blockDim.x) + int(threadIdx.x);
//printf("block dim:%d,%d,blockid:%d,threadidx.x:%d\n",blockDim.x,blockDim.y,blockIdx.x,threadIdx.x);
//printf("index:%d\n",index);
c[index] = a[index] + b[index];
if(index >= N - 1)
{
printf("%d\n",index);
printf("%d,%d,%d\n",a[index],b[index],c[index]);
}
}
int main()
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof( int );
/* allocate space for device copies of a, b, c */
cudaMalloc( (void **) &d_a, size );
cudaMalloc( (void **) &d_b, size );
cudaMalloc( (void **) &d_c, size );
/* allocate space for host copies of a, b, c and setup input values */
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for( int i = 0; i < N; i++ )
{
a[i] = b[i] = i;
c[i] = 0;
}
/* copy inputs to device */
/* fix the parameters needed to copy data to the device */
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
/* launch the kernel on the GPU */
/* insert the launch parameters to launch the kernel properly using blocks and threads */
vector_add<<< N/THREADS_PER_BLOCK, THREADS_PER_BLOCK >>>( d_a, d_b, d_c );
/* copy result back to host */
/* fix the parameters needed to copy data back to the host */
cudaMemcpy(c,d_c,size,cudaMemcpyDeviceToHost);
printf( "c[0] = %d\n",c[0] );
printf( "c[%d] = %d\n",N-1, c[N-1] );
/* clean up */
{
cudaError_t cudaerr = cudaDeviceSynchronize();
if (cudaerr != cudaSuccess)
printf("kernel launch failed with error \"%s\".\n",
cudaGetErrorString(cudaerr));
}
free(a);
free(b);
free(c);
cudaFree( d_a );
cudaFree( d_b );
cudaFree( d_c );
return 0;
} /* end main */ | #include <hip/hip_runtime.h>
#include <stdio.h>
/* experiment with N */
/* how large can it be? */
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void vector_add(int *a, int *b, int *c)
{
/* insert code to calculate the index properly using blockIdx.x, blockDim.x, threadIdx.x */
int index = int(blockIdx.x) * int(blockDim.x) + int(threadIdx.x);
//printf("block dim:%d,%d,blockid:%d,threadidx.x:%d\n",blockDim.x,blockDim.y,blockIdx.x,threadIdx.x);
//printf("index:%d\n",index);
c[index] = a[index] + b[index];
if(index >= N - 1)
{
printf("%d\n",index);
printf("%d,%d,%d\n",a[index],b[index],c[index]);
}
}
int main()
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof( int );
/* allocate space for device copies of a, b, c */
hipMalloc( (void **) &d_a, size );
hipMalloc( (void **) &d_b, size );
hipMalloc( (void **) &d_c, size );
/* allocate space for host copies of a, b, c and setup input values */
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for( int i = 0; i < N; i++ )
{
a[i] = b[i] = i;
c[i] = 0;
}
/* copy inputs to device */
/* fix the parameters needed to copy data to the device */
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
/* launch the kernel on the GPU */
/* insert the launch parameters to launch the kernel properly using blocks and threads */
vector_add<<< N/THREADS_PER_BLOCK, THREADS_PER_BLOCK >>>( d_a, d_b, d_c );
/* copy result back to host */
/* fix the parameters needed to copy data back to the host */
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
printf( "c[0] = %d\n",c[0] );
printf( "c[%d] = %d\n",N-1, c[N-1] );
/* clean up */
{
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr != hipSuccess)
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
}
free(a);
free(b);
free(c);
hipFree( d_a );
hipFree( d_b );
hipFree( d_c );
return 0;
} /* end main */ |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
/* experiment with N */
/* how large can it be? */
#define N (2048*2048)
#define THREADS_PER_BLOCK 512
__global__ void vector_add(int *a, int *b, int *c)
{
/* insert code to calculate the index properly using blockIdx.x, blockDim.x, threadIdx.x */
int index = int(blockIdx.x) * int(blockDim.x) + int(threadIdx.x);
//printf("block dim:%d,%d,blockid:%d,threadidx.x:%d\n",blockDim.x,blockDim.y,blockIdx.x,threadIdx.x);
//printf("index:%d\n",index);
c[index] = a[index] + b[index];
if(index >= N - 1)
{
printf("%d\n",index);
printf("%d,%d,%d\n",a[index],b[index],c[index]);
}
}
int main()
{
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof( int );
/* allocate space for device copies of a, b, c */
hipMalloc( (void **) &d_a, size );
hipMalloc( (void **) &d_b, size );
hipMalloc( (void **) &d_c, size );
/* allocate space for host copies of a, b, c and setup input values */
a = (int *)malloc( size );
b = (int *)malloc( size );
c = (int *)malloc( size );
for( int i = 0; i < N; i++ )
{
a[i] = b[i] = i;
c[i] = 0;
}
/* copy inputs to device */
/* fix the parameters needed to copy data to the device */
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
/* launch the kernel on the GPU */
/* insert the launch parameters to launch the kernel properly using blocks and threads */
vector_add<<< N/THREADS_PER_BLOCK, THREADS_PER_BLOCK >>>( d_a, d_b, d_c );
/* copy result back to host */
/* fix the parameters needed to copy data back to the host */
hipMemcpy(c,d_c,size,hipMemcpyDeviceToHost);
printf( "c[0] = %d\n",c[0] );
printf( "c[%d] = %d\n",N-1, c[N-1] );
/* clean up */
{
hipError_t cudaerr = hipDeviceSynchronize();
if (cudaerr != hipSuccess)
printf("kernel launch failed with error \"%s\".\n",
hipGetErrorString(cudaerr));
}
free(a);
free(b);
free(c);
hipFree( d_a );
hipFree( d_b );
hipFree( d_c );
return 0;
} /* end main */ | .text
.file "addVector.hip"
.globl _Z25__device_stub__vector_addPiS_S_ # -- Begin function _Z25__device_stub__vector_addPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPiS_S_,@function
_Z25__device_stub__vector_addPiS_S_: # @_Z25__device_stub__vector_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPiS_S_, .Lfunc_end0-_Z25__device_stub__vector_addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $16777216, %edx # imm = 0x1000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%r14,%r12,4)
movl %r12d, (%rbx,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 16777212(%r15), %edx
movl $.L.str.1, %edi
movl $4194303, %esi # imm = 0x3FFFFF
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPiS_S_,@object # @_Z10vector_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z10vector_addPiS_S_
.p2align 3, 0x0
_Z10vector_addPiS_S_:
.quad _Z25__device_stub__vector_addPiS_S_
.size _Z10vector_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[0] = %d\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "c[%d] = %d\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str.2, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122e7f_00000000-6_addVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.type _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, @function
_Z34__device_stub__Z10vector_addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10vector_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10vector_addPiS_S_PiS_S_, .-_Z34__device_stub__Z10vector_addPiS_S_PiS_S_
.globl _Z10vector_addPiS_S_
.type _Z10vector_addPiS_S_, @function
_Z10vector_addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10vector_addPiS_S_, .-_Z10vector_addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[0] = %d\n"
.LC1:
.string "c[%d] = %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "kernel launch failed with error \"%s\".\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%r12,%rax,4)
movl $0, (%rbx,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16777212(%rbx), %ecx
movl $4194303, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L19
.L14:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10vector_addPiS_S_PiS_S_
jmp .L13
.L19:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10vector_addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10vector_addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addVector.hip"
.globl _Z25__device_stub__vector_addPiS_S_ # -- Begin function _Z25__device_stub__vector_addPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__vector_addPiS_S_,@function
_Z25__device_stub__vector_addPiS_S_: # @_Z25__device_stub__vector_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__vector_addPiS_S_, .Lfunc_end0-_Z25__device_stub__vector_addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $16777216, %edx # imm = 0x1000000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%r14,%r12,4)
movl %r12d, (%rbx,%r12,4)
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10vector_addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 16777212(%r15), %edx
movl $.L.str.1, %edi
movl $4194303, %esi # imm = 0x3FFFFF
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10vector_addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10vector_addPiS_S_,@object # @_Z10vector_addPiS_S_
.section .rodata,"a",@progbits
.globl _Z10vector_addPiS_S_
.p2align 3, 0x0
_Z10vector_addPiS_S_:
.quad _Z25__device_stub__vector_addPiS_S_
.size _Z10vector_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[0] = %d\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "c[%d] = %d\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel launch failed with error \"%s\".\n"
.size .L.str.2, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10vector_addPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__vector_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10vector_addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
//using namespace std;
//#typedef n 100
// Kernel Definition
__global__ void VecAddKernel(float *d_A, float *d_B, float *d_C, int n){
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) d_C[i]=d_A[i]+d_B[i];
}
void vecAdd(float *A, float *B, float *C, int n){
float *d_A, *d_B, *d_C;
int size=n*sizeof(float);
// Device Memory Allocation
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
// Host to Device data transfer
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
// Calling Kernel
VecAddKernel<<< ceil(n/16),16>>> (d_A,d_B,d_C,n);
cudaMemcpy(C,d_C,size,cudaMemcpyDeviceToHost);
}
int main(){
float *A, *B, *C;
int n;
printf("Enter the size of Vector");
scanf("%d",&n);
A = (float*)malloc(n*sizeof(float));
B = (float*)malloc(n*sizeof(float));
C = (float*)malloc(n*sizeof(float));
for(int i=0;i<n;i++){
A[i]=i;
B[i]=i*i;
}
vecAdd(A,B,C,n);
printf("The value of A+B .i.e C = \n{");
for(int i=0;i<n;i++){
printf("%f, ",C[i]);
}
printf("}\n");
return 0;
} | code for sm_80
Function : _Z12VecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
//using namespace std;
//#typedef n 100
// Kernel Definition
__global__ void VecAddKernel(float *d_A, float *d_B, float *d_C, int n){
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) d_C[i]=d_A[i]+d_B[i];
}
void vecAdd(float *A, float *B, float *C, int n){
float *d_A, *d_B, *d_C;
int size=n*sizeof(float);
// Device Memory Allocation
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
// Host to Device data transfer
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
// Calling Kernel
VecAddKernel<<< ceil(n/16),16>>> (d_A,d_B,d_C,n);
cudaMemcpy(C,d_C,size,cudaMemcpyDeviceToHost);
}
int main(){
float *A, *B, *C;
int n;
printf("Enter the size of Vector");
scanf("%d",&n);
A = (float*)malloc(n*sizeof(float));
B = (float*)malloc(n*sizeof(float));
C = (float*)malloc(n*sizeof(float));
for(int i=0;i<n;i++){
A[i]=i;
B[i]=i*i;
}
vecAdd(A,B,C,n);
printf("The value of A+B .i.e C = \n{");
for(int i=0;i<n;i++){
printf("%f, ",C[i]);
}
printf("}\n");
return 0;
} | .file "tmpxft_000c93a9_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12VecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
.globl _Z12VecAddKernelPfS_S_i
.type _Z12VecAddKernelPfS_S_i, @function
_Z12VecAddKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12VecAddKernelPfS_S_i, .-_Z12VecAddKernelPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $1, 48(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the size of Vector"
.LC1:
.string "%d"
.LC2:
.string "The value of A+B .i.e C = \n{"
.LC3:
.string "%f, "
.LC4:
.string "}\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %r14d
movslq %r14d, %r13
leaq 0(,%r13,4), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
testl %r14d, %r14d
jle .L18
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
movl %eax, %edx
imull %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq %rax, %r13
jne .L19
.L18:
movl %r14d, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z6vecAddPfS_S_i
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L20
movl $0, %ebx
leaq .LC3(%rip), %r12
.L21:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L21
.L20:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12VecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12VecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//using namespace std;
//#typedef n 100
// Kernel Definition
__global__ void VecAddKernel(float *d_A, float *d_B, float *d_C, int n){
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) d_C[i]=d_A[i]+d_B[i];
}
void vecAdd(float *A, float *B, float *C, int n){
float *d_A, *d_B, *d_C;
int size=n*sizeof(float);
// Device Memory Allocation
cudaMalloc((void**)&d_A, size);
cudaMalloc((void**)&d_B, size);
cudaMalloc((void**)&d_C, size);
// Host to Device data transfer
cudaMemcpy(d_A,A,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_B,B,size,cudaMemcpyHostToDevice);
// Calling Kernel
VecAddKernel<<< ceil(n/16),16>>> (d_A,d_B,d_C,n);
cudaMemcpy(C,d_C,size,cudaMemcpyDeviceToHost);
}
int main(){
float *A, *B, *C;
int n;
printf("Enter the size of Vector");
scanf("%d",&n);
A = (float*)malloc(n*sizeof(float));
B = (float*)malloc(n*sizeof(float));
C = (float*)malloc(n*sizeof(float));
for(int i=0;i<n;i++){
A[i]=i;
B[i]=i*i;
}
vecAdd(A,B,C,n);
printf("The value of A+B .i.e C = \n{");
for(int i=0;i<n;i++){
printf("%f, ",C[i]);
}
printf("}\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
//using namespace std;
//#typedef n 100
// Kernel Definition
__global__ void VecAddKernel(float *d_A, float *d_B, float *d_C, int n){
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) d_C[i]=d_A[i]+d_B[i];
}
void vecAdd(float *A, float *B, float *C, int n){
float *d_A, *d_B, *d_C;
int size=n*sizeof(float);
// Device Memory Allocation
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
// Host to Device data transfer
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
// Calling Kernel
VecAddKernel<<< ceil(n/16),16>>> (d_A,d_B,d_C,n);
hipMemcpy(C,d_C,size,hipMemcpyDeviceToHost);
}
int main(){
float *A, *B, *C;
int n;
printf("Enter the size of Vector");
scanf("%d",&n);
A = (float*)malloc(n*sizeof(float));
B = (float*)malloc(n*sizeof(float));
C = (float*)malloc(n*sizeof(float));
for(int i=0;i<n;i++){
A[i]=i;
B[i]=i*i;
}
vecAdd(A,B,C,n);
printf("The value of A+B .i.e C = \n{");
for(int i=0;i<n;i++){
printf("%f, ",C[i]);
}
printf("}\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//using namespace std;
//#typedef n 100
// Kernel Definition
__global__ void VecAddKernel(float *d_A, float *d_B, float *d_C, int n){
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) d_C[i]=d_A[i]+d_B[i];
}
void vecAdd(float *A, float *B, float *C, int n){
float *d_A, *d_B, *d_C;
int size=n*sizeof(float);
// Device Memory Allocation
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
// Host to Device data transfer
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
// Calling Kernel
VecAddKernel<<< ceil(n/16),16>>> (d_A,d_B,d_C,n);
hipMemcpy(C,d_C,size,hipMemcpyDeviceToHost);
}
int main(){
float *A, *B, *C;
int n;
printf("Enter the size of Vector");
scanf("%d",&n);
A = (float*)malloc(n*sizeof(float));
B = (float*)malloc(n*sizeof(float));
C = (float*)malloc(n*sizeof(float));
for(int i=0;i<n;i++){
A[i]=i;
B[i]=i*i;
}
vecAdd(A,B,C,n);
printf("The value of A+B .i.e C = \n{");
for(int i=0;i<n;i++){
printf("%f, ",C[i]);
}
printf("}\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12VecAddKernelPfS_S_i
.globl _Z12VecAddKernelPfS_S_i
.p2align 8
.type _Z12VecAddKernelPfS_S_i,@function
_Z12VecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12VecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12VecAddKernelPfS_S_i, .Lfunc_end0-_Z12VecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12VecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12VecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//using namespace std;
//#typedef n 100
// Kernel Definition
__global__ void VecAddKernel(float *d_A, float *d_B, float *d_C, int n){
int i=blockDim.x*blockIdx.x+threadIdx.x;
if(i<n) d_C[i]=d_A[i]+d_B[i];
}
void vecAdd(float *A, float *B, float *C, int n){
float *d_A, *d_B, *d_C;
int size=n*sizeof(float);
// Device Memory Allocation
hipMalloc((void**)&d_A, size);
hipMalloc((void**)&d_B, size);
hipMalloc((void**)&d_C, size);
// Host to Device data transfer
hipMemcpy(d_A,A,size,hipMemcpyHostToDevice);
hipMemcpy(d_B,B,size,hipMemcpyHostToDevice);
// Calling Kernel
VecAddKernel<<< ceil(n/16),16>>> (d_A,d_B,d_C,n);
hipMemcpy(C,d_C,size,hipMemcpyDeviceToHost);
}
int main(){
float *A, *B, *C;
int n;
printf("Enter the size of Vector");
scanf("%d",&n);
A = (float*)malloc(n*sizeof(float));
B = (float*)malloc(n*sizeof(float));
C = (float*)malloc(n*sizeof(float));
for(int i=0;i<n;i++){
A[i]=i;
B[i]=i*i;
}
vecAdd(A,B,C,n);
printf("The value of A+B .i.e C = \n{");
for(int i=0;i<n;i++){
printf("%f, ",C[i]);
}
printf("}\n");
return 0;
} | .text
.file "vector_add.hip"
.globl _Z27__device_stub__VecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__VecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__VecAddKernelPfS_S_i,@function
_Z27__device_stub__VecAddKernelPfS_S_i: # @_Z27__device_stub__VecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12VecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__VecAddKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__VecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z6vecAddPfS_S_i # -- Begin function _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r15), %edi
testl %r15d, %r15d
cmovnsl %r15d, %edi
sarl $4, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12VecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6vecAddPfS_S_i, .Lfunc_end1-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r12
leaq (,%r12,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movl %r12d, %ecx
testq %r12, %r12
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl %eax, %edx
imull %eax, %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm0, (%r14,%rax,4)
movss %xmm1, (%r15,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r14, %rdi
movq %r15, %rsi
movq %rbx, %rdx
# kill: def $ecx killed $ecx killed $rcx
callq _Z6vecAddPfS_S_i
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB2_6
# %bb.4: # %.lr.ph20.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph20
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB2_5
.LBB2_6: # %._crit_edge21
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12VecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12VecAddKernelPfS_S_i,@object # @_Z12VecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12VecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12VecAddKernelPfS_S_i:
.quad _Z27__device_stub__VecAddKernelPfS_S_i
.size _Z12VecAddKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the size of Vector"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The value of A+B .i.e C = \n{"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f, "
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12VecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "}"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__VecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12VecAddKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12VecAddKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12VecAddKernelPfS_S_i
.globl _Z12VecAddKernelPfS_S_i
.p2align 8
.type _Z12VecAddKernelPfS_S_i,@function
_Z12VecAddKernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12VecAddKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12VecAddKernelPfS_S_i, .Lfunc_end0-_Z12VecAddKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12VecAddKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12VecAddKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c93a9_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
.type _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12VecAddKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
.globl _Z12VecAddKernelPfS_S_i
.type _Z12VecAddKernelPfS_S_i, @function
_Z12VecAddKernelPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12VecAddKernelPfS_S_i, .-_Z12VecAddKernelPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 44(%rsp)
movl $1, 48(%rsp)
leal 15(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $4, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12VecAddKernelPfS_S_iPfS_S_i
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the size of Vector"
.LC1:
.string "%d"
.LC2:
.string "The value of A+B .i.e C = \n{"
.LC3:
.string "%f, "
.LC4:
.string "}\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 4(%rsp), %r14d
movslq %r14d, %r13
leaq 0(,%r13,4), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
testl %r14d, %r14d
jle .L18
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
movl %eax, %edx
imull %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq %rax, %r13
jne .L19
.L18:
movl %r14d, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z6vecAddPfS_S_i
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L20
movl $0, %ebx
leaq .LC3(%rip), %r12
.L21:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L21
.L20:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12VecAddKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12VecAddKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_add.hip"
.globl _Z27__device_stub__VecAddKernelPfS_S_i # -- Begin function _Z27__device_stub__VecAddKernelPfS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__VecAddKernelPfS_S_i,@function
_Z27__device_stub__VecAddKernelPfS_S_i: # @_Z27__device_stub__VecAddKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12VecAddKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__VecAddKernelPfS_S_i, .Lfunc_end0-_Z27__device_stub__VecAddKernelPfS_S_i
.cfi_endproc
# -- End function
.globl _Z6vecAddPfS_S_i # -- Begin function _Z6vecAddPfS_S_i
.p2align 4, 0x90
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i: # @_Z6vecAddPfS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r15), %edi
testl %r15d, %r15d
cmovnsl %r15d, %edi
sarl $4, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $16, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12VecAddKernelPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6vecAddPfS_S_i, .Lfunc_end1-_Z6vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r12
leaq (,%r12,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movl %r12d, %ecx
testq %r12, %r12
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movl %eax, %edx
imull %eax, %edx
xorps %xmm1, %xmm1
cvtsi2ss %edx, %xmm1
movss %xmm0, (%r14,%rax,4)
movss %xmm1, (%r15,%rax,4)
incq %rax
cmpq %rax, %rcx
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r14, %rdi
movq %r15, %rsi
movq %rbx, %rdx
# kill: def $ecx killed $ecx killed $rcx
callq _Z6vecAddPfS_S_i
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB2_6
# %bb.4: # %.lr.ph20.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph20
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB2_5
.LBB2_6: # %._crit_edge21
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12VecAddKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12VecAddKernelPfS_S_i,@object # @_Z12VecAddKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z12VecAddKernelPfS_S_i
.p2align 3, 0x0
_Z12VecAddKernelPfS_S_i:
.quad _Z27__device_stub__VecAddKernelPfS_S_i
.size _Z12VecAddKernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the size of Vector"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "The value of A+B .i.e C = \n{"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f, "
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12VecAddKernelPfS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "}"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__VecAddKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12VecAddKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
typedef struct {
int N;
int M;
int step;
float* m;
} mat;
#define get_elem(A, r, c) (A.m[r * A.step + c])
#define set_elem(A, r, c, val) A.m[r * A.step + c] = val
#define BLOCK_SIZE 2
__device__ mat get_submat(mat A, int row, int col)
{
mat Asub;
Asub.M = BLOCK_SIZE;
Asub.N = BLOCK_SIZE;
Asub.step = A.step;
Asub.m = &A.m[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void matmul(mat A, mat B, mat C)
{
int blockCol = blockIdx.x;
int blockRow = blockIdx.y;
mat Csub = get_submat(C, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
float cij = 0;
for (int m = 0; m < (A.M / BLOCK_SIZE); ++m) {
mat Asub = get_submat(A, blockRow, m);
mat Bsub = get_submat(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = get_elem(Asub, row, col);
Bs[row][col] = get_elem(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
cij += As[row][e] * Bs[e][col];
__syncthreads();
}
set_elem(Csub, row, col, cij);
}
int main()
{
float m1[] = {1,2,3,4,
5,6,7,8,
9,10,11,12,
13,14,15,16};
float m2[] = {16,15,14,13,
12,11,10,9,
8,7,6,5,
4,3,2,1};
float *m3 = (float*)malloc(4 * 4 * sizeof(float));
mat A = { .N = 4, .M = 4, .step = 4, .m = m1 };
mat B = { .N = 4, .M = 4, .step = 4, .m = m2 };
mat C = { .N = 4, .M = 4, .step = 4, .m = m3 };
mat d_A = { .N = A.N, .M = A.M, .step = A.M };
int size = A.M * A.N * sizeof(float);
cudaMalloc(&d_A.m, size);
cudaMemcpy(d_A.m, A.m, size, cudaMemcpyHostToDevice);
mat d_B = { .N = B.N, .M = B.M, .step = B.M };
size = B.M * B.N * sizeof(float);
cudaMalloc(&d_B.m, size);
cudaMemcpy(d_B.m, B.m, size, cudaMemcpyHostToDevice);
mat d_C = { .N = C.N, .M = C.M, .step = C.M};
size = C.M * C.N * sizeof(float);
cudaMalloc(&d_C.m, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.M / dimBlock.x, A.N / dimBlock.y);
matmul<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaMemcpy(C.m, d_C.m, size, cudaMemcpyDeviceToHost);
int N = C.N, M = C.M;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
float elem = C.m[i * C.step + j];
printf("%f ", elem);
}
printf("\n");
}
cudaFree(d_A.m);
cudaFree(d_B.m);
cudaFree(d_C.m);
free(m3);
} | code for sm_80
Function : _Z6matmul3matS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ S2UR UR6, SR_CTAID.Y ; /* 0x00000000000679c3 */
/* 0x000e620000002600 */
/*0040*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R2.reuse, 0x2, PT ; /* 0x000000020200780c */
/* 0x040fe40003f06270 */
/*0080*/ LEA.HI R2, R2, c[0x0][0x164], RZ, 0x1 ; /* 0x0000590002027a11 */
/* 0x000fe400078f08ff */
/*0090*/ S2UR UR7, SR_CTAID.X ; /* 0x00000000000779c3 */
/* 0x000ef20000002500 */
/*00a0*/ @!P0 BRA 0x830 ; /* 0x0000078000008947 */
/* 0x00afea0003800000 */
/*00b0*/ SHF.R.S32.HI R11, RZ, 0x1, R2 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011402 */
/*00c0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IMAD R5, R0.reuse, c[0x0][0x180], R3.reuse ; /* 0x0000600000057a24 */
/* 0x145fe200078e0203 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ IADD3 R4, R11.reuse, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R6, R0, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x000fe200078e00ff */
/*0110*/ LOP3.LUT R2, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b027812 */
/* 0x000fe200078ec0ff */
/*0120*/ UIMAD UR5, UR6, UR5, URZ ; /* 0x00000005060572a4 */
/* 0x000fe2000f8e023f */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0140*/ IMAD R4, R0, c[0x0][0x168], R3 ; /* 0x00005a0000047a24 */
/* 0x000fe200078e0203 */
/*0150*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0160*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0170*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*0180*/ IMAD R6, R3, 0x4, R6 ; /* 0x0000000403067824 */
/* 0x000fe200078e0206 */
/*0190*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fce0000011404 */
/*01a0*/ @!P1 BRA 0x620 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01b0*/ USHF.L.U32 UR8, UR7, 0x1, URZ ; /* 0x0000000107087899 */
/* 0x000fe2000800063f */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff097624 */
/* 0x000fe200078e00ff */
/*01d0*/ ULEA UR4, UR5, 0x6, 0x1 ; /* 0x0000000605047891 */
/* 0x000fe2000f8e083f */
/*01e0*/ IMAD.IADD R10, R2, 0x1, -R11 ; /* 0x00000001020a7824 */
/* 0x000fe400078e0a0b */
/*01f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.SHL.U32 R11, R9, 0x2, RZ ; /* 0x00000002090b7824 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.U32 R22, RZ, RZ, UR8 ; /* 0x00000008ff167e24 */
/* 0x000fe4000f8e00ff */
/*0220*/ IMAD.U32 R23, RZ, RZ, UR4 ; /* 0x00000004ff177e24 */
/* 0x000fe2000f8e00ff */
/*0230*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc80008000000 */
/*0240*/ IADD3 R13, R23, -0x6, RZ ; /* 0xfffffffa170d7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R15, P1, R5, R22, RZ ; /* 0x00000016050f7210 */
/* 0x000fc40007f3e0ff */
/*0260*/ IADD3 R17, P2, R4, R13, RZ ; /* 0x0000000d04117210 */
/* 0x000fe40007f5e0ff */
/*0270*/ LEA.HI.X.SX32 R16, R22, R8, 0x1, P1 ; /* 0x0000000816107211 */
/* 0x000fe400008f0eff */
/*0280*/ LEA R12, P1, R15, c[0x0][0x188], 0x2 ; /* 0x000062000f0c7a11 */
/* 0x000fe400078210ff */
/*0290*/ LEA.HI.X.SX32 R18, R13, R7, 0x1, P2 ; /* 0x000000070d127211 */
/* 0x000fe400010f0eff */
/*02a0*/ LEA R14, P2, R17, c[0x0][0x170], 0x2 ; /* 0x00005c00110e7a11 */
/* 0x000fe400078410ff */
/*02b0*/ LEA.HI.X R13, R15, c[0x0][0x18c], R16, 0x2, P1 ; /* 0x000063000f0d7a11 */
/* 0x000fc400008f1410 */
/*02c0*/ LEA.HI.X R15, R17, c[0x0][0x174], R18, 0x2, P2 ; /* 0x00005d00110f7a11 */
/* 0x000fc600010f1412 */
/*02d0*/ LDG.E R27, [R12.64] ; /* 0x0000000a0c1b7981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R25, [R14.64] ; /* 0x0000000a0e197981 */
/* 0x000ee2000c1e1900 */
/*02f0*/ IMAD.WIDE R20, R11, 0x4, R12 ; /* 0x000000040b147825 */
/* 0x000fc600078e020c */
/*0300*/ STS [R6+0x10], R27 ; /* 0x0000101b06007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R6], R25 ; /* 0x0000001906007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R18, [R3.X4+0x10] ; /* 0x0000100003127984 */
/* 0x000fe80000004800 */
/*0340*/ LDS R26, [R3.X4+0x18] ; /* 0x00001800031a7984 */
/* 0x000fe80000004800 */
/*0350*/ LDS.64 R16, [R0.X8] ; /* 0x0000000000107984 */
/* 0x000e280000008a00 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ LDG.E R29, [R14.64+0x8] ; /* 0x0000080a0e1d7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R20.64] ; /* 0x0000000a141c7981 */
/* 0x000ee2000c1e1900 */
/*0390*/ FFMA R16, R18, R16, R19 ; /* 0x0000001012107223 */
/* 0x001fc40000000013 */
/*03a0*/ IMAD.WIDE R18, R11, 0x4, R20 ; /* 0x000000040b127825 */
/* 0x000fe200078e0214 */
/*03b0*/ STS [R6], R29 ; /* 0x0000001d06007388 */
/* 0x004fe80000000800 */
/*03c0*/ STS [R6+0x10], R28 ; /* 0x0000101c06007388 */
/* 0x008fe80000000800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ LDS R25, [R3.X4+0x10] ; /* 0x0000100003197984 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R24, [R3.X4+0x18] ; /* 0x0000180003187984 */
/* 0x000fe80000004800 */
/*0400*/ LDS.64 R12, [R0.X8] ; /* 0x00000000000c7984 */
/* 0x000e280000008a00 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ LDG.E R27, [R14.64+0x10] ; /* 0x0000100a0e1b7981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R21, [R18.64] ; /* 0x0000000a12157981 */
/* 0x000ee2000c1e1900 */
/*0440*/ FFMA R26, R26, R17, R16 ; /* 0x000000111a1a7223 */
/* 0x000fc40000000010 */
/*0450*/ IMAD.WIDE R16, R11, 0x4, R18 ; /* 0x000000040b107825 */
/* 0x000fe200078e0212 */
/*0460*/ STS [R6], R27 ; /* 0x0000001b06007388 */
/* 0x004fe80000000800 */
/*0470*/ STS [R6+0x10], R21 ; /* 0x0000101506007388 */
/* 0x008fe80000000800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ LDS R27, [R3.X4+0x10] ; /* 0x00001000031b7984 */
/* 0x000fe80000004800 */
/*04a0*/ LDS R28, [R3.X4+0x18] ; /* 0x00001800031c7984 */
/* 0x000fe80000004800 */
/*04b0*/ LDS.64 R20, [R0.X8] ; /* 0x0000000000147984 */
/* 0x000e680000008a00 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ LDG.E R14, [R14.64+0x18] ; /* 0x0000180a0e0e7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R17, [R16.64] ; /* 0x0000000a10117981 */
/* 0x000ee2000c1e1900 */
/*04f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0500*/ FFMA R12, R25, R12, R26 ; /* 0x0000000c190c7223 */
/* 0x001fe2000000001a */
/*0510*/ IADD3 R23, R23, 0x8, RZ ; /* 0x0000000817177810 */
/* 0x000fe20007ffe0ff */
/*0520*/ IMAD R22, R9, 0x8, R22 ; /* 0x0000000809167824 */
/* 0x000fc400078e0216 */
/*0530*/ FFMA R12, R24, R13, R12 ; /* 0x0000000d180c7223 */
/* 0x000fe2000000000c */
/*0540*/ IADD3 R13, R10, UR4, RZ ; /* 0x000000040a0d7c10 */
/* 0x000fc6000fffe0ff */
/*0550*/ FFMA R12, R27, R20, R12 ; /* 0x000000141b0c7223 */
/* 0x002fe2000000000c */
/*0560*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f25270 */
/*0570*/ FFMA R12, R28, R21, R12 ; /* 0x000000151c0c7223 */
/* 0x000fe2000000000c */
/*0580*/ STS [R6], R14 ; /* 0x0000000e06007388 */
/* 0x004fe80000000800 */
/*0590*/ STS [R6+0x10], R17 ; /* 0x0000101106007388 */
/* 0x008fe80000000800 */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05b0*/ LDS R15, [R3.X4+0x10] ; /* 0x00001000030f7984 */
/* 0x000fe80000004800 */
/*05c0*/ LDS.64 R18, [R0.X8] ; /* 0x0000000000127984 */
/* 0x000e280000008a00 */
/*05d0*/ LDS R29, [R3.X4+0x18] ; /* 0x00001800031d7984 */
/* 0x000e620000004800 */
/*05e0*/ FFMA R12, R15, R18, R12 ; /* 0x000000120f0c7223 */
/* 0x001fc8000000000c */
/*05f0*/ FFMA R19, R29, R19, R12 ; /* 0x000000131d137223 */
/* 0x002fe2000000000c */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ @P1 BRA 0x240 ; /* 0xfffffc2000001947 */
/* 0x000fea000383ffff */
/*0620*/ @!P0 BRA 0x830 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0630*/ ULDC UR8, c[0x0][0x180] ; /* 0x0000600000087ab9 */
/* 0x000fe40000000800 */
/*0640*/ UIADD3 UR5, UR5, UR4, URZ ; /* 0x0000000405057290 */
/* 0x000fe4000fffe03f */
/*0650*/ UIMAD UR4, UR4, UR8, UR7 ; /* 0x00000008040472a4 */
/* 0x000fc4000f8e0207 */
/*0660*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe4000800063f */
/*0670*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc8000800063f */
/*0680*/ IMAD.U32 R16, RZ, RZ, UR5 ; /* 0x00000005ff107e24 */
/* 0x000fe4000f8e00ff */
/*0690*/ IMAD.U32 R9, RZ, RZ, UR4 ; /* 0x00000004ff097e24 */
/* 0x000fc6000f8e00ff */
/*06a0*/ IADD3 R13, P0, R4, R16, RZ ; /* 0x00000010040d7210 */
/* 0x000fe40007f1e0ff */
/*06b0*/ IADD3 R10, P1, R5, R9, RZ ; /* 0x00000009050a7210 */
/* 0x000fe40007f3e0ff */
/*06c0*/ LEA.HI.X.SX32 R18, R16, R7, 0x1, P0 ; /* 0x0000000710127211 */
/* 0x000fe400000f0eff */
/*06d0*/ LEA R14, P0, R13, c[0x0][0x170], 0x2 ; /* 0x00005c000d0e7a11 */
/* 0x000fe400078010ff */
/*06e0*/ LEA.HI.X.SX32 R11, R9, R8, 0x1, P1 ; /* 0x00000008090b7211 */
/* 0x000fc400008f0eff */
/*06f0*/ LEA R12, P1, R10.reuse, c[0x0][0x188], 0x2 ; /* 0x000062000a0c7a11 */
/* 0x040fe400078210ff */
/*0700*/ LEA.HI.X R15, R13, c[0x0][0x174], R18, 0x2, P0 ; /* 0x00005d000d0f7a11 */
/* 0x000fe400000f1412 */
/*0710*/ LEA.HI.X R13, R10, c[0x0][0x18c], R11, 0x2, P1 ; /* 0x000063000a0d7a11 */
/* 0x000fc800008f140b */
/*0720*/ LDG.E R15, [R14.64] ; /* 0x0000000a0e0f7981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R13, [R12.64] ; /* 0x0000000a0c0d7981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff147624 */
/* 0x000fe200078e00ff */
/*0760*/ IADD3 R16, R16, 0x2, RZ ; /* 0x0000000210107810 */
/* 0x000fe40007ffe0ff */
/*0770*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0780*/ IMAD R9, R20, 0x2, R9 ; /* 0x0000000214097824 */
/* 0x000fe200078e0209 */
/*0790*/ STS [R6], R15 ; /* 0x0000000f06007388 */
/* 0x004fe80000000800 */
/*07a0*/ STS [R6+0x10], R13 ; /* 0x0000100d06007388 */
/* 0x008fe80000000800 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ LDS R17, [R3.X4+0x10] ; /* 0x0000100003117984 */
/* 0x000fe80000004800 */
/*07d0*/ LDS.64 R10, [R0.X8] ; /* 0x00000000000a7984 */
/* 0x000e280000008a00 */
/*07e0*/ LDS R18, [R3.X4+0x18] ; /* 0x0000180003127984 */
/* 0x000e620000004800 */
/*07f0*/ FFMA R10, R17, R10, R19 ; /* 0x0000000a110a7223 */
/* 0x001fc80000000013 */
/*0800*/ FFMA R19, R18, R11, R10 ; /* 0x0000000b12137223 */
/* 0x002fe2000000000a */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0820*/ @P0 BRA 0x6a0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0830*/ ULDC UR4, c[0x0][0x198] ; /* 0x0000660000047ab9 */
/* 0x000fe20000000800 */
/*0840*/ IMAD R0, R0, c[0x0][0x198], R3 ; /* 0x0000660000007a24 */
/* 0x005fe200078e0203 */
/*0850*/ UIMAD UR4, UR6, UR4, UR7 ; /* 0x00000004060472a4 */
/* 0x000fc8000f8e0207 */
/*0860*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc8000800063f */
/*0870*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*0880*/ IADD3 R3, P0, R0, UR4, RZ ; /* 0x0000000400037c10 */
/* 0x000fc8000ff1e0ff */
/*0890*/ LEA.HI.X.SX32 R0, R0, UR5, 0x1, P0 ; /* 0x0000000500007c11 */
/* 0x000fe400080f0eff */
/*08a0*/ LEA R2, P0, R3, c[0x0][0x1a0], 0x2 ; /* 0x0000680003027a11 */
/* 0x000fc800078010ff */
/*08b0*/ LEA.HI.X R3, R3, c[0x0][0x1a4], R0, 0x2, P0 ; /* 0x0000690003037a11 */
/* 0x000fca00000f1400 */
/*08c0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c10190a */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
typedef struct {
int N;
int M;
int step;
float* m;
} mat;
#define get_elem(A, r, c) (A.m[r * A.step + c])
#define set_elem(A, r, c, val) A.m[r * A.step + c] = val
#define BLOCK_SIZE 2
__device__ mat get_submat(mat A, int row, int col)
{
mat Asub;
Asub.M = BLOCK_SIZE;
Asub.N = BLOCK_SIZE;
Asub.step = A.step;
Asub.m = &A.m[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void matmul(mat A, mat B, mat C)
{
int blockCol = blockIdx.x;
int blockRow = blockIdx.y;
mat Csub = get_submat(C, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
float cij = 0;
for (int m = 0; m < (A.M / BLOCK_SIZE); ++m) {
mat Asub = get_submat(A, blockRow, m);
mat Bsub = get_submat(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = get_elem(Asub, row, col);
Bs[row][col] = get_elem(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
cij += As[row][e] * Bs[e][col];
__syncthreads();
}
set_elem(Csub, row, col, cij);
}
int main()
{
float m1[] = {1,2,3,4,
5,6,7,8,
9,10,11,12,
13,14,15,16};
float m2[] = {16,15,14,13,
12,11,10,9,
8,7,6,5,
4,3,2,1};
float *m3 = (float*)malloc(4 * 4 * sizeof(float));
mat A = { .N = 4, .M = 4, .step = 4, .m = m1 };
mat B = { .N = 4, .M = 4, .step = 4, .m = m2 };
mat C = { .N = 4, .M = 4, .step = 4, .m = m3 };
mat d_A = { .N = A.N, .M = A.M, .step = A.M };
int size = A.M * A.N * sizeof(float);
cudaMalloc(&d_A.m, size);
cudaMemcpy(d_A.m, A.m, size, cudaMemcpyHostToDevice);
mat d_B = { .N = B.N, .M = B.M, .step = B.M };
size = B.M * B.N * sizeof(float);
cudaMalloc(&d_B.m, size);
cudaMemcpy(d_B.m, B.m, size, cudaMemcpyHostToDevice);
mat d_C = { .N = C.N, .M = C.M, .step = C.M};
size = C.M * C.N * sizeof(float);
cudaMalloc(&d_C.m, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.M / dimBlock.x, A.N / dimBlock.y);
matmul<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaMemcpy(C.m, d_C.m, size, cudaMemcpyDeviceToHost);
int N = C.N, M = C.M;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
float elem = C.m[i * C.step + j];
printf("%f ", elem);
}
printf("\n");
}
cudaFree(d_A.m);
cudaFree(d_B.m);
cudaFree(d_C.m);
free(m3);
} | .file "tmpxft_0003b652_00000000-6_task42.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10get_submat3matii
.type _Z10get_submat3matii, @function
_Z10get_submat3matii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10get_submat3matii, .-_Z10get_submat3matii
.globl _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
.type _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_, @function
_Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6matmul3matS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_, .-_Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
.globl _Z6matmul3matS_S_
.type _Z6matmul3matS_S_, @function
_Z6matmul3matS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6matmul3matS_S_, .-_Z6matmul3matS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC16:
.string "%f "
.LC17:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $376, %rsp
.cfi_def_cfa_offset 432
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
movss .LC0(%rip), %xmm0
movss %xmm0, 224(%rsp)
movss .LC1(%rip), %xmm1
movss %xmm1, 228(%rsp)
movss .LC2(%rip), %xmm2
movss %xmm2, 232(%rsp)
movss .LC3(%rip), %xmm3
movss %xmm3, 236(%rsp)
movss .LC4(%rip), %xmm4
movss %xmm4, 240(%rsp)
movss .LC5(%rip), %xmm5
movss %xmm5, 244(%rsp)
movss .LC6(%rip), %xmm6
movss %xmm6, 248(%rsp)
movss .LC7(%rip), %xmm7
movss %xmm7, 252(%rsp)
movss .LC8(%rip), %xmm8
movss %xmm8, 256(%rsp)
movss .LC9(%rip), %xmm9
movss %xmm9, 260(%rsp)
movss .LC10(%rip), %xmm10
movss %xmm10, 264(%rsp)
movss .LC11(%rip), %xmm11
movss %xmm11, 268(%rsp)
movss .LC12(%rip), %xmm12
movss %xmm12, 272(%rsp)
movss .LC13(%rip), %xmm13
movss %xmm13, 276(%rsp)
movss .LC14(%rip), %xmm14
movss %xmm14, 280(%rsp)
movss .LC15(%rip), %xmm15
movss %xmm15, 284(%rsp)
movss %xmm15, 288(%rsp)
movss %xmm14, 292(%rsp)
movss %xmm13, 296(%rsp)
movss %xmm12, 300(%rsp)
movss %xmm11, 304(%rsp)
movss %xmm10, 308(%rsp)
movss %xmm9, 312(%rsp)
movss %xmm8, 316(%rsp)
movss %xmm7, 320(%rsp)
movss %xmm6, 324(%rsp)
movss %xmm5, 328(%rsp)
movss %xmm4, 332(%rsp)
movss %xmm3, 336(%rsp)
movss %xmm2, 340(%rsp)
movss %xmm1, 344(%rsp)
movss %xmm0, 348(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %r14
movq $0, 44(%rsp)
movl $0, 52(%rsp)
movl $4, 32(%rsp)
movl $4, 36(%rsp)
movl $4, 40(%rsp)
leaq 48(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 224(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 76(%rsp)
movl $0, 84(%rsp)
movl $4, 64(%rsp)
movl $4, 68(%rsp)
movl $4, 72(%rsp)
leaq 80(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 288(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 108(%rsp)
movl $0, 116(%rsp)
movl $4, 96(%rsp)
movl $4, 100(%rsp)
movl $4, 104(%rsp)
leaq 112(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $64, %edx
movq 112(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 16(%r14), %rbp
movl $0, %r13d
leaq .LC16(%rip), %r12
leaq .LC17(%rip), %r15
.L15:
leaq -16(%rbp), %rbx
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $4, %r13d
addq $16, %rbp
cmpl $16, %r13d
jne .L15
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movdqa 32(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm2
movaps %xmm2, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm3
movaps %xmm3, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z6matmul3matS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmul3matS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.align 4
.LC2:
.long 1077936128
.align 4
.LC3:
.long 1082130432
.align 4
.LC4:
.long 1084227584
.align 4
.LC5:
.long 1086324736
.align 4
.LC6:
.long 1088421888
.align 4
.LC7:
.long 1090519040
.align 4
.LC8:
.long 1091567616
.align 4
.LC9:
.long 1092616192
.align 4
.LC10:
.long 1093664768
.align 4
.LC11:
.long 1094713344
.align 4
.LC12:
.long 1095761920
.align 4
.LC13:
.long 1096810496
.align 4
.LC14:
.long 1097859072
.align 4
.LC15:
.long 1098907648
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
typedef struct {
int N;
int M;
int step;
float* m;
} mat;
#define get_elem(A, r, c) (A.m[r * A.step + c])
#define set_elem(A, r, c, val) A.m[r * A.step + c] = val
#define BLOCK_SIZE 2
__device__ mat get_submat(mat A, int row, int col)
{
mat Asub;
Asub.M = BLOCK_SIZE;
Asub.N = BLOCK_SIZE;
Asub.step = A.step;
Asub.m = &A.m[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void matmul(mat A, mat B, mat C)
{
int blockCol = blockIdx.x;
int blockRow = blockIdx.y;
mat Csub = get_submat(C, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
float cij = 0;
for (int m = 0; m < (A.M / BLOCK_SIZE); ++m) {
mat Asub = get_submat(A, blockRow, m);
mat Bsub = get_submat(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = get_elem(Asub, row, col);
Bs[row][col] = get_elem(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
cij += As[row][e] * Bs[e][col];
__syncthreads();
}
set_elem(Csub, row, col, cij);
}
int main()
{
float m1[] = {1,2,3,4,
5,6,7,8,
9,10,11,12,
13,14,15,16};
float m2[] = {16,15,14,13,
12,11,10,9,
8,7,6,5,
4,3,2,1};
float *m3 = (float*)malloc(4 * 4 * sizeof(float));
mat A = { .N = 4, .M = 4, .step = 4, .m = m1 };
mat B = { .N = 4, .M = 4, .step = 4, .m = m2 };
mat C = { .N = 4, .M = 4, .step = 4, .m = m3 };
mat d_A = { .N = A.N, .M = A.M, .step = A.M };
int size = A.M * A.N * sizeof(float);
cudaMalloc(&d_A.m, size);
cudaMemcpy(d_A.m, A.m, size, cudaMemcpyHostToDevice);
mat d_B = { .N = B.N, .M = B.M, .step = B.M };
size = B.M * B.N * sizeof(float);
cudaMalloc(&d_B.m, size);
cudaMemcpy(d_B.m, B.m, size, cudaMemcpyHostToDevice);
mat d_C = { .N = C.N, .M = C.M, .step = C.M};
size = C.M * C.N * sizeof(float);
cudaMalloc(&d_C.m, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.M / dimBlock.x, A.N / dimBlock.y);
matmul<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
cudaMemcpy(C.m, d_C.m, size, cudaMemcpyDeviceToHost);
int N = C.N, M = C.M;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
float elem = C.m[i * C.step + j];
printf("%f ", elem);
}
printf("\n");
}
cudaFree(d_A.m);
cudaFree(d_B.m);
cudaFree(d_C.m);
free(m3);
} | #include <hip/hip_runtime.h>
#include "stdio.h"
typedef struct {
int N;
int M;
int step;
float* m;
} mat;
#define get_elem(A, r, c) (A.m[r * A.step + c])
#define set_elem(A, r, c, val) A.m[r * A.step + c] = val
#define BLOCK_SIZE 2
__device__ mat get_submat(mat A, int row, int col)
{
mat Asub;
Asub.M = BLOCK_SIZE;
Asub.N = BLOCK_SIZE;
Asub.step = A.step;
Asub.m = &A.m[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void matmul(mat A, mat B, mat C)
{
int blockCol = blockIdx.x;
int blockRow = blockIdx.y;
mat Csub = get_submat(C, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
float cij = 0;
for (int m = 0; m < (A.M / BLOCK_SIZE); ++m) {
mat Asub = get_submat(A, blockRow, m);
mat Bsub = get_submat(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = get_elem(Asub, row, col);
Bs[row][col] = get_elem(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
cij += As[row][e] * Bs[e][col];
__syncthreads();
}
set_elem(Csub, row, col, cij);
}
int main()
{
float m1[] = {1,2,3,4,
5,6,7,8,
9,10,11,12,
13,14,15,16};
float m2[] = {16,15,14,13,
12,11,10,9,
8,7,6,5,
4,3,2,1};
float *m3 = (float*)malloc(4 * 4 * sizeof(float));
mat A = { .N = 4, .M = 4, .step = 4, .m = m1 };
mat B = { .N = 4, .M = 4, .step = 4, .m = m2 };
mat C = { .N = 4, .M = 4, .step = 4, .m = m3 };
mat d_A = { .N = A.N, .M = A.M, .step = A.M };
int size = A.M * A.N * sizeof(float);
hipMalloc(&d_A.m, size);
hipMemcpy(d_A.m, A.m, size, hipMemcpyHostToDevice);
mat d_B = { .N = B.N, .M = B.M, .step = B.M };
size = B.M * B.N * sizeof(float);
hipMalloc(&d_B.m, size);
hipMemcpy(d_B.m, B.m, size, hipMemcpyHostToDevice);
mat d_C = { .N = C.N, .M = C.M, .step = C.M};
size = C.M * C.N * sizeof(float);
hipMalloc(&d_C.m, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.M / dimBlock.x, A.N / dimBlock.y);
matmul<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipMemcpy(C.m, d_C.m, size, hipMemcpyDeviceToHost);
int N = C.N, M = C.M;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
float elem = C.m[i * C.step + j];
printf("%f ", elem);
}
printf("\n");
}
hipFree(d_A.m);
hipFree(d_B.m);
hipFree(d_C.m);
free(m3);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
typedef struct {
int N;
int M;
int step;
float* m;
} mat;
#define get_elem(A, r, c) (A.m[r * A.step + c])
#define set_elem(A, r, c, val) A.m[r * A.step + c] = val
#define BLOCK_SIZE 2
__device__ mat get_submat(mat A, int row, int col)
{
mat Asub;
Asub.M = BLOCK_SIZE;
Asub.N = BLOCK_SIZE;
Asub.step = A.step;
Asub.m = &A.m[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void matmul(mat A, mat B, mat C)
{
int blockCol = blockIdx.x;
int blockRow = blockIdx.y;
mat Csub = get_submat(C, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
float cij = 0;
for (int m = 0; m < (A.M / BLOCK_SIZE); ++m) {
mat Asub = get_submat(A, blockRow, m);
mat Bsub = get_submat(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = get_elem(Asub, row, col);
Bs[row][col] = get_elem(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
cij += As[row][e] * Bs[e][col];
__syncthreads();
}
set_elem(Csub, row, col, cij);
}
int main()
{
float m1[] = {1,2,3,4,
5,6,7,8,
9,10,11,12,
13,14,15,16};
float m2[] = {16,15,14,13,
12,11,10,9,
8,7,6,5,
4,3,2,1};
float *m3 = (float*)malloc(4 * 4 * sizeof(float));
mat A = { .N = 4, .M = 4, .step = 4, .m = m1 };
mat B = { .N = 4, .M = 4, .step = 4, .m = m2 };
mat C = { .N = 4, .M = 4, .step = 4, .m = m3 };
mat d_A = { .N = A.N, .M = A.M, .step = A.M };
int size = A.M * A.N * sizeof(float);
hipMalloc(&d_A.m, size);
hipMemcpy(d_A.m, A.m, size, hipMemcpyHostToDevice);
mat d_B = { .N = B.N, .M = B.M, .step = B.M };
size = B.M * B.N * sizeof(float);
hipMalloc(&d_B.m, size);
hipMemcpy(d_B.m, B.m, size, hipMemcpyHostToDevice);
mat d_C = { .N = C.N, .M = C.M, .step = C.M};
size = C.M * C.N * sizeof(float);
hipMalloc(&d_C.m, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.M / dimBlock.x, A.N / dimBlock.y);
matmul<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipMemcpy(C.m, d_C.m, size, hipMemcpyDeviceToHost);
int N = C.N, M = C.M;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
float elem = C.m[i * C.step + j];
printf("%f ", elem);
}
printf("\n");
}
hipFree(d_A.m);
hipFree(d_B.m);
hipFree(d_C.m);
free(m3);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmul3matS_S_
.globl _Z6matmul3matS_S_
.p2align 8
.type _Z6matmul3matS_S_,@function
_Z6matmul3matS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x40
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 2
s_cbranch_scc1 .LBB0_5
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
v_lshlrev_b32_e32 v2, 2, v0
v_lshlrev_b32_e32 v3, 3, v1
s_lshr_b32 s11, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s5, s5, s11
v_add_nc_u32_e32 v4, 16, v2
s_ashr_i32 s5, s5, 1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s10, v1, v[0:1]
v_mad_u64_u32 v[7:8], null, s4, v1, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v3, v2
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_add_nc_u32_e32 v6, v4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
s_mul_i32 s6, s10, s15
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_lshl_b32 s8, s9, 1
s_lshl_b32 s10, s10, 1
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v7, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v9, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v10, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v4
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v5, v12
s_waitcnt vmcnt(0)
ds_store_b32 v6, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v3
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 8, v11
s_cmp_lg_u32 s8, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s0, v1, v[0:1]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v4, 31, v3
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmul3matS_S_
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmul3matS_S_, .Lfunc_end0-_Z6matmul3matS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmul3matS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmul3matS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
typedef struct {
int N;
int M;
int step;
float* m;
} mat;
#define get_elem(A, r, c) (A.m[r * A.step + c])
#define set_elem(A, r, c, val) A.m[r * A.step + c] = val
#define BLOCK_SIZE 2
__device__ mat get_submat(mat A, int row, int col)
{
mat Asub;
Asub.M = BLOCK_SIZE;
Asub.N = BLOCK_SIZE;
Asub.step = A.step;
Asub.m = &A.m[A.step * BLOCK_SIZE * row + BLOCK_SIZE * col];
return Asub;
}
__global__ void matmul(mat A, mat B, mat C)
{
int blockCol = blockIdx.x;
int blockRow = blockIdx.y;
mat Csub = get_submat(C, blockRow, blockCol);
int row = threadIdx.y;
int col = threadIdx.x;
float cij = 0;
for (int m = 0; m < (A.M / BLOCK_SIZE); ++m) {
mat Asub = get_submat(A, blockRow, m);
mat Bsub = get_submat(B, m, blockCol);
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[row][col] = get_elem(Asub, row, col);
Bs[row][col] = get_elem(Bsub, row, col);
__syncthreads();
for (int e = 0; e < BLOCK_SIZE; ++e)
cij += As[row][e] * Bs[e][col];
__syncthreads();
}
set_elem(Csub, row, col, cij);
}
int main()
{
float m1[] = {1,2,3,4,
5,6,7,8,
9,10,11,12,
13,14,15,16};
float m2[] = {16,15,14,13,
12,11,10,9,
8,7,6,5,
4,3,2,1};
float *m3 = (float*)malloc(4 * 4 * sizeof(float));
mat A = { .N = 4, .M = 4, .step = 4, .m = m1 };
mat B = { .N = 4, .M = 4, .step = 4, .m = m2 };
mat C = { .N = 4, .M = 4, .step = 4, .m = m3 };
mat d_A = { .N = A.N, .M = A.M, .step = A.M };
int size = A.M * A.N * sizeof(float);
hipMalloc(&d_A.m, size);
hipMemcpy(d_A.m, A.m, size, hipMemcpyHostToDevice);
mat d_B = { .N = B.N, .M = B.M, .step = B.M };
size = B.M * B.N * sizeof(float);
hipMalloc(&d_B.m, size);
hipMemcpy(d_B.m, B.m, size, hipMemcpyHostToDevice);
mat d_C = { .N = C.N, .M = C.M, .step = C.M};
size = C.M * C.N * sizeof(float);
hipMalloc(&d_C.m, size);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.M / dimBlock.x, A.N / dimBlock.y);
matmul<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
hipMemcpy(C.m, d_C.m, size, hipMemcpyDeviceToHost);
int N = C.N, M = C.M;
for (int i = 0; i < N; i++) {
for (int j = 0; j < M; j++) {
float elem = C.m[i * C.step + j];
printf("%f ", elem);
}
printf("\n");
}
hipFree(d_A.m);
hipFree(d_B.m);
hipFree(d_C.m);
free(m3);
} | .text
.file "task42.hip"
.globl _Z21__device_stub__matmul3matS_S_ # -- Begin function _Z21__device_stub__matmul3matS_S_
.p2align 4, 0x90
.type _Z21__device_stub__matmul3matS_S_,@function
_Z21__device_stub__matmul3matS_S_: # @_Z21__device_stub__matmul3matS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6matmul3matS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__matmul3matS_S_, .Lfunc_end0-_Z21__device_stub__matmul3matS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI1_1:
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.long 0x40e00000 # float 7
.long 0x41000000 # float 8
.LCPI1_2:
.long 0x41100000 # float 9
.long 0x41200000 # float 10
.long 0x41300000 # float 11
.long 0x41400000 # float 12
.LCPI1_3:
.long 0x41500000 # float 13
.long 0x41600000 # float 14
.long 0x41700000 # float 15
.long 0x41800000 # float 16
.LCPI1_4:
.long 0x41800000 # float 16
.long 0x41700000 # float 15
.long 0x41600000 # float 14
.long 0x41500000 # float 13
.LCPI1_5:
.long 0x41400000 # float 12
.long 0x41300000 # float 11
.long 0x41200000 # float 10
.long 0x41100000 # float 9
.LCPI1_6:
.long 0x41000000 # float 8
.long 0x40e00000 # float 7
.long 0x40c00000 # float 6
.long 0x40a00000 # float 5
.LCPI1_7:
.long 0x40800000 # float 4
.long 0x40400000 # float 3
.long 0x40000000 # float 2
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 320(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5.0E+0,6.0E+0,7.0E+0,8.0E+0]
movaps %xmm0, 336(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1]
movaps %xmm0, 352(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [1.3E+1,1.4E+1,1.5E+1,1.6E+1]
movaps %xmm0, 368(%rsp)
movaps .LCPI1_4(%rip), %xmm0 # xmm0 = [1.6E+1,1.5E+1,1.4E+1,1.3E+1]
movaps %xmm0, 256(%rsp)
movaps .LCPI1_5(%rip), %xmm0 # xmm0 = [1.2E+1,1.1E+1,1.0E+1,9.0E+0]
movaps %xmm0, 272(%rsp)
movaps .LCPI1_6(%rip), %xmm0 # xmm0 = [8.0E+0,7.0E+0,6.0E+0,5.0E+0]
movaps %xmm0, 288(%rsp)
movaps .LCPI1_7(%rip), %xmm0 # xmm0 = [4.0E+0,3.0E+0,2.0E+0,1.0E+0]
movaps %xmm0, 304(%rsp)
movl $64, %edi
callq malloc
movq %rax, %rbx
movabsq $17179869188, %r14 # imm = 0x400000004
movq %r14, 56(%rsp)
movl $4, 64(%rsp)
leaq 72(%rsp), %rdi
movq $0, 72(%rsp)
movl $64, %esi
callq hipMalloc
movq 72(%rsp), %rdi
leaq 320(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, 32(%rsp)
movl $4, 40(%rsp)
leaq 48(%rsp), %rdi
movq $0, 48(%rsp)
movl $64, %esi
callq hipMalloc
movq 48(%rsp), %rdi
leaq 256(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, 8(%rsp)
movl $4, 16(%rsp)
leaq 24(%rsp), %rdi
movq $0, 24(%rsp)
movl $64, %esi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movups 56(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movups 32(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 24(%rsp), %rax
movq %rax, 240(%rsp)
movups 8(%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6matmul3matS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %r15
cmpq $4, %r14
jne .LBB1_3
# %bb.6:
movq 72(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmul3matS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmul3matS_S_,@object # @_Z6matmul3matS_S_
.section .rodata,"a",@progbits
.globl _Z6matmul3matS_S_
.p2align 3, 0x0
_Z6matmul3matS_S_:
.quad _Z21__device_stub__matmul3matS_S_
.size _Z6matmul3matS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmul3matS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmul3matS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmul3matS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matmul3matS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ S2UR UR6, SR_CTAID.Y ; /* 0x00000000000679c3 */
/* 0x000e620000002600 */
/*0040*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R2.reuse, 0x2, PT ; /* 0x000000020200780c */
/* 0x040fe40003f06270 */
/*0080*/ LEA.HI R2, R2, c[0x0][0x164], RZ, 0x1 ; /* 0x0000590002027a11 */
/* 0x000fe400078f08ff */
/*0090*/ S2UR UR7, SR_CTAID.X ; /* 0x00000000000779c3 */
/* 0x000ef20000002500 */
/*00a0*/ @!P0 BRA 0x830 ; /* 0x0000078000008947 */
/* 0x00afea0003800000 */
/*00b0*/ SHF.R.S32.HI R11, RZ, 0x1, R2 ; /* 0x00000001ff0b7819 */
/* 0x000fe20000011402 */
/*00c0*/ ULDC UR5, c[0x0][0x168] ; /* 0x00005a0000057ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IMAD R5, R0.reuse, c[0x0][0x180], R3.reuse ; /* 0x0000600000057a24 */
/* 0x145fe200078e0203 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ IADD3 R4, R11.reuse, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R6, R0, 0x8, RZ ; /* 0x0000000800067824 */
/* 0x000fe200078e00ff */
/*0110*/ LOP3.LUT R2, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b027812 */
/* 0x000fe200078ec0ff */
/*0120*/ UIMAD UR5, UR6, UR5, URZ ; /* 0x00000005060572a4 */
/* 0x000fe2000f8e023f */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*0140*/ IMAD R4, R0, c[0x0][0x168], R3 ; /* 0x00005a0000047a24 */
/* 0x000fe200078e0203 */
/*0150*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0160*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*0170*/ SHF.R.S32.HI R8, RZ, 0x1f, R5 ; /* 0x0000001fff087819 */
/* 0x000fe20000011405 */
/*0180*/ IMAD R6, R3, 0x4, R6 ; /* 0x0000000403067824 */
/* 0x000fe200078e0206 */
/*0190*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fce0000011404 */
/*01a0*/ @!P1 BRA 0x620 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01b0*/ USHF.L.U32 UR8, UR7, 0x1, URZ ; /* 0x0000000107087899 */
/* 0x000fe2000800063f */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff097624 */
/* 0x000fe200078e00ff */
/*01d0*/ ULEA UR4, UR5, 0x6, 0x1 ; /* 0x0000000605047891 */
/* 0x000fe2000f8e083f */
/*01e0*/ IMAD.IADD R10, R2, 0x1, -R11 ; /* 0x00000001020a7824 */
/* 0x000fe400078e0a0b */
/*01f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.SHL.U32 R11, R9, 0x2, RZ ; /* 0x00000002090b7824 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.U32 R22, RZ, RZ, UR8 ; /* 0x00000008ff167e24 */
/* 0x000fe4000f8e00ff */
/*0220*/ IMAD.U32 R23, RZ, RZ, UR4 ; /* 0x00000004ff177e24 */
/* 0x000fe2000f8e00ff */
/*0230*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc80008000000 */
/*0240*/ IADD3 R13, R23, -0x6, RZ ; /* 0xfffffffa170d7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R15, P1, R5, R22, RZ ; /* 0x00000016050f7210 */
/* 0x000fc40007f3e0ff */
/*0260*/ IADD3 R17, P2, R4, R13, RZ ; /* 0x0000000d04117210 */
/* 0x000fe40007f5e0ff */
/*0270*/ LEA.HI.X.SX32 R16, R22, R8, 0x1, P1 ; /* 0x0000000816107211 */
/* 0x000fe400008f0eff */
/*0280*/ LEA R12, P1, R15, c[0x0][0x188], 0x2 ; /* 0x000062000f0c7a11 */
/* 0x000fe400078210ff */
/*0290*/ LEA.HI.X.SX32 R18, R13, R7, 0x1, P2 ; /* 0x000000070d127211 */
/* 0x000fe400010f0eff */
/*02a0*/ LEA R14, P2, R17, c[0x0][0x170], 0x2 ; /* 0x00005c00110e7a11 */
/* 0x000fe400078410ff */
/*02b0*/ LEA.HI.X R13, R15, c[0x0][0x18c], R16, 0x2, P1 ; /* 0x000063000f0d7a11 */
/* 0x000fc400008f1410 */
/*02c0*/ LEA.HI.X R15, R17, c[0x0][0x174], R18, 0x2, P2 ; /* 0x00005d00110f7a11 */
/* 0x000fc600010f1412 */
/*02d0*/ LDG.E R27, [R12.64] ; /* 0x0000000a0c1b7981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R25, [R14.64] ; /* 0x0000000a0e197981 */
/* 0x000ee2000c1e1900 */
/*02f0*/ IMAD.WIDE R20, R11, 0x4, R12 ; /* 0x000000040b147825 */
/* 0x000fc600078e020c */
/*0300*/ STS [R6+0x10], R27 ; /* 0x0000101b06007388 */
/* 0x004fe80000000800 */
/*0310*/ STS [R6], R25 ; /* 0x0000001906007388 */
/* 0x008fe80000000800 */
/*0320*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0330*/ LDS R18, [R3.X4+0x10] ; /* 0x0000100003127984 */
/* 0x000fe80000004800 */
/*0340*/ LDS R26, [R3.X4+0x18] ; /* 0x00001800031a7984 */
/* 0x000fe80000004800 */
/*0350*/ LDS.64 R16, [R0.X8] ; /* 0x0000000000107984 */
/* 0x000e280000008a00 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ LDG.E R29, [R14.64+0x8] ; /* 0x0000080a0e1d7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R20.64] ; /* 0x0000000a141c7981 */
/* 0x000ee2000c1e1900 */
/*0390*/ FFMA R16, R18, R16, R19 ; /* 0x0000001012107223 */
/* 0x001fc40000000013 */
/*03a0*/ IMAD.WIDE R18, R11, 0x4, R20 ; /* 0x000000040b127825 */
/* 0x000fe200078e0214 */
/*03b0*/ STS [R6], R29 ; /* 0x0000001d06007388 */
/* 0x004fe80000000800 */
/*03c0*/ STS [R6+0x10], R28 ; /* 0x0000101c06007388 */
/* 0x008fe80000000800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ LDS R25, [R3.X4+0x10] ; /* 0x0000100003197984 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R24, [R3.X4+0x18] ; /* 0x0000180003187984 */
/* 0x000fe80000004800 */
/*0400*/ LDS.64 R12, [R0.X8] ; /* 0x00000000000c7984 */
/* 0x000e280000008a00 */
/*0410*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0420*/ LDG.E R27, [R14.64+0x10] ; /* 0x0000100a0e1b7981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R21, [R18.64] ; /* 0x0000000a12157981 */
/* 0x000ee2000c1e1900 */
/*0440*/ FFMA R26, R26, R17, R16 ; /* 0x000000111a1a7223 */
/* 0x000fc40000000010 */
/*0450*/ IMAD.WIDE R16, R11, 0x4, R18 ; /* 0x000000040b107825 */
/* 0x000fe200078e0212 */
/*0460*/ STS [R6], R27 ; /* 0x0000001b06007388 */
/* 0x004fe80000000800 */
/*0470*/ STS [R6+0x10], R21 ; /* 0x0000101506007388 */
/* 0x008fe80000000800 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0490*/ LDS R27, [R3.X4+0x10] ; /* 0x00001000031b7984 */
/* 0x000fe80000004800 */
/*04a0*/ LDS R28, [R3.X4+0x18] ; /* 0x00001800031c7984 */
/* 0x000fe80000004800 */
/*04b0*/ LDS.64 R20, [R0.X8] ; /* 0x0000000000147984 */
/* 0x000e680000008a00 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ LDG.E R14, [R14.64+0x18] ; /* 0x0000180a0e0e7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R17, [R16.64] ; /* 0x0000000a10117981 */
/* 0x000ee2000c1e1900 */
/*04f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0500*/ FFMA R12, R25, R12, R26 ; /* 0x0000000c190c7223 */
/* 0x001fe2000000001a */
/*0510*/ IADD3 R23, R23, 0x8, RZ ; /* 0x0000000817177810 */
/* 0x000fe20007ffe0ff */
/*0520*/ IMAD R22, R9, 0x8, R22 ; /* 0x0000000809167824 */
/* 0x000fc400078e0216 */
/*0530*/ FFMA R12, R24, R13, R12 ; /* 0x0000000d180c7223 */
/* 0x000fe2000000000c */
/*0540*/ IADD3 R13, R10, UR4, RZ ; /* 0x000000040a0d7c10 */
/* 0x000fc6000fffe0ff */
/*0550*/ FFMA R12, R27, R20, R12 ; /* 0x000000141b0c7223 */
/* 0x002fe2000000000c */
/*0560*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f25270 */
/*0570*/ FFMA R12, R28, R21, R12 ; /* 0x000000151c0c7223 */
/* 0x000fe2000000000c */
/*0580*/ STS [R6], R14 ; /* 0x0000000e06007388 */
/* 0x004fe80000000800 */
/*0590*/ STS [R6+0x10], R17 ; /* 0x0000101106007388 */
/* 0x008fe80000000800 */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05b0*/ LDS R15, [R3.X4+0x10] ; /* 0x00001000030f7984 */
/* 0x000fe80000004800 */
/*05c0*/ LDS.64 R18, [R0.X8] ; /* 0x0000000000127984 */
/* 0x000e280000008a00 */
/*05d0*/ LDS R29, [R3.X4+0x18] ; /* 0x00001800031d7984 */
/* 0x000e620000004800 */
/*05e0*/ FFMA R12, R15, R18, R12 ; /* 0x000000120f0c7223 */
/* 0x001fc8000000000c */
/*05f0*/ FFMA R19, R29, R19, R12 ; /* 0x000000131d137223 */
/* 0x002fe2000000000c */
/*0600*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0610*/ @P1 BRA 0x240 ; /* 0xfffffc2000001947 */
/* 0x000fea000383ffff */
/*0620*/ @!P0 BRA 0x830 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0630*/ ULDC UR8, c[0x0][0x180] ; /* 0x0000600000087ab9 */
/* 0x000fe40000000800 */
/*0640*/ UIADD3 UR5, UR5, UR4, URZ ; /* 0x0000000405057290 */
/* 0x000fe4000fffe03f */
/*0650*/ UIMAD UR4, UR4, UR8, UR7 ; /* 0x00000008040472a4 */
/* 0x000fc4000f8e0207 */
/*0660*/ USHF.L.U32 UR5, UR5, 0x1, URZ ; /* 0x0000000105057899 */
/* 0x000fe4000800063f */
/*0670*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc8000800063f */
/*0680*/ IMAD.U32 R16, RZ, RZ, UR5 ; /* 0x00000005ff107e24 */
/* 0x000fe4000f8e00ff */
/*0690*/ IMAD.U32 R9, RZ, RZ, UR4 ; /* 0x00000004ff097e24 */
/* 0x000fc6000f8e00ff */
/*06a0*/ IADD3 R13, P0, R4, R16, RZ ; /* 0x00000010040d7210 */
/* 0x000fe40007f1e0ff */
/*06b0*/ IADD3 R10, P1, R5, R9, RZ ; /* 0x00000009050a7210 */
/* 0x000fe40007f3e0ff */
/*06c0*/ LEA.HI.X.SX32 R18, R16, R7, 0x1, P0 ; /* 0x0000000710127211 */
/* 0x000fe400000f0eff */
/*06d0*/ LEA R14, P0, R13, c[0x0][0x170], 0x2 ; /* 0x00005c000d0e7a11 */
/* 0x000fe400078010ff */
/*06e0*/ LEA.HI.X.SX32 R11, R9, R8, 0x1, P1 ; /* 0x00000008090b7211 */
/* 0x000fc400008f0eff */
/*06f0*/ LEA R12, P1, R10.reuse, c[0x0][0x188], 0x2 ; /* 0x000062000a0c7a11 */
/* 0x040fe400078210ff */
/*0700*/ LEA.HI.X R15, R13, c[0x0][0x174], R18, 0x2, P0 ; /* 0x00005d000d0f7a11 */
/* 0x000fe400000f1412 */
/*0710*/ LEA.HI.X R13, R10, c[0x0][0x18c], R11, 0x2, P1 ; /* 0x000063000a0d7a11 */
/* 0x000fc800008f140b */
/*0720*/ LDG.E R15, [R14.64] ; /* 0x0000000a0e0f7981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R13, [R12.64] ; /* 0x0000000a0c0d7981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff147624 */
/* 0x000fe200078e00ff */
/*0760*/ IADD3 R16, R16, 0x2, RZ ; /* 0x0000000210107810 */
/* 0x000fe40007ffe0ff */
/*0770*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0780*/ IMAD R9, R20, 0x2, R9 ; /* 0x0000000214097824 */
/* 0x000fe200078e0209 */
/*0790*/ STS [R6], R15 ; /* 0x0000000f06007388 */
/* 0x004fe80000000800 */
/*07a0*/ STS [R6+0x10], R13 ; /* 0x0000100d06007388 */
/* 0x008fe80000000800 */
/*07b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07c0*/ LDS R17, [R3.X4+0x10] ; /* 0x0000100003117984 */
/* 0x000fe80000004800 */
/*07d0*/ LDS.64 R10, [R0.X8] ; /* 0x00000000000a7984 */
/* 0x000e280000008a00 */
/*07e0*/ LDS R18, [R3.X4+0x18] ; /* 0x0000180003127984 */
/* 0x000e620000004800 */
/*07f0*/ FFMA R10, R17, R10, R19 ; /* 0x0000000a110a7223 */
/* 0x001fc80000000013 */
/*0800*/ FFMA R19, R18, R11, R10 ; /* 0x0000000b12137223 */
/* 0x002fe2000000000a */
/*0810*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0820*/ @P0 BRA 0x6a0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0830*/ ULDC UR4, c[0x0][0x198] ; /* 0x0000660000047ab9 */
/* 0x000fe20000000800 */
/*0840*/ IMAD R0, R0, c[0x0][0x198], R3 ; /* 0x0000660000007a24 */
/* 0x005fe200078e0203 */
/*0850*/ UIMAD UR4, UR6, UR4, UR7 ; /* 0x00000004060472a4 */
/* 0x000fc8000f8e0207 */
/*0860*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fc8000800063f */
/*0870*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*0880*/ IADD3 R3, P0, R0, UR4, RZ ; /* 0x0000000400037c10 */
/* 0x000fc8000ff1e0ff */
/*0890*/ LEA.HI.X.SX32 R0, R0, UR5, 0x1, P0 ; /* 0x0000000500007c11 */
/* 0x000fe400080f0eff */
/*08a0*/ LEA R2, P0, R3, c[0x0][0x1a0], 0x2 ; /* 0x0000680003027a11 */
/* 0x000fc800078010ff */
/*08b0*/ LEA.HI.X R3, R3, c[0x0][0x1a4], R0, 0x2, P0 ; /* 0x0000690003037a11 */
/* 0x000fca00000f1400 */
/*08c0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c10190a */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmul3matS_S_
.globl _Z6matmul3matS_S_
.p2align 8
.type _Z6matmul3matS_S_,@function
_Z6matmul3matS_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x40
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 2
s_cbranch_scc1 .LBB0_5
s_clause 0x3
s_load_b32 s10, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x28
v_lshlrev_b32_e32 v2, 2, v0
v_lshlrev_b32_e32 v3, 3, v1
s_lshr_b32 s11, s5, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_i32 s5, s5, s11
v_add_nc_u32_e32 v4, 16, v2
s_ashr_i32 s5, s5, 1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s10, v1, v[0:1]
v_mad_u64_u32 v[7:8], null, s4, v1, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v3, v2
v_lshlrev_b64 v[11:12], 2, v[7:8]
v_add_nc_u32_e32 v6, v4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v12, vcc_lo
s_mul_i32 s6, s10, s15
s_mov_b32 s7, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_lshl_b32 s8, s9, 1
s_lshl_b32 s10, s10, 1
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v7, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v8, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v9, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v10, vcc_lo
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v4
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v5, v12
s_waitcnt vmcnt(0)
ds_store_b32 v6, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v3
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 8, v11
s_cmp_lg_u32 s8, 4
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s0, v1, v[0:1]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v4, 31, v3
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmul3matS_S_
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmul3matS_S_, .Lfunc_end0-_Z6matmul3matS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmul3matS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmul3matS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003b652_00000000-6_task42.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10get_submat3matii
.type _Z10get_submat3matii, @function
_Z10get_submat3matii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10get_submat3matii, .-_Z10get_submat3matii
.globl _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
.type _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_, @function
_Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6matmul3matS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_, .-_Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
.globl _Z6matmul3matS_S_
.type _Z6matmul3matS_S_, @function
_Z6matmul3matS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6matmul3matS_S_, .-_Z6matmul3matS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC16:
.string "%f "
.LC17:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $376, %rsp
.cfi_def_cfa_offset 432
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
movss .LC0(%rip), %xmm0
movss %xmm0, 224(%rsp)
movss .LC1(%rip), %xmm1
movss %xmm1, 228(%rsp)
movss .LC2(%rip), %xmm2
movss %xmm2, 232(%rsp)
movss .LC3(%rip), %xmm3
movss %xmm3, 236(%rsp)
movss .LC4(%rip), %xmm4
movss %xmm4, 240(%rsp)
movss .LC5(%rip), %xmm5
movss %xmm5, 244(%rsp)
movss .LC6(%rip), %xmm6
movss %xmm6, 248(%rsp)
movss .LC7(%rip), %xmm7
movss %xmm7, 252(%rsp)
movss .LC8(%rip), %xmm8
movss %xmm8, 256(%rsp)
movss .LC9(%rip), %xmm9
movss %xmm9, 260(%rsp)
movss .LC10(%rip), %xmm10
movss %xmm10, 264(%rsp)
movss .LC11(%rip), %xmm11
movss %xmm11, 268(%rsp)
movss .LC12(%rip), %xmm12
movss %xmm12, 272(%rsp)
movss .LC13(%rip), %xmm13
movss %xmm13, 276(%rsp)
movss .LC14(%rip), %xmm14
movss %xmm14, 280(%rsp)
movss .LC15(%rip), %xmm15
movss %xmm15, 284(%rsp)
movss %xmm15, 288(%rsp)
movss %xmm14, 292(%rsp)
movss %xmm13, 296(%rsp)
movss %xmm12, 300(%rsp)
movss %xmm11, 304(%rsp)
movss %xmm10, 308(%rsp)
movss %xmm9, 312(%rsp)
movss %xmm8, 316(%rsp)
movss %xmm7, 320(%rsp)
movss %xmm6, 324(%rsp)
movss %xmm5, 328(%rsp)
movss %xmm4, 332(%rsp)
movss %xmm3, 336(%rsp)
movss %xmm2, 340(%rsp)
movss %xmm1, 344(%rsp)
movss %xmm0, 348(%rsp)
movl $64, %edi
call malloc@PLT
movq %rax, %r14
movq $0, 44(%rsp)
movl $0, 52(%rsp)
movl $4, 32(%rsp)
movl $4, 36(%rsp)
movl $4, 40(%rsp)
leaq 48(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 224(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 76(%rsp)
movl $0, 84(%rsp)
movl $4, 64(%rsp)
movl $4, 68(%rsp)
movl $4, 72(%rsp)
leaq 80(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 288(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 108(%rsp)
movl $0, 116(%rsp)
movl $4, 96(%rsp)
movl $4, 100(%rsp)
movl $4, 104(%rsp)
leaq 112(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $2, 20(%rsp)
movl $2, 24(%rsp)
movl $2, 8(%rsp)
movl $2, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movl $64, %edx
movq 112(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq 16(%r14), %rbp
movl $0, %r13d
leaq .LC16(%rip), %r12
leaq .LC17(%rip), %r15
.L15:
leaq -16(%rbp), %rbx
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $4, %r13d
addq $16, %rbp
cmpl $16, %r13d
jne .L15
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movdqa 32(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movdqa 64(%rsp), %xmm2
movaps %xmm2, 160(%rsp)
movq 80(%rsp), %rax
movq %rax, 176(%rsp)
movdqa 96(%rsp), %xmm3
movaps %xmm3, 192(%rsp)
movq 112(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rdx
leaq 160(%rsp), %rsi
leaq 128(%rsp), %rdi
call _Z31__device_stub__Z6matmul3matS_S_R3matS0_S0_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z6matmul3matS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmul3matS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.align 4
.LC2:
.long 1077936128
.align 4
.LC3:
.long 1082130432
.align 4
.LC4:
.long 1084227584
.align 4
.LC5:
.long 1086324736
.align 4
.LC6:
.long 1088421888
.align 4
.LC7:
.long 1090519040
.align 4
.LC8:
.long 1091567616
.align 4
.LC9:
.long 1092616192
.align 4
.LC10:
.long 1093664768
.align 4
.LC11:
.long 1094713344
.align 4
.LC12:
.long 1095761920
.align 4
.LC13:
.long 1096810496
.align 4
.LC14:
.long 1097859072
.align 4
.LC15:
.long 1098907648
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task42.hip"
.globl _Z21__device_stub__matmul3matS_S_ # -- Begin function _Z21__device_stub__matmul3matS_S_
.p2align 4, 0x90
.type _Z21__device_stub__matmul3matS_S_,@function
_Z21__device_stub__matmul3matS_S_: # @_Z21__device_stub__matmul3matS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6matmul3matS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__matmul3matS_S_, .Lfunc_end0-_Z21__device_stub__matmul3matS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI1_1:
.long 0x40a00000 # float 5
.long 0x40c00000 # float 6
.long 0x40e00000 # float 7
.long 0x41000000 # float 8
.LCPI1_2:
.long 0x41100000 # float 9
.long 0x41200000 # float 10
.long 0x41300000 # float 11
.long 0x41400000 # float 12
.LCPI1_3:
.long 0x41500000 # float 13
.long 0x41600000 # float 14
.long 0x41700000 # float 15
.long 0x41800000 # float 16
.LCPI1_4:
.long 0x41800000 # float 16
.long 0x41700000 # float 15
.long 0x41600000 # float 14
.long 0x41500000 # float 13
.LCPI1_5:
.long 0x41400000 # float 12
.long 0x41300000 # float 11
.long 0x41200000 # float 10
.long 0x41100000 # float 9
.LCPI1_6:
.long 0x41000000 # float 8
.long 0x40e00000 # float 7
.long 0x40c00000 # float 6
.long 0x40a00000 # float 5
.LCPI1_7:
.long 0x40800000 # float 4
.long 0x40400000 # float 3
.long 0x40000000 # float 2
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 320(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [5.0E+0,6.0E+0,7.0E+0,8.0E+0]
movaps %xmm0, 336(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [9.0E+0,1.0E+1,1.1E+1,1.2E+1]
movaps %xmm0, 352(%rsp)
movaps .LCPI1_3(%rip), %xmm0 # xmm0 = [1.3E+1,1.4E+1,1.5E+1,1.6E+1]
movaps %xmm0, 368(%rsp)
movaps .LCPI1_4(%rip), %xmm0 # xmm0 = [1.6E+1,1.5E+1,1.4E+1,1.3E+1]
movaps %xmm0, 256(%rsp)
movaps .LCPI1_5(%rip), %xmm0 # xmm0 = [1.2E+1,1.1E+1,1.0E+1,9.0E+0]
movaps %xmm0, 272(%rsp)
movaps .LCPI1_6(%rip), %xmm0 # xmm0 = [8.0E+0,7.0E+0,6.0E+0,5.0E+0]
movaps %xmm0, 288(%rsp)
movaps .LCPI1_7(%rip), %xmm0 # xmm0 = [4.0E+0,3.0E+0,2.0E+0,1.0E+0]
movaps %xmm0, 304(%rsp)
movl $64, %edi
callq malloc
movq %rax, %rbx
movabsq $17179869188, %r14 # imm = 0x400000004
movq %r14, 56(%rsp)
movl $4, 64(%rsp)
leaq 72(%rsp), %rdi
movq $0, 72(%rsp)
movl $64, %esi
callq hipMalloc
movq 72(%rsp), %rdi
leaq 320(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, 32(%rsp)
movl $4, 40(%rsp)
leaq 48(%rsp), %rdi
movq $0, 48(%rsp)
movl $64, %esi
callq hipMalloc
movq 48(%rsp), %rdi
leaq 256(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq %r14, 8(%rsp)
movl $4, 16(%rsp)
leaq 24(%rsp), %rdi
movq $0, 24(%rsp)
movl $64, %esi
callq hipMalloc
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 72(%rsp), %rax
movq %rax, 176(%rsp)
movups 56(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 48(%rsp), %rax
movq %rax, 208(%rsp)
movups 32(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 24(%rsp), %rax
movq %rax, 240(%rsp)
movups 8(%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6matmul3matS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
movl $64, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %r15
cmpq $4, %r14
jne .LBB1_3
# %bb.6:
movq 72(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmul3matS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmul3matS_S_,@object # @_Z6matmul3matS_S_
.section .rodata,"a",@progbits
.globl _Z6matmul3matS_S_
.p2align 3, 0x0
_Z6matmul3matS_S_:
.quad _Z21__device_stub__matmul3matS_S_
.size _Z6matmul3matS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmul3matS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmul3matS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmul3matS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <string>
#include <vector>
#include <iostream>
using namespace std;
int main() {
string str = "\002banana\003";
vector<string> table;
for (int i = 0; i < str.length(); i++) {
string temp = str.substr(i, str.length()) + str.substr(0, i);
table.push_back(temp);
}
thrust::device_vector<char*> device_table;
for (int i = 0; i < table.size(); i++) {
char* temp;
cudaMalloc((void**)&temp, sizeof(char) * (str.length() + 1));
cudaMemcpy(temp, table[i].c_str(), sizeof(char) * (str.length() + 1), cudaMemcpyHostToDevice);
device_table.push_back(temp);
}
thrust::sort(device_table.begin(), device_table.end());
char* result;
cudaMallocHost((void**)&result, sizeof(char) * (device_table.size() + 1));
for (int i = 0; i < device_table.size(); i++) {
char* temp;
cudaMallocHost((void**)&temp, sizeof(char) * (str.length() + 1));
cudaMemcpy(temp, device_table[i], sizeof(char) * (str.length() + 1), cudaMemcpyDeviceToHost);
result[i] = temp[str.length() - 1];
cudaFreeHost(temp);
}
cout << result << endl;
for (int i = 0; i < device_table.size(); i++) {
cudaFree(device_table[i]);
}
cudaFreeHost(result);
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
#include <string>
#include <vector>
#include <iostream>
using namespace std;
int main() {
string str = "\002banana\003";
vector<string> table;
for (int i = 0; i < str.length(); i++) {
string temp = str.substr(i, str.length()) + str.substr(0, i);
table.push_back(temp);
}
thrust::device_vector<char*> device_table;
for (int i = 0; i < table.size(); i++) {
char* temp;
hipMalloc((void**)&temp, sizeof(char) * (str.length() + 1));
hipMemcpy(temp, table[i].c_str(), sizeof(char) * (str.length() + 1), hipMemcpyHostToDevice);
device_table.push_back(temp);
}
thrust::sort(device_table.begin(), device_table.end());
char* result;
hipHostMalloc((void**)&result, sizeof(char) * (device_table.size() + 1), hipHostMallocDefault);
for (int i = 0; i < device_table.size(); i++) {
char* temp;
hipHostMalloc((void**)&temp, sizeof(char) * (str.length() + 1), hipHostMallocDefault);
hipMemcpy(temp, device_table[i], sizeof(char) * (str.length() + 1), hipMemcpyDeviceToHost);
result[i] = temp[str.length() - 1];
hipHostFree(temp);
}
cout << result << endl;
for (int i = 0; i < device_table.size(); i++) {
hipFree(device_table[i]);
}
hipHostFree(result);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
comp = var_5 * var_6 / (+1.4955E35f + var_7);
for (int i=0; i < var_3; ++i) {
comp = (+1.9220E34f - sqrtf(+1.6696E-5f));
var_8[i] = -1.2810E-44f;
var_9[i] = (var_10 / +1.9766E-35f);
comp += var_9[i] - var_8[i] * (+0.0f - (var_11 * +1.5211E-44f));
}
if (comp < (var_12 / (var_13 + var_14 / (var_15 - (+0.0f + var_16))))) {
comp = (-1.9038E-41f - acosf(var_17 / -0.0f / -0.0f - (+0.0f - (-0.0f * var_18))));
comp += (+1.8471E-42f / +1.0305E35f + -1.8905E35f);
comp = (var_19 / var_20 / -1.2833E-35f / var_21 - +1.5192E-42f);
comp += (+1.9975E-41f / var_22 / var_23 - (var_24 / var_25 + var_26));
}
for (int i=0; i < var_4; ++i) {
float tmp_1 = (var_27 + +0.0f);
comp += tmp_1 - floorf(fmodf(coshf(+1.8288E-42f), (-0.0f + var_28 / sqrtf((var_29 * -1.5462E-11f / var_30 / var_31 * +1.9347E36f / var_32)))));
comp += +1.2492E-43f * +1.1390E7f;
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0014860d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
.type _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff, @function
_Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movl %ecx, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 4(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 464(%rsp), %rax
movq %rax, 288(%rsp)
leaq 472(%rsp), %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
leaq 520(%rsp), %rax
movq %rax, 344(%rsp)
leaq 528(%rsp), %rax
movq %rax, 352(%rsp)
leaq 536(%rsp), %rax
movq %rax, 360(%rsp)
leaq 544(%rsp), %rax
movq %rax, 368(%rsp)
leaq 552(%rsp), %rax
movq %rax, 376(%rsp)
leaq 560(%rsp), %rax
movq %rax, 384(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 424
pushq 72(%rsp)
.cfi_def_cfa_offset 432
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiiifffPfS_fffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff, .-_Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
.globl _Z7computefiiiifffPfS_fffffffffffffffffffffff
.type _Z7computefiiiifffPfS_fffffffffffffffffffffff, @function
_Z7computefiiiifffPfS_fffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiiifffPfS_fffffffffffffffffffffff, .-_Z7computefiiiifffPfS_fffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 208(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
subq $160, %rsp
.cfi_def_cfa_offset 480
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 312(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 320(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 328(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 336(%rsp), %xmm4
movq %r15, %r9
movq %r14, %r8
pxor %xmm3, %xmm3
cvtsd2ss 344(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 352(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 360(%rsp), %xmm1
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl 368(%rsp), %edi
call _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
addq $160, %rsp
.cfi_def_cfa_offset 320
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiiifffPfS_fffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiiifffPfS_fffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
comp = var_5 * var_6 / (+1.4955E35f + var_7);
for (int i=0; i < var_3; ++i) {
comp = (+1.9220E34f - sqrtf(+1.6696E-5f));
var_8[i] = -1.2810E-44f;
var_9[i] = (var_10 / +1.9766E-35f);
comp += var_9[i] - var_8[i] * (+0.0f - (var_11 * +1.5211E-44f));
}
if (comp < (var_12 / (var_13 + var_14 / (var_15 - (+0.0f + var_16))))) {
comp = (-1.9038E-41f - acosf(var_17 / -0.0f / -0.0f - (+0.0f - (-0.0f * var_18))));
comp += (+1.8471E-42f / +1.0305E35f + -1.8905E35f);
comp = (var_19 / var_20 / -1.2833E-35f / var_21 - +1.5192E-42f);
comp += (+1.9975E-41f / var_22 / var_23 - (var_24 / var_25 + var_26));
}
for (int i=0; i < var_4; ++i) {
float tmp_1 = (var_27 + +0.0f);
comp += tmp_1 - floorf(fmodf(coshf(+1.8288E-42f), (-0.0f + var_28 / sqrtf((var_29 * -1.5462E-11f / var_30 / var_31 * +1.9347E36f / var_32)))));
comp += +1.2492E-43f * +1.1390E7f;
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
comp = var_5 * var_6 / (+1.4955E35f + var_7);
for (int i=0; i < var_3; ++i) {
comp = (+1.9220E34f - sqrtf(+1.6696E-5f));
var_8[i] = -1.2810E-44f;
var_9[i] = (var_10 / +1.9766E-35f);
comp += var_9[i] - var_8[i] * (+0.0f - (var_11 * +1.5211E-44f));
}
if (comp < (var_12 / (var_13 + var_14 / (var_15 - (+0.0f + var_16))))) {
comp = (-1.9038E-41f - acosf(var_17 / -0.0f / -0.0f - (+0.0f - (-0.0f * var_18))));
comp += (+1.8471E-42f / +1.0305E35f + -1.8905E35f);
comp = (var_19 / var_20 / -1.2833E-35f / var_21 - +1.5192E-42f);
comp += (+1.9975E-41f / var_22 / var_23 - (var_24 / var_25 + var_26));
}
for (int i=0; i < var_4; ++i) {
float tmp_1 = (var_27 + +0.0f);
comp += tmp_1 - floorf(fmodf(coshf(+1.8288E-42f), (-0.0f + var_28 / sqrtf((var_29 * -1.5462E-11f / var_30 / var_31 * +1.9347E36f / var_32)))));
comp += +1.2492E-43f * +1.1390E7f;
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,int var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
for (int i=0; i < var_1; ++i) {
for (int i=0; i < var_2; ++i) {
comp = var_5 * var_6 / (+1.4955E35f + var_7);
for (int i=0; i < var_3; ++i) {
comp = (+1.9220E34f - sqrtf(+1.6696E-5f));
var_8[i] = -1.2810E-44f;
var_9[i] = (var_10 / +1.9766E-35f);
comp += var_9[i] - var_8[i] * (+0.0f - (var_11 * +1.5211E-44f));
}
if (comp < (var_12 / (var_13 + var_14 / (var_15 - (+0.0f + var_16))))) {
comp = (-1.9038E-41f - acosf(var_17 / -0.0f / -0.0f - (+0.0f - (-0.0f * var_18))));
comp += (+1.8471E-42f / +1.0305E35f + -1.8905E35f);
comp = (var_19 / var_20 / -1.2833E-35f / var_21 - +1.5192E-42f);
comp += (+1.9975E-41f / var_22 / var_23 - (var_24 / var_25 + var_26));
}
for (int i=0; i < var_4; ++i) {
float tmp_1 = (var_27 + +0.0f);
comp += tmp_1 - floorf(fmodf(coshf(+1.8288E-42f), (-0.0f + var_28 / sqrtf((var_29 * -1.5462E-11f / var_30 / var_31 * +1.9347E36f / var_32)))));
comp += +1.2492E-43f * +1.1390E7f;
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
int tmp_5 = atoi(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff,@function
_Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff: # @_Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
leaq 384(%rsp), %rax
movq %rax, 224(%rsp)
leaq 392(%rsp), %rax
movq %rax, 232(%rsp)
leaq 400(%rsp), %rax
movq %rax, 240(%rsp)
leaq 408(%rsp), %rax
movq %rax, 248(%rsp)
leaq 416(%rsp), %rax
movq %rax, 256(%rsp)
leaq 424(%rsp), %rax
movq %rax, 264(%rsp)
leaq 432(%rsp), %rax
movq %rax, 272(%rsp)
leaq 440(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 488(%rsp), %rax
movq %rax, 328(%rsp)
leaq 496(%rsp), %rax
movq %rax, 336(%rsp)
leaq 504(%rsp), %rax
movq %rax, 344(%rsp)
leaq 512(%rsp), %rax
movq %rax, 352(%rsp)
leaq 520(%rsp), %rax
movq %rax, 360(%rsp)
leaq 528(%rsp), %rax
movq %rax, 368(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiiifffPfS_fffffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 448
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movq 8(%rsi), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 16(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 384(%rsp) # 8-byte Spill
movq 24(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 376(%rsp) # 8-byte Spill
movq 32(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 48(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 56(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 64(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 72(%rbp), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 80(%rbp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $10, %r14
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit70
movq 88(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 96(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 104(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 112(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 120(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 128(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 136(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 144(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 152(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 160(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 168(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 176(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 184(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 192(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 200(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 208(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 216(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 224(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 232(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 240(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 248(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 256(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 264(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 144(%rsp)
movss %xmm9, 136(%rsp)
movss %xmm10, 128(%rsp)
movss %xmm11, 120(%rsp)
movss %xmm12, 112(%rsp)
movss %xmm13, 104(%rsp)
movss %xmm14, 96(%rsp)
movss %xmm15, 88(%rsp)
movss %xmm2, 80(%rsp)
movss %xmm3, 72(%rsp)
movss %xmm4, 64(%rsp)
movss %xmm5, 56(%rsp)
movss %xmm6, 48(%rsp)
movss %xmm7, 40(%rsp)
movss 168(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 32(%rsp)
movss 176(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 24(%rsp)
movss 184(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 16(%rsp)
movss 192(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 8(%rsp)
movss 200(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, (%rsp)
movq 384(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movq 376(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movl %r15d, %edx
movl %r12d, %ecx
movss 240(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 232(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movq %r13, %r8
movq %rbx, %r9
movss 160(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 216(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 208(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiiifffPfS_fffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiiifffPfS_fffffffffffffffffffffff,@object # @_Z7computefiiiifffPfS_fffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiiiifffPfS_fffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefiiiifffPfS_fffffffffffffffffffffff:
.quad _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.size _Z7computefiiiifffPfS_fffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiiifffPfS_fffffffffffffffffffffff"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiiifffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014860d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
.type _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff, @function
_Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movl %ecx, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 4(%rsp), %rax
movq %rax, 224(%rsp)
movq %rsp, %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 464(%rsp), %rax
movq %rax, 288(%rsp)
leaq 472(%rsp), %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
leaq 520(%rsp), %rax
movq %rax, 344(%rsp)
leaq 528(%rsp), %rax
movq %rax, 352(%rsp)
leaq 536(%rsp), %rax
movq %rax, 360(%rsp)
leaq 544(%rsp), %rax
movq %rax, 368(%rsp)
leaq 552(%rsp), %rax
movq %rax, 376(%rsp)
leaq 560(%rsp), %rax
movq %rax, 384(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 424
pushq 72(%rsp)
.cfi_def_cfa_offset 432
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiiifffPfS_fffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff, .-_Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
.globl _Z7computefiiiifffPfS_fffffffffffffffffffffff
.type _Z7computefiiiifffPfS_fffffffffffffffffffffff, @function
_Z7computefiiiifffPfS_fffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiiifffPfS_fffffffffffffffffffffff, .-_Z7computefiiiifffPfS_fffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 208(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 40(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
subq $160, %rsp
.cfi_def_cfa_offset 480
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 312(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 320(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 328(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 336(%rsp), %xmm4
movq %r15, %r9
movq %r14, %r8
pxor %xmm3, %xmm3
cvtsd2ss 344(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 352(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 360(%rsp), %xmm1
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl 368(%rsp), %edi
call _Z59__device_stub__Z7computefiiiifffPfS_ffffffffffffffffffffffffiiiifffPfS_fffffffffffffffffffffff
addq $160, %rsp
.cfi_def_cfa_offset 320
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiiifffPfS_fffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiiifffPfS_fffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff,@function
_Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff: # @_Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
movq %rsp, %rax
movq %rax, 216(%rsp)
leaq 384(%rsp), %rax
movq %rax, 224(%rsp)
leaq 392(%rsp), %rax
movq %rax, 232(%rsp)
leaq 400(%rsp), %rax
movq %rax, 240(%rsp)
leaq 408(%rsp), %rax
movq %rax, 248(%rsp)
leaq 416(%rsp), %rax
movq %rax, 256(%rsp)
leaq 424(%rsp), %rax
movq %rax, 264(%rsp)
leaq 432(%rsp), %rax
movq %rax, 272(%rsp)
leaq 440(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 488(%rsp), %rax
movq %rax, 328(%rsp)
leaq 496(%rsp), %rax
movq %rax, 336(%rsp)
leaq 504(%rsp), %rax
movq %rax, 344(%rsp)
leaq 512(%rsp), %rax
movq %rax, 352(%rsp)
leaq 520(%rsp), %rax
movq %rax, 360(%rsp)
leaq 528(%rsp), %rax
movq %rax, 368(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiiifffPfS_fffffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 448
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
movq 8(%rsi), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 16(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 384(%rsp) # 8-byte Spill
movq 24(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 376(%rsp) # 8-byte Spill
movq 32(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 48(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 56(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 64(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 72(%rbp), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 80(%rbp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $10, %r14
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit70
movq 88(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 96(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 104(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 112(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 120(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 128(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 136(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 144(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 152(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 160(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 168(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 176(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 184(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 192(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 200(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 208(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 216(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 224(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 232(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 240(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 248(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 256(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 264(%rbp), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 144(%rsp)
movss %xmm9, 136(%rsp)
movss %xmm10, 128(%rsp)
movss %xmm11, 120(%rsp)
movss %xmm12, 112(%rsp)
movss %xmm13, 104(%rsp)
movss %xmm14, 96(%rsp)
movss %xmm15, 88(%rsp)
movss %xmm2, 80(%rsp)
movss %xmm3, 72(%rsp)
movss %xmm4, 64(%rsp)
movss %xmm5, 56(%rsp)
movss %xmm6, 48(%rsp)
movss %xmm7, 40(%rsp)
movss 168(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 32(%rsp)
movss 176(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 24(%rsp)
movss 184(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 16(%rsp)
movss 192(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, 8(%rsp)
movss 200(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss %xmm2, (%rsp)
movq 384(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movq 376(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movl %r15d, %edx
movl %r12d, %ecx
movss 240(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 232(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movq %r13, %r8
movq %rbx, %r9
movss 160(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 216(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 208(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiiifffPfS_fffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiiifffPfS_fffffffffffffffffffffff,@object # @_Z7computefiiiifffPfS_fffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiiiifffPfS_fffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefiiiifffPfS_fffffffffffffffffffffff:
.quad _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.size _Z7computefiiiifffPfS_fffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiiifffPfS_fffffffffffffffffffffff"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiiifffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiiifffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define BLOCK_SIZE 16
/*
*********************************************************************
function name: inicializarMatrizRandom
descripcion: inicializa aleatoriamente los elementos de una matriz
parametros:
- M: puntero a la matriz a inicializar
- m: numero de filas de A
- n: numero de columnas de A
*********************************************************************
*/
void inicializarMatrizRandom (float *M, int m, int n){
int i;
for (i = 0; i < m*n; i++) {
M[i] = rand() % 10;
}
}
/*
*********************************************************************
funcion: gpu_matrix_mult
descripcion: producto de dos matrices sin caches en GPU (no necesariamente cuadradas)
parametros:
- a,b,c: punteros a las matrices con las que operar en GPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
__global__ void gpu_matrix_mult(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
/*
*********************************************************************
funcion: gpu_square_matrix_mult
descripcion: producto de dos matrices utilizando caches en GPU (matriz cuadrada)
parametros:
- d_a,d_b,d_result: punteros a las matrices device con las que operar en GPU
- n: numero de columnas de A (se presupone que la matriz sera cuadrada)
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(float *d_a, float *d_b, float *d_result, int n)
{
__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
float tmp = 0.0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if(idx >= n*n)
{
tile_a[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if(idx >= n*n)
{
tile_b[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if(row < n && col < n)
{
d_result[row * n + col] = tmp;
}
}
/*
*********************************************************************
funcion: cpu_matrix_mult
descripcion: producto de dos matrices (no necesariamente cuadradas) en CPU.
parametros:
- h_a,h_b,h_result: punteros a las matrices host con las que operar en CPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int m, int n, int k) {
/*
*********************************************************************
Version IKJ (secuencial optimizada)
*********************************************************************
*/
float r=0.0;
int i;
int j;
int h;
for (i=0; i< m; i++)
for (j=0; j< k; j++)
h_result[i*k+j] = 0;
for (i=0; i<m; i++)
for (h=0; h<n; h++) {
r = h_a[i*n+h];
for (j=0; j<k; j++)
h_result[i*k+j]+= r * h_b[h*k+j];
}
/*
*********************************************************************
Version IJK (secuencial original)
*********************************************************************
*/
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
{
float tmp = 0.0;
for (int h = 0; h < n; ++h)
{
tmp += h_a[i * n + h] * h_b[h * k + j];
}
h_result[i * k + j] = tmp;
}
}
}
int main(int argc, char const *argv[])
{
int m, n, k;
if(argc < 4 || argc > 4){
fprintf(stderr,"Uso: filas matriz A, columnas matriz A, columnas matriz B\n");
exit(-1);
}
// Recogemos los parámetros de ejecución relativos al tamaño de las matrices
m = atoi(argv[1]);
n = atoi(argv[2]);
k = atoi(argv[3]);
// Reservamos memoria para almacenar las matrices en host y su posterior multiplicación en CPU
float *h_a, *h_b, *h_c, *h_cc;
h_a=(float*)malloc(sizeof(float)*m*n);
h_b=(float*)malloc(sizeof(float)*n*k);
h_c=(float*)malloc(sizeof(float)*m*k);
h_cc=(float*)malloc(sizeof(float)*m*k);
// Inicializamos las matrices con valores decimales aleatorios
inicializarMatrizRandom (h_a, m, n);
inicializarMatrizRandom (h_b, n, k);
// Creamos cudaEvents para medir los tiempos de ejeución en CPU y GPU.
float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Reservamos memoria para almacenar las matrices en device y su posterior multiplicación en GPU
float *d_a, *d_b, *d_c;
cudaMalloc((void **) &d_a, sizeof(float)*m*n);
cudaMalloc((void **) &d_b, sizeof(float)*n*k);
cudaMalloc((void **) &d_c, sizeof(float)*m*k);
cudaMemcpy(d_a, h_a, sizeof(float)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sizeof(float)*n*k, cudaMemcpyHostToDevice);
// Establecemos las dimensiones del Grid (Rejilla) y el Bloque
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
// If y else para elegir entre ejecución sin caches o con caches (memoria sin compartir o compartida)
if(m == n && n == k){
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
}
else{
gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
}
cudaMemcpy(h_c, d_c, sizeof(float)*m*k, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en GPU
cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n", m, n, n, k, gpu_elapsed_time_ms/1000);
cudaEventRecord(start, 0);
cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en CPU
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n", m, n, n, k, cpu_elapsed_time_ms/1000);
// Comprobamos que los resultados de la multiplicación son correctos
int all_ok = 1;
for (int i = 0; i < m; ++i){
for (int j = 0; j < k; ++j){
if(h_cc[i*k + j] != h_c[i*k + j])
{
all_ok = 0;
}
}
}
// Calculamos el speedup empleado respecto a la CPU
if(all_ok){
printf("CORRECTO!, Speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
}
else{
printf("INCORRECTO\n");
}
// Liberamos la memoria reservada anteriormente
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFreeHost(h_cc);
return 0;
} | code for sm_80
Function : _Z22gpu_square_matrix_multPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0xc], PT ; /* 0x00000300ff007a0c */
/* 0x000fe20003f25270 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R17, SR_TID.X ; /* 0x0000000000117919 */
/* 0x000e280000002100 */
/*0060*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ LEA R3, R4, R17, 0x4 ; /* 0x0000001104037211 */
/* 0x001fc800078e20ff */
/*0090*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f06270 */
/*00a0*/ LEA R0, R0, R2, 0x4 ; /* 0x0000000200007211 */
/* 0x002fc800078e20ff */
/*00b0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fe20000706670 */
/*00c0*/ @!P1 BRA 0x4e0 ; /* 0x0000041000009947 */
/* 0x000fd80003800000 */
/*00d0*/ IMAD R16, R2.reuse, c[0x0][0x178], R17.reuse ; /* 0x00005e0002107a24 */
/* 0x140fe200078e0211 */
/*00e0*/ SHF.L.U32 R2, R2, 0x6, RZ ; /* 0x0000000602027819 */
/* 0x000fe200000006ff */
/*00f0*/ IMAD R18, R0, c[0x0][0x178], R17 ; /* 0x00005e0000127a24 */
/* 0x000fe200078e0211 */
/*0100*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fe20000000f00 */
/*0110*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0120*/ LEA R16, R4, R16, 0x4 ; /* 0x0000001004107211 */
/* 0x000fe200078e20ff */
/*0130*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0140*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe40000000f00 */
/*0150*/ LEA R20, R17, R2, 0x2 ; /* 0x0000000211147211 */
/* 0x000fc600078e10ff */
/*0160*/ ISETP.GE.AND P1, PT, R18, UR4, PT ; /* 0x0000000412007c0c */
/* 0x000fe2000bf26270 */
/*0170*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0180*/ ISETP.GE.AND P2, PT, R16, UR4, PT ; /* 0x0000000410007c0c */
/* 0x000fc4000bf46270 */
/*0190*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fd20000000f00 */
/*01a0*/ @!P1 MOV R5, 0x4 ; /* 0x0000000400059802 */
/* 0x000fe40000000f00 */
/*01b0*/ @!P2 MOV R11, 0x4 ; /* 0x00000004000ba802 */
/* 0x000fc60000000f00 */
/*01c0*/ @!P1 IMAD.WIDE R4, R18, R5, c[0x0][0x160] ; /* 0x0000580012049625 */
/* 0x000fc800078e0205 */
/*01d0*/ @!P2 IMAD.WIDE R10, R16, R11, c[0x0][0x168] ; /* 0x00005a00100aa625 */
/* 0x000fe200078e020b */
/*01e0*/ @!P1 LDG.E R21, [R4.64] ; /* 0x0000000604159981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ @!P2 LDG.E R27, [R10.64] ; /* 0x000000060a1ba981 */
/* 0x000ee2000c1e1900 */
/*0200*/ IADD3 R19, R19, 0x1, RZ ; /* 0x0000000113137810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P1, PT, R19, c[0x0][0xc], PT ; /* 0x0000030013007a0c */
/* 0x000fe20003f26070 */
/*0230*/ STS [R20], R21 ; /* 0x0000001514007388 */
/* 0x004fe80000000800 */
/*0240*/ STS [R20+0x400], R27 ; /* 0x0004001b14007388 */
/* 0x008fe80000000800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ LDS R8, [R17.X4+0x400] ; /* 0x0004000011087984 */
/* 0x000fe80000004800 */
/*0270*/ LDS.128 R12, [R2] ; /* 0x00000000020c7984 */
/* 0x000e280000000c00 */
/*0280*/ LDS R28, [R17.X4+0x440] ; /* 0x00044000111c7984 */
/* 0x000e680000004800 */
/*0290*/ LDS R29, [R17.X4+0x480] ; /* 0x00048000111d7984 */
/* 0x000ea80000004800 */
/*02a0*/ LDS R24, [R17.X4+0x4c0] ; /* 0x0004c00011187984 */
/* 0x000ee80000004800 */
/*02b0*/ LDS R25, [R17.X4+0x500] ; /* 0x0005000011197984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS.128 R4, [R2+0x10] ; /* 0x0000100002047984 */
/* 0x000f280000000c00 */
/*02d0*/ LDS R26, [R17.X4+0x540] ; /* 0x00054000111a7984 */
/* 0x000f680000004800 */
/*02e0*/ LDS R23, [R17.X4+0x580] ; /* 0x0005800011177984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R22, [R17.X4+0x5c0] ; /* 0x0005c00011167984 */
/* 0x000f680000004800 */
/*0300*/ LDS R21, [R17.X4+0x600] ; /* 0x0006000011157984 */
/* 0x000fe20000004800 */
/*0310*/ FFMA R8, R8, R12, R9 ; /* 0x0000000c08087223 */
/* 0x001fc80000000009 */
/*0320*/ FFMA R13, R28, R13, R8 ; /* 0x0000000d1c0d7223 */
/* 0x002fe40000000008 */
/*0330*/ LDS.128 R8, [R2+0x20] ; /* 0x0000200002087984 */
/* 0x000e240000000c00 */
/*0340*/ FFMA R13, R29, R14, R13 ; /* 0x0000000e1d0d7223 */
/* 0x004fc8000000000d */
/*0350*/ FFMA R13, R24, R15, R13 ; /* 0x0000000f180d7223 */
/* 0x008fe4000000000d */
/*0360*/ LDS R24, [R17.X4+0x640] ; /* 0x0006400011187984 */
/* 0x000e640000004800 */
/*0370*/ FFMA R4, R25, R4, R13 ; /* 0x0000000419047223 */
/* 0x010fe4000000000d */
/*0380*/ LDS R25, [R17.X4+0x680] ; /* 0x0006800011197984 */
/* 0x000ea40000004800 */
/*0390*/ FFMA R5, R26, R5, R4 ; /* 0x000000051a057223 */
/* 0x020fe40000000004 */
/*03a0*/ LDS R4, [R17.X4+0x6c0] ; /* 0x0006c00011047984 */
/* 0x000ee40000004800 */
/*03b0*/ FFMA R23, R23, R6, R5 ; /* 0x0000000617177223 */
/* 0x000fc40000000005 */
/*03c0*/ LDS R5, [R17.X4+0x700] ; /* 0x0007000011057984 */
/* 0x000fe40000004800 */
/*03d0*/ FFMA R23, R22, R7, R23 ; /* 0x0000000716177223 */
/* 0x000fe40000000017 */
/*03e0*/ LDS.128 R12, [R2+0x30] ; /* 0x00003000020c7984 */
/* 0x000f280000000c00 */
/*03f0*/ LDS R6, [R17.X4+0x740] ; /* 0x0007400011067984 */
/* 0x000f680000004800 */
/*0400*/ LDS R7, [R17.X4+0x780] ; /* 0x0007800011077984 */
/* 0x000f680000004800 */
/*0410*/ LDS R22, [R17.X4+0x7c0] ; /* 0x0007c00011167984 */
/* 0x000f620000004800 */
/*0420*/ FFMA R8, R21, R8, R23 ; /* 0x0000000815087223 */
/* 0x001fc80000000017 */
/*0430*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc80000000008 */
/*0440*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x004fc80000000008 */
/*0450*/ FFMA R4, R4, R11, R8 ; /* 0x0000000b04047223 */
/* 0x008fc80000000008 */
/*0460*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x010fe20000000004 */
/*0470*/ MOV R5, c[0x0][0x178] ; /* 0x00005e0000057a02 */
/* 0x000fc60000000f00 */
/*0480*/ FFMA R4, R6, R13, R4 ; /* 0x0000000d06047223 */
/* 0x020fe20000000004 */
/*0490*/ LEA R16, R5, R16, 0x4 ; /* 0x0000001005107211 */
/* 0x000fc600078e20ff */
/*04a0*/ FFMA R4, R7, R14, R4 ; /* 0x0000000e07047223 */
/* 0x000fc80000000004 */
/*04b0*/ FFMA R9, R22, R15, R4 ; /* 0x0000000f16097223 */
/* 0x000fe20000000004 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*04d0*/ @!P1 BRA 0x160 ; /* 0xfffffc8000009947 */
/* 0x000fea000383ffff */
/*04e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0500*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fd200078e0203 */
/*0510*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0520*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101906 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15gpu_matrix_multPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x180], R0 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define BLOCK_SIZE 16
/*
*********************************************************************
function name: inicializarMatrizRandom
descripcion: inicializa aleatoriamente los elementos de una matriz
parametros:
- M: puntero a la matriz a inicializar
- m: numero de filas de A
- n: numero de columnas de A
*********************************************************************
*/
void inicializarMatrizRandom (float *M, int m, int n){
int i;
for (i = 0; i < m*n; i++) {
M[i] = rand() % 10;
}
}
/*
*********************************************************************
funcion: gpu_matrix_mult
descripcion: producto de dos matrices sin caches en GPU (no necesariamente cuadradas)
parametros:
- a,b,c: punteros a las matrices con las que operar en GPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
__global__ void gpu_matrix_mult(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
/*
*********************************************************************
funcion: gpu_square_matrix_mult
descripcion: producto de dos matrices utilizando caches en GPU (matriz cuadrada)
parametros:
- d_a,d_b,d_result: punteros a las matrices device con las que operar en GPU
- n: numero de columnas de A (se presupone que la matriz sera cuadrada)
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(float *d_a, float *d_b, float *d_result, int n)
{
__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
float tmp = 0.0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if(idx >= n*n)
{
tile_a[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if(idx >= n*n)
{
tile_b[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if(row < n && col < n)
{
d_result[row * n + col] = tmp;
}
}
/*
*********************************************************************
funcion: cpu_matrix_mult
descripcion: producto de dos matrices (no necesariamente cuadradas) en CPU.
parametros:
- h_a,h_b,h_result: punteros a las matrices host con las que operar en CPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int m, int n, int k) {
/*
*********************************************************************
Version IKJ (secuencial optimizada)
*********************************************************************
*/
float r=0.0;
int i;
int j;
int h;
for (i=0; i< m; i++)
for (j=0; j< k; j++)
h_result[i*k+j] = 0;
for (i=0; i<m; i++)
for (h=0; h<n; h++) {
r = h_a[i*n+h];
for (j=0; j<k; j++)
h_result[i*k+j]+= r * h_b[h*k+j];
}
/*
*********************************************************************
Version IJK (secuencial original)
*********************************************************************
*/
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
{
float tmp = 0.0;
for (int h = 0; h < n; ++h)
{
tmp += h_a[i * n + h] * h_b[h * k + j];
}
h_result[i * k + j] = tmp;
}
}
}
int main(int argc, char const *argv[])
{
int m, n, k;
if(argc < 4 || argc > 4){
fprintf(stderr,"Uso: filas matriz A, columnas matriz A, columnas matriz B\n");
exit(-1);
}
// Recogemos los parámetros de ejecución relativos al tamaño de las matrices
m = atoi(argv[1]);
n = atoi(argv[2]);
k = atoi(argv[3]);
// Reservamos memoria para almacenar las matrices en host y su posterior multiplicación en CPU
float *h_a, *h_b, *h_c, *h_cc;
h_a=(float*)malloc(sizeof(float)*m*n);
h_b=(float*)malloc(sizeof(float)*n*k);
h_c=(float*)malloc(sizeof(float)*m*k);
h_cc=(float*)malloc(sizeof(float)*m*k);
// Inicializamos las matrices con valores decimales aleatorios
inicializarMatrizRandom (h_a, m, n);
inicializarMatrizRandom (h_b, n, k);
// Creamos cudaEvents para medir los tiempos de ejeución en CPU y GPU.
float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Reservamos memoria para almacenar las matrices en device y su posterior multiplicación en GPU
float *d_a, *d_b, *d_c;
cudaMalloc((void **) &d_a, sizeof(float)*m*n);
cudaMalloc((void **) &d_b, sizeof(float)*n*k);
cudaMalloc((void **) &d_c, sizeof(float)*m*k);
cudaMemcpy(d_a, h_a, sizeof(float)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sizeof(float)*n*k, cudaMemcpyHostToDevice);
// Establecemos las dimensiones del Grid (Rejilla) y el Bloque
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
// If y else para elegir entre ejecución sin caches o con caches (memoria sin compartir o compartida)
if(m == n && n == k){
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
}
else{
gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
}
cudaMemcpy(h_c, d_c, sizeof(float)*m*k, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en GPU
cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n", m, n, n, k, gpu_elapsed_time_ms/1000);
cudaEventRecord(start, 0);
cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en CPU
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n", m, n, n, k, cpu_elapsed_time_ms/1000);
// Comprobamos que los resultados de la multiplicación son correctos
int all_ok = 1;
for (int i = 0; i < m; ++i){
for (int j = 0; j < k; ++j){
if(h_cc[i*k + j] != h_c[i*k + j])
{
all_ok = 0;
}
}
}
// Calculamos el speedup empleado respecto a la CPU
if(all_ok){
printf("CORRECTO!, Speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
}
else{
printf("INCORRECTO\n");
}
// Liberamos la memoria reservada anteriormente
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFreeHost(h_cc);
return 0;
} | .file "tmpxft_0019f1f2_00000000-6_matmulCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23inicializarMatrizRandomPfii
.type _Z23inicializarMatrizRandomPfii, @function
_Z23inicializarMatrizRandomPfii:
.LFB2057:
.cfi_startproc
endbr64
imull %edx, %esi
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z23inicializarMatrizRandomPfii, .-_Z23inicializarMatrizRandomPfii
.globl _Z15cpu_matrix_multPfS_S_iii
.type _Z15cpu_matrix_multPfS_S_iii, @function
_Z15cpu_matrix_multPfS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L39
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r11
movq %rsi, %rbx
movq %rdx, %rbp
movl %ecx, %edi
movl %r8d, %r10d
movl %r9d, %edx
movl $0, %esi
movl $0, %r9d
movslq %edx, %r8
jmp .L13
.L16:
movslq %esi, %rcx
leaq 0(%rbp,%rcx,4), %rax
addq %r8, %rcx
leaq 0(%rbp,%rcx,4), %rcx
.L14:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L14
.L17:
leal 1(%r9), %eax
addl %edx, %esi
cmpl %eax, %edi
je .L15
movl %eax, %r9d
.L13:
testl %edx, %edx
jg .L16
jmp .L17
.L15:
movl %r9d, -24(%rsp)
movl $0, %r14d
movl $0, %r13d
movl $0, %ecx
movslq %r10d, %r15
movslq %edx, %rax
movq %rax, -16(%rsp)
movq %r15, %rsi
jmp .L18
.L23:
movslq %r13d, %rax
leaq (%r11,%rax,4), %r8
addq %rsi, %rax
leaq (%r11,%rax,4), %r12
movslq %r14d, %rax
leaq 0(%rbp,%rax,4), %r15
movq -16(%rsp), %rdi
addq %rdi, %rax
leaq 0(%rbp,%rax,4), %rdi
movl $0, %r9d
movl %ecx, -20(%rsp)
.L21:
movss (%r8), %xmm1
testl %edx, %edx
jle .L19
movslq %r9d, %rax
leaq (%rbx,%rax,4), %rcx
movq %r15, %rax
.L20:
movaps %xmm1, %xmm0
mulss (%rcx), %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
addq $4, %rcx
cmpq %rdi, %rax
jne .L20
.L19:
addq $4, %r8
addl %edx, %r9d
cmpq %r12, %r8
jne .L21
movl -20(%rsp), %ecx
.L24:
leal 1(%rcx), %eax
addl %r10d, %r13d
addl %edx, %r14d
cmpl %ecx, -24(%rsp)
je .L22
movl %eax, %ecx
.L18:
testl %r10d, %r10d
jg .L23
jmp .L24
.L22:
movslq %edx, %r13
leaq 0(,%r13,4), %rsi
movl $0, %r14d
movl $0, %r15d
movl $0, %eax
movslq %r10d, %rdi
movq %rdi, -16(%rsp)
movq %rbx, -8(%rsp)
movq %rbp, %rdi
jmp .L25
.L26:
movss (%rax), %xmm0
mulss (%rcx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rcx
cmpq %r8, %rax
jne .L26
.L28:
movss %xmm1, 0(%rbp,%r9,4)
addq $1, %r9
addq $4, %rbx
cmpq %r9, %r13
je .L36
.L29:
movq %rbx, %rcx
movq %r12, %rax
pxor %xmm1, %xmm1
testl %r10d, %r10d
jg .L26
jmp .L28
.L36:
movl -20(%rsp), %eax
.L27:
leal 1(%rax), %ecx
addl %edx, %r15d
addl %r10d, %r14d
cmpl %eax, -24(%rsp)
je .L11
movl %ecx, %eax
.L25:
testl %edx, %edx
jle .L27
movq -8(%rsp), %rbx
movslq %r14d, %rcx
leaq (%r11,%rcx,4), %r12
movq -16(%rsp), %r9
addq %r9, %rcx
leaq (%r11,%rcx,4), %r8
movslq %r15d, %rcx
leaq (%rdi,%rcx,4), %rbp
movl $0, %r9d
movl %eax, -20(%rsp)
jmp .L29
.L11:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z15cpu_matrix_multPfS_S_iii, .-_Z15cpu_matrix_multPfS_S_iii
.globl _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15gpu_matrix_multPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
.globl _Z15gpu_matrix_multPfS_S_iii
.type _Z15gpu_matrix_multPfS_S_iii, @function
_Z15gpu_matrix_multPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15gpu_matrix_multPfS_S_iii, .-_Z15gpu_matrix_multPfS_S_iii
.globl _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
.type _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22gpu_square_matrix_multPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
.globl _Z22gpu_square_matrix_multPfS_S_i
.type _Z22gpu_square_matrix_multPfS_S_i, @function
_Z22gpu_square_matrix_multPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z22gpu_square_matrix_multPfS_S_i, .-_Z22gpu_square_matrix_multPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Uso: filas matriz A, columnas matriz A, columnas matriz B\n"
.align 8
.LC3:
.string "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n"
.align 8
.LC4:
.string "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "CORRECTO!, Speedup = %f\n"
.LC6:
.string "INCORRECTO\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $4, %edi
jne .L76
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 12(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r13d
movq %r14, 40(%rsp)
movslq 40(%rsp), %rbx
movq %rbp, 32(%rsp)
movslq 32(%rsp), %r14
movq %rbx, %rsi
imulq %r14, %rsi
leaq 0(,%rsi,4), %rsi
movq %rsi, 48(%rsp)
movq %rsi, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movslq %r15d, %rbp
imulq %rbp, %r14
leaq 0(,%r14,4), %rdx
movq %rdx, 56(%rsp)
movq %rdx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
imulq %rbp, %rbx
leaq 0(,%rbx,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl 12(%rsp), %edx
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z23inicializarMatrizRandomPfii
movl %r15d, %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z23inicializarMatrizRandomPfii
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
leaq 88(%rsp), %rdi
movq 48(%rsp), %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq 56(%rsp), %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 48(%rsp), %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 56(%rsp), %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leal 30(%r15), %eax
movl %r15d, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 112(%rsp)
movq 40(%rsp), %rcx
leal 30(%rcx), %eax
movl %ecx, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
movl $16, 124(%rsp)
movl $16, 128(%rsp)
movl $1, 132(%rsp)
movq 32(%rsp), %rax
cmpl %ecx, %eax
jne .L60
cmpl %eax, %r15d
jne .L60
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L61:
movl $2, %ecx
movq %r14, %rdx
movq 104(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 64(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 64(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %r9d
movq 32(%rsp), %r14
movl %r14d, %r8d
movl 12(%rsp), %ecx
movl %r12d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %r9d
movl %r14d, %r8d
movl %r12d, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z15cpu_matrix_multPfS_S_iii
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 68(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %r9d
movl %r14d, %r8d
movl 12(%rsp), %ecx
movl %r12d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
jle .L62
movl %r15d, %r10d
movl $0, %r8d
movl $0, %edi
movl $1, %ecx
leal -1(%r15), %r9d
addq $1, %r9
movl $0, %esi
jmp .L63
.L76:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L77:
movl 12(%rsp), %ecx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
jmp .L61
.L60:
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl 120(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L61
movl %r15d, %r9d
movl 32(%rsp), %r8d
movl %r12d, %ecx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
jmp .L61
.L73:
movl %esi, %ecx
.L64:
addq $4, %rax
cmpq %rdx, %rax
je .L69
.L66:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L73
je .L64
jmp .L73
.L69:
addl $1, %edi
addl %r10d, %r8d
cmpl %r12d, %edi
je .L67
.L63:
testl %r13d, %r13d
jle .L69
movslq %r8d, %rdx
leaq 0(,%rdx,4), %rax
addq %r9, %rdx
salq $2, %rdx
jmp .L66
.L67:
testl %ecx, %ecx
jne .L62
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L71
.L62:
movss 68(%rsp), %xmm0
divss 64(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L71:
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbp, %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call cudaFreeHost@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L78
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z22gpu_square_matrix_multPfS_S_i"
.section .rodata.str1.1
.LC8:
.string "_Z15gpu_matrix_multPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_square_matrix_multPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gpu_matrix_multPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define BLOCK_SIZE 16
/*
*********************************************************************
function name: inicializarMatrizRandom
descripcion: inicializa aleatoriamente los elementos de una matriz
parametros:
- M: puntero a la matriz a inicializar
- m: numero de filas de A
- n: numero de columnas de A
*********************************************************************
*/
void inicializarMatrizRandom (float *M, int m, int n){
int i;
for (i = 0; i < m*n; i++) {
M[i] = rand() % 10;
}
}
/*
*********************************************************************
funcion: gpu_matrix_mult
descripcion: producto de dos matrices sin caches en GPU (no necesariamente cuadradas)
parametros:
- a,b,c: punteros a las matrices con las que operar en GPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
__global__ void gpu_matrix_mult(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
/*
*********************************************************************
funcion: gpu_square_matrix_mult
descripcion: producto de dos matrices utilizando caches en GPU (matriz cuadrada)
parametros:
- d_a,d_b,d_result: punteros a las matrices device con las que operar en GPU
- n: numero de columnas de A (se presupone que la matriz sera cuadrada)
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(float *d_a, float *d_b, float *d_result, int n)
{
__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
float tmp = 0.0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if(idx >= n*n)
{
tile_a[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if(idx >= n*n)
{
tile_b[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if(row < n && col < n)
{
d_result[row * n + col] = tmp;
}
}
/*
*********************************************************************
funcion: cpu_matrix_mult
descripcion: producto de dos matrices (no necesariamente cuadradas) en CPU.
parametros:
- h_a,h_b,h_result: punteros a las matrices host con las que operar en CPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int m, int n, int k) {
/*
*********************************************************************
Version IKJ (secuencial optimizada)
*********************************************************************
*/
float r=0.0;
int i;
int j;
int h;
for (i=0; i< m; i++)
for (j=0; j< k; j++)
h_result[i*k+j] = 0;
for (i=0; i<m; i++)
for (h=0; h<n; h++) {
r = h_a[i*n+h];
for (j=0; j<k; j++)
h_result[i*k+j]+= r * h_b[h*k+j];
}
/*
*********************************************************************
Version IJK (secuencial original)
*********************************************************************
*/
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
{
float tmp = 0.0;
for (int h = 0; h < n; ++h)
{
tmp += h_a[i * n + h] * h_b[h * k + j];
}
h_result[i * k + j] = tmp;
}
}
}
int main(int argc, char const *argv[])
{
int m, n, k;
if(argc < 4 || argc > 4){
fprintf(stderr,"Uso: filas matriz A, columnas matriz A, columnas matriz B\n");
exit(-1);
}
// Recogemos los parámetros de ejecución relativos al tamaño de las matrices
m = atoi(argv[1]);
n = atoi(argv[2]);
k = atoi(argv[3]);
// Reservamos memoria para almacenar las matrices en host y su posterior multiplicación en CPU
float *h_a, *h_b, *h_c, *h_cc;
h_a=(float*)malloc(sizeof(float)*m*n);
h_b=(float*)malloc(sizeof(float)*n*k);
h_c=(float*)malloc(sizeof(float)*m*k);
h_cc=(float*)malloc(sizeof(float)*m*k);
// Inicializamos las matrices con valores decimales aleatorios
inicializarMatrizRandom (h_a, m, n);
inicializarMatrizRandom (h_b, n, k);
// Creamos cudaEvents para medir los tiempos de ejeución en CPU y GPU.
float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
// Reservamos memoria para almacenar las matrices en device y su posterior multiplicación en GPU
float *d_a, *d_b, *d_c;
cudaMalloc((void **) &d_a, sizeof(float)*m*n);
cudaMalloc((void **) &d_b, sizeof(float)*n*k);
cudaMalloc((void **) &d_c, sizeof(float)*m*k);
cudaMemcpy(d_a, h_a, sizeof(float)*m*n, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sizeof(float)*n*k, cudaMemcpyHostToDevice);
// Establecemos las dimensiones del Grid (Rejilla) y el Bloque
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
// If y else para elegir entre ejecución sin caches o con caches (memoria sin compartir o compartida)
if(m == n && n == k){
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
}
else{
gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
}
cudaMemcpy(h_c, d_c, sizeof(float)*m*k, cudaMemcpyDeviceToHost);
cudaThreadSynchronize();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en GPU
cudaEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n", m, n, n, k, gpu_elapsed_time_ms/1000);
cudaEventRecord(start, 0);
cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en CPU
cudaEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n", m, n, n, k, cpu_elapsed_time_ms/1000);
// Comprobamos que los resultados de la multiplicación son correctos
int all_ok = 1;
for (int i = 0; i < m; ++i){
for (int j = 0; j < k; ++j){
if(h_cc[i*k + j] != h_c[i*k + j])
{
all_ok = 0;
}
}
}
// Calculamos el speedup empleado respecto a la CPU
if(all_ok){
printf("CORRECTO!, Speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
}
else{
printf("INCORRECTO\n");
}
// Liberamos la memoria reservada anteriormente
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
cudaFreeHost(h_cc);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define BLOCK_SIZE 16
/*
*********************************************************************
function name: inicializarMatrizRandom
descripcion: inicializa aleatoriamente los elementos de una matriz
parametros:
- M: puntero a la matriz a inicializar
- m: numero de filas de A
- n: numero de columnas de A
*********************************************************************
*/
void inicializarMatrizRandom (float *M, int m, int n){
int i;
for (i = 0; i < m*n; i++) {
M[i] = rand() % 10;
}
}
/*
*********************************************************************
funcion: gpu_matrix_mult
descripcion: producto de dos matrices sin caches en GPU (no necesariamente cuadradas)
parametros:
- a,b,c: punteros a las matrices con las que operar en GPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
__global__ void gpu_matrix_mult(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
/*
*********************************************************************
funcion: gpu_square_matrix_mult
descripcion: producto de dos matrices utilizando caches en GPU (matriz cuadrada)
parametros:
- d_a,d_b,d_result: punteros a las matrices device con las que operar en GPU
- n: numero de columnas de A (se presupone que la matriz sera cuadrada)
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(float *d_a, float *d_b, float *d_result, int n)
{
__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
float tmp = 0.0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if(idx >= n*n)
{
tile_a[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if(idx >= n*n)
{
tile_b[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if(row < n && col < n)
{
d_result[row * n + col] = tmp;
}
}
/*
*********************************************************************
funcion: cpu_matrix_mult
descripcion: producto de dos matrices (no necesariamente cuadradas) en CPU.
parametros:
- h_a,h_b,h_result: punteros a las matrices host con las que operar en CPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int m, int n, int k) {
/*
*********************************************************************
Version IKJ (secuencial optimizada)
*********************************************************************
*/
float r=0.0;
int i;
int j;
int h;
for (i=0; i< m; i++)
for (j=0; j< k; j++)
h_result[i*k+j] = 0;
for (i=0; i<m; i++)
for (h=0; h<n; h++) {
r = h_a[i*n+h];
for (j=0; j<k; j++)
h_result[i*k+j]+= r * h_b[h*k+j];
}
/*
*********************************************************************
Version IJK (secuencial original)
*********************************************************************
*/
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
{
float tmp = 0.0;
for (int h = 0; h < n; ++h)
{
tmp += h_a[i * n + h] * h_b[h * k + j];
}
h_result[i * k + j] = tmp;
}
}
}
int main(int argc, char const *argv[])
{
int m, n, k;
if(argc < 4 || argc > 4){
fprintf(stderr,"Uso: filas matriz A, columnas matriz A, columnas matriz B\n");
exit(-1);
}
// Recogemos los parámetros de ejecución relativos al tamaño de las matrices
m = atoi(argv[1]);
n = atoi(argv[2]);
k = atoi(argv[3]);
// Reservamos memoria para almacenar las matrices en host y su posterior multiplicación en CPU
float *h_a, *h_b, *h_c, *h_cc;
h_a=(float*)malloc(sizeof(float)*m*n);
h_b=(float*)malloc(sizeof(float)*n*k);
h_c=(float*)malloc(sizeof(float)*m*k);
h_cc=(float*)malloc(sizeof(float)*m*k);
// Inicializamos las matrices con valores decimales aleatorios
inicializarMatrizRandom (h_a, m, n);
inicializarMatrizRandom (h_b, n, k);
// Creamos cudaEvents para medir los tiempos de ejeución en CPU y GPU.
float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Reservamos memoria para almacenar las matrices en device y su posterior multiplicación en GPU
float *d_a, *d_b, *d_c;
hipMalloc((void **) &d_a, sizeof(float)*m*n);
hipMalloc((void **) &d_b, sizeof(float)*n*k);
hipMalloc((void **) &d_c, sizeof(float)*m*k);
hipMemcpy(d_a, h_a, sizeof(float)*m*n, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sizeof(float)*n*k, hipMemcpyHostToDevice);
// Establecemos las dimensiones del Grid (Rejilla) y el Bloque
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
// If y else para elegir entre ejecución sin caches o con caches (memoria sin compartir o compartida)
if(m == n && n == k){
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
}
else{
gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
}
hipMemcpy(h_c, d_c, sizeof(float)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en GPU
hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n", m, n, n, k, gpu_elapsed_time_ms/1000);
hipEventRecord(start, 0);
cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en CPU
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n", m, n, n, k, cpu_elapsed_time_ms/1000);
// Comprobamos que los resultados de la multiplicación son correctos
int all_ok = 1;
for (int i = 0; i < m; ++i){
for (int j = 0; j < k; ++j){
if(h_cc[i*k + j] != h_c[i*k + j])
{
all_ok = 0;
}
}
}
// Calculamos el speedup empleado respecto a la CPU
if(all_ok){
printf("CORRECTO!, Speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
}
else{
printf("INCORRECTO\n");
}
// Liberamos la memoria reservada anteriormente
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipHostFree(h_cc);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define BLOCK_SIZE 16
/*
*********************************************************************
function name: inicializarMatrizRandom
descripcion: inicializa aleatoriamente los elementos de una matriz
parametros:
- M: puntero a la matriz a inicializar
- m: numero de filas de A
- n: numero de columnas de A
*********************************************************************
*/
void inicializarMatrizRandom (float *M, int m, int n){
int i;
for (i = 0; i < m*n; i++) {
M[i] = rand() % 10;
}
}
/*
*********************************************************************
funcion: gpu_matrix_mult
descripcion: producto de dos matrices sin caches en GPU (no necesariamente cuadradas)
parametros:
- a,b,c: punteros a las matrices con las que operar en GPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
__global__ void gpu_matrix_mult(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
/*
*********************************************************************
funcion: gpu_square_matrix_mult
descripcion: producto de dos matrices utilizando caches en GPU (matriz cuadrada)
parametros:
- d_a,d_b,d_result: punteros a las matrices device con las que operar en GPU
- n: numero de columnas de A (se presupone que la matriz sera cuadrada)
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(float *d_a, float *d_b, float *d_result, int n)
{
__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
float tmp = 0.0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if(idx >= n*n)
{
tile_a[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if(idx >= n*n)
{
tile_b[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if(row < n && col < n)
{
d_result[row * n + col] = tmp;
}
}
/*
*********************************************************************
funcion: cpu_matrix_mult
descripcion: producto de dos matrices (no necesariamente cuadradas) en CPU.
parametros:
- h_a,h_b,h_result: punteros a las matrices host con las que operar en CPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int m, int n, int k) {
/*
*********************************************************************
Version IKJ (secuencial optimizada)
*********************************************************************
*/
float r=0.0;
int i;
int j;
int h;
for (i=0; i< m; i++)
for (j=0; j< k; j++)
h_result[i*k+j] = 0;
for (i=0; i<m; i++)
for (h=0; h<n; h++) {
r = h_a[i*n+h];
for (j=0; j<k; j++)
h_result[i*k+j]+= r * h_b[h*k+j];
}
/*
*********************************************************************
Version IJK (secuencial original)
*********************************************************************
*/
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
{
float tmp = 0.0;
for (int h = 0; h < n; ++h)
{
tmp += h_a[i * n + h] * h_b[h * k + j];
}
h_result[i * k + j] = tmp;
}
}
}
int main(int argc, char const *argv[])
{
int m, n, k;
if(argc < 4 || argc > 4){
fprintf(stderr,"Uso: filas matriz A, columnas matriz A, columnas matriz B\n");
exit(-1);
}
// Recogemos los parámetros de ejecución relativos al tamaño de las matrices
m = atoi(argv[1]);
n = atoi(argv[2]);
k = atoi(argv[3]);
// Reservamos memoria para almacenar las matrices en host y su posterior multiplicación en CPU
float *h_a, *h_b, *h_c, *h_cc;
h_a=(float*)malloc(sizeof(float)*m*n);
h_b=(float*)malloc(sizeof(float)*n*k);
h_c=(float*)malloc(sizeof(float)*m*k);
h_cc=(float*)malloc(sizeof(float)*m*k);
// Inicializamos las matrices con valores decimales aleatorios
inicializarMatrizRandom (h_a, m, n);
inicializarMatrizRandom (h_b, n, k);
// Creamos cudaEvents para medir los tiempos de ejeución en CPU y GPU.
float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Reservamos memoria para almacenar las matrices en device y su posterior multiplicación en GPU
float *d_a, *d_b, *d_c;
hipMalloc((void **) &d_a, sizeof(float)*m*n);
hipMalloc((void **) &d_b, sizeof(float)*n*k);
hipMalloc((void **) &d_c, sizeof(float)*m*k);
hipMemcpy(d_a, h_a, sizeof(float)*m*n, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sizeof(float)*n*k, hipMemcpyHostToDevice);
// Establecemos las dimensiones del Grid (Rejilla) y el Bloque
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
// If y else para elegir entre ejecución sin caches o con caches (memoria sin compartir o compartida)
if(m == n && n == k){
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
}
else{
gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
}
hipMemcpy(h_c, d_c, sizeof(float)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en GPU
hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n", m, n, n, k, gpu_elapsed_time_ms/1000);
hipEventRecord(start, 0);
cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en CPU
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n", m, n, n, k, cpu_elapsed_time_ms/1000);
// Comprobamos que los resultados de la multiplicación son correctos
int all_ok = 1;
for (int i = 0; i < m; ++i){
for (int j = 0; j < k; ++j){
if(h_cc[i*k + j] != h_c[i*k + j])
{
all_ok = 0;
}
}
}
// Calculamos el speedup empleado respecto a la CPU
if(all_ok){
printf("CORRECTO!, Speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
}
else{
printf("INCORRECTO\n");
}
// Liberamos la memoria reservada anteriormente
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipHostFree(h_cc);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15gpu_matrix_multPfS_S_iii
.globl _Z15gpu_matrix_multPfS_S_iii
.p2align 8
.type _Z15gpu_matrix_multPfS_S_iii,@function
_Z15gpu_matrix_multPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15gpu_matrix_multPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15gpu_matrix_multPfS_S_iii, .Lfunc_end0-_Z15gpu_matrix_multPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22gpu_square_matrix_multPfS_S_i
.globl _Z22gpu_square_matrix_multPfS_S_i
.p2align 8
.type _Z22gpu_square_matrix_multPfS_S_i,@function
_Z22gpu_square_matrix_multPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v6, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 4, v6
v_lshl_add_u32 v0, s14, 4, v3
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB1_13
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b32_e32 v7, 6, v6
v_mad_u64_u32 v[1:2], null, v4, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mov_b32 v11, 0 :: v_dual_add_nc_u32 v8, 0x400, v5
v_add_nc_u32_e32 v9, v7, v5
s_mul_i32 s9, s2, s2
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, v8, v7
.LBB1_2:
s_lshl_b32 s10, s8, 4
s_mov_b32 s11, exec_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s10, v1
v_cmpx_le_i32_e64 s9, v2
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB1_4
ds_store_b32 v9, v11
.LBB1_4:
s_and_not1_saveexec_b32 s11, s11
s_cbranch_execz .LBB1_6
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v2
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v12, s10, v6
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v12, s2, v[0:1]
v_cmpx_le_i32_e64 s9, v2
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB1_8
ds_store_b32 v10, v11
.LBB1_8:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB1_10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v2
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v2, v8
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_11:
v_add_nc_u32_e32 v3, s10, v7
s_add_i32 s10, s10, 4
ds_load_b32 v12, v2
ds_load_b32 v3, v3
v_add_nc_u32_e32 v2, 64, v2
s_cmp_eq_u32 s10, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v3, v12
s_cbranch_scc0 .LBB1_11
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_14
.LBB1_13:
v_mov_b32_e32 v5, 0
.LBB1_14:
v_max_i32_e32 v1, v4, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_16
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB1_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22gpu_square_matrix_multPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22gpu_square_matrix_multPfS_S_i, .Lfunc_end1-_Z22gpu_square_matrix_multPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15gpu_matrix_multPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15gpu_matrix_multPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22gpu_square_matrix_multPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22gpu_square_matrix_multPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#define BLOCK_SIZE 16
/*
*********************************************************************
function name: inicializarMatrizRandom
descripcion: inicializa aleatoriamente los elementos de una matriz
parametros:
- M: puntero a la matriz a inicializar
- m: numero de filas de A
- n: numero de columnas de A
*********************************************************************
*/
void inicializarMatrizRandom (float *M, int m, int n){
int i;
for (i = 0; i < m*n; i++) {
M[i] = rand() % 10;
}
}
/*
*********************************************************************
funcion: gpu_matrix_mult
descripcion: producto de dos matrices sin caches en GPU (no necesariamente cuadradas)
parametros:
- a,b,c: punteros a las matrices con las que operar en GPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
__global__ void gpu_matrix_mult(float *a,float *b, float *c, int m, int n, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.0;
if( col < k && row < m)
{
for(int i = 0; i < n; i++)
{
sum += a[row * n + i] * b[i * k + col];
}
c[row * k + col] = sum;
}
}
/*
*********************************************************************
funcion: gpu_square_matrix_mult
descripcion: producto de dos matrices utilizando caches en GPU (matriz cuadrada)
parametros:
- d_a,d_b,d_result: punteros a las matrices device con las que operar en GPU
- n: numero de columnas de A (se presupone que la matriz sera cuadrada)
*********************************************************************
*/
__global__ void gpu_square_matrix_mult(float *d_a, float *d_b, float *d_result, int n)
{
__shared__ float tile_a[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float tile_b[BLOCK_SIZE][BLOCK_SIZE];
int row = blockIdx.y * BLOCK_SIZE + threadIdx.y;
int col = blockIdx.x * BLOCK_SIZE + threadIdx.x;
float tmp = 0.0;
int idx;
for (int sub = 0; sub < gridDim.x; ++sub)
{
idx = row * n + sub * BLOCK_SIZE + threadIdx.x;
if(idx >= n*n)
{
tile_a[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_a[threadIdx.y][threadIdx.x] = d_a[idx];
}
idx = (sub * BLOCK_SIZE + threadIdx.y) * n + col;
if(idx >= n*n)
{
tile_b[threadIdx.y][threadIdx.x] = 0.0;
}
else
{
tile_b[threadIdx.y][threadIdx.x] = d_b[idx];
}
__syncthreads();
for (int k = 0; k < BLOCK_SIZE; ++k)
{
tmp += tile_a[threadIdx.y][k] * tile_b[k][threadIdx.x];
}
__syncthreads();
}
if(row < n && col < n)
{
d_result[row * n + col] = tmp;
}
}
/*
*********************************************************************
funcion: cpu_matrix_mult
descripcion: producto de dos matrices (no necesariamente cuadradas) en CPU.
parametros:
- h_a,h_b,h_result: punteros a las matrices host con las que operar en CPU
- m: numero de filas de A
- n: numero de columnas de A
- k: numero de columnas de B
*********************************************************************
*/
void cpu_matrix_mult(float *h_a, float *h_b, float *h_result, int m, int n, int k) {
/*
*********************************************************************
Version IKJ (secuencial optimizada)
*********************************************************************
*/
float r=0.0;
int i;
int j;
int h;
for (i=0; i< m; i++)
for (j=0; j< k; j++)
h_result[i*k+j] = 0;
for (i=0; i<m; i++)
for (h=0; h<n; h++) {
r = h_a[i*n+h];
for (j=0; j<k; j++)
h_result[i*k+j]+= r * h_b[h*k+j];
}
/*
*********************************************************************
Version IJK (secuencial original)
*********************************************************************
*/
for (int i = 0; i < m; ++i)
{
for (int j = 0; j < k; ++j)
{
float tmp = 0.0;
for (int h = 0; h < n; ++h)
{
tmp += h_a[i * n + h] * h_b[h * k + j];
}
h_result[i * k + j] = tmp;
}
}
}
int main(int argc, char const *argv[])
{
int m, n, k;
if(argc < 4 || argc > 4){
fprintf(stderr,"Uso: filas matriz A, columnas matriz A, columnas matriz B\n");
exit(-1);
}
// Recogemos los parámetros de ejecución relativos al tamaño de las matrices
m = atoi(argv[1]);
n = atoi(argv[2]);
k = atoi(argv[3]);
// Reservamos memoria para almacenar las matrices en host y su posterior multiplicación en CPU
float *h_a, *h_b, *h_c, *h_cc;
h_a=(float*)malloc(sizeof(float)*m*n);
h_b=(float*)malloc(sizeof(float)*n*k);
h_c=(float*)malloc(sizeof(float)*m*k);
h_cc=(float*)malloc(sizeof(float)*m*k);
// Inicializamos las matrices con valores decimales aleatorios
inicializarMatrizRandom (h_a, m, n);
inicializarMatrizRandom (h_b, n, k);
// Creamos cudaEvents para medir los tiempos de ejeución en CPU y GPU.
float gpu_elapsed_time_ms, cpu_elapsed_time_ms;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
// Reservamos memoria para almacenar las matrices en device y su posterior multiplicación en GPU
float *d_a, *d_b, *d_c;
hipMalloc((void **) &d_a, sizeof(float)*m*n);
hipMalloc((void **) &d_b, sizeof(float)*n*k);
hipMalloc((void **) &d_c, sizeof(float)*m*k);
hipMemcpy(d_a, h_a, sizeof(float)*m*n, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sizeof(float)*n*k, hipMemcpyHostToDevice);
// Establecemos las dimensiones del Grid (Rejilla) y el Bloque
unsigned int grid_rows = (m + BLOCK_SIZE - 1) / BLOCK_SIZE;
unsigned int grid_cols = (k + BLOCK_SIZE - 1) / BLOCK_SIZE;
dim3 dimGrid(grid_cols, grid_rows);
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
// If y else para elegir entre ejecución sin caches o con caches (memoria sin compartir o compartida)
if(m == n && n == k){
gpu_square_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, n);
}
else{
gpu_matrix_mult<<<dimGrid, dimBlock>>>(d_a, d_b, d_c, m, n, k);
}
hipMemcpy(h_c, d_c, sizeof(float)*m*k, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en GPU
hipEventElapsedTime(&gpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n", m, n, n, k, gpu_elapsed_time_ms/1000);
hipEventRecord(start, 0);
cpu_matrix_mult(h_a, h_b, h_cc, m, n, k);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
// Medimos el tiempo empleado en ejecutar la multiplicación en CPU
hipEventElapsedTime(&cpu_elapsed_time_ms, start, stop);
printf("Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n", m, n, n, k, cpu_elapsed_time_ms/1000);
// Comprobamos que los resultados de la multiplicación son correctos
int all_ok = 1;
for (int i = 0; i < m; ++i){
for (int j = 0; j < k; ++j){
if(h_cc[i*k + j] != h_c[i*k + j])
{
all_ok = 0;
}
}
}
// Calculamos el speedup empleado respecto a la CPU
if(all_ok){
printf("CORRECTO!, Speedup = %f\n", cpu_elapsed_time_ms / gpu_elapsed_time_ms);
}
else{
printf("INCORRECTO\n");
}
// Liberamos la memoria reservada anteriormente
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
hipHostFree(h_cc);
return 0;
} | .text
.file "matmulCUDA.hip"
.globl _Z23inicializarMatrizRandomPfii # -- Begin function _Z23inicializarMatrizRandomPfii
.p2align 4, 0x90
.type _Z23inicializarMatrizRandomPfii,@function
_Z23inicializarMatrizRandomPfii: # @_Z23inicializarMatrizRandomPfii
.cfi_startproc
# %bb.0:
imull %edx, %esi
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z23inicializarMatrizRandomPfii, .Lfunc_end0-_Z23inicializarMatrizRandomPfii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_matrix_multPfS_S_iii # -- Begin function _Z30__device_stub__gpu_matrix_multPfS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__gpu_matrix_multPfS_S_iii,@function
_Z30__device_stub__gpu_matrix_multPfS_S_iii: # @_Z30__device_stub__gpu_matrix_multPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15gpu_matrix_multPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__gpu_matrix_multPfS_S_iii, .Lfunc_end1-_Z30__device_stub__gpu_matrix_multPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__gpu_square_matrix_multPfS_S_i # -- Begin function _Z37__device_stub__gpu_square_matrix_multPfS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__gpu_square_matrix_multPfS_S_i,@function
_Z37__device_stub__gpu_square_matrix_multPfS_S_i: # @_Z37__device_stub__gpu_square_matrix_multPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22gpu_square_matrix_multPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z37__device_stub__gpu_square_matrix_multPfS_S_i, .Lfunc_end2-_Z37__device_stub__gpu_square_matrix_multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z15cpu_matrix_multPfS_S_iii # -- Begin function _Z15cpu_matrix_multPfS_S_iii
.p2align 4, 0x90
.type _Z15cpu_matrix_multPfS_S_iii,@function
_Z15cpu_matrix_multPfS_S_iii: # @_Z15cpu_matrix_multPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movq %rdx, (%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, 24(%rsp) # 8-byte Spill
movl %r9d, %r12d
movl %ecx, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl %ecx, 20(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB3_5
# %bb.1: # %.preheader70.lr.ph
leaq (,%r12,4), %rax
movq %rax, 32(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movq 8(%rsp), %r13 # 8-byte Reload
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
addl %ebx, %r14d
decq %r13
je .LBB3_5
.LBB3_2: # %.preheader70
# =>This Inner Loop Header: Depth=1
testl %ebx, %ebx
jle .LBB3_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdi
xorl %esi, %esi
movq 32(%rsp), %rdx # 8-byte Reload
callq memset@PLT
jmp .LBB3_4
.LBB3_5: # %.preheader69
movl %ebp, %eax
movl 20(%rsp), %r14d # 4-byte Reload
testl %r14d, %r14d
jle .LBB3_14
# %bb.6: # %.preheader68.lr.ph
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_13: # %._crit_edge79
# in Loop: Header=BB3_7 Depth=1
incq %rdx
addl %ebx, %ecx
cmpq 8(%rsp), %rdx # 8-byte Folded Reload
je .LBB3_14
.LBB3_7: # %.preheader68
# =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
# Child Loop BB3_11 Depth 3
testl %ebp, %ebp
jle .LBB3_13
# %bb.8: # %.lr.ph78
# in Loop: Header=BB3_7 Depth=1
movl %ecx, %esi
movq (%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rsi,4), %rsi
movl %edx, %edi
imull %ebp, %edi
movq 24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_12: # %._crit_edge76
# in Loop: Header=BB3_9 Depth=2
incq %r9
addl %ebx, %r8d
cmpq %rax, %r9
je .LBB3_13
.LBB3_9: # Parent Loop BB3_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_11 Depth 3
testl %ebx, %ebx
jle .LBB3_12
# %bb.10: # %.lr.ph75
# in Loop: Header=BB3_9 Depth=2
movl %r8d, %r10d
leaq (%r15,%r10,4), %r10
movss (%rdi,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_7 Depth=1
# Parent Loop BB3_9 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rsi,%r11,4), %xmm1
movss %xmm1, (%rsi,%r11,4)
incq %r11
cmpq %r11, %r12
jne .LBB3_11
jmp .LBB3_12
.LBB3_14: # %.preheader67
testl %r14d, %r14d
jle .LBB3_23
# %bb.15: # %.preheader66.lr.ph
movslq %ebx, %rcx
leaq (,%rcx,4), %rdx
xorl %esi, %esi
xorl %edi, %edi
jmp .LBB3_16
.p2align 4, 0x90
.LBB3_22: # %._crit_edge86
# in Loop: Header=BB3_16 Depth=1
incq %rdi
addl %ebp, %esi
cmpq 8(%rsp), %rdi # 8-byte Folded Reload
je .LBB3_23
.LBB3_16: # %.preheader66
# =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
# Child Loop BB3_20 Depth 3
testl %ebx, %ebx
jle .LBB3_22
# %bb.17: # %.preheader.lr.ph
# in Loop: Header=BB3_16 Depth=1
movl %esi, %r8d
movq 24(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r8
movq %rdi, %r9
imulq %rcx, %r9
movq (%rsp), %r10 # 8-byte Reload
leaq (%r10,%r9,4), %r9
movq %r15, %r10
xorl %r11d, %r11d
jmp .LBB3_18
.p2align 4, 0x90
.LBB3_21: # %._crit_edge84
# in Loop: Header=BB3_18 Depth=2
movss %xmm0, (%r9,%r11,4)
incq %r11
addq $4, %r10
cmpq %r12, %r11
je .LBB3_22
.LBB3_18: # %.preheader
# Parent Loop BB3_16 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_20 Depth 3
xorps %xmm0, %xmm0
testl %ebp, %ebp
jle .LBB3_21
# %bb.19: # %.lr.ph83.preheader
# in Loop: Header=BB3_18 Depth=2
movq %r10, %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_20: # %.lr.ph83
# Parent Loop BB3_16 Depth=1
# Parent Loop BB3_18 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %rdx, %r14
cmpq %r13, %rax
jne .LBB3_20
jmp .LBB3_21
.LBB3_23: # %._crit_edge88
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15cpu_matrix_multPfS_S_iii, .Lfunc_end3-_Z15cpu_matrix_multPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
jne .LBB4_24
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %rax, 32(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movslq %r15d, %rbp
shlq $2, %rbp
movslq %r14d, %r12
movq %r12, %rdi
imulq %rbp, %rdi
movq %rdi, 224(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movslq %r13d, %r15
imulq %r15, %r12
shlq $2, %r12
movq %r12, 232(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
imulq %r15, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, 160(%rsp) # 8-byte Spill
movq %rbp, 168(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, 152(%rsp) # 8-byte Spill
movq %r14, 240(%rsp) # 8-byte Spill
movl %r14d, %eax
imull 32(%rsp), %eax # 4-byte Folded Reload
testl %eax, %eax
jle .LBB4_4
# %bb.2: # %.lr.ph.preheader.i
movl %eax, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_3
.LBB4_4: # %_Z23inicializarMatrizRandomPfii.exit
movq %rbx, 80(%rsp) # 8-byte Spill
movl %r13d, %eax
movq 240(%rsp), %r14 # 8-byte Reload
imull %r14d, %eax
testl %eax, %eax
movq 72(%rsp), %rbx # 8-byte Reload
jle .LBB4_7
# %bb.5: # %.lr.ph.preheader.i100
movl %eax, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_6: # %.lr.ph.i102
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_6
.LBB4_7: # %_Z23inicializarMatrizRandomPfii.exit106
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 56(%rsp), %rdi
movq 224(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 232(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq 168(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %r15 # 8-byte Reload
leal 15(%r15), %eax
leal 30(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
leal 15(%r13), %eax
leal 30(%r13), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
shlq $32, %rdi
orq %rcx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
cmpl %r14d, %r15d
jne .LBB4_11
# %bb.8: # %_Z23inicializarMatrizRandomPfii.exit106
cmpl %r13d, %r14d
jne .LBB4_11
# %bb.9:
testl %eax, %eax
movq 160(%rsp), %r12 # 8-byte Reload
movq 152(%rsp), %rbp # 8-byte Reload
jne .LBB4_14
# %bb.10:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 4(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z22gpu_square_matrix_multPfS_S_i, %edi
jmp .LBB4_13
.LBB4_11:
testl %eax, %eax
movq 160(%rsp), %r12 # 8-byte Reload
movq 152(%rsp), %rbp # 8-byte Reload
jne .LBB4_14
# %bb.12:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movl %eax, 4(%rsp)
movl %r14d, 148(%rsp)
movl %r13d, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 148(%rsp), %rax
movq %rax, 208(%rsp)
leaq 144(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z15gpu_matrix_multPfS_S_iii, %edi
.LBB4_13:
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq 40(%rsp), %rsi
movq %r12, %rdi
movq 168(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movq 32(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
movl %r14d, %edx
movl %r14d, %ecx
movl %r13d, %r8d
movb $1, %al
callq printf
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi # 8-byte Reload
movq 72(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl %ebx, %ecx
movl %r14d, %r8d
movl %r13d, %r9d
callq _Z15cpu_matrix_multPfS_S_iii
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebx, %esi
movl %r14d, %edx
movl %r14d, %ecx
movl %r13d, %r8d
movb $1, %al
callq printf
testl %ebx, %ebx
jle .LBB4_21
# %bb.15: # %.preheader.lr.ph
movl %ebx, %eax
movl %r13d, %ecx
movl $1, %edx
xorl %esi, %esi
xorl %edi, %edi
jmp .LBB4_16
.p2align 4, 0x90
.LBB4_19: # %._crit_edge
# in Loop: Header=BB4_16 Depth=1
incq %rdi
addl %r13d, %esi
cmpq %rax, %rdi
je .LBB4_20
.LBB4_16: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_18 Depth 2
testl %r13d, %r13d
jle .LBB4_19
# %bb.17: # %.lr.ph
# in Loop: Header=BB4_16 Depth=1
movl %esi, %r9d
leaq (%r12,%r9,4), %r8
leaq (,%r9,4), %r9
addq %rbp, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_16 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r8,%r10,4), %xmm0
cmovnel %r15d, %edx
cmovpl %r15d, %edx
incq %r10
cmpq %r10, %rcx
jne .LBB4_18
jmp .LBB4_19
.LBB4_20: # %._crit_edge125.loopexit
testl %edx, %edx
je .LBB4_22
.LBB4_21: # %.critedge
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 176(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB4_23
.LBB4_22:
movl $.Lstr, %edi
callq puts@PLT
.LBB4_23:
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi # 8-byte Reload
callq hipHostFree
movq 72(%rsp), %rdi # 8-byte Reload
callq hipHostFree
movq %r12, %rdi
callq hipHostFree
movq %rbp, %rdi
callq hipHostFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_24:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $58, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_matrix_multPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_square_matrix_multPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15gpu_matrix_multPfS_S_iii,@object # @_Z15gpu_matrix_multPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z15gpu_matrix_multPfS_S_iii
.p2align 3, 0x0
_Z15gpu_matrix_multPfS_S_iii:
.quad _Z30__device_stub__gpu_matrix_multPfS_S_iii
.size _Z15gpu_matrix_multPfS_S_iii, 8
.type _Z22gpu_square_matrix_multPfS_S_i,@object # @_Z22gpu_square_matrix_multPfS_S_i
.globl _Z22gpu_square_matrix_multPfS_S_i
.p2align 3, 0x0
_Z22gpu_square_matrix_multPfS_S_i:
.quad _Z37__device_stub__gpu_square_matrix_multPfS_S_i
.size _Z22gpu_square_matrix_multPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Uso: filas matriz A, columnas matriz A, columnas matriz B\n"
.size .L.str, 59
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n"
.size .L.str.1, 68
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n"
.size .L.str.2, 68
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CORRECTO!, Speedup = %f\n"
.size .L.str.3, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15gpu_matrix_multPfS_S_iii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22gpu_square_matrix_multPfS_S_i"
.size .L__unnamed_2, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "INCORRECTO"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__gpu_matrix_multPfS_S_iii
.addrsig_sym _Z37__device_stub__gpu_square_matrix_multPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15gpu_matrix_multPfS_S_iii
.addrsig_sym _Z22gpu_square_matrix_multPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019f1f2_00000000-6_matmulCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23inicializarMatrizRandomPfii
.type _Z23inicializarMatrizRandomPfii, @function
_Z23inicializarMatrizRandomPfii:
.LFB2057:
.cfi_startproc
endbr64
imull %edx, %esi
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z23inicializarMatrizRandomPfii, .-_Z23inicializarMatrizRandomPfii
.globl _Z15cpu_matrix_multPfS_S_iii
.type _Z15cpu_matrix_multPfS_S_iii, @function
_Z15cpu_matrix_multPfS_S_iii:
.LFB2058:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L39
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r11
movq %rsi, %rbx
movq %rdx, %rbp
movl %ecx, %edi
movl %r8d, %r10d
movl %r9d, %edx
movl $0, %esi
movl $0, %r9d
movslq %edx, %r8
jmp .L13
.L16:
movslq %esi, %rcx
leaq 0(%rbp,%rcx,4), %rax
addq %r8, %rcx
leaq 0(%rbp,%rcx,4), %rcx
.L14:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L14
.L17:
leal 1(%r9), %eax
addl %edx, %esi
cmpl %eax, %edi
je .L15
movl %eax, %r9d
.L13:
testl %edx, %edx
jg .L16
jmp .L17
.L15:
movl %r9d, -24(%rsp)
movl $0, %r14d
movl $0, %r13d
movl $0, %ecx
movslq %r10d, %r15
movslq %edx, %rax
movq %rax, -16(%rsp)
movq %r15, %rsi
jmp .L18
.L23:
movslq %r13d, %rax
leaq (%r11,%rax,4), %r8
addq %rsi, %rax
leaq (%r11,%rax,4), %r12
movslq %r14d, %rax
leaq 0(%rbp,%rax,4), %r15
movq -16(%rsp), %rdi
addq %rdi, %rax
leaq 0(%rbp,%rax,4), %rdi
movl $0, %r9d
movl %ecx, -20(%rsp)
.L21:
movss (%r8), %xmm1
testl %edx, %edx
jle .L19
movslq %r9d, %rax
leaq (%rbx,%rax,4), %rcx
movq %r15, %rax
.L20:
movaps %xmm1, %xmm0
mulss (%rcx), %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rax)
addq $4, %rax
addq $4, %rcx
cmpq %rdi, %rax
jne .L20
.L19:
addq $4, %r8
addl %edx, %r9d
cmpq %r12, %r8
jne .L21
movl -20(%rsp), %ecx
.L24:
leal 1(%rcx), %eax
addl %r10d, %r13d
addl %edx, %r14d
cmpl %ecx, -24(%rsp)
je .L22
movl %eax, %ecx
.L18:
testl %r10d, %r10d
jg .L23
jmp .L24
.L22:
movslq %edx, %r13
leaq 0(,%r13,4), %rsi
movl $0, %r14d
movl $0, %r15d
movl $0, %eax
movslq %r10d, %rdi
movq %rdi, -16(%rsp)
movq %rbx, -8(%rsp)
movq %rbp, %rdi
jmp .L25
.L26:
movss (%rax), %xmm0
mulss (%rcx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rcx
cmpq %r8, %rax
jne .L26
.L28:
movss %xmm1, 0(%rbp,%r9,4)
addq $1, %r9
addq $4, %rbx
cmpq %r9, %r13
je .L36
.L29:
movq %rbx, %rcx
movq %r12, %rax
pxor %xmm1, %xmm1
testl %r10d, %r10d
jg .L26
jmp .L28
.L36:
movl -20(%rsp), %eax
.L27:
leal 1(%rax), %ecx
addl %edx, %r15d
addl %r10d, %r14d
cmpl %eax, -24(%rsp)
je .L11
movl %ecx, %eax
.L25:
testl %edx, %edx
jle .L27
movq -8(%rsp), %rbx
movslq %r14d, %rcx
leaq (%r11,%rcx,4), %r12
movq -16(%rsp), %r9
addq %r9, %rcx
leaq (%r11,%rcx,4), %r8
movslq %r15d, %rcx
leaq (%rdi,%rcx,4), %rbp
movl $0, %r9d
movl %eax, -20(%rsp)
jmp .L29
.L11:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z15cpu_matrix_multPfS_S_iii, .-_Z15cpu_matrix_multPfS_S_iii
.globl _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
.type _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii, @function
_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15gpu_matrix_multPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii, .-_Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
.globl _Z15gpu_matrix_multPfS_S_iii
.type _Z15gpu_matrix_multPfS_S_iii, @function
_Z15gpu_matrix_multPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z15gpu_matrix_multPfS_S_iii, .-_Z15gpu_matrix_multPfS_S_iii
.globl _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
.type _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i, @function
_Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22gpu_square_matrix_multPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i, .-_Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
.globl _Z22gpu_square_matrix_multPfS_S_i
.type _Z22gpu_square_matrix_multPfS_S_i, @function
_Z22gpu_square_matrix_multPfS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z22gpu_square_matrix_multPfS_S_i, .-_Z22gpu_square_matrix_multPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Uso: filas matriz A, columnas matriz A, columnas matriz B\n"
.align 8
.LC3:
.string "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n"
.align 8
.LC4:
.string "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "CORRECTO!, Speedup = %f\n"
.LC6:
.string "INCORRECTO\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $4, %edi
jne .L76
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, 12(%rsp)
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movl %eax, %r13d
movq %r14, 40(%rsp)
movslq 40(%rsp), %rbx
movq %rbp, 32(%rsp)
movslq 32(%rsp), %r14
movq %rbx, %rsi
imulq %r14, %rsi
leaq 0(,%rsi,4), %rsi
movq %rsi, 48(%rsp)
movq %rsi, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movslq %r15d, %rbp
imulq %rbp, %r14
leaq 0(,%r14,4), %rdx
movq %rdx, 56(%rsp)
movq %rdx, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
imulq %rbp, %rbx
leaq 0(,%rbx,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movl 12(%rsp), %edx
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z23inicializarMatrizRandomPfii
movl %r15d, %edx
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z23inicializarMatrizRandomPfii
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
leaq 88(%rsp), %rdi
movq 48(%rsp), %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq 56(%rsp), %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 48(%rsp), %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq 56(%rsp), %rdx
movq 24(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
leal 30(%r15), %eax
movl %r15d, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 112(%rsp)
movq 40(%rsp), %rcx
leal 30(%rcx), %eax
movl %ecx, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
movl $16, 124(%rsp)
movl $16, 128(%rsp)
movl $1, 132(%rsp)
movq 32(%rsp), %rax
cmpl %ecx, %eax
jne .L60
cmpl %eax, %r15d
jne .L60
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L77
.L61:
movl $2, %ecx
movq %r14, %rdx
movq 104(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 64(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 64(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %r9d
movq 32(%rsp), %r14
movl %r14d, %r8d
movl 12(%rsp), %ecx
movl %r12d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl %r15d, %r9d
movl %r14d, %r8d
movl %r12d, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z15cpu_matrix_multPfS_S_iii
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movq 80(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 68(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %r15d, %r9d
movl %r14d, %r8d
movl 12(%rsp), %ecx
movl %r12d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $0, 40(%rsp)
jle .L62
movl %r15d, %r10d
movl $0, %r8d
movl $0, %edi
movl $1, %ecx
leal -1(%r15), %r9d
addq $1, %r9
movl $0, %esi
jmp .L63
.L76:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L77:
movl 12(%rsp), %ecx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z47__device_stub__Z22gpu_square_matrix_multPfS_S_iPfS_S_i
jmp .L61
.L60:
movl 132(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movq 112(%rsp), %rdi
movl 120(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L61
movl %r15d, %r9d
movl 32(%rsp), %r8d
movl %r12d, %ecx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z42__device_stub__Z15gpu_matrix_multPfS_S_iiiPfS_S_iii
jmp .L61
.L73:
movl %esi, %ecx
.L64:
addq $4, %rax
cmpq %rdx, %rax
je .L69
.L66:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L73
je .L64
jmp .L73
.L69:
addl $1, %edi
addl %r10d, %r8d
cmpl %r12d, %edi
je .L67
.L63:
testl %r13d, %r13d
jle .L69
movslq %r8d, %rdx
leaq 0(,%rdx,4), %rax
addq %r9, %rdx
salq $2, %rdx
jmp .L66
.L67:
testl %ecx, %ecx
jne .L62
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L71
.L62:
movss 68(%rsp), %xmm0
divss 64(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L71:
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbp, %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call cudaFreeHost@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L78
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC7:
.string "_Z22gpu_square_matrix_multPfS_S_i"
.section .rodata.str1.1
.LC8:
.string "_Z15gpu_matrix_multPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z22gpu_square_matrix_multPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gpu_matrix_multPfS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmulCUDA.hip"
.globl _Z23inicializarMatrizRandomPfii # -- Begin function _Z23inicializarMatrizRandomPfii
.p2align 4, 0x90
.type _Z23inicializarMatrizRandomPfii,@function
_Z23inicializarMatrizRandomPfii: # @_Z23inicializarMatrizRandomPfii
.cfi_startproc
# %bb.0:
imull %edx, %esi
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size _Z23inicializarMatrizRandomPfii, .Lfunc_end0-_Z23inicializarMatrizRandomPfii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_matrix_multPfS_S_iii # -- Begin function _Z30__device_stub__gpu_matrix_multPfS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__gpu_matrix_multPfS_S_iii,@function
_Z30__device_stub__gpu_matrix_multPfS_S_iii: # @_Z30__device_stub__gpu_matrix_multPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15gpu_matrix_multPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__gpu_matrix_multPfS_S_iii, .Lfunc_end1-_Z30__device_stub__gpu_matrix_multPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__gpu_square_matrix_multPfS_S_i # -- Begin function _Z37__device_stub__gpu_square_matrix_multPfS_S_i
.p2align 4, 0x90
.type _Z37__device_stub__gpu_square_matrix_multPfS_S_i,@function
_Z37__device_stub__gpu_square_matrix_multPfS_S_i: # @_Z37__device_stub__gpu_square_matrix_multPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22gpu_square_matrix_multPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z37__device_stub__gpu_square_matrix_multPfS_S_i, .Lfunc_end2-_Z37__device_stub__gpu_square_matrix_multPfS_S_i
.cfi_endproc
# -- End function
.globl _Z15cpu_matrix_multPfS_S_iii # -- Begin function _Z15cpu_matrix_multPfS_S_iii
.p2align 4, 0x90
.type _Z15cpu_matrix_multPfS_S_iii,@function
_Z15cpu_matrix_multPfS_S_iii: # @_Z15cpu_matrix_multPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movq %rdx, (%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, 24(%rsp) # 8-byte Spill
movl %r9d, %r12d
movl %ecx, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movl %ecx, 20(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB3_5
# %bb.1: # %.preheader70.lr.ph
leaq (,%r12,4), %rax
movq %rax, 32(%rsp) # 8-byte Spill
xorl %r14d, %r14d
movq 8(%rsp), %r13 # 8-byte Reload
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
addl %ebx, %r14d
decq %r13
je .LBB3_5
.LBB3_2: # %.preheader70
# =>This Inner Loop Header: Depth=1
testl %ebx, %ebx
jle .LBB3_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rdi
xorl %esi, %esi
movq 32(%rsp), %rdx # 8-byte Reload
callq memset@PLT
jmp .LBB3_4
.LBB3_5: # %.preheader69
movl %ebp, %eax
movl 20(%rsp), %r14d # 4-byte Reload
testl %r14d, %r14d
jle .LBB3_14
# %bb.6: # %.preheader68.lr.ph
xorl %ecx, %ecx
xorl %edx, %edx
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_13: # %._crit_edge79
# in Loop: Header=BB3_7 Depth=1
incq %rdx
addl %ebx, %ecx
cmpq 8(%rsp), %rdx # 8-byte Folded Reload
je .LBB3_14
.LBB3_7: # %.preheader68
# =>This Loop Header: Depth=1
# Child Loop BB3_9 Depth 2
# Child Loop BB3_11 Depth 3
testl %ebp, %ebp
jle .LBB3_13
# %bb.8: # %.lr.ph78
# in Loop: Header=BB3_7 Depth=1
movl %ecx, %esi
movq (%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rsi,4), %rsi
movl %edx, %edi
imull %ebp, %edi
movq 24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB3_9
.p2align 4, 0x90
.LBB3_12: # %._crit_edge76
# in Loop: Header=BB3_9 Depth=2
incq %r9
addl %ebx, %r8d
cmpq %rax, %r9
je .LBB3_13
.LBB3_9: # Parent Loop BB3_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_11 Depth 3
testl %ebx, %ebx
jle .LBB3_12
# %bb.10: # %.lr.ph75
# in Loop: Header=BB3_9 Depth=2
movl %r8d, %r10d
leaq (%r15,%r10,4), %r10
movss (%rdi,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_11: # Parent Loop BB3_7 Depth=1
# Parent Loop BB3_9 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r10,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rsi,%r11,4), %xmm1
movss %xmm1, (%rsi,%r11,4)
incq %r11
cmpq %r11, %r12
jne .LBB3_11
jmp .LBB3_12
.LBB3_14: # %.preheader67
testl %r14d, %r14d
jle .LBB3_23
# %bb.15: # %.preheader66.lr.ph
movslq %ebx, %rcx
leaq (,%rcx,4), %rdx
xorl %esi, %esi
xorl %edi, %edi
jmp .LBB3_16
.p2align 4, 0x90
.LBB3_22: # %._crit_edge86
# in Loop: Header=BB3_16 Depth=1
incq %rdi
addl %ebp, %esi
cmpq 8(%rsp), %rdi # 8-byte Folded Reload
je .LBB3_23
.LBB3_16: # %.preheader66
# =>This Loop Header: Depth=1
# Child Loop BB3_18 Depth 2
# Child Loop BB3_20 Depth 3
testl %ebx, %ebx
jle .LBB3_22
# %bb.17: # %.preheader.lr.ph
# in Loop: Header=BB3_16 Depth=1
movl %esi, %r8d
movq 24(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r8
movq %rdi, %r9
imulq %rcx, %r9
movq (%rsp), %r10 # 8-byte Reload
leaq (%r10,%r9,4), %r9
movq %r15, %r10
xorl %r11d, %r11d
jmp .LBB3_18
.p2align 4, 0x90
.LBB3_21: # %._crit_edge84
# in Loop: Header=BB3_18 Depth=2
movss %xmm0, (%r9,%r11,4)
incq %r11
addq $4, %r10
cmpq %r12, %r11
je .LBB3_22
.LBB3_18: # %.preheader
# Parent Loop BB3_16 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_20 Depth 3
xorps %xmm0, %xmm0
testl %ebp, %ebp
jle .LBB3_21
# %bb.19: # %.lr.ph83.preheader
# in Loop: Header=BB3_18 Depth=2
movq %r10, %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_20: # %.lr.ph83
# Parent Loop BB3_16 Depth=1
# Parent Loop BB3_18 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r14), %xmm1
addss %xmm1, %xmm0
incq %r13
addq %rdx, %r14
cmpq %r13, %rax
jne .LBB3_20
jmp .LBB3_21
.LBB3_23: # %._crit_edge88
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15cpu_matrix_multPfS_S_iii, .Lfunc_end3-_Z15cpu_matrix_multPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
jne .LBB4_24
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %rax, 32(%rsp) # 8-byte Spill
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movslq %r15d, %rbp
shlq $2, %rbp
movslq %r14d, %r12
movq %r12, %rdi
imulq %rbp, %rdi
movq %rdi, 224(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movslq %r13d, %r15
imulq %r15, %r12
shlq $2, %r12
movq %r12, 232(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
imulq %r15, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, 160(%rsp) # 8-byte Spill
movq %rbp, 168(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, 152(%rsp) # 8-byte Spill
movq %r14, 240(%rsp) # 8-byte Spill
movl %r14d, %eax
imull 32(%rsp), %eax # 4-byte Folded Reload
testl %eax, %eax
jle .LBB4_4
# %bb.2: # %.lr.ph.preheader.i
movl %eax, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_3
.LBB4_4: # %_Z23inicializarMatrizRandomPfii.exit
movq %rbx, 80(%rsp) # 8-byte Spill
movl %r13d, %eax
movq 240(%rsp), %r14 # 8-byte Reload
imull %r14d, %eax
testl %eax, %eax
movq 72(%rsp), %rbx # 8-byte Reload
jle .LBB4_7
# %bb.5: # %.lr.ph.preheader.i100
movl %eax, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_6: # %.lr.ph.i102
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_6
.LBB4_7: # %_Z23inicializarMatrizRandomPfii.exit106
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 56(%rsp), %rdi
movq 224(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq 232(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq 168(%rsp), %rsi # 8-byte Reload
callq hipMalloc
movq 56(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %r15 # 8-byte Reload
leal 15(%r15), %eax
leal 30(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $4, %edi
leal 15(%r13), %eax
leal 30(%r13), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
shlq $32, %rdi
orq %rcx, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
cmpl %r14d, %r15d
jne .LBB4_11
# %bb.8: # %_Z23inicializarMatrizRandomPfii.exit106
cmpl %r13d, %r14d
jne .LBB4_11
# %bb.9:
testl %eax, %eax
movq 160(%rsp), %r12 # 8-byte Reload
movq 152(%rsp), %rbp # 8-byte Reload
jne .LBB4_14
# %bb.10:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 4(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z22gpu_square_matrix_multPfS_S_i, %edi
jmp .LBB4_13
.LBB4_11:
testl %eax, %eax
movq 160(%rsp), %r12 # 8-byte Reload
movq 152(%rsp), %rbp # 8-byte Reload
jne .LBB4_14
# %bb.12:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movl %eax, 4(%rsp)
movl %r14d, 148(%rsp)
movl %r13d, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 148(%rsp), %rax
movq %rax, 208(%rsp)
leaq 144(%rsp), %rax
movq %rax, 216(%rsp)
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z15gpu_matrix_multPfS_S_iii, %edi
.LBB4_13:
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_14:
movq 40(%rsp), %rsi
movq %r12, %rdi
movq 168(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 176(%rsp), %rdi
callq hipEventElapsedTime
movss 176(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movq 32(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
movl %r14d, %edx
movl %r14d, %ecx
movl %r13d, %r8d
movb $1, %al
callq printf
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 80(%rsp), %rdi # 8-byte Reload
movq 72(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl %ebx, %ecx
movl %r14d, %r8d
movl %r13d, %r9d
callq _Z15cpu_matrix_multPfS_S_iii
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebx, %esi
movl %r14d, %edx
movl %r14d, %ecx
movl %r13d, %r8d
movb $1, %al
callq printf
testl %ebx, %ebx
jle .LBB4_21
# %bb.15: # %.preheader.lr.ph
movl %ebx, %eax
movl %r13d, %ecx
movl $1, %edx
xorl %esi, %esi
xorl %edi, %edi
jmp .LBB4_16
.p2align 4, 0x90
.LBB4_19: # %._crit_edge
# in Loop: Header=BB4_16 Depth=1
incq %rdi
addl %r13d, %esi
cmpq %rax, %rdi
je .LBB4_20
.LBB4_16: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_18 Depth 2
testl %r13d, %r13d
jle .LBB4_19
# %bb.17: # %.lr.ph
# in Loop: Header=BB4_16 Depth=1
movl %esi, %r9d
leaq (%r12,%r9,4), %r8
leaq (,%r9,4), %r9
addq %rbp, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_18: # Parent Loop BB4_16 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r9,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%r8,%r10,4), %xmm0
cmovnel %r15d, %edx
cmovpl %r15d, %edx
incq %r10
cmpq %r10, %rcx
jne .LBB4_18
jmp .LBB4_19
.LBB4_20: # %._crit_edge125.loopexit
testl %edx, %edx
je .LBB4_22
.LBB4_21: # %.critedge
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 176(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
jmp .LBB4_23
.LBB4_22:
movl $.Lstr, %edi
callq puts@PLT
.LBB4_23:
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi # 8-byte Reload
callq hipHostFree
movq 72(%rsp), %rdi # 8-byte Reload
callq hipHostFree
movq %r12, %rdi
callq hipHostFree
movq %rbp, %rdi
callq hipHostFree
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_24:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $58, %esi
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_matrix_multPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22gpu_square_matrix_multPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15gpu_matrix_multPfS_S_iii,@object # @_Z15gpu_matrix_multPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z15gpu_matrix_multPfS_S_iii
.p2align 3, 0x0
_Z15gpu_matrix_multPfS_S_iii:
.quad _Z30__device_stub__gpu_matrix_multPfS_S_iii
.size _Z15gpu_matrix_multPfS_S_iii, 8
.type _Z22gpu_square_matrix_multPfS_S_i,@object # @_Z22gpu_square_matrix_multPfS_S_i
.globl _Z22gpu_square_matrix_multPfS_S_i
.p2align 3, 0x0
_Z22gpu_square_matrix_multPfS_S_i:
.quad _Z37__device_stub__gpu_square_matrix_multPfS_S_i
.size _Z22gpu_square_matrix_multPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Uso: filas matriz A, columnas matriz A, columnas matriz B\n"
.size .L.str, 59
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en GPU: %fs.\n\n"
.size .L.str.1, 68
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Tiempo empleado en la Mult de Matrices %dx%d . %dx%d en CPU: %fs.\n\n"
.size .L.str.2, 68
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CORRECTO!, Speedup = %f\n"
.size .L.str.3, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15gpu_matrix_multPfS_S_iii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22gpu_square_matrix_multPfS_S_i"
.size .L__unnamed_2, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "INCORRECTO"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__gpu_matrix_multPfS_S_iii
.addrsig_sym _Z37__device_stub__gpu_square_matrix_multPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15gpu_matrix_multPfS_S_iii
.addrsig_sym _Z22gpu_square_matrix_multPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void forward_zero_nonmax_kernel(int n, float *input, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= n) return;
if (input[id] != output[id]) output[id] = 0;
} | code for sm_80
Function : _Z26forward_zero_nonmax_kerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FSETP.NEU.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fda0003f0d000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void forward_zero_nonmax_kernel(int n, float *input, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= n) return;
if (input[id] != output[id]) output[id] = 0;
} | .file "tmpxft_0004691b_00000000-6_forward_zero_nonmax_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_
.type _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_, @function
_Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26forward_zero_nonmax_kerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_, .-_Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_
.globl _Z26forward_zero_nonmax_kerneliPfS_
.type _Z26forward_zero_nonmax_kerneliPfS_, @function
_Z26forward_zero_nonmax_kerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26forward_zero_nonmax_kerneliPfS_, .-_Z26forward_zero_nonmax_kerneliPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26forward_zero_nonmax_kerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26forward_zero_nonmax_kerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void forward_zero_nonmax_kernel(int n, float *input, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= n) return;
if (input[id] != output[id]) output[id] = 0;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void forward_zero_nonmax_kernel(int n, float *input, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= n) return;
if (input[id] != output[id]) output[id] = 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void forward_zero_nonmax_kernel(int n, float *input, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= n) return;
if (input[id] != output[id]) output[id] = 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26forward_zero_nonmax_kerneliPfS_
.globl _Z26forward_zero_nonmax_kerneliPfS_
.p2align 8
.type _Z26forward_zero_nonmax_kerneliPfS_,@function
_Z26forward_zero_nonmax_kerneliPfS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26forward_zero_nonmax_kerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26forward_zero_nonmax_kerneliPfS_, .Lfunc_end0-_Z26forward_zero_nonmax_kerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26forward_zero_nonmax_kerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26forward_zero_nonmax_kerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void forward_zero_nonmax_kernel(int n, float *input, float *output)
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if (id >= n) return;
if (input[id] != output[id]) output[id] = 0;
} | .text
.file "forward_zero_nonmax_kernel.hip"
.globl _Z41__device_stub__forward_zero_nonmax_kerneliPfS_ # -- Begin function _Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.p2align 4, 0x90
.type _Z41__device_stub__forward_zero_nonmax_kerneliPfS_,@function
_Z41__device_stub__forward_zero_nonmax_kerneliPfS_: # @_Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26forward_zero_nonmax_kerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z41__device_stub__forward_zero_nonmax_kerneliPfS_, .Lfunc_end0-_Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26forward_zero_nonmax_kerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26forward_zero_nonmax_kerneliPfS_,@object # @_Z26forward_zero_nonmax_kerneliPfS_
.section .rodata,"a",@progbits
.globl _Z26forward_zero_nonmax_kerneliPfS_
.p2align 3, 0x0
_Z26forward_zero_nonmax_kerneliPfS_:
.quad _Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.size _Z26forward_zero_nonmax_kerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26forward_zero_nonmax_kerneliPfS_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26forward_zero_nonmax_kerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26forward_zero_nonmax_kerneliPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ FSETP.NEU.AND P0, PT, R3, R0, PT ; /* 0x000000000300720b */
/* 0x004fda0003f0d000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26forward_zero_nonmax_kerneliPfS_
.globl _Z26forward_zero_nonmax_kerneliPfS_
.p2align 8
.type _Z26forward_zero_nonmax_kerneliPfS_,@function
_Z26forward_zero_nonmax_kerneliPfS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26forward_zero_nonmax_kerneliPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26forward_zero_nonmax_kerneliPfS_, .Lfunc_end0-_Z26forward_zero_nonmax_kerneliPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26forward_zero_nonmax_kerneliPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26forward_zero_nonmax_kerneliPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004691b_00000000-6_forward_zero_nonmax_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_
.type _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_, @function
_Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26forward_zero_nonmax_kerneliPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_, .-_Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_
.globl _Z26forward_zero_nonmax_kerneliPfS_
.type _Z26forward_zero_nonmax_kerneliPfS_, @function
_Z26forward_zero_nonmax_kerneliPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26forward_zero_nonmax_kerneliPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26forward_zero_nonmax_kerneliPfS_, .-_Z26forward_zero_nonmax_kerneliPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26forward_zero_nonmax_kerneliPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26forward_zero_nonmax_kerneliPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "forward_zero_nonmax_kernel.hip"
.globl _Z41__device_stub__forward_zero_nonmax_kerneliPfS_ # -- Begin function _Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.p2align 4, 0x90
.type _Z41__device_stub__forward_zero_nonmax_kerneliPfS_,@function
_Z41__device_stub__forward_zero_nonmax_kerneliPfS_: # @_Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26forward_zero_nonmax_kerneliPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z41__device_stub__forward_zero_nonmax_kerneliPfS_, .Lfunc_end0-_Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26forward_zero_nonmax_kerneliPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26forward_zero_nonmax_kerneliPfS_,@object # @_Z26forward_zero_nonmax_kerneliPfS_
.section .rodata,"a",@progbits
.globl _Z26forward_zero_nonmax_kerneliPfS_
.p2align 3, 0x0
_Z26forward_zero_nonmax_kerneliPfS_:
.quad _Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.size _Z26forward_zero_nonmax_kerneliPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26forward_zero_nonmax_kerneliPfS_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__forward_zero_nonmax_kerneliPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26forward_zero_nonmax_kerneliPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) 2019-2020, NVIDIA CORPORATION.
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} | .file "tmpxft_000c3b4a_00000000-6__upfirdn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5978:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
.type _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi, @function
_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi:
.LFB6000:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_float32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6000:
.size _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi, .-_Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
.globl _cupy_upfirdn1D_float32
.type _cupy_upfirdn1D_float32, @function
_cupy_upfirdn1D_float32:
.LFB6001:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z56__device_stub__Z23_cupy_upfirdn1D_float32PKfS0_iiiiiiPfiPKfS0_iiiiiiPfi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6001:
.size _cupy_upfirdn1D_float32, .-_cupy_upfirdn1D_float32
.globl _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
.type _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi, @function
_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi:
.LFB6002:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_float64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6002:
.size _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi, .-_Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
.globl _cupy_upfirdn1D_float64
.type _cupy_upfirdn1D_float64, @function
_cupy_upfirdn1D_float64:
.LFB6003:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z56__device_stub__Z23_cupy_upfirdn1D_float64PKdS0_iiiiiiPdiPKdS0_iiiiiiPdi
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6003:
.size _cupy_upfirdn1D_float64, .-_cupy_upfirdn1D_float64
.globl _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i
.type _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i, @function
_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i:
.LFB6004:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_complex64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6004:
.size _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i, .-_Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i
.globl _cupy_upfirdn1D_complex64
.type _cupy_upfirdn1D_complex64, @function
_cupy_upfirdn1D_complex64:
.LFB6005:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z101__device_stub__Z25_cupy_upfirdn1D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIfEES4_iiiiiiPS2_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6005:
.size _cupy_upfirdn1D_complex64, .-_cupy_upfirdn1D_complex64
.globl _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i
.type _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i, @function
_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i:
.LFB6006:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn1D_complex128(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6006:
.size _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i, .-_Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i
.globl _cupy_upfirdn1D_complex128
.type _cupy_upfirdn1D_complex128, @function
_cupy_upfirdn1D_complex128:
.LFB6007:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z102__device_stub__Z26_cupy_upfirdn1D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_iPKN6thrust20THRUST_200700_800_NS7complexIdEES4_iiiiiiPS2_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6007:
.size _cupy_upfirdn1D_complex128, .-_cupy_upfirdn1D_complex128
.globl _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
.type _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii, @function
_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii:
.LFB6008:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_float32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6008:
.size _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii, .-_Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
.globl _cupy_upfirdn2D_float32
.type _cupy_upfirdn2D_float32, @function
_cupy_upfirdn2D_float32:
.LFB6009:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z58__device_stub__Z23_cupy_upfirdn2D_float32PKfiS0_iiiiiiPfiiPKfiS0_iiiiiiPfii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6009:
.size _cupy_upfirdn2D_float32, .-_cupy_upfirdn2D_float32
.globl _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
.type _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii, @function
_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii:
.LFB6010:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_float64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6010:
.size _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii, .-_Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
.globl _cupy_upfirdn2D_float64
.type _cupy_upfirdn2D_float64, @function
_cupy_upfirdn2D_float64:
.LFB6011:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z58__device_stub__Z23_cupy_upfirdn2D_float64PKdiS0_iiiiiiPdiiPKdiS0_iiiiiiPdii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6011:
.size _cupy_upfirdn2D_float64, .-_cupy_upfirdn2D_float64
.globl _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii
.type _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii, @function
_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii:
.LFB6012:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_complex64(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6012:
.size _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii, .-_Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii
.globl _cupy_upfirdn2D_complex64
.type _cupy_upfirdn2D_complex64, @function
_cupy_upfirdn2D_complex64:
.LFB6013:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z103__device_stub__Z25_cupy_upfirdn2D_complex64PKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIfEEiS4_iiiiiiPS2_ii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6013:
.size _cupy_upfirdn2D_complex64, .-_cupy_upfirdn2D_complex64
.globl _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii
.type _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii, @function
_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii:
.LFB6014:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movl %esi, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
movq 264(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 248
pushq 56(%rsp)
.cfi_def_cfa_offset 256
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _cupy_upfirdn2D_complex128(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE6014:
.size _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii, .-_Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii
.globl _cupy_upfirdn2D_complex128
.type _cupy_upfirdn2D_complex128, @function
_cupy_upfirdn2D_complex128:
.LFB6015:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z104__device_stub__Z26_cupy_upfirdn2D_complex128PKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_iiPKN6thrust20THRUST_200700_800_NS7complexIdEEiS4_iiiiiiPS2_ii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6015:
.size _cupy_upfirdn2D_complex128, .-_cupy_upfirdn2D_complex128
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_cupy_upfirdn2D_complex128"
.LC1:
.string "_cupy_upfirdn2D_complex64"
.LC2:
.string "_cupy_upfirdn2D_float64"
.LC3:
.string "_cupy_upfirdn2D_float32"
.LC4:
.string "_cupy_upfirdn1D_complex128"
.LC5:
.string "_cupy_upfirdn1D_complex64"
.LC6:
.string "_cupy_upfirdn1D_float64"
.LC7:
.string "_cupy_upfirdn1D_float32"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std3__45__cpo5beginE"
.align 8
.LC9:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std3__45__cpo3endE"
.align 8
.LC10:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std3__45__cpo6cbeginE"
.align 8
.LC11:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std3__45__cpo4cendE"
.align 8
.LC12:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE"
.align 8
.LC13:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std3__419piecewise_constructE"
.align 8
.LC14:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std3__48in_placeE"
.align 8
.LC15:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC16:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo9iter_moveE"
.align 8
.LC17:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955904cuda3std6ranges3__45__cpo7advanceE"
.align 8
.LC18:
.string "_ZN42_INTERNAL_f601861c_11__upfirdn_cu_c38955906thrust20THRUST_200700_800_NS6system6detail10sequential3seqE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6017:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_complex128(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_complex64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_float64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn2D_float32(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_complex128(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_complex64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_float64(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _cupy_upfirdn1D_float32(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6017:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object
.size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo7advanceE
.section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
.type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
.zero 1
.hidden _ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE
.weak _ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE
.section .rodata._ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE,"aG",@progbits,_ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE,comdat
.type _ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE, @gnu_unique_object
.size _ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE, 1
_ZN4cuda3std3__444_GLOBAL__N__f601861c_11__upfirdn_cu_c38955906ignoreE:
.zero 1
.weak _ZN4cuda3std3__48in_placeE
.section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
.type _ZN4cuda3std3__48in_placeE, @gnu_unique_object
.size _ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
.zero 1
.weak _ZN4cuda3std3__45__cpo4cendE
.section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
.type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
.zero 1
.weak _ZN4cuda3std3__45__cpo6cbeginE
.section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
.type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
.zero 1
.weak _ZN4cuda3std3__45__cpo3endE
.section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
.type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
.zero 1
.weak _ZN4cuda3std3__45__cpo5beginE
.section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
.type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
.zero 1
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) 2019-2020, NVIDIA CORPORATION.
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} | // Copyright (c) 2019-2020, NVIDIA CORPORATION.
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <hip/hip_runtime.h>
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Copyright (c) 2019-2020, NVIDIA CORPORATION.
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <hip/hip_runtime.h>
#include <thrust/complex.h>
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN1D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn1D( const T *__restrict__ inp,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW ) {
const int t { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int stride { static_cast<int>( blockDim.x * gridDim.x ) };
for ( size_t tid = t; tid < outW; tid += stride ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
__builtin_assume( tid > 0 );
#endif
const int x_idx { static_cast<int>( ( tid * down ) / up ) % padded_len };
int h_idx { static_cast<int>( ( tid * down ) % up * h_per_phase ) };
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
temp += inp[x_c] * h_trans_flip[h_idx];
h_idx += 1;
}
out[tid] = temp;
}
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float32( const float *__restrict__ inp,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<float>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 ) _cupy_upfirdn1D_float64( const double *__restrict__ inp,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<double>( inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex64( const thrust::complex<float> *__restrict__ inp,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<float>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
extern "C" __global__ void __launch_bounds__( 512 )
_cupy_upfirdn1D_complex128( const thrust::complex<double> *__restrict__ inp,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW ) {
_cupy_upfirdn1D<thrust::complex<double>>(
inp, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW );
}
///////////////////////////////////////////////////////////////////////////////
// UPFIRDN2D //
///////////////////////////////////////////////////////////////////////////////
template<typename T>
__device__ void _cupy_upfirdn2D( const T *__restrict__ inp,
const int inpH,
const T *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
T *__restrict__ out,
const int outW,
const int outH ) {
const int ty { static_cast<int>( blockIdx.x * blockDim.x + threadIdx.x ) };
const int tx { static_cast<int>( blockIdx.y * blockDim.y + threadIdx.y ) };
const int stride_y { static_cast<int>( blockDim.x * gridDim.x ) };
const int stride_x { static_cast<int>( blockDim.y * gridDim.y ) };
for ( int x = tx; x < outH; x += stride_x ) {
for ( int y = ty; y < outW; y += stride_y ) {
int x_idx {};
int h_idx {};
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( padded_len > 0 );
__builtin_assume( up > 0 );
__builtin_assume( down > 0 );
#endif
if ( axis == 1 ) {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( x > 0 );
#endif
x_idx = ( static_cast<int>( x * down ) / up ) % padded_len;
h_idx = ( x * down ) % up * h_per_phase;
} else {
#if ( __CUDACC_VER_MAJOR__ >= 11 ) && ( __CUDACC_VER_MINOR__ >= 2 )
__builtin_assume( y > 0 );
#endif
x_idx = ( static_cast<int>( y * down ) / up ) % padded_len;
h_idx = ( y * down ) % up * h_per_phase;
}
int x_conv_idx { x_idx - h_per_phase + 1 };
if ( x_conv_idx < 0 ) {
h_idx -= x_conv_idx;
x_conv_idx = 0;
}
T temp {};
int stop = ( x_shape_a < ( x_idx + 1 ) ) ? x_shape_a : ( x_idx + 1 );
for ( int x_c = x_conv_idx; x_c < stop; x_c++ ) {
if ( axis == 1 ) {
temp += inp[y * inpH + x_c] * h_trans_flip[h_idx];
} else {
temp += inp[x_c * inpH + x] * h_trans_flip[h_idx];
}
h_idx += 1;
}
out[y * outH + x] = temp;
}
}
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float32( const float *__restrict__ inp,
const int inpH,
const float *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
float *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<float>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 ) _cupy_upfirdn2D_float64( const double *__restrict__ inp,
const int inpH,
const double *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
double *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<double>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex64( const thrust::complex<float> *__restrict__ inp,
const int inpH,
const thrust::complex<float> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<float> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<float>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
}
extern "C" __global__ void __launch_bounds__( 64 )
_cupy_upfirdn2D_complex128( const thrust::complex<double> *__restrict__ inp,
const int inpH,
const thrust::complex<double> *__restrict__ h_trans_flip,
const int up,
const int down,
const int axis,
const int x_shape_a,
const int h_per_phase,
const int padded_len,
thrust::complex<double> *__restrict__ out,
const int outW,
const int outH ) {
_cupy_upfirdn2D<thrust::complex<double>>(
inp, inpH, h_trans_flip, up, down, axis, x_shape_a, h_per_phase, padded_len, out, outW, outH );
} | .text
.file "_upfirdn.hip"
.globl __device_stub___cupy_upfirdn1D_float32 # -- Begin function __device_stub___cupy_upfirdn1D_float32
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_float32,@function
__device_stub___cupy_upfirdn1D_float32: # @__device_stub___cupy_upfirdn1D_float32
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_float32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub___cupy_upfirdn1D_float32, .Lfunc_end0-__device_stub___cupy_upfirdn1D_float32
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn1D_float64 # -- Begin function __device_stub___cupy_upfirdn1D_float64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_float64,@function
__device_stub___cupy_upfirdn1D_float64: # @__device_stub___cupy_upfirdn1D_float64
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_float64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size __device_stub___cupy_upfirdn1D_float64, .Lfunc_end1-__device_stub___cupy_upfirdn1D_float64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn1D_complex64 # -- Begin function __device_stub___cupy_upfirdn1D_complex64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_complex64,@function
__device_stub___cupy_upfirdn1D_complex64: # @__device_stub___cupy_upfirdn1D_complex64
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_complex64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size __device_stub___cupy_upfirdn1D_complex64, .Lfunc_end2-__device_stub___cupy_upfirdn1D_complex64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn1D_complex128 # -- Begin function __device_stub___cupy_upfirdn1D_complex128
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn1D_complex128,@function
__device_stub___cupy_upfirdn1D_complex128: # @__device_stub___cupy_upfirdn1D_complex128
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn1D_complex128, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size __device_stub___cupy_upfirdn1D_complex128, .Lfunc_end3-__device_stub___cupy_upfirdn1D_complex128
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_float32 # -- Begin function __device_stub___cupy_upfirdn2D_float32
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_float32,@function
__device_stub___cupy_upfirdn2D_float32: # @__device_stub___cupy_upfirdn2D_float32
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_float32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end4:
.size __device_stub___cupy_upfirdn2D_float32, .Lfunc_end4-__device_stub___cupy_upfirdn2D_float32
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_float64 # -- Begin function __device_stub___cupy_upfirdn2D_float64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_float64,@function
__device_stub___cupy_upfirdn2D_float64: # @__device_stub___cupy_upfirdn2D_float64
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_float64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end5:
.size __device_stub___cupy_upfirdn2D_float64, .Lfunc_end5-__device_stub___cupy_upfirdn2D_float64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_complex64 # -- Begin function __device_stub___cupy_upfirdn2D_complex64
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_complex64,@function
__device_stub___cupy_upfirdn2D_complex64: # @__device_stub___cupy_upfirdn2D_complex64
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_complex64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end6:
.size __device_stub___cupy_upfirdn2D_complex64, .Lfunc_end6-__device_stub___cupy_upfirdn2D_complex64
.cfi_endproc
# -- End function
.globl __device_stub___cupy_upfirdn2D_complex128 # -- Begin function __device_stub___cupy_upfirdn2D_complex128
.p2align 4, 0x90
.type __device_stub___cupy_upfirdn2D_complex128,@function
__device_stub___cupy_upfirdn2D_complex128: # @__device_stub___cupy_upfirdn2D_complex128
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 192(%rsp), %rax
movq %rax, 128(%rsp)
leaq 200(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_cupy_upfirdn2D_complex128, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end7:
.size __device_stub___cupy_upfirdn2D_complex128, .Lfunc_end7-__device_stub___cupy_upfirdn2D_complex128
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_float32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_float64, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_complex64, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn1D_complex128, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_float32, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_float64, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_complex64, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_cupy_upfirdn2D_complex128, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _cupy_upfirdn1D_float32,@object # @_cupy_upfirdn1D_float32
.section .rodata,"a",@progbits
.globl _cupy_upfirdn1D_float32
.p2align 3, 0x0
_cupy_upfirdn1D_float32:
.quad __device_stub___cupy_upfirdn1D_float32
.size _cupy_upfirdn1D_float32, 8
.type _cupy_upfirdn1D_float64,@object # @_cupy_upfirdn1D_float64
.globl _cupy_upfirdn1D_float64
.p2align 3, 0x0
_cupy_upfirdn1D_float64:
.quad __device_stub___cupy_upfirdn1D_float64
.size _cupy_upfirdn1D_float64, 8
.type _cupy_upfirdn1D_complex64,@object # @_cupy_upfirdn1D_complex64
.globl _cupy_upfirdn1D_complex64
.p2align 3, 0x0
_cupy_upfirdn1D_complex64:
.quad __device_stub___cupy_upfirdn1D_complex64
.size _cupy_upfirdn1D_complex64, 8
.type _cupy_upfirdn1D_complex128,@object # @_cupy_upfirdn1D_complex128
.globl _cupy_upfirdn1D_complex128
.p2align 3, 0x0
_cupy_upfirdn1D_complex128:
.quad __device_stub___cupy_upfirdn1D_complex128
.size _cupy_upfirdn1D_complex128, 8
.type _cupy_upfirdn2D_float32,@object # @_cupy_upfirdn2D_float32
.globl _cupy_upfirdn2D_float32
.p2align 3, 0x0
_cupy_upfirdn2D_float32:
.quad __device_stub___cupy_upfirdn2D_float32
.size _cupy_upfirdn2D_float32, 8
.type _cupy_upfirdn2D_float64,@object # @_cupy_upfirdn2D_float64
.globl _cupy_upfirdn2D_float64
.p2align 3, 0x0
_cupy_upfirdn2D_float64:
.quad __device_stub___cupy_upfirdn2D_float64
.size _cupy_upfirdn2D_float64, 8
.type _cupy_upfirdn2D_complex64,@object # @_cupy_upfirdn2D_complex64
.globl _cupy_upfirdn2D_complex64
.p2align 3, 0x0
_cupy_upfirdn2D_complex64:
.quad __device_stub___cupy_upfirdn2D_complex64
.size _cupy_upfirdn2D_complex64, 8
.type _cupy_upfirdn2D_complex128,@object # @_cupy_upfirdn2D_complex128
.globl _cupy_upfirdn2D_complex128
.p2align 3, 0x0
_cupy_upfirdn2D_complex128:
.quad __device_stub___cupy_upfirdn2D_complex128
.size _cupy_upfirdn2D_complex128, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_cupy_upfirdn1D_float32"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_cupy_upfirdn1D_float64"
.size .L__unnamed_2, 24
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_cupy_upfirdn1D_complex64"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_cupy_upfirdn1D_complex128"
.size .L__unnamed_4, 27
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_cupy_upfirdn2D_float32"
.size .L__unnamed_5, 24
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_cupy_upfirdn2D_float64"
.size .L__unnamed_6, 24
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_cupy_upfirdn2D_complex64"
.size .L__unnamed_7, 26
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_cupy_upfirdn2D_complex128"
.size .L__unnamed_8, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub___cupy_upfirdn1D_float32
.addrsig_sym __device_stub___cupy_upfirdn1D_float64
.addrsig_sym __device_stub___cupy_upfirdn1D_complex64
.addrsig_sym __device_stub___cupy_upfirdn1D_complex128
.addrsig_sym __device_stub___cupy_upfirdn2D_float32
.addrsig_sym __device_stub___cupy_upfirdn2D_float64
.addrsig_sym __device_stub___cupy_upfirdn2D_complex64
.addrsig_sym __device_stub___cupy_upfirdn2D_complex128
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _cupy_upfirdn1D_float32
.addrsig_sym _cupy_upfirdn1D_float64
.addrsig_sym _cupy_upfirdn1D_complex64
.addrsig_sym _cupy_upfirdn1D_complex128
.addrsig_sym _cupy_upfirdn2D_float32
.addrsig_sym _cupy_upfirdn2D_float64
.addrsig_sym _cupy_upfirdn2D_complex64
.addrsig_sym _cupy_upfirdn2D_complex128
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define HISTOGRAM_SIZE 256 /* Histogram has 256 bins */
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
__global__ void find_prefix_kernel(int *input_data, int *prefix_array, int num_elements, int range)
{
__shared__ unsigned int s[HISTOGRAM_SIZE];
__shared__ unsigned int s_temp[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x <= range){
s[threadIdx.x] = 0;
s_temp[threadIdx.x] = 0;
}
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[input_data[offset]], 1);
offset += stride;
}
__syncthreads();
/* Step 2: Calculate starting indices in output array for storing sorted elements.
* Use inclusive scan of the bin elements. */
int off = 1;
int pingpong_flag = 1;
int tid = threadIdx.x;
while(off < num_elements){
if (pingpong_flag){
if (tid >= off)
s_temp[tid] = s[tid] + s[tid - off];
else
s_temp[tid] = s[tid];
}
else{
if (tid >= off)
s[tid] = s_temp[tid] + s_temp[tid - off];
else
s[tid] = s_temp[tid];
}
__syncthreads();
pingpong_flag = !pingpong_flag;
off = 2*off;
}
/* Accumulate prefix array in shared memory into global memory, and send to CPU */
if (threadIdx.x <= range)
atomicAdd(&prefix_array[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void counting_sort_kernel(int *prefix_array, int *sorted_array, int num_elements, int range)
{
__shared__ unsigned int prefix_shared[HISTOGRAM_SIZE];
/* Get prefix array from CPU, copy to shared mem and arrange the sorted array */
int tid = threadIdx.x;
if (tid <= range)
prefix_shared[tid] = prefix_array[tid];
__syncthreads();
int start_idx = 0;
int j = 0;
if (tid == 0)
start_idx = 0;
else
start_idx = prefix_shared[tid-1];
int end_idx = prefix_shared[tid];
for (j = start_idx; j < end_idx; j++)
sorted_array[j] = tid;
return;
} | code for sm_80
Function : _Z20counting_sort_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xd0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GT.AND P0, PT, R0.reuse, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x041fe40003f04270 */
/*0060*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f25270 */
/*0070*/ @P0 BRA 0xc0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0041e40000004800 */
/*00c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P1 LDS R4, [R0.X4+-0x4] ; /* 0xfffffc0000041984 */
/* 0x000fe80000004800 */
/*00f0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e640000004800 */
/*0100*/ ISETP.GT.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x002fda0003f04270 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ LOP3.LUT R6, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff067212 */
/* 0x000fe200078e33ff */
/*0130*/ IMAD.IADD R2, R5.reuse, 0x1, -R4 ; /* 0x0000000105027824 */
/* 0x040fe200078e0a04 */
/*0140*/ BSSY B0, 0x230 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0150*/ IMAD.IADD R3, R5, 0x1, R6 ; /* 0x0000000105037824 */
/* 0x001fe200078e0206 */
/*0160*/ LOP3.LUT P1, R6, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302067812 */
/* 0x000fc8000782c0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fd20003f06070 */
/*0180*/ @!P1 BRA 0x220 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0203 */
/*01b0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e2000c101904 */
/*01d0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*01f0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*0200*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fcc00010e0603 */
/*0210*/ @P1 BRA 0x1b0 ; /* 0xffffff9000001947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0240*/ IMAD.IADD R6, R5, 0x1, -R4 ; /* 0x0000000105067824 */
/* 0x000fe200078e0a04 */
/*0250*/ BSSY B0, 0x470 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0280*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0203 */
/*0290*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f1e0ff */
/*02a0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*02c0*/ @!P1 BRA 0x460 ; /* 0x0000019000009947 */
/* 0x000fee0003800000 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02e0*/ IADD3 R7, R5, -0xc, RZ ; /* 0xfffffff405077810 */
/* 0x000fc60007ffe0ff */
/*02f0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0300*/ STG.E [R2.64+-0x8], R0 ; /* 0xfffff80002007986 */
/* 0x000fe2000c101904 */
/*0310*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe40007f5e0ff */
/*0320*/ ISETP.GE.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe20003f26270 */
/*0330*/ STG.E [R2.64+-0x4], R0 ; /* 0xfffffc0002007986 */
/* 0x000fe4000c101904 */
/*0340*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fc400010e0603 */
/*0350*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0380*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0390*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R2.64+0x18], R0 ; /* 0x0000180002007986 */
/* 0x000fe8000c101904 */
/*03c0*/ STG.E [R2.64+0x1c], R0 ; /* 0x00001c0002007986 */
/* 0x000fe8000c101904 */
/*03d0*/ STG.E [R2.64+0x20], R0 ; /* 0x0000200002007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R2.64+0x24], R0 ; /* 0x0000240002007986 */
/* 0x000fe8000c101904 */
/*03f0*/ STG.E [R2.64+0x28], R0 ; /* 0x0000280002007986 */
/* 0x000fe8000c101904 */
/*0400*/ STG.E [R2.64+0x2c], R0 ; /* 0x00002c0002007986 */
/* 0x000fe8000c101904 */
/*0410*/ STG.E [R2.64+0x30], R0 ; /* 0x0000300002007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R2.64+0x34], R0 ; /* 0x0000340002007986 */
/* 0x0001e4000c101904 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0450*/ @!P1 BRA 0x2f0 ; /* 0xfffffe9000009947 */
/* 0x000fea000383ffff */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.IADD R6, R5, 0x1, -R4 ; /* 0x0000000105067824 */
/* 0x000fe200078e0a04 */
/*0480*/ BSSY B0, 0x5a0 ; /* 0x0000011000007945 */
/* 0x000fe80003800000 */
/*0490*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*04a0*/ @!P1 BRA 0x590 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*04b0*/ IADD3 R6, P1, R2, 0x20, RZ ; /* 0x0000002002067810 */
/* 0x000fe20007f3e0ff */
/*04c0*/ STG.E [R2.64+-0x8], R0 ; /* 0xfffff80002007986 */
/* 0x000fe2000c101904 */
/*04d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04e0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*04f0*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0603 */
/*0500*/ STG.E [R2.64+-0x4], R0 ; /* 0xfffffc0002007986 */
/* 0x000fe8000c101904 */
/*0510*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0520*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0530*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0540*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0550*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*0560*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x0001e4000c101904 */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0580*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.LT.OR P0, PT, R4, R5, P0 ; /* 0x000000050400720c */
/* 0x000fda0000701670 */
/*05b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05c0*/ STG.E [R2.64+-0x8], R0 ; /* 0xfffff80002007986 */
/* 0x000fe8000c101904 */
/*05d0*/ STG.E [R2.64+-0x4], R0 ; /* 0xfffffc0002007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*05f0*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe2000c101904 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18find_prefix_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P1, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x001fe20003f24070 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0207 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fce0003f06270 */
/*0070*/ @!P1 STS [R7.X4], RZ ; /* 0x000000ff07009388 */
/* 0x0001e80000004800 */
/*0080*/ @!P1 STS [R7.X4+0x400], RZ ; /* 0x000400ff07009388 */
/* 0x0001e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ @P0 BRA 0x140 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0100*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0120*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0130*/ @!P0 BRA 0xb0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0150*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0170*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0180*/ @!P0 BRA 0x300 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fd800078e00ff */
/*01b0*/ @!P0 BRA 0x240 ; /* 0x0000008000008947 */
/* 0x001fea0003800000 */
/*01c0*/ LDS R2, [R7.X4] ; /* 0x0000000007027984 */
/* 0x001e220000004800 */
/*01d0*/ ISETP.GE.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f46270 */
/*01e0*/ @P2 IADD3 R3, R7, -R0, RZ ; /* 0x8000000007032210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ @!P2 STS [R7.X4+0x400], R2 ; /* 0x000400020700a388 */
/* 0x001fea0000004800 */
/*0200*/ @P2 LDS R3, [R3.X4] ; /* 0x0000000003032984 */
/* 0x000e240000004800 */
/*0210*/ @P2 IMAD.IADD R4, R2, 0x1, R3 ; /* 0x0000000102042824 */
/* 0x001fca00078e0203 */
/*0220*/ @P2 STS [R7.X4+0x400], R4 ; /* 0x0004000407002388 */
/* 0x0001e20000004800 */
/*0230*/ BRA 0x2b0 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0240*/ LDS R3, [R7.X4+0x400] ; /* 0x0004000007037984 */
/* 0x000e620000004800 */
/*0250*/ ISETP.GE.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f46270 */
/*0260*/ @P2 IMAD.IADD R4, R7, 0x1, -R0 ; /* 0x0000000107042824 */
/* 0x000fe200078e0a00 */
/*0270*/ @!P2 STS [R7.X4], R3 ; /* 0x000000030700a388 */
/* 0x002fe80000004800 */
/*0280*/ @P2 LDS R2, [R4.X4+0x400] ; /* 0x0004000004022984 */
/* 0x001e240000004800 */
/*0290*/ @P2 IADD3 R2, R2, R3, RZ ; /* 0x0000000302022210 */
/* 0x001fca0007ffe0ff */
/*02a0*/ @P2 STS [R7.X4], R2 ; /* 0x0000000207002388 */
/* 0x0001e40000004800 */
/*02b0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc6000070e170 */
/*02e0*/ ISETP.GE.AND P2, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f46270 */
/*02f0*/ @!P2 BRA 0x1b0 ; /* 0xfffffeb00000a947 */
/* 0x000fea000383ffff */
/*0300*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0310*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e620000004800 */
/*0320*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x001fd400000001ff */
/*0330*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e0002 */
/*0340*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e184 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define HISTOGRAM_SIZE 256 /* Histogram has 256 bins */
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
__global__ void find_prefix_kernel(int *input_data, int *prefix_array, int num_elements, int range)
{
__shared__ unsigned int s[HISTOGRAM_SIZE];
__shared__ unsigned int s_temp[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x <= range){
s[threadIdx.x] = 0;
s_temp[threadIdx.x] = 0;
}
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[input_data[offset]], 1);
offset += stride;
}
__syncthreads();
/* Step 2: Calculate starting indices in output array for storing sorted elements.
* Use inclusive scan of the bin elements. */
int off = 1;
int pingpong_flag = 1;
int tid = threadIdx.x;
while(off < num_elements){
if (pingpong_flag){
if (tid >= off)
s_temp[tid] = s[tid] + s[tid - off];
else
s_temp[tid] = s[tid];
}
else{
if (tid >= off)
s[tid] = s_temp[tid] + s_temp[tid - off];
else
s[tid] = s_temp[tid];
}
__syncthreads();
pingpong_flag = !pingpong_flag;
off = 2*off;
}
/* Accumulate prefix array in shared memory into global memory, and send to CPU */
if (threadIdx.x <= range)
atomicAdd(&prefix_array[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void counting_sort_kernel(int *prefix_array, int *sorted_array, int num_elements, int range)
{
__shared__ unsigned int prefix_shared[HISTOGRAM_SIZE];
/* Get prefix array from CPU, copy to shared mem and arrange the sorted array */
int tid = threadIdx.x;
if (tid <= range)
prefix_shared[tid] = prefix_array[tid];
__syncthreads();
int start_idx = 0;
int j = 0;
if (tid == 0)
start_idx = 0;
else
start_idx = prefix_shared[tid-1];
int end_idx = prefix_shared[tid];
for (j = start_idx; j < end_idx; j++)
sorted_array[j] = tid;
return;
} | .file "tmpxft_001390fe_00000000-6_counting_sort_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii
.type _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii, @function
_Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18find_prefix_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii, .-_Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii
.globl _Z18find_prefix_kernelPiS_ii
.type _Z18find_prefix_kernelPiS_ii, @function
_Z18find_prefix_kernelPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18find_prefix_kernelPiS_ii, .-_Z18find_prefix_kernelPiS_ii
.globl _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.type _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, @function
_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, .-_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.type _Z20counting_sort_kernelPiS_ii, @function
_Z20counting_sort_kernelPiS_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z20counting_sort_kernelPiS_ii, .-_Z20counting_sort_kernelPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20counting_sort_kernelPiS_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z18find_prefix_kernelPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18find_prefix_kernelPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define HISTOGRAM_SIZE 256 /* Histogram has 256 bins */
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
__global__ void find_prefix_kernel(int *input_data, int *prefix_array, int num_elements, int range)
{
__shared__ unsigned int s[HISTOGRAM_SIZE];
__shared__ unsigned int s_temp[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x <= range){
s[threadIdx.x] = 0;
s_temp[threadIdx.x] = 0;
}
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[input_data[offset]], 1);
offset += stride;
}
__syncthreads();
/* Step 2: Calculate starting indices in output array for storing sorted elements.
* Use inclusive scan of the bin elements. */
int off = 1;
int pingpong_flag = 1;
int tid = threadIdx.x;
while(off < num_elements){
if (pingpong_flag){
if (tid >= off)
s_temp[tid] = s[tid] + s[tid - off];
else
s_temp[tid] = s[tid];
}
else{
if (tid >= off)
s[tid] = s_temp[tid] + s_temp[tid - off];
else
s[tid] = s_temp[tid];
}
__syncthreads();
pingpong_flag = !pingpong_flag;
off = 2*off;
}
/* Accumulate prefix array in shared memory into global memory, and send to CPU */
if (threadIdx.x <= range)
atomicAdd(&prefix_array[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void counting_sort_kernel(int *prefix_array, int *sorted_array, int num_elements, int range)
{
__shared__ unsigned int prefix_shared[HISTOGRAM_SIZE];
/* Get prefix array from CPU, copy to shared mem and arrange the sorted array */
int tid = threadIdx.x;
if (tid <= range)
prefix_shared[tid] = prefix_array[tid];
__syncthreads();
int start_idx = 0;
int j = 0;
if (tid == 0)
start_idx = 0;
else
start_idx = prefix_shared[tid-1];
int end_idx = prefix_shared[tid];
for (j = start_idx; j < end_idx; j++)
sorted_array[j] = tid;
return;
} | #include <hip/hip_runtime.h>
#define HISTOGRAM_SIZE 256 /* Histogram has 256 bins */
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
__global__ void find_prefix_kernel(int *input_data, int *prefix_array, int num_elements, int range)
{
__shared__ unsigned int s[HISTOGRAM_SIZE];
__shared__ unsigned int s_temp[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x <= range){
s[threadIdx.x] = 0;
s_temp[threadIdx.x] = 0;
}
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[input_data[offset]], 1);
offset += stride;
}
__syncthreads();
/* Step 2: Calculate starting indices in output array for storing sorted elements.
* Use inclusive scan of the bin elements. */
int off = 1;
int pingpong_flag = 1;
int tid = threadIdx.x;
while(off < num_elements){
if (pingpong_flag){
if (tid >= off)
s_temp[tid] = s[tid] + s[tid - off];
else
s_temp[tid] = s[tid];
}
else{
if (tid >= off)
s[tid] = s_temp[tid] + s_temp[tid - off];
else
s[tid] = s_temp[tid];
}
__syncthreads();
pingpong_flag = !pingpong_flag;
off = 2*off;
}
/* Accumulate prefix array in shared memory into global memory, and send to CPU */
if (threadIdx.x <= range)
atomicAdd(&prefix_array[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void counting_sort_kernel(int *prefix_array, int *sorted_array, int num_elements, int range)
{
__shared__ unsigned int prefix_shared[HISTOGRAM_SIZE];
/* Get prefix array from CPU, copy to shared mem and arrange the sorted array */
int tid = threadIdx.x;
if (tid <= range)
prefix_shared[tid] = prefix_array[tid];
__syncthreads();
int start_idx = 0;
int j = 0;
if (tid == 0)
start_idx = 0;
else
start_idx = prefix_shared[tid-1];
int end_idx = prefix_shared[tid];
for (j = start_idx; j < end_idx; j++)
sorted_array[j] = tid;
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define HISTOGRAM_SIZE 256 /* Histogram has 256 bins */
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
__global__ void find_prefix_kernel(int *input_data, int *prefix_array, int num_elements, int range)
{
__shared__ unsigned int s[HISTOGRAM_SIZE];
__shared__ unsigned int s_temp[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x <= range){
s[threadIdx.x] = 0;
s_temp[threadIdx.x] = 0;
}
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[input_data[offset]], 1);
offset += stride;
}
__syncthreads();
/* Step 2: Calculate starting indices in output array for storing sorted elements.
* Use inclusive scan of the bin elements. */
int off = 1;
int pingpong_flag = 1;
int tid = threadIdx.x;
while(off < num_elements){
if (pingpong_flag){
if (tid >= off)
s_temp[tid] = s[tid] + s[tid - off];
else
s_temp[tid] = s[tid];
}
else{
if (tid >= off)
s[tid] = s_temp[tid] + s_temp[tid - off];
else
s[tid] = s_temp[tid];
}
__syncthreads();
pingpong_flag = !pingpong_flag;
off = 2*off;
}
/* Accumulate prefix array in shared memory into global memory, and send to CPU */
if (threadIdx.x <= range)
atomicAdd(&prefix_array[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void counting_sort_kernel(int *prefix_array, int *sorted_array, int num_elements, int range)
{
__shared__ unsigned int prefix_shared[HISTOGRAM_SIZE];
/* Get prefix array from CPU, copy to shared mem and arrange the sorted array */
int tid = threadIdx.x;
if (tid <= range)
prefix_shared[tid] = prefix_array[tid];
__syncthreads();
int start_idx = 0;
int j = 0;
if (tid == 0)
start_idx = 0;
else
start_idx = prefix_shared[tid-1];
int end_idx = prefix_shared[tid];
for (j = start_idx; j < end_idx; j++)
sorted_array[j] = tid;
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18find_prefix_kernelPiS_ii
.globl _Z18find_prefix_kernelPiS_ii
.p2align 8
.type _Z18find_prefix_kernelPiS_ii,@function
_Z18find_prefix_kernelPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_ge_u32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_2addr_stride64_b32 v1, v2, v2 offset1:4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_5
s_load_b32 s4, s[4:5], 0x0
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s3
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s5, 0
.LBB0_4:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s3, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s3, s7, v3, s3
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_lt_i32 s8, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_20
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s4, 1
s_mov_b32 s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0x400, v1
s_branch .LBB0_9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_lshl_b32 s5, s5, 1
s_xor_b32 s4, s4, 1
s_cmp_lt_i32 s5, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_20
.LBB0_9:
v_cmp_le_u32_e64 s3, s5, v0
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s3
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_12
v_subrev_nc_u32_e32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v1
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v4
ds_store_b32 v2, v3
.LBB0_12:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_14
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v3
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_8
s_branch .LBB0_16
.LBB0_15:
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s3
s_xor_b32 s3, exec_lo, s6
s_cbranch_execz .LBB0_18
v_subrev_nc_u32_e32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v2
ds_load_b32 v3, v3 offset:1024
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v4
ds_store_b32 v1, v3
.LBB0_18:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_7
ds_load_b32 v3, v2
s_waitcnt lgkmcnt(0)
ds_store_b32 v1, v3
s_branch .LBB0_7
.LBB0_20:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_22
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18find_prefix_kernelPiS_ii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18find_prefix_kernelPiS_ii, .Lfunc_end0-_Z18find_prefix_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20counting_sort_kernelPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.p2align 8
.type _Z20counting_sort_kernelPiS_ii,@function
_Z20counting_sort_kernelPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v1, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB1_4
v_lshl_add_u32 v1, v0, 2, -4
ds_load_b32 v1, v1
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s2, exec_lo
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e64 v1, v4
s_cbranch_execz .LBB1_7
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s1, 0
.LBB1_6:
v_add_nc_u32_e32 v1, 1, v1
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
v_cmp_ge_i32_e32 vcc_lo, v1, v4
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_6
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20counting_sort_kernelPiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20counting_sort_kernelPiS_ii, .Lfunc_end1-_Z20counting_sort_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18find_prefix_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18find_prefix_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20counting_sort_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z20counting_sort_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define HISTOGRAM_SIZE 256 /* Histogram has 256 bins */
/* Write GPU code to perform the step(s) involved in counting sort.
Add additional kernels and device functions as needed. */
__global__ void find_prefix_kernel(int *input_data, int *prefix_array, int num_elements, int range)
{
__shared__ unsigned int s[HISTOGRAM_SIZE];
__shared__ unsigned int s_temp[HISTOGRAM_SIZE];
/* Initialize shared memory */
if(threadIdx.x <= range){
s[threadIdx.x] = 0;
s_temp[threadIdx.x] = 0;
}
__syncthreads();
int offset = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
while (offset < num_elements) {
atomicAdd(&s[input_data[offset]], 1);
offset += stride;
}
__syncthreads();
/* Step 2: Calculate starting indices in output array for storing sorted elements.
* Use inclusive scan of the bin elements. */
int off = 1;
int pingpong_flag = 1;
int tid = threadIdx.x;
while(off < num_elements){
if (pingpong_flag){
if (tid >= off)
s_temp[tid] = s[tid] + s[tid - off];
else
s_temp[tid] = s[tid];
}
else{
if (tid >= off)
s[tid] = s_temp[tid] + s_temp[tid - off];
else
s[tid] = s_temp[tid];
}
__syncthreads();
pingpong_flag = !pingpong_flag;
off = 2*off;
}
/* Accumulate prefix array in shared memory into global memory, and send to CPU */
if (threadIdx.x <= range)
atomicAdd(&prefix_array[threadIdx.x], s[threadIdx.x]);
return;
}
__global__ void counting_sort_kernel(int *prefix_array, int *sorted_array, int num_elements, int range)
{
__shared__ unsigned int prefix_shared[HISTOGRAM_SIZE];
/* Get prefix array from CPU, copy to shared mem and arrange the sorted array */
int tid = threadIdx.x;
if (tid <= range)
prefix_shared[tid] = prefix_array[tid];
__syncthreads();
int start_idx = 0;
int j = 0;
if (tid == 0)
start_idx = 0;
else
start_idx = prefix_shared[tid-1];
int end_idx = prefix_shared[tid];
for (j = start_idx; j < end_idx; j++)
sorted_array[j] = tid;
return;
} | .text
.file "counting_sort_kernel.hip"
.globl _Z33__device_stub__find_prefix_kernelPiS_ii # -- Begin function _Z33__device_stub__find_prefix_kernelPiS_ii
.p2align 4, 0x90
.type _Z33__device_stub__find_prefix_kernelPiS_ii,@function
_Z33__device_stub__find_prefix_kernelPiS_ii: # @_Z33__device_stub__find_prefix_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18find_prefix_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__find_prefix_kernelPiS_ii, .Lfunc_end0-_Z33__device_stub__find_prefix_kernelPiS_ii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__counting_sort_kernelPiS_ii # -- Begin function _Z35__device_stub__counting_sort_kernelPiS_ii
.p2align 4, 0x90
.type _Z35__device_stub__counting_sort_kernelPiS_ii,@function
_Z35__device_stub__counting_sort_kernelPiS_ii: # @_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20counting_sort_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z35__device_stub__counting_sort_kernelPiS_ii, .Lfunc_end1-_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18find_prefix_kernelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20counting_sort_kernelPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18find_prefix_kernelPiS_ii,@object # @_Z18find_prefix_kernelPiS_ii
.section .rodata,"a",@progbits
.globl _Z18find_prefix_kernelPiS_ii
.p2align 3, 0x0
_Z18find_prefix_kernelPiS_ii:
.quad _Z33__device_stub__find_prefix_kernelPiS_ii
.size _Z18find_prefix_kernelPiS_ii, 8
.type _Z20counting_sort_kernelPiS_ii,@object # @_Z20counting_sort_kernelPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.p2align 3, 0x0
_Z20counting_sort_kernelPiS_ii:
.quad _Z35__device_stub__counting_sort_kernelPiS_ii
.size _Z20counting_sort_kernelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18find_prefix_kernelPiS_ii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20counting_sort_kernelPiS_ii"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__find_prefix_kernelPiS_ii
.addrsig_sym _Z35__device_stub__counting_sort_kernelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18find_prefix_kernelPiS_ii
.addrsig_sym _Z20counting_sort_kernelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20counting_sort_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xd0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GT.AND P0, PT, R0.reuse, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x041fe40003f04270 */
/*0060*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f25270 */
/*0070*/ @P0 BRA 0xc0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0041e40000004800 */
/*00c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P1 LDS R4, [R0.X4+-0x4] ; /* 0xfffffc0000041984 */
/* 0x000fe80000004800 */
/*00f0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e640000004800 */
/*0100*/ ISETP.GT.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x002fda0003f04270 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ LOP3.LUT R6, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff067212 */
/* 0x000fe200078e33ff */
/*0130*/ IMAD.IADD R2, R5.reuse, 0x1, -R4 ; /* 0x0000000105027824 */
/* 0x040fe200078e0a04 */
/*0140*/ BSSY B0, 0x230 ; /* 0x000000e000007945 */
/* 0x000fe60003800000 */
/*0150*/ IMAD.IADD R3, R5, 0x1, R6 ; /* 0x0000000105037824 */
/* 0x001fe200078e0206 */
/*0160*/ LOP3.LUT P1, R6, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302067812 */
/* 0x000fc8000782c0ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fd20003f06070 */
/*0180*/ @!P1 BRA 0x220 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0203 */
/*01b0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e2000c101904 */
/*01d0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*01f0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*0200*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fcc00010e0603 */
/*0210*/ @P1 BRA 0x1b0 ; /* 0xffffff9000001947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0240*/ IMAD.IADD R6, R5, 0x1, -R4 ; /* 0x0000000105067824 */
/* 0x000fe200078e0a04 */
/*0250*/ BSSY B0, 0x470 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0280*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0203 */
/*0290*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f1e0ff */
/*02a0*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*02c0*/ @!P1 BRA 0x460 ; /* 0x0000019000009947 */
/* 0x000fee0003800000 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02e0*/ IADD3 R7, R5, -0xc, RZ ; /* 0xfffffff405077810 */
/* 0x000fc60007ffe0ff */
/*02f0*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0300*/ STG.E [R2.64+-0x8], R0 ; /* 0xfffff80002007986 */
/* 0x000fe2000c101904 */
/*0310*/ IADD3 R6, P2, R2, 0x40, RZ ; /* 0x0000004002067810 */
/* 0x000fe40007f5e0ff */
/*0320*/ ISETP.GE.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe20003f26270 */
/*0330*/ STG.E [R2.64+-0x4], R0 ; /* 0xfffffc0002007986 */
/* 0x000fe4000c101904 */
/*0340*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fc400010e0603 */
/*0350*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0380*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0390*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R2.64+0x18], R0 ; /* 0x0000180002007986 */
/* 0x000fe8000c101904 */
/*03c0*/ STG.E [R2.64+0x1c], R0 ; /* 0x00001c0002007986 */
/* 0x000fe8000c101904 */
/*03d0*/ STG.E [R2.64+0x20], R0 ; /* 0x0000200002007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R2.64+0x24], R0 ; /* 0x0000240002007986 */
/* 0x000fe8000c101904 */
/*03f0*/ STG.E [R2.64+0x28], R0 ; /* 0x0000280002007986 */
/* 0x000fe8000c101904 */
/*0400*/ STG.E [R2.64+0x2c], R0 ; /* 0x00002c0002007986 */
/* 0x000fe8000c101904 */
/*0410*/ STG.E [R2.64+0x30], R0 ; /* 0x0000300002007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R2.64+0x34], R0 ; /* 0x0000340002007986 */
/* 0x0001e4000c101904 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0450*/ @!P1 BRA 0x2f0 ; /* 0xfffffe9000009947 */
/* 0x000fea000383ffff */
/*0460*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.IADD R6, R5, 0x1, -R4 ; /* 0x0000000105067824 */
/* 0x000fe200078e0a04 */
/*0480*/ BSSY B0, 0x5a0 ; /* 0x0000011000007945 */
/* 0x000fe80003800000 */
/*0490*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*04a0*/ @!P1 BRA 0x590 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*04b0*/ IADD3 R6, P1, R2, 0x20, RZ ; /* 0x0000002002067810 */
/* 0x000fe20007f3e0ff */
/*04c0*/ STG.E [R2.64+-0x8], R0 ; /* 0xfffff80002007986 */
/* 0x000fe2000c101904 */
/*04d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04e0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*04f0*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0603 */
/*0500*/ STG.E [R2.64+-0x4], R0 ; /* 0xfffffc0002007986 */
/* 0x000fe8000c101904 */
/*0510*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0520*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe8000c101904 */
/*0530*/ STG.E [R2.64+0x8], R0 ; /* 0x0000080002007986 */
/* 0x000fe8000c101904 */
/*0540*/ STG.E [R2.64+0xc], R0 ; /* 0x00000c0002007986 */
/* 0x000fe8000c101904 */
/*0550*/ STG.E [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101904 */
/*0560*/ STG.E [R2.64+0x14], R0 ; /* 0x0000140002007986 */
/* 0x0001e4000c101904 */
/*0570*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0006 */
/*0580*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.LT.OR P0, PT, R4, R5, P0 ; /* 0x000000050400720c */
/* 0x000fda0000701670 */
/*05b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05c0*/ STG.E [R2.64+-0x8], R0 ; /* 0xfffff80002007986 */
/* 0x000fe8000c101904 */
/*05d0*/ STG.E [R2.64+-0x4], R0 ; /* 0xfffffc0002007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*05f0*/ STG.E [R2.64+0x4], R0 ; /* 0x0000040002007986 */
/* 0x000fe2000c101904 */
/*0600*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0610*/ BRA 0x610; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18find_prefix_kernelPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0040*/ ISETP.GT.U32.AND P1, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x001fe20003f24070 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0207 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fce0003f06270 */
/*0070*/ @!P1 STS [R7.X4], RZ ; /* 0x000000ff07009388 */
/* 0x0001e80000004800 */
/*0080*/ @!P1 STS [R7.X4+0x400], RZ ; /* 0x000400ff07009388 */
/* 0x0001e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ @P0 BRA 0x140 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0203 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*00f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0100*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0120*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0130*/ @!P0 BRA 0xb0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0150*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0170*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f06270 */
/*0180*/ @!P0 BRA 0x300 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fd800078e00ff */
/*01b0*/ @!P0 BRA 0x240 ; /* 0x0000008000008947 */
/* 0x001fea0003800000 */
/*01c0*/ LDS R2, [R7.X4] ; /* 0x0000000007027984 */
/* 0x001e220000004800 */
/*01d0*/ ISETP.GE.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f46270 */
/*01e0*/ @P2 IADD3 R3, R7, -R0, RZ ; /* 0x8000000007032210 */
/* 0x000fe20007ffe0ff */
/*01f0*/ @!P2 STS [R7.X4+0x400], R2 ; /* 0x000400020700a388 */
/* 0x001fea0000004800 */
/*0200*/ @P2 LDS R3, [R3.X4] ; /* 0x0000000003032984 */
/* 0x000e240000004800 */
/*0210*/ @P2 IMAD.IADD R4, R2, 0x1, R3 ; /* 0x0000000102042824 */
/* 0x001fca00078e0203 */
/*0220*/ @P2 STS [R7.X4+0x400], R4 ; /* 0x0004000407002388 */
/* 0x0001e20000004800 */
/*0230*/ BRA 0x2b0 ; /* 0x0000007000007947 */
/* 0x000fea0003800000 */
/*0240*/ LDS R3, [R7.X4+0x400] ; /* 0x0004000007037984 */
/* 0x000e620000004800 */
/*0250*/ ISETP.GE.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f46270 */
/*0260*/ @P2 IMAD.IADD R4, R7, 0x1, -R0 ; /* 0x0000000107042824 */
/* 0x000fe200078e0a00 */
/*0270*/ @!P2 STS [R7.X4], R3 ; /* 0x000000030700a388 */
/* 0x002fe80000004800 */
/*0280*/ @P2 LDS R2, [R4.X4+0x400] ; /* 0x0004000004022984 */
/* 0x001e240000004800 */
/*0290*/ @P2 IADD3 R2, R2, R3, RZ ; /* 0x0000000302022210 */
/* 0x001fca0007ffe0ff */
/*02a0*/ @P2 STS [R7.X4], R2 ; /* 0x0000000207002388 */
/* 0x0001e40000004800 */
/*02b0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fe200078e00ff */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02d0*/ PLOP3.LUT P0, PT, P0, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc6000070e170 */
/*02e0*/ ISETP.GE.AND P2, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f46270 */
/*02f0*/ @!P2 BRA 0x1b0 ; /* 0xfffffeb00000a947 */
/* 0x000fea000383ffff */
/*0300*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0310*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e620000004800 */
/*0320*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x001fd400000001ff */
/*0330*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e0002 */
/*0340*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x002fe2000c10e184 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18find_prefix_kernelPiS_ii
.globl _Z18find_prefix_kernelPiS_ii
.p2align 8
.type _Z18find_prefix_kernelPiS_ii,@function
_Z18find_prefix_kernelPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_ge_u32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
ds_store_2addr_stride64_b32 v1, v2, v2 offset1:4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_5
s_load_b32 s4, s[4:5], 0x0
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s4, s3
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s5, 0
.LBB0_4:
global_load_b32 v5, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s3, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s3, s7, v3, s3
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, 2, v5
ds_add_u32 v5, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_lt_i32 s8, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_20
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s4, 1
s_mov_b32 s5, 1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v2, 0x400, v1
s_branch .LBB0_9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_lshl_b32 s5, s5, 1
s_xor_b32 s4, s4, 1
s_cmp_lt_i32 s5, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_20
.LBB0_9:
v_cmp_le_u32_e64 s3, s5, v0
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s3
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_12
v_subrev_nc_u32_e32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v1
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v4
ds_store_b32 v2, v3
.LBB0_12:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_14
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
ds_store_b32 v2, v3
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_8
s_branch .LBB0_16
.LBB0_15:
.LBB0_16:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s3
s_xor_b32 s3, exec_lo, s6
s_cbranch_execz .LBB0_18
v_subrev_nc_u32_e32 v3, s5, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v3, 2, v3
ds_load_b32 v4, v2
ds_load_b32 v3, v3 offset:1024
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v4
ds_store_b32 v1, v3
.LBB0_18:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_7
ds_load_b32 v3, v2
s_waitcnt lgkmcnt(0)
ds_store_b32 v1, v3
s_branch .LBB0_7
.LBB0_20:
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_22
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18find_prefix_kernelPiS_ii
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18find_prefix_kernelPiS_ii, .Lfunc_end0-_Z18find_prefix_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20counting_sort_kernelPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.p2align 8
.type _Z20counting_sort_kernelPiS_ii,@function
_Z20counting_sort_kernelPiS_ii:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v1, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB1_4
v_lshl_add_u32 v1, v0, 2, -4
ds_load_b32 v1, v1
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s2, exec_lo
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_cmpx_lt_i32_e64 v1, v4
s_cbranch_execz .LBB1_7
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b32 s1, 0
.LBB1_6:
v_add_nc_u32_e32 v1, 1, v1
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
v_cmp_ge_i32_e32 vcc_lo, v1, v4
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_6
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20counting_sort_kernelPiS_ii
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20counting_sort_kernelPiS_ii, .Lfunc_end1-_Z20counting_sort_kernelPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18find_prefix_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18find_prefix_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20counting_sort_kernelPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z20counting_sort_kernelPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001390fe_00000000-6_counting_sort_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii
.type _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii, @function
_Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18find_prefix_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii, .-_Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii
.globl _Z18find_prefix_kernelPiS_ii
.type _Z18find_prefix_kernelPiS_ii, @function
_Z18find_prefix_kernelPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18find_prefix_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18find_prefix_kernelPiS_ii, .-_Z18find_prefix_kernelPiS_ii
.globl _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.type _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, @function
_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii, .-_Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.type _Z20counting_sort_kernelPiS_ii, @function
_Z20counting_sort_kernelPiS_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20counting_sort_kernelPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z20counting_sort_kernelPiS_ii, .-_Z20counting_sort_kernelPiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20counting_sort_kernelPiS_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z18find_prefix_kernelPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20counting_sort_kernelPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z18find_prefix_kernelPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "counting_sort_kernel.hip"
.globl _Z33__device_stub__find_prefix_kernelPiS_ii # -- Begin function _Z33__device_stub__find_prefix_kernelPiS_ii
.p2align 4, 0x90
.type _Z33__device_stub__find_prefix_kernelPiS_ii,@function
_Z33__device_stub__find_prefix_kernelPiS_ii: # @_Z33__device_stub__find_prefix_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18find_prefix_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__find_prefix_kernelPiS_ii, .Lfunc_end0-_Z33__device_stub__find_prefix_kernelPiS_ii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__counting_sort_kernelPiS_ii # -- Begin function _Z35__device_stub__counting_sort_kernelPiS_ii
.p2align 4, 0x90
.type _Z35__device_stub__counting_sort_kernelPiS_ii,@function
_Z35__device_stub__counting_sort_kernelPiS_ii: # @_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20counting_sort_kernelPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z35__device_stub__counting_sort_kernelPiS_ii, .Lfunc_end1-_Z35__device_stub__counting_sort_kernelPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18find_prefix_kernelPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20counting_sort_kernelPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18find_prefix_kernelPiS_ii,@object # @_Z18find_prefix_kernelPiS_ii
.section .rodata,"a",@progbits
.globl _Z18find_prefix_kernelPiS_ii
.p2align 3, 0x0
_Z18find_prefix_kernelPiS_ii:
.quad _Z33__device_stub__find_prefix_kernelPiS_ii
.size _Z18find_prefix_kernelPiS_ii, 8
.type _Z20counting_sort_kernelPiS_ii,@object # @_Z20counting_sort_kernelPiS_ii
.globl _Z20counting_sort_kernelPiS_ii
.p2align 3, 0x0
_Z20counting_sort_kernelPiS_ii:
.quad _Z35__device_stub__counting_sort_kernelPiS_ii
.size _Z20counting_sort_kernelPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18find_prefix_kernelPiS_ii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20counting_sort_kernelPiS_ii"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__find_prefix_kernelPiS_ii
.addrsig_sym _Z35__device_stub__counting_sort_kernelPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18find_prefix_kernelPiS_ii
.addrsig_sym _Z20counting_sort_kernelPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
//#include <cuda.h>
//#include "cuda_runtime_api.h"
//#include <stdint.h>
//#include <stdlib.h>
//This is the working matrix multiplication code - very basic
/*
Done:
- printing of matrix in a more pleasant manner using printMatrix function
- command line arguments
- opens matrix files and reads the matrix successfully
- working array passing from main to auxiliary (loadMatrixFile) function :)
- fixed printing of matrix
- fixed erroneous matrix values by moving loading into host matrix multiplication function!
Problems:
- (fixed) MatA and MatB values are overlapping and erroneous
*/
// START of AUXILIARY functions
//START vector addition kernel function
__global__ void MatrixAddKernel ( int *Md, int *Nd, int *Pd, int N ){
int tid = blockIdx.x; //thred id
if ( tid < N )
Pd[ tid ] = Md[ tid ] + Nd[ tid ];
/* int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue = Mdelement + Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue; */
}
//END of kernel addition
//Start of kernel multiplication
__global__ void MatrixMulKernel ( int *Md, int *Nd, int *Pd, int Width ){
int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue += Mdelement * Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue;
}
//End of kernel multiplication
//function to print matrix
void printMatrix ( int *M, int rows, int columns ){
//assumes matrix is in row-major format
int index;
printf ( "\n \n " );
for ( int v = 0; v < rows; v++ ){
//assumes a square matrix
for ( int w = 0; w < columns; w++ ) {
index = v * columns + w;
printf ( " %02d", M[ index ] );
}
printf ( " \n\n " );
}
}//End of printMatrix function
//START of loadMatrixFile
void loadMatrixFile( char *filename, int *z, int matWidth, int matHeight ){
int y = 0;
int w = 0;
int x;
int offset = 0;
FILE *ptr1 = fopen( filename, "r" );
// int *z = ( int * )malloc( sizeof( ( matWidth * matHeight ) ) );
//int z[ ( matWidth * matHeight ) + offset ] ;
fscanf( ptr1, " %d", &x );
while( !feof( ptr1 ) && y < ( matWidth * matHeight ) + 1 ){
if ( y > offset ){
fscanf( ptr1, " %d", &z[ w - offset ] );
//printf( " B: z[ %d ]: %d \n", w, z[ w - offset ] );
w++;
}
else{
fscanf( ptr1, " %d", &x );
}
y++;
}
fclose( ptr1 );
// x = y = w = 0;
// array = &z[ 0 ];
// free( z );
}
//END of loadMatrixFile
//Start of matrix multiplication host function MatrixMul
void MatrixMul( char *filename0, char *filename1, char *filename2, int Width /*, int *M, int *N, int *P, int Width*/ ){
int size = Width * Width * sizeof( int );
int *Md, *Nd, *Pd;
dim3 dimBlock( Width, Width );
dim3 dimGrid( 1, 1 );
int *matA = ( int * )malloc( size );
//printf( "Width and height of Matrix A: %d %d and init values are\n", Width, Width );
//printMatrix( matA, Width, Width );
loadMatrixFile( filename1, matA, Width, Width );
printf( " \ns after loading from file: \n" );
printMatrix( matA, Width, Width );
int *matB = ( int * )malloc( size );
loadMatrixFile( filename2, matB, Width, Width );
printf( " \nM after loading from file: \n" );
printMatrix( matB, Width, Width );
//assumes a square matrix
int *matC = ( int * )malloc( size );
cudaMalloc( (void**) &Md, size );
cudaMemcpy( Md, matA, size, cudaMemcpyHostToDevice );
cudaMalloc( (void**) &Nd, size );
cudaMemcpy( Nd, matB, size, cudaMemcpyHostToDevice );
cudaMalloc( (void**) &Pd, size );
MatrixMulKernel<<< dimGrid, dimBlock >>>( Md, Nd, Pd, Width );
//MatrixAddKernel<<< N, 1 >>>( Md, Nd, Pd );
cudaMemcpy( matC, Pd, size, cudaMemcpyDeviceToHost );
printf( " \ns * M: \n" );
printMatrix( matC, Width, Width );
free( matA ); free( matB ); free( matC );
cudaFree( Md ); cudaFree( Nd ); cudaFree ( Pd );
}
//End of Matrix multiplication function MatrixMul
//END of AUXILIARY functions
//START of MAIN function
int main ( int argc, char *argv[ ] ) {
int offset = 2;
if ( argc != 5 ) {
printf( "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n", argv [ 0 ] );
}
else {
char *confVec = argv[ 1 ];
char *spikVec = argv[ 2 ];
char *spikTransMat = argv[ 3 ];
int width = atoi( argv[ 4 ] );
printf( "\nYou have entered files %s, %s, and %s and square matrix width %d \n", spikVec, confVec, spikTransMat, width );
//load matrices from files
FILE *ptr1 = fopen( confVec, "r" );
FILE *ptr2 = fopen( spikVec, "r" );
FILE *ptr3 = fopen( spikTransMat, "r" );
if ( ptr1 == 0 && ptr2 == 0 && ptr3 == 0 )
printf( "\n could not open one of the following files: %s %s \n", argv[ 1 ], argv[ 2 ] );
else {
MatrixMul( confVec, spikVec, spikTransMat, width );
}
fclose( ptr1 ); fclose( ptr2 ); fclose( ptr3 );
}
}
//END of MAIN function | code for sm_80
Function : _Z15MatrixMulKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xba0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa80 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0140*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fce00078e0219 */
/*0150*/ @!P0 BRA 0x8f0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0160*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0180*/ @!P1 BRA 0x630 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01a0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01b0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01c0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01d0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01e0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0200*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0210*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0220*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0230*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0240*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0250*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0260*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0270*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02a0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02d0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*02f0*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0300*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0310*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0320*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0330*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0350*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0360*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*0370*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0380*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0390*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03a0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03b0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03c0*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*03d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03e0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0420*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0430*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0440*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0450*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0460*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0470*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0480*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0490*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04a0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04b0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04c0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04d0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04e0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0500*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0510*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0530*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0560*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*0570*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*0580*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0590*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05a0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05b0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05d0*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*05e0*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*05f0*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0600*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0610*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0620*/ @P1 BRA 0x1a0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0630*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0640*/ @!P1 BRA 0x8d0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0660*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0670*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0680*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0690*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06a0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06b0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06c0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06d0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06e0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*06f0*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0700*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0710*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0720*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0730*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0740*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0750*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0760*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0770*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0780*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0790*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07a0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07c0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07d0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*07f0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0810*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0820*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0830*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0840*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0850*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*0860*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*0870*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*0880*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0890*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08a0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08b0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08c0*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*08d0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08e0*/ @!P0 BRA 0xa80 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*08f0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0900*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0910*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0920*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0930*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0940*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0950*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0970*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0980*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0990*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09a0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09c0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09d0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*09f0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a00*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a10*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a20*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a30*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a40*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a50*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0a60*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0a70*/ @P0 BRA 0x8f0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0a90*/ @!P0 BRA 0xba0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ab0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ad0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0ae0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0af0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b00*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b10*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b20*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b30*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b50*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b60*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b70*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b80*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0b90*/ @P0 BRA 0xb00 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0ba0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bb0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bc0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bd0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0be0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bf0*/ BRA 0xbf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15MatrixAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
//#include <cuda.h>
//#include "cuda_runtime_api.h"
//#include <stdint.h>
//#include <stdlib.h>
//This is the working matrix multiplication code - very basic
/*
Done:
- printing of matrix in a more pleasant manner using printMatrix function
- command line arguments
- opens matrix files and reads the matrix successfully
- working array passing from main to auxiliary (loadMatrixFile) function :)
- fixed printing of matrix
- fixed erroneous matrix values by moving loading into host matrix multiplication function!
Problems:
- (fixed) MatA and MatB values are overlapping and erroneous
*/
// START of AUXILIARY functions
//START vector addition kernel function
__global__ void MatrixAddKernel ( int *Md, int *Nd, int *Pd, int N ){
int tid = blockIdx.x; //thred id
if ( tid < N )
Pd[ tid ] = Md[ tid ] + Nd[ tid ];
/* int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue = Mdelement + Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue; */
}
//END of kernel addition
//Start of kernel multiplication
__global__ void MatrixMulKernel ( int *Md, int *Nd, int *Pd, int Width ){
int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue += Mdelement * Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue;
}
//End of kernel multiplication
//function to print matrix
void printMatrix ( int *M, int rows, int columns ){
//assumes matrix is in row-major format
int index;
printf ( "\n \n " );
for ( int v = 0; v < rows; v++ ){
//assumes a square matrix
for ( int w = 0; w < columns; w++ ) {
index = v * columns + w;
printf ( " %02d", M[ index ] );
}
printf ( " \n\n " );
}
}//End of printMatrix function
//START of loadMatrixFile
void loadMatrixFile( char *filename, int *z, int matWidth, int matHeight ){
int y = 0;
int w = 0;
int x;
int offset = 0;
FILE *ptr1 = fopen( filename, "r" );
// int *z = ( int * )malloc( sizeof( ( matWidth * matHeight ) ) );
//int z[ ( matWidth * matHeight ) + offset ] ;
fscanf( ptr1, " %d", &x );
while( !feof( ptr1 ) && y < ( matWidth * matHeight ) + 1 ){
if ( y > offset ){
fscanf( ptr1, " %d", &z[ w - offset ] );
//printf( " B: z[ %d ]: %d \n", w, z[ w - offset ] );
w++;
}
else{
fscanf( ptr1, " %d", &x );
}
y++;
}
fclose( ptr1 );
// x = y = w = 0;
// array = &z[ 0 ];
// free( z );
}
//END of loadMatrixFile
//Start of matrix multiplication host function MatrixMul
void MatrixMul( char *filename0, char *filename1, char *filename2, int Width /*, int *M, int *N, int *P, int Width*/ ){
int size = Width * Width * sizeof( int );
int *Md, *Nd, *Pd;
dim3 dimBlock( Width, Width );
dim3 dimGrid( 1, 1 );
int *matA = ( int * )malloc( size );
//printf( "Width and height of Matrix A: %d %d and init values are\n", Width, Width );
//printMatrix( matA, Width, Width );
loadMatrixFile( filename1, matA, Width, Width );
printf( " \ns after loading from file: \n" );
printMatrix( matA, Width, Width );
int *matB = ( int * )malloc( size );
loadMatrixFile( filename2, matB, Width, Width );
printf( " \nM after loading from file: \n" );
printMatrix( matB, Width, Width );
//assumes a square matrix
int *matC = ( int * )malloc( size );
cudaMalloc( (void**) &Md, size );
cudaMemcpy( Md, matA, size, cudaMemcpyHostToDevice );
cudaMalloc( (void**) &Nd, size );
cudaMemcpy( Nd, matB, size, cudaMemcpyHostToDevice );
cudaMalloc( (void**) &Pd, size );
MatrixMulKernel<<< dimGrid, dimBlock >>>( Md, Nd, Pd, Width );
//MatrixAddKernel<<< N, 1 >>>( Md, Nd, Pd );
cudaMemcpy( matC, Pd, size, cudaMemcpyDeviceToHost );
printf( " \ns * M: \n" );
printMatrix( matC, Width, Width );
free( matA ); free( matB ); free( matC );
cudaFree( Md ); cudaFree( Nd ); cudaFree ( Pd );
}
//End of Matrix multiplication function MatrixMul
//END of AUXILIARY functions
//START of MAIN function
int main ( int argc, char *argv[ ] ) {
int offset = 2;
if ( argc != 5 ) {
printf( "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n", argv [ 0 ] );
}
else {
char *confVec = argv[ 1 ];
char *spikVec = argv[ 2 ];
char *spikTransMat = argv[ 3 ];
int width = atoi( argv[ 4 ] );
printf( "\nYou have entered files %s, %s, and %s and square matrix width %d \n", spikVec, confVec, spikTransMat, width );
//load matrices from files
FILE *ptr1 = fopen( confVec, "r" );
FILE *ptr2 = fopen( spikVec, "r" );
FILE *ptr3 = fopen( spikTransMat, "r" );
if ( ptr1 == 0 && ptr2 == 0 && ptr3 == 0 )
printf( "\n could not open one of the following files: %s %s \n", argv[ 1 ], argv[ 2 ] );
else {
MatrixMul( confVec, spikVec, spikTransMat, width );
}
fclose( ptr1 ); fclose( ptr2 ); fclose( ptr3 );
}
}
//END of MAIN function | .file "tmpxft_0007d02d_00000000-6_mulMatrix-v1-test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n \n "
.LC1:
.string " %02d"
.LC2:
.string " \n\n "
.text
.globl _Z11printMatrixPiii
.type _Z11printMatrixPiii, @function
_Z11printMatrixPiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L3
movl $0, %r14d
movl $0, %r13d
movslq %r15d, %rax
movq %rax, 24(%rsp)
leaq .LC1(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdi
addq %rdi, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPiii, .-_Z11printMatrixPiii
.section .rodata.str1.1
.LC3:
.string "r"
.LC4:
.string " %d"
.text
.globl _Z14loadMatrixFilePcPiii
.type _Z14loadMatrixFilePcPiii, @function
_Z14loadMatrixFilePcPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r15
movl %edx, %r13d
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
leaq 4(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
imull %ebx, %r13d
movl $0, %r12d
movl $0, %ebx
leaq .LC4(%rip), %r14
jmp .L12
.L15:
movslq %r12d, %rax
leaq (%r15,%rax,4), %rdx
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %r12d
.L13:
addl $1, %ebx
.L12:
movq %rbp, %rdi
call feof@PLT
testl %eax, %eax
jne .L14
cmpl %ebx, %r13d
jl .L14
testl %ebx, %ebx
jg .L15
leaq 4(%rsp), %rdx
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
jmp .L13
.L14:
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14loadMatrixFilePcPiii, .-_Z14loadMatrixFilePcPiii
.globl _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i
.globl _Z15MatrixAddKernelPiS_S_i
.type _Z15MatrixAddKernelPiS_S_i, @function
_Z15MatrixAddKernelPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15MatrixAddKernelPiS_S_i, .-_Z15MatrixAddKernelPiS_S_i
.globl _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
.globl _Z15MatrixMulKernelPiS_S_i
.type _Z15MatrixMulKernelPiS_S_i, @function
_Z15MatrixMulKernelPiS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15MatrixMulKernelPiS_S_i, .-_Z15MatrixMulKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " \ns after loading from file: \n"
.align 8
.LC6:
.string " \nM after loading from file: \n"
.section .rodata.str1.1
.LC7:
.string " \ns * M: \n"
.text
.globl _Z9MatrixMulPcS_S_i
.type _Z9MatrixMulPcS_S_i, @function
_Z9MatrixMulPcS_S_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r12
movq %rdx, %r14
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, 32(%rsp)
movl %ecx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ecx, %ebp
imull %ecx, %ebp
sall $2, %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %ecx
movl %ebx, %edx
movq %rax, %rsi
movq %r12, %rdi
call _Z14loadMatrixFilePcPiii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r13, %rdi
call _Z11printMatrixPiii
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebx, %ecx
movl %ebx, %edx
movq %rax, %rsi
movq %r14, %rdi
call _Z14loadMatrixFilePcPiii
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z11printMatrixPiii
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L38:
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r14, %rdi
call _Z11printMatrixPiii
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %ebx, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
jmp .L38
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9MatrixMulPcS_S_i, .-_Z9MatrixMulPcS_S_i
.section .rodata.str1.8
.align 8
.LC8:
.string "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n"
.align 8
.LC9:
.string "\nYou have entered files %s, %s, and %s and square matrix width %d \n"
.align 8
.LC10:
.string "\n could not open one of the following files: %s %s \n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
cmpl $5, %edi
je .L44
movq (%rsi), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L45:
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 8(%rsi), %r12
movq 16(%rsi), %r13
movq 24(%rsi), %r14
movq 32(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r9
movl %eax, 12(%rsp)
movq %r14, %r8
movq %r12, %rcx
movq %r13, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %r15
movq %r15, %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %rbp
movq %r15, %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, (%rsp)
movq %r15, %rsi
movq %r14, %rdi
call fopen@PLT
movq %rax, %r15
movq (%rsp), %rax
orq %rbp, %rax
orq %r15, %rax
je .L49
movl 12(%rsp), %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z9MatrixMulPcS_S_i
.L47:
movq %rbp, %rdi
call fclose@PLT
movq (%rsp), %rdi
call fclose@PLT
movq %r15, %rdi
call fclose@PLT
jmp .L45
.L49:
movq 16(%rbx), %rcx
movq 8(%rbx), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z15MatrixMulKernelPiS_S_i"
.LC12:
.string "_Z15MatrixAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixAddKernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//#include <cuda.h>
//#include "cuda_runtime_api.h"
//#include <stdint.h>
//#include <stdlib.h>
//This is the working matrix multiplication code - very basic
/*
Done:
- printing of matrix in a more pleasant manner using printMatrix function
- command line arguments
- opens matrix files and reads the matrix successfully
- working array passing from main to auxiliary (loadMatrixFile) function :)
- fixed printing of matrix
- fixed erroneous matrix values by moving loading into host matrix multiplication function!
Problems:
- (fixed) MatA and MatB values are overlapping and erroneous
*/
// START of AUXILIARY functions
//START vector addition kernel function
__global__ void MatrixAddKernel ( int *Md, int *Nd, int *Pd, int N ){
int tid = blockIdx.x; //thred id
if ( tid < N )
Pd[ tid ] = Md[ tid ] + Nd[ tid ];
/* int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue = Mdelement + Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue; */
}
//END of kernel addition
//Start of kernel multiplication
__global__ void MatrixMulKernel ( int *Md, int *Nd, int *Pd, int Width ){
int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue += Mdelement * Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue;
}
//End of kernel multiplication
//function to print matrix
void printMatrix ( int *M, int rows, int columns ){
//assumes matrix is in row-major format
int index;
printf ( "\n \n " );
for ( int v = 0; v < rows; v++ ){
//assumes a square matrix
for ( int w = 0; w < columns; w++ ) {
index = v * columns + w;
printf ( " %02d", M[ index ] );
}
printf ( " \n\n " );
}
}//End of printMatrix function
//START of loadMatrixFile
void loadMatrixFile( char *filename, int *z, int matWidth, int matHeight ){
int y = 0;
int w = 0;
int x;
int offset = 0;
FILE *ptr1 = fopen( filename, "r" );
// int *z = ( int * )malloc( sizeof( ( matWidth * matHeight ) ) );
//int z[ ( matWidth * matHeight ) + offset ] ;
fscanf( ptr1, " %d", &x );
while( !feof( ptr1 ) && y < ( matWidth * matHeight ) + 1 ){
if ( y > offset ){
fscanf( ptr1, " %d", &z[ w - offset ] );
//printf( " B: z[ %d ]: %d \n", w, z[ w - offset ] );
w++;
}
else{
fscanf( ptr1, " %d", &x );
}
y++;
}
fclose( ptr1 );
// x = y = w = 0;
// array = &z[ 0 ];
// free( z );
}
//END of loadMatrixFile
//Start of matrix multiplication host function MatrixMul
void MatrixMul( char *filename0, char *filename1, char *filename2, int Width /*, int *M, int *N, int *P, int Width*/ ){
int size = Width * Width * sizeof( int );
int *Md, *Nd, *Pd;
dim3 dimBlock( Width, Width );
dim3 dimGrid( 1, 1 );
int *matA = ( int * )malloc( size );
//printf( "Width and height of Matrix A: %d %d and init values are\n", Width, Width );
//printMatrix( matA, Width, Width );
loadMatrixFile( filename1, matA, Width, Width );
printf( " \ns after loading from file: \n" );
printMatrix( matA, Width, Width );
int *matB = ( int * )malloc( size );
loadMatrixFile( filename2, matB, Width, Width );
printf( " \nM after loading from file: \n" );
printMatrix( matB, Width, Width );
//assumes a square matrix
int *matC = ( int * )malloc( size );
cudaMalloc( (void**) &Md, size );
cudaMemcpy( Md, matA, size, cudaMemcpyHostToDevice );
cudaMalloc( (void**) &Nd, size );
cudaMemcpy( Nd, matB, size, cudaMemcpyHostToDevice );
cudaMalloc( (void**) &Pd, size );
MatrixMulKernel<<< dimGrid, dimBlock >>>( Md, Nd, Pd, Width );
//MatrixAddKernel<<< N, 1 >>>( Md, Nd, Pd );
cudaMemcpy( matC, Pd, size, cudaMemcpyDeviceToHost );
printf( " \ns * M: \n" );
printMatrix( matC, Width, Width );
free( matA ); free( matB ); free( matC );
cudaFree( Md ); cudaFree( Nd ); cudaFree ( Pd );
}
//End of Matrix multiplication function MatrixMul
//END of AUXILIARY functions
//START of MAIN function
int main ( int argc, char *argv[ ] ) {
int offset = 2;
if ( argc != 5 ) {
printf( "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n", argv [ 0 ] );
}
else {
char *confVec = argv[ 1 ];
char *spikVec = argv[ 2 ];
char *spikTransMat = argv[ 3 ];
int width = atoi( argv[ 4 ] );
printf( "\nYou have entered files %s, %s, and %s and square matrix width %d \n", spikVec, confVec, spikTransMat, width );
//load matrices from files
FILE *ptr1 = fopen( confVec, "r" );
FILE *ptr2 = fopen( spikVec, "r" );
FILE *ptr3 = fopen( spikTransMat, "r" );
if ( ptr1 == 0 && ptr2 == 0 && ptr3 == 0 )
printf( "\n could not open one of the following files: %s %s \n", argv[ 1 ], argv[ 2 ] );
else {
MatrixMul( confVec, spikVec, spikTransMat, width );
}
fclose( ptr1 ); fclose( ptr2 ); fclose( ptr3 );
}
}
//END of MAIN function | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <cuda.h>
//#include "cuda_runtime_api.h"
//#include <stdint.h>
//#include <stdlib.h>
//This is the working matrix multiplication code - very basic
/*
Done:
- printing of matrix in a more pleasant manner using printMatrix function
- command line arguments
- opens matrix files and reads the matrix successfully
- working array passing from main to auxiliary (loadMatrixFile) function :)
- fixed printing of matrix
- fixed erroneous matrix values by moving loading into host matrix multiplication function!
Problems:
- (fixed) MatA and MatB values are overlapping and erroneous
*/
// START of AUXILIARY functions
//START vector addition kernel function
__global__ void MatrixAddKernel ( int *Md, int *Nd, int *Pd, int N ){
int tid = blockIdx.x; //thred id
if ( tid < N )
Pd[ tid ] = Md[ tid ] + Nd[ tid ];
/* int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue = Mdelement + Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue; */
}
//END of kernel addition
//Start of kernel multiplication
__global__ void MatrixMulKernel ( int *Md, int *Nd, int *Pd, int Width ){
int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue += Mdelement * Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue;
}
//End of kernel multiplication
//function to print matrix
void printMatrix ( int *M, int rows, int columns ){
//assumes matrix is in row-major format
int index;
printf ( "\n \n " );
for ( int v = 0; v < rows; v++ ){
//assumes a square matrix
for ( int w = 0; w < columns; w++ ) {
index = v * columns + w;
printf ( " %02d", M[ index ] );
}
printf ( " \n\n " );
}
}//End of printMatrix function
//START of loadMatrixFile
void loadMatrixFile( char *filename, int *z, int matWidth, int matHeight ){
int y = 0;
int w = 0;
int x;
int offset = 0;
FILE *ptr1 = fopen( filename, "r" );
// int *z = ( int * )malloc( sizeof( ( matWidth * matHeight ) ) );
//int z[ ( matWidth * matHeight ) + offset ] ;
fscanf( ptr1, " %d", &x );
while( !feof( ptr1 ) && y < ( matWidth * matHeight ) + 1 ){
if ( y > offset ){
fscanf( ptr1, " %d", &z[ w - offset ] );
//printf( " B: z[ %d ]: %d \n", w, z[ w - offset ] );
w++;
}
else{
fscanf( ptr1, " %d", &x );
}
y++;
}
fclose( ptr1 );
// x = y = w = 0;
// array = &z[ 0 ];
// free( z );
}
//END of loadMatrixFile
//Start of matrix multiplication host function MatrixMul
void MatrixMul( char *filename0, char *filename1, char *filename2, int Width /*, int *M, int *N, int *P, int Width*/ ){
int size = Width * Width * sizeof( int );
int *Md, *Nd, *Pd;
dim3 dimBlock( Width, Width );
dim3 dimGrid( 1, 1 );
int *matA = ( int * )malloc( size );
//printf( "Width and height of Matrix A: %d %d and init values are\n", Width, Width );
//printMatrix( matA, Width, Width );
loadMatrixFile( filename1, matA, Width, Width );
printf( " \ns after loading from file: \n" );
printMatrix( matA, Width, Width );
int *matB = ( int * )malloc( size );
loadMatrixFile( filename2, matB, Width, Width );
printf( " \nM after loading from file: \n" );
printMatrix( matB, Width, Width );
//assumes a square matrix
int *matC = ( int * )malloc( size );
hipMalloc( (void**) &Md, size );
hipMemcpy( Md, matA, size, hipMemcpyHostToDevice );
hipMalloc( (void**) &Nd, size );
hipMemcpy( Nd, matB, size, hipMemcpyHostToDevice );
hipMalloc( (void**) &Pd, size );
MatrixMulKernel<<< dimGrid, dimBlock >>>( Md, Nd, Pd, Width );
//MatrixAddKernel<<< N, 1 >>>( Md, Nd, Pd );
hipMemcpy( matC, Pd, size, hipMemcpyDeviceToHost );
printf( " \ns * M: \n" );
printMatrix( matC, Width, Width );
free( matA ); free( matB ); free( matC );
hipFree( Md ); hipFree( Nd ); hipFree ( Pd );
}
//End of Matrix multiplication function MatrixMul
//END of AUXILIARY functions
//START of MAIN function
int main ( int argc, char *argv[ ] ) {
int offset = 2;
if ( argc != 5 ) {
printf( "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n", argv [ 0 ] );
}
else {
char *confVec = argv[ 1 ];
char *spikVec = argv[ 2 ];
char *spikTransMat = argv[ 3 ];
int width = atoi( argv[ 4 ] );
printf( "\nYou have entered files %s, %s, and %s and square matrix width %d \n", spikVec, confVec, spikTransMat, width );
//load matrices from files
FILE *ptr1 = fopen( confVec, "r" );
FILE *ptr2 = fopen( spikVec, "r" );
FILE *ptr3 = fopen( spikTransMat, "r" );
if ( ptr1 == 0 && ptr2 == 0 && ptr3 == 0 )
printf( "\n could not open one of the following files: %s %s \n", argv[ 1 ], argv[ 2 ] );
else {
MatrixMul( confVec, spikVec, spikTransMat, width );
}
fclose( ptr1 ); fclose( ptr2 ); fclose( ptr3 );
}
}
//END of MAIN function |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <cuda.h>
//#include "cuda_runtime_api.h"
//#include <stdint.h>
//#include <stdlib.h>
//This is the working matrix multiplication code - very basic
/*
Done:
- printing of matrix in a more pleasant manner using printMatrix function
- command line arguments
- opens matrix files and reads the matrix successfully
- working array passing from main to auxiliary (loadMatrixFile) function :)
- fixed printing of matrix
- fixed erroneous matrix values by moving loading into host matrix multiplication function!
Problems:
- (fixed) MatA and MatB values are overlapping and erroneous
*/
// START of AUXILIARY functions
//START vector addition kernel function
__global__ void MatrixAddKernel ( int *Md, int *Nd, int *Pd, int N ){
int tid = blockIdx.x; //thred id
if ( tid < N )
Pd[ tid ] = Md[ tid ] + Nd[ tid ];
/* int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue = Mdelement + Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue; */
}
//END of kernel addition
//Start of kernel multiplication
__global__ void MatrixMulKernel ( int *Md, int *Nd, int *Pd, int Width ){
int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue += Mdelement * Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue;
}
//End of kernel multiplication
//function to print matrix
void printMatrix ( int *M, int rows, int columns ){
//assumes matrix is in row-major format
int index;
printf ( "\n \n " );
for ( int v = 0; v < rows; v++ ){
//assumes a square matrix
for ( int w = 0; w < columns; w++ ) {
index = v * columns + w;
printf ( " %02d", M[ index ] );
}
printf ( " \n\n " );
}
}//End of printMatrix function
//START of loadMatrixFile
void loadMatrixFile( char *filename, int *z, int matWidth, int matHeight ){
int y = 0;
int w = 0;
int x;
int offset = 0;
FILE *ptr1 = fopen( filename, "r" );
// int *z = ( int * )malloc( sizeof( ( matWidth * matHeight ) ) );
//int z[ ( matWidth * matHeight ) + offset ] ;
fscanf( ptr1, " %d", &x );
while( !feof( ptr1 ) && y < ( matWidth * matHeight ) + 1 ){
if ( y > offset ){
fscanf( ptr1, " %d", &z[ w - offset ] );
//printf( " B: z[ %d ]: %d \n", w, z[ w - offset ] );
w++;
}
else{
fscanf( ptr1, " %d", &x );
}
y++;
}
fclose( ptr1 );
// x = y = w = 0;
// array = &z[ 0 ];
// free( z );
}
//END of loadMatrixFile
//Start of matrix multiplication host function MatrixMul
void MatrixMul( char *filename0, char *filename1, char *filename2, int Width /*, int *M, int *N, int *P, int Width*/ ){
int size = Width * Width * sizeof( int );
int *Md, *Nd, *Pd;
dim3 dimBlock( Width, Width );
dim3 dimGrid( 1, 1 );
int *matA = ( int * )malloc( size );
//printf( "Width and height of Matrix A: %d %d and init values are\n", Width, Width );
//printMatrix( matA, Width, Width );
loadMatrixFile( filename1, matA, Width, Width );
printf( " \ns after loading from file: \n" );
printMatrix( matA, Width, Width );
int *matB = ( int * )malloc( size );
loadMatrixFile( filename2, matB, Width, Width );
printf( " \nM after loading from file: \n" );
printMatrix( matB, Width, Width );
//assumes a square matrix
int *matC = ( int * )malloc( size );
hipMalloc( (void**) &Md, size );
hipMemcpy( Md, matA, size, hipMemcpyHostToDevice );
hipMalloc( (void**) &Nd, size );
hipMemcpy( Nd, matB, size, hipMemcpyHostToDevice );
hipMalloc( (void**) &Pd, size );
MatrixMulKernel<<< dimGrid, dimBlock >>>( Md, Nd, Pd, Width );
//MatrixAddKernel<<< N, 1 >>>( Md, Nd, Pd );
hipMemcpy( matC, Pd, size, hipMemcpyDeviceToHost );
printf( " \ns * M: \n" );
printMatrix( matC, Width, Width );
free( matA ); free( matB ); free( matC );
hipFree( Md ); hipFree( Nd ); hipFree ( Pd );
}
//End of Matrix multiplication function MatrixMul
//END of AUXILIARY functions
//START of MAIN function
int main ( int argc, char *argv[ ] ) {
int offset = 2;
if ( argc != 5 ) {
printf( "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n", argv [ 0 ] );
}
else {
char *confVec = argv[ 1 ];
char *spikVec = argv[ 2 ];
char *spikTransMat = argv[ 3 ];
int width = atoi( argv[ 4 ] );
printf( "\nYou have entered files %s, %s, and %s and square matrix width %d \n", spikVec, confVec, spikTransMat, width );
//load matrices from files
FILE *ptr1 = fopen( confVec, "r" );
FILE *ptr2 = fopen( spikVec, "r" );
FILE *ptr3 = fopen( spikTransMat, "r" );
if ( ptr1 == 0 && ptr2 == 0 && ptr3 == 0 )
printf( "\n could not open one of the following files: %s %s \n", argv[ 1 ], argv[ 2 ] );
else {
MatrixMul( confVec, spikVec, spikTransMat, width );
}
fclose( ptr1 ); fclose( ptr2 ); fclose( ptr3 );
}
}
//END of MAIN function | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixAddKernelPiS_S_i
.globl _Z15MatrixAddKernelPiS_S_i
.p2align 8
.type _Z15MatrixAddKernelPiS_S_i,@function
_Z15MatrixAddKernelPiS_S_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixAddKernelPiS_S_i, .Lfunc_end0-_Z15MatrixAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15MatrixMulKernelPiS_S_i
.globl _Z15MatrixMulKernelPiS_S_i
.p2align 8
.type _Z15MatrixMulKernelPiS_S_i,@function
_Z15MatrixMulKernelPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v6, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v6, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v0, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB1_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v7
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
v_mov_b32_e32 v0, 0
.LBB1_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v6, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15MatrixMulKernelPiS_S_i, .Lfunc_end1-_Z15MatrixMulKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15MatrixAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <cuda.h>
//#include "cuda_runtime_api.h"
//#include <stdint.h>
//#include <stdlib.h>
//This is the working matrix multiplication code - very basic
/*
Done:
- printing of matrix in a more pleasant manner using printMatrix function
- command line arguments
- opens matrix files and reads the matrix successfully
- working array passing from main to auxiliary (loadMatrixFile) function :)
- fixed printing of matrix
- fixed erroneous matrix values by moving loading into host matrix multiplication function!
Problems:
- (fixed) MatA and MatB values are overlapping and erroneous
*/
// START of AUXILIARY functions
//START vector addition kernel function
__global__ void MatrixAddKernel ( int *Md, int *Nd, int *Pd, int N ){
int tid = blockIdx.x; //thred id
if ( tid < N )
Pd[ tid ] = Md[ tid ] + Nd[ tid ];
/* int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue = Mdelement + Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue; */
}
//END of kernel addition
//Start of kernel multiplication
__global__ void MatrixMulKernel ( int *Md, int *Nd, int *Pd, int Width ){
int tx = threadIdx.x;
int ty = threadIdx.y;
int Pvalue = 0;
for ( int k = 0; k < Width; ++k ){
int Mdelement = Md[ ty * Width + k ];
int Ndelement = Nd[ k * Width + tx ];
Pvalue += Mdelement * Ndelement;
}
Pd[ ty * Width + tx ] = Pvalue;
}
//End of kernel multiplication
//function to print matrix
void printMatrix ( int *M, int rows, int columns ){
//assumes matrix is in row-major format
int index;
printf ( "\n \n " );
for ( int v = 0; v < rows; v++ ){
//assumes a square matrix
for ( int w = 0; w < columns; w++ ) {
index = v * columns + w;
printf ( " %02d", M[ index ] );
}
printf ( " \n\n " );
}
}//End of printMatrix function
//START of loadMatrixFile
void loadMatrixFile( char *filename, int *z, int matWidth, int matHeight ){
int y = 0;
int w = 0;
int x;
int offset = 0;
FILE *ptr1 = fopen( filename, "r" );
// int *z = ( int * )malloc( sizeof( ( matWidth * matHeight ) ) );
//int z[ ( matWidth * matHeight ) + offset ] ;
fscanf( ptr1, " %d", &x );
while( !feof( ptr1 ) && y < ( matWidth * matHeight ) + 1 ){
if ( y > offset ){
fscanf( ptr1, " %d", &z[ w - offset ] );
//printf( " B: z[ %d ]: %d \n", w, z[ w - offset ] );
w++;
}
else{
fscanf( ptr1, " %d", &x );
}
y++;
}
fclose( ptr1 );
// x = y = w = 0;
// array = &z[ 0 ];
// free( z );
}
//END of loadMatrixFile
//Start of matrix multiplication host function MatrixMul
void MatrixMul( char *filename0, char *filename1, char *filename2, int Width /*, int *M, int *N, int *P, int Width*/ ){
int size = Width * Width * sizeof( int );
int *Md, *Nd, *Pd;
dim3 dimBlock( Width, Width );
dim3 dimGrid( 1, 1 );
int *matA = ( int * )malloc( size );
//printf( "Width and height of Matrix A: %d %d and init values are\n", Width, Width );
//printMatrix( matA, Width, Width );
loadMatrixFile( filename1, matA, Width, Width );
printf( " \ns after loading from file: \n" );
printMatrix( matA, Width, Width );
int *matB = ( int * )malloc( size );
loadMatrixFile( filename2, matB, Width, Width );
printf( " \nM after loading from file: \n" );
printMatrix( matB, Width, Width );
//assumes a square matrix
int *matC = ( int * )malloc( size );
hipMalloc( (void**) &Md, size );
hipMemcpy( Md, matA, size, hipMemcpyHostToDevice );
hipMalloc( (void**) &Nd, size );
hipMemcpy( Nd, matB, size, hipMemcpyHostToDevice );
hipMalloc( (void**) &Pd, size );
MatrixMulKernel<<< dimGrid, dimBlock >>>( Md, Nd, Pd, Width );
//MatrixAddKernel<<< N, 1 >>>( Md, Nd, Pd );
hipMemcpy( matC, Pd, size, hipMemcpyDeviceToHost );
printf( " \ns * M: \n" );
printMatrix( matC, Width, Width );
free( matA ); free( matB ); free( matC );
hipFree( Md ); hipFree( Nd ); hipFree ( Pd );
}
//End of Matrix multiplication function MatrixMul
//END of AUXILIARY functions
//START of MAIN function
int main ( int argc, char *argv[ ] ) {
int offset = 2;
if ( argc != 5 ) {
printf( "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n", argv [ 0 ] );
}
else {
char *confVec = argv[ 1 ];
char *spikVec = argv[ 2 ];
char *spikTransMat = argv[ 3 ];
int width = atoi( argv[ 4 ] );
printf( "\nYou have entered files %s, %s, and %s and square matrix width %d \n", spikVec, confVec, spikTransMat, width );
//load matrices from files
FILE *ptr1 = fopen( confVec, "r" );
FILE *ptr2 = fopen( spikVec, "r" );
FILE *ptr3 = fopen( spikTransMat, "r" );
if ( ptr1 == 0 && ptr2 == 0 && ptr3 == 0 )
printf( "\n could not open one of the following files: %s %s \n", argv[ 1 ], argv[ 2 ] );
else {
MatrixMul( confVec, spikVec, spikTransMat, width );
}
fclose( ptr1 ); fclose( ptr2 ); fclose( ptr3 );
}
}
//END of MAIN function | .text
.file "mulMatrix-v1-test.hip"
.globl _Z30__device_stub__MatrixAddKernelPiS_S_i # -- Begin function _Z30__device_stub__MatrixAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixAddKernelPiS_S_i,@function
_Z30__device_stub__MatrixAddKernelPiS_S_i: # @_Z30__device_stub__MatrixAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixAddKernelPiS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__MatrixMulKernelPiS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPiS_S_i,@function
_Z30__device_stub__MatrixMulKernelPiS_S_i: # @_Z30__device_stub__MatrixMulKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__MatrixMulKernelPiS_S_i, .Lfunc_end1-_Z30__device_stub__MatrixMulKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z11printMatrixPiii # -- Begin function _Z11printMatrixPiii
.p2align 4, 0x90
.type _Z11printMatrixPiii,@function
_Z11printMatrixPiii: # @_Z11printMatrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, 8(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge14
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11printMatrixPiii, .Lfunc_end2-_Z11printMatrixPiii
.cfi_endproc
# -- End function
.globl _Z14loadMatrixFilePcPiii # -- Begin function _Z14loadMatrixFilePcPiii
.p2align 4, 0x90
.type _Z14loadMatrixFilePcPiii,@function
_Z14loadMatrixFilePcPiii: # @_Z14loadMatrixFilePcPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movl $.L.str.3, %esi
callq fopen
movq %rax, %r15
leaq 4(%rsp), %rdx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movq %r15, %rdi
callq feof
testl %eax, %eax
jne .LBB3_8
# %bb.1:
imull %ebp, %ebx
testl %ebx, %ebx
js .LBB3_8
# %bb.2: # %.lr.ph.preheader
leaq 4(%rsp), %r12
xorl %ebp, %ebp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testl %ebp, %ebp
je .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movslq %r13d, %r13
leaq (%r14,%r13,4), %rdx
movl $.L.str.4, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
incl %r13d
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
movl $.L.str.4, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
.LBB3_6: # in Loop: Header=BB3_3 Depth=1
movq %r15, %rdi
callq feof
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_3 Depth=1
leal 1(%rbp), %eax
cmpl %ebx, %ebp
movl %eax, %ebp
jl .LBB3_3
.LBB3_8: # %.critedge
movq %r15, %rdi
callq fclose
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14loadMatrixFilePcPiii, .Lfunc_end3-_Z14loadMatrixFilePcPiii
.cfi_endproc
# -- End function
.globl _Z9MatrixMulPcS_S_i # -- Begin function _Z9MatrixMulPcS_S_i
.p2align 4, 0x90
.type _Z9MatrixMulPcS_S_i,@function
_Z9MatrixMulPcS_S_i: # @_Z9MatrixMulPcS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rsi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movl %ecx, %r13d
movq %r13, %rcx
shlq $32, %rcx
movq %rcx, 64(%rsp) # 8-byte Spill
movslq %eax, %rdi
movq %rdi, 16(%rsp) # 8-byte Spill
callq malloc
movq %r12, %rdi
movq %rax, 24(%rsp) # 8-byte Spill
movq %rax, %rsi
movl %ebx, %edx
movl %ebx, %ecx
callq _Z14loadMatrixFilePcPiii
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB4_5
# %bb.1: # %.preheader.i.preheader
xorl %r12d, %r12d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %r12d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r13
jne .LBB4_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB4_2 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbp
addl %ebx, %r12d
cmpq %r13, %rbp
jne .LBB4_2
.LBB4_5: # %_Z11printMatrixPiii.exit
addq %r13, 64(%rsp) # 8-byte Folded Spill
movq 16(%rsp), %rdi # 8-byte Reload
callq malloc
movq 8(%rsp), %rdi # 8-byte Reload
movq %rax, 8(%rsp) # 8-byte Spill
movq %rax, %rsi
movl %ebx, %edx
movl %ebx, %ecx
callq _Z14loadMatrixFilePcPiii
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB4_10
# %bb.6: # %.preheader.i46.preheader
xorl %ebp, %ebp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_7: # %.preheader.i46
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_8: # Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB4_8
# %bb.9: # %._crit_edge.i48
# in Loop: Header=BB4_7 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r15
addl %ebx, %ebp
cmpq %r13, %r15
jne .LBB4_7
.LBB4_10: # %_Z11printMatrixPiii.exit55
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq malloc
movq %rax, %r12
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq 64(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %ebx, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 32(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl %ebx, 16(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB4_17
# %bb.13: # %.preheader.i58.preheader
xorl %r15d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_14: # %.preheader.i58
# =>This Loop Header: Depth=1
# Child Loop BB4_15 Depth 2
movl %r15d, %eax
movq %r12, %rbx
leaq (%r12,%rax,4), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_15: # Parent Loop BB4_14 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r13
jne .LBB4_15
# %bb.16: # %._crit_edge.i60
# in Loop: Header=BB4_14 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
addl 16(%rsp), %r15d # 4-byte Folded Reload
cmpq %r13, %r14
movq %rbx, %r12
jne .LBB4_14
.LBB4_17: # %_Z11printMatrixPiii.exit67
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9MatrixMulPcS_S_i, .Lfunc_end4-_Z9MatrixMulPcS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB5_1
# %bb.2:
movq 8(%rsi), %r12
movq 16(%rsi), %rbx
movq 24(%rsi), %r14
movq %rsi, (%rsp) # 8-byte Spill
movq 32(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $.L.str.9, %edi
movq %rbx, %rsi
movq %r12, %rdx
movq %r14, %rcx
movl %r15d, %r8d
xorl %eax, %eax
callq printf
movl $.L.str.3, %esi
movq %r12, %rdi
callq fopen
movq %rax, %r12
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r13
movl $.L.str.3, %esi
movq %r14, %rdi
callq fopen
movq %rax, %rbp
testq %r12, %r12
jne .LBB5_6
# %bb.3:
testq %r13, %r13
jne .LBB5_6
# %bb.4:
testq %rbp, %rbp
jne .LBB5_6
# %bb.5:
movq (%rsp), %rax # 8-byte Reload
movq 8(%rax), %rsi
movq 16(%rax), %rdx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_7
.LBB5_1:
movq (%rsi), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_8
.LBB5_6:
movq %rbx, %rsi
movq %r14, %rdx
movl %r15d, %ecx
callq _Z9MatrixMulPcS_S_i
.LBB5_7:
movq %r12, %rdi
callq fclose
movq %r13, %rdi
callq fclose
movq %rbp, %rdi
callq fclose
.LBB5_8:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixAddKernelPiS_S_i,@object # @_Z15MatrixAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixAddKernelPiS_S_i
.p2align 3, 0x0
_Z15MatrixAddKernelPiS_S_i:
.quad _Z30__device_stub__MatrixAddKernelPiS_S_i
.size _Z15MatrixAddKernelPiS_S_i, 8
.type _Z15MatrixMulKernelPiS_S_i,@object # @_Z15MatrixMulKernelPiS_S_i
.globl _Z15MatrixMulKernelPiS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPiS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPiS_S_i
.size _Z15MatrixMulKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n \n "
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " %02d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " \n\n "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " %d"
.size .L.str.4, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n"
.size .L.str.8, 89
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nYou have entered files %s, %s, and %s and square matrix width %d \n"
.size .L.str.9, 68
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n could not open one of the following files: %s %s \n"
.size .L.str.10, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixAddKernelPiS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15MatrixMulKernelPiS_S_i"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " \ns after loading from file: "
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " \nM after loading from file: "
.size .Lstr.1, 30
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " \ns * M: "
.size .Lstr.2, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixAddKernelPiS_S_i
.addrsig_sym _Z30__device_stub__MatrixMulKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixAddKernelPiS_S_i
.addrsig_sym _Z15MatrixMulKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xba0 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa80 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe40000000f00 */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*0140*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fce00078e0219 */
/*0150*/ @!P0 BRA 0x8f0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0160*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0180*/ @!P1 BRA 0x630 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01a0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01b0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01c0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01d0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01e0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0200*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0210*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0220*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0230*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0240*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0250*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0260*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0270*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0280*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02a0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02b0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02d0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02e0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*02f0*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0300*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0310*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0320*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*0330*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0350*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0360*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*0370*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0380*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0390*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*03a0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03b0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03c0*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*03d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03e0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0410*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0420*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*0430*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0440*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*0450*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0460*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0470*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0480*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0490*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04a0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04b0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04c0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04d0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04e0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*04f0*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0500*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0510*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0530*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0560*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*0570*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*0580*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0590*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*05a0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05b0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05d0*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*05e0*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*05f0*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0600*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0610*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0620*/ @P1 BRA 0x1a0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0630*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0640*/ @!P1 BRA 0x8d0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0660*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0670*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0680*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0690*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06a0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06b0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06c0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06d0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06e0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*06f0*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0700*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0710*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0720*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0730*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0740*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0750*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0760*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0770*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0780*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0790*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07a0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07c0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07d0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*07f0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0800*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0810*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0820*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0830*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0840*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*0850*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*0860*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*0870*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*0880*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0890*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*08a0*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*08b0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08c0*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*08d0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08e0*/ @!P0 BRA 0xa80 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*08f0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0900*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0910*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0920*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0930*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0940*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0950*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0970*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0980*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0990*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09a0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09c0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09d0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*09f0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a00*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a10*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a20*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0a30*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0a40*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a50*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0a60*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0a70*/ @P0 BRA 0x8f0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a80*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0a90*/ @!P0 BRA 0xba0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ab0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ad0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0ae0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0af0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b00*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b10*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b20*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b30*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b50*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b60*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b70*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b80*/ IMAD R28, R3, R6, R28 ; /* 0x00000006031c7224 */
/* 0x004fd000078e021c */
/*0b90*/ @P0 BRA 0xb00 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0ba0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bb0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bc0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bd0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0be0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bf0*/ BRA 0xbf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15MatrixAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixAddKernelPiS_S_i
.globl _Z15MatrixAddKernelPiS_S_i
.p2align 8
.type _Z15MatrixAddKernelPiS_S_i,@function
_Z15MatrixAddKernelPiS_S_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixAddKernelPiS_S_i, .Lfunc_end0-_Z15MatrixAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15MatrixMulKernelPiS_S_i
.globl _Z15MatrixMulKernelPiS_S_i
.p2align 8
.type _Z15MatrixMulKernelPiS_S_i,@function
_Z15MatrixMulKernelPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v6, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v6, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v0, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB1_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v7
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
v_mov_b32_e32 v0, 0
.LBB1_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v6, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15MatrixMulKernelPiS_S_i, .Lfunc_end1-_Z15MatrixMulKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15MatrixAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007d02d_00000000-6_mulMatrix-v1-test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n \n "
.LC1:
.string " %02d"
.LC2:
.string " \n\n "
.text
.globl _Z11printMatrixPiii
.type _Z11printMatrixPiii, @function
_Z11printMatrixPiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, %ebx
movl %esi, 12(%rsp)
movl %edx, %r15d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L3
movl $0, %r14d
movl $0, %r13d
movslq %r15d, %rax
movq %rax, 24(%rsp)
leaq .LC1(%rip), %r12
jmp .L5
.L7:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdi
addq %rdi, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L3
.L5:
testl %r15d, %r15d
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPiii, .-_Z11printMatrixPiii
.section .rodata.str1.1
.LC3:
.string "r"
.LC4:
.string " %d"
.text
.globl _Z14loadMatrixFilePcPiii
.type _Z14loadMatrixFilePcPiii, @function
_Z14loadMatrixFilePcPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r15
movl %edx, %r13d
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
leaq 4(%rsp), %rdx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
imull %ebx, %r13d
movl $0, %r12d
movl $0, %ebx
leaq .LC4(%rip), %r14
jmp .L12
.L15:
movslq %r12d, %rax
leaq (%r15,%rax,4), %rdx
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %r12d
.L13:
addl $1, %ebx
.L12:
movq %rbp, %rdi
call feof@PLT
testl %eax, %eax
jne .L14
cmpl %ebx, %r13d
jl .L14
testl %ebx, %ebx
jg .L15
leaq 4(%rsp), %rdx
movq %r14, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
jmp .L13
.L14:
movq %rbp, %rdi
call fclose@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z14loadMatrixFilePcPiii, .-_Z14loadMatrixFilePcPiii
.globl _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i
.globl _Z15MatrixAddKernelPiS_S_i
.type _Z15MatrixAddKernelPiS_S_i, @function
_Z15MatrixAddKernelPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z15MatrixAddKernelPiS_S_i, .-_Z15MatrixAddKernelPiS_S_i
.globl _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
.type _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i, @function
_Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixMulKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i, .-_Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
.globl _Z15MatrixMulKernelPiS_S_i
.type _Z15MatrixMulKernelPiS_S_i, @function
_Z15MatrixMulKernelPiS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z15MatrixMulKernelPiS_S_i, .-_Z15MatrixMulKernelPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string " \ns after loading from file: \n"
.align 8
.LC6:
.string " \nM after loading from file: \n"
.section .rodata.str1.1
.LC7:
.string " \ns * M: \n"
.text
.globl _Z9MatrixMulPcS_S_i
.type _Z9MatrixMulPcS_S_i, @function
_Z9MatrixMulPcS_S_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r12
movq %rdx, %r14
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %ecx, 32(%rsp)
movl %ecx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ecx, %ebp
imull %ecx, %ebp
sall $2, %ebp
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %ecx
movl %ebx, %edx
movq %rax, %rsi
movq %r12, %rdi
call _Z14loadMatrixFilePcPiii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r13, %rdi
call _Z11printMatrixPiii
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %ebx, %ecx
movl %ebx, %edx
movq %rax, %rsi
movq %r14, %rdi
call _Z14loadMatrixFilePcPiii
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z11printMatrixPiii
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L38:
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
movl %ebx, %esi
movq %r14, %rdi
call _Z11printMatrixPiii
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movl %ebx, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z15MatrixMulKernelPiS_S_iPiS_S_i
jmp .L38
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z9MatrixMulPcS_S_i, .-_Z9MatrixMulPcS_S_i
.section .rodata.str1.8
.align 8
.LC8:
.string "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n"
.align 8
.LC9:
.string "\nYou have entered files %s, %s, and %s and square matrix width %d \n"
.align 8
.LC10:
.string "\n could not open one of the following files: %s %s \n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
cmpl $5, %edi
je .L44
movq (%rsi), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L45:
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movq 8(%rsi), %r12
movq 16(%rsi), %r13
movq 24(%rsi), %r14
movq 32(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r9
movl %eax, 12(%rsp)
movq %r14, %r8
movq %r12, %rcx
movq %r13, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %r15
movq %r15, %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, %rbp
movq %r15, %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, (%rsp)
movq %r15, %rsi
movq %r14, %rdi
call fopen@PLT
movq %rax, %r15
movq (%rsp), %rax
orq %rbp, %rax
orq %r15, %rax
je .L49
movl 12(%rsp), %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z9MatrixMulPcS_S_i
.L47:
movq %rbp, %rdi
call fclose@PLT
movq (%rsp), %rdi
call fclose@PLT
movq %r15, %rdi
call fclose@PLT
jmp .L45
.L49:
movq 16(%rbx), %rcx
movq 8(%rbx), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z15MatrixMulKernelPiS_S_i"
.LC12:
.string "_Z15MatrixAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPiS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixAddKernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mulMatrix-v1-test.hip"
.globl _Z30__device_stub__MatrixAddKernelPiS_S_i # -- Begin function _Z30__device_stub__MatrixAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixAddKernelPiS_S_i,@function
_Z30__device_stub__MatrixAddKernelPiS_S_i: # @_Z30__device_stub__MatrixAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixAddKernelPiS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__MatrixMulKernelPiS_S_i # -- Begin function _Z30__device_stub__MatrixMulKernelPiS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPiS_S_i,@function
_Z30__device_stub__MatrixMulKernelPiS_S_i: # @_Z30__device_stub__MatrixMulKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__MatrixMulKernelPiS_S_i, .Lfunc_end1-_Z30__device_stub__MatrixMulKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z11printMatrixPiii # -- Begin function _Z11printMatrixPiii
.p2align 4, 0x90
.type _Z11printMatrixPiii,@function
_Z11printMatrixPiii: # @_Z11printMatrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, 8(%rsp) # 8-byte Spill
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %r12d
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r13
addl %ebx, %ebp
cmpq 16(%rsp), %r13 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge14
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11printMatrixPiii, .Lfunc_end2-_Z11printMatrixPiii
.cfi_endproc
# -- End function
.globl _Z14loadMatrixFilePcPiii # -- Begin function _Z14loadMatrixFilePcPiii
.p2align 4, 0x90
.type _Z14loadMatrixFilePcPiii,@function
_Z14loadMatrixFilePcPiii: # @_Z14loadMatrixFilePcPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movl $.L.str.3, %esi
callq fopen
movq %rax, %r15
leaq 4(%rsp), %rdx
movl $.L.str.4, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movq %r15, %rdi
callq feof
testl %eax, %eax
jne .LBB3_8
# %bb.1:
imull %ebp, %ebx
testl %ebx, %ebx
js .LBB3_8
# %bb.2: # %.lr.ph.preheader
leaq 4(%rsp), %r12
xorl %ebp, %ebp
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testl %ebp, %ebp
je .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movslq %r13d, %r13
leaq (%r14,%r13,4), %rdx
movl $.L.str.4, %esi
movq %r15, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
incl %r13d
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
movl $.L.str.4, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
.LBB3_6: # in Loop: Header=BB3_3 Depth=1
movq %r15, %rdi
callq feof
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_3 Depth=1
leal 1(%rbp), %eax
cmpl %ebx, %ebp
movl %eax, %ebp
jl .LBB3_3
.LBB3_8: # %.critedge
movq %r15, %rdi
callq fclose
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14loadMatrixFilePcPiii, .Lfunc_end3-_Z14loadMatrixFilePcPiii
.cfi_endproc
# -- End function
.globl _Z9MatrixMulPcS_S_i # -- Begin function _Z9MatrixMulPcS_S_i
.p2align 4, 0x90
.type _Z9MatrixMulPcS_S_i,@function
_Z9MatrixMulPcS_S_i: # @_Z9MatrixMulPcS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 8(%rsp) # 8-byte Spill
movq %rsi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movl %ecx, %r13d
movq %r13, %rcx
shlq $32, %rcx
movq %rcx, 64(%rsp) # 8-byte Spill
movslq %eax, %rdi
movq %rdi, 16(%rsp) # 8-byte Spill
callq malloc
movq %r12, %rdi
movq %rax, 24(%rsp) # 8-byte Spill
movq %rax, %rsi
movl %ebx, %edx
movl %ebx, %ecx
callq _Z14loadMatrixFilePcPiii
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB4_5
# %bb.1: # %.preheader.i.preheader
xorl %r12d, %r12d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %r12d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r13
jne .LBB4_3
# %bb.4: # %._crit_edge.i
# in Loop: Header=BB4_2 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %rbp
addl %ebx, %r12d
cmpq %r13, %rbp
jne .LBB4_2
.LBB4_5: # %_Z11printMatrixPiii.exit
addq %r13, 64(%rsp) # 8-byte Folded Spill
movq 16(%rsp), %rdi # 8-byte Reload
callq malloc
movq 8(%rsp), %rdi # 8-byte Reload
movq %rax, 8(%rsp) # 8-byte Spill
movq %rax, %rsi
movl %ebx, %edx
movl %ebx, %ecx
callq _Z14loadMatrixFilePcPiii
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebx, %ebx
jle .LBB4_10
# %bb.6: # %.preheader.i46.preheader
xorl %ebp, %ebp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_7: # %.preheader.i46
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_8: # Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq %r12, %r13
jne .LBB4_8
# %bb.9: # %._crit_edge.i48
# in Loop: Header=BB4_7 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r15
addl %ebx, %ebp
cmpq %r13, %r15
jne .LBB4_7
.LBB4_10: # %_Z11printMatrixPiii.exit55
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq malloc
movq %rax, %r12
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq 64(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %ebx, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z15MatrixMulKernelPiS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
movq 32(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl %ebx, 16(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB4_17
# %bb.13: # %.preheader.i58.preheader
xorl %r15d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_14: # %.preheader.i58
# =>This Loop Header: Depth=1
# Child Loop BB4_15 Depth 2
movl %r15d, %eax
movq %r12, %rbx
leaq (%r12,%rax,4), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB4_15: # Parent Loop BB4_14 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r12,%rbp,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbp
cmpq %rbp, %r13
jne .LBB4_15
# %bb.16: # %._crit_edge.i60
# in Loop: Header=BB4_14 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
addl 16(%rsp), %r15d # 4-byte Folded Reload
cmpq %r13, %r14
movq %rbx, %r12
jne .LBB4_14
.LBB4_17: # %_Z11printMatrixPiii.exit67
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
movq %r12, %rdi
callq free
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9MatrixMulPcS_S_i, .Lfunc_end4-_Z9MatrixMulPcS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB5_1
# %bb.2:
movq 8(%rsi), %r12
movq 16(%rsi), %rbx
movq 24(%rsi), %r14
movq %rsi, (%rsp) # 8-byte Spill
movq 32(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $.L.str.9, %edi
movq %rbx, %rsi
movq %r12, %rdx
movq %r14, %rcx
movl %r15d, %r8d
xorl %eax, %eax
callq printf
movl $.L.str.3, %esi
movq %r12, %rdi
callq fopen
movq %rax, %r12
movl $.L.str.3, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r13
movl $.L.str.3, %esi
movq %r14, %rdi
callq fopen
movq %rax, %rbp
testq %r12, %r12
jne .LBB5_6
# %bb.3:
testq %r13, %r13
jne .LBB5_6
# %bb.4:
testq %rbp, %rbp
jne .LBB5_6
# %bb.5:
movq (%rsp), %rax # 8-byte Reload
movq 8(%rax), %rsi
movq 16(%rax), %rdx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_7
.LBB5_1:
movq (%rsi), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
jmp .LBB5_8
.LBB5_6:
movq %rbx, %rsi
movq %r14, %rdx
movl %r15d, %ecx
callq _Z9MatrixMulPcS_S_i
.LBB5_7:
movq %r12, %rdi
callq fclose
movq %r13, %rdi
callq fclose
movq %rbp, %rdi
callq fclose
.LBB5_8:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPiS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixAddKernelPiS_S_i,@object # @_Z15MatrixAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z15MatrixAddKernelPiS_S_i
.p2align 3, 0x0
_Z15MatrixAddKernelPiS_S_i:
.quad _Z30__device_stub__MatrixAddKernelPiS_S_i
.size _Z15MatrixAddKernelPiS_S_i, 8
.type _Z15MatrixMulKernelPiS_S_i,@object # @_Z15MatrixMulKernelPiS_S_i
.globl _Z15MatrixMulKernelPiS_S_i
.p2align 3, 0x0
_Z15MatrixMulKernelPiS_S_i:
.quad _Z30__device_stub__MatrixMulKernelPiS_S_i
.size _Z15MatrixMulKernelPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n \n "
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " %02d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " \n\n "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " %d"
.size .L.str.4, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nusage: %s configurationVector spikingVector spikingTransitionMatrix squarematrixwidth\n\n"
.size .L.str.8, 89
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nYou have entered files %s, %s, and %s and square matrix width %d \n"
.size .L.str.9, 68
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n could not open one of the following files: %s %s \n"
.size .L.str.10, 53
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixAddKernelPiS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15MatrixMulKernelPiS_S_i"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " \ns after loading from file: "
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " \nM after loading from file: "
.size .Lstr.1, 30
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " \ns * M: "
.size .Lstr.2, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixAddKernelPiS_S_i
.addrsig_sym _Z30__device_stub__MatrixMulKernelPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixAddKernelPiS_S_i
.addrsig_sym _Z15MatrixMulKernelPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void VectorAdd(int *a, int *r, int n, double gamma)
{
int i=threadIdx.x;
if(i<n)
r[i] = (int)(255.0*pow((double)a[i]/255.0,1.0/gamma));
} | .file "tmpxft_001afa17_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9VectorAddPiS_idPiS_id
.type _Z32__device_stub__Z9VectorAddPiS_idPiS_id, @function
_Z32__device_stub__Z9VectorAddPiS_idPiS_id:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_id(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9VectorAddPiS_idPiS_id, .-_Z32__device_stub__Z9VectorAddPiS_idPiS_id
.globl _Z9VectorAddPiS_id
.type _Z9VectorAddPiS_id, @function
_Z9VectorAddPiS_id:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9VectorAddPiS_idPiS_id
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9VectorAddPiS_id, .-_Z9VectorAddPiS_id
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPiS_id"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_id(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void VectorAdd(int *a, int *r, int n, double gamma)
{
int i=threadIdx.x;
if(i<n)
r[i] = (int)(255.0*pow((double)a[i]/255.0,1.0/gamma));
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorAdd(int *a, int *r, int n, double gamma)
{
int i=threadIdx.x;
if(i<n)
r[i] = (int)(255.0*pow((double)a[i]/255.0,1.0/gamma));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorAdd(int *a, int *r, int n, double gamma)
{
int i=threadIdx.x;
if(i<n)
r[i] = (int)(255.0*pow((double)a[i]/255.0,1.0/gamma));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPiS_id
.globl _Z9VectorAddPiS_id
.p2align 8
.type _Z9VectorAddPiS_id,@function
_Z9VectorAddPiS_id:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s1, 0x3fe55555
s_waitcnt lgkmcnt(0)
global_load_b32 v0, v2, s[4:5]
v_div_scale_f64 v[5:6], null, s[2:3], s[2:3], 1.0
s_mov_b32 s5, 0x3fbdee67
s_mov_b32 s4, 0x4222de17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[5:6]
s_waitcnt_depctr 0xfff
v_fma_f64 v[13:14], -v[5:6], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], -v[5:6], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[13:14], v[9:10]
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[3:4], null, 0x406fe000, 0x406fe000, v[0:1]
v_div_scale_f64 v[15:16], vcc_lo, v[0:1], 0x406fe000, v[0:1]
v_rcp_f64_e32 v[7:8], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[3:4], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[11:12], v[7:8]
v_fma_f64 v[11:12], -v[3:4], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[7:8], v[11:12], v[7:8]
v_div_scale_f64 v[11:12], s0, 1.0, s[2:3], 1.0
v_mul_f64 v[13:14], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[17:18], v[11:12], v[9:10]
v_fma_f64 v[3:4], -v[3:4], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[5:6], -v[5:6], v[17:18], v[11:12]
v_div_fmas_f64 v[3:4], v[3:4], v[7:8], v[13:14]
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, 0x55555555
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[5:6], v[5:6], v[9:10], v[17:18]
v_div_fixup_f64 v[3:4], v[3:4], 0x406fe000, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[0:1], v[5:6], s[2:3], 1.0
s_mov_b32 s3, 0x3fba6564
s_mov_b32 s2, 0x968915a9
v_cmp_neq_f64_e32 vcc_lo, 1.0, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v1, 0x3ff00000, v1, vcc_lo
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_neq_f64_e32 vcc_lo, 0, v[0:1]
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cndmask_b32_e32 v4, 0x3ff00000, v4, vcc_lo
v_frexp_mant_f64_e64 v[5:6], |v[3:4]|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[5:6]
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_ldexp_f64 v[5:6], v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[5:6], 1.0
v_add_f64 v[13:14], v[5:6], -1.0
v_rcp_f64_e32 v[9:10], v[7:8]
v_add_f64 v[15:16], v[7:8], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[13:14], v[9:10]
v_mul_f64 v[17:18], v[7:8], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
v_fma_f64 v[5:6], v[11:12], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[17:18], v[5:6]
v_add_f64 v[15:16], v[13:14], -v[7:8]
v_add_f64 v[17:18], v[7:8], -v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[13:14], -v[15:16]
v_add_f64 v[5:6], v[17:18], -v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[13:14], -v[7:8]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[15:16], v[5:6]
v_mul_f64 v[5:6], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[11:12], v[5:6]
v_add_f64 v[9:10], v[7:8], -v[11:12]
v_mul_f64 v[11:12], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[9:10]
v_fma_f64 v[9:10], v[7:8], v[7:8], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[5:6], v[5:6]
v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[15:16], v[13:14], s[4:5], s[2:3]
s_mov_b32 s3, 0x3fbe25e4
s_mov_b32 s2, 0x3abe935a
v_add_f64 v[11:12], v[13:14], -v[11:12]
v_mul_f64 v[21:22], v[7:8], v[13:14]
s_mov_b32 s5, 0x3ff71547
s_mov_b32 s4, 0x652b82fe
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fc110ef
s_mov_b32 s2, 0x47e6c9c2
v_add_f64 v[9:10], v[9:10], -v[11:12]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fc3b13b
s_mov_b32 s2, 0xcfa74449
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fc745d1
s_mov_b32 s2, 0x71bf3c30
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fcc71c7
s_mov_b32 s2, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fd24924
s_mov_b32 s2, 0x924920da
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3fd99999
s_mov_b32 s2, 0x9999999c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[2:3]
s_mov_b32 s3, 0x3c7abc9e
s_mov_b32 s2, 0x3b39803f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[13:14], v[15:16]
v_fma_f64 v[11:12], v[13:14], v[15:16], -v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12]
v_add_f64 v[15:16], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[19:20], v[15:16], s[0:1]
v_add_f64 v[17:18], v[15:16], -v[17:18]
s_mov_b32 s1, 0xbfe55555
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[23:24], v[19:20], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], -v[17:18]
v_fma_f64 v[17:18], v[13:14], v[7:8], -v[21:22]
s_mov_b32 s1, 0x3c8543b0
s_mov_b32 s0, 0xd5df274d
v_add_f64 v[15:16], v[15:16], -v[23:24]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], s[0:1]
v_fma_f64 v[13:14], v[13:14], v[5:6], v[17:18]
s_mov_b32 s1, 0x3fe62e42
s_mov_b32 s0, 0xfefa39ef
v_ldexp_f64 v[5:6], v[5:6], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], v[15:16]
v_fma_f64 v[9:10], v[9:10], v[7:8], v[13:14]
v_ldexp_f64 v[7:8], v[7:8], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[19:20], v[11:12]
v_add_f64 v[15:16], v[21:22], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[19:20], -v[13:14]
v_mul_f64 v[19:20], v[15:16], v[13:14]
v_add_f64 v[21:22], v[15:16], -v[21:22]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], v[17:18]
v_fma_f64 v[17:18], v[15:16], v[13:14], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], -v[21:22]
v_fma_f64 v[11:12], v[15:16], v[11:12], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[9:10], v[13:14], v[11:12]
v_frexp_exp_i32_f64_e32 v13, v[3:4]
v_add_f64 v[11:12], v[19:20], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
v_cvt_f64_i32_e32 v[13:14], v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[7:8], v[11:12]
v_add_f64 v[17:18], v[11:12], -v[19:20]
v_mul_f64 v[19:20], v[13:14], s[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[15:16], -v[7:8]
v_add_f64 v[9:10], v[9:10], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[17:18], v[13:14], s[0:1], -v[19:20]
s_mov_b32 s1, 0xbfe62e42
v_add_f64 v[7:8], v[11:12], -v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[5:6], v[5:6], v[9:10]
v_fma_f64 v[9:10], v[13:14], s[2:3], v[17:18]
s_mov_b32 s3, 0xbc7abc9e
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[19:20], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[15:16], v[5:6]
v_add_f64 v[19:20], v[7:8], -v[19:20]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[13:14], v[7:8], v[11:12]
v_add_f64 v[15:16], v[11:12], -v[15:16]
v_add_f64 v[9:10], v[9:10], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[13:14], -v[7:8]
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[21:22], v[13:14], -v[17:18]
v_add_f64 v[11:12], v[11:12], -v[17:18]
v_add_f64 v[15:16], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -v[21:22]
v_add_f64 v[7:8], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[15:16], -v[9:10]
v_add_f64 v[7:8], v[15:16], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[15:16], -v[11:12]
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[17:18], v[13:14], v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[9:10], -v[15:16]
v_add_f64 v[11:12], v[17:18], -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], v[9:10]
v_add_f64 v[7:8], v[7:8], -v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[7:8]
v_add_f64 v[7:8], v[17:18], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[7:8], -v[17:18]
v_mul_f64 v[11:12], v[0:1], v[7:8]
v_add_f64 v[5:6], v[5:6], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[7:8], v[0:1], v[7:8], -v[11:12]
v_cmp_class_f64_e64 vcc_lo, v[11:12], 0x204
v_fma_f64 v[5:6], v[0:1], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[11:12], v[5:6]
v_dual_cndmask_b32 v10, v8, v12 :: v_dual_cndmask_b32 v9, v7, v11
v_add_f64 v[7:8], v[7:8], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f64 v[13:14], v[9:10], s[4:5]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_trunc_f64_e32 v[7:8], v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rndne_f64_e32 v[13:14], v[13:14]
v_dual_cndmask_b32 v6, 0, v6 :: v_dual_cndmask_b32 v5, 0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[13:14], s[0:1], v[9:10]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
v_cvt_i32_f64_e32 v19, v[13:14]
v_fma_f64 v[15:16], v[13:14], s[2:3], v[15:16]
s_mov_b32 s3, 0x3e5ade15
s_mov_b32 s2, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], s[2:3], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
v_cmp_neq_f64_e64 s2, v[0:1], |v[0:1]|
v_cmp_lt_f64_e64 s3, |v[3:4]|, 1.0
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[9:10]
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
s_and_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
v_ldexp_f64 v[11:12], v[13:14], v19
v_mul_f64 v[13:14], v[0:1], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v12, 0x7ff00000, v12, s0
v_trunc_f64_e32 v[9:10], v[13:14]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cmp_eq_f64_e32 vcc_lo, v[7:8], v[0:1]
v_and_b32_e32 v8, 0x7fffffff, v1
v_cndmask_b32_e64 v12, 0, v12, s1
v_fma_f64 v[5:6], v[11:12], v[5:6], v[11:12]
v_cmp_class_f64_e64 s1, v[11:12], 0x204
v_cmp_neq_f64_e64 s0, v[9:10], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v12, s1
v_cndmask_b32_e64 v5, v5, v11, s1
s_xor_b32 s1, s2, s3
v_cmp_gt_f64_e64 s2, 0, v[0:1]
v_cmp_eq_f64_e64 s3, 0, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_cndmask_b32 v10, 0, v5 :: v_dual_and_b32 v11, 0x7fffffff, v4
s_and_b32 s0, vcc_lo, s0
v_cndmask_b32_e64 v7, 0x3ff00000, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_bfi_b32 v6, 0x7fffffff, v6, v7
v_cndmask_b32_e64 v7, v8, 0, s1
v_cndmask_b32_e64 v8, v0, 0, s1
v_cmp_eq_f64_e64 s1, |v[3:4]|, 1.0
v_cndmask_b32_e32 v9, 0x7ff80000, v6, vcc_lo
v_cmp_gt_f64_e32 vcc_lo, 0, v[3:4]
s_xor_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v8, v8, v3, s1
v_cndmask_b32_e64 v7, v7, v11, s1
v_cmp_class_f64_e64 s1, v[3:4], 0x204
v_dual_cndmask_b32 v5, v5, v10 :: v_dual_cndmask_b32 v6, v6, v9
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x204
v_cndmask_b32_e64 v3, 0x7ff00000, 0, s2
v_cndmask_b32_e64 v4, 0, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_bfi_b32 v4, 0x7fffffff, v3, v4
v_dual_cndmask_b32 v6, v6, v7 :: v_dual_cndmask_b32 v5, v5, v8
s_or_b32 vcc_lo, s3, s1
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v5, 0, vcc_lo
v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
v_mul_f64 v[3:4], v[3:4], 0x406fe000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, 0x7ff80000, v4, vcc_lo
v_cndmask_b32_e32 v0, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f64_e32 v0, v[0:1]
global_store_b32 v2, v0, s[6:7]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPiS_id
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPiS_id, .Lfunc_end0-_Z9VectorAddPiS_id
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPiS_id
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPiS_id.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorAdd(int *a, int *r, int n, double gamma)
{
int i=threadIdx.x;
if(i<n)
r[i] = (int)(255.0*pow((double)a[i]/255.0,1.0/gamma));
} | .text
.file "VectorAdd.hip"
.globl _Z24__device_stub__VectorAddPiS_id # -- Begin function _Z24__device_stub__VectorAddPiS_id
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPiS_id,@function
_Z24__device_stub__VectorAddPiS_id: # @_Z24__device_stub__VectorAddPiS_id
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPiS_id, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPiS_id, .Lfunc_end0-_Z24__device_stub__VectorAddPiS_id
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPiS_id, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPiS_id,@object # @_Z9VectorAddPiS_id
.section .rodata,"a",@progbits
.globl _Z9VectorAddPiS_id
.p2align 3, 0x0
_Z9VectorAddPiS_id:
.quad _Z24__device_stub__VectorAddPiS_id
.size _Z9VectorAddPiS_id, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPiS_id"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPiS_id
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPiS_id
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001afa17_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9VectorAddPiS_idPiS_id
.type _Z32__device_stub__Z9VectorAddPiS_idPiS_id, @function
_Z32__device_stub__Z9VectorAddPiS_idPiS_id:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPiS_id(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z9VectorAddPiS_idPiS_id, .-_Z32__device_stub__Z9VectorAddPiS_idPiS_id
.globl _Z9VectorAddPiS_id
.type _Z9VectorAddPiS_id, @function
_Z9VectorAddPiS_id:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9VectorAddPiS_idPiS_id
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9VectorAddPiS_id, .-_Z9VectorAddPiS_id
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPiS_id"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPiS_id(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorAdd.hip"
.globl _Z24__device_stub__VectorAddPiS_id # -- Begin function _Z24__device_stub__VectorAddPiS_id
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPiS_id,@function
_Z24__device_stub__VectorAddPiS_id: # @_Z24__device_stub__VectorAddPiS_id
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movsd %xmm0, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPiS_id, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPiS_id, .Lfunc_end0-_Z24__device_stub__VectorAddPiS_id
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPiS_id, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPiS_id,@object # @_Z9VectorAddPiS_id
.section .rodata,"a",@progbits
.globl _Z9VectorAddPiS_id
.p2align 3, 0x0
_Z9VectorAddPiS_id:
.quad _Z24__device_stub__VectorAddPiS_id
.size _Z9VectorAddPiS_id, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPiS_id"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPiS_id
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPiS_id
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* This is a CUDA version of bellman_ford algorithm
* Compile: nvcc -std=c++11 -arch=sm_52 -o cuda_bellman_ford cuda_bellman_ford.cu
* Run: ./cuda_bellman_ford <input file> <number of blocks per grid> <number of threads per block>, you will find the output file 'output.txt'
* */
#include <string>
#include <cassert>
#include <iostream>
#include <fstream>
#include <algorithm>
#include <iomanip>
#include <cstring>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
using std::string;
using std::cout;
using std::endl;
#define INF 1000000
/*
* This is a CHECK function to check CUDA calls
*/
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
/**
* utils is a namespace for utility functions
* including I/O (read input file and print results) and matrix dimension convert(2D->1D) function
*/
namespace utils {
int N; //number of vertices
int *mat; // the adjacency matrix
void abort_with_error_message(string msg) {
std::cerr << msg << endl;
abort();
}
//translate 2-dimension coordinate to 1-dimension
int convert_dimension_2D_1D(int x, int y, int n) {
return x * n + y;
}
int read_file(string filename) {
std::ifstream inputf(filename, std::ifstream::in);
if (!inputf.good()) {
abort_with_error_message("ERROR OCCURRED WHILE READING INPUT FILE");
}
inputf >> N;
//input matrix should be smaller than 20MB * 20MB (400MB, we don't have too much memory for multi-processors)
assert(N < (1024 * 1024 * 20));
mat = (int *) malloc(N * N * sizeof(int));
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++) {
inputf >> mat[convert_dimension_2D_1D(i, j, N)];
}
return 0;
}
int print_result(bool has_negative_cycle, int *dist) {
std::ofstream outputf("output.txt", std::ofstream::out);
if (!has_negative_cycle) {
for (int i = 0; i < N; i++) {
if (dist[i] > INF)
dist[i] = INF;
outputf << dist[i] << '\n';
}
outputf.flush();
} else {
outputf << "FOUND NEGATIVE CYCLE!" << endl;
}
outputf.close();
return 0;
}
}//namespace utils
__global__ void bellman_ford_one_iter(int n, int *d_mat, int *d_dist, bool *d_has_next, int iter_num){
int global_tid = blockDim.x * blockIdx.x + threadIdx.x;
int elementSkip = blockDim.x * gridDim.x;
if(global_tid >= n) return;
for(int u = 0 ; u < n ; u ++){
for(int v = global_tid; v < n; v+= elementSkip){
int weight = d_mat[u * n + v];
if(weight < INF){
int new_dist = d_dist[u] + weight;
if(new_dist < d_dist[v]){
d_dist[v] = new_dist;
*d_has_next = true;
}
}
}
}
}
/**
* Bellman-Ford algorithm. Find the shortest path from vertex 0 to other vertices.
* @param blockPerGrid number of blocks per grid
* @param threadsPerBlock number of threads per block
* @param n input size
* @param *mat input adjacency matrix
* @param *dist distance array
* @param *has_negative_cycle a bool variable to recode if there are negative cycles
*/
void bellman_ford(int blocksPerGrid, int threadsPerBlock, int n, int *mat, int *dist, bool *has_negative_cycle) {
dim3 blocks(blocksPerGrid);
dim3 threads(threadsPerBlock);
int iter_num = 0;
int *d_mat, *d_dist;
bool *d_has_next, h_has_next;
cudaMalloc(&d_mat, sizeof(int) * n * n);
cudaMalloc(&d_dist, sizeof(int) *n);
cudaMalloc(&d_has_next, sizeof(bool));
*has_negative_cycle = false;
for(int i = 0 ; i < n; i ++){
dist[i] = INF;
}
dist[0] = 0;
cudaMemcpy(d_mat, mat, sizeof(int) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_dist, dist, sizeof(int) * n, cudaMemcpyHostToDevice);
for(;;){
h_has_next = false;
cudaMemcpy(d_has_next, &h_has_next, sizeof(bool), cudaMemcpyHostToDevice);
bellman_ford_one_iter<<<blocks, threads>>>(n, d_mat, d_dist, d_has_next, iter_num);
CHECK(cudaDeviceSynchronize());
cudaMemcpy(&h_has_next, d_has_next, sizeof(bool), cudaMemcpyDeviceToHost);
iter_num++;
if(iter_num >= n-1){
*has_negative_cycle = true;
break;
}
if(!h_has_next){
break;
}
}
if(! *has_negative_cycle){
cudaMemcpy(dist, d_dist, sizeof(int) * n, cudaMemcpyDeviceToHost);
}
cudaFree(d_mat);
cudaFree(d_dist);
cudaFree(d_has_next);
}
int main(int argc, char **argv) {
if (argc <= 1) {
utils::abort_with_error_message("INPUT FILE WAS NOT FOUND!");
}
if (argc <= 3) {
utils::abort_with_error_message("blocksPerGrid or threadsPerBlock WAS NOT FOUND!");
}
string filename = argv[1];
int blockPerGrid = atoi(argv[2]);
int threadsPerBlock = atoi(argv[3]);
int *dist;
bool has_negative_cycle = false;
assert(utils::read_file(filename) == 0);
dist = (int *) calloc(sizeof(int), utils::N);
//time counter
timeval start_wall_time_t, end_wall_time_t;
float ms_wall;
cudaDeviceReset();
//start timer
gettimeofday(&start_wall_time_t, nullptr);
//bellman-ford algorithm
bellman_ford(blockPerGrid, threadsPerBlock, utils::N, utils::mat, dist, &has_negative_cycle);
CHECK(cudaDeviceSynchronize());
//end timer
gettimeofday(&end_wall_time_t, nullptr);
ms_wall = ((end_wall_time_t.tv_sec - start_wall_time_t.tv_sec) * 1000 * 1000
+ end_wall_time_t.tv_usec - start_wall_time_t.tv_usec) / 1000.0;
std::cerr.setf(std::ios::fixed);
std::cerr << std::setprecision(6) << "Time(s): " << (ms_wall/1000.0) << endl;
utils::print_result(has_negative_cycle, dist);
free(dist);
free(utils::mat);
return 0;
} | code for sm_80
Function : _Z21bellman_ford_one_iteriPiS_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], !P0 ; /* 0x0000580000007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fe20000000f00 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ MOV R17, 0x4 ; /* 0x0000000400117802 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a24 */
/* 0x000fe400078e02ff */
/*00d0*/ IMAD.WIDE R16, R0, R17, c[0x0][0x170] ; /* 0x00005c0000107625 */
/* 0x000fe400078e0211 */
/*00e0*/ I2F.U32.RP R7, R3 ; /* 0x0000000300077306 */
/* 0x000e220000209000 */
/*00f0*/ ISETP.NE.U32.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f45070 */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x000fc400078e0a03 */
/*0110*/ IMAD.IADD R2, R0, 0x1, R3 ; /* 0x0000000100027824 */
/* 0x000fe400078e0203 */
/*0120*/ IMAD.WIDE R14, R3, 0x4, R16 ; /* 0x00000004030e7825 */
/* 0x000fc600078e0210 */
/*0130*/ LOP3.LUT R6, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff067212 */
/* 0x000fc600078e33ff */
/*0140*/ IMAD.WIDE R12, R3, 0x4, R14 ; /* 0x00000004030c7825 */
/* 0x000fe200078e020e */
/*0150*/ IADD3 R6, R6, c[0x0][0x160], R3 ; /* 0x0000580006067a10 */
/* 0x000fe20007ffe003 */
/*0160*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0170*/ IADD3 R5, R7, 0xffffffe, RZ ; /* 0x0ffffffe07057810 */
/* 0x001fcc0007ffe0ff */
/*0180*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*0190*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x001fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R9, R5, R9, R4 ; /* 0x0000000905097227 */
/* 0x000fc800078e0004 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.HI.U32 R4, R9, R6, RZ ; /* 0x0000000609047227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -R4 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a04 */
/*01e0*/ IMAD R6, R3, R7, R6 ; /* 0x0000000703067224 */
/* 0x000fca00078e0206 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IMAD.IADD R6, R6, 0x1, -R3 ; /* 0x0000000106060824 */
/* 0x000fe200078e0a03 */
/*0210*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f26070 */
/*0230*/ IMAD.IADD R6, R3, 0x1, R2 ; /* 0x0000000103067824 */
/* 0x000fca00078e0202 */
/*0240*/ IADD3 R7, R3, R6, RZ ; /* 0x0000000603077210 */
/* 0x000fce0007ffe0ff */
/*0250*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0260*/ @!P2 LOP3.LUT R4, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff04a212 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R8, R4, 0x1, RZ ; /* 0x0000000104087810 */
/* 0x000fc80007ffe0ff */
/*0280*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fc800078ec0ff */
/*0290*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*02a0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff147424 */
/* 0x001fe200078e00ff */
/*02b0*/ BSSY B0, 0x6a0 ; /* 0x000003e000007945 */
/* 0x000fe20003800000 */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*02d0*/ MOV R26, R0 ; /* 0x00000000001a7202 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.WIDE R10, R5.reuse, R20, c[0x0][0x170] ; /* 0x00005c00050a7625 */
/* 0x040fe200078e0214 */
/*02f0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x160], PT ; /* 0x0000580005007a0c */
/* 0x000fc60003f06270 */
/*0310*/ @!P1 BRA 0x690 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD R19, R9, c[0x0][0x160], R0 ; /* 0x0000580009137a24 */
/* 0x000fc800078e0200 */
/*0330*/ IMAD.WIDE R18, R19, R20, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0214 */
/*0340*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x000ea2000c1e1900 */
/*0350*/ BSSY B1, 0x430 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0360*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f25270 */
/*0370*/ ISETP.GT.AND P2, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f44270 */
/*0380*/ @P2 BRA 0x420 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.IADD R22, R21, 0x1, R18 ; /* 0x0000000115167824 */
/* 0x004fe400078e0212 */
/*03c0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fc600078e00ff */
/*03d0*/ ISETP.GE.AND P2, PT, R22, R19, PT ; /* 0x000000131600720c */
/* 0x008fda0003f46270 */
/*03e0*/ @!P2 MOV R18, c[0x0][0x178] ; /* 0x00005e000012aa02 */
/* 0x000fe20000000f00 */
/*03f0*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff13a624 */
/* 0x000fe200078e00ff */
/*0400*/ @!P2 STG.E [R16.64], R22 ; /* 0x000000161000a986 */
/* 0x0001e8000c101904 */
/*0410*/ @!P2 STG.E.U8 [R18.64], R21 ; /* 0x000000151200a986 */
/* 0x0001e4000c101104 */
/*0420*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R26, RZ, RZ, R2 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0002 */
/*0440*/ @!P1 BRA 0x690 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R19, R9, c[0x0][0x160], R2 ; /* 0x0000580009137a24 */
/* 0x001fc800078e0202 */
/*0460*/ IMAD.WIDE R18, R19, R20, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0214 */
/*0470*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x000ea2000c1e1900 */
/*0480*/ BSSY B1, 0x560 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0490*/ ISETP.NE.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe40003f25270 */
/*04a0*/ ISETP.GT.AND P2, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f44270 */
/*04b0*/ @P2 BRA 0x550 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000ee2000c1e1900 */
/*04e0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*04f0*/ IADD3 R21, R21, R18, RZ ; /* 0x0000001215157210 */
/* 0x004fc80007ffe0ff */
/*0500*/ ISETP.GE.AND P2, PT, R21, R19, PT ; /* 0x000000131500720c */
/* 0x008fda0003f46270 */
/*0510*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff12a624 */
/* 0x000fe200078e00ff */
/*0520*/ @!P2 MOV R19, c[0x0][0x17c] ; /* 0x00005f000013aa02 */
/* 0x000fe20000000f00 */
/*0530*/ @!P2 STG.E [R14.64], R21 ; /* 0x000000150e00a986 */
/* 0x0001e8000c101904 */
/*0540*/ @!P2 STG.E.U8 [R18.64], R22 ; /* 0x000000161200a986 */
/* 0x0001e4000c101104 */
/*0550*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.MOV.U32 R26, RZ, RZ, R6 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0006 */
/*0570*/ @!P1 BRA 0x690 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0580*/ IMAD R21, R9, c[0x0][0x160], R6 ; /* 0x0000580009157a24 */
/* 0x001fc800078e0206 */
/*0590*/ IMAD.WIDE R20, R21, R20, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fcc00078e0214 */
/*05a0*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IMAD.MOV.U32 R26, RZ, RZ, R7 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0007 */
/*05c0*/ ISETP.GT.AND P1, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f24270 */
/*05d0*/ @P1 BRA 0x690 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*05e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ee2000c1e1900 */
/*0600*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R26, R7 ; /* 0x00000007001a7202 */
/* 0x000fe40000000f00 */
/*0620*/ IADD3 R21, R21, R18, RZ ; /* 0x0000001215157210 */
/* 0x004fc80007ffe0ff */
/*0630*/ ISETP.GE.AND P1, PT, R21, R19, PT ; /* 0x000000131500720c */
/* 0x008fda0003f26270 */
/*0640*/ @!P1 MOV R18, c[0x0][0x178] ; /* 0x00005e0000129a02 */
/* 0x000fe20000000f00 */
/*0650*/ @!P1 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff139624 */
/* 0x000fe200078e00ff */
/*0660*/ @!P1 STG.E [R12.64], R21 ; /* 0x000000150c009986 */
/* 0x0001e2000c101904 */
/*0670*/ @!P1 IMAD.MOV.U32 R26, RZ, RZ, R7 ; /* 0x000000ffff1a9224 */
/* 0x000fc600078e0007 */
/*0680*/ @!P1 STG.E.U8 [R18.64], R20 ; /* 0x0000001412009986 */
/* 0x0001e8000c101104 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*06b0*/ BSSY B0, 0xb90 ; /* 0x000004d000007945 */
/* 0x000fd80003800000 */
/*06c0*/ @!P1 BRA 0xb80 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*06d0*/ HFMA2.MMA R24, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff187435 */
/* 0x001fe200000001ff */
/*06e0*/ IMAD R19, R9, c[0x0][0x160], R26 ; /* 0x0000580009137a24 */
/* 0x001fd200078e021a */
/*06f0*/ IMAD.WIDE R18, R19, R24, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0218 */
/*0700*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ea2000c1e1900 */
/*0710*/ BSSY B1, 0x810 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0720*/ IMAD.WIDE R20, R3, 0x4, R18 ; /* 0x0000000403147825 */
/* 0x000fe200078e0212 */
/*0730*/ ISETP.GT.AND P1, PT, R25, 0xf423f, PT ; /* 0x000f423f1900780c */
/* 0x004fda0003f24270 */
/*0740*/ @P1 BRA 0x800 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.WIDE R22, R26, R24, c[0x0][0x170] ; /* 0x00005c001a167625 */
/* 0x000fe200078e0218 */
/*0760*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.IADD R25, R25, 0x1, R18 ; /* 0x0000000119197824 */
/* 0x004fe200078e0212 */
/*0790*/ MOV R18, 0x1 ; /* 0x0000000100127802 */
/* 0x000fc80000000f00 */
/*07a0*/ ISETP.GE.AND P1, PT, R25, R19, PT ; /* 0x000000131900720c */
/* 0x008fda0003f26270 */
/*07b0*/ @!P1 STG.E [R22.64], R25 ; /* 0x0000001916009986 */
/* 0x0001e2000c101904 */
/*07c0*/ @!P1 MOV R19, c[0x0][0x17c] ; /* 0x00005f0000139a02 */
/* 0x000fe40000000f00 */
/*07d0*/ @!P1 PRMT R23, R18, 0x7610, R23 ; /* 0x0000761012179816 */
/* 0x001fe20000000017 */
/*07e0*/ @!P1 IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff129624 */
/* 0x000fca00078e00ff */
/*07f0*/ @!P1 STG.E.U8 [R18.64], R23 ; /* 0x0000001712009986 */
/* 0x0001e4000c101104 */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0820*/ BSSY B1, 0x930 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*0830*/ IMAD.WIDE R18, R3, 0x4, R20 ; /* 0x0000000403127825 */
/* 0x001fc800078e0214 */
/*0840*/ IMAD.IADD R25, R3, 0x1, R26 ; /* 0x0000000103197824 */
/* 0x000fe200078e021a */
/*0850*/ ISETP.GT.AND P1, PT, R27, 0xf423f, PT ; /* 0x000f423f1b00780c */
/* 0x004fda0003f24270 */
/*0860*/ @P1 BRA 0x920 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.WIDE R22, R25, R24, c[0x0][0x170] ; /* 0x00005c0019167625 */
/* 0x000fe200078e0218 */
/*0880*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x000ee2000c1e1900 */
/*08a0*/ IADD3 R27, R27, R20, RZ ; /* 0x000000141b1b7210 */
/* 0x004fe20007ffe0ff */
/*08b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fc600078e00ff */
/*08c0*/ ISETP.GE.AND P1, PT, R27, R21, PT ; /* 0x000000151b00720c */
/* 0x008fda0003f26270 */
/*08d0*/ @!P1 STG.E [R22.64], R27 ; /* 0x0000001b16009986 */
/* 0x0001e2000c101904 */
/*08e0*/ @!P1 IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff159624 */
/* 0x000fe200078e00ff */
/*08f0*/ @!P1 PRMT R23, R20, 0x7610, R23 ; /* 0x0000761014179816 */
/* 0x001fe40000000017 */
/*0900*/ @!P1 MOV R20, c[0x0][0x178] ; /* 0x00005e0000149a02 */
/* 0x000fca0000000f00 */
/*0910*/ @!P1 STG.E.U8 [R20.64], R23 ; /* 0x0000001714009986 */
/* 0x0001e4000c101104 */
/*0920*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0930*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x000ea2000c1e1900 */
/*0940*/ BSSY B1, 0xa50 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*0950*/ IMAD.WIDE R20, R3.reuse, 0x4, R18 ; /* 0x0000000403147825 */
/* 0x041fe200078e0212 */
/*0960*/ IADD3 R25, R3, R25, RZ ; /* 0x0000001903197210 */
/* 0x000fe40007ffe0ff */
/*0970*/ ISETP.GT.AND P1, PT, R27, 0xf423f, PT ; /* 0x000f423f1b00780c */
/* 0x004fda0003f24270 */
/*0980*/ @P1 BRA 0xa40 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD.WIDE R18, R25, R24, c[0x0][0x170] ; /* 0x00005c0019127625 */
/* 0x000fe200078e0218 */
/*09a0*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.IADD R27, R27, 0x1, R22 ; /* 0x000000011b1b7824 */
/* 0x004fe200078e0216 */
/*09d0*/ HFMA2.MMA R22, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff167435 */
/* 0x000fc800000001ff */
/*09e0*/ ISETP.GE.AND P1, PT, R27, R23, PT ; /* 0x000000171b00720c */
/* 0x008fda0003f26270 */
/*09f0*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e2000c101904 */
/*0a00*/ @!P1 MOV R23, c[0x0][0x17c] ; /* 0x00005f0000179a02 */
/* 0x000fe40000000f00 */
/*0a10*/ @!P1 PRMT R19, R22, 0x7610, R19 ; /* 0x0000761016139816 */
/* 0x001fe20000000013 */
/*0a20*/ @!P1 IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff169624 */
/* 0x000fca00078e00ff */
/*0a30*/ @!P1 STG.E.U8 [R22.64], R19 ; /* 0x0000001316009986 */
/* 0x0001e4000c101104 */
/*0a40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a50*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ea2000c1e1900 */
/*0a60*/ BSSY B1, 0xb50 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0a70*/ IMAD.IADD R26, R3, 0x1, R25 ; /* 0x00000001031a7824 */
/* 0x000fe200078e0219 */
/*0a80*/ ISETP.GT.AND P1, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f24270 */
/*0a90*/ @P1 BRA 0xb40 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.WIDE R24, R26, R24, c[0x0][0x170] ; /* 0x00005c001a187625 */
/* 0x000fe200078e0218 */
/*0ab0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x001ee2000c1e1900 */
/*0ad0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe200078e00ff */
/*0ae0*/ IADD3 R21, R21, R18, RZ ; /* 0x0000001215157210 */
/* 0x004fc80007ffe0ff */
/*0af0*/ ISETP.GE.AND P1, PT, R21, R19, PT ; /* 0x000000131500720c */
/* 0x008fda0003f26270 */
/*0b00*/ @!P1 MOV R18, c[0x0][0x178] ; /* 0x00005e0000129a02 */
/* 0x000fe20000000f00 */
/*0b10*/ @!P1 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff139624 */
/* 0x000fe200078e00ff */
/*0b20*/ @!P1 STG.E [R24.64], R21 ; /* 0x0000001518009986 */
/* 0x0001e8000c101904 */
/*0b30*/ @!P1 STG.E.U8 [R18.64], R20 ; /* 0x0000001412009986 */
/* 0x0001e4000c101104 */
/*0b40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b50*/ IADD3 R26, R3, R26, RZ ; /* 0x0000001a031a7210 */
/* 0x000fc80007ffe0ff */
/*0b60*/ ISETP.GE.AND P1, PT, R26, c[0x0][0x160], PT ; /* 0x000058001a007a0c */
/* 0x000fda0003f26270 */
/*0b70*/ @!P1 BRA 0x6d0 ; /* 0xfffffb5000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ @!P0 BRA 0x290 ; /* 0xfffff6f000008947 */
/* 0x000fea000383ffff */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* This is a CUDA version of bellman_ford algorithm
* Compile: nvcc -std=c++11 -arch=sm_52 -o cuda_bellman_ford cuda_bellman_ford.cu
* Run: ./cuda_bellman_ford <input file> <number of blocks per grid> <number of threads per block>, you will find the output file 'output.txt'
* */
#include <string>
#include <cassert>
#include <iostream>
#include <fstream>
#include <algorithm>
#include <iomanip>
#include <cstring>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
using std::string;
using std::cout;
using std::endl;
#define INF 1000000
/*
* This is a CHECK function to check CUDA calls
*/
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
/**
* utils is a namespace for utility functions
* including I/O (read input file and print results) and matrix dimension convert(2D->1D) function
*/
namespace utils {
int N; //number of vertices
int *mat; // the adjacency matrix
void abort_with_error_message(string msg) {
std::cerr << msg << endl;
abort();
}
//translate 2-dimension coordinate to 1-dimension
int convert_dimension_2D_1D(int x, int y, int n) {
return x * n + y;
}
int read_file(string filename) {
std::ifstream inputf(filename, std::ifstream::in);
if (!inputf.good()) {
abort_with_error_message("ERROR OCCURRED WHILE READING INPUT FILE");
}
inputf >> N;
//input matrix should be smaller than 20MB * 20MB (400MB, we don't have too much memory for multi-processors)
assert(N < (1024 * 1024 * 20));
mat = (int *) malloc(N * N * sizeof(int));
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++) {
inputf >> mat[convert_dimension_2D_1D(i, j, N)];
}
return 0;
}
int print_result(bool has_negative_cycle, int *dist) {
std::ofstream outputf("output.txt", std::ofstream::out);
if (!has_negative_cycle) {
for (int i = 0; i < N; i++) {
if (dist[i] > INF)
dist[i] = INF;
outputf << dist[i] << '\n';
}
outputf.flush();
} else {
outputf << "FOUND NEGATIVE CYCLE!" << endl;
}
outputf.close();
return 0;
}
}//namespace utils
__global__ void bellman_ford_one_iter(int n, int *d_mat, int *d_dist, bool *d_has_next, int iter_num){
int global_tid = blockDim.x * blockIdx.x + threadIdx.x;
int elementSkip = blockDim.x * gridDim.x;
if(global_tid >= n) return;
for(int u = 0 ; u < n ; u ++){
for(int v = global_tid; v < n; v+= elementSkip){
int weight = d_mat[u * n + v];
if(weight < INF){
int new_dist = d_dist[u] + weight;
if(new_dist < d_dist[v]){
d_dist[v] = new_dist;
*d_has_next = true;
}
}
}
}
}
/**
* Bellman-Ford algorithm. Find the shortest path from vertex 0 to other vertices.
* @param blockPerGrid number of blocks per grid
* @param threadsPerBlock number of threads per block
* @param n input size
* @param *mat input adjacency matrix
* @param *dist distance array
* @param *has_negative_cycle a bool variable to recode if there are negative cycles
*/
void bellman_ford(int blocksPerGrid, int threadsPerBlock, int n, int *mat, int *dist, bool *has_negative_cycle) {
dim3 blocks(blocksPerGrid);
dim3 threads(threadsPerBlock);
int iter_num = 0;
int *d_mat, *d_dist;
bool *d_has_next, h_has_next;
cudaMalloc(&d_mat, sizeof(int) * n * n);
cudaMalloc(&d_dist, sizeof(int) *n);
cudaMalloc(&d_has_next, sizeof(bool));
*has_negative_cycle = false;
for(int i = 0 ; i < n; i ++){
dist[i] = INF;
}
dist[0] = 0;
cudaMemcpy(d_mat, mat, sizeof(int) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_dist, dist, sizeof(int) * n, cudaMemcpyHostToDevice);
for(;;){
h_has_next = false;
cudaMemcpy(d_has_next, &h_has_next, sizeof(bool), cudaMemcpyHostToDevice);
bellman_ford_one_iter<<<blocks, threads>>>(n, d_mat, d_dist, d_has_next, iter_num);
CHECK(cudaDeviceSynchronize());
cudaMemcpy(&h_has_next, d_has_next, sizeof(bool), cudaMemcpyDeviceToHost);
iter_num++;
if(iter_num >= n-1){
*has_negative_cycle = true;
break;
}
if(!h_has_next){
break;
}
}
if(! *has_negative_cycle){
cudaMemcpy(dist, d_dist, sizeof(int) * n, cudaMemcpyDeviceToHost);
}
cudaFree(d_mat);
cudaFree(d_dist);
cudaFree(d_has_next);
}
int main(int argc, char **argv) {
if (argc <= 1) {
utils::abort_with_error_message("INPUT FILE WAS NOT FOUND!");
}
if (argc <= 3) {
utils::abort_with_error_message("blocksPerGrid or threadsPerBlock WAS NOT FOUND!");
}
string filename = argv[1];
int blockPerGrid = atoi(argv[2]);
int threadsPerBlock = atoi(argv[3]);
int *dist;
bool has_negative_cycle = false;
assert(utils::read_file(filename) == 0);
dist = (int *) calloc(sizeof(int), utils::N);
//time counter
timeval start_wall_time_t, end_wall_time_t;
float ms_wall;
cudaDeviceReset();
//start timer
gettimeofday(&start_wall_time_t, nullptr);
//bellman-ford algorithm
bellman_ford(blockPerGrid, threadsPerBlock, utils::N, utils::mat, dist, &has_negative_cycle);
CHECK(cudaDeviceSynchronize());
//end timer
gettimeofday(&end_wall_time_t, nullptr);
ms_wall = ((end_wall_time_t.tv_sec - start_wall_time_t.tv_sec) * 1000 * 1000
+ end_wall_time_t.tv_usec - start_wall_time_t.tv_usec) / 1000.0;
std::cerr.setf(std::ios::fixed);
std::cerr << std::setprecision(6) << "Time(s): " << (ms_wall/1000.0) << endl;
utils::print_result(has_negative_cycle, dist);
free(dist);
free(utils::mat);
return 0;
} | .file "tmpxft_0015af36_00000000-6_cuda_bellman_ford.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4301:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4301:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB4293:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 8(%rdi), %rdx
movq (%rdi), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call abort@PLT
.cfi_endproc
.LFE4293:
.size _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.globl _ZN5utils23convert_dimension_2D_1DEiii
.type _ZN5utils23convert_dimension_2D_1DEiii, @function
_ZN5utils23convert_dimension_2D_1DEiii:
.LFB4294:
.cfi_startproc
endbr64
imull %edx, %edi
leal (%rdi,%rsi), %eax
ret
.cfi_endproc
.LFE4294:
.size _ZN5utils23convert_dimension_2D_1DEiii, .-_ZN5utils23convert_dimension_2D_1DEiii
.globl _Z47__device_stub__Z21bellman_ford_one_iteriPiS_PbiiPiS_Pbi
.type _Z47__device_stub__Z21bellman_ford_one_iteriPiS_PbiiPiS_Pbi, @function
_Z47__device_stub__Z21bellman_ford_one_iteriPiS_PbiiPiS_Pbi:
.LFB4323:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movl %r8d, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21bellman_ford_one_iteriPiS_Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4323:
.size _Z47__device_stub__Z21bellman_ford_one_iteriPiS_PbiiPiS_Pbi, .-_Z47__device_stub__Z21bellman_ford_one_iteriPiS_PbiiPiS_Pbi
.globl _Z21bellman_ford_one_iteriPiS_Pbi
.type _Z21bellman_ford_one_iteriPiS_Pbi, @function
_Z21bellman_ford_one_iteriPiS_Pbi:
.LFB4324:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z21bellman_ford_one_iteriPiS_PbiiPiS_Pbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4324:
.size _Z21bellman_ford_one_iteriPiS_Pbi, .-_Z21bellman_ford_one_iteriPiS_Pbi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/qiansunn/BellmanFord/master/cuda_bellman_ford.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: %s:%d, "
.LC2:
.string "code: %d, reason: %s\n"
.text
.globl _Z12bellman_fordiiiPiS_Pb
.type _Z12bellman_fordiiiPiS_Pb, @function
_Z12bellman_fordiiiPiS_Pb:
.LFB4297:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edx, %r13d
movq %rcx, %rbp
movq %r8, %r15
movq %r9, %r12
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl %edi, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %esi, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movslq %edx, %r14
movq %r14, %rbx
imulq %r14, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
salq $2, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
movb $0, (%r12)
testl %r13d, %r13d
jle .L15
movq %r15, %rax
leaq (%r14,%r15), %rdx
.L16:
movl $1000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L16
.L15:
movl $0, (%r15)
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebp
leaq 23(%rsp), %r12
jmp .L21
.L17:
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $2, %ecx
movl $1, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
addl $1, %ebp
leal -1(%r13), %eax
cmpl %ebp, %eax
jle .L27
cmpb $0, 23(%rsp)
je .L28
.L21:
movb $0, 23(%rsp)
movl $1, %ecx
movl $1, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movl %ebp, %r8d
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl %r13d, %edi
call _Z47__device_stub__Z21bellman_ford_one_iteriPiS_PbiiPiS_Pbi
jmp .L17
.L26:
movl $150, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movq 8(%rsp), %rax
movb $1, (%rax)
.L20:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rax
cmpb $0, (%rax)
jne .L20
movl $2, %ecx
movq %r14, %rdx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
jmp .L20
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4297:
.size _Z12bellman_fordiiiPiS_Pb, .-_Z12bellman_fordiiiPiS_Pb
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z21bellman_ford_one_iteriPiS_Pbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4326:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z21bellman_ford_one_iteriPiS_Pbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4326:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4654:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L41
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L42
cmpq $1, %rax
jne .L37
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L38:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L44
leaq .LC4(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L44:
call __stack_chk_fail@PLT
.L42:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L36:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L38
.L37:
testq %rax, %rax
je .L38
jmp .L36
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4654:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.8
.align 8
.LC5:
.string "ERROR OCCURRED WHILE READING INPUT FILE"
.text
.globl _ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.type _ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB4295:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4295
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $584, %rsp
.cfi_def_cfa_offset 640
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 568(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbp
leaq 304(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 304(%rsp)
movq $0, 520(%rsp)
movb $0, 528(%rsp)
movb $0, 529(%rsp)
movq $0, 536(%rsp)
movq $0, 544(%rsp)
movq $0, 552(%rsp)
movq $0, 560(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r14
movq %r14, 48(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r15
movq -24(%r14), %rax
movq %r15, 48(%rsp,%rax)
movq $0, 56(%rsp)
movq 48(%rsp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 40(%rax), %rax
movq %rax, 304(%rsp)
leaq 64(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 64(%rsp), %rsi
leaq 304(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
movq (%rbx), %rsi
leaq 64(%rsp), %rdi
movl $8, %edx
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L79
movq 48(%rsp), %rax
movq -24(%rax), %rax
leaq 48(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L47
.L79:
movq 48(%rsp), %rax
movq -24(%rax), %rax
leaq 48(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE2:
.L47:
movl 336(%rsp), %r13d
testl %r13d, %r13d
jne .L80
leaq 48(%rsp), %rdi
leaq _ZN5utils1NE(%rip), %rsi
.LEHB3:
call _ZNSirsERi@PLT
.LEHE3:
jmp .L81
.L71:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L51:
movq %r14, 48(%rsp)
movq -24(%r14), %rax
movq %r15, 48(%rsp,%rax)
movq $0, 56(%rsp)
.L52:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 304(%rsp)
leaq 304(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L70:
endbr64
movq %rax, %rbx
jmp .L51
.L69:
endbr64
movq %rax, %rbx
jmp .L52
.L53:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L80:
leaq 15(%rsp), %rdx
leaq 16(%rsp), %rdi
leaq .LC5(%rip), %rsi
.LEHB5:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE5:
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L82
leaq 16(%rsp), %rdi
.LEHB6:
call _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE6:
.L68:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L62:
leaq 48(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
je .L63
call __stack_chk_fail@PLT
.L82:
call __stack_chk_fail@PLT
.L81:
movl _ZN5utils1NE(%rip), %ebx
movl %ebx, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, _ZN5utils3matE(%rip)
movl %r13d, %ebp
leaq 48(%rsp), %r12
testl %ebx, %ebx
jg .L55
.L56:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 48(%rsp)
leaq 40(%rax), %rax
movq %rax, 304(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rdi
.LEHB7:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE7:
jmp .L60
.L83:
addl $1, %ebx
movl _ZN5utils1NE(%rip), %eax
cmpl %ebx, %eax
jle .L58
.L57:
imull %ebp, %eax
addl %ebx, %eax
cltq
movq _ZN5utils3matE(%rip), %rdx
leaq (%rdx,%rax,4), %rsi
movq %r12, %rdi
.LEHB8:
call _ZNSirsERi@PLT
.LEHE8:
jmp .L83
.L58:
addl $1, %ebp
cmpl %ebp, _ZN5utils1NE(%rip)
jle .L56
.L55:
movl _ZN5utils1NE(%rip), %eax
movl %r13d, %ebx
testl %eax, %eax
jg .L57
jmp .L58
.L72:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L60:
leaq 168(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 64(%rsp)
leaq 120(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r14, 48(%rsp)
movq -24(%r14), %rax
movq %r15, 48(%rsp,%rax)
movq $0, 56(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 304(%rsp)
leaq 304(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 568(%rsp), %rax
subq %fs:40, %rax
jne .L84
movl $0, %eax
addq $584, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L62
.L63:
movq %rbx, %rdi
.LEHB9:
call _Unwind_Resume@PLT
.LEHE9:
.L84:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4295:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4295:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4295-.LLSDATTD4295
.LLSDATTD4295:
.byte 0x1
.uleb128 .LLSDACSE4295-.LLSDACSB4295
.LLSDACSB4295:
.uleb128 .LEHB0-.LFB4295
.uleb128 .LEHE0-.LEHB0
.uleb128 .L69-.LFB4295
.uleb128 0
.uleb128 .LEHB1-.LFB4295
.uleb128 .LEHE1-.LEHB1
.uleb128 .L70-.LFB4295
.uleb128 0
.uleb128 .LEHB2-.LFB4295
.uleb128 .LEHE2-.LEHB2
.uleb128 .L71-.LFB4295
.uleb128 0
.uleb128 .LEHB3-.LFB4295
.uleb128 .LEHE3-.LEHB3
.uleb128 .L67-.LFB4295
.uleb128 0
.uleb128 .LEHB4-.LFB4295
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4295
.uleb128 .LEHE5-.LEHB5
.uleb128 .L67-.LFB4295
.uleb128 0
.uleb128 .LEHB6-.LFB4295
.uleb128 .LEHE6-.LEHB6
.uleb128 .L68-.LFB4295
.uleb128 0
.uleb128 .LEHB7-.LFB4295
.uleb128 .LEHE7-.LEHB7
.uleb128 .L72-.LFB4295
.uleb128 0x1
.uleb128 .LEHB8-.LFB4295
.uleb128 .LEHE8-.LEHB8
.uleb128 .L67-.LFB4295
.uleb128 0
.uleb128 .LEHB9-.LFB4295
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.LLSDACSE4295:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4295:
.text
.size _ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.section .rodata.str1.1
.LC6:
.string "output.txt"
.LC7:
.string "FOUND NEGATIVE CYCLE!"
.text
.globl _ZN5utils12print_resultEbPi
.type _ZN5utils12print_resultEbPi, @function
_ZN5utils12print_resultEbPi:
.LFB4296:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4296
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $544, %rsp
.cfi_def_cfa_offset 592
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %r12
leaq 264(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 264(%rsp)
movq $0, 480(%rsp)
movb $0, 488(%rsp)
movb $0, 489(%rsp)
movq $0, 496(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq 8+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r13
movq %r13, 16(%rsp)
movq 16+_ZTTSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %r14
movq -24(%r13), %rax
movq %r14, 16(%rsp,%rax)
movq 16(%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB10:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE10:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 264(%rsp)
leaq 24(%rsp), %rdi
.LEHB11:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE11:
leaq 24(%rsp), %rsi
leaq 264(%rsp), %rdi
.LEHB12:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
leaq 24(%rsp), %rdi
movl $16, %edx
leaq .LC6(%rip), %rsi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L119
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L87
.L119:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE12:
.L87:
testb %bl, %bl
jne .L88
movl $0, %ebx
leaq 16(%rsp), %r12
cmpl $0, _ZN5utils1NE(%rip)
jg .L89
.L90:
leaq 16(%rsp), %rdi
.LEHB13:
call _ZNSo5flushEv@PLT
.LEHE13:
jmp .L98
.L113:
endbr64
movq %rax, %rbx
leaq 24(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L92:
movq %r13, 16(%rsp)
movq -24(%r13), %rax
movq %r14, 16(%rsp,%rax)
.L93:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 264(%rsp)
leaq 264(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L94
call __stack_chk_fail@PLT
.L112:
endbr64
movq %rax, %rbx
jmp .L92
.L111:
endbr64
movq %rax, %rbx
jmp .L93
.L94:
movq %rbx, %rdi
.LEHB14:
call _Unwind_Resume@PLT
.LEHE14:
.L120:
movq %rax, %rdi
movb $10, 15(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L96
leaq 15(%rsp), %rsi
movl $1, %edx
.LEHB15:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L97
.L96:
movl $10, %esi
call _ZNSo3putEc@PLT
.L97:
addq $1, %rbx
cmpl %ebx, _ZN5utils1NE(%rip)
jle .L90
.L89:
cmpl $1000000, 0(%rbp,%rbx,4)
jle .L95
movl $1000000, 0(%rbp,%rbx,4)
.L95:
movl 0(%rbp,%rbx,4), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
jmp .L120
.L88:
leaq 16(%rsp), %rdi
movl $21, %edx
leaq .LC7(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %rbx
testq %rbx, %rbx
je .L121
cmpb $0, 56(%rbx)
je .L101
movzbl 67(%rbx), %esi
.L102:
movsbl %sil, %esi
leaq 16(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L122
.L121:
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L123
call _ZSt16__throw_bad_castv@PLT
.L110:
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L107
call __stack_chk_fail@PLT
.L123:
call __stack_chk_fail@PLT
.L101:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L102
.L122:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L98:
leaq 24(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE15:
testq %rax, %rax
je .L124
.L103:
leaq 24+_ZTVSt14basic_ofstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 264(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 24(%rsp)
leaq 24(%rsp), %rdi
.LEHB16:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE16:
jmp .L105
.L124:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
.LEHB17:
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.LEHE17:
jmp .L103
.L114:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L105:
leaq 128(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 24(%rsp)
leaq 80(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r13, 16(%rsp)
movq -24(%r13), %rax
movq %r14, 16(%rsp,%rax)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 264(%rsp)
leaq 264(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L125
movl $0, %eax
addq $544, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L107:
.cfi_restore_state
movq %rbx, %rdi
.LEHB18:
call _Unwind_Resume@PLT
.LEHE18:
.L125:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4296:
.section .gcc_except_table
.align 4
.LLSDA4296:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4296-.LLSDATTD4296
.LLSDATTD4296:
.byte 0x1
.uleb128 .LLSDACSE4296-.LLSDACSB4296
.LLSDACSB4296:
.uleb128 .LEHB10-.LFB4296
.uleb128 .LEHE10-.LEHB10
.uleb128 .L111-.LFB4296
.uleb128 0
.uleb128 .LEHB11-.LFB4296
.uleb128 .LEHE11-.LEHB11
.uleb128 .L112-.LFB4296
.uleb128 0
.uleb128 .LEHB12-.LFB4296
.uleb128 .LEHE12-.LEHB12
.uleb128 .L113-.LFB4296
.uleb128 0
.uleb128 .LEHB13-.LFB4296
.uleb128 .LEHE13-.LEHB13
.uleb128 .L110-.LFB4296
.uleb128 0
.uleb128 .LEHB14-.LFB4296
.uleb128 .LEHE14-.LEHB14
.uleb128 0
.uleb128 0
.uleb128 .LEHB15-.LFB4296
.uleb128 .LEHE15-.LEHB15
.uleb128 .L110-.LFB4296
.uleb128 0
.uleb128 .LEHB16-.LFB4296
.uleb128 .LEHE16-.LEHB16
.uleb128 .L114-.LFB4296
.uleb128 0x1
.uleb128 .LEHB17-.LFB4296
.uleb128 .LEHE17-.LEHB17
.uleb128 .L110-.LFB4296
.uleb128 0
.uleb128 .LEHB18-.LFB4296
.uleb128 .LEHE18-.LEHB18
.uleb128 0
.uleb128 0
.LLSDACSE4296:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4296:
.text
.size _ZN5utils12print_resultEbPi, .-_ZN5utils12print_resultEbPi
.section .rodata.str1.1
.LC8:
.string "INPUT FILE WAS NOT FOUND!"
.section .rodata.str1.8
.align 8
.LC9:
.string "blocksPerGrid or threadsPerBlock WAS NOT FOUND!"
.section .rodata.str1.1
.LC11:
.string "Time(s): "
.text
.globl main
.type main, @function
main:
.LFB4298:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4298
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L144
movq %rsi, %rbx
cmpl $3, %edi
jle .L145
leaq 48(%rsp), %rdx
movq 8(%rsi), %rsi
leaq 64(%rsp), %rdi
.LEHB19:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE19:
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movb $0, 31(%rsp)
movslq _ZN5utils1NE(%rip), %rsi
movl $4, %edi
call calloc@PLT
movq %rax, %rbx
.LEHB20:
call cudaDeviceReset@PLT
.LEHE20:
jmp .L146
.L144:
leaq 48(%rsp), %rdx
leaq 64(%rsp), %rdi
leaq .LC8(%rip), %rsi
.LEHB21:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L147
leaq 64(%rsp), %rdi
.LEHB22:
call _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE22:
.L139:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L133
call __stack_chk_fail@PLT
.L147:
call __stack_chk_fail@PLT
.L145:
leaq 48(%rsp), %rdx
leaq 64(%rsp), %rdi
leaq .LC9(%rip), %rsi
.LEHB23:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE23:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L148
leaq 64(%rsp), %rdi
.LEHB24:
call _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.LEHE24:
.L140:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L135
call __stack_chk_fail@PLT
.L148:
call __stack_chk_fail@PLT
.L146:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 31(%rsp), %r9
movq %rbx, %r8
movq _ZN5utils3matE(%rip), %rcx
movl _ZN5utils1NE(%rip), %edx
movl %ebp, %esi
movl %r12d, %edi
.LEHB25:
call _Z12bellman_fordiiiPiS_Pb
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L149
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 48(%rsp), %rax
subq 32(%rsp), %rax
imulq $1000000, %rax, %rax
addq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
movss %xmm1, 12(%rsp)
leaq _ZSt4cerr(%rip), %rdi
orl $4, 32+_ZSt4cerr(%rip)
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq $6, 8(%rdi,%rax)
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L150
.L149:
movl $200, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L150:
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
divsd .LC10(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movzbl 31(%rsp), %edi
movq %rbx, %rsi
call _ZN5utils12print_resultEbPi
.LEHE25:
movq %rbx, %rdi
call free@PLT
movq _ZN5utils3matE(%rip), %rdi
call free@PLT
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L151
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L133:
.cfi_restore_state
movq %rbx, %rdi
.LEHB26:
call _Unwind_Resume@PLT
.L135:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L141:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L137
call __stack_chk_fail@PLT
.L137:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE26:
.L151:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4298:
.section .gcc_except_table
.LLSDA4298:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4298-.LLSDACSB4298
.LLSDACSB4298:
.uleb128 .LEHB19-.LFB4298
.uleb128 .LEHE19-.LEHB19
.uleb128 0
.uleb128 0
.uleb128 .LEHB20-.LFB4298
.uleb128 .LEHE20-.LEHB20
.uleb128 .L141-.LFB4298
.uleb128 0
.uleb128 .LEHB21-.LFB4298
.uleb128 .LEHE21-.LEHB21
.uleb128 0
.uleb128 0
.uleb128 .LEHB22-.LFB4298
.uleb128 .LEHE22-.LEHB22
.uleb128 .L139-.LFB4298
.uleb128 0
.uleb128 .LEHB23-.LFB4298
.uleb128 .LEHE23-.LEHB23
.uleb128 0
.uleb128 0
.uleb128 .LEHB24-.LFB4298
.uleb128 .LEHE24-.LEHB24
.uleb128 .L140-.LFB4298
.uleb128 0
.uleb128 .LEHB25-.LFB4298
.uleb128 .LEHE25-.LEHB25
.uleb128 .L141-.LFB4298
.uleb128 0
.uleb128 .LEHB26-.LFB4298
.uleb128 .LEHE26-.LEHB26
.uleb128 0
.uleb128 0
.LLSDACSE4298:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl _ZN5utils3matE
.bss
.align 8
.type _ZN5utils3matE, @object
.size _ZN5utils3matE, 8
_ZN5utils3matE:
.zero 8
.globl _ZN5utils1NE
.align 4
.type _ZN5utils1NE, @object
.size _ZN5utils1NE, 4
_ZN5utils1NE:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1083129856
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* This is a CUDA version of bellman_ford algorithm
* Compile: nvcc -std=c++11 -arch=sm_52 -o cuda_bellman_ford cuda_bellman_ford.cu
* Run: ./cuda_bellman_ford <input file> <number of blocks per grid> <number of threads per block>, you will find the output file 'output.txt'
* */
#include <string>
#include <cassert>
#include <iostream>
#include <fstream>
#include <algorithm>
#include <iomanip>
#include <cstring>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
using std::string;
using std::cout;
using std::endl;
#define INF 1000000
/*
* This is a CHECK function to check CUDA calls
*/
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(1); \
} \
}
/**
* utils is a namespace for utility functions
* including I/O (read input file and print results) and matrix dimension convert(2D->1D) function
*/
namespace utils {
int N; //number of vertices
int *mat; // the adjacency matrix
void abort_with_error_message(string msg) {
std::cerr << msg << endl;
abort();
}
//translate 2-dimension coordinate to 1-dimension
int convert_dimension_2D_1D(int x, int y, int n) {
return x * n + y;
}
int read_file(string filename) {
std::ifstream inputf(filename, std::ifstream::in);
if (!inputf.good()) {
abort_with_error_message("ERROR OCCURRED WHILE READING INPUT FILE");
}
inputf >> N;
//input matrix should be smaller than 20MB * 20MB (400MB, we don't have too much memory for multi-processors)
assert(N < (1024 * 1024 * 20));
mat = (int *) malloc(N * N * sizeof(int));
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++) {
inputf >> mat[convert_dimension_2D_1D(i, j, N)];
}
return 0;
}
int print_result(bool has_negative_cycle, int *dist) {
std::ofstream outputf("output.txt", std::ofstream::out);
if (!has_negative_cycle) {
for (int i = 0; i < N; i++) {
if (dist[i] > INF)
dist[i] = INF;
outputf << dist[i] << '\n';
}
outputf.flush();
} else {
outputf << "FOUND NEGATIVE CYCLE!" << endl;
}
outputf.close();
return 0;
}
}//namespace utils
__global__ void bellman_ford_one_iter(int n, int *d_mat, int *d_dist, bool *d_has_next, int iter_num){
int global_tid = blockDim.x * blockIdx.x + threadIdx.x;
int elementSkip = blockDim.x * gridDim.x;
if(global_tid >= n) return;
for(int u = 0 ; u < n ; u ++){
for(int v = global_tid; v < n; v+= elementSkip){
int weight = d_mat[u * n + v];
if(weight < INF){
int new_dist = d_dist[u] + weight;
if(new_dist < d_dist[v]){
d_dist[v] = new_dist;
*d_has_next = true;
}
}
}
}
}
/**
* Bellman-Ford algorithm. Find the shortest path from vertex 0 to other vertices.
* @param blockPerGrid number of blocks per grid
* @param threadsPerBlock number of threads per block
* @param n input size
* @param *mat input adjacency matrix
* @param *dist distance array
* @param *has_negative_cycle a bool variable to recode if there are negative cycles
*/
void bellman_ford(int blocksPerGrid, int threadsPerBlock, int n, int *mat, int *dist, bool *has_negative_cycle) {
dim3 blocks(blocksPerGrid);
dim3 threads(threadsPerBlock);
int iter_num = 0;
int *d_mat, *d_dist;
bool *d_has_next, h_has_next;
cudaMalloc(&d_mat, sizeof(int) * n * n);
cudaMalloc(&d_dist, sizeof(int) *n);
cudaMalloc(&d_has_next, sizeof(bool));
*has_negative_cycle = false;
for(int i = 0 ; i < n; i ++){
dist[i] = INF;
}
dist[0] = 0;
cudaMemcpy(d_mat, mat, sizeof(int) * n * n, cudaMemcpyHostToDevice);
cudaMemcpy(d_dist, dist, sizeof(int) * n, cudaMemcpyHostToDevice);
for(;;){
h_has_next = false;
cudaMemcpy(d_has_next, &h_has_next, sizeof(bool), cudaMemcpyHostToDevice);
bellman_ford_one_iter<<<blocks, threads>>>(n, d_mat, d_dist, d_has_next, iter_num);
CHECK(cudaDeviceSynchronize());
cudaMemcpy(&h_has_next, d_has_next, sizeof(bool), cudaMemcpyDeviceToHost);
iter_num++;
if(iter_num >= n-1){
*has_negative_cycle = true;
break;
}
if(!h_has_next){
break;
}
}
if(! *has_negative_cycle){
cudaMemcpy(dist, d_dist, sizeof(int) * n, cudaMemcpyDeviceToHost);
}
cudaFree(d_mat);
cudaFree(d_dist);
cudaFree(d_has_next);
}
int main(int argc, char **argv) {
if (argc <= 1) {
utils::abort_with_error_message("INPUT FILE WAS NOT FOUND!");
}
if (argc <= 3) {
utils::abort_with_error_message("blocksPerGrid or threadsPerBlock WAS NOT FOUND!");
}
string filename = argv[1];
int blockPerGrid = atoi(argv[2]);
int threadsPerBlock = atoi(argv[3]);
int *dist;
bool has_negative_cycle = false;
assert(utils::read_file(filename) == 0);
dist = (int *) calloc(sizeof(int), utils::N);
//time counter
timeval start_wall_time_t, end_wall_time_t;
float ms_wall;
cudaDeviceReset();
//start timer
gettimeofday(&start_wall_time_t, nullptr);
//bellman-ford algorithm
bellman_ford(blockPerGrid, threadsPerBlock, utils::N, utils::mat, dist, &has_negative_cycle);
CHECK(cudaDeviceSynchronize());
//end timer
gettimeofday(&end_wall_time_t, nullptr);
ms_wall = ((end_wall_time_t.tv_sec - start_wall_time_t.tv_sec) * 1000 * 1000
+ end_wall_time_t.tv_usec - start_wall_time_t.tv_usec) / 1000.0;
std::cerr.setf(std::ios::fixed);
std::cerr << std::setprecision(6) << "Time(s): " << (ms_wall/1000.0) << endl;
utils::print_result(has_negative_cycle, dist);
free(dist);
free(utils::mat);
return 0;
} | /*
* This is a CUDA version of bellman_ford algorithm
* Compile: nvcc -std=c++11 -arch=sm_52 -o cuda_bellman_ford cuda_bellman_ford.cu
* Run: ./cuda_bellman_ford <input file> <number of blocks per grid> <number of threads per block>, you will find the output file 'output.txt'
* */
#include <string>
#include <cassert>
#include <iostream>
#include <fstream>
#include <algorithm>
#include <iomanip>
#include <cstring>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using std::string;
using std::cout;
using std::endl;
#define INF 1000000
/*
* This is a CHECK function to check CUDA calls
*/
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
/**
* utils is a namespace for utility functions
* including I/O (read input file and print results) and matrix dimension convert(2D->1D) function
*/
namespace utils {
int N; //number of vertices
int *mat; // the adjacency matrix
void abort_with_error_message(string msg) {
std::cerr << msg << endl;
abort();
}
//translate 2-dimension coordinate to 1-dimension
int convert_dimension_2D_1D(int x, int y, int n) {
return x * n + y;
}
int read_file(string filename) {
std::ifstream inputf(filename, std::ifstream::in);
if (!inputf.good()) {
abort_with_error_message("ERROR OCCURRED WHILE READING INPUT FILE");
}
inputf >> N;
//input matrix should be smaller than 20MB * 20MB (400MB, we don't have too much memory for multi-processors)
assert(N < (1024 * 1024 * 20));
mat = (int *) malloc(N * N * sizeof(int));
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++) {
inputf >> mat[convert_dimension_2D_1D(i, j, N)];
}
return 0;
}
int print_result(bool has_negative_cycle, int *dist) {
std::ofstream outputf("output.txt", std::ofstream::out);
if (!has_negative_cycle) {
for (int i = 0; i < N; i++) {
if (dist[i] > INF)
dist[i] = INF;
outputf << dist[i] << '\n';
}
outputf.flush();
} else {
outputf << "FOUND NEGATIVE CYCLE!" << endl;
}
outputf.close();
return 0;
}
}//namespace utils
__global__ void bellman_ford_one_iter(int n, int *d_mat, int *d_dist, bool *d_has_next, int iter_num){
int global_tid = blockDim.x * blockIdx.x + threadIdx.x;
int elementSkip = blockDim.x * gridDim.x;
if(global_tid >= n) return;
for(int u = 0 ; u < n ; u ++){
for(int v = global_tid; v < n; v+= elementSkip){
int weight = d_mat[u * n + v];
if(weight < INF){
int new_dist = d_dist[u] + weight;
if(new_dist < d_dist[v]){
d_dist[v] = new_dist;
*d_has_next = true;
}
}
}
}
}
/**
* Bellman-Ford algorithm. Find the shortest path from vertex 0 to other vertices.
* @param blockPerGrid number of blocks per grid
* @param threadsPerBlock number of threads per block
* @param n input size
* @param *mat input adjacency matrix
* @param *dist distance array
* @param *has_negative_cycle a bool variable to recode if there are negative cycles
*/
void bellman_ford(int blocksPerGrid, int threadsPerBlock, int n, int *mat, int *dist, bool *has_negative_cycle) {
dim3 blocks(blocksPerGrid);
dim3 threads(threadsPerBlock);
int iter_num = 0;
int *d_mat, *d_dist;
bool *d_has_next, h_has_next;
hipMalloc(&d_mat, sizeof(int) * n * n);
hipMalloc(&d_dist, sizeof(int) *n);
hipMalloc(&d_has_next, sizeof(bool));
*has_negative_cycle = false;
for(int i = 0 ; i < n; i ++){
dist[i] = INF;
}
dist[0] = 0;
hipMemcpy(d_mat, mat, sizeof(int) * n * n, hipMemcpyHostToDevice);
hipMemcpy(d_dist, dist, sizeof(int) * n, hipMemcpyHostToDevice);
for(;;){
h_has_next = false;
hipMemcpy(d_has_next, &h_has_next, sizeof(bool), hipMemcpyHostToDevice);
bellman_ford_one_iter<<<blocks, threads>>>(n, d_mat, d_dist, d_has_next, iter_num);
CHECK(hipDeviceSynchronize());
hipMemcpy(&h_has_next, d_has_next, sizeof(bool), hipMemcpyDeviceToHost);
iter_num++;
if(iter_num >= n-1){
*has_negative_cycle = true;
break;
}
if(!h_has_next){
break;
}
}
if(! *has_negative_cycle){
hipMemcpy(dist, d_dist, sizeof(int) * n, hipMemcpyDeviceToHost);
}
hipFree(d_mat);
hipFree(d_dist);
hipFree(d_has_next);
}
int main(int argc, char **argv) {
if (argc <= 1) {
utils::abort_with_error_message("INPUT FILE WAS NOT FOUND!");
}
if (argc <= 3) {
utils::abort_with_error_message("blocksPerGrid or threadsPerBlock WAS NOT FOUND!");
}
string filename = argv[1];
int blockPerGrid = atoi(argv[2]);
int threadsPerBlock = atoi(argv[3]);
int *dist;
bool has_negative_cycle = false;
assert(utils::read_file(filename) == 0);
dist = (int *) calloc(sizeof(int), utils::N);
//time counter
timeval start_wall_time_t, end_wall_time_t;
float ms_wall;
hipDeviceReset();
//start timer
gettimeofday(&start_wall_time_t, nullptr);
//bellman-ford algorithm
bellman_ford(blockPerGrid, threadsPerBlock, utils::N, utils::mat, dist, &has_negative_cycle);
CHECK(hipDeviceSynchronize());
//end timer
gettimeofday(&end_wall_time_t, nullptr);
ms_wall = ((end_wall_time_t.tv_sec - start_wall_time_t.tv_sec) * 1000 * 1000
+ end_wall_time_t.tv_usec - start_wall_time_t.tv_usec) / 1000.0;
std::cerr.setf(std::ios::fixed);
std::cerr << std::setprecision(6) << "Time(s): " << (ms_wall/1000.0) << endl;
utils::print_result(has_negative_cycle, dist);
free(dist);
free(utils::mat);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* This is a CUDA version of bellman_ford algorithm
* Compile: nvcc -std=c++11 -arch=sm_52 -o cuda_bellman_ford cuda_bellman_ford.cu
* Run: ./cuda_bellman_ford <input file> <number of blocks per grid> <number of threads per block>, you will find the output file 'output.txt'
* */
#include <string>
#include <cassert>
#include <iostream>
#include <fstream>
#include <algorithm>
#include <iomanip>
#include <cstring>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using std::string;
using std::cout;
using std::endl;
#define INF 1000000
/*
* This is a CHECK function to check CUDA calls
*/
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
/**
* utils is a namespace for utility functions
* including I/O (read input file and print results) and matrix dimension convert(2D->1D) function
*/
namespace utils {
int N; //number of vertices
int *mat; // the adjacency matrix
void abort_with_error_message(string msg) {
std::cerr << msg << endl;
abort();
}
//translate 2-dimension coordinate to 1-dimension
int convert_dimension_2D_1D(int x, int y, int n) {
return x * n + y;
}
int read_file(string filename) {
std::ifstream inputf(filename, std::ifstream::in);
if (!inputf.good()) {
abort_with_error_message("ERROR OCCURRED WHILE READING INPUT FILE");
}
inputf >> N;
//input matrix should be smaller than 20MB * 20MB (400MB, we don't have too much memory for multi-processors)
assert(N < (1024 * 1024 * 20));
mat = (int *) malloc(N * N * sizeof(int));
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++) {
inputf >> mat[convert_dimension_2D_1D(i, j, N)];
}
return 0;
}
int print_result(bool has_negative_cycle, int *dist) {
std::ofstream outputf("output.txt", std::ofstream::out);
if (!has_negative_cycle) {
for (int i = 0; i < N; i++) {
if (dist[i] > INF)
dist[i] = INF;
outputf << dist[i] << '\n';
}
outputf.flush();
} else {
outputf << "FOUND NEGATIVE CYCLE!" << endl;
}
outputf.close();
return 0;
}
}//namespace utils
__global__ void bellman_ford_one_iter(int n, int *d_mat, int *d_dist, bool *d_has_next, int iter_num){
int global_tid = blockDim.x * blockIdx.x + threadIdx.x;
int elementSkip = blockDim.x * gridDim.x;
if(global_tid >= n) return;
for(int u = 0 ; u < n ; u ++){
for(int v = global_tid; v < n; v+= elementSkip){
int weight = d_mat[u * n + v];
if(weight < INF){
int new_dist = d_dist[u] + weight;
if(new_dist < d_dist[v]){
d_dist[v] = new_dist;
*d_has_next = true;
}
}
}
}
}
/**
* Bellman-Ford algorithm. Find the shortest path from vertex 0 to other vertices.
* @param blockPerGrid number of blocks per grid
* @param threadsPerBlock number of threads per block
* @param n input size
* @param *mat input adjacency matrix
* @param *dist distance array
* @param *has_negative_cycle a bool variable to recode if there are negative cycles
*/
void bellman_ford(int blocksPerGrid, int threadsPerBlock, int n, int *mat, int *dist, bool *has_negative_cycle) {
dim3 blocks(blocksPerGrid);
dim3 threads(threadsPerBlock);
int iter_num = 0;
int *d_mat, *d_dist;
bool *d_has_next, h_has_next;
hipMalloc(&d_mat, sizeof(int) * n * n);
hipMalloc(&d_dist, sizeof(int) *n);
hipMalloc(&d_has_next, sizeof(bool));
*has_negative_cycle = false;
for(int i = 0 ; i < n; i ++){
dist[i] = INF;
}
dist[0] = 0;
hipMemcpy(d_mat, mat, sizeof(int) * n * n, hipMemcpyHostToDevice);
hipMemcpy(d_dist, dist, sizeof(int) * n, hipMemcpyHostToDevice);
for(;;){
h_has_next = false;
hipMemcpy(d_has_next, &h_has_next, sizeof(bool), hipMemcpyHostToDevice);
bellman_ford_one_iter<<<blocks, threads>>>(n, d_mat, d_dist, d_has_next, iter_num);
CHECK(hipDeviceSynchronize());
hipMemcpy(&h_has_next, d_has_next, sizeof(bool), hipMemcpyDeviceToHost);
iter_num++;
if(iter_num >= n-1){
*has_negative_cycle = true;
break;
}
if(!h_has_next){
break;
}
}
if(! *has_negative_cycle){
hipMemcpy(dist, d_dist, sizeof(int) * n, hipMemcpyDeviceToHost);
}
hipFree(d_mat);
hipFree(d_dist);
hipFree(d_has_next);
}
int main(int argc, char **argv) {
if (argc <= 1) {
utils::abort_with_error_message("INPUT FILE WAS NOT FOUND!");
}
if (argc <= 3) {
utils::abort_with_error_message("blocksPerGrid or threadsPerBlock WAS NOT FOUND!");
}
string filename = argv[1];
int blockPerGrid = atoi(argv[2]);
int threadsPerBlock = atoi(argv[3]);
int *dist;
bool has_negative_cycle = false;
assert(utils::read_file(filename) == 0);
dist = (int *) calloc(sizeof(int), utils::N);
//time counter
timeval start_wall_time_t, end_wall_time_t;
float ms_wall;
hipDeviceReset();
//start timer
gettimeofday(&start_wall_time_t, nullptr);
//bellman-ford algorithm
bellman_ford(blockPerGrid, threadsPerBlock, utils::N, utils::mat, dist, &has_negative_cycle);
CHECK(hipDeviceSynchronize());
//end timer
gettimeofday(&end_wall_time_t, nullptr);
ms_wall = ((end_wall_time_t.tv_sec - start_wall_time_t.tv_sec) * 1000 * 1000
+ end_wall_time_t.tv_usec - start_wall_time_t.tv_usec) / 1000.0;
std::cerr.setf(std::ios::fixed);
std::cerr << std::setprecision(6) << "Time(s): " << (ms_wall/1000.0) << endl;
utils::print_result(has_negative_cycle, dist);
free(dist);
free(utils::mat);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21bellman_ford_one_iteriPiS_Pbi
.globl _Z21bellman_ford_one_iteriPiS_Pbi
.p2align 8
.type _Z21bellman_ford_one_iteriPiS_Pbi,@function
_Z21bellman_ford_one_iteriPiS_Pbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s16, s[0:1], 0x0
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s16, v0
s_cbranch_execz .LBB0_8
s_load_b32 s8, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s2
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
s_ashr_i32 s9, s8, 31
s_mov_b32 s2, s3
s_lshl_b64 s[10:11], s[8:9], 2
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v2, s16, v2
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, s16
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_lshl_b64 s[12:13], s[2:3], 2
v_mov_b32_e32 v9, v1
s_add_u32 s12, s6, s12
s_addc_u32 s13, s7, s13
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_mov_b64 s[14:15], 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v9, s8, v9
s_add_u32 s14, s14, s10
s_addc_u32 s15, s15, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s16, v9
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_2
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v7, s14
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v8, vcc_lo
s_mov_b32 s17, exec_lo
global_load_b32 v10, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0xf4240, v10
s_cbranch_execz .LBB0_4
v_add_co_u32 v3, vcc_lo, v5, s14
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v6, vcc_lo
s_clause 0x1
global_load_b32 v11, v0, s[12:13]
global_load_b32 v12, v[3:4], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v10, v11, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v10, v12
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v11, 1
global_store_b32 v[3:4], v10, off
global_store_b8 v0, v11, s[0:1]
s_branch .LBB0_4
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21bellman_ford_one_iteriPiS_Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21bellman_ford_one_iteriPiS_Pbi, .Lfunc_end0-_Z21bellman_ford_one_iteriPiS_Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21bellman_ford_one_iteriPiS_Pbi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z21bellman_ford_one_iteriPiS_Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* This is a CUDA version of bellman_ford algorithm
* Compile: nvcc -std=c++11 -arch=sm_52 -o cuda_bellman_ford cuda_bellman_ford.cu
* Run: ./cuda_bellman_ford <input file> <number of blocks per grid> <number of threads per block>, you will find the output file 'output.txt'
* */
#include <string>
#include <cassert>
#include <iostream>
#include <fstream>
#include <algorithm>
#include <iomanip>
#include <cstring>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using std::string;
using std::cout;
using std::endl;
#define INF 1000000
/*
* This is a CHECK function to check CUDA calls
*/
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(1); \
} \
}
/**
* utils is a namespace for utility functions
* including I/O (read input file and print results) and matrix dimension convert(2D->1D) function
*/
namespace utils {
int N; //number of vertices
int *mat; // the adjacency matrix
void abort_with_error_message(string msg) {
std::cerr << msg << endl;
abort();
}
//translate 2-dimension coordinate to 1-dimension
int convert_dimension_2D_1D(int x, int y, int n) {
return x * n + y;
}
int read_file(string filename) {
std::ifstream inputf(filename, std::ifstream::in);
if (!inputf.good()) {
abort_with_error_message("ERROR OCCURRED WHILE READING INPUT FILE");
}
inputf >> N;
//input matrix should be smaller than 20MB * 20MB (400MB, we don't have too much memory for multi-processors)
assert(N < (1024 * 1024 * 20));
mat = (int *) malloc(N * N * sizeof(int));
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++) {
inputf >> mat[convert_dimension_2D_1D(i, j, N)];
}
return 0;
}
int print_result(bool has_negative_cycle, int *dist) {
std::ofstream outputf("output.txt", std::ofstream::out);
if (!has_negative_cycle) {
for (int i = 0; i < N; i++) {
if (dist[i] > INF)
dist[i] = INF;
outputf << dist[i] << '\n';
}
outputf.flush();
} else {
outputf << "FOUND NEGATIVE CYCLE!" << endl;
}
outputf.close();
return 0;
}
}//namespace utils
__global__ void bellman_ford_one_iter(int n, int *d_mat, int *d_dist, bool *d_has_next, int iter_num){
int global_tid = blockDim.x * blockIdx.x + threadIdx.x;
int elementSkip = blockDim.x * gridDim.x;
if(global_tid >= n) return;
for(int u = 0 ; u < n ; u ++){
for(int v = global_tid; v < n; v+= elementSkip){
int weight = d_mat[u * n + v];
if(weight < INF){
int new_dist = d_dist[u] + weight;
if(new_dist < d_dist[v]){
d_dist[v] = new_dist;
*d_has_next = true;
}
}
}
}
}
/**
* Bellman-Ford algorithm. Find the shortest path from vertex 0 to other vertices.
* @param blockPerGrid number of blocks per grid
* @param threadsPerBlock number of threads per block
* @param n input size
* @param *mat input adjacency matrix
* @param *dist distance array
* @param *has_negative_cycle a bool variable to recode if there are negative cycles
*/
void bellman_ford(int blocksPerGrid, int threadsPerBlock, int n, int *mat, int *dist, bool *has_negative_cycle) {
dim3 blocks(blocksPerGrid);
dim3 threads(threadsPerBlock);
int iter_num = 0;
int *d_mat, *d_dist;
bool *d_has_next, h_has_next;
hipMalloc(&d_mat, sizeof(int) * n * n);
hipMalloc(&d_dist, sizeof(int) *n);
hipMalloc(&d_has_next, sizeof(bool));
*has_negative_cycle = false;
for(int i = 0 ; i < n; i ++){
dist[i] = INF;
}
dist[0] = 0;
hipMemcpy(d_mat, mat, sizeof(int) * n * n, hipMemcpyHostToDevice);
hipMemcpy(d_dist, dist, sizeof(int) * n, hipMemcpyHostToDevice);
for(;;){
h_has_next = false;
hipMemcpy(d_has_next, &h_has_next, sizeof(bool), hipMemcpyHostToDevice);
bellman_ford_one_iter<<<blocks, threads>>>(n, d_mat, d_dist, d_has_next, iter_num);
CHECK(hipDeviceSynchronize());
hipMemcpy(&h_has_next, d_has_next, sizeof(bool), hipMemcpyDeviceToHost);
iter_num++;
if(iter_num >= n-1){
*has_negative_cycle = true;
break;
}
if(!h_has_next){
break;
}
}
if(! *has_negative_cycle){
hipMemcpy(dist, d_dist, sizeof(int) * n, hipMemcpyDeviceToHost);
}
hipFree(d_mat);
hipFree(d_dist);
hipFree(d_has_next);
}
int main(int argc, char **argv) {
if (argc <= 1) {
utils::abort_with_error_message("INPUT FILE WAS NOT FOUND!");
}
if (argc <= 3) {
utils::abort_with_error_message("blocksPerGrid or threadsPerBlock WAS NOT FOUND!");
}
string filename = argv[1];
int blockPerGrid = atoi(argv[2]);
int threadsPerBlock = atoi(argv[3]);
int *dist;
bool has_negative_cycle = false;
assert(utils::read_file(filename) == 0);
dist = (int *) calloc(sizeof(int), utils::N);
//time counter
timeval start_wall_time_t, end_wall_time_t;
float ms_wall;
hipDeviceReset();
//start timer
gettimeofday(&start_wall_time_t, nullptr);
//bellman-ford algorithm
bellman_ford(blockPerGrid, threadsPerBlock, utils::N, utils::mat, dist, &has_negative_cycle);
CHECK(hipDeviceSynchronize());
//end timer
gettimeofday(&end_wall_time_t, nullptr);
ms_wall = ((end_wall_time_t.tv_sec - start_wall_time_t.tv_sec) * 1000 * 1000
+ end_wall_time_t.tv_usec - start_wall_time_t.tv_usec) / 1000.0;
std::cerr.setf(std::ios::fixed);
std::cerr << std::setprecision(6) << "Time(s): " << (ms_wall/1000.0) << endl;
utils::print_result(has_negative_cycle, dist);
free(dist);
free(utils::mat);
return 0;
} | .text
.file "cuda_bellman_ford.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rdi, %rsi
movl $_ZSt4cerr, %edi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
callq abort
.Lfunc_end0:
.size _ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end0-_ZN5utils24abort_with_error_messageENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
# -- End function
.globl _ZN5utils23convert_dimension_2D_1DEiii # -- Begin function _ZN5utils23convert_dimension_2D_1DEiii
.p2align 4, 0x90
.type _ZN5utils23convert_dimension_2D_1DEiii,@function
_ZN5utils23convert_dimension_2D_1DEiii: # @_ZN5utils23convert_dimension_2D_1DEiii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
imull %edx, %edi
leal (%rdi,%rsi), %eax
retq
.Lfunc_end1:
.size _ZN5utils23convert_dimension_2D_1DEiii, .Lfunc_end1-_ZN5utils23convert_dimension_2D_1DEiii
.cfi_endproc
# -- End function
.globl _ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.p2align 4, 0x90
.type _ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $560, %rsp # imm = 0x230
.cfi_def_cfa_offset 592
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rsi
leaq 40(%rsp), %rdi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode
movq 40(%rsp), %rax
movq -24(%rax), %rax
cmpl $0, 72(%rsp,%rax)
jne .LBB2_1
# %bb.9:
.Ltmp8:
leaq 40(%rsp), %rdi
movl $_ZN5utils1NE, %esi
callq _ZNSirsERi
.Ltmp9:
# %bb.10:
movl _ZN5utils1NE(%rip), %ebx
movl %ebx, %edi
imull %edi, %edi
shlq $2, %rdi
callq malloc
movq %rax, _ZN5utils3matE(%rip)
testl %ebx, %ebx
jle .LBB2_17
# %bb.11: # %.preheader.preheader
xorl %r14d, %r14d
leaq 40(%rsp), %rbx
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_16: # %._crit_edge
# in Loop: Header=BB2_12 Depth=1
incl %r14d
cmpl _ZN5utils1NE(%rip), %r14d
jge .LBB2_17
.LBB2_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
movl _ZN5utils1NE(%rip), %eax
testl %eax, %eax
jle .LBB2_16
# %bb.13: # %.lr.ph.preheader
# in Loop: Header=BB2_12 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_14: # %.lr.ph
# Parent Loop BB2_12 Depth=1
# => This Inner Loop Header: Depth=2
imull %r14d, %eax
movslq %eax, %rsi
addq %r15, %rsi
shlq $2, %rsi
addq _ZN5utils3matE(%rip), %rsi
.Ltmp11:
movq %rbx, %rdi
callq _ZNSirsERi
.Ltmp12:
# %bb.15: # in Loop: Header=BB2_14 Depth=2
movl _ZN5utils1NE(%rip), %eax
incq %r15
cmpl %eax, %r15d
jl .LBB2_14
jmp .LBB2_16
.LBB2_17: # %._crit_edge25
leaq 40(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 296(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $560, %rsp # imm = 0x230
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.cfi_def_cfa_offset 592
leaq 24(%rsp), %r14
movq %r14, 8(%rsp)
.Ltmp0:
movl $40, %edi
callq _Znwm
.Ltmp1:
# %bb.2: # %.noexc16
movq %rax, 8(%rsp)
movq $39, 24(%rsp)
movups .L.str+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str(%rip), %xmm0
movups %xmm0, (%rax)
movabsq $4993446652385973584, %rcx # imm = 0x454C494620545550
movq %rcx, 31(%rax)
movq $39, 16(%rsp)
movb $0, 39(%rax)
.Ltmp3:
movl $_ZSt4cerr, %edi
movl $39, %edx
movq %rax, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp4:
# %bb.3: # %.noexc17
.Ltmp5:
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp6:
# %bb.4: # %.noexc18
callq abort
.LBB2_7:
.Ltmp7:
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.8: # %.critedge.i.i19
callq _ZdlPv
jmp .LBB2_20
.LBB2_6:
.Ltmp2:
jmp .LBB2_19
.LBB2_5:
.Ltmp10:
jmp .LBB2_19
.LBB2_18:
.Ltmp13:
.LBB2_19: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit21
movq %rax, %rbx
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit21
leaq 40(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 296(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end2-_ZN5utils9read_fileENSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp8-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp8
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Lfunc_end2-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _ZN5utils12print_resultEbPi # -- Begin function _ZN5utils12print_resultEbPi
.p2align 4, 0x90
.type _ZN5utils12print_resultEbPi,@function
_ZN5utils12print_resultEbPi: # @_ZN5utils12print_resultEbPi
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 576
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movl %edi, %ebp
leaq 16(%rsp), %rbx
movl $.L.str.1, %esi
movq %rbx, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
testl %ebp, %ebp
je .LBB3_1
# %bb.11:
.Ltmp21:
leaq 16(%rsp), %rdi
movl $.L.str.2, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp22:
# %bb.12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq 16(%rsp), %rax
movq -24(%rax), %rax
movq 256(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB3_13
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_17
# %bb.16:
movzbl 67(%rbx), %eax
jmp .LBB3_19
.LBB3_1: # %.preheader
cmpl $0, _ZN5utils1NE(%rip)
jle .LBB3_21
# %bb.2: # %.lr.ph.preheader
xorl %r12d, %r12d
leaq 16(%rsp), %rbx
leaq 15(%rsp), %r15
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_3 Depth=1
.Ltmp18:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp19:
.LBB3_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB3_3 Depth=1
incq %r12
movslq _ZN5utils1NE(%rip), %rax
cmpq %rax, %r12
jge .LBB3_21
.LBB3_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpl $1000001, (%r14,%r12,4) # imm = 0xF4241
jl .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl $1000000, (%r14,%r12,4) # imm = 0xF4240
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
movl (%r14,%r12,4), %esi
.Ltmp14:
movq %rbx, %rdi
callq _ZNSolsEi
.Ltmp15:
# %bb.6: # in Loop: Header=BB3_3 Depth=1
movb $10, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB3_8
# %bb.7: # in Loop: Header=BB3_3 Depth=1
.Ltmp16:
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
jmp .LBB3_9
.LBB3_17:
.Ltmp23:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp24:
# %bb.18: # %.noexc20
movq (%rbx), %rax
.Ltmp25:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp26:
.LBB3_19: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp27:
movsbl %al, %esi
leaq 16(%rsp), %rdi
callq _ZNSo3putEc
.Ltmp28:
# %bb.20:
movq %rax, %rbx
.LBB3_21: # %.noexc22.invoke
.Ltmp29:
movq %rbx, %rdi
callq _ZNSo5flushEv
.Ltmp30:
# %bb.22: # %_ZNSolsEPFRSoS_E.exit
leaq 24(%rsp), %rdi
.Ltmp31:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp32:
# %bb.23: # %.noexc17
testq %rax, %rax
jne .LBB3_25
# %bb.24:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $16, %rdi
movl 48(%rsp,%rax), %esi
orl $4, %esi
.Ltmp33:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp34:
.LBB3_25: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
leaq 16(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_13:
.cfi_def_cfa_offset 576
.Ltmp35:
callq _ZSt16__throw_bad_castv
.Ltmp36:
# %bb.14: # %.noexc19
.LBB3_10:
.Ltmp37:
jmp .LBB3_27
.LBB3_26:
.Ltmp20:
.LBB3_27:
movq %rax, %rbx
leaq 16(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _ZN5utils12print_resultEbPi, .Lfunc_end3-_ZN5utils12print_resultEbPi
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp21-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp21
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp37-.Lfunc_begin1 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp17-.Ltmp18 # Call between .Ltmp18 and .Ltmp17
.uleb128 .Ltmp20-.Lfunc_begin1 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp36-.Ltmp23 # Call between .Ltmp23 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin1 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp36 # Call between .Ltmp36 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.text
.globl _Z36__device_stub__bellman_ford_one_iteriPiS_Pbi # -- Begin function _Z36__device_stub__bellman_ford_one_iteriPiS_Pbi
.p2align 4, 0x90
.type _Z36__device_stub__bellman_ford_one_iteriPiS_Pbi,@function
_Z36__device_stub__bellman_ford_one_iteriPiS_Pbi: # @_Z36__device_stub__bellman_ford_one_iteriPiS_Pbi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
movl %r8d, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21bellman_ford_one_iteriPiS_Pbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z36__device_stub__bellman_ford_one_iteriPiS_Pbi, .Lfunc_end4-_Z36__device_stub__bellman_ford_one_iteriPiS_Pbi
.cfi_endproc
# -- End function
.globl _Z12bellman_fordiiiPiS_Pb # -- Begin function _Z12bellman_fordiiiPiS_Pb
.p2align 4, 0x90
.type _Z12bellman_fordiiiPiS_Pb,@function
_Z12bellman_fordiiiPiS_Pb: # @_Z12bellman_fordiiiPiS_Pb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r12
movq %r8, %rbx
movq %rcx, 80(%rsp) # 8-byte Spill
# kill: def $edx killed $edx def $rdx
movl %edi, %eax
movq %rax, 72(%rsp) # 8-byte Spill
movl %esi, %ebp
movq %rdx, 32(%rsp) # 8-byte Spill
movslq %edx, %r13
leaq (,%r13,4), %r15
movq %r15, %r14
imulq %r13, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, 56(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1, %esi
callq hipMalloc
movq %r12, 64(%rsp) # 8-byte Spill
movb $0, (%r12)
testl %r13d, %r13d
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl 32(%rsp), %eax # 4-byte Reload
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1000000, (%rbx,%rcx,4) # imm = 0xF4240
incq %rcx
cmpq %rcx, %rax
jne .LBB5_2
.LBB5_3: # %._crit_edge
movabsq $4294967296, %rax # imm = 0x100000000
addq %rax, 72(%rsp) # 8-byte Folded Spill
orq %rax, %rbp
movl $0, (%rbx)
movq 40(%rsp), %rdi
movl $1, %r13d
movq 80(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq 56(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rax # 8-byte Reload
leal -1(%rax), %r12d
cmpl $2, %r12d
cmovll %r13d, %r12d
decl %r12d
xorl %r13d, %r13d
leaq 15(%rsp), %r14
.p2align 4, 0x90
.LBB5_4: # =>This Inner Loop Header: Depth=1
movb $0, 15(%rsp)
movq 16(%rsp), %rdi
movl $1, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=1
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi # 8-byte Reload
movl %esi, 52(%rsp)
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %r13d, 48(%rsp)
leaq 52(%rsp), %rax
movq %rax, 160(%rsp)
leaq 152(%rsp), %rax
movq %rax, 168(%rsp)
leaq 144(%rsp), %rax
movq %rax, 176(%rsp)
leaq 136(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z21bellman_ford_one_iteriPiS_Pbi, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_6: # in Loop: Header=BB5_4 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_13
# %bb.7: # in Loop: Header=BB5_4 Depth=1
movq 16(%rsp), %rsi
movl $1, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl %r13d, %r12d
je .LBB5_8
# %bb.9: # in Loop: Header=BB5_4 Depth=1
incl %r13d
cmpb $0, 15(%rsp)
jne .LBB5_4
jmp .LBB5_10
.LBB5_8:
movq 64(%rsp), %rax # 8-byte Reload
movb $1, (%rax)
.LBB5_10: # %.loopexit
movq 64(%rsp), %rax # 8-byte Reload
cmpb $0, (%rax)
jne .LBB5_12
# %bb.11:
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
.LBB5_12:
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_13:
.cfi_def_cfa_offset 256
movl %eax, %r15d
movq stderr(%rip), %rdi
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movl $150, %ecx
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
movl %r15d, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movl %r15d, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end5:
.size _Z12bellman_fordiiiPiS_Pb, .Lfunc_end5-_Z12bellman_fordiiiPiS_Pb
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB6_1
# %bb.6:
cmpl $3, %edi
jle .LBB6_7
# %bb.10:
movq %rsi, %rbx
movq 8(%rsi), %r14
leaq 24(%rsp), %r12
movq %r12, 8(%rsp)
testq %r14, %r14
je .LBB6_11
# %bb.13:
movq %r14, %rdi
callq strlen
movq %rax, %r15
cmpq $16, %rax
jb .LBB6_22
# %bb.14:
testq %r15, %r15
js .LBB6_15
# %bb.17:
movq %r15, %rdi
incq %rdi
js .LBB6_18
# %bb.20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i52
.Ltmp38:
callq _Znwm
.Ltmp39:
# %bb.21: # %.noexc58
movq %rax, 8(%rsp)
movq %r15, 24(%rsp)
.LBB6_22:
testq %r15, %r15
je .LBB6_26
# %bb.23:
movq 8(%rsp), %rdi
cmpq $1, %r15
jne .LBB6_25
# %bb.24:
movzbl (%r14), %eax
movb %al, (%rdi)
jmp .LBB6_26
.LBB6_25:
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB6_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit59
movq %r15, 16(%rsp)
movq 8(%rsp), %rax
movb $0, (%rax,%r15)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movb $0, 7(%rsp)
movslq _ZN5utils1NE(%rip), %rsi
movl $4, %edi
callq calloc
movq %rax, %rbx
.Ltmp40:
callq hipDeviceReset
.Ltmp41:
# %bb.27:
leaq 56(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl _ZN5utils1NE(%rip), %edx
movq _ZN5utils3matE(%rip), %rcx
.Ltmp42:
leaq 7(%rsp), %r9
movl %r14d, %edi
movl %r15d, %esi
movq %rbx, %r8
callq _Z12bellman_fordiiiPiS_Pb
.Ltmp43:
# %bb.28:
.Ltmp44:
callq hipDeviceSynchronize
.Ltmp45:
# %bb.29:
testl %eax, %eax
jne .LBB6_30
# %bb.34:
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %r15
movq 48(%rsp), %r14
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rcx
orl $4, _ZSt4cerr+24(%rcx)
movq 56(%rsp), %rbp
movq 64(%rsp), %r13
movq -24(%rax), %rax
movq $6, _ZSt4cerr+8(%rax)
.Ltmp49:
movl $_ZSt4cerr, %edi
movl $.L.str.8, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp50:
# %bb.35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
subq %rbp, %r15
imulq $1000000, %r15, %rax # imm = 0xF4240
addq %r14, %rax
subq %r13, %rax
cvtsi2sd %rax, %xmm0
movsd .LCPI6_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
.Ltmp51:
movl $_ZSt4cerr, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp52:
# %bb.36: # %_ZNSolsEd.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB6_37
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB6_41
# %bb.40:
movzbl 67(%r15), %eax
jmp .LBB6_43
.LBB6_41:
.Ltmp53:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp54:
# %bb.42: # %.noexc73
movq (%r15), %rax
.Ltmp55:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp56:
.LBB6_43: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp57:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp58:
# %bb.44: # %.noexc75
.Ltmp59:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp60:
# %bb.45: # %_ZNSolsEPFRSoS_E.exit
movzbl 7(%rsp), %edi
.Ltmp61:
movq %rbx, %rsi
callq _ZN5utils12print_resultEbPi
.Ltmp62:
# %bb.46:
movq %rbx, %rdi
callq free
movq _ZN5utils3matE(%rip), %rdi
callq free
movq 8(%rsp), %rdi
cmpq %r12, %rdi
je .LBB6_48
# %bb.47: # %.critedge.i.i63
callq _ZdlPv
.LBB6_48: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit65
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_30:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rdi
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movl $200, %ecx
movl %eax, %ebp
xorl %eax, %eax
callq fprintf
movq stderr(%rip), %rbx
.Ltmp46:
movl %ebp, %edi
callq hipGetErrorString
.Ltmp47:
# %bb.31:
movl $.L.str.5, %esi
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB6_18: # %.noexc11.i53
.Ltmp66:
callq _ZSt17__throw_bad_allocv
.Ltmp67:
# %bb.19: # %.noexc57
.LBB6_1: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
leaq 120(%rsp), %r14
movq %r14, 104(%rsp)
movl $26, %edi
callq _Znwm
movq %rax, 104(%rsp)
movq $25, 120(%rsp)
movups .L.str.6(%rip), %xmm0
movups %xmm0, (%rax)
movupd .L.str.6+9(%rip), %xmm0
movupd %xmm0, 9(%rax)
movq $25, 112(%rsp)
movb $0, 25(%rax)
.Ltmp78:
movl $_ZSt4cerr, %edi
movl $25, %edx
movq %rax, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp79:
# %bb.2: # %.noexc31
.Ltmp80:
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp81:
jmp .LBB6_3
.LBB6_7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i36
leaq 88(%rsp), %r14
movq %r14, 72(%rsp)
movl $48, %edi
callq _Znwm
movq %rax, 72(%rsp)
movq $47, 88(%rsp)
movups .L.str.7(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.7+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movupd .L.str.7+31(%rip), %xmm0
movupd %xmm0, 31(%rax)
movq $47, 80(%rsp)
movb $0, 47(%rax)
.Ltmp73:
movl $_ZSt4cerr, %edi
movl $47, %edx
movq %rax, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp74:
# %bb.8: # %.noexc43
.Ltmp75:
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp76:
.LBB6_3: # %.noexc32
callq abort
.LBB6_11:
.Ltmp70:
movl $.L.str.9, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp71:
# %bb.12: # %.noexc55
.LBB6_37:
.Ltmp63:
callq _ZSt16__throw_bad_castv
.Ltmp64:
# %bb.38: # %.noexc72
.LBB6_15: # %.noexc.i54
.Ltmp68:
movl $.L.str.10, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp69:
# %bb.16: # %.noexc56
.LBB6_9:
.Ltmp77:
movq %rax, %rbx
movq 72(%rsp), %rdi
jmp .LBB6_5
.LBB6_4:
.Ltmp82:
movq %rax, %rbx
movq 104(%rsp), %rdi
.LBB6_5:
cmpq %r14, %rdi
jne .LBB6_51
jmp .LBB6_52
.LBB6_49:
.Ltmp65:
jmp .LBB6_50
.LBB6_32:
.Ltmp72:
movq %rax, %rdi
callq _Unwind_Resume@PLT
.LBB6_33:
.Ltmp48:
.LBB6_50:
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r12, %rdi
je .LBB6_52
.LBB6_51: # %.critedge.i.i66
callq _ZdlPv
.LBB6_52: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit35
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table6:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp38-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp72-.Lfunc_begin2 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp43-.Ltmp40 # Call between .Ltmp40 and .Ltmp43
.uleb128 .Ltmp65-.Lfunc_begin2 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp45-.Ltmp44 # Call between .Ltmp44 and .Ltmp45
.uleb128 .Ltmp48-.Lfunc_begin2 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp62-.Ltmp49 # Call between .Ltmp49 and .Ltmp62
.uleb128 .Ltmp65-.Lfunc_begin2 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp46-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Ltmp47-.Ltmp46 # Call between .Ltmp46 and .Ltmp47
.uleb128 .Ltmp48-.Lfunc_begin2 # jumps to .Ltmp48
.byte 0 # On action: cleanup
.uleb128 .Ltmp66-.Lfunc_begin2 # >> Call Site 7 <<
.uleb128 .Ltmp67-.Ltmp66 # Call between .Ltmp66 and .Ltmp67
.uleb128 .Ltmp72-.Lfunc_begin2 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp67-.Lfunc_begin2 # >> Call Site 8 <<
.uleb128 .Ltmp78-.Ltmp67 # Call between .Ltmp67 and .Ltmp78
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp78-.Lfunc_begin2 # >> Call Site 9 <<
.uleb128 .Ltmp81-.Ltmp78 # Call between .Ltmp78 and .Ltmp81
.uleb128 .Ltmp82-.Lfunc_begin2 # jumps to .Ltmp82
.byte 0 # On action: cleanup
.uleb128 .Ltmp81-.Lfunc_begin2 # >> Call Site 10 <<
.uleb128 .Ltmp73-.Ltmp81 # Call between .Ltmp81 and .Ltmp73
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin2 # >> Call Site 11 <<
.uleb128 .Ltmp76-.Ltmp73 # Call between .Ltmp73 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin2 # jumps to .Ltmp77
.byte 0 # On action: cleanup
.uleb128 .Ltmp70-.Lfunc_begin2 # >> Call Site 12 <<
.uleb128 .Ltmp71-.Ltmp70 # Call between .Ltmp70 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin2 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin2 # >> Call Site 13 <<
.uleb128 .Ltmp64-.Ltmp63 # Call between .Ltmp63 and .Ltmp64
.uleb128 .Ltmp65-.Lfunc_begin2 # jumps to .Ltmp65
.byte 0 # On action: cleanup
.uleb128 .Ltmp68-.Lfunc_begin2 # >> Call Site 14 <<
.uleb128 .Ltmp69-.Ltmp68 # Call between .Ltmp68 and .Ltmp69
.uleb128 .Ltmp72-.Lfunc_begin2 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp69-.Lfunc_begin2 # >> Call Site 15 <<
.uleb128 .Lfunc_end6-.Ltmp69 # Call between .Ltmp69 and .Lfunc_end6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21bellman_ford_one_iteriPiS_Pbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN5utils1NE,@object # @_ZN5utils1NE
.bss
.globl _ZN5utils1NE
.p2align 2, 0x0
_ZN5utils1NE:
.long 0 # 0x0
.size _ZN5utils1NE, 4
.type _ZN5utils3matE,@object # @_ZN5utils3matE
.globl _ZN5utils3matE
.p2align 3, 0x0
_ZN5utils3matE:
.quad 0
.size _ZN5utils3matE, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ERROR OCCURRED WHILE READING INPUT FILE"
.size .L.str, 40
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "output.txt"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "FOUND NEGATIVE CYCLE!"
.size .L.str.2, 22
.type _Z21bellman_ford_one_iteriPiS_Pbi,@object # @_Z21bellman_ford_one_iteriPiS_Pbi
.section .rodata,"a",@progbits
.globl _Z21bellman_ford_one_iteriPiS_Pbi
.p2align 3, 0x0
_Z21bellman_ford_one_iteriPiS_Pbi:
.quad _Z36__device_stub__bellman_ford_one_iteriPiS_Pbi
.size _Z21bellman_ford_one_iteriPiS_Pbi, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Error: %s:%d, "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/qiansunn/BellmanFord/master/cuda_bellman_ford.hip"
.size .L.str.4, 107
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "code: %d, reason: %s\n"
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "INPUT FILE WAS NOT FOUND!"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "blocksPerGrid or threadsPerBlock WAS NOT FOUND!"
.size .L.str.7, 48
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Time(s): "
.size .L.str.8, 10
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "basic_string: construction from null is not valid"
.size .L.str.9, 50
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "basic_string::_M_create"
.size .L.str.10, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21bellman_ford_one_iteriPiS_Pbi"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z36__device_stub__bellman_ford_one_iteriPiS_Pbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZN5utils1NE
.addrsig_sym _ZSt4cerr
.addrsig_sym _Z21bellman_ford_one_iteriPiS_Pbi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21bellman_ford_one_iteriPiS_Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], !P0 ; /* 0x0000580000007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x000fe20000000f00 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*00a0*/ MOV R17, 0x4 ; /* 0x0000000400117802 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0xc], RZ ; /* 0x0000030003037a24 */
/* 0x000fe400078e02ff */
/*00d0*/ IMAD.WIDE R16, R0, R17, c[0x0][0x170] ; /* 0x00005c0000107625 */
/* 0x000fe400078e0211 */
/*00e0*/ I2F.U32.RP R7, R3 ; /* 0x0000000300077306 */
/* 0x000e220000209000 */
/*00f0*/ ISETP.NE.U32.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f45070 */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x000fc400078e0a03 */
/*0110*/ IMAD.IADD R2, R0, 0x1, R3 ; /* 0x0000000100027824 */
/* 0x000fe400078e0203 */
/*0120*/ IMAD.WIDE R14, R3, 0x4, R16 ; /* 0x00000004030e7825 */
/* 0x000fc600078e0210 */
/*0130*/ LOP3.LUT R6, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff067212 */
/* 0x000fc600078e33ff */
/*0140*/ IMAD.WIDE R12, R3, 0x4, R14 ; /* 0x00000004030c7825 */
/* 0x000fe200078e020e */
/*0150*/ IADD3 R6, R6, c[0x0][0x160], R3 ; /* 0x0000580006067a10 */
/* 0x000fe20007ffe003 */
/*0160*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0170*/ IADD3 R5, R7, 0xffffffe, RZ ; /* 0x0ffffffe07057810 */
/* 0x001fcc0007ffe0ff */
/*0180*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*0190*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x001fc800078e02ff */
/*01a0*/ IMAD.HI.U32 R9, R5, R9, R4 ; /* 0x0000000905097227 */
/* 0x000fc800078e0004 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.HI.U32 R4, R9, R6, RZ ; /* 0x0000000609047227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R7, RZ, RZ, -R4 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a04 */
/*01e0*/ IMAD R6, R3, R7, R6 ; /* 0x0000000703067224 */
/* 0x000fca00078e0206 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f06070 */
/*0200*/ @P0 IMAD.IADD R6, R6, 0x1, -R3 ; /* 0x0000000106060824 */
/* 0x000fe200078e0a03 */
/*0210*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe20003f26070 */
/*0230*/ IMAD.IADD R6, R3, 0x1, R2 ; /* 0x0000000103067824 */
/* 0x000fca00078e0202 */
/*0240*/ IADD3 R7, R3, R6, RZ ; /* 0x0000000603077210 */
/* 0x000fce0007ffe0ff */
/*0250*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0260*/ @!P2 LOP3.LUT R4, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff04a212 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R8, R4, 0x1, RZ ; /* 0x0000000104087810 */
/* 0x000fc80007ffe0ff */
/*0280*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fc800078ec0ff */
/*0290*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*02a0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x4 ; /* 0x00000004ff147424 */
/* 0x001fe200078e00ff */
/*02b0*/ BSSY B0, 0x6a0 ; /* 0x000003e000007945 */
/* 0x000fe20003800000 */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*02d0*/ MOV R26, R0 ; /* 0x00000000001a7202 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.WIDE R10, R5.reuse, R20, c[0x0][0x170] ; /* 0x00005c00050a7625 */
/* 0x040fe200078e0214 */
/*02f0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x160], PT ; /* 0x0000580005007a0c */
/* 0x000fc60003f06270 */
/*0310*/ @!P1 BRA 0x690 ; /* 0x0000037000009947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD R19, R9, c[0x0][0x160], R0 ; /* 0x0000580009137a24 */
/* 0x000fc800078e0200 */
/*0330*/ IMAD.WIDE R18, R19, R20, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0214 */
/*0340*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x000ea2000c1e1900 */
/*0350*/ BSSY B1, 0x430 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0360*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f25270 */
/*0370*/ ISETP.GT.AND P2, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f44270 */
/*0380*/ @P2 BRA 0x420 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x000ee2000c1e1900 */
/*03b0*/ IMAD.IADD R22, R21, 0x1, R18 ; /* 0x0000000115167824 */
/* 0x004fe400078e0212 */
/*03c0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fc600078e00ff */
/*03d0*/ ISETP.GE.AND P2, PT, R22, R19, PT ; /* 0x000000131600720c */
/* 0x008fda0003f46270 */
/*03e0*/ @!P2 MOV R18, c[0x0][0x178] ; /* 0x00005e000012aa02 */
/* 0x000fe20000000f00 */
/*03f0*/ @!P2 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff13a624 */
/* 0x000fe200078e00ff */
/*0400*/ @!P2 STG.E [R16.64], R22 ; /* 0x000000161000a986 */
/* 0x0001e8000c101904 */
/*0410*/ @!P2 STG.E.U8 [R18.64], R21 ; /* 0x000000151200a986 */
/* 0x0001e4000c101104 */
/*0420*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R26, RZ, RZ, R2 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0002 */
/*0440*/ @!P1 BRA 0x690 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R19, R9, c[0x0][0x160], R2 ; /* 0x0000580009137a24 */
/* 0x001fc800078e0202 */
/*0460*/ IMAD.WIDE R18, R19, R20, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0214 */
/*0470*/ LDG.E R21, [R18.64] ; /* 0x0000000412157981 */
/* 0x000ea2000c1e1900 */
/*0480*/ BSSY B1, 0x560 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0490*/ ISETP.NE.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fe40003f25270 */
/*04a0*/ ISETP.GT.AND P2, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f44270 */
/*04b0*/ @P2 BRA 0x550 ; /* 0x0000009000002947 */
/* 0x000fea0003800000 */
/*04c0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000ee2000c1e1900 */
/*04e0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe200078e00ff */
/*04f0*/ IADD3 R21, R21, R18, RZ ; /* 0x0000001215157210 */
/* 0x004fc80007ffe0ff */
/*0500*/ ISETP.GE.AND P2, PT, R21, R19, PT ; /* 0x000000131500720c */
/* 0x008fda0003f46270 */
/*0510*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff12a624 */
/* 0x000fe200078e00ff */
/*0520*/ @!P2 MOV R19, c[0x0][0x17c] ; /* 0x00005f000013aa02 */
/* 0x000fe20000000f00 */
/*0530*/ @!P2 STG.E [R14.64], R21 ; /* 0x000000150e00a986 */
/* 0x0001e8000c101904 */
/*0540*/ @!P2 STG.E.U8 [R18.64], R22 ; /* 0x000000161200a986 */
/* 0x0001e4000c101104 */
/*0550*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.MOV.U32 R26, RZ, RZ, R6 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0006 */
/*0570*/ @!P1 BRA 0x690 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*0580*/ IMAD R21, R9, c[0x0][0x160], R6 ; /* 0x0000580009157a24 */
/* 0x001fc800078e0206 */
/*0590*/ IMAD.WIDE R20, R21, R20, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fcc00078e0214 */
/*05a0*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IMAD.MOV.U32 R26, RZ, RZ, R7 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0007 */
/*05c0*/ ISETP.GT.AND P1, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f24270 */
/*05d0*/ @P1 BRA 0x690 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*05e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ee2000c1e1900 */
/*0600*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R26, R7 ; /* 0x00000007001a7202 */
/* 0x000fe40000000f00 */
/*0620*/ IADD3 R21, R21, R18, RZ ; /* 0x0000001215157210 */
/* 0x004fc80007ffe0ff */
/*0630*/ ISETP.GE.AND P1, PT, R21, R19, PT ; /* 0x000000131500720c */
/* 0x008fda0003f26270 */
/*0640*/ @!P1 MOV R18, c[0x0][0x178] ; /* 0x00005e0000129a02 */
/* 0x000fe20000000f00 */
/*0650*/ @!P1 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff139624 */
/* 0x000fe200078e00ff */
/*0660*/ @!P1 STG.E [R12.64], R21 ; /* 0x000000150c009986 */
/* 0x0001e2000c101904 */
/*0670*/ @!P1 IMAD.MOV.U32 R26, RZ, RZ, R7 ; /* 0x000000ffff1a9224 */
/* 0x000fc600078e0007 */
/*0680*/ @!P1 STG.E.U8 [R18.64], R20 ; /* 0x0000001412009986 */
/* 0x0001e8000c101104 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f26070 */
/*06b0*/ BSSY B0, 0xb90 ; /* 0x000004d000007945 */
/* 0x000fd80003800000 */
/*06c0*/ @!P1 BRA 0xb80 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*06d0*/ HFMA2.MMA R24, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff187435 */
/* 0x001fe200000001ff */
/*06e0*/ IMAD R19, R9, c[0x0][0x160], R26 ; /* 0x0000580009137a24 */
/* 0x001fd200078e021a */
/*06f0*/ IMAD.WIDE R18, R19, R24, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fca00078e0218 */
/*0700*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000ea2000c1e1900 */
/*0710*/ BSSY B1, 0x810 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*0720*/ IMAD.WIDE R20, R3, 0x4, R18 ; /* 0x0000000403147825 */
/* 0x000fe200078e0212 */
/*0730*/ ISETP.GT.AND P1, PT, R25, 0xf423f, PT ; /* 0x000f423f1900780c */
/* 0x004fda0003f24270 */
/*0740*/ @P1 BRA 0x800 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.WIDE R22, R26, R24, c[0x0][0x170] ; /* 0x00005c001a167625 */
/* 0x000fe200078e0218 */
/*0760*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R19, [R22.64] ; /* 0x0000000416137981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.IADD R25, R25, 0x1, R18 ; /* 0x0000000119197824 */
/* 0x004fe200078e0212 */
/*0790*/ MOV R18, 0x1 ; /* 0x0000000100127802 */
/* 0x000fc80000000f00 */
/*07a0*/ ISETP.GE.AND P1, PT, R25, R19, PT ; /* 0x000000131900720c */
/* 0x008fda0003f26270 */
/*07b0*/ @!P1 STG.E [R22.64], R25 ; /* 0x0000001916009986 */
/* 0x0001e2000c101904 */
/*07c0*/ @!P1 MOV R19, c[0x0][0x17c] ; /* 0x00005f0000139a02 */
/* 0x000fe40000000f00 */
/*07d0*/ @!P1 PRMT R23, R18, 0x7610, R23 ; /* 0x0000761012179816 */
/* 0x001fe20000000017 */
/*07e0*/ @!P1 IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff129624 */
/* 0x000fca00078e00ff */
/*07f0*/ @!P1 STG.E.U8 [R18.64], R23 ; /* 0x0000001712009986 */
/* 0x0001e4000c101104 */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0820*/ BSSY B1, 0x930 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*0830*/ IMAD.WIDE R18, R3, 0x4, R20 ; /* 0x0000000403127825 */
/* 0x001fc800078e0214 */
/*0840*/ IMAD.IADD R25, R3, 0x1, R26 ; /* 0x0000000103197824 */
/* 0x000fe200078e021a */
/*0850*/ ISETP.GT.AND P1, PT, R27, 0xf423f, PT ; /* 0x000f423f1b00780c */
/* 0x004fda0003f24270 */
/*0860*/ @P1 BRA 0x920 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.WIDE R22, R25, R24, c[0x0][0x170] ; /* 0x00005c0019167625 */
/* 0x000fe200078e0218 */
/*0880*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x000ee2000c1e1900 */
/*08a0*/ IADD3 R27, R27, R20, RZ ; /* 0x000000141b1b7210 */
/* 0x004fe20007ffe0ff */
/*08b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fc600078e00ff */
/*08c0*/ ISETP.GE.AND P1, PT, R27, R21, PT ; /* 0x000000151b00720c */
/* 0x008fda0003f26270 */
/*08d0*/ @!P1 STG.E [R22.64], R27 ; /* 0x0000001b16009986 */
/* 0x0001e2000c101904 */
/*08e0*/ @!P1 IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff159624 */
/* 0x000fe200078e00ff */
/*08f0*/ @!P1 PRMT R23, R20, 0x7610, R23 ; /* 0x0000761014179816 */
/* 0x001fe40000000017 */
/*0900*/ @!P1 MOV R20, c[0x0][0x178] ; /* 0x00005e0000149a02 */
/* 0x000fca0000000f00 */
/*0910*/ @!P1 STG.E.U8 [R20.64], R23 ; /* 0x0000001714009986 */
/* 0x0001e4000c101104 */
/*0920*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0930*/ LDG.E R27, [R18.64] ; /* 0x00000004121b7981 */
/* 0x000ea2000c1e1900 */
/*0940*/ BSSY B1, 0xa50 ; /* 0x0000010000017945 */
/* 0x000fe20003800000 */
/*0950*/ IMAD.WIDE R20, R3.reuse, 0x4, R18 ; /* 0x0000000403147825 */
/* 0x041fe200078e0212 */
/*0960*/ IADD3 R25, R3, R25, RZ ; /* 0x0000001903197210 */
/* 0x000fe40007ffe0ff */
/*0970*/ ISETP.GT.AND P1, PT, R27, 0xf423f, PT ; /* 0x000f423f1b00780c */
/* 0x004fda0003f24270 */
/*0980*/ @P1 BRA 0xa40 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD.WIDE R18, R25, R24, c[0x0][0x170] ; /* 0x00005c0019127625 */
/* 0x000fe200078e0218 */
/*09a0*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R23, [R18.64] ; /* 0x0000000412177981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.IADD R27, R27, 0x1, R22 ; /* 0x000000011b1b7824 */
/* 0x004fe200078e0216 */
/*09d0*/ HFMA2.MMA R22, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff167435 */
/* 0x000fc800000001ff */
/*09e0*/ ISETP.GE.AND P1, PT, R27, R23, PT ; /* 0x000000171b00720c */
/* 0x008fda0003f26270 */
/*09f0*/ @!P1 STG.E [R18.64], R27 ; /* 0x0000001b12009986 */
/* 0x0001e2000c101904 */
/*0a00*/ @!P1 MOV R23, c[0x0][0x17c] ; /* 0x00005f0000179a02 */
/* 0x000fe40000000f00 */
/*0a10*/ @!P1 PRMT R19, R22, 0x7610, R19 ; /* 0x0000761016139816 */
/* 0x001fe20000000013 */
/*0a20*/ @!P1 IMAD.MOV.U32 R22, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff169624 */
/* 0x000fca00078e00ff */
/*0a30*/ @!P1 STG.E.U8 [R22.64], R19 ; /* 0x0000001316009986 */
/* 0x0001e4000c101104 */
/*0a40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a50*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x000ea2000c1e1900 */
/*0a60*/ BSSY B1, 0xb50 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*0a70*/ IMAD.IADD R26, R3, 0x1, R25 ; /* 0x00000001031a7824 */
/* 0x000fe200078e0219 */
/*0a80*/ ISETP.GT.AND P1, PT, R21, 0xf423f, PT ; /* 0x000f423f1500780c */
/* 0x004fda0003f24270 */
/*0a90*/ @P1 BRA 0xb40 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.WIDE R24, R26, R24, c[0x0][0x170] ; /* 0x00005c001a187625 */
/* 0x000fe200078e0218 */
/*0ab0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ LDG.E R19, [R24.64] ; /* 0x0000000418137981 */
/* 0x001ee2000c1e1900 */
/*0ad0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x1 ; /* 0x00000001ff147424 */
/* 0x000fe200078e00ff */
/*0ae0*/ IADD3 R21, R21, R18, RZ ; /* 0x0000001215157210 */
/* 0x004fc80007ffe0ff */
/*0af0*/ ISETP.GE.AND P1, PT, R21, R19, PT ; /* 0x000000131500720c */
/* 0x008fda0003f26270 */
/*0b00*/ @!P1 MOV R18, c[0x0][0x178] ; /* 0x00005e0000129a02 */
/* 0x000fe20000000f00 */
/*0b10*/ @!P1 IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff139624 */
/* 0x000fe200078e00ff */
/*0b20*/ @!P1 STG.E [R24.64], R21 ; /* 0x0000001518009986 */
/* 0x0001e8000c101904 */
/*0b30*/ @!P1 STG.E.U8 [R18.64], R20 ; /* 0x0000001412009986 */
/* 0x0001e4000c101104 */
/*0b40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b50*/ IADD3 R26, R3, R26, RZ ; /* 0x0000001a031a7210 */
/* 0x000fc80007ffe0ff */
/*0b60*/ ISETP.GE.AND P1, PT, R26, c[0x0][0x160], PT ; /* 0x000058001a007a0c */
/* 0x000fda0003f26270 */
/*0b70*/ @!P1 BRA 0x6d0 ; /* 0xfffffb5000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ @!P0 BRA 0x290 ; /* 0xfffff6f000008947 */
/* 0x000fea000383ffff */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21bellman_ford_one_iteriPiS_Pbi
.globl _Z21bellman_ford_one_iteriPiS_Pbi
.p2align 8
.type _Z21bellman_ford_one_iteriPiS_Pbi,@function
_Z21bellman_ford_one_iteriPiS_Pbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s16, s[0:1], 0x0
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s16, v0
s_cbranch_execz .LBB0_8
s_load_b32 s8, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v2, v1
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s8, s2
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
s_ashr_i32 s9, s8, 31
s_mov_b32 s2, s3
s_lshl_b64 s[10:11], s[8:9], 2
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v2, s16, v2
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, s16
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_lshl_b64 s[12:13], s[2:3], 2
v_mov_b32_e32 v9, v1
s_add_u32 s12, s6, s12
s_addc_u32 s13, s7, s13
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_mov_b64 s[14:15], 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v9, s8, v9
s_add_u32 s14, s14, s10
s_addc_u32 s15, s15, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s16, v9
s_or_b32 s9, vcc_lo, s9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB0_2
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, v7, s14
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v8, vcc_lo
s_mov_b32 s17, exec_lo
global_load_b32 v10, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0xf4240, v10
s_cbranch_execz .LBB0_4
v_add_co_u32 v3, vcc_lo, v5, s14
v_add_co_ci_u32_e32 v4, vcc_lo, s15, v6, vcc_lo
s_clause 0x1
global_load_b32 v11, v0, s[12:13]
global_load_b32 v12, v[3:4], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v10, v11, v10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v10, v12
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v11, 1
global_store_b32 v[3:4], v10, off
global_store_b8 v0, v11, s[0:1]
s_branch .LBB0_4
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21bellman_ford_one_iteriPiS_Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21bellman_ford_one_iteriPiS_Pbi, .Lfunc_end0-_Z21bellman_ford_one_iteriPiS_Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21bellman_ford_one_iteriPiS_Pbi
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z21bellman_ford_one_iteriPiS_Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Assignment 03 Program - ceasar_cipher.cu
* Sarah Helble
* 9/17/17
*
* Usage ./out <total_num_threads> <threads_per_block> <input_file> <key_file>
*
* Creates two arrays of <total_num_threads> length, and reads <total_num_threads>
* characters from <input_file> and <key_file> to fill them.
* Adds the character values together to create a cipher text (caesar cipher with
* keyword)
*
* Uses <total_num_threads> as total number of threads for the execution.
* Creates blocks with <threads_per_block> each.
* This results in # blocks = <total_num_threads> / <threads_per_block>
*
* Assumes that all values in input_file and key_file are printable (within the
* range of 32-126 ASCII decimal values)
*/
#include <stdio.h>
#include <stdlib.h>
/*
* The maximum and minimum integer values of the range of printable characters
* in the ASCII alphabet. Used by encrypt kernel to wrap adjust values to that
* ciphertext is always printable.
*/
#define MAX_PRINTABLE 126
#define MIN_PRINTABLE 32
#define NUM_ALPHA MAX_PRINTABLE - MIN_PRINTABLE
/**
* Kernel function that creates a ciphertext by adding the values
* in @text to the values in @key. As in a caesar cipher with keyword.
*
* @text plaintext values
* @key key values
* @result ciphertext
*
* TODO: some of the values in the resultant ciphertext will be unprintable.
* Make wrap around more advanced to deal with this.
*/
__global__ void encrypt(unsigned int *text, unsigned int *key, unsigned int *result, unsigned int *thread, unsigned int *block)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
/*
* Adjust value of text and key to be based at 0
* Printable ASCII starts at MIN_PRINTABLE, but 0 start is easier to work with
*/
char adjusted_text = text[idx] - MIN_PRINTABLE;
char adjusted_key = key[idx] - MIN_PRINTABLE;
/* The cipher character is the text char added to the key char modulo the number of chars in the alphabet*/
char cipherchar = (adjusted_text + adjusted_key) % (NUM_ALPHA);
/* adjust back to normal ascii (starting at MIN_PRINTABLE) and save to result */
result[idx] = (unsigned int) cipherchar + MIN_PRINTABLE ;
/* Calculating these extras so that we can see which blocks/threads do what */
thread[idx] = threadIdx.x;
block[idx] = blockIdx.x;
}
/**
* One fuction to handle the printing of all results.
* @text is the plaintext array
* @key is the key used to encrypt
* @result is the resulting ciphertext
* @blocks is the array holding the block number for each calculation
* @threads is the array holding the thread number fo each calculation
*/
void print_all_results(unsigned int *text, unsigned int *key, unsigned int *result,
unsigned int *blocks, unsigned int *threads, int array_size)
{
int i = 0;
/* Print the calculations */
for(i = 0; i < array_size; i++) {
printf("Block %2u - Thread %2u Calculated: %c + %c = %c\n", blocks[i], threads[i], text[i], key[i], result[i]);
}
/* Print the plain text, key, and result */
printf("\nSummary:\n\nEncrypted text:\n");
for(i = 0; i < array_size; i++) {
printf("%c", text[i]);
}
printf("\n\nWith Key:\n");
for(i = 0; i < array_size; i++) {
printf("%c", key[i]);
}
printf("\n\nResults in ciphertext:\n");
for(i = 0; i < array_size; i++) {
printf("%c", result[i]);
}
printf("\n\n");
}
/**
* Function that sets up everything for the kernel function encrypt()
*
* @array_size size of array (total number of threads)
* @threads_per_block number of threads to put in each block
* @input_fp file pointer to the input file text
* @key_fp file pointer to the key file
*
* Closes the file pointers @input_fp and @key_fp
*/
void main_sub(int array_size, int threads_per_block, FILE *input_fp, FILE *key_fp)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (array_size));
int i = 0;
unsigned int cpu_text[array_size];
unsigned int cpu_key[array_size];
unsigned int cpu_result[array_size];
unsigned int cpu_threads[array_size];
unsigned int cpu_blocks[array_size];
/* Read characters from the input and key files into the text and key arrays respectively */
for(i = 0; i < array_size; i++) {
cpu_text[i] = fgetc(input_fp);
cpu_key[i] = fgetc(key_fp);
}
/* Close the file pointers */
fclose(input_fp);
fclose(key_fp);
/* Declare and allocate pointers for GPU based parameters */
unsigned int *gpu_text;
unsigned int *gpu_key;
unsigned int *gpu_result;
unsigned int *gpu_threads;
unsigned int *gpu_blocks;
cudaMalloc((void **)&gpu_text, array_size_in_bytes);
cudaMalloc((void **)&gpu_key, array_size_in_bytes);
cudaMalloc((void **)&gpu_result, array_size_in_bytes);
cudaMalloc((void **)&gpu_threads, array_size_in_bytes);
cudaMalloc((void **)&gpu_blocks, array_size_in_bytes);
/* Copy the CPU memory to the GPU memory */
cudaMemcpy( gpu_text, cpu_text, array_size_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy( gpu_key, cpu_key, array_size_in_bytes, cudaMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = array_size/threads_per_block;
const unsigned int num_threads = array_size/num_blocks;
/* Execute the encryption kernel */
encrypt<<<num_blocks, num_threads>>>(gpu_text, gpu_key, gpu_result, gpu_threads, gpu_blocks);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpy( cpu_result, gpu_result, array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaMemcpy( cpu_threads, gpu_threads, array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaMemcpy( cpu_blocks, gpu_blocks, array_size_in_bytes, cudaMemcpyDeviceToHost);
/* Free the GPU memory */
cudaFree(gpu_text);
cudaFree(gpu_key);
cudaFree(gpu_result);
cudaFree(gpu_threads);
cudaFree(gpu_blocks);
print_all_results(cpu_text, cpu_key, cpu_result, cpu_blocks, cpu_threads, array_size);
}
/**
* Prints the correct usage of this file
* @name is the name of the executable (argv[0])
*/
void print_usage(char *name)
{
printf("Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n", name);
}
/**
* Entry point for excution. Checks command line arguments and
* opens input files, then passes execution to subordinate main_sub()
*/
int main(int argc, char *argv[])
{
/* Check the number of arguments, print usage if wrong */
if(argc != 5) {
printf("Error: Incorrect number of command line arguments\n");
print_usage(argv[0]);
exit(-1);
}
/* Check the values for num_threads and threads_per_block */
int num_threads = atoi(argv[1]);
int threads_per_block = atoi(argv[2]);
if(num_threads <= 0 || threads_per_block <= 0) {
printf("Error: num_threads and threads_per_block must be integer > 0");
print_usage(argv[0]);
exit(-1);
}
/* Sanity check */
if(threads_per_block > num_threads) {
printf("Error: threads per block is greater than number of threads\n");
print_usage(argv[0]);
exit(-1);
}
char *input_filename = argv[3];
char *key_filename = argv[4];
/* Make sure the input text file and the key file are openable */
FILE *input_fp = fopen(input_filename, "r");
if(!input_fp) {
printf("Error: failed to open input file %s\n", argv[3]);
exit(-1);
}
FILE *key_fp = fopen(key_filename, "r");
if(!key_fp){
printf("Error: failed to open key file %s\n", argv[4]);
fclose(input_fp);
exit(-1);
}
/* Pass all arguments to the subordinate main function */
main_sub(num_threads, threads_per_block, input_fp, key_fp);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z7encryptPjS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R11, c[0x0][0x0], R8 ; /* 0x000000000b007a24 */
/* 0x001fca00078e0208 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e000d */
/*0070*/ IMAD.WIDE.U32 R4, R0, R13.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x080fe400078e000d */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ LEA R6, R2, 0xe0000000, 0x18 ; /* 0xe000000002067811 */
/* 0x004fe200078ec0ff */
/*00b0*/ IMAD.WIDE.U32 R2, R0, R13, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe200078e000d */
/*00c0*/ LEA R7, R4, 0xe0000000, 0x18 ; /* 0xe000000004077811 */
/* 0x008fc600078ec0ff */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R13, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e000d */
/*00e0*/ SHF.R.S32.HI R6, RZ, 0x18, R6 ; /* 0x00000018ff067819 */
/* 0x000fc80000011406 */
/*00f0*/ LEA.HI.SX32 R7, R7, R6, 0x8 ; /* 0x0000000607077211 */
/* 0x000fe200078f42ff */
/*0100*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fd400000001ff */
/*0110*/ IMAD.HI R6, R7, -0x51b3bea3, R6 ; /* 0xae4c415d07067827 */
/* 0x000fca00078e0206 */
/*0120*/ SHF.R.U32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fc80000011606 */
/*0130*/ LEA.HI.SX32 R9, R6, R9, 0x1a ; /* 0x0000000906097211 */
/* 0x000fca00078fd2ff */
/*0140*/ IMAD R9, R9, -0x5e, R7 ; /* 0xffffffa209097824 */
/* 0x000fe400078e0207 */
/*0150*/ IMAD.WIDE.U32 R6, R0, R13, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fc600078e000d */
/*0160*/ IADD3 R9, R9, 0x20, RZ ; /* 0x0000002009097810 */
/* 0x000fca0007ffe0ff */
/*0170*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0180*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe8000c101904 */
/*0190*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Assignment 03 Program - ceasar_cipher.cu
* Sarah Helble
* 9/17/17
*
* Usage ./out <total_num_threads> <threads_per_block> <input_file> <key_file>
*
* Creates two arrays of <total_num_threads> length, and reads <total_num_threads>
* characters from <input_file> and <key_file> to fill them.
* Adds the character values together to create a cipher text (caesar cipher with
* keyword)
*
* Uses <total_num_threads> as total number of threads for the execution.
* Creates blocks with <threads_per_block> each.
* This results in # blocks = <total_num_threads> / <threads_per_block>
*
* Assumes that all values in input_file and key_file are printable (within the
* range of 32-126 ASCII decimal values)
*/
#include <stdio.h>
#include <stdlib.h>
/*
* The maximum and minimum integer values of the range of printable characters
* in the ASCII alphabet. Used by encrypt kernel to wrap adjust values to that
* ciphertext is always printable.
*/
#define MAX_PRINTABLE 126
#define MIN_PRINTABLE 32
#define NUM_ALPHA MAX_PRINTABLE - MIN_PRINTABLE
/**
* Kernel function that creates a ciphertext by adding the values
* in @text to the values in @key. As in a caesar cipher with keyword.
*
* @text plaintext values
* @key key values
* @result ciphertext
*
* TODO: some of the values in the resultant ciphertext will be unprintable.
* Make wrap around more advanced to deal with this.
*/
__global__ void encrypt(unsigned int *text, unsigned int *key, unsigned int *result, unsigned int *thread, unsigned int *block)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
/*
* Adjust value of text and key to be based at 0
* Printable ASCII starts at MIN_PRINTABLE, but 0 start is easier to work with
*/
char adjusted_text = text[idx] - MIN_PRINTABLE;
char adjusted_key = key[idx] - MIN_PRINTABLE;
/* The cipher character is the text char added to the key char modulo the number of chars in the alphabet*/
char cipherchar = (adjusted_text + adjusted_key) % (NUM_ALPHA);
/* adjust back to normal ascii (starting at MIN_PRINTABLE) and save to result */
result[idx] = (unsigned int) cipherchar + MIN_PRINTABLE ;
/* Calculating these extras so that we can see which blocks/threads do what */
thread[idx] = threadIdx.x;
block[idx] = blockIdx.x;
}
/**
* One fuction to handle the printing of all results.
* @text is the plaintext array
* @key is the key used to encrypt
* @result is the resulting ciphertext
* @blocks is the array holding the block number for each calculation
* @threads is the array holding the thread number fo each calculation
*/
void print_all_results(unsigned int *text, unsigned int *key, unsigned int *result,
unsigned int *blocks, unsigned int *threads, int array_size)
{
int i = 0;
/* Print the calculations */
for(i = 0; i < array_size; i++) {
printf("Block %2u - Thread %2u Calculated: %c + %c = %c\n", blocks[i], threads[i], text[i], key[i], result[i]);
}
/* Print the plain text, key, and result */
printf("\nSummary:\n\nEncrypted text:\n");
for(i = 0; i < array_size; i++) {
printf("%c", text[i]);
}
printf("\n\nWith Key:\n");
for(i = 0; i < array_size; i++) {
printf("%c", key[i]);
}
printf("\n\nResults in ciphertext:\n");
for(i = 0; i < array_size; i++) {
printf("%c", result[i]);
}
printf("\n\n");
}
/**
* Function that sets up everything for the kernel function encrypt()
*
* @array_size size of array (total number of threads)
* @threads_per_block number of threads to put in each block
* @input_fp file pointer to the input file text
* @key_fp file pointer to the key file
*
* Closes the file pointers @input_fp and @key_fp
*/
void main_sub(int array_size, int threads_per_block, FILE *input_fp, FILE *key_fp)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (array_size));
int i = 0;
unsigned int cpu_text[array_size];
unsigned int cpu_key[array_size];
unsigned int cpu_result[array_size];
unsigned int cpu_threads[array_size];
unsigned int cpu_blocks[array_size];
/* Read characters from the input and key files into the text and key arrays respectively */
for(i = 0; i < array_size; i++) {
cpu_text[i] = fgetc(input_fp);
cpu_key[i] = fgetc(key_fp);
}
/* Close the file pointers */
fclose(input_fp);
fclose(key_fp);
/* Declare and allocate pointers for GPU based parameters */
unsigned int *gpu_text;
unsigned int *gpu_key;
unsigned int *gpu_result;
unsigned int *gpu_threads;
unsigned int *gpu_blocks;
cudaMalloc((void **)&gpu_text, array_size_in_bytes);
cudaMalloc((void **)&gpu_key, array_size_in_bytes);
cudaMalloc((void **)&gpu_result, array_size_in_bytes);
cudaMalloc((void **)&gpu_threads, array_size_in_bytes);
cudaMalloc((void **)&gpu_blocks, array_size_in_bytes);
/* Copy the CPU memory to the GPU memory */
cudaMemcpy( gpu_text, cpu_text, array_size_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy( gpu_key, cpu_key, array_size_in_bytes, cudaMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = array_size/threads_per_block;
const unsigned int num_threads = array_size/num_blocks;
/* Execute the encryption kernel */
encrypt<<<num_blocks, num_threads>>>(gpu_text, gpu_key, gpu_result, gpu_threads, gpu_blocks);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpy( cpu_result, gpu_result, array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaMemcpy( cpu_threads, gpu_threads, array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaMemcpy( cpu_blocks, gpu_blocks, array_size_in_bytes, cudaMemcpyDeviceToHost);
/* Free the GPU memory */
cudaFree(gpu_text);
cudaFree(gpu_key);
cudaFree(gpu_result);
cudaFree(gpu_threads);
cudaFree(gpu_blocks);
print_all_results(cpu_text, cpu_key, cpu_result, cpu_blocks, cpu_threads, array_size);
}
/**
* Prints the correct usage of this file
* @name is the name of the executable (argv[0])
*/
void print_usage(char *name)
{
printf("Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n", name);
}
/**
* Entry point for excution. Checks command line arguments and
* opens input files, then passes execution to subordinate main_sub()
*/
int main(int argc, char *argv[])
{
/* Check the number of arguments, print usage if wrong */
if(argc != 5) {
printf("Error: Incorrect number of command line arguments\n");
print_usage(argv[0]);
exit(-1);
}
/* Check the values for num_threads and threads_per_block */
int num_threads = atoi(argv[1]);
int threads_per_block = atoi(argv[2]);
if(num_threads <= 0 || threads_per_block <= 0) {
printf("Error: num_threads and threads_per_block must be integer > 0");
print_usage(argv[0]);
exit(-1);
}
/* Sanity check */
if(threads_per_block > num_threads) {
printf("Error: threads per block is greater than number of threads\n");
print_usage(argv[0]);
exit(-1);
}
char *input_filename = argv[3];
char *key_filename = argv[4];
/* Make sure the input text file and the key file are openable */
FILE *input_fp = fopen(input_filename, "r");
if(!input_fp) {
printf("Error: failed to open input file %s\n", argv[3]);
exit(-1);
}
FILE *key_fp = fopen(key_filename, "r");
if(!key_fp){
printf("Error: failed to open key file %s\n", argv[4]);
fclose(input_fp);
exit(-1);
}
/* Pass all arguments to the subordinate main function */
main_sub(num_threads, threads_per_block, input_fp, key_fp);
return EXIT_SUCCESS;
} | .file "tmpxft_0001647c_00000000-6_ceasar_cipher.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Block %2u - Thread %2u Calculated: %c + %c = %c\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nSummary:\n\nEncrypted text:\n"
.LC2:
.string "%c"
.LC3:
.string "\n\nWith Key:\n"
.LC4:
.string "\n\nResults in ciphertext:\n"
.LC5:
.string "\n\n"
.text
.globl _Z17print_all_resultsPjS_S_S_S_i
.type _Z17print_all_resultsPjS_S_S_S_i, @function
_Z17print_all_resultsPjS_S_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, 8(%rsp)
testl %r9d, %r9d
jle .L4
movq %rdi, %r12
movq %rdx, %rbp
movq %rcx, %r14
movq %r8, %r15
movslq %r9d, %r9
leaq 0(,%r9,4), %r13
movl $0, %ebx
.L5:
movl (%r15,%rbx), %ecx
movl (%r14,%rbx), %edx
subq $8, %rsp
.cfi_def_cfa_offset 88
movl 0(%rbp,%rbx), %eax
pushq %rax
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
movl (%rax,%rbx), %r9d
movl (%r12,%rbx), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 80
cmpq %r13, %rbx
jne .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
addq %r13, %r12
leaq .LC2(%rip), %r14
.L6:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L6
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %r12
movq %r12, %rbx
addq %r13, %r12
leaq .LC2(%rip), %r14
.L7:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L7
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq %r13, %rbp
leaq .LC2(%rip), %r12
.L8:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L8
.L9:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2057:
.size _Z17print_all_resultsPjS_S_S_S_i, .-_Z17print_all_resultsPjS_S_S_S_i
.section .rodata.str1.8
.align 8
.LC6:
.string "Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n"
.text
.globl _Z11print_usagePc
.type _Z11print_usagePc, @function
_Z11print_usagePc:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_usagePc, .-_Z11print_usagePc
.globl _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
.type _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_, @function
_Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7encryptPjS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_, .-_Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
.globl _Z7encryptPjS_S_S_S_
.type _Z7encryptPjS_S_S_S_, @function
_Z7encryptPjS_S_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7encryptPjS_S_S_S_, .-_Z7encryptPjS_S_S_S_
.globl _Z8main_subiiP8_IO_FILES0_
.type _Z8main_subiiP8_IO_FILES0_, @function
_Z8main_subiiP8_IO_FILES0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -132(%rbp)
movl %esi, -156(%rbp)
movq %rdx, %r15
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movslq %edi, %r13
leal 0(,%rdi,4), %eax
movl %eax, -136(%rbp)
salq $2, %r13
leaq 15(%r13), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L27:
cmpq %rdx, %rsp
je .L28
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L27
.L28:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L29
orq $0, -8(%rsp,%rax)
.L29:
movq %rsp, -144(%rbp)
leaq 15(%r13), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L30:
cmpq %rdx, %rsp
je .L31
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L30
.L31:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L32
orq $0, -8(%rsp,%rax)
.L32:
movq %rsp, -152(%rbp)
leaq 15(%r13), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L33:
cmpq %rdx, %rsp
je .L34
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L33
.L34:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L35
orq $0, -8(%rsp,%rax)
.L35:
movq %rsp, -168(%rbp)
leaq 15(%r13), %rax
movq %rax, %rdx
andq $-16, %rdx
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L36:
cmpq %rcx, %rsp
je .L37
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L36
.L37:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L38
orq $0, -8(%rsp,%rax)
.L38:
movq %rsp, -176(%rbp)
leaq 15(%r13), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L39:
cmpq %rcx, %rsp
je .L40
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L39
.L40:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L41
orq $0, -8(%rsp,%rdx)
.L41:
movq %rsp, -184(%rbp)
cmpl $0, -132(%rbp)
jle .L42
movq -144(%rbp), %rax
movq %rax, %rbx
movq -152(%rbp), %r12
addq %rax, %r13
.L43:
movq %r15, %rdi
call fgetc@PLT
movl %eax, (%rbx)
movq %r14, %rdi
call fgetc@PLT
movl %eax, (%r12)
addq $4, %rbx
addq $4, %r12
cmpq %r13, %rbx
jne .L43
.L42:
movq %r15, %rdi
call fclose@PLT
movq %r14, %rdi
call fclose@PLT
movslq -136(%rbp), %rbx
leaq -120(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -144(%rbp), %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -152(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl -132(%rbp), %eax
cltd
idivl -156(%rbp)
movl %eax, %ecx
movl -132(%rbp), %eax
movl $0, %edx
divl %ecx
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl %ecx, -80(%rbp)
movl $1, -76(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movl $2, %ecx
movq %rbx, %rdx
movq -104(%rbp), %rsi
movq -168(%rbp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -96(%rbp), %rsi
movq -176(%rbp), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -88(%rbp), %rsi
movq -184(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movl -132(%rbp), %r9d
movq %r14, %r8
movq %rbx, %rcx
movq %r15, %rdx
movq -152(%rbp), %rsi
movq -144(%rbp), %rdi
call _Z17print_all_resultsPjS_S_S_S_i
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L49
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L48:
.cfi_restore_state
movq -88(%rbp), %r8
movq -96(%rbp), %rcx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8main_subiiP8_IO_FILES0_, .-_Z8main_subiiP8_IO_FILES0_
.section .rodata.str1.8
.align 8
.LC7:
.string "Error: Incorrect number of command line arguments\n"
.align 8
.LC8:
.string "Error: num_threads and threads_per_block must be integer > 0"
.align 8
.LC9:
.string "Error: threads per block is greater than number of threads\n"
.section .rodata.str1.1
.LC10:
.string "r"
.section .rodata.str1.8
.align 8
.LC11:
.string "Error: failed to open input file %s\n"
.align 8
.LC12:
.string "Error: failed to open key file %s\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %rbx
cmpl $5, %edi
jne .L59
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
testl %ebp, %ebp
jle .L57
testl %eax, %eax
jle .L57
cmpl %ebp, %eax
jg .L60
movq 32(%rbx), %r14
movq 24(%rbx), %rdi
leaq .LC10(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L61
leaq .LC10(%rip), %rsi
movq %r14, %rdi
call fopen@PLT
movq %rax, %rcx
testq %rax, %rax
je .L62
movq %rbp, %rdx
movl %r13d, %esi
movl %r12d, %edi
call _Z8main_subiiP8_IO_FILES0_
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call _Z11print_usagePc
movl $-1, %edi
call exit@PLT
.L57:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call _Z11print_usagePc
movl $-1, %edi
call exit@PLT
.L60:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call _Z11print_usagePc
movl $-1, %edi
call exit@PLT
.L61:
movq 24(%rbx), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
movq 32(%rbx), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7encryptPjS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPjS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Assignment 03 Program - ceasar_cipher.cu
* Sarah Helble
* 9/17/17
*
* Usage ./out <total_num_threads> <threads_per_block> <input_file> <key_file>
*
* Creates two arrays of <total_num_threads> length, and reads <total_num_threads>
* characters from <input_file> and <key_file> to fill them.
* Adds the character values together to create a cipher text (caesar cipher with
* keyword)
*
* Uses <total_num_threads> as total number of threads for the execution.
* Creates blocks with <threads_per_block> each.
* This results in # blocks = <total_num_threads> / <threads_per_block>
*
* Assumes that all values in input_file and key_file are printable (within the
* range of 32-126 ASCII decimal values)
*/
#include <stdio.h>
#include <stdlib.h>
/*
* The maximum and minimum integer values of the range of printable characters
* in the ASCII alphabet. Used by encrypt kernel to wrap adjust values to that
* ciphertext is always printable.
*/
#define MAX_PRINTABLE 126
#define MIN_PRINTABLE 32
#define NUM_ALPHA MAX_PRINTABLE - MIN_PRINTABLE
/**
* Kernel function that creates a ciphertext by adding the values
* in @text to the values in @key. As in a caesar cipher with keyword.
*
* @text plaintext values
* @key key values
* @result ciphertext
*
* TODO: some of the values in the resultant ciphertext will be unprintable.
* Make wrap around more advanced to deal with this.
*/
__global__ void encrypt(unsigned int *text, unsigned int *key, unsigned int *result, unsigned int *thread, unsigned int *block)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
/*
* Adjust value of text and key to be based at 0
* Printable ASCII starts at MIN_PRINTABLE, but 0 start is easier to work with
*/
char adjusted_text = text[idx] - MIN_PRINTABLE;
char adjusted_key = key[idx] - MIN_PRINTABLE;
/* The cipher character is the text char added to the key char modulo the number of chars in the alphabet*/
char cipherchar = (adjusted_text + adjusted_key) % (NUM_ALPHA);
/* adjust back to normal ascii (starting at MIN_PRINTABLE) and save to result */
result[idx] = (unsigned int) cipherchar + MIN_PRINTABLE ;
/* Calculating these extras so that we can see which blocks/threads do what */
thread[idx] = threadIdx.x;
block[idx] = blockIdx.x;
}
/**
* One fuction to handle the printing of all results.
* @text is the plaintext array
* @key is the key used to encrypt
* @result is the resulting ciphertext
* @blocks is the array holding the block number for each calculation
* @threads is the array holding the thread number fo each calculation
*/
void print_all_results(unsigned int *text, unsigned int *key, unsigned int *result,
unsigned int *blocks, unsigned int *threads, int array_size)
{
int i = 0;
/* Print the calculations */
for(i = 0; i < array_size; i++) {
printf("Block %2u - Thread %2u Calculated: %c + %c = %c\n", blocks[i], threads[i], text[i], key[i], result[i]);
}
/* Print the plain text, key, and result */
printf("\nSummary:\n\nEncrypted text:\n");
for(i = 0; i < array_size; i++) {
printf("%c", text[i]);
}
printf("\n\nWith Key:\n");
for(i = 0; i < array_size; i++) {
printf("%c", key[i]);
}
printf("\n\nResults in ciphertext:\n");
for(i = 0; i < array_size; i++) {
printf("%c", result[i]);
}
printf("\n\n");
}
/**
* Function that sets up everything for the kernel function encrypt()
*
* @array_size size of array (total number of threads)
* @threads_per_block number of threads to put in each block
* @input_fp file pointer to the input file text
* @key_fp file pointer to the key file
*
* Closes the file pointers @input_fp and @key_fp
*/
void main_sub(int array_size, int threads_per_block, FILE *input_fp, FILE *key_fp)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (array_size));
int i = 0;
unsigned int cpu_text[array_size];
unsigned int cpu_key[array_size];
unsigned int cpu_result[array_size];
unsigned int cpu_threads[array_size];
unsigned int cpu_blocks[array_size];
/* Read characters from the input and key files into the text and key arrays respectively */
for(i = 0; i < array_size; i++) {
cpu_text[i] = fgetc(input_fp);
cpu_key[i] = fgetc(key_fp);
}
/* Close the file pointers */
fclose(input_fp);
fclose(key_fp);
/* Declare and allocate pointers for GPU based parameters */
unsigned int *gpu_text;
unsigned int *gpu_key;
unsigned int *gpu_result;
unsigned int *gpu_threads;
unsigned int *gpu_blocks;
cudaMalloc((void **)&gpu_text, array_size_in_bytes);
cudaMalloc((void **)&gpu_key, array_size_in_bytes);
cudaMalloc((void **)&gpu_result, array_size_in_bytes);
cudaMalloc((void **)&gpu_threads, array_size_in_bytes);
cudaMalloc((void **)&gpu_blocks, array_size_in_bytes);
/* Copy the CPU memory to the GPU memory */
cudaMemcpy( gpu_text, cpu_text, array_size_in_bytes, cudaMemcpyHostToDevice);
cudaMemcpy( gpu_key, cpu_key, array_size_in_bytes, cudaMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = array_size/threads_per_block;
const unsigned int num_threads = array_size/num_blocks;
/* Execute the encryption kernel */
encrypt<<<num_blocks, num_threads>>>(gpu_text, gpu_key, gpu_result, gpu_threads, gpu_blocks);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpy( cpu_result, gpu_result, array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaMemcpy( cpu_threads, gpu_threads, array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaMemcpy( cpu_blocks, gpu_blocks, array_size_in_bytes, cudaMemcpyDeviceToHost);
/* Free the GPU memory */
cudaFree(gpu_text);
cudaFree(gpu_key);
cudaFree(gpu_result);
cudaFree(gpu_threads);
cudaFree(gpu_blocks);
print_all_results(cpu_text, cpu_key, cpu_result, cpu_blocks, cpu_threads, array_size);
}
/**
* Prints the correct usage of this file
* @name is the name of the executable (argv[0])
*/
void print_usage(char *name)
{
printf("Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n", name);
}
/**
* Entry point for excution. Checks command line arguments and
* opens input files, then passes execution to subordinate main_sub()
*/
int main(int argc, char *argv[])
{
/* Check the number of arguments, print usage if wrong */
if(argc != 5) {
printf("Error: Incorrect number of command line arguments\n");
print_usage(argv[0]);
exit(-1);
}
/* Check the values for num_threads and threads_per_block */
int num_threads = atoi(argv[1]);
int threads_per_block = atoi(argv[2]);
if(num_threads <= 0 || threads_per_block <= 0) {
printf("Error: num_threads and threads_per_block must be integer > 0");
print_usage(argv[0]);
exit(-1);
}
/* Sanity check */
if(threads_per_block > num_threads) {
printf("Error: threads per block is greater than number of threads\n");
print_usage(argv[0]);
exit(-1);
}
char *input_filename = argv[3];
char *key_filename = argv[4];
/* Make sure the input text file and the key file are openable */
FILE *input_fp = fopen(input_filename, "r");
if(!input_fp) {
printf("Error: failed to open input file %s\n", argv[3]);
exit(-1);
}
FILE *key_fp = fopen(key_filename, "r");
if(!key_fp){
printf("Error: failed to open key file %s\n", argv[4]);
fclose(input_fp);
exit(-1);
}
/* Pass all arguments to the subordinate main function */
main_sub(num_threads, threads_per_block, input_fp, key_fp);
return EXIT_SUCCESS;
} | /**
* Assignment 03 Program - ceasar_cipher.cu
* Sarah Helble
* 9/17/17
*
* Usage ./out <total_num_threads> <threads_per_block> <input_file> <key_file>
*
* Creates two arrays of <total_num_threads> length, and reads <total_num_threads>
* characters from <input_file> and <key_file> to fill them.
* Adds the character values together to create a cipher text (caesar cipher with
* keyword)
*
* Uses <total_num_threads> as total number of threads for the execution.
* Creates blocks with <threads_per_block> each.
* This results in # blocks = <total_num_threads> / <threads_per_block>
*
* Assumes that all values in input_file and key_file are printable (within the
* range of 32-126 ASCII decimal values)
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
* The maximum and minimum integer values of the range of printable characters
* in the ASCII alphabet. Used by encrypt kernel to wrap adjust values to that
* ciphertext is always printable.
*/
#define MAX_PRINTABLE 126
#define MIN_PRINTABLE 32
#define NUM_ALPHA MAX_PRINTABLE - MIN_PRINTABLE
/**
* Kernel function that creates a ciphertext by adding the values
* in @text to the values in @key. As in a caesar cipher with keyword.
*
* @text plaintext values
* @key key values
* @result ciphertext
*
* TODO: some of the values in the resultant ciphertext will be unprintable.
* Make wrap around more advanced to deal with this.
*/
__global__ void encrypt(unsigned int *text, unsigned int *key, unsigned int *result, unsigned int *thread, unsigned int *block)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
/*
* Adjust value of text and key to be based at 0
* Printable ASCII starts at MIN_PRINTABLE, but 0 start is easier to work with
*/
char adjusted_text = text[idx] - MIN_PRINTABLE;
char adjusted_key = key[idx] - MIN_PRINTABLE;
/* The cipher character is the text char added to the key char modulo the number of chars in the alphabet*/
char cipherchar = (adjusted_text + adjusted_key) % (NUM_ALPHA);
/* adjust back to normal ascii (starting at MIN_PRINTABLE) and save to result */
result[idx] = (unsigned int) cipherchar + MIN_PRINTABLE ;
/* Calculating these extras so that we can see which blocks/threads do what */
thread[idx] = threadIdx.x;
block[idx] = blockIdx.x;
}
/**
* One fuction to handle the printing of all results.
* @text is the plaintext array
* @key is the key used to encrypt
* @result is the resulting ciphertext
* @blocks is the array holding the block number for each calculation
* @threads is the array holding the thread number fo each calculation
*/
void print_all_results(unsigned int *text, unsigned int *key, unsigned int *result,
unsigned int *blocks, unsigned int *threads, int array_size)
{
int i = 0;
/* Print the calculations */
for(i = 0; i < array_size; i++) {
printf("Block %2u - Thread %2u Calculated: %c + %c = %c\n", blocks[i], threads[i], text[i], key[i], result[i]);
}
/* Print the plain text, key, and result */
printf("\nSummary:\n\nEncrypted text:\n");
for(i = 0; i < array_size; i++) {
printf("%c", text[i]);
}
printf("\n\nWith Key:\n");
for(i = 0; i < array_size; i++) {
printf("%c", key[i]);
}
printf("\n\nResults in ciphertext:\n");
for(i = 0; i < array_size; i++) {
printf("%c", result[i]);
}
printf("\n\n");
}
/**
* Function that sets up everything for the kernel function encrypt()
*
* @array_size size of array (total number of threads)
* @threads_per_block number of threads to put in each block
* @input_fp file pointer to the input file text
* @key_fp file pointer to the key file
*
* Closes the file pointers @input_fp and @key_fp
*/
void main_sub(int array_size, int threads_per_block, FILE *input_fp, FILE *key_fp)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (array_size));
int i = 0;
unsigned int cpu_text[array_size];
unsigned int cpu_key[array_size];
unsigned int cpu_result[array_size];
unsigned int cpu_threads[array_size];
unsigned int cpu_blocks[array_size];
/* Read characters from the input and key files into the text and key arrays respectively */
for(i = 0; i < array_size; i++) {
cpu_text[i] = fgetc(input_fp);
cpu_key[i] = fgetc(key_fp);
}
/* Close the file pointers */
fclose(input_fp);
fclose(key_fp);
/* Declare and allocate pointers for GPU based parameters */
unsigned int *gpu_text;
unsigned int *gpu_key;
unsigned int *gpu_result;
unsigned int *gpu_threads;
unsigned int *gpu_blocks;
hipMalloc((void **)&gpu_text, array_size_in_bytes);
hipMalloc((void **)&gpu_key, array_size_in_bytes);
hipMalloc((void **)&gpu_result, array_size_in_bytes);
hipMalloc((void **)&gpu_threads, array_size_in_bytes);
hipMalloc((void **)&gpu_blocks, array_size_in_bytes);
/* Copy the CPU memory to the GPU memory */
hipMemcpy( gpu_text, cpu_text, array_size_in_bytes, hipMemcpyHostToDevice);
hipMemcpy( gpu_key, cpu_key, array_size_in_bytes, hipMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = array_size/threads_per_block;
const unsigned int num_threads = array_size/num_blocks;
/* Execute the encryption kernel */
encrypt<<<num_blocks, num_threads>>>(gpu_text, gpu_key, gpu_result, gpu_threads, gpu_blocks);
/* Copy the changed GPU memory back to the CPU */
hipMemcpy( cpu_result, gpu_result, array_size_in_bytes, hipMemcpyDeviceToHost);
hipMemcpy( cpu_threads, gpu_threads, array_size_in_bytes, hipMemcpyDeviceToHost);
hipMemcpy( cpu_blocks, gpu_blocks, array_size_in_bytes, hipMemcpyDeviceToHost);
/* Free the GPU memory */
hipFree(gpu_text);
hipFree(gpu_key);
hipFree(gpu_result);
hipFree(gpu_threads);
hipFree(gpu_blocks);
print_all_results(cpu_text, cpu_key, cpu_result, cpu_blocks, cpu_threads, array_size);
}
/**
* Prints the correct usage of this file
* @name is the name of the executable (argv[0])
*/
void print_usage(char *name)
{
printf("Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n", name);
}
/**
* Entry point for excution. Checks command line arguments and
* opens input files, then passes execution to subordinate main_sub()
*/
int main(int argc, char *argv[])
{
/* Check the number of arguments, print usage if wrong */
if(argc != 5) {
printf("Error: Incorrect number of command line arguments\n");
print_usage(argv[0]);
exit(-1);
}
/* Check the values for num_threads and threads_per_block */
int num_threads = atoi(argv[1]);
int threads_per_block = atoi(argv[2]);
if(num_threads <= 0 || threads_per_block <= 0) {
printf("Error: num_threads and threads_per_block must be integer > 0");
print_usage(argv[0]);
exit(-1);
}
/* Sanity check */
if(threads_per_block > num_threads) {
printf("Error: threads per block is greater than number of threads\n");
print_usage(argv[0]);
exit(-1);
}
char *input_filename = argv[3];
char *key_filename = argv[4];
/* Make sure the input text file and the key file are openable */
FILE *input_fp = fopen(input_filename, "r");
if(!input_fp) {
printf("Error: failed to open input file %s\n", argv[3]);
exit(-1);
}
FILE *key_fp = fopen(key_filename, "r");
if(!key_fp){
printf("Error: failed to open key file %s\n", argv[4]);
fclose(input_fp);
exit(-1);
}
/* Pass all arguments to the subordinate main function */
main_sub(num_threads, threads_per_block, input_fp, key_fp);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Assignment 03 Program - ceasar_cipher.cu
* Sarah Helble
* 9/17/17
*
* Usage ./out <total_num_threads> <threads_per_block> <input_file> <key_file>
*
* Creates two arrays of <total_num_threads> length, and reads <total_num_threads>
* characters from <input_file> and <key_file> to fill them.
* Adds the character values together to create a cipher text (caesar cipher with
* keyword)
*
* Uses <total_num_threads> as total number of threads for the execution.
* Creates blocks with <threads_per_block> each.
* This results in # blocks = <total_num_threads> / <threads_per_block>
*
* Assumes that all values in input_file and key_file are printable (within the
* range of 32-126 ASCII decimal values)
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
* The maximum and minimum integer values of the range of printable characters
* in the ASCII alphabet. Used by encrypt kernel to wrap adjust values to that
* ciphertext is always printable.
*/
#define MAX_PRINTABLE 126
#define MIN_PRINTABLE 32
#define NUM_ALPHA MAX_PRINTABLE - MIN_PRINTABLE
/**
* Kernel function that creates a ciphertext by adding the values
* in @text to the values in @key. As in a caesar cipher with keyword.
*
* @text plaintext values
* @key key values
* @result ciphertext
*
* TODO: some of the values in the resultant ciphertext will be unprintable.
* Make wrap around more advanced to deal with this.
*/
__global__ void encrypt(unsigned int *text, unsigned int *key, unsigned int *result, unsigned int *thread, unsigned int *block)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
/*
* Adjust value of text and key to be based at 0
* Printable ASCII starts at MIN_PRINTABLE, but 0 start is easier to work with
*/
char adjusted_text = text[idx] - MIN_PRINTABLE;
char adjusted_key = key[idx] - MIN_PRINTABLE;
/* The cipher character is the text char added to the key char modulo the number of chars in the alphabet*/
char cipherchar = (adjusted_text + adjusted_key) % (NUM_ALPHA);
/* adjust back to normal ascii (starting at MIN_PRINTABLE) and save to result */
result[idx] = (unsigned int) cipherchar + MIN_PRINTABLE ;
/* Calculating these extras so that we can see which blocks/threads do what */
thread[idx] = threadIdx.x;
block[idx] = blockIdx.x;
}
/**
* One fuction to handle the printing of all results.
* @text is the plaintext array
* @key is the key used to encrypt
* @result is the resulting ciphertext
* @blocks is the array holding the block number for each calculation
* @threads is the array holding the thread number fo each calculation
*/
void print_all_results(unsigned int *text, unsigned int *key, unsigned int *result,
unsigned int *blocks, unsigned int *threads, int array_size)
{
int i = 0;
/* Print the calculations */
for(i = 0; i < array_size; i++) {
printf("Block %2u - Thread %2u Calculated: %c + %c = %c\n", blocks[i], threads[i], text[i], key[i], result[i]);
}
/* Print the plain text, key, and result */
printf("\nSummary:\n\nEncrypted text:\n");
for(i = 0; i < array_size; i++) {
printf("%c", text[i]);
}
printf("\n\nWith Key:\n");
for(i = 0; i < array_size; i++) {
printf("%c", key[i]);
}
printf("\n\nResults in ciphertext:\n");
for(i = 0; i < array_size; i++) {
printf("%c", result[i]);
}
printf("\n\n");
}
/**
* Function that sets up everything for the kernel function encrypt()
*
* @array_size size of array (total number of threads)
* @threads_per_block number of threads to put in each block
* @input_fp file pointer to the input file text
* @key_fp file pointer to the key file
*
* Closes the file pointers @input_fp and @key_fp
*/
void main_sub(int array_size, int threads_per_block, FILE *input_fp, FILE *key_fp)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (array_size));
int i = 0;
unsigned int cpu_text[array_size];
unsigned int cpu_key[array_size];
unsigned int cpu_result[array_size];
unsigned int cpu_threads[array_size];
unsigned int cpu_blocks[array_size];
/* Read characters from the input and key files into the text and key arrays respectively */
for(i = 0; i < array_size; i++) {
cpu_text[i] = fgetc(input_fp);
cpu_key[i] = fgetc(key_fp);
}
/* Close the file pointers */
fclose(input_fp);
fclose(key_fp);
/* Declare and allocate pointers for GPU based parameters */
unsigned int *gpu_text;
unsigned int *gpu_key;
unsigned int *gpu_result;
unsigned int *gpu_threads;
unsigned int *gpu_blocks;
hipMalloc((void **)&gpu_text, array_size_in_bytes);
hipMalloc((void **)&gpu_key, array_size_in_bytes);
hipMalloc((void **)&gpu_result, array_size_in_bytes);
hipMalloc((void **)&gpu_threads, array_size_in_bytes);
hipMalloc((void **)&gpu_blocks, array_size_in_bytes);
/* Copy the CPU memory to the GPU memory */
hipMemcpy( gpu_text, cpu_text, array_size_in_bytes, hipMemcpyHostToDevice);
hipMemcpy( gpu_key, cpu_key, array_size_in_bytes, hipMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = array_size/threads_per_block;
const unsigned int num_threads = array_size/num_blocks;
/* Execute the encryption kernel */
encrypt<<<num_blocks, num_threads>>>(gpu_text, gpu_key, gpu_result, gpu_threads, gpu_blocks);
/* Copy the changed GPU memory back to the CPU */
hipMemcpy( cpu_result, gpu_result, array_size_in_bytes, hipMemcpyDeviceToHost);
hipMemcpy( cpu_threads, gpu_threads, array_size_in_bytes, hipMemcpyDeviceToHost);
hipMemcpy( cpu_blocks, gpu_blocks, array_size_in_bytes, hipMemcpyDeviceToHost);
/* Free the GPU memory */
hipFree(gpu_text);
hipFree(gpu_key);
hipFree(gpu_result);
hipFree(gpu_threads);
hipFree(gpu_blocks);
print_all_results(cpu_text, cpu_key, cpu_result, cpu_blocks, cpu_threads, array_size);
}
/**
* Prints the correct usage of this file
* @name is the name of the executable (argv[0])
*/
void print_usage(char *name)
{
printf("Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n", name);
}
/**
* Entry point for excution. Checks command line arguments and
* opens input files, then passes execution to subordinate main_sub()
*/
int main(int argc, char *argv[])
{
/* Check the number of arguments, print usage if wrong */
if(argc != 5) {
printf("Error: Incorrect number of command line arguments\n");
print_usage(argv[0]);
exit(-1);
}
/* Check the values for num_threads and threads_per_block */
int num_threads = atoi(argv[1]);
int threads_per_block = atoi(argv[2]);
if(num_threads <= 0 || threads_per_block <= 0) {
printf("Error: num_threads and threads_per_block must be integer > 0");
print_usage(argv[0]);
exit(-1);
}
/* Sanity check */
if(threads_per_block > num_threads) {
printf("Error: threads per block is greater than number of threads\n");
print_usage(argv[0]);
exit(-1);
}
char *input_filename = argv[3];
char *key_filename = argv[4];
/* Make sure the input text file and the key file are openable */
FILE *input_fp = fopen(input_filename, "r");
if(!input_fp) {
printf("Error: failed to open input file %s\n", argv[3]);
exit(-1);
}
FILE *key_fp = fopen(key_filename, "r");
if(!key_fp){
printf("Error: failed to open key file %s\n", argv[4]);
fclose(input_fp);
exit(-1);
}
/* Pass all arguments to the subordinate main function */
main_sub(num_threads, threads_per_block, input_fp, key_fp);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7encryptPjS_S_S_S_
.globl _Z7encryptPjS_S_S_S_
.p2align 8
.type _Z7encryptPjS_S_S_S_,@function
_Z7encryptPjS_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v3, 24, 0xe0000000
s_waitcnt vmcnt(0)
v_lshl_add_u32 v4, v4, 24, 0xe0000000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 24, v3
v_ashrrev_i32_e32 v4, 24, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v4, v3
v_mul_hi_i32 v3, v5, 0xae4c415d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v5
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v6, v3, 0x5e
v_add_co_u32 v3, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v8, v5, v6
v_add_co_u32 v5, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v2, vcc_lo
v_dual_mov_b32 v7, s15 :: v_dual_add_nc_u32 v8, 32, v8
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[3:4], v8, off
global_store_b32 v[5:6], v0, off
global_store_b32 v[1:2], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPjS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7encryptPjS_S_S_S_, .Lfunc_end0-_Z7encryptPjS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPjS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7encryptPjS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Assignment 03 Program - ceasar_cipher.cu
* Sarah Helble
* 9/17/17
*
* Usage ./out <total_num_threads> <threads_per_block> <input_file> <key_file>
*
* Creates two arrays of <total_num_threads> length, and reads <total_num_threads>
* characters from <input_file> and <key_file> to fill them.
* Adds the character values together to create a cipher text (caesar cipher with
* keyword)
*
* Uses <total_num_threads> as total number of threads for the execution.
* Creates blocks with <threads_per_block> each.
* This results in # blocks = <total_num_threads> / <threads_per_block>
*
* Assumes that all values in input_file and key_file are printable (within the
* range of 32-126 ASCII decimal values)
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
* The maximum and minimum integer values of the range of printable characters
* in the ASCII alphabet. Used by encrypt kernel to wrap adjust values to that
* ciphertext is always printable.
*/
#define MAX_PRINTABLE 126
#define MIN_PRINTABLE 32
#define NUM_ALPHA MAX_PRINTABLE - MIN_PRINTABLE
/**
* Kernel function that creates a ciphertext by adding the values
* in @text to the values in @key. As in a caesar cipher with keyword.
*
* @text plaintext values
* @key key values
* @result ciphertext
*
* TODO: some of the values in the resultant ciphertext will be unprintable.
* Make wrap around more advanced to deal with this.
*/
__global__ void encrypt(unsigned int *text, unsigned int *key, unsigned int *result, unsigned int *thread, unsigned int *block)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
/*
* Adjust value of text and key to be based at 0
* Printable ASCII starts at MIN_PRINTABLE, but 0 start is easier to work with
*/
char adjusted_text = text[idx] - MIN_PRINTABLE;
char adjusted_key = key[idx] - MIN_PRINTABLE;
/* The cipher character is the text char added to the key char modulo the number of chars in the alphabet*/
char cipherchar = (adjusted_text + adjusted_key) % (NUM_ALPHA);
/* adjust back to normal ascii (starting at MIN_PRINTABLE) and save to result */
result[idx] = (unsigned int) cipherchar + MIN_PRINTABLE ;
/* Calculating these extras so that we can see which blocks/threads do what */
thread[idx] = threadIdx.x;
block[idx] = blockIdx.x;
}
/**
* One fuction to handle the printing of all results.
* @text is the plaintext array
* @key is the key used to encrypt
* @result is the resulting ciphertext
* @blocks is the array holding the block number for each calculation
* @threads is the array holding the thread number fo each calculation
*/
void print_all_results(unsigned int *text, unsigned int *key, unsigned int *result,
unsigned int *blocks, unsigned int *threads, int array_size)
{
int i = 0;
/* Print the calculations */
for(i = 0; i < array_size; i++) {
printf("Block %2u - Thread %2u Calculated: %c + %c = %c\n", blocks[i], threads[i], text[i], key[i], result[i]);
}
/* Print the plain text, key, and result */
printf("\nSummary:\n\nEncrypted text:\n");
for(i = 0; i < array_size; i++) {
printf("%c", text[i]);
}
printf("\n\nWith Key:\n");
for(i = 0; i < array_size; i++) {
printf("%c", key[i]);
}
printf("\n\nResults in ciphertext:\n");
for(i = 0; i < array_size; i++) {
printf("%c", result[i]);
}
printf("\n\n");
}
/**
* Function that sets up everything for the kernel function encrypt()
*
* @array_size size of array (total number of threads)
* @threads_per_block number of threads to put in each block
* @input_fp file pointer to the input file text
* @key_fp file pointer to the key file
*
* Closes the file pointers @input_fp and @key_fp
*/
void main_sub(int array_size, int threads_per_block, FILE *input_fp, FILE *key_fp)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (array_size));
int i = 0;
unsigned int cpu_text[array_size];
unsigned int cpu_key[array_size];
unsigned int cpu_result[array_size];
unsigned int cpu_threads[array_size];
unsigned int cpu_blocks[array_size];
/* Read characters from the input and key files into the text and key arrays respectively */
for(i = 0; i < array_size; i++) {
cpu_text[i] = fgetc(input_fp);
cpu_key[i] = fgetc(key_fp);
}
/* Close the file pointers */
fclose(input_fp);
fclose(key_fp);
/* Declare and allocate pointers for GPU based parameters */
unsigned int *gpu_text;
unsigned int *gpu_key;
unsigned int *gpu_result;
unsigned int *gpu_threads;
unsigned int *gpu_blocks;
hipMalloc((void **)&gpu_text, array_size_in_bytes);
hipMalloc((void **)&gpu_key, array_size_in_bytes);
hipMalloc((void **)&gpu_result, array_size_in_bytes);
hipMalloc((void **)&gpu_threads, array_size_in_bytes);
hipMalloc((void **)&gpu_blocks, array_size_in_bytes);
/* Copy the CPU memory to the GPU memory */
hipMemcpy( gpu_text, cpu_text, array_size_in_bytes, hipMemcpyHostToDevice);
hipMemcpy( gpu_key, cpu_key, array_size_in_bytes, hipMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = array_size/threads_per_block;
const unsigned int num_threads = array_size/num_blocks;
/* Execute the encryption kernel */
encrypt<<<num_blocks, num_threads>>>(gpu_text, gpu_key, gpu_result, gpu_threads, gpu_blocks);
/* Copy the changed GPU memory back to the CPU */
hipMemcpy( cpu_result, gpu_result, array_size_in_bytes, hipMemcpyDeviceToHost);
hipMemcpy( cpu_threads, gpu_threads, array_size_in_bytes, hipMemcpyDeviceToHost);
hipMemcpy( cpu_blocks, gpu_blocks, array_size_in_bytes, hipMemcpyDeviceToHost);
/* Free the GPU memory */
hipFree(gpu_text);
hipFree(gpu_key);
hipFree(gpu_result);
hipFree(gpu_threads);
hipFree(gpu_blocks);
print_all_results(cpu_text, cpu_key, cpu_result, cpu_blocks, cpu_threads, array_size);
}
/**
* Prints the correct usage of this file
* @name is the name of the executable (argv[0])
*/
void print_usage(char *name)
{
printf("Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n", name);
}
/**
* Entry point for excution. Checks command line arguments and
* opens input files, then passes execution to subordinate main_sub()
*/
int main(int argc, char *argv[])
{
/* Check the number of arguments, print usage if wrong */
if(argc != 5) {
printf("Error: Incorrect number of command line arguments\n");
print_usage(argv[0]);
exit(-1);
}
/* Check the values for num_threads and threads_per_block */
int num_threads = atoi(argv[1]);
int threads_per_block = atoi(argv[2]);
if(num_threads <= 0 || threads_per_block <= 0) {
printf("Error: num_threads and threads_per_block must be integer > 0");
print_usage(argv[0]);
exit(-1);
}
/* Sanity check */
if(threads_per_block > num_threads) {
printf("Error: threads per block is greater than number of threads\n");
print_usage(argv[0]);
exit(-1);
}
char *input_filename = argv[3];
char *key_filename = argv[4];
/* Make sure the input text file and the key file are openable */
FILE *input_fp = fopen(input_filename, "r");
if(!input_fp) {
printf("Error: failed to open input file %s\n", argv[3]);
exit(-1);
}
FILE *key_fp = fopen(key_filename, "r");
if(!key_fp){
printf("Error: failed to open key file %s\n", argv[4]);
fclose(input_fp);
exit(-1);
}
/* Pass all arguments to the subordinate main function */
main_sub(num_threads, threads_per_block, input_fp, key_fp);
return EXIT_SUCCESS;
} | .text
.file "ceasar_cipher.hip"
.globl _Z22__device_stub__encryptPjS_S_S_S_ # -- Begin function _Z22__device_stub__encryptPjS_S_S_S_
.p2align 4, 0x90
.type _Z22__device_stub__encryptPjS_S_S_S_,@function
_Z22__device_stub__encryptPjS_S_S_S_: # @_Z22__device_stub__encryptPjS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7encryptPjS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z22__device_stub__encryptPjS_S_S_S_, .Lfunc_end0-_Z22__device_stub__encryptPjS_S_S_S_
.cfi_endproc
# -- End function
.globl _Z17print_all_resultsPjS_S_S_S_i # -- Begin function _Z17print_all_resultsPjS_S_S_S_i
.p2align 4, 0x90
.type _Z17print_all_resultsPjS_S_S_S_i,@function
_Z17print_all_resultsPjS_S_S_S_i: # @_Z17print_all_resultsPjS_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rax
movq %rsi, %r14
movq %rdi, %r15
movl %r9d, %ebp
movl %r9d, 12(%rsp) # 4-byte Spill
testl %r9d, %r9d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r8, %r13
xorl %ebx, %ebx
movq %rcx, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rcx,%rbx,4), %esi
movl (%r13,%rbx,4), %edx
movl (%r15,%rbx,4), %ecx
movl (%r14,%rbx,4), %r8d
movl (%rax,%rbx,4), %r9d
movl $.L.str, %edi
movq %rbp, %r12
movq %r15, %rbp
movq %r14, %r15
movq %rax, %r14
xorl %eax, %eax
callq printf
movq %r14, %rax
movq %r15, %r14
movq %rbp, %r15
movq %r12, %rbp
movq 16(%rsp), %rcx # 8-byte Reload
incq %rbx
cmpq %rbx, %r12
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %rax, %r12
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %r13d # 4-byte Reload
testl %r13d, %r13d
jle .LBB1_6
# %bb.4: # %.lr.ph36.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph36
# =>This Inner Loop Header: Depth=1
movl (%r15,%rbx,4), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_5
.LBB1_6: # %._crit_edge37
movl $.Lstr.1, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB1_9
# %bb.7: # %.lr.ph40.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_8: # %.lr.ph40
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_8
.LBB1_9: # %._crit_edge41
movl $.Lstr.2, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB1_12
# %bb.10: # %.lr.ph44.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph44
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbx,4), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_11
.LBB1_12: # %._crit_edge45
movl $.Lstr.3, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z17print_all_resultsPjS_S_S_S_i, .Lfunc_end1-_Z17print_all_resultsPjS_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z8main_subiiP8_IO_FILES0_ # -- Begin function _Z8main_subiiP8_IO_FILES0_
.p2align 4, 0x90
.type _Z8main_subiiP8_IO_FILES0_,@function
_Z8main_subiiP8_IO_FILES0_: # @_Z8main_subiiP8_IO_FILES0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $232, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rcx, %r13
movq %rdx, %r12
movl %esi, -96(%rbp) # 4-byte Spill
# kill: def $edi killed $edi def $rdi
leal (,%rdi,4), %eax
movl %eax, -92(%rbp) # 4-byte Spill
movl %edi, %ebx
movq %rsp, %rcx
leaq 15(,%rbx,4), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, %r15
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -48(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -128(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -120(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -112(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rdi, -136(%rbp) # 8-byte Spill
testl %edi, %edi
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r12, %rdi
callq fgetc
movl %eax, (%r15,%r14,4)
movq %r13, %rdi
callq fgetc
movq -48(%rbp), %rcx # 8-byte Reload
movl %eax, (%rcx,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r12, %rdi
callq fclose
movq %r13, %rdi
callq fclose
movslq -92(%rbp), %r13 # 4-byte Folded Reload
leaq -88(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -80(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -72(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -64(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -56(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -88(%rbp), %rdi
movq %r15, -104(%rbp) # 8-byte Spill
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq -80(%rbp), %rdi
movq -48(%rbp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq -136(%rbp), %rbx # 8-byte Reload
movl %ebx, %eax
cltd
idivl -96(%rbp) # 4-byte Folded Reload
movl %eax, %edi
movl %ebx, %eax
xorl %edx, %edx
divl %edi
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq -88(%rbp), %rax
movq -80(%rbp), %rcx
movq -72(%rbp), %rdx
movq -64(%rbp), %rsi
movq -56(%rbp), %rdi
movq %rax, -224(%rbp)
movq %rcx, -216(%rbp)
movq %rdx, -208(%rbp)
movq %rsi, -200(%rbp)
movq %rdi, -192(%rbp)
leaq -224(%rbp), %rax
movq %rax, -272(%rbp)
leaq -216(%rbp), %rax
movq %rax, -264(%rbp)
leaq -208(%rbp), %rax
movq %rax, -256(%rbp)
leaq -200(%rbp), %rax
movq %rax, -248(%rbp)
leaq -192(%rbp), %rax
movq %rax, -240(%rbp)
leaq -184(%rbp), %rdi
leaq -168(%rbp), %rsi
leaq -152(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -184(%rbp), %rsi
movl -176(%rbp), %edx
movq -168(%rbp), %rcx
movl -160(%rbp), %r8d
leaq -272(%rbp), %r9
movl $_Z7encryptPjS_S_S_S_, %edi
pushq -144(%rbp)
pushq -152(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_5:
movq -72(%rbp), %rsi
movq -128(%rbp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rsi
movq -120(%rbp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -56(%rbp), %rsi
movq -112(%rbp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
callq hipFree
movq -80(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq -104(%rbp), %rdi # 8-byte Reload
movq -48(%rbp), %rsi # 8-byte Reload
movq %r12, %rdx
movq %r14, %rcx
movq %r15, %r8
movl %ebx, %r9d
callq _Z17print_all_resultsPjS_S_S_S_i
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end2:
.size _Z8main_subiiP8_IO_FILES0_, .Lfunc_end2-_Z8main_subiiP8_IO_FILES0_
.cfi_endproc
# -- End function
.globl _Z11print_usagePc # -- Begin function _Z11print_usagePc
.p2align 4, 0x90
.type _Z11print_usagePc,@function
_Z11print_usagePc: # @_Z11print_usagePc
.cfi_startproc
# %bb.0:
movq %rdi, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z11print_usagePc, .Lfunc_end3-_Z11print_usagePc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $5, %edi
jne .LBB4_1
# %bb.4:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %r14d, %r14d
jle .LBB4_6
# %bb.5:
movq %rax, %r15
testl %r15d, %r15d
jle .LBB4_6
# %bb.7:
cmpl %r14d, %r15d
jg .LBB4_8
# %bb.9:
movq 24(%rbx), %rdi
movq 32(%rbx), %r13
movl $.L.str.10, %esi
callq fopen
testq %rax, %rax
je .LBB4_12
# %bb.10:
movq %rax, %r12
movl $.L.str.10, %esi
movq %r13, %rdi
callq fopen
testq %rax, %rax
je .LBB4_13
# %bb.11:
movl %r14d, %edi
movl %r15d, %esi
movq %r12, %rdx
movq %rax, %rcx
callq _Z8main_subiiP8_IO_FILES0_
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 48
movl $.Lstr.5, %edi
jmp .LBB4_2
.LBB4_6:
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
jmp .LBB4_3
.LBB4_8:
movl $.Lstr.4, %edi
.LBB4_2:
callq puts@PLT
.LBB4_3:
movq (%rbx), %rdi
callq _Z11print_usagePc
movl $-1, %edi
callq exit
.LBB4_12:
movq 24(%rbx), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB4_13:
movq 32(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq %r12, %rdi
callq fclose
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPjS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7encryptPjS_S_S_S_,@object # @_Z7encryptPjS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z7encryptPjS_S_S_S_
.p2align 3, 0x0
_Z7encryptPjS_S_S_S_:
.quad _Z22__device_stub__encryptPjS_S_S_S_
.size _Z7encryptPjS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Block %2u - Thread %2u Calculated: %c + %c = %c\n"
.size .L.str, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n"
.size .L.str.6, 75
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: num_threads and threads_per_block must be integer > 0"
.size .L.str.8, 61
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "r"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Error: failed to open input file %s\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Error: failed to open key file %s\n"
.size .L.str.12, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7encryptPjS_S_S_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nSummary:\n\nEncrypted text:"
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nWith Key:"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nResults in ciphertext:"
.size .Lstr.2, 25
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n"
.size .Lstr.3, 2
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error: threads per block is greater than number of threads"
.size .Lstr.4, 59
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error: Incorrect number of command line arguments"
.size .Lstr.5, 50
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__encryptPjS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7encryptPjS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7encryptPjS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R11, c[0x0][0x0], R8 ; /* 0x000000000b007a24 */
/* 0x001fca00078e0208 */
/*0060*/ IMAD.WIDE.U32 R2, R0, R13, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e000d */
/*0070*/ IMAD.WIDE.U32 R4, R0, R13.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x080fe400078e000d */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ LEA R6, R2, 0xe0000000, 0x18 ; /* 0xe000000002067811 */
/* 0x004fe200078ec0ff */
/*00b0*/ IMAD.WIDE.U32 R2, R0, R13, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe200078e000d */
/*00c0*/ LEA R7, R4, 0xe0000000, 0x18 ; /* 0xe000000004077811 */
/* 0x008fc600078ec0ff */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R13, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e000d */
/*00e0*/ SHF.R.S32.HI R6, RZ, 0x18, R6 ; /* 0x00000018ff067819 */
/* 0x000fc80000011406 */
/*00f0*/ LEA.HI.SX32 R7, R7, R6, 0x8 ; /* 0x0000000607077211 */
/* 0x000fe200078f42ff */
/*0100*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fd400000001ff */
/*0110*/ IMAD.HI R6, R7, -0x51b3bea3, R6 ; /* 0xae4c415d07067827 */
/* 0x000fca00078e0206 */
/*0120*/ SHF.R.U32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fc80000011606 */
/*0130*/ LEA.HI.SX32 R9, R6, R9, 0x1a ; /* 0x0000000906097211 */
/* 0x000fca00078fd2ff */
/*0140*/ IMAD R9, R9, -0x5e, R7 ; /* 0xffffffa209097824 */
/* 0x000fe400078e0207 */
/*0150*/ IMAD.WIDE.U32 R6, R0, R13, c[0x0][0x180] ; /* 0x0000600000067625 */
/* 0x000fc600078e000d */
/*0160*/ IADD3 R9, R9, 0x20, RZ ; /* 0x0000002009097810 */
/* 0x000fca0007ffe0ff */
/*0170*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0180*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x000fe8000c101904 */
/*0190*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7encryptPjS_S_S_S_
.globl _Z7encryptPjS_S_S_S_
.p2align 8
.type _Z7encryptPjS_S_S_S_,@function
_Z7encryptPjS_S_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v3, v3, 24, 0xe0000000
s_waitcnt vmcnt(0)
v_lshl_add_u32 v4, v4, 24, 0xe0000000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 24, v3
v_ashrrev_i32_e32 v4, 24, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v4, v3
v_mul_hi_i32 v3, v5, 0xae4c415d
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v5
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_lo_u32 v6, v3, 0x5e
v_add_co_u32 v3, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v8, v5, v6
v_add_co_u32 v5, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v2, vcc_lo
v_dual_mov_b32 v7, s15 :: v_dual_add_nc_u32 v8, 32, v8
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[3:4], v8, off
global_store_b32 v[5:6], v0, off
global_store_b32 v[1:2], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPjS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7encryptPjS_S_S_S_, .Lfunc_end0-_Z7encryptPjS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPjS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7encryptPjS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001647c_00000000-6_ceasar_cipher.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Block %2u - Thread %2u Calculated: %c + %c = %c\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nSummary:\n\nEncrypted text:\n"
.LC2:
.string "%c"
.LC3:
.string "\n\nWith Key:\n"
.LC4:
.string "\n\nResults in ciphertext:\n"
.LC5:
.string "\n\n"
.text
.globl _Z17print_all_resultsPjS_S_S_S_i
.type _Z17print_all_resultsPjS_S_S_S_i, @function
_Z17print_all_resultsPjS_S_S_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, 8(%rsp)
testl %r9d, %r9d
jle .L4
movq %rdi, %r12
movq %rdx, %rbp
movq %rcx, %r14
movq %r8, %r15
movslq %r9d, %r9
leaq 0(,%r9,4), %r13
movl $0, %ebx
.L5:
movl (%r15,%rbx), %ecx
movl (%r14,%rbx), %edx
subq $8, %rsp
.cfi_def_cfa_offset 88
movl 0(%rbp,%rbx), %eax
pushq %rax
.cfi_def_cfa_offset 96
movq 24(%rsp), %rax
movl (%rax,%rbx), %r9d
movl (%r12,%rbx), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 80
cmpq %r13, %rbx
jne .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
addq %r13, %r12
leaq .LC2(%rip), %r14
.L6:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L6
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %r12
movq %r12, %rbx
addq %r13, %r12
leaq .LC2(%rip), %r14
.L7:
movl (%rbx), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L7
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq %r13, %rbp
leaq .LC2(%rip), %r12
.L8:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L8
.L9:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2057:
.size _Z17print_all_resultsPjS_S_S_S_i, .-_Z17print_all_resultsPjS_S_S_S_i
.section .rodata.str1.8
.align 8
.LC6:
.string "Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n"
.text
.globl _Z11print_usagePc
.type _Z11print_usagePc, @function
_Z11print_usagePc:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_usagePc, .-_Z11print_usagePc
.globl _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
.type _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_, @function
_Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7encryptPjS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_, .-_Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
.globl _Z7encryptPjS_S_S_S_
.type _Z7encryptPjS_S_S_S_, @function
_Z7encryptPjS_S_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7encryptPjS_S_S_S_, .-_Z7encryptPjS_S_S_S_
.globl _Z8main_subiiP8_IO_FILES0_
.type _Z8main_subiiP8_IO_FILES0_, @function
_Z8main_subiiP8_IO_FILES0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $152, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -132(%rbp)
movl %esi, -156(%rbp)
movq %rdx, %r15
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movslq %edi, %r13
leal 0(,%rdi,4), %eax
movl %eax, -136(%rbp)
salq $2, %r13
leaq 15(%r13), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L27:
cmpq %rdx, %rsp
je .L28
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L27
.L28:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L29
orq $0, -8(%rsp,%rax)
.L29:
movq %rsp, -144(%rbp)
leaq 15(%r13), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L30:
cmpq %rdx, %rsp
je .L31
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L30
.L31:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L32
orq $0, -8(%rsp,%rax)
.L32:
movq %rsp, -152(%rbp)
leaq 15(%r13), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L33:
cmpq %rdx, %rsp
je .L34
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L33
.L34:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L35
orq $0, -8(%rsp,%rax)
.L35:
movq %rsp, -168(%rbp)
leaq 15(%r13), %rax
movq %rax, %rdx
andq $-16, %rdx
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L36:
cmpq %rcx, %rsp
je .L37
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L36
.L37:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L38
orq $0, -8(%rsp,%rax)
.L38:
movq %rsp, -176(%rbp)
leaq 15(%r13), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L39:
cmpq %rcx, %rsp
je .L40
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L39
.L40:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L41
orq $0, -8(%rsp,%rdx)
.L41:
movq %rsp, -184(%rbp)
cmpl $0, -132(%rbp)
jle .L42
movq -144(%rbp), %rax
movq %rax, %rbx
movq -152(%rbp), %r12
addq %rax, %r13
.L43:
movq %r15, %rdi
call fgetc@PLT
movl %eax, (%rbx)
movq %r14, %rdi
call fgetc@PLT
movl %eax, (%r12)
addq $4, %rbx
addq $4, %r12
cmpq %r13, %rbx
jne .L43
.L42:
movq %r15, %rdi
call fclose@PLT
movq %r14, %rdi
call fclose@PLT
movslq -136(%rbp), %rbx
leaq -120(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -112(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -104(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -144(%rbp), %rsi
movq -120(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -152(%rbp), %rsi
movq -112(%rbp), %rdi
call cudaMemcpy@PLT
movl -132(%rbp), %eax
cltd
idivl -156(%rbp)
movl %eax, %ecx
movl -132(%rbp), %eax
movl $0, %edx
divl %ecx
movl %eax, -68(%rbp)
movl $1, -64(%rbp)
movl %ecx, -80(%rbp)
movl $1, -76(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movl $2, %ecx
movq %rbx, %rdx
movq -104(%rbp), %rsi
movq -168(%rbp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -96(%rbp), %rsi
movq -176(%rbp), %r14
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -88(%rbp), %rsi
movq -184(%rbp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq -120(%rbp), %rdi
call cudaFree@PLT
movq -112(%rbp), %rdi
call cudaFree@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movl -132(%rbp), %r9d
movq %r14, %r8
movq %rbx, %rcx
movq %r15, %rdx
movq -152(%rbp), %rsi
movq -144(%rbp), %rdi
call _Z17print_all_resultsPjS_S_S_S_i
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L49
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L48:
.cfi_restore_state
movq -88(%rbp), %r8
movq -96(%rbp), %rcx
movq -104(%rbp), %rdx
movq -112(%rbp), %rsi
movq -120(%rbp), %rdi
call _Z34__device_stub__Z7encryptPjS_S_S_S_PjS_S_S_S_
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8main_subiiP8_IO_FILES0_, .-_Z8main_subiiP8_IO_FILES0_
.section .rodata.str1.8
.align 8
.LC7:
.string "Error: Incorrect number of command line arguments\n"
.align 8
.LC8:
.string "Error: num_threads and threads_per_block must be integer > 0"
.align 8
.LC9:
.string "Error: threads per block is greater than number of threads\n"
.section .rodata.str1.1
.LC10:
.string "r"
.section .rodata.str1.8
.align 8
.LC11:
.string "Error: failed to open input file %s\n"
.align 8
.LC12:
.string "Error: failed to open key file %s\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %rbx
cmpl $5, %edi
jne .L59
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movl %eax, %r12d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
testl %ebp, %ebp
jle .L57
testl %eax, %eax
jle .L57
cmpl %ebp, %eax
jg .L60
movq 32(%rbx), %r14
movq 24(%rbx), %rdi
leaq .LC10(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L61
leaq .LC10(%rip), %rsi
movq %r14, %rdi
call fopen@PLT
movq %rax, %rcx
testq %rax, %rax
je .L62
movq %rbp, %rdx
movl %r13d, %esi
movl %r12d, %edi
call _Z8main_subiiP8_IO_FILES0_
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call _Z11print_usagePc
movl $-1, %edi
call exit@PLT
.L57:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call _Z11print_usagePc
movl $-1, %edi
call exit@PLT
.L60:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdi
call _Z11print_usagePc
movl $-1, %edi
call exit@PLT
.L61:
movq 24(%rbx), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L62:
movq 32(%rbx), %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call fclose@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7encryptPjS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPjS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ceasar_cipher.hip"
.globl _Z22__device_stub__encryptPjS_S_S_S_ # -- Begin function _Z22__device_stub__encryptPjS_S_S_S_
.p2align 4, 0x90
.type _Z22__device_stub__encryptPjS_S_S_S_,@function
_Z22__device_stub__encryptPjS_S_S_S_: # @_Z22__device_stub__encryptPjS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7encryptPjS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z22__device_stub__encryptPjS_S_S_S_, .Lfunc_end0-_Z22__device_stub__encryptPjS_S_S_S_
.cfi_endproc
# -- End function
.globl _Z17print_all_resultsPjS_S_S_S_i # -- Begin function _Z17print_all_resultsPjS_S_S_S_i
.p2align 4, 0x90
.type _Z17print_all_resultsPjS_S_S_S_i,@function
_Z17print_all_resultsPjS_S_S_S_i: # @_Z17print_all_resultsPjS_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rax
movq %rsi, %r14
movq %rdi, %r15
movl %r9d, %ebp
movl %r9d, 12(%rsp) # 4-byte Spill
testl %r9d, %r9d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r8, %r13
xorl %ebx, %ebx
movq %rcx, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rcx,%rbx,4), %esi
movl (%r13,%rbx,4), %edx
movl (%r15,%rbx,4), %ecx
movl (%r14,%rbx,4), %r8d
movl (%rax,%rbx,4), %r9d
movl $.L.str, %edi
movq %rbp, %r12
movq %r15, %rbp
movq %r14, %r15
movq %rax, %r14
xorl %eax, %eax
callq printf
movq %r14, %rax
movq %r15, %r14
movq %rbp, %r15
movq %r12, %rbp
movq 16(%rsp), %rcx # 8-byte Reload
incq %rbx
cmpq %rbx, %r12
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %rax, %r12
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %r13d # 4-byte Reload
testl %r13d, %r13d
jle .LBB1_6
# %bb.4: # %.lr.ph36.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph36
# =>This Inner Loop Header: Depth=1
movl (%r15,%rbx,4), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_5
.LBB1_6: # %._crit_edge37
movl $.Lstr.1, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB1_9
# %bb.7: # %.lr.ph40.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_8: # %.lr.ph40
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_8
.LBB1_9: # %._crit_edge41
movl $.Lstr.2, %edi
callq puts@PLT
testl %r13d, %r13d
jle .LBB1_12
# %bb.10: # %.lr.ph44.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph44
# =>This Inner Loop Header: Depth=1
movl (%r12,%rbx,4), %edi
callq putchar@PLT
incq %rbx
cmpq %rbx, %rbp
jne .LBB1_11
.LBB1_12: # %._crit_edge45
movl $.Lstr.3, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z17print_all_resultsPjS_S_S_S_i, .Lfunc_end1-_Z17print_all_resultsPjS_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z8main_subiiP8_IO_FILES0_ # -- Begin function _Z8main_subiiP8_IO_FILES0_
.p2align 4, 0x90
.type _Z8main_subiiP8_IO_FILES0_,@function
_Z8main_subiiP8_IO_FILES0_: # @_Z8main_subiiP8_IO_FILES0_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $232, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rcx, %r13
movq %rdx, %r12
movl %esi, -96(%rbp) # 4-byte Spill
# kill: def $edi killed $edi def $rdi
leal (,%rdi,4), %eax
movl %eax, -92(%rbp) # 4-byte Spill
movl %edi, %ebx
movq %rsp, %rcx
leaq 15(,%rbx,4), %rax
andq $-16, %rax
subq %rax, %rcx
movq %rcx, %r15
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -48(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -128(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -120(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rsp, %rcx
subq %rax, %rcx
movq %rcx, -112(%rbp) # 8-byte Spill
movq %rcx, %rsp
movq %rdi, -136(%rbp) # 8-byte Spill
testl %edi, %edi
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r12, %rdi
callq fgetc
movl %eax, (%r15,%r14,4)
movq %r13, %rdi
callq fgetc
movq -48(%rbp), %rcx # 8-byte Reload
movl %eax, (%rcx,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r12, %rdi
callq fclose
movq %r13, %rdi
callq fclose
movslq -92(%rbp), %r13 # 4-byte Folded Reload
leaq -88(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -80(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -72(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -64(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq -56(%rbp), %rdi
movq %r13, %rsi
callq hipMalloc
movq -88(%rbp), %rdi
movq %r15, -104(%rbp) # 8-byte Spill
movq %r15, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq -80(%rbp), %rdi
movq -48(%rbp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq -136(%rbp), %rbx # 8-byte Reload
movl %ebx, %eax
cltd
idivl -96(%rbp) # 4-byte Folded Reload
movl %eax, %edi
movl %ebx, %eax
xorl %edx, %edx
divl %edi
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq -88(%rbp), %rax
movq -80(%rbp), %rcx
movq -72(%rbp), %rdx
movq -64(%rbp), %rsi
movq -56(%rbp), %rdi
movq %rax, -224(%rbp)
movq %rcx, -216(%rbp)
movq %rdx, -208(%rbp)
movq %rsi, -200(%rbp)
movq %rdi, -192(%rbp)
leaq -224(%rbp), %rax
movq %rax, -272(%rbp)
leaq -216(%rbp), %rax
movq %rax, -264(%rbp)
leaq -208(%rbp), %rax
movq %rax, -256(%rbp)
leaq -200(%rbp), %rax
movq %rax, -248(%rbp)
leaq -192(%rbp), %rax
movq %rax, -240(%rbp)
leaq -184(%rbp), %rdi
leaq -168(%rbp), %rsi
leaq -152(%rbp), %rdx
leaq -144(%rbp), %rcx
callq __hipPopCallConfiguration
movq -184(%rbp), %rsi
movl -176(%rbp), %edx
movq -168(%rbp), %rcx
movl -160(%rbp), %r8d
leaq -272(%rbp), %r9
movl $_Z7encryptPjS_S_S_S_, %edi
pushq -144(%rbp)
pushq -152(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_5:
movq -72(%rbp), %rsi
movq -128(%rbp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -64(%rbp), %rsi
movq -120(%rbp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -56(%rbp), %rsi
movq -112(%rbp), %r14 # 8-byte Reload
movq %r14, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq -88(%rbp), %rdi
callq hipFree
movq -80(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq -104(%rbp), %rdi # 8-byte Reload
movq -48(%rbp), %rsi # 8-byte Reload
movq %r12, %rdx
movq %r14, %rcx
movq %r15, %r8
movl %ebx, %r9d
callq _Z17print_all_resultsPjS_S_S_S_i
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end2:
.size _Z8main_subiiP8_IO_FILES0_, .Lfunc_end2-_Z8main_subiiP8_IO_FILES0_
.cfi_endproc
# -- End function
.globl _Z11print_usagePc # -- Begin function _Z11print_usagePc
.p2align 4, 0x90
.type _Z11print_usagePc,@function
_Z11print_usagePc: # @_Z11print_usagePc
.cfi_startproc
# %bb.0:
movq %rdi, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z11print_usagePc, .Lfunc_end3-_Z11print_usagePc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $5, %edi
jne .LBB4_1
# %bb.4:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %r14d, %r14d
jle .LBB4_6
# %bb.5:
movq %rax, %r15
testl %r15d, %r15d
jle .LBB4_6
# %bb.7:
cmpl %r14d, %r15d
jg .LBB4_8
# %bb.9:
movq 24(%rbx), %rdi
movq 32(%rbx), %r13
movl $.L.str.10, %esi
callq fopen
testq %rax, %rax
je .LBB4_12
# %bb.10:
movq %rax, %r12
movl $.L.str.10, %esi
movq %r13, %rdi
callq fopen
testq %rax, %rax
je .LBB4_13
# %bb.11:
movl %r14d, %edi
movl %r15d, %esi
movq %r12, %rdx
movq %rax, %rcx
callq _Z8main_subiiP8_IO_FILES0_
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 48
movl $.Lstr.5, %edi
jmp .LBB4_2
.LBB4_6:
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
jmp .LBB4_3
.LBB4_8:
movl $.Lstr.4, %edi
.LBB4_2:
callq puts@PLT
.LBB4_3:
movq (%rbx), %rdi
callq _Z11print_usagePc
movl $-1, %edi
callq exit
.LBB4_12:
movq 24(%rbx), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB4_13:
movq 32(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq %r12, %rdi
callq fclose
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPjS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7encryptPjS_S_S_S_,@object # @_Z7encryptPjS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z7encryptPjS_S_S_S_
.p2align 3, 0x0
_Z7encryptPjS_S_S_S_:
.quad _Z22__device_stub__encryptPjS_S_S_S_
.size _Z7encryptPjS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Block %2u - Thread %2u Calculated: %c + %c = %c\n"
.size .L.str, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s <total_num_threads> <threads_per_block> <input_file> <key_file>\n"
.size .L.str.6, 75
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: num_threads and threads_per_block must be integer > 0"
.size .L.str.8, 61
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "r"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Error: failed to open input file %s\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Error: failed to open key file %s\n"
.size .L.str.12, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7encryptPjS_S_S_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nSummary:\n\nEncrypted text:"
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nWith Key:"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n\nResults in ciphertext:"
.size .Lstr.2, 25
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n"
.size .Lstr.3, 2
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error: threads per block is greater than number of threads"
.size .Lstr.4, 59
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error: Incorrect number of command line arguments"
.size .Lstr.5, 50
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__encryptPjS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7encryptPjS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
// #include <demo_util.h>
// #include <cuda_util.h>
#define CLOCK_RATE 1076000 // Titan
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
__device__ void sleep(float t)
{
clock_t t0 = clock64();
clock_t t1 = t0;
while ((t1 - t0)/(CLOCK_RATE*1000.0f) < t)
{
t1 = clock64();
}
}
__global__ void worker()
{
sleep(1.0);
}
int main(int argc, char** argv)
{
cudaDeviceProp prop;
clock_t clock_rate;
int mp;
double etime, start;
cudaGetDeviceProperties(&prop, 0); /* Only look at first processor */
printf("Name: %s\n", prop.name );
mp = prop.multiProcessorCount;
clock_rate = prop.clockRate;
printf("Clock rate = %d\n",clock_rate);
int threads_per_block = 16;
int blocks_per_sm = 1;
dim3 block(threads_per_block);
dim3 grid(mp*blocks_per_sm);
start = cpuSecond();
worker<<<grid,block>>>();
cudaDeviceSynchronize();
etime = cpuSecond() - start;
int total_threads = block.x*grid.x;
printf("Device has %d SMs\n",mp);
printf("%27s %12d\n", "Threads per block",block.x*block.y);
printf("%27s %12d\n", "Total number of blocks",grid.x);
printf("%27s %12d\n", "Total number of threads",total_threads);
printf("%27s %12.3f (s)\n","GPU Kernel Time (scaled)", etime);
printf("\n");
cudaDeviceReset();
} | code for sm_80
Function : _Z6workerv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fca0000015000 */
/*0020*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*0030*/ IADD3 R4, P0, -R2, R4, RZ ; /* 0x0000000402047210 */
/* 0x000fe20007f1e1ff */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x307f7676 ; /* 0x307f7676ff077424 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4e8044ea ; /* 0x4e8044eaff007424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.X R5, R5, 0x1, ~R3, P0 ; /* 0x0000000105057824 */
/* 0x000fe400000e0e03 */
/*0070*/ FFMA R0, R7, -R0, 1 ; /* 0x3f80000007007423 */
/* 0x000fe40000000800 */
/*0080*/ I2F.S64 R4, R4 ; /* 0x0000000400047312 */
/* 0x000e240000301400 */
/*0090*/ FFMA R7, R0, R7, 9.2936802698062592754e-10 ; /* 0x307f767600077423 */
/* 0x000fcc0000000007 */
/*00a0*/ FCHK P0, R4, 1.07600000000000000000e+09 ; /* 0x4e8044ea04007902 */
/* 0x001e220000000000 */
/*00b0*/ FFMA R0, R4, R7, RZ ; /* 0x0000000704007223 */
/* 0x000fc800000000ff */
/*00c0*/ FFMA R6, R0, -1.07600000000000000000e+09, R4 ; /* 0xce8044ea00067823 */
/* 0x000fc80000000004 */
/*00d0*/ FFMA R0, R7, R6, R0 ; /* 0x0000000607007223 */
/* 0x000fe20000000000 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*00f0*/ MOV R0, 0x110 ; /* 0x0000011000007802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x150 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x001fca00078e0006 */
/*0120*/ FSETP.GEU.AND P0, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fda0003f0e000 */
/*0130*/ @!P0 BRA 0x20 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*0170*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0180*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, !PT ; /* 0x000000fd0800780c */
/* 0x000fda0007f04470 */
/*01a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*01b0*/ @!P0 BRA 0x2b0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*01c0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*01d0*/ @P0 BRA 0x680 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4e8044ea ; /* 0x4e8044eaff077424 */
/* 0x000fca00078e00ff */
/*01f0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0200*/ @!P0 BRA 0x660 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0210*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x640 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0230*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1d200 */
/*0240*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0250*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0260*/ @P0 BRA 0x610 ; /* 0x000003a000000947 */
/* 0x000fea0003800000 */
/*0270*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f06270 */
/*0280*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0290*/ @!P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004068823 */
/* 0x000fe400000000ff */
/*02a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*02b0*/ UMOV UR4, 0x4e8044ea ; /* 0x4e8044ea00047882 */
/* 0x000fe20000000000 */
/*02c0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ UIADD3 UR4, UR4, -0xf000000, URZ ; /* 0xf100000004047890 */
/* 0x000fc6000fffe03f */
/*02e0*/ IADD3 R7, R7, -0x1e, R5 ; /* 0xffffffe207077810 */
/* 0x000fe20007ffe005 */
/*02f0*/ IMAD R6, R5, -0x800000, R6 ; /* 0xff80000005067824 */
/* 0x000fe400078e0206 */
/*0300*/ FADD.FTZ R9, -RZ, -UR4 ; /* 0x80000004ff097e21 */
/* 0x000fc60008010100 */
/*0310*/ MUFU.RCP R4, UR4 ; /* 0x0000000400047d08 */
/* 0x000e240008001000 */
/*0320*/ FFMA R11, R4, R9, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000009 */
/*0330*/ FFMA R11, R4, R11, R4 ; /* 0x0000000b040b7223 */
/* 0x000fc80000000004 */
/*0340*/ FFMA R4, R6, R11, RZ ; /* 0x0000000b06047223 */
/* 0x000fc800000000ff */
/*0350*/ FFMA R8, R9, R4, R6 ; /* 0x0000000409087223 */
/* 0x000fc80000000006 */
/*0360*/ FFMA R8, R11, R8, R4 ; /* 0x000000080b087223 */
/* 0x000fc80000000004 */
/*0370*/ FFMA R9, R9, R8, R6 ; /* 0x0000000809097223 */
/* 0x000fc80000000006 */
/*0380*/ FFMA R6, R11, R9, R8 ; /* 0x000000090b067223 */
/* 0x000fca0000000008 */
/*0390*/ SHF.R.U32.HI R4, RZ, 0x17, R6 ; /* 0x00000017ff047819 */
/* 0x000fc80000011606 */
/*03a0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*03b0*/ IMAD.IADD R10, R4, 0x1, R7 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0207 */
/*03c0*/ IADD3 R4, R10, -0x1, RZ ; /* 0xffffffff0a047810 */
/* 0x000fc80007ffe0ff */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*03e0*/ @!P0 BRA 0x5f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0400*/ @P0 BRA 0x5c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0420*/ @P0 BRA 0x690 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0440*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0450*/ @!P0 BRA 0x690 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0460*/ FFMA.RZ R4, R11.reuse, R9.reuse, R8 ; /* 0x000000090b047223 */
/* 0x0c0fe2000000c008 */
/*0470*/ ISETP.NE.AND P2, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x040fe20003f45270 */
/*0480*/ IMAD.MOV R7, RZ, RZ, -R10 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0a */
/*0490*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25270 */
/*04a0*/ LOP3.LUT R5, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04057812 */
/* 0x000fe200078ec0ff */
/*04b0*/ FFMA.RP R4, R11.reuse, R9.reuse, R8.reuse ; /* 0x000000090b047223 */
/* 0x1c0fe40000008008 */
/*04c0*/ FFMA.RM R11, R11, R9, R8 ; /* 0x000000090b0b7223 */
/* 0x000fe20000004008 */
/*04d0*/ IADD3 R8, R10, 0x20, RZ ; /* 0x000000200a087810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fc400078efcff */
/*04f0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x000fe40003f1d000 */
/*0500*/ SHF.L.U32 R8, R5, R8, RZ ; /* 0x0000000805087219 */
/* 0x000fe400000006ff */
/*0510*/ SEL R4, R7, RZ, P2 ; /* 0x000000ff07047207 */
/* 0x000fe40001000000 */
/*0520*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0530*/ SHF.R.U32.HI R4, RZ, R4, R5 ; /* 0x00000004ff047219 */
/* 0x000fe40000011605 */
/*0540*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0550*/ SHF.R.U32.HI R8, RZ, 0x1, R4 ; /* 0x00000001ff087819 */
/* 0x000fe40000011604 */
/*0560*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0570*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0580*/ LOP3.LUT R5, R5, R4, RZ, 0xc0, !PT ; /* 0x0000000405057212 */
/* 0x000fca00078ec0ff */
/*0590*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*05a0*/ LOP3.LUT R6, R5, R6, RZ, 0xfc, !PT ; /* 0x0000000605067212 */
/* 0x000fe200078efcff */
/*05b0*/ BRA 0x690 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*05c0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*05d0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*05e0*/ BRA 0x690 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD R6, R7, 0x800000, R6 ; /* 0x0080000007067824 */
/* 0x000fe200078e0206 */
/*0600*/ BRA 0x690 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0610*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*0620*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0630*/ BRA 0x690 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0640*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*0650*/ BRA 0x690 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0660*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0670*/ BRA 0x690 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0680*/ FADD.FTZ R6, R4, 1.07600000000000000000e+09 ; /* 0x4e8044ea04067421 */
/* 0x000fe40000010000 */
/*0690*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*06b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff94004007950 */
/* 0x000fea0003c3ffff */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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