system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
// #include <demo_util.h>
// #include <cuda_util.h>
#define CLOCK_RATE 1076000 // Titan
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
__device__ void sleep(float t)
{
clock_t t0 = clock64();
clock_t t1 = t0;
while ((t1 - t0)/(CLOCK_RATE*1000.0f) < t)
{
t1 = clock64();
}
}
__global__ void worker()
{
sleep(1.0);
}
int main(int argc, char** argv)
{
cudaDeviceProp prop;
clock_t clock_rate;
int mp;
double etime, start;
cudaGetDeviceProperties(&prop, 0); /* Only look at first processor */
printf("Name: %s\n", prop.name );
mp = prop.multiProcessorCount;
clock_rate = prop.clockRate;
printf("Clock rate = %d\n",clock_rate);
int threads_per_block = 16;
int blocks_per_sm = 1;
dim3 block(threads_per_block);
dim3 grid(mp*blocks_per_sm);
start = cpuSecond();
worker<<<grid,block>>>();
cudaDeviceSynchronize();
etime = cpuSecond() - start;
int total_threads = block.x*grid.x;
printf("Device has %d SMs\n",mp);
printf("%27s %12d\n", "Threads per block",block.x*block.y);
printf("%27s %12d\n", "Total number of blocks",grid.x);
printf("%27s %12d\n", "Total number of threads",total_threads);
printf("%27s %12.3f (s)\n","GPU Kernel Time (scaled)", etime);
printf("\n");
cudaDeviceReset();
} | .file "tmpxft_000244bf_00000000-6_sm_question.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z5sleepf
.type _Z5sleepf, @function
_Z5sleepf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5sleepf, .-_Z5sleepf
.globl _Z24__device_stub__Z6workervv
.type _Z24__device_stub__Z6workervv, @function
_Z24__device_stub__Z6workervv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6workerv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6workervv, .-_Z24__device_stub__Z6workervv
.globl _Z6workerv
.type _Z6workerv, @function
_Z6workerv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6workervv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6workerv, .-_Z6workerv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Name: %s\n"
.LC2:
.string "Clock rate = %d\n"
.LC3:
.string "Device has %d SMs\n"
.LC4:
.string "Threads per block"
.LC5:
.string "%27s %12d\n"
.LC6:
.string "Total number of blocks"
.LC7:
.string "Total number of threads"
.LC8:
.string "GPU Kernel Time (scaled)"
.LC9:
.string "%27s %12.3f (s)\n"
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1096, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 436(%rsp), %ebx
movslq 396(%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 32(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl %ebx, 36(%rsp)
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
call cudaDeviceSynchronize@PLT
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
leaq .LC6(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
sall $4, %ecx
leaq .LC7(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call _Z24__device_stub__Z6workervv
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6workerv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6workerv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
// #include <demo_util.h>
// #include <cuda_util.h>
#define CLOCK_RATE 1076000 // Titan
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
__device__ void sleep(float t)
{
clock_t t0 = clock64();
clock_t t1 = t0;
while ((t1 - t0)/(CLOCK_RATE*1000.0f) < t)
{
t1 = clock64();
}
}
__global__ void worker()
{
sleep(1.0);
}
int main(int argc, char** argv)
{
cudaDeviceProp prop;
clock_t clock_rate;
int mp;
double etime, start;
cudaGetDeviceProperties(&prop, 0); /* Only look at first processor */
printf("Name: %s\n", prop.name );
mp = prop.multiProcessorCount;
clock_rate = prop.clockRate;
printf("Clock rate = %d\n",clock_rate);
int threads_per_block = 16;
int blocks_per_sm = 1;
dim3 block(threads_per_block);
dim3 grid(mp*blocks_per_sm);
start = cpuSecond();
worker<<<grid,block>>>();
cudaDeviceSynchronize();
etime = cpuSecond() - start;
int total_threads = block.x*grid.x;
printf("Device has %d SMs\n",mp);
printf("%27s %12d\n", "Threads per block",block.x*block.y);
printf("%27s %12d\n", "Total number of blocks",grid.x);
printf("%27s %12d\n", "Total number of threads",total_threads);
printf("%27s %12.3f (s)\n","GPU Kernel Time (scaled)", etime);
printf("\n");
cudaDeviceReset();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
// #include <demo_util.h>
// #include <cuda_util.h>
#define CLOCK_RATE 1076000 // Titan
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
__device__ void sleep(float t)
{
clock_t t0 = clock64();
clock_t t1 = t0;
while ((t1 - t0)/(CLOCK_RATE*1000.0f) < t)
{
t1 = clock64();
}
}
__global__ void worker()
{
sleep(1.0);
}
int main(int argc, char** argv)
{
hipDeviceProp_t prop;
clock_t clock_rate;
int mp;
double etime, start;
hipGetDeviceProperties(&prop, 0); /* Only look at first processor */
printf("Name: %s\n", prop.name );
mp = prop.multiProcessorCount;
clock_rate = prop.clockRate;
printf("Clock rate = %d\n",clock_rate);
int threads_per_block = 16;
int blocks_per_sm = 1;
dim3 block(threads_per_block);
dim3 grid(mp*blocks_per_sm);
start = cpuSecond();
worker<<<grid,block>>>();
hipDeviceSynchronize();
etime = cpuSecond() - start;
int total_threads = block.x*grid.x;
printf("Device has %d SMs\n",mp);
printf("%27s %12d\n", "Threads per block",block.x*block.y);
printf("%27s %12d\n", "Total number of blocks",grid.x);
printf("%27s %12d\n", "Total number of threads",total_threads);
printf("%27s %12.3f (s)\n","GPU Kernel Time (scaled)", etime);
printf("\n");
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
// #include <demo_util.h>
// #include <cuda_util.h>
#define CLOCK_RATE 1076000 // Titan
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
__device__ void sleep(float t)
{
clock_t t0 = clock64();
clock_t t1 = t0;
while ((t1 - t0)/(CLOCK_RATE*1000.0f) < t)
{
t1 = clock64();
}
}
__global__ void worker()
{
sleep(1.0);
}
int main(int argc, char** argv)
{
hipDeviceProp_t prop;
clock_t clock_rate;
int mp;
double etime, start;
hipGetDeviceProperties(&prop, 0); /* Only look at first processor */
printf("Name: %s\n", prop.name );
mp = prop.multiProcessorCount;
clock_rate = prop.clockRate;
printf("Clock rate = %d\n",clock_rate);
int threads_per_block = 16;
int blocks_per_sm = 1;
dim3 block(threads_per_block);
dim3 grid(mp*blocks_per_sm);
start = cpuSecond();
worker<<<grid,block>>>();
hipDeviceSynchronize();
etime = cpuSecond() - start;
int total_threads = block.x*grid.x;
printf("Device has %d SMs\n",mp);
printf("%27s %12d\n", "Threads per block",block.x*block.y);
printf("%27s %12d\n", "Total number of blocks",grid.x);
printf("%27s %12d\n", "Total number of threads",total_threads);
printf("%27s %12.3f (s)\n","GPU Kernel Time (scaled)", etime);
printf("\n");
hipDeviceReset();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6workerv
.globl _Z6workerv
.p2align 8
.type _Z6workerv,@function
_Z6workerv:
s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[2:3], s[0:1]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_4
.LBB0_2:
s_sub_u32 s2, s2, s0
s_subb_u32 s3, s3, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s2, s3
s_cls_i32 s5, s3
s_ashr_i32 s4, s4, 31
s_add_i32 s5, s5, -1
s_add_i32 s4, s4, 32
s_min_u32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], s4
s_min_u32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_mov_b32 s3, -1
v_cvt_f32_i32_e32 v0, s2
s_sub_i32 s2, 32, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_ldexp_f32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v1, null, 0x4e8044ea, 0x4e8044ea, v0
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v2
v_div_scale_f32 v3, vcc_lo, v0, 0x4e8044ea, v0
v_mul_f32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v1, v4, v3
v_fmac_f32_e32 v4, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v4, v3
v_div_fmas_f32 v1, v1, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v1, 0x4e8044ea, v0
v_cmp_ngt_f32_e32 vcc_lo, 1.0, v0
s_cbranch_vccnz .LBB0_1
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s3, 0
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6workerv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6workerv, .Lfunc_end0-_Z6workerv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6workerv
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6workerv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
// #include <demo_util.h>
// #include <cuda_util.h>
#define CLOCK_RATE 1076000 // Titan
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
__device__ void sleep(float t)
{
clock_t t0 = clock64();
clock_t t1 = t0;
while ((t1 - t0)/(CLOCK_RATE*1000.0f) < t)
{
t1 = clock64();
}
}
__global__ void worker()
{
sleep(1.0);
}
int main(int argc, char** argv)
{
hipDeviceProp_t prop;
clock_t clock_rate;
int mp;
double etime, start;
hipGetDeviceProperties(&prop, 0); /* Only look at first processor */
printf("Name: %s\n", prop.name );
mp = prop.multiProcessorCount;
clock_rate = prop.clockRate;
printf("Clock rate = %d\n",clock_rate);
int threads_per_block = 16;
int blocks_per_sm = 1;
dim3 block(threads_per_block);
dim3 grid(mp*blocks_per_sm);
start = cpuSecond();
worker<<<grid,block>>>();
hipDeviceSynchronize();
etime = cpuSecond() - start;
int total_threads = block.x*grid.x;
printf("Device has %d SMs\n",mp);
printf("%27s %12d\n", "Threads per block",block.x*block.y);
printf("%27s %12d\n", "Total number of blocks",grid.x);
printf("%27s %12d\n", "Total number of threads",total_threads);
printf("%27s %12.3f (s)\n","GPU Kernel Time (scaled)", etime);
printf("\n");
hipDeviceReset();
} | .text
.file "sm_question.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z21__device_stub__workerv # -- Begin function _Z21__device_stub__workerv
.p2align 4, 0x90
.type _Z21__device_stub__workerv,@function
_Z21__device_stub__workerv: # @_Z21__device_stub__workerv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6workerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z21__device_stub__workerv, .Lfunc_end1-_Z21__device_stub__workerv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 72(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 460(%rsp), %ebx
movslq 420(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movabsq $4294967296, %r14 # imm = 0x100000000
movq %rbx, %r15
orq %r14, %r15
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %r12
movq 16(%rsp), %r13
orq $16, %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6workerv, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
cvtsi2sd %r13, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
cvtsi2sd %r12, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 24(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 24(%rsp) # 8-byte Spill
movl %ebx, %ebp
shll $4, %ebp
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $16, %edx
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $.L.str.5, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $.L.str.6, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movl $.L.str.8, %esi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
callq hipDeviceReset
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6workerv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6workerv,@object # @_Z6workerv
.section .rodata,"a",@progbits
.globl _Z6workerv
.p2align 3, 0x0
_Z6workerv:
.quad _Z21__device_stub__workerv
.size _Z6workerv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Name: %s\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Clock rate = %d\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device has %d SMs\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%27s %12d\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Threads per block"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total number of blocks"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total number of threads"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%27s %12.3f (s)\n"
.size .L.str.7, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU Kernel Time (scaled)"
.size .L.str.8, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6workerv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__workerv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6workerv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6workerv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fca0000015000 */
/*0020*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*0030*/ IADD3 R4, P0, -R2, R4, RZ ; /* 0x0000000402047210 */
/* 0x000fe20007f1e1ff */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x307f7676 ; /* 0x307f7676ff077424 */
/* 0x000fe400078e00ff */
/*0050*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4e8044ea ; /* 0x4e8044eaff007424 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.X R5, R5, 0x1, ~R3, P0 ; /* 0x0000000105057824 */
/* 0x000fe400000e0e03 */
/*0070*/ FFMA R0, R7, -R0, 1 ; /* 0x3f80000007007423 */
/* 0x000fe40000000800 */
/*0080*/ I2F.S64 R4, R4 ; /* 0x0000000400047312 */
/* 0x000e240000301400 */
/*0090*/ FFMA R7, R0, R7, 9.2936802698062592754e-10 ; /* 0x307f767600077423 */
/* 0x000fcc0000000007 */
/*00a0*/ FCHK P0, R4, 1.07600000000000000000e+09 ; /* 0x4e8044ea04007902 */
/* 0x001e220000000000 */
/*00b0*/ FFMA R0, R4, R7, RZ ; /* 0x0000000704007223 */
/* 0x000fc800000000ff */
/*00c0*/ FFMA R6, R0, -1.07600000000000000000e+09, R4 ; /* 0xce8044ea00067823 */
/* 0x000fc80000000004 */
/*00d0*/ FFMA R0, R7, R6, R0 ; /* 0x0000000607007223 */
/* 0x000fe20000000000 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*00f0*/ MOV R0, 0x110 ; /* 0x0000011000007802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x150 ; /* 0x0000004000007944 */
/* 0x000fea0003c00000 */
/*0110*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x001fca00078e0006 */
/*0120*/ FSETP.GEU.AND P0, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fda0003f0e000 */
/*0130*/ @!P0 BRA 0x20 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fc600078e0004 */
/*0170*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*0180*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, !PT ; /* 0x000000fd0800780c */
/* 0x000fda0007f04470 */
/*01a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*01b0*/ @!P0 BRA 0x2b0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*01c0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*01d0*/ @P0 BRA 0x680 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4e8044ea ; /* 0x4e8044eaff077424 */
/* 0x000fca00078e00ff */
/*01f0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0200*/ @!P0 BRA 0x660 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0210*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x640 ; /* 0x0000041000008947 */
/* 0x000fea0003800000 */
/*0230*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1d200 */
/*0240*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0250*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0260*/ @P0 BRA 0x610 ; /* 0x000003a000000947 */
/* 0x000fea0003800000 */
/*0270*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f06270 */
/*0280*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0290*/ @!P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004068823 */
/* 0x000fe400000000ff */
/*02a0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*02b0*/ UMOV UR4, 0x4e8044ea ; /* 0x4e8044ea00047882 */
/* 0x000fe20000000000 */
/*02c0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fe20007ffe0ff */
/*02d0*/ UIADD3 UR4, UR4, -0xf000000, URZ ; /* 0xf100000004047890 */
/* 0x000fc6000fffe03f */
/*02e0*/ IADD3 R7, R7, -0x1e, R5 ; /* 0xffffffe207077810 */
/* 0x000fe20007ffe005 */
/*02f0*/ IMAD R6, R5, -0x800000, R6 ; /* 0xff80000005067824 */
/* 0x000fe400078e0206 */
/*0300*/ FADD.FTZ R9, -RZ, -UR4 ; /* 0x80000004ff097e21 */
/* 0x000fc60008010100 */
/*0310*/ MUFU.RCP R4, UR4 ; /* 0x0000000400047d08 */
/* 0x000e240008001000 */
/*0320*/ FFMA R11, R4, R9, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000009 */
/*0330*/ FFMA R11, R4, R11, R4 ; /* 0x0000000b040b7223 */
/* 0x000fc80000000004 */
/*0340*/ FFMA R4, R6, R11, RZ ; /* 0x0000000b06047223 */
/* 0x000fc800000000ff */
/*0350*/ FFMA R8, R9, R4, R6 ; /* 0x0000000409087223 */
/* 0x000fc80000000006 */
/*0360*/ FFMA R8, R11, R8, R4 ; /* 0x000000080b087223 */
/* 0x000fc80000000004 */
/*0370*/ FFMA R9, R9, R8, R6 ; /* 0x0000000809097223 */
/* 0x000fc80000000006 */
/*0380*/ FFMA R6, R11, R9, R8 ; /* 0x000000090b067223 */
/* 0x000fca0000000008 */
/*0390*/ SHF.R.U32.HI R4, RZ, 0x17, R6 ; /* 0x00000017ff047819 */
/* 0x000fc80000011606 */
/*03a0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*03b0*/ IMAD.IADD R10, R4, 0x1, R7 ; /* 0x00000001040a7824 */
/* 0x000fca00078e0207 */
/*03c0*/ IADD3 R4, R10, -0x1, RZ ; /* 0xffffffff0a047810 */
/* 0x000fc80007ffe0ff */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*03e0*/ @!P0 BRA 0x5f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GT.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f04270 */
/*0400*/ @P0 BRA 0x5c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f06270 */
/*0420*/ @P0 BRA 0x690 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.AND P0, PT, R10, -0x18, PT ; /* 0xffffffe80a00780c */
/* 0x000fe40003f06270 */
/*0440*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0450*/ @!P0 BRA 0x690 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0460*/ FFMA.RZ R4, R11.reuse, R9.reuse, R8 ; /* 0x000000090b047223 */
/* 0x0c0fe2000000c008 */
/*0470*/ ISETP.NE.AND P2, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x040fe20003f45270 */
/*0480*/ IMAD.MOV R7, RZ, RZ, -R10 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0a */
/*0490*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25270 */
/*04a0*/ LOP3.LUT R5, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04057812 */
/* 0x000fe200078ec0ff */
/*04b0*/ FFMA.RP R4, R11.reuse, R9.reuse, R8.reuse ; /* 0x000000090b047223 */
/* 0x1c0fe40000008008 */
/*04c0*/ FFMA.RM R11, R11, R9, R8 ; /* 0x000000090b0b7223 */
/* 0x000fe20000004008 */
/*04d0*/ IADD3 R8, R10, 0x20, RZ ; /* 0x000000200a087810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fc400078efcff */
/*04f0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720b */
/* 0x000fe40003f1d000 */
/*0500*/ SHF.L.U32 R8, R5, R8, RZ ; /* 0x0000000805087219 */
/* 0x000fe400000006ff */
/*0510*/ SEL R4, R7, RZ, P2 ; /* 0x000000ff07047207 */
/* 0x000fe40001000000 */
/*0520*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0530*/ SHF.R.U32.HI R4, RZ, R4, R5 ; /* 0x00000004ff047219 */
/* 0x000fe40000011605 */
/*0540*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0550*/ SHF.R.U32.HI R8, RZ, 0x1, R4 ; /* 0x00000001ff087819 */
/* 0x000fe40000011604 */
/*0560*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0570*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0580*/ LOP3.LUT R5, R5, R4, RZ, 0xc0, !PT ; /* 0x0000000405057212 */
/* 0x000fca00078ec0ff */
/*0590*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*05a0*/ LOP3.LUT R6, R5, R6, RZ, 0xfc, !PT ; /* 0x0000000605067212 */
/* 0x000fe200078efcff */
/*05b0*/ BRA 0x690 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*05c0*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*05d0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*05e0*/ BRA 0x690 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD R6, R7, 0x800000, R6 ; /* 0x0080000007067824 */
/* 0x000fe200078e0206 */
/*0600*/ BRA 0x690 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0610*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fc800078e4806 */
/*0620*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0630*/ BRA 0x690 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0640*/ LOP3.LUT R6, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007067812 */
/* 0x000fe200078e4806 */
/*0650*/ BRA 0x690 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0660*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0670*/ BRA 0x690 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0680*/ FADD.FTZ R6, R4, 1.07600000000000000000e+09 ; /* 0x4e8044ea04067421 */
/* 0x000fe40000010000 */
/*0690*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*06b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff94004007950 */
/* 0x000fea0003c3ffff */
/*06c0*/ BRA 0x6c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6workerv
.globl _Z6workerv
.p2align 8
.type _Z6workerv,@function
_Z6workerv:
s_getreg_b32 s0, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[2:3], s[0:1]
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccz .LBB0_4
.LBB0_2:
s_sub_u32 s2, s2, s0
s_subb_u32 s3, s3, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s2, s3
s_cls_i32 s5, s3
s_ashr_i32 s4, s4, 31
s_add_i32 s5, s5, -1
s_add_i32 s4, s4, 32
s_min_u32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], s4
s_min_u32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s3, s2
s_mov_b32 s3, -1
v_cvt_f32_i32_e32 v0, s2
s_sub_i32 s2, 32, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_ldexp_f32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v1, null, 0x4e8044ea, 0x4e8044ea, v0
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v2
v_div_scale_f32 v3, vcc_lo, v0, 0x4e8044ea, v0
v_mul_f32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v1, v4, v3
v_fmac_f32_e32 v4, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v4, v3
v_div_fmas_f32 v1, v1, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v1, 0x4e8044ea, v0
v_cmp_ngt_f32_e32 vcc_lo, 1.0, v0
s_cbranch_vccnz .LBB0_1
s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_mov_b32 s3, 0
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6workerv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6workerv, .Lfunc_end0-_Z6workerv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6workerv
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6workerv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000244bf_00000000-6_sm_question.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z5sleepf
.type _Z5sleepf, @function
_Z5sleepf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5sleepf, .-_Z5sleepf
.globl _Z24__device_stub__Z6workervv
.type _Z24__device_stub__Z6workervv, @function
_Z24__device_stub__Z6workervv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6workerv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6workervv, .-_Z24__device_stub__Z6workervv
.globl _Z6workerv
.type _Z6workerv, @function
_Z6workerv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6workervv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6workerv, .-_Z6workerv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Name: %s\n"
.LC2:
.string "Clock rate = %d\n"
.LC3:
.string "Device has %d SMs\n"
.LC4:
.string "Threads per block"
.LC5:
.string "%27s %12d\n"
.LC6:
.string "Total number of blocks"
.LC7:
.string "Total number of threads"
.LC8:
.string "GPU Kernel Time (scaled)"
.LC9:
.string "%27s %12.3f (s)\n"
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1096, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 436(%rsp), %ebx
movslq 396(%rsp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 32(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl %ebx, 36(%rsp)
movl $16, 24(%rsp)
movl $1, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L18:
call cudaDeviceSynchronize@PLT
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rbp
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
leaq .LC6(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
sall $4, %ecx
leaq .LC7(%rip), %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceReset@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call _Z24__device_stub__Z6workervv
jmp .L18
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z6workerv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6workerv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sm_question.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z21__device_stub__workerv # -- Begin function _Z21__device_stub__workerv
.p2align 4, 0x90
.type _Z21__device_stub__workerv,@function
_Z21__device_stub__workerv: # @_Z21__device_stub__workerv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6workerv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z21__device_stub__workerv, .Lfunc_end1-_Z21__device_stub__workerv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 72(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 460(%rsp), %ebx
movslq 420(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movabsq $4294967296, %r14 # imm = 0x100000000
movq %rbx, %r15
orq %r14, %r15
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %r12
movq 16(%rsp), %r13
orq $16, %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6workerv, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
cvtsi2sd %r13, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
cvtsi2sd %r12, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
mulsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 24(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 24(%rsp) # 8-byte Spill
movl %ebx, %ebp
shll $4, %ebp
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $16, %edx
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $.L.str.5, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $.L.str.6, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
movl $.L.str.8, %esi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
callq hipDeviceReset
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6workerv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6workerv,@object # @_Z6workerv
.section .rodata,"a",@progbits
.globl _Z6workerv
.p2align 3, 0x0
_Z6workerv:
.quad _Z21__device_stub__workerv
.size _Z6workerv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Name: %s\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Clock rate = %d\n"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device has %d SMs\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%27s %12d\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Threads per block"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total number of blocks"
.size .L.str.5, 23
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total number of threads"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%27s %12.3f (s)\n"
.size .L.str.7, 17
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU Kernel Time (scaled)"
.size .L.str.8, 25
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6workerv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__workerv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6workerv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* Open source copyright declaration based on BSD open source template:
* http://www.opensource.org/licenses/bsd-license.php
*
* This file is part of the OPS distribution.
*
* Copyright (c) 2013, Mike Giles and others. Please see the AUTHORS file in
* the main source directory for a full list of copyright holders.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * The name of Mike Giles may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mike Giles ''AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mike Giles BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file
* @brief OPS mpi+cuda run-time support routines
* @author Gihan Mudalige, Istvan Reguly
* @details Implements the runtime support routines for the OPS mpi+cuda
* backend
*/
int halo_buffer_size = 0;
char *halo_buffer_d = NULL;
__global__ void copy_kernel_frombuf(char *dest, char *src, int rx_s, int rx_e, int ry_s, int ry_e, int rz_s, int rz_e, int x_step, int y_step, int z_step, int size_x, int size_y, int size_z, int buf_strides_x, int buf_strides_y, int buf_strides_z, int type_size, int dim, int OPS_soa) {
int idx_z = rz_s + z_step * (blockDim.z * blockIdx.z + threadIdx.z);
int idx_y = ry_s + y_step * (blockDim.y * blockIdx.y + threadIdx.y);
int idx_x = rx_s + x_step * (blockDim.x * blockIdx.x + threadIdx.x);
if ((x_step == 1 ? idx_x < rx_e : idx_x > rx_e) &&
(y_step == 1 ? idx_y < ry_e : idx_y > ry_e) &&
(z_step == 1 ? idx_z < rz_e : idx_z > rz_e)) {
if (OPS_soa) dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size;
else dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size * dim;
src += ((idx_z - rz_s) * z_step * buf_strides_z +
(idx_y - ry_s) * y_step * buf_strides_y +
(idx_x - rx_s) * x_step * buf_strides_x) *
type_size * dim;
for (int d = 0; d < dim; d++) {
memcpy(dest, src + d * type_size, type_size);
if (OPS_soa) dest += size_x * size_y * size_z * type_size;
else dest += type_size;
}
}
} | .file "tmpxft_001820d2_00000000-6_copy_kernel_frombuf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
.type _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii, @function
_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 288(%rsp), %rax
movq %rax, 144(%rsp)
leaq 296(%rsp), %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 392(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 296
pushq 40(%rsp)
.cfi_def_cfa_offset 304
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii, .-_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
.globl _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.type _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, @function
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
call _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .-_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl halo_buffer_d
.bss
.align 8
.type halo_buffer_d, @object
.size halo_buffer_d, 8
halo_buffer_d:
.zero 8
.globl halo_buffer_size
.align 4
.type halo_buffer_size, @object
.size halo_buffer_size, 4
halo_buffer_size:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* Open source copyright declaration based on BSD open source template:
* http://www.opensource.org/licenses/bsd-license.php
*
* This file is part of the OPS distribution.
*
* Copyright (c) 2013, Mike Giles and others. Please see the AUTHORS file in
* the main source directory for a full list of copyright holders.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * The name of Mike Giles may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mike Giles ''AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mike Giles BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file
* @brief OPS mpi+cuda run-time support routines
* @author Gihan Mudalige, Istvan Reguly
* @details Implements the runtime support routines for the OPS mpi+cuda
* backend
*/
int halo_buffer_size = 0;
char *halo_buffer_d = NULL;
__global__ void copy_kernel_frombuf(char *dest, char *src, int rx_s, int rx_e, int ry_s, int ry_e, int rz_s, int rz_e, int x_step, int y_step, int z_step, int size_x, int size_y, int size_z, int buf_strides_x, int buf_strides_y, int buf_strides_z, int type_size, int dim, int OPS_soa) {
int idx_z = rz_s + z_step * (blockDim.z * blockIdx.z + threadIdx.z);
int idx_y = ry_s + y_step * (blockDim.y * blockIdx.y + threadIdx.y);
int idx_x = rx_s + x_step * (blockDim.x * blockIdx.x + threadIdx.x);
if ((x_step == 1 ? idx_x < rx_e : idx_x > rx_e) &&
(y_step == 1 ? idx_y < ry_e : idx_y > ry_e) &&
(z_step == 1 ? idx_z < rz_e : idx_z > rz_e)) {
if (OPS_soa) dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size;
else dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size * dim;
src += ((idx_z - rz_s) * z_step * buf_strides_z +
(idx_y - ry_s) * y_step * buf_strides_y +
(idx_x - rx_s) * x_step * buf_strides_x) *
type_size * dim;
for (int d = 0; d < dim; d++) {
memcpy(dest, src + d * type_size, type_size);
if (OPS_soa) dest += size_x * size_y * size_z * type_size;
else dest += type_size;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Open source copyright declaration based on BSD open source template:
* http://www.opensource.org/licenses/bsd-license.php
*
* This file is part of the OPS distribution.
*
* Copyright (c) 2013, Mike Giles and others. Please see the AUTHORS file in
* the main source directory for a full list of copyright holders.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * The name of Mike Giles may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mike Giles ''AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mike Giles BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file
* @brief OPS mpi+cuda run-time support routines
* @author Gihan Mudalige, Istvan Reguly
* @details Implements the runtime support routines for the OPS mpi+cuda
* backend
*/
int halo_buffer_size = 0;
char *halo_buffer_d = NULL;
__global__ void copy_kernel_frombuf(char *dest, char *src, int rx_s, int rx_e, int ry_s, int ry_e, int rz_s, int rz_e, int x_step, int y_step, int z_step, int size_x, int size_y, int size_z, int buf_strides_x, int buf_strides_y, int buf_strides_z, int type_size, int dim, int OPS_soa) {
int idx_z = rz_s + z_step * (blockDim.z * blockIdx.z + threadIdx.z);
int idx_y = ry_s + y_step * (blockDim.y * blockIdx.y + threadIdx.y);
int idx_x = rx_s + x_step * (blockDim.x * blockIdx.x + threadIdx.x);
if ((x_step == 1 ? idx_x < rx_e : idx_x > rx_e) &&
(y_step == 1 ? idx_y < ry_e : idx_y > ry_e) &&
(z_step == 1 ? idx_z < rz_e : idx_z > rz_e)) {
if (OPS_soa) dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size;
else dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size * dim;
src += ((idx_z - rz_s) * z_step * buf_strides_z +
(idx_y - ry_s) * y_step * buf_strides_y +
(idx_x - rx_s) * x_step * buf_strides_x) *
type_size * dim;
for (int d = 0; d < dim; d++) {
memcpy(dest, src + d * type_size, type_size);
if (OPS_soa) dest += size_x * size_y * size_z * type_size;
else dest += type_size;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Open source copyright declaration based on BSD open source template:
* http://www.opensource.org/licenses/bsd-license.php
*
* This file is part of the OPS distribution.
*
* Copyright (c) 2013, Mike Giles and others. Please see the AUTHORS file in
* the main source directory for a full list of copyright holders.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * The name of Mike Giles may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mike Giles ''AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mike Giles BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file
* @brief OPS mpi+cuda run-time support routines
* @author Gihan Mudalige, Istvan Reguly
* @details Implements the runtime support routines for the OPS mpi+cuda
* backend
*/
int halo_buffer_size = 0;
char *halo_buffer_d = NULL;
__global__ void copy_kernel_frombuf(char *dest, char *src, int rx_s, int rx_e, int ry_s, int ry_e, int rz_s, int rz_e, int x_step, int y_step, int z_step, int size_x, int size_y, int size_z, int buf_strides_x, int buf_strides_y, int buf_strides_z, int type_size, int dim, int OPS_soa) {
int idx_z = rz_s + z_step * (blockDim.z * blockIdx.z + threadIdx.z);
int idx_y = ry_s + y_step * (blockDim.y * blockIdx.y + threadIdx.y);
int idx_x = rx_s + x_step * (blockDim.x * blockIdx.x + threadIdx.x);
if ((x_step == 1 ? idx_x < rx_e : idx_x > rx_e) &&
(y_step == 1 ? idx_y < ry_e : idx_y > ry_e) &&
(z_step == 1 ? idx_z < rz_e : idx_z > rz_e)) {
if (OPS_soa) dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size;
else dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size * dim;
src += ((idx_z - rz_s) * z_step * buf_strides_z +
(idx_y - ry_s) * y_step * buf_strides_y +
(idx_x - rx_s) * x_step * buf_strides_x) *
type_size * dim;
for (int d = 0; d < dim; d++) {
memcpy(dest, src + d * type_size, type_size);
if (OPS_soa) dest += size_x * size_y * size_z * type_size;
else dest += type_size;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.globl _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.p2align 8
.type _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@function
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x64
s_load_b32 s6, s[0:1], 0x28
v_and_b32_e32 v1, 0x3ff, v0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_cmp_lg_u32 s6, 1
v_mad_u64_u32 v[2:3], null, s13, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s6
v_add_nc_u32_e32 v1, s2, v4
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s3, v1
s_and_b32 s2, vcc_lo, exec_lo
s_cbranch_execz .LBB0_3
s_branch .LBB0_4
.LBB0_2:
s_mov_b32 s2, 0
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_or_b32 s2, s2, s3
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_39
s_clause 0x1
s_load_b32 s7, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s4, 0xffff, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[5:6], null, s14, s4, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s7
s_cmp_lg_u32 s7, 1
v_add_nc_u32_e32 v2, s2, v5
s_cbranch_scc0 .LBB0_7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s3, v2
s_and_b32 s2, vcc_lo, exec_lo
s_cbranch_execz .LBB0_8
s_branch .LBB0_9
.LBB0_7:
s_mov_b32 s2, 0
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_or_b32 s2, s2, s3
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_39
s_clause 0x1
s_load_b32 s4, s[0:1], 0x68
s_load_b32 s8, s[0:1], 0x30
v_bfe_u32 v0, v0, 20, 10
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, 0xffff, s4
s_cmp_lg_u32 s8, 1
v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v6, s8
v_add_nc_u32_e32 v3, s2, v0
s_cbranch_scc0 .LBB0_12
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s3, v3
s_and_b32 s2, vcc_lo, exec_lo
s_cbranch_execz .LBB0_13
s_branch .LBB0_14
.LBB0_12:
s_mov_b32 s2, 0
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v3
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s3, vcc_lo, exec_lo
s_or_b32 s2, s2, s3
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_39
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x34
s_load_b32 s9, s[0:1], 0x54
s_load_b64 s[2:3], s[0:1], 0x4c
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v3, s5, v[2:3]
s_cmp_eq_u32 s9, 0
s_cselect_b32 s9, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s9
v_mad_u64_u32 v[2:3], null, v6, s4, v[1:2]
s_cbranch_vccnz .LBB0_17
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v1, v2, s2
s_branch .LBB0_18
.LBB0_17:
s_mov_b32 s10, -1
.LBB0_18:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s10
s_mul_i32 s10, s3, s2
s_cbranch_vccnz .LBB0_20
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v1, s10, v2
.LBB0_20:
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_39
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x3c
s_load_b128 s[16:19], s[0:1], 0x0
s_mul_i32 s4, s5, s4
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s15, s8
s_mul_i32 s1, s14, s7
s_mul_i32 s6, s13, s6
v_mul_lo_u32 v0, s0, v0
v_mul_lo_u32 v2, s1, v5
v_mul_lo_u32 v3, s6, v4
v_ashrrev_i32_e32 v4, 31, v1
s_mul_i32 s4, s4, s12
s_ashr_i32 s1, s2, 31
s_cmp_gt_u32 s2, 3
s_mul_i32 s4, s4, s2
s_cselect_b32 s8, -1, 0
s_ashr_i32 s5, s4, 31
v_add3_u32 v0, v2, v0, v3
s_and_b32 s6, s9, exec_lo
s_mov_b32 s0, s2
s_cselect_b32 s9, s1, s5
s_mov_b32 s12, 0
v_mul_lo_u32 v2, s10, v0
v_add_co_u32 v0, vcc_lo, s16, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s17, v4, vcc_lo
s_cselect_b32 s10, s2, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v6, vcc_lo, s18, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v3, vcc_lo
s_branch .LBB0_23
.LBB0_22:
v_add_co_u32 v0, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_add_i32 s12, s12, 1
s_add_i32 s11, s11, s2
s_cmp_lg_u32 s12, s3
s_cbranch_scc0 .LBB0_39
.LBB0_23:
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_27
s_ashr_i32 s4, s11, 31
v_add_co_u32 v2, vcc_lo, v6, s11
v_add_co_ci_u32_e32 v3, vcc_lo, s4, v7, vcc_lo
s_mov_b64 s[6:7], 0
s_mov_b64 s[4:5], s[0:1]
.p2align 6
.LBB0_25:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v1, vcc_lo
global_load_u8 v10, v[4:5], off
s_add_u32 s4, s4, -4
s_addc_u32 s5, s5, -1
s_add_u32 s6, s6, 4
v_cmp_gt_u64_e64 s13, s[4:5], 3
s_addc_u32 s7, s7, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s13
s_waitcnt vmcnt(0)
global_store_b8 v[8:9], v10, off
global_load_u8 v10, v[4:5], off offset:1
s_waitcnt vmcnt(0)
global_store_b8 v[8:9], v10, off offset:1
global_load_u8 v10, v[4:5], off offset:2
s_waitcnt vmcnt(0)
global_store_b8 v[8:9], v10, off offset:2
global_load_u8 v4, v[4:5], off offset:3
s_waitcnt vmcnt(0)
global_store_b8 v[8:9], v4, off offset:3
s_cbranch_vccnz .LBB0_25
v_add_co_u32 v2, vcc_lo, v2, s6
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v0, s6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_branch .LBB0_28
.LBB0_27:
s_mul_i32 s4, s12, s2
v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
s_ashr_i32 s5, s4, 31
v_add_co_u32 v2, vcc_lo, v6, s4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo
s_mov_b64 s[4:5], s[0:1]
.LBB0_28:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i64_e64 s6, s[4:5], 2
s_and_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_34
v_cmp_gt_i64_e64 s6, s[4:5], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s6
s_mov_b32 s6, -1
s_cbranch_vccz .LBB0_32
s_cmp_eq_u64 s[4:5], 3
s_mov_b32 s6, 0
s_cbranch_scc0 .LBB0_32
global_load_u8 v8, v[2:3], off offset:2
s_mov_b32 s6, -1
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v8, off offset:2
.LBB0_32:
s_mov_b32 s7, 0
s_and_b32 vcc_lo, exec_lo, s6
s_mov_b32 s6, 0
s_cbranch_vccz .LBB0_35
global_load_u8 v8, v[2:3], off offset:1
s_mov_b32 s6, -1
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v8, off offset:1
s_branch .LBB0_35
.LBB0_34:
s_mov_b32 s7, -1
s_mov_b32 s6, 0
.LBB0_35:
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccz .LBB0_37
s_cmp_eq_u64 s[4:5], 1
s_cselect_b32 s6, -1, 0
.LBB0_37:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s6
s_cbranch_vccnz .LBB0_22
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v2, off
s_branch .LBB0_22
.LBB0_39:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .Lfunc_end0-_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* Open source copyright declaration based on BSD open source template:
* http://www.opensource.org/licenses/bsd-license.php
*
* This file is part of the OPS distribution.
*
* Copyright (c) 2013, Mike Giles and others. Please see the AUTHORS file in
* the main source directory for a full list of copyright holders.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * The name of Mike Giles may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Mike Giles ''AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Mike Giles BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @file
* @brief OPS mpi+cuda run-time support routines
* @author Gihan Mudalige, Istvan Reguly
* @details Implements the runtime support routines for the OPS mpi+cuda
* backend
*/
int halo_buffer_size = 0;
char *halo_buffer_d = NULL;
__global__ void copy_kernel_frombuf(char *dest, char *src, int rx_s, int rx_e, int ry_s, int ry_e, int rz_s, int rz_e, int x_step, int y_step, int z_step, int size_x, int size_y, int size_z, int buf_strides_x, int buf_strides_y, int buf_strides_z, int type_size, int dim, int OPS_soa) {
int idx_z = rz_s + z_step * (blockDim.z * blockIdx.z + threadIdx.z);
int idx_y = ry_s + y_step * (blockDim.y * blockIdx.y + threadIdx.y);
int idx_x = rx_s + x_step * (blockDim.x * blockIdx.x + threadIdx.x);
if ((x_step == 1 ? idx_x < rx_e : idx_x > rx_e) &&
(y_step == 1 ? idx_y < ry_e : idx_y > ry_e) &&
(z_step == 1 ? idx_z < rz_e : idx_z > rz_e)) {
if (OPS_soa) dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size;
else dest += (idx_z * size_x * size_y + idx_y * size_x + idx_x) * type_size * dim;
src += ((idx_z - rz_s) * z_step * buf_strides_z +
(idx_y - ry_s) * y_step * buf_strides_y +
(idx_x - rx_s) * x_step * buf_strides_x) *
type_size * dim;
for (int d = 0; d < dim; d++) {
memcpy(dest, src + d * type_size, type_size);
if (OPS_soa) dest += size_x * size_y * size_z * type_size;
else dest += type_size;
}
}
} | .text
.file "copy_kernel_frombuf.hip"
.globl _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii # -- Begin function _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.p2align 4, 0x90
.type _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@function
_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii: # @_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 256(%rsp), %rax
movq %rax, 128(%rsp)
leaq 264(%rsp), %rax
movq %rax, 136(%rsp)
leaq 272(%rsp), %rax
movq %rax, 144(%rsp)
leaq 280(%rsp), %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .Lfunc_end0-_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type halo_buffer_size,@object # @halo_buffer_size
.bss
.globl halo_buffer_size
.p2align 2, 0x0
halo_buffer_size:
.long 0 # 0x0
.size halo_buffer_size, 4
.type halo_buffer_d,@object # @halo_buffer_d
.globl halo_buffer_d
.p2align 3, 0x0
halo_buffer_d:
.quad 0
.size halo_buffer_d, 8
.type _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@object # @_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.p2align 3, 0x0
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii:
.quad _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.size _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001820d2_00000000-6_copy_kernel_frombuf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
.type _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii, @function
_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 288(%rsp), %rax
movq %rax, 144(%rsp)
leaq 296(%rsp), %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 392(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 296
pushq 40(%rsp)
.cfi_def_cfa_offset 304
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii, .-_Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
.globl _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.type _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, @function
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 96
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 128
call _Z59__device_stub__Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiiiPcS_iiiiiiiiiiiiiiiiii
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .-_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl halo_buffer_d
.bss
.align 8
.type halo_buffer_d, @object
.size halo_buffer_d, 8
halo_buffer_d:
.zero 8
.globl halo_buffer_size
.align 4
.type halo_buffer_size, @object
.size halo_buffer_size, 4
halo_buffer_size:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy_kernel_frombuf.hip"
.globl _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii # -- Begin function _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.p2align 4, 0x90
.type _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@function
_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii: # @_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 256(%rsp), %rax
movq %rax, 128(%rsp)
leaq 264(%rsp), %rax
movq %rax, 136(%rsp)
leaq 272(%rsp), %rax
movq %rax, 144(%rsp)
leaq 280(%rsp), %rax
movq %rax, 152(%rsp)
leaq 288(%rsp), %rax
movq %rax, 160(%rsp)
leaq 296(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, .Lfunc_end0-_Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type halo_buffer_size,@object # @halo_buffer_size
.bss
.globl halo_buffer_size
.p2align 2, 0x0
halo_buffer_size:
.long 0 # 0x0
.size halo_buffer_size, 4
.type halo_buffer_d,@object # @halo_buffer_d
.globl halo_buffer_d
.p2align 3, 0x0
halo_buffer_d:
.quad 0
.size halo_buffer_d, 8
.type _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii,@object # @_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.section .rodata,"a",@progbits
.globl _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.p2align 3, 0x0
_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii:
.quad _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.size _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19copy_kernel_frombufPcS_iiiiiiiiiiiiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void mat_mult_transposed_kernel(int *mat_a, int *mat_b, int *res) {
int B_TRANS_ROWS = B_COLS;
int B_TRANS_COLS = B_ROWS;
// El for each thread, shared per block
__shared__ int smem[128];
for (int row_block = 0; row_block * gridDim.x < A_ROWS; row_block++) {
int a_row = blockIdx.x + (row_block * gridDim.x);
for (int b_row = 0; b_row < B_TRANS_ROWS; b_row++) {
int total = 0;
for (int thread_i = 0; thread_i * blockDim.x < A_COLS; thread_i++) {
int thread_col = threadIdx.x + (thread_i * blockDim.x);
// Need to check because 240 not even multiple of 128
if (thread_col >= A_COLS)
smem[threadIdx.x] = 0;
else
smem[threadIdx.x] = mat_a[a_row * A_COLS + thread_col] * mat_b[b_row * B_TRANS_COLS + thread_col];
__syncthreads();
//Parallel reduction
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
if (threadIdx.x == 0) {
total += smem[threadIdx.x];
}
}
if (threadIdx.x == 0) {
res[a_row * C_COLS + b_row] = total;
}
}
}
} | code for sm_80
Function : _Z26mat_mult_transposed_kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*0030*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x003fe400078e00ff */
/*0090*/ IADD3 R4, R4, UR5, RZ ; /* 0x0000000504047c10 */
/* 0x000fe2000fffe0ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fcc00078e00ff */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fce00078e00ff */
/*00e0*/ IADD3 R6, R0, R7, RZ ; /* 0x0000000700067210 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.AND P0, PT, R6, 0xef, PT ; /* 0x000000ef0600780c */
/* 0x000fda0003f04270 */
/*0100*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff078424 */
/* 0x000fe400078e00ff */
/*0110*/ @!P0 IMAD R8, R3, 0xf0, R6.reuse ; /* 0x000000f003088824 */
/* 0x100fe400078e0206 */
/*0120*/ @!P0 IMAD R6, R4, 0xf0, R6 ; /* 0x000000f004068824 */
/* 0x000fe400078e0206 */
/*0130*/ @!P0 IMAD.WIDE R8, R8, R7, c[0x0][0x168] ; /* 0x00005a0008088625 */
/* 0x000fc800078e0207 */
/*0140*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006068625 */
/* 0x000fe400078e0207 */
/*0150*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000608088981 */
/* 0x000ea8000c1e1900 */
/*0160*/ @!P0 LDG.E R7, [R6.64] ; /* 0x0000000606078981 */
/* 0x000ea2000c1e1900 */
/*0170*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0190*/ @!P0 IMAD R11, R8, R7, RZ ; /* 0x00000007080b8224 */
/* 0x004fca00078e02ff */
/*01a0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @!P1 BRA 0x280 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*01d0*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x001fc80008000f00 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06070 */
/*01f0*/ @!P0 IMAD R8, R7, 0x4, R2 ; /* 0x0000000407088824 */
/* 0x000fe200078e0202 */
/*0200*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe20000004800 */
/*0210*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fc60000011607 */
/*0220*/ @!P0 LDS R9, [R8] ; /* 0x0000000008098984 */
/* 0x000e240000000800 */
/*0230*/ @!P0 IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106098824 */
/* 0x001fca00078e0209 */
/*0240*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x0001e80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0270*/ @P0 BRA 0x1e0 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0280*/ LDS R6, [RZ] ; /* 0x00000000ff067984 */
/* 0x001e220000000800 */
/*0290*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*02b0*/ IMAD R7, R12, c[0x0][0x0], RZ ; /* 0x000000000c077a24 */
/* 0x000fca00078e02ff */
/*02c0*/ ISETP.GE.U32.AND P1, PT, R7, 0xf0, PT ; /* 0x000000f00700780c */
/* 0x000fe40003f26070 */
/*02d0*/ SEL R6, R6, RZ, !P0 ; /* 0x000000ff06067207 */
/* 0x001fc80004000000 */
/*02e0*/ IADD3 R5, R6, R5, RZ ; /* 0x0000000506057210 */
/* 0x000fce0007ffe0ff */
/*02f0*/ @!P1 BRA 0xe0 ; /* 0xfffffde000009947 */
/* 0x000fea000383ffff */
/*0300*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0310*/ @!P0 MOV R7, 0x4 ; /* 0x0000000400078802 */
/* 0x000fe20000000f00 */
/*0320*/ @!P0 IMAD R6, R4, 0x200, R3 ; /* 0x0000020004068824 */
/* 0x000fe200078e0203 */
/*0330*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc60007ffe0ff */
/*0340*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006068625 */
/* 0x000fca00078e0207 */
/*0350*/ @!P0 STG.E [R6.64], R5 ; /* 0x0000000506008986 */
/* 0x0001e2000c101906 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fda0003f06070 */
/*0370*/ @!P0 BRA 0xb0 ; /* 0xfffffd3000008947 */
/* 0x001fea000383ffff */
/*0380*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fca0007ffe0ff */
/*0390*/ IMAD R4, R10, c[0x0][0xc], RZ ; /* 0x000003000a047a24 */
/* 0x000fca00078e02ff */
/*03a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x100, PT ; /* 0x000001000400780c */
/* 0x000fda0003f06070 */
/*03b0*/ @!P0 BRA 0x90 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void mat_mult_transposed_kernel(int *mat_a, int *mat_b, int *res) {
int B_TRANS_ROWS = B_COLS;
int B_TRANS_COLS = B_ROWS;
// El for each thread, shared per block
__shared__ int smem[128];
for (int row_block = 0; row_block * gridDim.x < A_ROWS; row_block++) {
int a_row = blockIdx.x + (row_block * gridDim.x);
for (int b_row = 0; b_row < B_TRANS_ROWS; b_row++) {
int total = 0;
for (int thread_i = 0; thread_i * blockDim.x < A_COLS; thread_i++) {
int thread_col = threadIdx.x + (thread_i * blockDim.x);
// Need to check because 240 not even multiple of 128
if (thread_col >= A_COLS)
smem[threadIdx.x] = 0;
else
smem[threadIdx.x] = mat_a[a_row * A_COLS + thread_col] * mat_b[b_row * B_TRANS_COLS + thread_col];
__syncthreads();
//Parallel reduction
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
if (threadIdx.x == 0) {
total += smem[threadIdx.x];
}
}
if (threadIdx.x == 0) {
res[a_row * C_COLS + b_row] = total;
}
}
}
} | .file "tmpxft_000c112d_00000000-6_mat_mult_transposed_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_
.type _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_, @function
_Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26mat_mult_transposed_kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_, .-_Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_
.globl _Z26mat_mult_transposed_kernelPiS_S_
.type _Z26mat_mult_transposed_kernelPiS_S_, @function
_Z26mat_mult_transposed_kernelPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26mat_mult_transposed_kernelPiS_S_, .-_Z26mat_mult_transposed_kernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26mat_mult_transposed_kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26mat_mult_transposed_kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void mat_mult_transposed_kernel(int *mat_a, int *mat_b, int *res) {
int B_TRANS_ROWS = B_COLS;
int B_TRANS_COLS = B_ROWS;
// El for each thread, shared per block
__shared__ int smem[128];
for (int row_block = 0; row_block * gridDim.x < A_ROWS; row_block++) {
int a_row = blockIdx.x + (row_block * gridDim.x);
for (int b_row = 0; b_row < B_TRANS_ROWS; b_row++) {
int total = 0;
for (int thread_i = 0; thread_i * blockDim.x < A_COLS; thread_i++) {
int thread_col = threadIdx.x + (thread_i * blockDim.x);
// Need to check because 240 not even multiple of 128
if (thread_col >= A_COLS)
smem[threadIdx.x] = 0;
else
smem[threadIdx.x] = mat_a[a_row * A_COLS + thread_col] * mat_b[b_row * B_TRANS_COLS + thread_col];
__syncthreads();
//Parallel reduction
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
if (threadIdx.x == 0) {
total += smem[threadIdx.x];
}
}
if (threadIdx.x == 0) {
res[a_row * C_COLS + b_row] = total;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mat_mult_transposed_kernel(int *mat_a, int *mat_b, int *res) {
int B_TRANS_ROWS = B_COLS;
int B_TRANS_COLS = B_ROWS;
// El for each thread, shared per block
__shared__ int smem[128];
for (int row_block = 0; row_block * gridDim.x < A_ROWS; row_block++) {
int a_row = blockIdx.x + (row_block * gridDim.x);
for (int b_row = 0; b_row < B_TRANS_ROWS; b_row++) {
int total = 0;
for (int thread_i = 0; thread_i * blockDim.x < A_COLS; thread_i++) {
int thread_col = threadIdx.x + (thread_i * blockDim.x);
// Need to check because 240 not even multiple of 128
if (thread_col >= A_COLS)
smem[threadIdx.x] = 0;
else
smem[threadIdx.x] = mat_a[a_row * A_COLS + thread_col] * mat_b[b_row * B_TRANS_COLS + thread_col];
__syncthreads();
//Parallel reduction
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
if (threadIdx.x == 0) {
total += smem[threadIdx.x];
}
}
if (threadIdx.x == 0) {
res[a_row * C_COLS + b_row] = total;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mat_mult_transposed_kernel(int *mat_a, int *mat_b, int *res) {
int B_TRANS_ROWS = B_COLS;
int B_TRANS_COLS = B_ROWS;
// El for each thread, shared per block
__shared__ int smem[128];
for (int row_block = 0; row_block * gridDim.x < A_ROWS; row_block++) {
int a_row = blockIdx.x + (row_block * gridDim.x);
for (int b_row = 0; b_row < B_TRANS_ROWS; b_row++) {
int total = 0;
for (int thread_i = 0; thread_i * blockDim.x < A_COLS; thread_i++) {
int thread_col = threadIdx.x + (thread_i * blockDim.x);
// Need to check because 240 not even multiple of 128
if (thread_col >= A_COLS)
smem[threadIdx.x] = 0;
else
smem[threadIdx.x] = mat_a[a_row * A_COLS + thread_col] * mat_b[b_row * B_TRANS_COLS + thread_col];
__syncthreads();
//Parallel reduction
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
if (threadIdx.x == 0) {
total += smem[threadIdx.x];
}
}
if (threadIdx.x == 0) {
res[a_row * C_COLS + b_row] = total;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26mat_mult_transposed_kernelPiS_S_
.globl _Z26mat_mult_transposed_kernelPiS_S_
.p2align 8
.type _Z26mat_mult_transposed_kernelPiS_S_,@function
_Z26mat_mult_transposed_kernelPiS_S_:
s_clause 0x3
s_load_b32 s9, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_cmp_eq_u32_e64 s0, 0, v0
s_mov_b32 s11, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s1, 1
s_cselect_b32 s9, -1, 0
s_branch .LBB0_2
.LBB0_1:
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s11, s8, s10
s_cmpk_gt_u32 s11, 0xff
s_cbranch_scc1 .LBB0_18
.LBB0_2:
s_add_i32 s12, s11, s15
s_mov_b32 s13, 0
s_mul_i32 s11, s12, 0xf0
s_lshl_b32 s12, s12, 9
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s13, 0x200
s_cbranch_scc1 .LBB0_1
.LBB0_4:
v_mov_b32_e32 v4, 0
s_mul_i32 s14, s13, 0xf0
s_mov_b32 s17, 0
s_mov_b32 s16, 0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s17, s16, s1
s_cmpk_gt_u32 s17, 0xef
s_cbranch_scc1 .LBB0_16
.LBB0_6:
v_add_nc_u32_e32 v1, s17, v0
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0xf0, v1
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v5, s11, v1
v_add_nc_u32_e32 v1, s14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[5:6], off
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v5, v1
ds_store_b32 v3, v1
.LBB0_8:
s_and_not1_saveexec_b32 s17, s17
s_cbranch_execz .LBB0_10
ds_store_b32 v3, v2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s9
s_mov_b32 s17, s1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_14
.LBB0_11:
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_5
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v1, v4
s_branch .LBB0_5
.p2align 6
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s19
s_cmp_lt_u32 s17, 4
s_mov_b32 s17, s18
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
.LBB0_14:
s_lshr_b32 s18, s17, 1
s_mov_b32 s19, exec_lo
v_cmpx_gt_u32_e64 s18, v0
s_cbranch_execz .LBB0_13
v_add_lshl_u32 v1, s18, v0, 2
ds_load_b32 v5, v3
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v5
ds_store_b32 v3, v1
s_branch .LBB0_13
.LBB0_16:
s_and_saveexec_b32 s14, s0
s_cbranch_execz .LBB0_3
s_add_i32 s16, s13, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s17, s16, 31
s_lshl_b64 s[16:17], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s2, s16
s_addc_u32 s17, s3, s17
global_store_b32 v2, v4, s[16:17]
s_branch .LBB0_3
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26mat_mult_transposed_kernelPiS_S_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26mat_mult_transposed_kernelPiS_S_, .Lfunc_end0-_Z26mat_mult_transposed_kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26mat_mult_transposed_kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z26mat_mult_transposed_kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mat_mult_transposed_kernel(int *mat_a, int *mat_b, int *res) {
int B_TRANS_ROWS = B_COLS;
int B_TRANS_COLS = B_ROWS;
// El for each thread, shared per block
__shared__ int smem[128];
for (int row_block = 0; row_block * gridDim.x < A_ROWS; row_block++) {
int a_row = blockIdx.x + (row_block * gridDim.x);
for (int b_row = 0; b_row < B_TRANS_ROWS; b_row++) {
int total = 0;
for (int thread_i = 0; thread_i * blockDim.x < A_COLS; thread_i++) {
int thread_col = threadIdx.x + (thread_i * blockDim.x);
// Need to check because 240 not even multiple of 128
if (thread_col >= A_COLS)
smem[threadIdx.x] = 0;
else
smem[threadIdx.x] = mat_a[a_row * A_COLS + thread_col] * mat_b[b_row * B_TRANS_COLS + thread_col];
__syncthreads();
//Parallel reduction
for (int i = blockDim.x / 2; i > 0; i /= 2) {
if (threadIdx.x < i) {
int temp = smem[threadIdx.x] + smem[threadIdx.x + i];
smem[threadIdx.x] = temp;
}
__syncthreads();
}
if (threadIdx.x == 0) {
total += smem[threadIdx.x];
}
}
if (threadIdx.x == 0) {
res[a_row * C_COLS + b_row] = total;
}
}
}
} | .text
.file "mat_mult_transposed_kernel.hip"
.globl _Z41__device_stub__mat_mult_transposed_kernelPiS_S_ # -- Begin function _Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.p2align 4, 0x90
.type _Z41__device_stub__mat_mult_transposed_kernelPiS_S_,@function
_Z41__device_stub__mat_mult_transposed_kernelPiS_S_: # @_Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26mat_mult_transposed_kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z41__device_stub__mat_mult_transposed_kernelPiS_S_, .Lfunc_end0-_Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26mat_mult_transposed_kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26mat_mult_transposed_kernelPiS_S_,@object # @_Z26mat_mult_transposed_kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z26mat_mult_transposed_kernelPiS_S_
.p2align 3, 0x0
_Z26mat_mult_transposed_kernelPiS_S_:
.quad _Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.size _Z26mat_mult_transposed_kernelPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26mat_mult_transposed_kernelPiS_S_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26mat_mult_transposed_kernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26mat_mult_transposed_kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ S2UR UR5, SR_CTAID.X ; /* 0x00000000000579c3 */
/* 0x000e620000002500 */
/*0030*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe40008011604 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x003fe400078e00ff */
/*0090*/ IADD3 R4, R4, UR5, RZ ; /* 0x0000000504047c10 */
/* 0x000fe2000fffe0ff */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fcc00078e00ff */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fce00078e00ff */
/*00e0*/ IADD3 R6, R0, R7, RZ ; /* 0x0000000700067210 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.AND P0, PT, R6, 0xef, PT ; /* 0x000000ef0600780c */
/* 0x000fda0003f04270 */
/*0100*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff078424 */
/* 0x000fe400078e00ff */
/*0110*/ @!P0 IMAD R8, R3, 0xf0, R6.reuse ; /* 0x000000f003088824 */
/* 0x100fe400078e0206 */
/*0120*/ @!P0 IMAD R6, R4, 0xf0, R6 ; /* 0x000000f004068824 */
/* 0x000fe400078e0206 */
/*0130*/ @!P0 IMAD.WIDE R8, R8, R7, c[0x0][0x168] ; /* 0x00005a0008088625 */
/* 0x000fc800078e0207 */
/*0140*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006068625 */
/* 0x000fe400078e0207 */
/*0150*/ @!P0 LDG.E R8, [R8.64] ; /* 0x0000000608088981 */
/* 0x000ea8000c1e1900 */
/*0160*/ @!P0 LDG.E R7, [R6.64] ; /* 0x0000000606078981 */
/* 0x000ea2000c1e1900 */
/*0170*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0190*/ @!P0 IMAD R11, R8, R7, RZ ; /* 0x00000007080b8224 */
/* 0x004fca00078e02ff */
/*01a0*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @!P1 BRA 0x280 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*01d0*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x001fc80008000f00 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f06070 */
/*01f0*/ @!P0 IMAD R8, R7, 0x4, R2 ; /* 0x0000000407088824 */
/* 0x000fe200078e0202 */
/*0200*/ @!P0 LDS R6, [R0.X4] ; /* 0x0000000000068984 */
/* 0x000fe20000004800 */
/*0210*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fc60000011607 */
/*0220*/ @!P0 LDS R9, [R8] ; /* 0x0000000008098984 */
/* 0x000e240000000800 */
/*0230*/ @!P0 IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106098824 */
/* 0x001fca00078e0209 */
/*0240*/ @!P0 STS [R0.X4], R9 ; /* 0x0000000900008388 */
/* 0x0001e80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0260*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0270*/ @P0 BRA 0x1e0 ; /* 0xffffff6000000947 */
/* 0x001fea000383ffff */
/*0280*/ LDS R6, [RZ] ; /* 0x00000000ff067984 */
/* 0x001e220000000800 */
/*0290*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f05270 */
/*02b0*/ IMAD R7, R12, c[0x0][0x0], RZ ; /* 0x000000000c077a24 */
/* 0x000fca00078e02ff */
/*02c0*/ ISETP.GE.U32.AND P1, PT, R7, 0xf0, PT ; /* 0x000000f00700780c */
/* 0x000fe40003f26070 */
/*02d0*/ SEL R6, R6, RZ, !P0 ; /* 0x000000ff06067207 */
/* 0x001fc80004000000 */
/*02e0*/ IADD3 R5, R6, R5, RZ ; /* 0x0000000506057210 */
/* 0x000fce0007ffe0ff */
/*02f0*/ @!P1 BRA 0xe0 ; /* 0xfffffde000009947 */
/* 0x000fea000383ffff */
/*0300*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0310*/ @!P0 MOV R7, 0x4 ; /* 0x0000000400078802 */
/* 0x000fe20000000f00 */
/*0320*/ @!P0 IMAD R6, R4, 0x200, R3 ; /* 0x0000020004068824 */
/* 0x000fe200078e0203 */
/*0330*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc60007ffe0ff */
/*0340*/ @!P0 IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006068625 */
/* 0x000fca00078e0207 */
/*0350*/ @!P0 STG.E [R6.64], R5 ; /* 0x0000000506008986 */
/* 0x0001e2000c101906 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R3, 0x200, PT ; /* 0x000002000300780c */
/* 0x000fda0003f06070 */
/*0370*/ @!P0 BRA 0xb0 ; /* 0xfffffd3000008947 */
/* 0x001fea000383ffff */
/*0380*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fca0007ffe0ff */
/*0390*/ IMAD R4, R10, c[0x0][0xc], RZ ; /* 0x000003000a047a24 */
/* 0x000fca00078e02ff */
/*03a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x100, PT ; /* 0x000001000400780c */
/* 0x000fda0003f06070 */
/*03b0*/ @!P0 BRA 0x90 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ BRA 0x3d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26mat_mult_transposed_kernelPiS_S_
.globl _Z26mat_mult_transposed_kernelPiS_S_
.p2align 8
.type _Z26mat_mult_transposed_kernelPiS_S_,@function
_Z26mat_mult_transposed_kernelPiS_S_:
s_clause 0x3
s_load_b32 s9, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0
v_cmp_eq_u32_e64 s0, 0, v0
s_mov_b32 s11, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s1, 1
s_cselect_b32 s9, -1, 0
s_branch .LBB0_2
.LBB0_1:
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s11, s8, s10
s_cmpk_gt_u32 s11, 0xff
s_cbranch_scc1 .LBB0_18
.LBB0_2:
s_add_i32 s12, s11, s15
s_mov_b32 s13, 0
s_mul_i32 s11, s12, 0xf0
s_lshl_b32 s12, s12, 9
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s13, s13, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s13, 0x200
s_cbranch_scc1 .LBB0_1
.LBB0_4:
v_mov_b32_e32 v4, 0
s_mul_i32 s14, s13, 0xf0
s_mov_b32 s17, 0
s_mov_b32 s16, 0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s17, s16, s1
s_cmpk_gt_u32 s17, 0xef
s_cbranch_scc1 .LBB0_16
.LBB0_6:
v_add_nc_u32_e32 v1, s17, v0
s_mov_b32 s17, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0xf0, v1
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v5, s11, v1
v_add_nc_u32_e32 v1, s14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[5:6], off
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v5, v1
ds_store_b32 v3, v1
.LBB0_8:
s_and_not1_saveexec_b32 s17, s17
s_cbranch_execz .LBB0_10
ds_store_b32 v3, v2
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s9
s_mov_b32 s17, s1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_14
.LBB0_11:
s_and_saveexec_b32 s17, s0
s_cbranch_execz .LBB0_5
ds_load_b32 v1, v3
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v1, v4
s_branch .LBB0_5
.p2align 6
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s19
s_cmp_lt_u32 s17, 4
s_mov_b32 s17, s18
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
.LBB0_14:
s_lshr_b32 s18, s17, 1
s_mov_b32 s19, exec_lo
v_cmpx_gt_u32_e64 s18, v0
s_cbranch_execz .LBB0_13
v_add_lshl_u32 v1, s18, v0, 2
ds_load_b32 v5, v3
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v1, v5
ds_store_b32 v3, v1
s_branch .LBB0_13
.LBB0_16:
s_and_saveexec_b32 s14, s0
s_cbranch_execz .LBB0_3
s_add_i32 s16, s13, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s17, s16, 31
s_lshl_b64 s[16:17], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s2, s16
s_addc_u32 s17, s3, s17
global_store_b32 v2, v4, s[16:17]
s_branch .LBB0_3
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26mat_mult_transposed_kernelPiS_S_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26mat_mult_transposed_kernelPiS_S_, .Lfunc_end0-_Z26mat_mult_transposed_kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26mat_mult_transposed_kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z26mat_mult_transposed_kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c112d_00000000-6_mat_mult_transposed_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_
.type _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_, @function
_Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26mat_mult_transposed_kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_, .-_Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_
.globl _Z26mat_mult_transposed_kernelPiS_S_
.type _Z26mat_mult_transposed_kernelPiS_S_, @function
_Z26mat_mult_transposed_kernelPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z26mat_mult_transposed_kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26mat_mult_transposed_kernelPiS_S_, .-_Z26mat_mult_transposed_kernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26mat_mult_transposed_kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26mat_mult_transposed_kernelPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mult_transposed_kernel.hip"
.globl _Z41__device_stub__mat_mult_transposed_kernelPiS_S_ # -- Begin function _Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.p2align 4, 0x90
.type _Z41__device_stub__mat_mult_transposed_kernelPiS_S_,@function
_Z41__device_stub__mat_mult_transposed_kernelPiS_S_: # @_Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26mat_mult_transposed_kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z41__device_stub__mat_mult_transposed_kernelPiS_S_, .Lfunc_end0-_Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26mat_mult_transposed_kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26mat_mult_transposed_kernelPiS_S_,@object # @_Z26mat_mult_transposed_kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z26mat_mult_transposed_kernelPiS_S_
.p2align 3, 0x0
_Z26mat_mult_transposed_kernelPiS_S_:
.quad _Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.size _Z26mat_mult_transposed_kernelPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26mat_mult_transposed_kernelPiS_S_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__mat_mult_transposed_kernelPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26mat_mult_transposed_kernelPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ inline float3 addCuda(float3 a, float3 b) {
return{ a.x + b.x, a.y + b.y, a.z + b.z };
}
__device__ inline float3 multiplyCuda(float a, float3 b) {
return{ a * b.x, a * b.y, a * b.z };
}
__device__ inline float euclideanLenCuda(float3 a, float3 b, float d) {
float mod = (b.x - a.x) * (b.x - a.x) + (b.y - a.y) * (b.y - a.y) + (b.z - a.z) * (b.z - a.z);
return expf(-mod / (2.0f * d * d));
}
__global__ void bilateralFilterCudaKernel(float3 * dev_input, float3 * dev_output, float l2norm, int width, int height, int radius)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x<width) && (y<height))
{
float sum = 0.0f;
float3 t = { 0.f, 0.f, 0.f };
float3 center = dev_input[y * width + x];
int r = radius;
float domainDist = 0.0f, colorDist = 0.0f, factor = 0.0f;
for (int i = -r; i <= r; i++) {
int crtY = y + i;
if (crtY < 0) crtY = 0;
else if (crtY >= height) crtY = height - 1;
for (int j = -r; j <= r; ++j) {
int crtX = x + j;
if (crtX < 0) crtX = 0;
else if (crtX >= width) crtX = width - 1;
float3 curPix = dev_input[crtY * width + crtX];
domainDist = c_gaussian[r + i] * c_gaussian[r + j];
colorDist = euclideanLenCuda(curPix, center, l2norm);
factor = domainDist * colorDist;
sum += factor;
t = addCuda(t, multiplyCuda(factor, curPix));
}
}
dev_output[y * width + x] = multiplyCuda(1.f / sum, t);
}
} | .file "tmpxft_00116212_00000000-6_bilateralFilterCudaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii
.type _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii, @function
_Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25bilateralFilterCudaKernelP6float3S0_fiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii, .-_Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii
.globl _Z25bilateralFilterCudaKernelP6float3S0_fiii
.type _Z25bilateralFilterCudaKernelP6float3S0_fiii, @function
_Z25bilateralFilterCudaKernelP6float3S0_fiii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z25bilateralFilterCudaKernelP6float3S0_fiii, .-_Z25bilateralFilterCudaKernelP6float3S0_fiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25bilateralFilterCudaKernelP6float3S0_fiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_gaussian"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25bilateralFilterCudaKernelP6float3S0_fiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10c_gaussian(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10c_gaussian
.comm _ZL10c_gaussian,256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ inline float3 addCuda(float3 a, float3 b) {
return{ a.x + b.x, a.y + b.y, a.z + b.z };
}
__device__ inline float3 multiplyCuda(float a, float3 b) {
return{ a * b.x, a * b.y, a * b.z };
}
__device__ inline float euclideanLenCuda(float3 a, float3 b, float d) {
float mod = (b.x - a.x) * (b.x - a.x) + (b.y - a.y) * (b.y - a.y) + (b.z - a.z) * (b.z - a.z);
return expf(-mod / (2.0f * d * d));
}
__global__ void bilateralFilterCudaKernel(float3 * dev_input, float3 * dev_output, float l2norm, int width, int height, int radius)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x<width) && (y<height))
{
float sum = 0.0f;
float3 t = { 0.f, 0.f, 0.f };
float3 center = dev_input[y * width + x];
int r = radius;
float domainDist = 0.0f, colorDist = 0.0f, factor = 0.0f;
for (int i = -r; i <= r; i++) {
int crtY = y + i;
if (crtY < 0) crtY = 0;
else if (crtY >= height) crtY = height - 1;
for (int j = -r; j <= r; ++j) {
int crtX = x + j;
if (crtX < 0) crtX = 0;
else if (crtX >= width) crtX = width - 1;
float3 curPix = dev_input[crtY * width + crtX];
domainDist = c_gaussian[r + i] * c_gaussian[r + j];
colorDist = euclideanLenCuda(curPix, center, l2norm);
factor = domainDist * colorDist;
sum += factor;
t = addCuda(t, multiplyCuda(factor, curPix));
}
}
dev_output[y * width + x] = multiplyCuda(1.f / sum, t);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline float3 addCuda(float3 a, float3 b) {
return{ a.x + b.x, a.y + b.y, a.z + b.z };
}
__device__ inline float3 multiplyCuda(float a, float3 b) {
return{ a * b.x, a * b.y, a * b.z };
}
__device__ inline float euclideanLenCuda(float3 a, float3 b, float d) {
float mod = (b.x - a.x) * (b.x - a.x) + (b.y - a.y) * (b.y - a.y) + (b.z - a.z) * (b.z - a.z);
return expf(-mod / (2.0f * d * d));
}
__global__ void bilateralFilterCudaKernel(float3 * dev_input, float3 * dev_output, float l2norm, int width, int height, int radius)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x<width) && (y<height))
{
float sum = 0.0f;
float3 t = { 0.f, 0.f, 0.f };
float3 center = dev_input[y * width + x];
int r = radius;
float domainDist = 0.0f, colorDist = 0.0f, factor = 0.0f;
for (int i = -r; i <= r; i++) {
int crtY = y + i;
if (crtY < 0) crtY = 0;
else if (crtY >= height) crtY = height - 1;
for (int j = -r; j <= r; ++j) {
int crtX = x + j;
if (crtX < 0) crtX = 0;
else if (crtX >= width) crtX = width - 1;
float3 curPix = dev_input[crtY * width + crtX];
domainDist = c_gaussian[r + i] * c_gaussian[r + j];
colorDist = euclideanLenCuda(curPix, center, l2norm);
factor = domainDist * colorDist;
sum += factor;
t = addCuda(t, multiplyCuda(factor, curPix));
}
}
dev_output[y * width + x] = multiplyCuda(1.f / sum, t);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline float3 addCuda(float3 a, float3 b) {
return{ a.x + b.x, a.y + b.y, a.z + b.z };
}
__device__ inline float3 multiplyCuda(float a, float3 b) {
return{ a * b.x, a * b.y, a * b.z };
}
__device__ inline float euclideanLenCuda(float3 a, float3 b, float d) {
float mod = (b.x - a.x) * (b.x - a.x) + (b.y - a.y) * (b.y - a.y) + (b.z - a.z) * (b.z - a.z);
return expf(-mod / (2.0f * d * d));
}
__global__ void bilateralFilterCudaKernel(float3 * dev_input, float3 * dev_output, float l2norm, int width, int height, int radius)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x<width) && (y<height))
{
float sum = 0.0f;
float3 t = { 0.f, 0.f, 0.f };
float3 center = dev_input[y * width + x];
int r = radius;
float domainDist = 0.0f, colorDist = 0.0f, factor = 0.0f;
for (int i = -r; i <= r; i++) {
int crtY = y + i;
if (crtY < 0) crtY = 0;
else if (crtY >= height) crtY = height - 1;
for (int j = -r; j <= r; ++j) {
int crtX = x + j;
if (crtX < 0) crtX = 0;
else if (crtX >= width) crtX = width - 1;
float3 curPix = dev_input[crtY * width + crtX];
domainDist = c_gaussian[r + i] * c_gaussian[r + j];
colorDist = euclideanLenCuda(curPix, center, l2norm);
factor = domainDist * colorDist;
sum += factor;
t = addCuda(t, multiplyCuda(factor, curPix));
}
}
dev_output[y * width + x] = multiplyCuda(1.f / sum, t);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.globl _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.p2align 8
.type _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii,@function
_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
v_add_nc_u32_e32 v6, s14, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s4, v6
v_cmp_gt_i32_e64 s2, s5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_load_b32 s8, s[0:1], 0x1c
v_mad_u64_u32 v[3:4], null, v5, s4, v[6:7]
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, 0
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 0
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x10
v_subrev_nc_u32_e32 v6, s8, v6
v_mov_b32_e32 v8, 0
s_sub_i32 s10, 0, s8
s_add_i32 s9, s5, -1
s_add_i32 s11, s4, -1
v_mov_b32_e32 v7, 0
v_mov_b32_e32 v9, 0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v3, 12, s[2:3]
v_add_f32_e64 v4, s6, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mul_f32_e32 v10, s6, v4
global_load_b96 v[0:2], v[0:1], off
v_mov_b32_e32 v4, 0
s_lshl_b32 s6, s8, 1
s_or_b32 s12, s6, 1
.LBB0_3:
s_add_i32 s6, s10, s8
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, c_gaussian@rel32@lo+4
s_addc_u32 s15, s15, c_gaussian@rel32@hi+12
v_add_nc_u32_e32 v11, s10, v5
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[6:7], 2
s_add_u32 s6, s6, s14
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v11
s_addc_u32 s7, s7, s15
s_load_b32 s13, s[6:7], 0x0
s_mov_b32 s6, 0
v_cndmask_b32_e32 v12, s9, v11, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v11, 0, v12, vcc_lo
v_mul_lo_u32 v11, v11, s4
.LBB0_4:
v_add_nc_u32_e32 v12, s6, v6
s_ashr_i32 s7, s6, 31
s_getpc_b64 s[14:15]
s_add_u32 s14, s14, c_gaussian@rel32@lo+4
s_addc_u32 s15, s15, c_gaussian@rel32@hi+12
s_lshl_b64 s[16:17], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s16, s14
v_cmp_gt_i32_e32 vcc_lo, s4, v12
s_addc_u32 s15, s17, s15
s_add_i32 s6, s6, 1
s_load_b32 s7, s[14:15], 0x0
s_cmp_eq_u32 s12, s6
v_cndmask_b32_e32 v13, s11, v12, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v12, 0, v13, vcc_lo
v_add_nc_u32_e32 v14, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mad_i64_i32 v[12:13], null, v14, 12, s[2:3]
global_load_b96 v[12:14], v[12:13], off
s_waitcnt vmcnt(0)
v_dual_sub_f32 v15, v1, v13 :: v_dual_sub_f32 v16, v0, v12
v_sub_f32_e32 v17, v2, v14
v_mul_f32_e32 v15, v15, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v15, v16, v16
v_fmac_f32_e32 v15, v17, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v16, null, v10, v10, -v15
v_div_scale_f32 v19, vcc_lo, -v15, v10, -v15
v_rcp_f32_e32 v17, v16
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v16, v17, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v18, v17
v_mul_f32_e32 v18, v19, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v20, -v16, v18, v19
v_fmac_f32_e32 v18, v20, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v16, v18, v19
v_div_fmas_f32 v16, v16, v17, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v15, v16, v10, -v15
v_mul_f32_e32 v16, 0x3fb8aa3b, v15
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v17, v15, 0x3fb8aa3b, -v16
v_rndne_f32_e32 v18, v16
v_dual_fmac_f32 v17, 0x32a5705f, v15 :: v_dual_sub_f32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v16, v16, v17
v_cvt_i32_f32_e32 v17, v18
v_exp_f32_e32 v16, v16
s_waitcnt_depctr 0xfff
v_ldexp_f32 v16, v16, v17
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v17, s13, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v16, 0, v16, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
v_cndmask_b32_e32 v15, 0x7f800000, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v17, v15
v_mul_f32_e32 v16, v17, v15
v_fmac_f32_e32 v4, v12, v16
v_fmac_f32_e32 v8, v13, v16
v_fmac_f32_e32 v9, v14, v16
s_cbranch_scc0 .LBB0_4
s_add_i32 s6, s10, 1
s_cmp_eq_u32 s10, s8
s_cbranch_scc1 .LBB0_7
s_mov_b32 s10, s6
s_branch .LBB0_3
.LBB0_7:
v_div_scale_f32 v0, null, v7, v7, 1.0
v_div_scale_f32 v5, vcc_lo, 1.0, v7, 1.0
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v1, 1.0
v_fmac_f32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v5, v1
v_fma_f32 v6, -v0, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, v6, v1
v_fma_f32 v0, -v0, v2, v5
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[5:6], null, v3, 12, s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v0, v0, v1, v2
v_div_fixup_f32 v2, v0, v7, 1.0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v0, v4, v2
v_mul_f32_e32 v1, v8, v2
v_mul_f32_e32 v2, v9, v2
global_store_b96 v[5:6], v[0:2], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, .Lfunc_end0-_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected c_gaussian
.type c_gaussian,@object
.section .bss,"aw",@nobits
.globl c_gaussian
.p2align 4, 0x0
c_gaussian:
.zero 256
.size c_gaussian, 256
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym c_gaussian
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline float3 addCuda(float3 a, float3 b) {
return{ a.x + b.x, a.y + b.y, a.z + b.z };
}
__device__ inline float3 multiplyCuda(float a, float3 b) {
return{ a * b.x, a * b.y, a * b.z };
}
__device__ inline float euclideanLenCuda(float3 a, float3 b, float d) {
float mod = (b.x - a.x) * (b.x - a.x) + (b.y - a.y) * (b.y - a.y) + (b.z - a.z) * (b.z - a.z);
return expf(-mod / (2.0f * d * d));
}
__global__ void bilateralFilterCudaKernel(float3 * dev_input, float3 * dev_output, float l2norm, int width, int height, int radius)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if ((x<width) && (y<height))
{
float sum = 0.0f;
float3 t = { 0.f, 0.f, 0.f };
float3 center = dev_input[y * width + x];
int r = radius;
float domainDist = 0.0f, colorDist = 0.0f, factor = 0.0f;
for (int i = -r; i <= r; i++) {
int crtY = y + i;
if (crtY < 0) crtY = 0;
else if (crtY >= height) crtY = height - 1;
for (int j = -r; j <= r; ++j) {
int crtX = x + j;
if (crtX < 0) crtX = 0;
else if (crtX >= width) crtX = width - 1;
float3 curPix = dev_input[crtY * width + crtX];
domainDist = c_gaussian[r + i] * c_gaussian[r + j];
colorDist = euclideanLenCuda(curPix, center, l2norm);
factor = domainDist * colorDist;
sum += factor;
t = addCuda(t, multiplyCuda(factor, curPix));
}
}
dev_output[y * width + x] = multiplyCuda(1.f / sum, t);
}
} | .text
.file "bilateralFilterCudaKernel.hip"
.globl _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii # -- Begin function _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.p2align 4, 0x90
.type _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii,@function
_Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii: # @_Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, .Lfunc_end0-_Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_gaussian, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $256, %r9d # imm = 0x100
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_gaussian,@object # @c_gaussian
.local c_gaussian
.comm c_gaussian,256,16
.type _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii,@object # @_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.section .rodata,"a",@progbits
.globl _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.p2align 3, 0x0
_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii:
.quad _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.size _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii"
.size .L__unnamed_1, 62
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_gaussian"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_gaussian
.addrsig_sym _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00116212_00000000-6_bilateralFilterCudaKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii
.type _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii, @function
_Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii:
.LFB2054:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25bilateralFilterCudaKernelP6float3S0_fiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii, .-_Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii
.globl _Z25bilateralFilterCudaKernelP6float3S0_fiii
.type _Z25bilateralFilterCudaKernelP6float3S0_fiii, @function
_Z25bilateralFilterCudaKernelP6float3S0_fiii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z58__device_stub__Z25bilateralFilterCudaKernelP6float3S0_fiiiP6float3S0_fiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z25bilateralFilterCudaKernelP6float3S0_fiii, .-_Z25bilateralFilterCudaKernelP6float3S0_fiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25bilateralFilterCudaKernelP6float3S0_fiii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c_gaussian"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25bilateralFilterCudaKernelP6float3S0_fiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10c_gaussian(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL10c_gaussian
.comm _ZL10c_gaussian,256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bilateralFilterCudaKernel.hip"
.globl _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii # -- Begin function _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.p2align 4, 0x90
.type _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii,@function
_Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii: # @_Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, .Lfunc_end0-_Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $c_gaussian, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $256, %r9d # imm = 0x100
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type c_gaussian,@object # @c_gaussian
.local c_gaussian
.comm c_gaussian,256,16
.type _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii,@object # @_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.section .rodata,"a",@progbits
.globl _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.p2align 3, 0x0
_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii:
.quad _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.size _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii"
.size .L__unnamed_1, 62
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "c_gaussian"
.size .L__unnamed_2, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym c_gaussian
.addrsig_sym _Z25bilateralFilterCudaKernelP15HIP_vector_typeIfLj3EES1_fiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void MultiplicarMatrices(float *m1, float *m2, float *mr, int columna1, int fila1, int columna2, int fila2)
{
int fila_r = blockIdx.y*blockDim.y+threadIdx.y;
int columna_r = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_mult = 0;
if ((fila_r < fila2) && (columna_r < columna1)) {
for (int i = 0; i < fila2 ; i++) {
tmp_mult += m1[i+columna1*fila_r]*m2[i*columna2+columna_r];
}
mr[fila_r*columna2+columna_r]= tmp_mult;
}
} | code for sm_80
Function : _Z19MultiplicarMatricesPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x184], RZ ; /* 0x0000610004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fcc00078e0208 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R0, c[0x0][0x178], R2 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0203 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void MultiplicarMatrices(float *m1, float *m2, float *mr, int columna1, int fila1, int columna2, int fila2)
{
int fila_r = blockIdx.y*blockDim.y+threadIdx.y;
int columna_r = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_mult = 0;
if ((fila_r < fila2) && (columna_r < columna1)) {
for (int i = 0; i < fila2 ; i++) {
tmp_mult += m1[i+columna1*fila_r]*m2[i*columna2+columna_r];
}
mr[fila_r*columna2+columna_r]= tmp_mult;
}
} | .file "tmpxft_000ce32f_00000000-6_MultiplicarMatrices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii
.type _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii, @function
_Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19MultiplicarMatricesPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii, .-_Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii
.globl _Z19MultiplicarMatricesPfS_S_iiii
.type _Z19MultiplicarMatricesPfS_S_iiii, @function
_Z19MultiplicarMatricesPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19MultiplicarMatricesPfS_S_iiii, .-_Z19MultiplicarMatricesPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19MultiplicarMatricesPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MultiplicarMatricesPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void MultiplicarMatrices(float *m1, float *m2, float *mr, int columna1, int fila1, int columna2, int fila2)
{
int fila_r = blockIdx.y*blockDim.y+threadIdx.y;
int columna_r = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_mult = 0;
if ((fila_r < fila2) && (columna_r < columna1)) {
for (int i = 0; i < fila2 ; i++) {
tmp_mult += m1[i+columna1*fila_r]*m2[i*columna2+columna_r];
}
mr[fila_r*columna2+columna_r]= tmp_mult;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MultiplicarMatrices(float *m1, float *m2, float *mr, int columna1, int fila1, int columna2, int fila2)
{
int fila_r = blockIdx.y*blockDim.y+threadIdx.y;
int columna_r = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_mult = 0;
if ((fila_r < fila2) && (columna_r < columna1)) {
for (int i = 0; i < fila2 ; i++) {
tmp_mult += m1[i+columna1*fila_r]*m2[i*columna2+columna_r];
}
mr[fila_r*columna2+columna_r]= tmp_mult;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MultiplicarMatrices(float *m1, float *m2, float *mr, int columna1, int fila1, int columna2, int fila2)
{
int fila_r = blockIdx.y*blockDim.y+threadIdx.y;
int columna_r = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_mult = 0;
if ((fila_r < fila2) && (columna_r < columna1)) {
for (int i = 0; i < fila2 ; i++) {
tmp_mult += m1[i+columna1*fila_r]*m2[i*columna2+columna_r];
}
mr[fila_r*columna2+columna_r]= tmp_mult;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19MultiplicarMatricesPfS_S_iiii
.globl _Z19MultiplicarMatricesPfS_S_iiii
.p2align 8
.type _Z19MultiplicarMatricesPfS_S_iiii,@function
_Z19MultiplicarMatricesPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s8, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x20
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s8
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19MultiplicarMatricesPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19MultiplicarMatricesPfS_S_iiii, .Lfunc_end0-_Z19MultiplicarMatricesPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19MultiplicarMatricesPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19MultiplicarMatricesPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void MultiplicarMatrices(float *m1, float *m2, float *mr, int columna1, int fila1, int columna2, int fila2)
{
int fila_r = blockIdx.y*blockDim.y+threadIdx.y;
int columna_r = blockIdx.x*blockDim.x+threadIdx.x;
float tmp_mult = 0;
if ((fila_r < fila2) && (columna_r < columna1)) {
for (int i = 0; i < fila2 ; i++) {
tmp_mult += m1[i+columna1*fila_r]*m2[i*columna2+columna_r];
}
mr[fila_r*columna2+columna_r]= tmp_mult;
}
} | .text
.file "MultiplicarMatrices.hip"
.globl _Z34__device_stub__MultiplicarMatricesPfS_S_iiii # -- Begin function _Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.p2align 4, 0x90
.type _Z34__device_stub__MultiplicarMatricesPfS_S_iiii,@function
_Z34__device_stub__MultiplicarMatricesPfS_S_iiii: # @_Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19MultiplicarMatricesPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__MultiplicarMatricesPfS_S_iiii, .Lfunc_end0-_Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MultiplicarMatricesPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19MultiplicarMatricesPfS_S_iiii,@object # @_Z19MultiplicarMatricesPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z19MultiplicarMatricesPfS_S_iiii
.p2align 3, 0x0
_Z19MultiplicarMatricesPfS_S_iiii:
.quad _Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.size _Z19MultiplicarMatricesPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19MultiplicarMatricesPfS_S_iiii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19MultiplicarMatricesPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19MultiplicarMatricesPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x184], RZ ; /* 0x0000610004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fcc00078e0208 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R0, c[0x0][0x178], R2 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0203 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19MultiplicarMatricesPfS_S_iiii
.globl _Z19MultiplicarMatricesPfS_S_iiii
.p2align 8
.type _Z19MultiplicarMatricesPfS_S_iiii,@function
_Z19MultiplicarMatricesPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s8, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x20
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s8
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19MultiplicarMatricesPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19MultiplicarMatricesPfS_S_iiii, .Lfunc_end0-_Z19MultiplicarMatricesPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19MultiplicarMatricesPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19MultiplicarMatricesPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce32f_00000000-6_MultiplicarMatrices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii
.type _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii, @function
_Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19MultiplicarMatricesPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii, .-_Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii
.globl _Z19MultiplicarMatricesPfS_S_iiii
.type _Z19MultiplicarMatricesPfS_S_iiii, @function
_Z19MultiplicarMatricesPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z47__device_stub__Z19MultiplicarMatricesPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19MultiplicarMatricesPfS_S_iiii, .-_Z19MultiplicarMatricesPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19MultiplicarMatricesPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19MultiplicarMatricesPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MultiplicarMatrices.hip"
.globl _Z34__device_stub__MultiplicarMatricesPfS_S_iiii # -- Begin function _Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.p2align 4, 0x90
.type _Z34__device_stub__MultiplicarMatricesPfS_S_iiii,@function
_Z34__device_stub__MultiplicarMatricesPfS_S_iiii: # @_Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19MultiplicarMatricesPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__MultiplicarMatricesPfS_S_iiii, .Lfunc_end0-_Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19MultiplicarMatricesPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19MultiplicarMatricesPfS_S_iiii,@object # @_Z19MultiplicarMatricesPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z19MultiplicarMatricesPfS_S_iiii
.p2align 3, 0x0
_Z19MultiplicarMatricesPfS_S_iiii:
.quad _Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.size _Z19MultiplicarMatricesPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19MultiplicarMatricesPfS_S_iiii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__MultiplicarMatricesPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19MultiplicarMatricesPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
const int N = 100;
const int M = 100;
__global__ void matrixAdd(int* A, int* B, int* C){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int pos = i * N + j;
if(i < N && j < M && (N*M) <= 1024){
C[pos] = A[pos] + B[pos];
}
}
/*
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}*/
void fError(cudaError_t err){
if(err != cudaSuccess){
printf("Ha ocurrido un error con codigo: %s\n", cudaGetErrorString(err));
}
}
int main(){
//Reservar espacio en memoria HOST
int h_A[N][M];
int h_B[N][M];
int h_C[N][M];
//int * h_A = (int*)malloc(num_elements * sizeof(int));
//int * h_B = (int*)malloc(num_elements * sizeof(int));
//int * h_C = (int*)malloc(num_elements * sizeof(int));
/*if(h_A == NULL || h_B == NULL || h_C == NULL){
printf("Error al reservar memoria para los vectores HOST");
exit(1);
}*/
//Inicializar elementos de los vectores
for(int i=0; i<N; i++){
for(int j=0; j<M; j++){
h_A[i][j] = 1;
h_B[i][j] = i;
}
}
cudaError_t err;
int size = N * M * sizeof(int);
//int size_col = M * sizeof(int);
int * d_A = NULL;
err = cudaMalloc((void **)(&d_A), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_A[i]), size_col);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//}
//err = cudaMalloc((void **)*&d_A, size)
int * d_B = NULL;
err = cudaMalloc((void **)(&d_B), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_B[i]), size_col);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//}
int * d_C = NULL;
err = cudaMalloc((void **)(&d_C), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_C[i]), size_col);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//}
//Copiamos a GPU DEVICE
//err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//int HilosPorBloque = 512;
int hilos = 256;
int bloques = (N * M + hilos - 1) / hilos;
dim3 HilosPorBloque(16,16,1);
//int BloquesPorGrid = (N * M + HilosPorBloque -1) / HilosPorBloque;
dim3 BloquesPorGrid(bloques, bloques);
cudaError_t Err;
//Lanzamos el kernel y medimos tiempos
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
matrixAdd<<<BloquesPorGrid, HilosPorBloque>>>(reinterpret_cast<int*>(&d_A), reinterpret_cast<int*>(&d_B), reinterpret_cast<int*>(&d_C));
Err = cudaGetLastError();
fError(Err);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float tiempo_reserva_host;
cudaEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
cudaEventDestroy(start);
cudaEventDestroy(stop);
for(int i=0; i<N*M; i++){
printf("%d\n", d_C[i]);
printf("\n");
}
//Copiamos a CPU el vector C
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
} | code for sm_80
Function : _Z9matrixAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
const int N = 100;
const int M = 100;
__global__ void matrixAdd(int* A, int* B, int* C){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int pos = i * N + j;
if(i < N && j < M && (N*M) <= 1024){
C[pos] = A[pos] + B[pos];
}
}
/*
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}*/
void fError(cudaError_t err){
if(err != cudaSuccess){
printf("Ha ocurrido un error con codigo: %s\n", cudaGetErrorString(err));
}
}
int main(){
//Reservar espacio en memoria HOST
int h_A[N][M];
int h_B[N][M];
int h_C[N][M];
//int * h_A = (int*)malloc(num_elements * sizeof(int));
//int * h_B = (int*)malloc(num_elements * sizeof(int));
//int * h_C = (int*)malloc(num_elements * sizeof(int));
/*if(h_A == NULL || h_B == NULL || h_C == NULL){
printf("Error al reservar memoria para los vectores HOST");
exit(1);
}*/
//Inicializar elementos de los vectores
for(int i=0; i<N; i++){
for(int j=0; j<M; j++){
h_A[i][j] = 1;
h_B[i][j] = i;
}
}
cudaError_t err;
int size = N * M * sizeof(int);
//int size_col = M * sizeof(int);
int * d_A = NULL;
err = cudaMalloc((void **)(&d_A), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_A[i]), size_col);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//}
//err = cudaMalloc((void **)*&d_A, size)
int * d_B = NULL;
err = cudaMalloc((void **)(&d_B), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_B[i]), size_col);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//}
int * d_C = NULL;
err = cudaMalloc((void **)(&d_C), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_C[i]), size_col);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//}
//Copiamos a GPU DEVICE
//err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//int HilosPorBloque = 512;
int hilos = 256;
int bloques = (N * M + hilos - 1) / hilos;
dim3 HilosPorBloque(16,16,1);
//int BloquesPorGrid = (N * M + HilosPorBloque -1) / HilosPorBloque;
dim3 BloquesPorGrid(bloques, bloques);
cudaError_t Err;
//Lanzamos el kernel y medimos tiempos
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
matrixAdd<<<BloquesPorGrid, HilosPorBloque>>>(reinterpret_cast<int*>(&d_A), reinterpret_cast<int*>(&d_B), reinterpret_cast<int*>(&d_C));
Err = cudaGetLastError();
fError(Err);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float tiempo_reserva_host;
cudaEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
cudaEventDestroy(start);
cudaEventDestroy(stop);
for(int i=0; i<N*M; i++){
printf("%d\n", d_C[i]);
printf("\n");
}
//Copiamos a CPU el vector C
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
} | .file "tmpxft_000c66c0_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Ha ocurrido un error con codigo: %s\n"
.text
.globl _Z6fError9cudaError
.type _Z6fError9cudaError, @function
_Z6fError9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6fError9cudaError, .-_Z6fError9cudaError
.globl _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.type _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, @function
_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, .-_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.globl _Z9matrixAddPiS_S_
.type _Z9matrixAddPiS_S_, @function
_Z9matrixAddPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9matrixAddPiS_S_, .-_Z9matrixAddPiS_S_
.section .rodata.str1.8
.align 8
.LC1:
.string "Tiempo de suma vectores DEVICE: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d\n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -118784(%rsp), %r11
.cfi_def_cfa 11, 118816
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1312, %rsp
.cfi_def_cfa_offset 120128
movq %fs:40, %rax
movq %rax, 120088(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rsi
leaq 40080(%rsp), %rcx
movl $0, %edx
.L19:
movl $0, %eax
.L20:
movl $1, (%rsi,%rax)
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L20
addl $1, %edx
addq $400, %rsi
addq $400, %rcx
cmpl $100, %edx
jne .L19
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z6fError9cudaError
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z6fError9cudaError
leaq 40080(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z6fError9cudaError
leaq 80080(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $40, 68(%rsp)
movl $40, 72(%rsp)
movl $1, 76(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
call cudaGetLastError@PLT
movl %eax, %edi
call _Z6fError9cudaError
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %rbp
.L23:
movq 32(%rsp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40000, %rbx
jne .L23
leaq 80080(%rsp), %rdi
movl $2, %ecx
movl $40000, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq 120088(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $120096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9matrixAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
const int N = 100;
const int M = 100;
__global__ void matrixAdd(int* A, int* B, int* C){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int pos = i * N + j;
if(i < N && j < M && (N*M) <= 1024){
C[pos] = A[pos] + B[pos];
}
}
/*
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}*/
void fError(cudaError_t err){
if(err != cudaSuccess){
printf("Ha ocurrido un error con codigo: %s\n", cudaGetErrorString(err));
}
}
int main(){
//Reservar espacio en memoria HOST
int h_A[N][M];
int h_B[N][M];
int h_C[N][M];
//int * h_A = (int*)malloc(num_elements * sizeof(int));
//int * h_B = (int*)malloc(num_elements * sizeof(int));
//int * h_C = (int*)malloc(num_elements * sizeof(int));
/*if(h_A == NULL || h_B == NULL || h_C == NULL){
printf("Error al reservar memoria para los vectores HOST");
exit(1);
}*/
//Inicializar elementos de los vectores
for(int i=0; i<N; i++){
for(int j=0; j<M; j++){
h_A[i][j] = 1;
h_B[i][j] = i;
}
}
cudaError_t err;
int size = N * M * sizeof(int);
//int size_col = M * sizeof(int);
int * d_A = NULL;
err = cudaMalloc((void **)(&d_A), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_A[i]), size_col);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//}
//err = cudaMalloc((void **)*&d_A, size)
int * d_B = NULL;
err = cudaMalloc((void **)(&d_B), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_B[i]), size_col);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//}
int * d_C = NULL;
err = cudaMalloc((void **)(&d_C), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_C[i]), size_col);
cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//}
//Copiamos a GPU DEVICE
//err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//int HilosPorBloque = 512;
int hilos = 256;
int bloques = (N * M + hilos - 1) / hilos;
dim3 HilosPorBloque(16,16,1);
//int BloquesPorGrid = (N * M + HilosPorBloque -1) / HilosPorBloque;
dim3 BloquesPorGrid(bloques, bloques);
cudaError_t Err;
//Lanzamos el kernel y medimos tiempos
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
matrixAdd<<<BloquesPorGrid, HilosPorBloque>>>(reinterpret_cast<int*>(&d_A), reinterpret_cast<int*>(&d_B), reinterpret_cast<int*>(&d_C));
Err = cudaGetLastError();
fError(Err);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float tiempo_reserva_host;
cudaEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
cudaEventDestroy(start);
cudaEventDestroy(stop);
for(int i=0; i<N*M; i++){
printf("%d\n", d_C[i]);
printf("\n");
}
//Copiamos a CPU el vector C
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
const int N = 100;
const int M = 100;
__global__ void matrixAdd(int* A, int* B, int* C){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int pos = i * N + j;
if(i < N && j < M && (N*M) <= 1024){
C[pos] = A[pos] + B[pos];
}
}
/*
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}*/
void fError(hipError_t err){
if(err != hipSuccess){
printf("Ha ocurrido un error con codigo: %s\n", hipGetErrorString(err));
}
}
int main(){
//Reservar espacio en memoria HOST
int h_A[N][M];
int h_B[N][M];
int h_C[N][M];
//int * h_A = (int*)malloc(num_elements * sizeof(int));
//int * h_B = (int*)malloc(num_elements * sizeof(int));
//int * h_C = (int*)malloc(num_elements * sizeof(int));
/*if(h_A == NULL || h_B == NULL || h_C == NULL){
printf("Error al reservar memoria para los vectores HOST");
exit(1);
}*/
//Inicializar elementos de los vectores
for(int i=0; i<N; i++){
for(int j=0; j<M; j++){
h_A[i][j] = 1;
h_B[i][j] = i;
}
}
hipError_t err;
int size = N * M * sizeof(int);
//int size_col = M * sizeof(int);
int * d_A = NULL;
err = hipMalloc((void **)(&d_A), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_A[i]), size_col);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
//}
//err = cudaMalloc((void **)*&d_A, size)
int * d_B = NULL;
err = hipMalloc((void **)(&d_B), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_B[i]), size_col);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//}
int * d_C = NULL;
err = hipMalloc((void **)(&d_C), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_C[i]), size_col);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
//}
//Copiamos a GPU DEVICE
//err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//int HilosPorBloque = 512;
int hilos = 256;
int bloques = (N * M + hilos - 1) / hilos;
dim3 HilosPorBloque(16,16,1);
//int BloquesPorGrid = (N * M + HilosPorBloque -1) / HilosPorBloque;
dim3 BloquesPorGrid(bloques, bloques);
hipError_t Err;
//Lanzamos el kernel y medimos tiempos
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
matrixAdd<<<BloquesPorGrid, HilosPorBloque>>>(reinterpret_cast<int*>(&d_A), reinterpret_cast<int*>(&d_B), reinterpret_cast<int*>(&d_C));
Err = hipGetLastError();
fError(Err);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float tiempo_reserva_host;
hipEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
hipEventDestroy(start);
hipEventDestroy(stop);
for(int i=0; i<N*M; i++){
printf("%d\n", d_C[i]);
printf("\n");
}
//Copiamos a CPU el vector C
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
const int N = 100;
const int M = 100;
__global__ void matrixAdd(int* A, int* B, int* C){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int pos = i * N + j;
if(i < N && j < M && (N*M) <= 1024){
C[pos] = A[pos] + B[pos];
}
}
/*
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}*/
void fError(hipError_t err){
if(err != hipSuccess){
printf("Ha ocurrido un error con codigo: %s\n", hipGetErrorString(err));
}
}
int main(){
//Reservar espacio en memoria HOST
int h_A[N][M];
int h_B[N][M];
int h_C[N][M];
//int * h_A = (int*)malloc(num_elements * sizeof(int));
//int * h_B = (int*)malloc(num_elements * sizeof(int));
//int * h_C = (int*)malloc(num_elements * sizeof(int));
/*if(h_A == NULL || h_B == NULL || h_C == NULL){
printf("Error al reservar memoria para los vectores HOST");
exit(1);
}*/
//Inicializar elementos de los vectores
for(int i=0; i<N; i++){
for(int j=0; j<M; j++){
h_A[i][j] = 1;
h_B[i][j] = i;
}
}
hipError_t err;
int size = N * M * sizeof(int);
//int size_col = M * sizeof(int);
int * d_A = NULL;
err = hipMalloc((void **)(&d_A), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_A[i]), size_col);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
//}
//err = cudaMalloc((void **)*&d_A, size)
int * d_B = NULL;
err = hipMalloc((void **)(&d_B), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_B[i]), size_col);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//}
int * d_C = NULL;
err = hipMalloc((void **)(&d_C), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_C[i]), size_col);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
//}
//Copiamos a GPU DEVICE
//err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//int HilosPorBloque = 512;
int hilos = 256;
int bloques = (N * M + hilos - 1) / hilos;
dim3 HilosPorBloque(16,16,1);
//int BloquesPorGrid = (N * M + HilosPorBloque -1) / HilosPorBloque;
dim3 BloquesPorGrid(bloques, bloques);
hipError_t Err;
//Lanzamos el kernel y medimos tiempos
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
matrixAdd<<<BloquesPorGrid, HilosPorBloque>>>(reinterpret_cast<int*>(&d_A), reinterpret_cast<int*>(&d_B), reinterpret_cast<int*>(&d_C));
Err = hipGetLastError();
fError(Err);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float tiempo_reserva_host;
hipEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
hipEventDestroy(start);
hipEventDestroy(stop);
for(int i=0; i<N*M; i++){
printf("%d\n", d_C[i]);
printf("\n");
}
//Copiamos a CPU el vector C
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPiS_S_
.globl _Z9matrixAddPiS_S_
.p2align 8
.type _Z9matrixAddPiS_S_,@function
_Z9matrixAddPiS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPiS_S_, .Lfunc_end0-_Z9matrixAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
const int N = 100;
const int M = 100;
__global__ void matrixAdd(int* A, int* B, int* C){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int pos = i * N + j;
if(i < N && j < M && (N*M) <= 1024){
C[pos] = A[pos] + B[pos];
}
}
/*
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}*/
void fError(hipError_t err){
if(err != hipSuccess){
printf("Ha ocurrido un error con codigo: %s\n", hipGetErrorString(err));
}
}
int main(){
//Reservar espacio en memoria HOST
int h_A[N][M];
int h_B[N][M];
int h_C[N][M];
//int * h_A = (int*)malloc(num_elements * sizeof(int));
//int * h_B = (int*)malloc(num_elements * sizeof(int));
//int * h_C = (int*)malloc(num_elements * sizeof(int));
/*if(h_A == NULL || h_B == NULL || h_C == NULL){
printf("Error al reservar memoria para los vectores HOST");
exit(1);
}*/
//Inicializar elementos de los vectores
for(int i=0; i<N; i++){
for(int j=0; j<M; j++){
h_A[i][j] = 1;
h_B[i][j] = i;
}
}
hipError_t err;
int size = N * M * sizeof(int);
//int size_col = M * sizeof(int);
int * d_A = NULL;
err = hipMalloc((void **)(&d_A), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_A[i]), size_col);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
//}
//err = cudaMalloc((void **)*&d_A, size)
int * d_B = NULL;
err = hipMalloc((void **)(&d_B), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_B[i]), size_col);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
//}
int * d_C = NULL;
err = hipMalloc((void **)(&d_C), size);
fError(err);
//for(int i=0; i<M; i++){
//cudaMalloc((void**)(&d_C[i]), size_col);
hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
//}
//Copiamos a GPU DEVICE
//err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
//err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
//int HilosPorBloque = 512;
int hilos = 256;
int bloques = (N * M + hilos - 1) / hilos;
dim3 HilosPorBloque(16,16,1);
//int BloquesPorGrid = (N * M + HilosPorBloque -1) / HilosPorBloque;
dim3 BloquesPorGrid(bloques, bloques);
hipError_t Err;
//Lanzamos el kernel y medimos tiempos
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
matrixAdd<<<BloquesPorGrid, HilosPorBloque>>>(reinterpret_cast<int*>(&d_A), reinterpret_cast<int*>(&d_B), reinterpret_cast<int*>(&d_C));
Err = hipGetLastError();
fError(Err);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float tiempo_reserva_host;
hipEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
hipEventDestroy(start);
hipEventDestroy(stop);
for(int i=0; i<N*M; i++){
printf("%d\n", d_C[i]);
printf("\n");
}
//Copiamos a CPU el vector C
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
} | .text
.file "main.hip"
.globl _Z24__device_stub__matrixAddPiS_S_ # -- Begin function _Z24__device_stub__matrixAddPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPiS_S_,@function
_Z24__device_stub__matrixAddPiS_S_: # @_Z24__device_stub__matrixAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPiS_S_, .Lfunc_end0-_Z24__device_stub__matrixAddPiS_S_
.cfi_endproc
# -- End function
.globl _Z6fError10hipError_t # -- Begin function _Z6fError10hipError_t
.p2align 4, 0x90
.type _Z6fError10hipError_t,@function
_Z6fError10hipError_t: # @_Z6fError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB1_1
# %bb.2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_1:
retq
.Lfunc_end1:
.size _Z6fError10hipError_t, .Lfunc_end1-_Z6fError10hipError_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $120144, %rsp # imm = 0x1D550
.cfi_def_cfa_offset 120176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 80144(%rsp), %rax
leaq 40144(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rsi,4)
movl %edx, (%rcx,%rsi,4)
incq %rsi
cmpq $100, %rsi
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rdx
addq $400, %rax # imm = 0x190
addq $400, %rcx # imm = 0x190
cmpq $100, %rdx
jne .LBB2_1
# %bb.4:
movq $0, 40(%rsp)
leaq 40(%rsp), %rbx
movl $40000, %esi # imm = 0x9C40
movq %rbx, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_6: # %_Z6fError10hipError_t.exit
movq 40(%rsp), %rdi
leaq 80144(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movq $0, 32(%rsp)
leaq 32(%rsp), %r14
movl $40000, %esi # imm = 0x9C40
movq %r14, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_8: # %_Z6fError10hipError_t.exit37
movq 32(%rsp), %rdi
leaq 40144(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movq $0, 16(%rsp)
leaq 16(%rsp), %r15
movl $40000, %esi # imm = 0x9C40
movq %r15, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_10: # %_Z6fError10hipError_t.exit39
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $171798691880, %rdi # imm = 0x2800000028
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq %rbx, 136(%rsp)
movq %r14, 128(%rsp)
movq %r15, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipGetLastError
testl %eax, %eax
je .LBB2_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_14: # %_Z6fError10hipError_t.exit41
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
jne .LBB2_15
# %bb.16:
movq 16(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120144, %rsp # imm = 0x1D550
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPiS_S_,@object # @_Z9matrixAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z9matrixAddPiS_S_
.p2align 3, 0x0
_Z9matrixAddPiS_S_:
.quad _Z24__device_stub__matrixAddPiS_S_
.size _Z9matrixAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Ha ocurrido un error con codigo: %s\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo de suma vectores DEVICE: %f\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\n"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPiS_S_
.globl _Z9matrixAddPiS_S_
.p2align 8
.type _Z9matrixAddPiS_S_,@function
_Z9matrixAddPiS_S_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPiS_S_, .Lfunc_end0-_Z9matrixAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c66c0_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Ha ocurrido un error con codigo: %s\n"
.text
.globl _Z6fError9cudaError
.type _Z6fError9cudaError, @function
_Z6fError9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6fError9cudaError, .-_Z6fError9cudaError
.globl _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.type _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, @function
_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L14
.L10:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L10
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_, .-_Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
.globl _Z9matrixAddPiS_S_
.type _Z9matrixAddPiS_S_, @function
_Z9matrixAddPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9matrixAddPiS_S_, .-_Z9matrixAddPiS_S_
.section .rodata.str1.8
.align 8
.LC1:
.string "Tiempo de suma vectores DEVICE: %f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d\n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -118784(%rsp), %r11
.cfi_def_cfa 11, 118816
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1312, %rsp
.cfi_def_cfa_offset 120128
movq %fs:40, %rax
movq %rax, 120088(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rsi
leaq 40080(%rsp), %rcx
movl $0, %edx
.L19:
movl $0, %eax
.L20:
movl $1, (%rsi,%rax)
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $400, %rax
jne .L20
addl $1, %edx
addq $400, %rsi
addq $400, %rcx
cmpl $100, %edx
jne .L19
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z6fError9cudaError
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z6fError9cudaError
leaq 40080(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z6fError9cudaError
leaq 80080(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl $1, 64(%rsp)
movl $40, 68(%rsp)
movl $40, 72(%rsp)
movl $1, 76(%rsp)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
call cudaGetLastError@PLT
movl %eax, %edi
call _Z6fError9cudaError
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
leaq .LC3(%rip), %rbp
.L23:
movq 32(%rsp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40000, %rbx
jne .L23
leaq 80080(%rsp), %rdi
movl $2, %ecx
movl $40000, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq 120088(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $120096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z32__device_stub__Z9matrixAddPiS_S_PiS_S_
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9matrixAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z24__device_stub__matrixAddPiS_S_ # -- Begin function _Z24__device_stub__matrixAddPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPiS_S_,@function
_Z24__device_stub__matrixAddPiS_S_: # @_Z24__device_stub__matrixAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPiS_S_, .Lfunc_end0-_Z24__device_stub__matrixAddPiS_S_
.cfi_endproc
# -- End function
.globl _Z6fError10hipError_t # -- Begin function _Z6fError10hipError_t
.p2align 4, 0x90
.type _Z6fError10hipError_t,@function
_Z6fError10hipError_t: # @_Z6fError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB1_1
# %bb.2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_1:
retq
.Lfunc_end1:
.size _Z6fError10hipError_t, .Lfunc_end1-_Z6fError10hipError_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $120144, %rsp # imm = 0x1D550
.cfi_def_cfa_offset 120176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 80144(%rsp), %rax
leaq 40144(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rsi,4)
movl %edx, (%rcx,%rsi,4)
incq %rsi
cmpq $100, %rsi
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rdx
addq $400, %rax # imm = 0x190
addq $400, %rcx # imm = 0x190
cmpq $100, %rdx
jne .LBB2_1
# %bb.4:
movq $0, 40(%rsp)
leaq 40(%rsp), %rbx
movl $40000, %esi # imm = 0x9C40
movq %rbx, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_6: # %_Z6fError10hipError_t.exit
movq 40(%rsp), %rdi
leaq 80144(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movq $0, 32(%rsp)
leaq 32(%rsp), %r14
movl $40000, %esi # imm = 0x9C40
movq %r14, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_8: # %_Z6fError10hipError_t.exit37
movq 32(%rsp), %rdi
leaq 40144(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
movq $0, 16(%rsp)
leaq 16(%rsp), %r15
movl $40000, %esi # imm = 0x9C40
movq %r15, %rdi
callq hipMalloc
testl %eax, %eax
je .LBB2_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_10: # %_Z6fError10hipError_t.exit39
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $171798691880, %rdi # imm = 0x2800000028
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq %rbx, 136(%rsp)
movq %r14, 128(%rsp)
movq %r15, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9matrixAddPiS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipGetLastError
testl %eax, %eax
je .LBB2_14
# %bb.13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_14: # %_Z6fError10hipError_t.exit41
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
jne .LBB2_15
# %bb.16:
movq 16(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120144, %rsp # imm = 0x1D550
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPiS_S_,@object # @_Z9matrixAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z9matrixAddPiS_S_
.p2align 3, 0x0
_Z9matrixAddPiS_S_:
.quad _Z24__device_stub__matrixAddPiS_S_
.size _Z9matrixAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Ha ocurrido un error con codigo: %s\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo de suma vectores DEVICE: %f\n"
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d\n"
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixAddPiS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void checkIndex() {
printf("threadIdx = ( %d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z);
printf("blockDim = ( %d, %d, %d)\n", blockDim.x, blockDim.y, blockDim.z);
printf("gridDim = ( %d, %d, %d)\n", gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nElem = 6;
dim3 block(3);
dim3 grid((nElem - block.x - 1)/block.x);
printf("block = ( %d, %d, %d)\n", block.x, block.y, block.z);
printf("grid = ( %d, %d, %d)\n", grid.x, grid.y, grid.z);
checkIndex <<<block, grid>>> ();
// check
printf("==== test ====\n");
checkIndex <<<2, 3>>> ();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10checkIndexv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_TID.Y ; /* 0x00000000000b7919 */
/* 0x000e220000002200 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R17, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001117a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R8, c[0x4][R2] ; /* 0x0100000002087b82 */
/* 0x0002a20000000a00 */
/*0090*/ S2R R0, SR_TID.Z ; /* 0x0000000000007919 */
/* 0x000ee40000002300 */
/*00a0*/ IMAD.X R16, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff107624 */
/* 0x000fc400000e06ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0011 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0010 */
/*00d0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0013e80000100a00 */
/*00e0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0083e40000100800 */
/*00f0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x006fe40000000000 */
/*0100*/ MOV R3, 0x170 ; /* 0x0000017000037802 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R20, 0xf0 ; /* 0x000000f000147802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0130*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0140*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0150*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0160*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0170*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0a7624 */
/* 0x000fe200078e00ff */
/*0180*/ LDC.64 R8, c[0x4][R2] ; /* 0x0100000002087b82 */
/* 0x0000620000000a00 */
/*0190*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0b7624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x8] ; /* 0x00000200ff007624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*01c0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0011 */
/*01f0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0001e20000100800 */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0010 */
/*0210*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x001fc80000000000 */
/*0220*/ MOV R3, 0x290 ; /* 0x0000029000037802 */
/* 0x000fe40000000f00 */
/*0230*/ MOV R20, 0x210 ; /* 0x0000021000147802 */
/* 0x000fc40000000f00 */
/*0240*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0250*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0260*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0270*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0280*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0xc] ; /* 0x00000300ff087624 */
/* 0x000fe200078e00ff */
/*02a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e220000000a00 */
/*02b0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x10] ; /* 0x00000400ff097624 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x14] ; /* 0x00000500ff007624 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, R17 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0011 */
/*02e0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0003e20000100a00 */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, R16 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0010 */
/*0300*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe200078e00ff */
/*0310*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0003e20000100800 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fc600078e00ff */
/*0330*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc80000000000 */
/*0340*/ MOV R11, 0x3b0 ; /* 0x000003b0000b7802 */
/* 0x000fe40000000f00 */
/*0350*/ MOV R20, 0x330 ; /* 0x0000033000147802 */
/* 0x000fc40000000f00 */
/*0360*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0370*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0380*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0390*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*03a0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ BRA 0x3c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void checkIndex() {
printf("threadIdx = ( %d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z);
printf("blockDim = ( %d, %d, %d)\n", blockDim.x, blockDim.y, blockDim.z);
printf("gridDim = ( %d, %d, %d)\n", gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nElem = 6;
dim3 block(3);
dim3 grid((nElem - block.x - 1)/block.x);
printf("block = ( %d, %d, %d)\n", block.x, block.y, block.z);
printf("grid = ( %d, %d, %d)\n", grid.x, grid.y, grid.z);
checkIndex <<<block, grid>>> ();
// check
printf("==== test ====\n");
checkIndex <<<2, 3>>> ();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00118cd6_00000000-6_checkDimention.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "block = ( %d, %d, %d)\n"
.LC1:
.string "grid = ( %d, %d, %d)\n"
.LC2:
.string "==== test ====\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $1, %r8d
movl $1, %ecx
movl $3, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, (%rsp)
movl $1, 4(%rsp)
movl $0, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 36(%rsp)
movl $1, 40(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
call _Z29__device_stub__Z10checkIndexvv
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void checkIndex() {
printf("threadIdx = ( %d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z);
printf("blockDim = ( %d, %d, %d)\n", blockDim.x, blockDim.y, blockDim.z);
printf("gridDim = ( %d, %d, %d)\n", gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nElem = 6;
dim3 block(3);
dim3 grid((nElem - block.x - 1)/block.x);
printf("block = ( %d, %d, %d)\n", block.x, block.y, block.z);
printf("grid = ( %d, %d, %d)\n", grid.x, grid.y, grid.z);
checkIndex <<<block, grid>>> ();
// check
printf("==== test ====\n");
checkIndex <<<2, 3>>> ();
cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void checkIndex() {
printf("threadIdx = ( %d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z);
printf("blockDim = ( %d, %d, %d)\n", blockDim.x, blockDim.y, blockDim.z);
printf("gridDim = ( %d, %d, %d)\n", gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nElem = 6;
dim3 block(3);
dim3 grid((nElem - block.x - 1)/block.x);
printf("block = ( %d, %d, %d)\n", block.x, block.y, block.z);
printf("grid = ( %d, %d, %d)\n", grid.x, grid.y, grid.z);
checkIndex <<<block, grid>>> ();
// check
printf("==== test ====\n");
checkIndex <<<2, 3>>> ();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void checkIndex() {
printf("threadIdx = ( %d, %d, %d)\n", threadIdx.x, threadIdx.y, threadIdx.z);
printf("blockDim = ( %d, %d, %d)\n", blockDim.x, blockDim.y, blockDim.z);
printf("gridDim = ( %d, %d, %d)\n", gridDim.x, gridDim.y, gridDim.z);
}
int main() {
int nElem = 6;
dim3 block(3);
dim3 grid((nElem - block.x - 1)/block.x);
printf("block = ( %d, %d, %d)\n", block.x, block.y, block.z);
printf("grid = ( %d, %d, %d)\n", grid.x, grid.y, grid.z);
checkIndex <<<block, grid>>> ();
// check
printf("==== test ====\n");
checkIndex <<<2, 3>>> ();
hipDeviceSynchronize();
return 0;
} | .text
.file "checkDimention.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967299, %rbx # imm = 0x100000003
movl $.L.str, %edi
movl $3, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %esi, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
leaq -3(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
leaq -1(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "block = ( %d, %d, %d)\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "grid = ( %d, %d, %d)\n"
.size .L.str.1, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "==== test ===="
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00118cd6_00000000-6_checkDimention.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10checkIndexvv
.type _Z29__device_stub__Z10checkIndexvv, @function
_Z29__device_stub__Z10checkIndexvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10checkIndexv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10checkIndexvv, .-_Z29__device_stub__Z10checkIndexvv
.globl _Z10checkIndexv
.type _Z10checkIndexv, @function
_Z10checkIndexv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10checkIndexvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10checkIndexv, .-_Z10checkIndexv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "block = ( %d, %d, %d)\n"
.LC1:
.string "grid = ( %d, %d, %d)\n"
.LC2:
.string "==== test ====\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $1, %r8d
movl $1, %ecx
movl $3, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r8d
movl $1, %ecx
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, (%rsp)
movl $1, 4(%rsp)
movl $0, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 36(%rsp)
movl $1, 40(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
call _Z29__device_stub__Z10checkIndexvv
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call _Z29__device_stub__Z10checkIndexvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z10checkIndexv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10checkIndexv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "checkDimention.hip"
.globl _Z25__device_stub__checkIndexv # -- Begin function _Z25__device_stub__checkIndexv
.p2align 4, 0x90
.type _Z25__device_stub__checkIndexv,@function
_Z25__device_stub__checkIndexv: # @_Z25__device_stub__checkIndexv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__checkIndexv, .Lfunc_end0-_Z25__device_stub__checkIndexv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movabsq $4294967299, %rbx # imm = 0x100000003
movl $.L.str, %edi
movl $3, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %esi, %esi
movl $1, %edx
movl $1, %ecx
xorl %eax, %eax
callq printf
leaq -3(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
leaq -1(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10checkIndexv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10checkIndexv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10checkIndexv,@object # @_Z10checkIndexv
.section .rodata,"a",@progbits
.globl _Z10checkIndexv
.p2align 3, 0x0
_Z10checkIndexv:
.quad _Z25__device_stub__checkIndexv
.size _Z10checkIndexv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "block = ( %d, %d, %d)\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "grid = ( %d, %d, %d)\n"
.size .L.str.1, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10checkIndexv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "==== test ===="
.size .Lstr, 15
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__checkIndexv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10checkIndexv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <sys/time.h>
#include <thrust/transform_reduce.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
#include <thrust/scan.h>
#define FUN(x) exp(sin(x))*cos(x/40)
#include <thrust/iterator/zip_iterator.h>
void read(int argc,char* arcgv[], int *npartitions){
if( argc == 2){
*npartitions=atoi(arcgv[1]);
}else{
printf("Argument donnot enough!");
}
}
__host__ __device__ int getCoefficient(int num,int npartitions){
int coeff[]={17,59,43,49,48};
if(num<4)
{
return coeff[num];
}else if(num>npartitions-4){
return coeff[npartitions-num];
}else
{return 48;}
}
struct simp
{
simp(double t){h =(double) (100/t);}
double h;
__host__ __device__
double operator()(thrust::tuple<int,int> t){
int coe,index;
thrust::tie(index,coe)=t;
return coe*FUN((double)(index*h));
}
};
int main(int argc,char *argcv[]){
struct timeval start1,end1;
int npartitions;
double cpu_time;
read(argc,argcv,&npartitions);
simp calc(npartitions);
thrust::plus<double> binary_op;
double init = 0;
gettimeofday(&start1,NULL);
thrust::device_vector<int> coe(npartitions,48);
coe[0]=17;coe[npartitions-1]=17;
coe[1]=59;coe[npartitions-2]=59;
coe[2]=43;coe[npartitions-3]=43;
coe[4]=49;coe[npartitions-4]=49;
thrust::device_vector<int> index(npartitions,1);
index[0]=0;
thrust::inclusive_scan(index.begin(),index.end(),index.begin());
double rest=thrust::transform_reduce(
thrust::make_zip_iterator(thrust::make_tuple(index.begin(), coe.begin())),
thrust::make_zip_iterator(thrust::make_tuple(index.end(), coe.end())),
simp(npartitions),init,binary_op);
rest = rest*100/npartitions/48;
gettimeofday(&end1,NULL);
cpu_time = ((double)(end1.tv_usec-start1.tv_usec))/1000000;
std::cout.precision(15);
std::cout<<rest-32.121040666358<<'\t'<<rest<<std::endl;
std::cout.precision(6);
std::cout<<cpu_time<<std::endl;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <sys/time.h>
#include <thrust/transform_reduce.h>
#include <stdlib.h>
#include <iostream>
#include <math.h>
#include <thrust/scan.h>
#define FUN(x) exp(sin(x))*cos(x/40)
#include <thrust/iterator/zip_iterator.h>
void read(int argc,char* arcgv[], int *npartitions){
if( argc == 2){
*npartitions=atoi(arcgv[1]);
}else{
printf("Argument donnot enough!");
}
}
__host__ __device__ int getCoefficient(int num,int npartitions){
int coeff[]={17,59,43,49,48};
if(num<4)
{
return coeff[num];
}else if(num>npartitions-4){
return coeff[npartitions-num];
}else
{return 48;}
}
struct simp
{
simp(double t){h =(double) (100/t);}
double h;
__host__ __device__
double operator()(thrust::tuple<int,int> t){
int coe,index;
thrust::tie(index,coe)=t;
return coe*FUN((double)(index*h));
}
};
int main(int argc,char *argcv[]){
struct timeval start1,end1;
int npartitions;
double cpu_time;
read(argc,argcv,&npartitions);
simp calc(npartitions);
thrust::plus<double> binary_op;
double init = 0;
gettimeofday(&start1,NULL);
thrust::device_vector<int> coe(npartitions,48);
coe[0]=17;coe[npartitions-1]=17;
coe[1]=59;coe[npartitions-2]=59;
coe[2]=43;coe[npartitions-3]=43;
coe[4]=49;coe[npartitions-4]=49;
thrust::device_vector<int> index(npartitions,1);
index[0]=0;
thrust::inclusive_scan(index.begin(),index.end(),index.begin());
double rest=thrust::transform_reduce(
thrust::make_zip_iterator(thrust::make_tuple(index.begin(), coe.begin())),
thrust::make_zip_iterator(thrust::make_tuple(index.end(), coe.end())),
simp(npartitions),init,binary_op);
rest = rest*100/npartitions/48;
gettimeofday(&end1,NULL);
cpu_time = ((double)(end1.tv_usec-start1.tv_usec))/1000000;
std::cout.precision(15);
std::cout<<rest-32.121040666358<<'\t'<<rest<<std::endl;
std::cout.precision(6);
std::cout<<cpu_time<<std::endl;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void fp_bias_fc(float *preact, float *bias, const int n_channel)
{
const int pos = blockIdx.x * blockDim.x + threadIdx.x;
const int totalPos = blockDim.x * gridDim.x;
const int N = n_channel;
for (int idx = N * pos / totalPos; idx < N * (pos+1) / totalPos; ++idx) {
preact[idx] += bias[idx];
}
} | code for sm_80
Function : _Z10fp_bias_fcPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e260000002500 */
/*0030*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ IABS R9, R0.reuse ; /* 0x0000000000097213 */
/* 0x080fe40000000000 */
/*0060*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc40000000000 */
/*0070*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e700000209400 */
/*0080*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R5, R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a24 */
/* 0x000fca00078e02ff */
/*00b0*/ IADD3 R7, R5, c[0x0][0x170], RZ ; /* 0x00005c0005077a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ IABS R13, R7 ; /* 0x00000007000d7213 */
/* 0x000fe40000000000 */
/*00d0*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x002fe40007ffe0ff */
/*00e0*/ LOP3.LUT R7, R7, R0, RZ, 0x3c, !PT ; /* 0x0000000007077212 */
/* 0x000fc800078e3cff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0100*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f26270 */
/*0110*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x001fca0007ffe0ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0130*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fe40000000000 */
/*0140*/ LOP3.LUT R5, R5, R0, RZ, 0x3c, !PT ; /* 0x0000000005057212 */
/* 0x000fe200078e3cff */
/*0150*/ IMAD R11, R2, R9, RZ ; /* 0x00000009020b7224 */
/* 0x000fe400078e02ff */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f06270 */
/*0180*/ IMAD.HI.U32 R2, R3, R11, R2 ; /* 0x0000000b03027227 */
/* 0x000fe200078e0002 */
/*0190*/ IADD3 R11, RZ, -R8, RZ ; /* 0x80000008ff0b7210 */
/* 0x000fca0007ffe0ff */
/*01a0*/ IMAD.HI.U32 R3, R2, R6, RZ ; /* 0x0000000602037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.HI.U32 R4, R2, R13, RZ ; /* 0x0000000d02047227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD R2, R3, R11.reuse, R6 ; /* 0x0000000b03027224 */
/* 0x080fe400078e0206 */
/*01d0*/ IMAD R6, R4, R11, R13 ; /* 0x0000000b04067224 */
/* 0x000fc600078e020d */
/*01e0*/ ISETP.GT.U32.AND P4, PT, R9.reuse, R2, PT ; /* 0x000000020900720c */
/* 0x040fe40003f84070 */
/*01f0*/ ISETP.GT.U32.AND P5, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fd60003fa4070 */
/*0200*/ @!P4 IMAD.IADD R2, R2, 0x1, -R9.reuse ; /* 0x000000010202c824 */
/* 0x100fe200078e0a09 */
/*0210*/ @!P4 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303c810 */
/* 0x000fe20007ffe0ff */
/*0220*/ @!P5 IMAD.IADD R6, R6, 0x1, -R9 ; /* 0x000000010606d824 */
/* 0x000fe200078e0a09 */
/*0230*/ @!P5 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404d810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P2, PT, R2, R9.reuse, PT ; /* 0x000000090200720c */
/* 0x080fe40003f46070 */
/*0250*/ ISETP.GE.U32.AND P3, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fd60003f66070 */
/*0260*/ @P2 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103032810 */
/* 0x000fe40007ffe0ff */
/*0270*/ @P3 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104043810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*0290*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fe200078e33ff */
/*02a0*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*02b0*/ @!P0 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03038210 */
/* 0x000fc80007ffe1ff */
/*02c0*/ SEL R7, R0.reuse, R3, !P2 ; /* 0x0000000300077207 */
/* 0x040fe40005000000 */
/*02d0*/ SEL R0, R0, R4, !P2 ; /* 0x0000000400007207 */
/* 0x000fc80005000000 */
/*02e0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f04270 */
/*02f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0300*/ IMAD.IADD R2, R0, 0x1, -R7 ; /* 0x0000000100027824 */
/* 0x000fe200078e0a07 */
/*0310*/ LOP3.LUT R3, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff037212 */
/* 0x000fe200078e33ff */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0330*/ BSSY B0, 0x4e0 ; /* 0x000001a000007945 */
/* 0x000fe40003800000 */
/*0340*/ LOP3.LUT P0, R6, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302067812 */
/* 0x000fe4000780c0ff */
/*0350*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fce0003f26070 */
/*0370*/ @!P0 BRA 0x4d0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0380*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.WIDE R2, R7, R4, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0204 */
/*03a0*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fe200078e0204 */
/*03b0*/ MOV R13, R3 ; /* 0x00000003000d7202 */
/* 0x000fc60000000f00 */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*03d0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0005 */
/*03e0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*03f0*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x001fe20000000f00 */
/*0400*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0008 */
/*0410*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a8000c1e1900 */
/*0420*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0440*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0460*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fca0007f7e0ff */
/*0470*/ IMAD.X R11, RZ, RZ, R11, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400018e060b */
/*0480*/ FADD R9, R8, R5 ; /* 0x0000000508097221 */
/* 0x004fe20000000000 */
/*0490*/ IADD3 R8, P2, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fc80007f5e0ff */
/*04a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*04b0*/ IADD3.X R13, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fe200017fe4ff */
/*04c0*/ @P0 BRA 0x3e0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*04f0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0500*/ IMAD.IADD R3, R0, 0x1, -R7 ; /* 0x0000000100037824 */
/* 0x001fe200078e0a07 */
/*0510*/ BSSY B0, 0xa80 ; /* 0x0000056000007945 */
/* 0x000fe80003800000 */
/*0520*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fc80003f24270 */
/*0530*/ IMAD.WIDE R4, R7, R4, c[0x2][0x0] ; /* 0x0080000007047625 */
/* 0x000fca00078e0204 */
/*0540*/ IADD3 R2, P0, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x040fe40007f1e0ff */
/*0550*/ IADD3 R4, P2, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe40007f5e0ff */
/*0560*/ IADD3.X R3, R5.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005037a10 */
/* 0x040fe400007fe4ff */
/*0570*/ IADD3.X R5, R5, c[0x0][0x164], RZ, P2, !PT ; /* 0x0000590005057a10 */
/* 0x000fe400017fe4ff */
/*0580*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0590*/ @!P1 BRA 0xa70 ; /* 0x000004d000009947 */
/* 0x000fee0003800000 */
/*05a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05b0*/ IADD3 R6, R0, -0xc, RZ ; /* 0xfffffff400067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ LDG.E R8, [R4.64+-0x8] ; /* 0xfffff80404087981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*05f0*/ LDG.E R8, [R4.64+-0x4] ; /* 0xfffffc0404087981 */
/* 0x000ea8000c1e1900 */
/*0600*/ STG.E [R4.64+-0x8], R9 ; /* 0xfffff80904007986 */
/* 0x0001e8000c101904 */
/*0610*/ LDG.E R11, [R2.64+-0x4] ; /* 0xfffffc04020b7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0630*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0640*/ STG.E [R4.64+-0x4], R11 ; /* 0xfffffc0b04007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0660*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0670*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea8000c1e1900 */
/*0680*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0007e8000c101904 */
/*0690*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fc40000000000 */
/*06b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0009e8000c101904 */
/*06d0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x001ea4000c1e1900 */
/*06e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*06f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000ea8000c1e1900 */
/*0700*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0720*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0730*/ LDG.E R8, [R4.64+0x10] ; /* 0x0000100404087981 */
/* 0x000ea8000c1e1900 */
/*0740*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0003e8000c101904 */
/*0750*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001004020d7981 */
/* 0x008ea4000c1e1900 */
/*0760*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0770*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140404087981 */
/* 0x000ea8000c1e1900 */
/*0780*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x0007e8000c101904 */
/*0790*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x010ea4000c1e1900 */
/*07a0*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fc40000000000 */
/*07b0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180404087981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ STG.E [R4.64+0x14], R15 ; /* 0x0000140f04007986 */
/* 0x0009e8000c101904 */
/*07d0*/ LDG.E R9, [R2.64+0x18] ; /* 0x0000180402097981 */
/* 0x001ea4000c1e1900 */
/*07e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*07f0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0404087981 */
/* 0x000ea8000c1e1900 */
/*0800*/ STG.E [R4.64+0x18], R9 ; /* 0x0000180904007986 */
/* 0x0001e8000c101904 */
/*0810*/ LDG.E R11, [R2.64+0x1c] ; /* 0x00001c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0820*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0830*/ LDG.E R8, [R4.64+0x20] ; /* 0x0000200404087981 */
/* 0x000ea8000c1e1900 */
/*0840*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0003e8000c101904 */
/*0850*/ LDG.E R13, [R2.64+0x20] ; /* 0x00002004020d7981 */
/* 0x008ea4000c1e1900 */
/*0860*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0870*/ LDG.E R8, [R4.64+0x24] ; /* 0x0000240404087981 */
/* 0x000ea8000c1e1900 */
/*0880*/ STG.E [R4.64+0x20], R13 ; /* 0x0000200d04007986 */
/* 0x0007e8000c101904 */
/*0890*/ LDG.E R15, [R2.64+0x24] ; /* 0x00002404020f7981 */
/* 0x010ea4000c1e1900 */
/*08a0*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fc40000000000 */
/*08b0*/ LDG.E R8, [R4.64+0x28] ; /* 0x0000280404087981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ STG.E [R4.64+0x24], R15 ; /* 0x0000240f04007986 */
/* 0x0009e8000c101904 */
/*08d0*/ LDG.E R9, [R2.64+0x28] ; /* 0x0000280402097981 */
/* 0x001ea4000c1e1900 */
/*08e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*08f0*/ LDG.E R8, [R4.64+0x2c] ; /* 0x00002c0404087981 */
/* 0x000ea8000c1e1900 */
/*0900*/ STG.E [R4.64+0x28], R9 ; /* 0x0000280904007986 */
/* 0x000fe8000c101904 */
/*0910*/ LDG.E R11, [R2.64+0x2c] ; /* 0x00002c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0920*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0930*/ LDG.E R8, [R4.64+0x30] ; /* 0x0000300404087981 */
/* 0x000ea8000c1e1900 */
/*0940*/ STG.E [R4.64+0x2c], R11 ; /* 0x00002c0b04007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R13, [R2.64+0x30] ; /* 0x00003004020d7981 */
/* 0x008ea2000c1e1900 */
/*0960*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe20007ffe0ff */
/*0970*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0980*/ LDG.E R8, [R4.64+0x34] ; /* 0x0000340404087981 */
/* 0x000ea8000c1e1900 */
/*0990*/ STG.E [R4.64+0x30], R13 ; /* 0x0000300d04007986 */
/* 0x000fe8000c101904 */
/*09a0*/ LDG.E R15, [R2.64+0x34] ; /* 0x00003404020f7981 */
/* 0x0102a2000c1e1900 */
/*09b0*/ ISETP.GE.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe40003f26270 */
/*09c0*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*09d0*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe400017fe4ff */
/*09e0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x002fc60000000f00 */
/*09f0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0a00*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fe20000000000 */
/*0a10*/ IADD3 R8, P3, R4, 0x40, RZ ; /* 0x0000004004087810 */
/* 0x000fc80007f7e0ff */
/*0a20*/ STG.E [R4.64+0x34], R15 ; /* 0x0000340f04007986 */
/* 0x0001e2000c101904 */
/*0a30*/ IMAD.X R9, RZ, RZ, R5, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0605 */
/*0a40*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fc60000000f00 */
/*0a50*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0a60*/ @!P1 BRA 0x5c0 ; /* 0xfffffb5000009947 */
/* 0x000fea000383ffff */
/*0a70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a80*/ IADD3 R6, R0, -R7, RZ ; /* 0x8000000700067210 */
/* 0x000fe20007ffe0ff */
/*0a90*/ BSSY B0, 0xd70 ; /* 0x000002d000007945 */
/* 0x000fe60003800000 */
/*0aa0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0ab0*/ @!P1 BRA 0xd60 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R6, [R4.64+-0x8] ; /* 0xfffff80404067981 */
/* 0x000ea8000c1e1900 */
/*0ad0*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea4000c1e1900 */
/*0ae0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fe40000000000 */
/*0af0*/ LDG.E R6, [R4.64+-0x4] ; /* 0xfffffc0404067981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ STG.E [R4.64+-0x8], R9 ; /* 0xfffff80904007986 */
/* 0x0001e8000c101904 */
/*0b10*/ LDG.E R11, [R2.64+-0x4] ; /* 0xfffffc04020b7981 */
/* 0x000ea4000c1e1900 */
/*0b20*/ FADD R11, R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fc40000000000 */
/*0b30*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ STG.E [R4.64+-0x4], R11 ; /* 0xfffffc0b04007986 */
/* 0x0003e8000c101904 */
/*0b50*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0b60*/ FADD R13, R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fc40000000000 */
/*0b70*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0007e8000c101904 */
/*0b90*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ea4000c1e1900 */
/*0ba0*/ FADD R15, R6, R15 ; /* 0x0000000f060f7221 */
/* 0x004fc40000000000 */
/*0bb0*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0009e8000c101904 */
/*0bd0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x001ea4000c1e1900 */
/*0be0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fc40000000000 */
/*0bf0*/ LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404067981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x000fe8000c101904 */
/*0c10*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0c20*/ FADD R11, R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fc40000000000 */
/*0c30*/ LDG.E R6, [R4.64+0x10] ; /* 0x0000100404067981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0001e8000c101904 */
/*0c50*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001004020d7981 */
/* 0x008ea4000c1e1900 */
/*0c60*/ FADD R13, R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fc40000000000 */
/*0c70*/ LDG.E R6, [R4.64+0x14] ; /* 0x0000140404067981 */
/* 0x000ea8000c1e1900 */
/*0c80*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x000fe8000c101904 */
/*0c90*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x0102a2000c1e1900 */
/*0ca0*/ IADD3 R8, P1, R2, 0x20, RZ ; /* 0x0000002002087810 */
/* 0x000fe40007f3e0ff */
/*0cb0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0cc0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ IMAD.X R11, RZ, RZ, R3, P1 ; /* 0x000000ffff0b7224 */
/* 0x001fe400008e0603 */
/*0ce0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x002fc600078e0008 */
/*0cf0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*0d00*/ FADD R15, R6, R15 ; /* 0x0000000f060f7221 */
/* 0x004fe20000000000 */
/*0d10*/ IADD3 R6, P2, R4, 0x20, RZ ; /* 0x0000002004067810 */
/* 0x000fc80007f5e0ff */
/*0d20*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fe200017fe4ff */
/*0d30*/ STG.E [R4.64+0x14], R15 ; /* 0x0000140f04007986 */
/* 0x0001e4000c101904 */
/*0d40*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0006 */
/*0d50*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*0d60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.LT.OR P0, PT, R7, R0, P0 ; /* 0x000000000700720c */
/* 0x000fda0000701670 */
/*0d80*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d90*/ LDG.E R0, [R4.64+-0x8] ; /* 0xfffff80404007981 */
/* 0x000ea8000c1e1900 */
/*0da0*/ LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80402077981 */
/* 0x000ea4000c1e1900 */
/*0db0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fe40000000000 */
/*0dc0*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ea8000c1e1900 */
/*0dd0*/ STG.E [R4.64+-0x8], R7 ; /* 0xfffff80704007986 */
/* 0x000fe8000c101904 */
/*0de0*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ea4000c1e1900 */
/*0df0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fc40000000000 */
/*0e00*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0e10*/ STG.E [R4.64+-0x4], R9 ; /* 0xfffffc0904007986 */
/* 0x000fe8000c101904 */
/*0e20*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0e30*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fc40000000000 */
/*0e40*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea8000c1e1900 */
/*0e50*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0e60*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea4000c1e1900 */
/*0e70*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x004fca0000000000 */
/*0e80*/ STG.E [R4.64+0x4], R13 ; /* 0x0000040d04007986 */
/* 0x000fe2000c101904 */
/*0e90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ea0*/ BRA 0xea0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fp_bias_fc(float *preact, float *bias, const int n_channel)
{
const int pos = blockIdx.x * blockDim.x + threadIdx.x;
const int totalPos = blockDim.x * gridDim.x;
const int N = n_channel;
for (int idx = N * pos / totalPos; idx < N * (pos+1) / totalPos; ++idx) {
preact[idx] += bias[idx];
}
} | .file "tmpxft_0010caba_00000000-6_fp_bias_fc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i
.type _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i, @function
_Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10fp_bias_fcPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i, .-_Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i
.globl _Z10fp_bias_fcPfS_i
.type _Z10fp_bias_fcPfS_i, @function
_Z10fp_bias_fcPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10fp_bias_fcPfS_i, .-_Z10fp_bias_fcPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10fp_bias_fcPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10fp_bias_fcPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fp_bias_fc(float *preact, float *bias, const int n_channel)
{
const int pos = blockIdx.x * blockDim.x + threadIdx.x;
const int totalPos = blockDim.x * gridDim.x;
const int N = n_channel;
for (int idx = N * pos / totalPos; idx < N * (pos+1) / totalPos; ++idx) {
preact[idx] += bias[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fp_bias_fc(float *preact, float *bias, const int n_channel)
{
const int pos = blockIdx.x * blockDim.x + threadIdx.x;
const int totalPos = blockDim.x * gridDim.x;
const int N = n_channel;
for (int idx = N * pos / totalPos; idx < N * (pos+1) / totalPos; ++idx) {
preact[idx] += bias[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fp_bias_fc(float *preact, float *bias, const int n_channel)
{
const int pos = blockIdx.x * blockDim.x + threadIdx.x;
const int totalPos = blockDim.x * gridDim.x;
const int N = n_channel;
for (int idx = N * pos / totalPos; idx < N * (pos+1) / totalPos; ++idx) {
preact[idx] += bias[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10fp_bias_fcPfS_i
.globl _Z10fp_bias_fcPfS_i
.p2align 8
.type _Z10fp_bias_fcPfS_i,@function
_Z10fp_bias_fcPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
s_xor_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v3, s5, v1
v_cvt_u32_f32_e32 v0, v0
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v3
v_mul_lo_u32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
v_xor_b32_e32 v4, s4, v4
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
v_xor_b32_e32 v2, v3, v5
v_xor_b32_e32 v5, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v3, v1, v0
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v3, s3
v_mul_lo_u32 v7, v0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v1, v1, v6
v_add_nc_u32_e32 v6, 1, v3
v_sub_nc_u32_e32 v2, v2, v7
v_add_nc_u32_e32 v7, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_subrev_nc_u32_e32 v8, s3, v2
v_cmp_le_u32_e64 s2, s3, v2
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, v7, s2
v_cndmask_b32_e64 v2, v2, v8, s2
s_mov_b32 s2, 0
v_dual_cndmask_b32 v1, v1, v6 :: v_dual_add_nc_u32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, v3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_mov_b32 s3, exec_lo
v_xor_b32_e32 v1, v1, v4
v_cndmask_b32_e32 v0, v0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v0, v5
v_sub_nc_u32_e32 v0, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v2, v5
v_cmpx_lt_i32_e64 v0, v5
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v6, v[1:2], off
global_load_b32 v7, v[3:4], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v0, v5
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[3:4], v6, off
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10fp_bias_fcPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10fp_bias_fcPfS_i, .Lfunc_end0-_Z10fp_bias_fcPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10fp_bias_fcPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10fp_bias_fcPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fp_bias_fc(float *preact, float *bias, const int n_channel)
{
const int pos = blockIdx.x * blockDim.x + threadIdx.x;
const int totalPos = blockDim.x * gridDim.x;
const int N = n_channel;
for (int idx = N * pos / totalPos; idx < N * (pos+1) / totalPos; ++idx) {
preact[idx] += bias[idx];
}
} | .text
.file "fp_bias_fc.hip"
.globl _Z25__device_stub__fp_bias_fcPfS_i # -- Begin function _Z25__device_stub__fp_bias_fcPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__fp_bias_fcPfS_i,@function
_Z25__device_stub__fp_bias_fcPfS_i: # @_Z25__device_stub__fp_bias_fcPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10fp_bias_fcPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__fp_bias_fcPfS_i, .Lfunc_end0-_Z25__device_stub__fp_bias_fcPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10fp_bias_fcPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10fp_bias_fcPfS_i,@object # @_Z10fp_bias_fcPfS_i
.section .rodata,"a",@progbits
.globl _Z10fp_bias_fcPfS_i
.p2align 3, 0x0
_Z10fp_bias_fcPfS_i:
.quad _Z25__device_stub__fp_bias_fcPfS_i
.size _Z10fp_bias_fcPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10fp_bias_fcPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__fp_bias_fcPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10fp_bias_fcPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10fp_bias_fcPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e260000002500 */
/*0030*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ IABS R9, R0.reuse ; /* 0x0000000000097213 */
/* 0x080fe40000000000 */
/*0060*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc40000000000 */
/*0070*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e700000209400 */
/*0080*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0090*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R5, R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a24 */
/* 0x000fca00078e02ff */
/*00b0*/ IADD3 R7, R5, c[0x0][0x170], RZ ; /* 0x00005c0005077a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ IABS R13, R7 ; /* 0x00000007000d7213 */
/* 0x000fe40000000000 */
/*00d0*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x002fe40007ffe0ff */
/*00e0*/ LOP3.LUT R7, R7, R0, RZ, 0x3c, !PT ; /* 0x0000000007077212 */
/* 0x000fc800078e3cff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0100*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f26270 */
/*0110*/ IADD3 R6, RZ, -R3, RZ ; /* 0x80000003ff067210 */
/* 0x001fca0007ffe0ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0130*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fe40000000000 */
/*0140*/ LOP3.LUT R5, R5, R0, RZ, 0x3c, !PT ; /* 0x0000000005057212 */
/* 0x000fe200078e3cff */
/*0150*/ IMAD R11, R2, R9, RZ ; /* 0x00000009020b7224 */
/* 0x000fe400078e02ff */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f06270 */
/*0180*/ IMAD.HI.U32 R2, R3, R11, R2 ; /* 0x0000000b03027227 */
/* 0x000fe200078e0002 */
/*0190*/ IADD3 R11, RZ, -R8, RZ ; /* 0x80000008ff0b7210 */
/* 0x000fca0007ffe0ff */
/*01a0*/ IMAD.HI.U32 R3, R2, R6, RZ ; /* 0x0000000602037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.HI.U32 R4, R2, R13, RZ ; /* 0x0000000d02047227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD R2, R3, R11.reuse, R6 ; /* 0x0000000b03027224 */
/* 0x080fe400078e0206 */
/*01d0*/ IMAD R6, R4, R11, R13 ; /* 0x0000000b04067224 */
/* 0x000fc600078e020d */
/*01e0*/ ISETP.GT.U32.AND P4, PT, R9.reuse, R2, PT ; /* 0x000000020900720c */
/* 0x040fe40003f84070 */
/*01f0*/ ISETP.GT.U32.AND P5, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fd60003fa4070 */
/*0200*/ @!P4 IMAD.IADD R2, R2, 0x1, -R9.reuse ; /* 0x000000010202c824 */
/* 0x100fe200078e0a09 */
/*0210*/ @!P4 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303c810 */
/* 0x000fe20007ffe0ff */
/*0220*/ @!P5 IMAD.IADD R6, R6, 0x1, -R9 ; /* 0x000000010606d824 */
/* 0x000fe200078e0a09 */
/*0230*/ @!P5 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404d810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P2, PT, R2, R9.reuse, PT ; /* 0x000000090200720c */
/* 0x080fe40003f46070 */
/*0250*/ ISETP.GE.U32.AND P3, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fd60003f66070 */
/*0260*/ @P2 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103032810 */
/* 0x000fe40007ffe0ff */
/*0270*/ @P3 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104043810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*0290*/ LOP3.LUT R0, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff007212 */
/* 0x000fe200078e33ff */
/*02a0*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fe200078e0a04 */
/*02b0*/ @!P0 IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03038210 */
/* 0x000fc80007ffe1ff */
/*02c0*/ SEL R7, R0.reuse, R3, !P2 ; /* 0x0000000300077207 */
/* 0x040fe40005000000 */
/*02d0*/ SEL R0, R0, R4, !P2 ; /* 0x0000000400007207 */
/* 0x000fc80005000000 */
/*02e0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f04270 */
/*02f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0300*/ IMAD.IADD R2, R0, 0x1, -R7 ; /* 0x0000000100027824 */
/* 0x000fe200078e0a07 */
/*0310*/ LOP3.LUT R3, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff037212 */
/* 0x000fe200078e33ff */
/*0320*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0330*/ BSSY B0, 0x4e0 ; /* 0x000001a000007945 */
/* 0x000fe40003800000 */
/*0340*/ LOP3.LUT P0, R6, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302067812 */
/* 0x000fe4000780c0ff */
/*0350*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fce0003f26070 */
/*0370*/ @!P0 BRA 0x4d0 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0380*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0390*/ IMAD.WIDE R2, R7, R4, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0204 */
/*03a0*/ IMAD.WIDE R4, R7, R4, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fe200078e0204 */
/*03b0*/ MOV R13, R3 ; /* 0x00000003000d7202 */
/* 0x000fc60000000f00 */
/*03c0*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0002 */
/*03d0*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0005 */
/*03e0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*03f0*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x001fe20000000f00 */
/*0400*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0008 */
/*0410*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a8000c1e1900 */
/*0420*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0440*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0460*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fca0007f7e0ff */
/*0470*/ IMAD.X R11, RZ, RZ, R11, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400018e060b */
/*0480*/ FADD R9, R8, R5 ; /* 0x0000000508097221 */
/* 0x004fe20000000000 */
/*0490*/ IADD3 R8, P2, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fc80007f5e0ff */
/*04a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e2000c101904 */
/*04b0*/ IADD3.X R13, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fe200017fe4ff */
/*04c0*/ @P0 BRA 0x3e0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*04f0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0500*/ IMAD.IADD R3, R0, 0x1, -R7 ; /* 0x0000000100037824 */
/* 0x001fe200078e0a07 */
/*0510*/ BSSY B0, 0xa80 ; /* 0x0000056000007945 */
/* 0x000fe80003800000 */
/*0520*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fc80003f24270 */
/*0530*/ IMAD.WIDE R4, R7, R4, c[0x2][0x0] ; /* 0x0080000007047625 */
/* 0x000fca00078e0204 */
/*0540*/ IADD3 R2, P0, R4.reuse, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x040fe40007f1e0ff */
/*0550*/ IADD3 R4, P2, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a10 */
/* 0x000fe40007f5e0ff */
/*0560*/ IADD3.X R3, R5.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005037a10 */
/* 0x040fe400007fe4ff */
/*0570*/ IADD3.X R5, R5, c[0x0][0x164], RZ, P2, !PT ; /* 0x0000590005057a10 */
/* 0x000fe400017fe4ff */
/*0580*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0590*/ @!P1 BRA 0xa70 ; /* 0x000004d000009947 */
/* 0x000fee0003800000 */
/*05a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05b0*/ IADD3 R6, R0, -0xc, RZ ; /* 0xfffffff400067810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ LDG.E R8, [R4.64+-0x8] ; /* 0xfffff80404087981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*05f0*/ LDG.E R8, [R4.64+-0x4] ; /* 0xfffffc0404087981 */
/* 0x000ea8000c1e1900 */
/*0600*/ STG.E [R4.64+-0x8], R9 ; /* 0xfffff80904007986 */
/* 0x0001e8000c101904 */
/*0610*/ LDG.E R11, [R2.64+-0x4] ; /* 0xfffffc04020b7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0630*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*0640*/ STG.E [R4.64+-0x4], R11 ; /* 0xfffffc0b04007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0660*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0670*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea8000c1e1900 */
/*0680*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0007e8000c101904 */
/*0690*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ea4000c1e1900 */
/*06a0*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fc40000000000 */
/*06b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080404087981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0009e8000c101904 */
/*06d0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x001ea4000c1e1900 */
/*06e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*06f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0404087981 */
/* 0x000ea8000c1e1900 */
/*0700*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0720*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0730*/ LDG.E R8, [R4.64+0x10] ; /* 0x0000100404087981 */
/* 0x000ea8000c1e1900 */
/*0740*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0003e8000c101904 */
/*0750*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001004020d7981 */
/* 0x008ea4000c1e1900 */
/*0760*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0770*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140404087981 */
/* 0x000ea8000c1e1900 */
/*0780*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x0007e8000c101904 */
/*0790*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x010ea4000c1e1900 */
/*07a0*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fc40000000000 */
/*07b0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180404087981 */
/* 0x000ea8000c1e1900 */
/*07c0*/ STG.E [R4.64+0x14], R15 ; /* 0x0000140f04007986 */
/* 0x0009e8000c101904 */
/*07d0*/ LDG.E R9, [R2.64+0x18] ; /* 0x0000180402097981 */
/* 0x001ea4000c1e1900 */
/*07e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*07f0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0404087981 */
/* 0x000ea8000c1e1900 */
/*0800*/ STG.E [R4.64+0x18], R9 ; /* 0x0000180904007986 */
/* 0x0001e8000c101904 */
/*0810*/ LDG.E R11, [R2.64+0x1c] ; /* 0x00001c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0820*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0830*/ LDG.E R8, [R4.64+0x20] ; /* 0x0000200404087981 */
/* 0x000ea8000c1e1900 */
/*0840*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0003e8000c101904 */
/*0850*/ LDG.E R13, [R2.64+0x20] ; /* 0x00002004020d7981 */
/* 0x008ea4000c1e1900 */
/*0860*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0870*/ LDG.E R8, [R4.64+0x24] ; /* 0x0000240404087981 */
/* 0x000ea8000c1e1900 */
/*0880*/ STG.E [R4.64+0x20], R13 ; /* 0x0000200d04007986 */
/* 0x0007e8000c101904 */
/*0890*/ LDG.E R15, [R2.64+0x24] ; /* 0x00002404020f7981 */
/* 0x010ea4000c1e1900 */
/*08a0*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fc40000000000 */
/*08b0*/ LDG.E R8, [R4.64+0x28] ; /* 0x0000280404087981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ STG.E [R4.64+0x24], R15 ; /* 0x0000240f04007986 */
/* 0x0009e8000c101904 */
/*08d0*/ LDG.E R9, [R2.64+0x28] ; /* 0x0000280402097981 */
/* 0x001ea4000c1e1900 */
/*08e0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*08f0*/ LDG.E R8, [R4.64+0x2c] ; /* 0x00002c0404087981 */
/* 0x000ea8000c1e1900 */
/*0900*/ STG.E [R4.64+0x28], R9 ; /* 0x0000280904007986 */
/* 0x000fe8000c101904 */
/*0910*/ LDG.E R11, [R2.64+0x2c] ; /* 0x00002c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0920*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0930*/ LDG.E R8, [R4.64+0x30] ; /* 0x0000300404087981 */
/* 0x000ea8000c1e1900 */
/*0940*/ STG.E [R4.64+0x2c], R11 ; /* 0x00002c0b04007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R13, [R2.64+0x30] ; /* 0x00003004020d7981 */
/* 0x008ea2000c1e1900 */
/*0960*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe20007ffe0ff */
/*0970*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fc40000000000 */
/*0980*/ LDG.E R8, [R4.64+0x34] ; /* 0x0000340404087981 */
/* 0x000ea8000c1e1900 */
/*0990*/ STG.E [R4.64+0x30], R13 ; /* 0x0000300d04007986 */
/* 0x000fe8000c101904 */
/*09a0*/ LDG.E R15, [R2.64+0x34] ; /* 0x00003404020f7981 */
/* 0x0102a2000c1e1900 */
/*09b0*/ ISETP.GE.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe40003f26270 */
/*09c0*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*09d0*/ IADD3.X R11, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff0b7210 */
/* 0x001fe400017fe4ff */
/*09e0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x002fc60000000f00 */
/*09f0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0a00*/ FADD R15, R8, R15 ; /* 0x0000000f080f7221 */
/* 0x004fe20000000000 */
/*0a10*/ IADD3 R8, P3, R4, 0x40, RZ ; /* 0x0000004004087810 */
/* 0x000fc80007f7e0ff */
/*0a20*/ STG.E [R4.64+0x34], R15 ; /* 0x0000340f04007986 */
/* 0x0001e2000c101904 */
/*0a30*/ IMAD.X R9, RZ, RZ, R5, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0605 */
/*0a40*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x001fc60000000f00 */
/*0a50*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0a60*/ @!P1 BRA 0x5c0 ; /* 0xfffffb5000009947 */
/* 0x000fea000383ffff */
/*0a70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a80*/ IADD3 R6, R0, -R7, RZ ; /* 0x8000000700067210 */
/* 0x000fe20007ffe0ff */
/*0a90*/ BSSY B0, 0xd70 ; /* 0x000002d000007945 */
/* 0x000fe60003800000 */
/*0aa0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0ab0*/ @!P1 BRA 0xd60 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R6, [R4.64+-0x8] ; /* 0xfffff80404067981 */
/* 0x000ea8000c1e1900 */
/*0ad0*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea4000c1e1900 */
/*0ae0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fe40000000000 */
/*0af0*/ LDG.E R6, [R4.64+-0x4] ; /* 0xfffffc0404067981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ STG.E [R4.64+-0x8], R9 ; /* 0xfffff80904007986 */
/* 0x0001e8000c101904 */
/*0b10*/ LDG.E R11, [R2.64+-0x4] ; /* 0xfffffc04020b7981 */
/* 0x000ea4000c1e1900 */
/*0b20*/ FADD R11, R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fc40000000000 */
/*0b30*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0b40*/ STG.E [R4.64+-0x4], R11 ; /* 0xfffffc0b04007986 */
/* 0x0003e8000c101904 */
/*0b50*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0b60*/ FADD R13, R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fc40000000000 */
/*0b70*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0007e8000c101904 */
/*0b90*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ea4000c1e1900 */
/*0ba0*/ FADD R15, R6, R15 ; /* 0x0000000f060f7221 */
/* 0x004fc40000000000 */
/*0bb0*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ STG.E [R4.64+0x4], R15 ; /* 0x0000040f04007986 */
/* 0x0009e8000c101904 */
/*0bd0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x001ea4000c1e1900 */
/*0be0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x004fc40000000000 */
/*0bf0*/ LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404067981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x000fe8000c101904 */
/*0c10*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x002ea4000c1e1900 */
/*0c20*/ FADD R11, R6, R11 ; /* 0x0000000b060b7221 */
/* 0x004fc40000000000 */
/*0c30*/ LDG.E R6, [R4.64+0x10] ; /* 0x0000100404067981 */
/* 0x000ea8000c1e1900 */
/*0c40*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0001e8000c101904 */
/*0c50*/ LDG.E R13, [R2.64+0x10] ; /* 0x00001004020d7981 */
/* 0x008ea4000c1e1900 */
/*0c60*/ FADD R13, R6, R13 ; /* 0x0000000d060d7221 */
/* 0x004fc40000000000 */
/*0c70*/ LDG.E R6, [R4.64+0x14] ; /* 0x0000140404067981 */
/* 0x000ea8000c1e1900 */
/*0c80*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x000fe8000c101904 */
/*0c90*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x0102a2000c1e1900 */
/*0ca0*/ IADD3 R8, P1, R2, 0x20, RZ ; /* 0x0000002002087810 */
/* 0x000fe40007f3e0ff */
/*0cb0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0cc0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ IMAD.X R11, RZ, RZ, R3, P1 ; /* 0x000000ffff0b7224 */
/* 0x001fe400008e0603 */
/*0ce0*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x002fc600078e0008 */
/*0cf0*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe20000000f00 */
/*0d00*/ FADD R15, R6, R15 ; /* 0x0000000f060f7221 */
/* 0x004fe20000000000 */
/*0d10*/ IADD3 R6, P2, R4, 0x20, RZ ; /* 0x0000002004067810 */
/* 0x000fc80007f5e0ff */
/*0d20*/ IADD3.X R9, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff097210 */
/* 0x000fe200017fe4ff */
/*0d30*/ STG.E [R4.64+0x14], R15 ; /* 0x0000140f04007986 */
/* 0x0001e4000c101904 */
/*0d40*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0006 */
/*0d50*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*0d60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d70*/ ISETP.LT.OR P0, PT, R7, R0, P0 ; /* 0x000000000700720c */
/* 0x000fda0000701670 */
/*0d80*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d90*/ LDG.E R0, [R4.64+-0x8] ; /* 0xfffff80404007981 */
/* 0x000ea8000c1e1900 */
/*0da0*/ LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80402077981 */
/* 0x000ea4000c1e1900 */
/*0db0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fe40000000000 */
/*0dc0*/ LDG.E R0, [R4.64+-0x4] ; /* 0xfffffc0404007981 */
/* 0x000ea8000c1e1900 */
/*0dd0*/ STG.E [R4.64+-0x8], R7 ; /* 0xfffff80704007986 */
/* 0x000fe8000c101904 */
/*0de0*/ LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0402097981 */
/* 0x000ea4000c1e1900 */
/*0df0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fc40000000000 */
/*0e00*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0e10*/ STG.E [R4.64+-0x4], R9 ; /* 0xfffffc0904007986 */
/* 0x000fe8000c101904 */
/*0e20*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea4000c1e1900 */
/*0e30*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fc40000000000 */
/*0e40*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ea8000c1e1900 */
/*0e50*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0e60*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea4000c1e1900 */
/*0e70*/ FADD R13, R0, R13 ; /* 0x0000000d000d7221 */
/* 0x004fca0000000000 */
/*0e80*/ STG.E [R4.64+0x4], R13 ; /* 0x0000040d04007986 */
/* 0x000fe2000c101904 */
/*0e90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ea0*/ BRA 0xea0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10fp_bias_fcPfS_i
.globl _Z10fp_bias_fcPfS_i
.p2align 8
.type _Z10fp_bias_fcPfS_i,@function
_Z10fp_bias_fcPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_ashr_i32 s4, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s4
s_xor_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v3, s5, v1
v_cvt_u32_f32_e32 v0, v0
v_ashrrev_i32_e32 v4, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v3
v_mul_lo_u32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v1, v1, v4
v_add_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v4
v_xor_b32_e32 v4, s4, v4
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
v_xor_b32_e32 v2, v3, v5
v_xor_b32_e32 v5, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v3, v1, v0
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, v3, s3
v_mul_lo_u32 v7, v0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v1, v1, v6
v_add_nc_u32_e32 v6, 1, v3
v_sub_nc_u32_e32 v2, v2, v7
v_add_nc_u32_e32 v7, 1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_subrev_nc_u32_e32 v8, s3, v2
v_cmp_le_u32_e64 s2, s3, v2
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v0, v7, s2
v_cndmask_b32_e64 v2, v2, v8, s2
s_mov_b32 s2, 0
v_dual_cndmask_b32 v1, v1, v6 :: v_dual_add_nc_u32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, v3, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_mov_b32 s3, exec_lo
v_xor_b32_e32 v1, v1, v4
v_cndmask_b32_e32 v0, v0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v0, v5
v_sub_nc_u32_e32 v0, v1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v2, v5
v_cmpx_lt_i32_e64 v0, v5
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v6, v[1:2], off
global_load_b32 v7, v[3:4], off
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v0, v5
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v6, v7
global_store_b32 v[3:4], v6, off
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10fp_bias_fcPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10fp_bias_fcPfS_i, .Lfunc_end0-_Z10fp_bias_fcPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10fp_bias_fcPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10fp_bias_fcPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010caba_00000000-6_fp_bias_fc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i
.type _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i, @function
_Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10fp_bias_fcPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i, .-_Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i
.globl _Z10fp_bias_fcPfS_i
.type _Z10fp_bias_fcPfS_i, @function
_Z10fp_bias_fcPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10fp_bias_fcPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10fp_bias_fcPfS_i, .-_Z10fp_bias_fcPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10fp_bias_fcPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10fp_bias_fcPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fp_bias_fc.hip"
.globl _Z25__device_stub__fp_bias_fcPfS_i # -- Begin function _Z25__device_stub__fp_bias_fcPfS_i
.p2align 4, 0x90
.type _Z25__device_stub__fp_bias_fcPfS_i,@function
_Z25__device_stub__fp_bias_fcPfS_i: # @_Z25__device_stub__fp_bias_fcPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10fp_bias_fcPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__fp_bias_fcPfS_i, .Lfunc_end0-_Z25__device_stub__fp_bias_fcPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10fp_bias_fcPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10fp_bias_fcPfS_i,@object # @_Z10fp_bias_fcPfS_i
.section .rodata,"a",@progbits
.globl _Z10fp_bias_fcPfS_i
.p2align 3, 0x0
_Z10fp_bias_fcPfS_i:
.quad _Z25__device_stub__fp_bias_fcPfS_i
.size _Z10fp_bias_fcPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10fp_bias_fcPfS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__fp_bias_fcPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10fp_bias_fcPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Pointer.to(iGA_nPtBlock0.gpuArray),
Pointer.to(iGA_nPtBlock1.gpuArray),
Pointer.to(iGA_blockLevel.gpuArray),
Pointer.to(iGA_nPtBlPos.gpuArray),
Pointer.to(iGA_nPtBlNeg.gpuArray),
Pointer.to(iGA_nPtBlMid0.gpuArray),
Pointer.to(iGA_nPtBlMid1.gpuArray),
Pointer.to(iGA_newBlockCvg.gpuArray),
Pointer.to(iGA_newBlockLevel.gpuArray),
Pointer.to(new int[]{nDots}), // offset for blocks : 0 or 1
Pointer.to(new int[]{nBlocks}),
// Output values
Pointer.to(iGA_WhatToDoWithTheseBlocks.gpuArray)
*/
extern "C"
__global__ void sortBlocks(// Old tree specs
int* nPtBl0,
int* nPtBl1,
int* blLev,
// New tree specs
int* nPtBlPos,
int* nPtBlNeg,
int* nPtBlMid0,
int* nPtBlMid1,
int* newBlockCvg,
int* newBlockLvl,
int nDots,
int nBlocks,
int minInteract,
int minPointsToKeep,
// Output
int* whatToDo,
int* nPtKeep,
int* nBlocsKeep,
int* addrPt,
int* addrBloc
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocks) {
// do stuff
// first compute the number of interactions before split
float nInteractBefore=0;
float nPtB0 = (float)(nPtBl0[idBloc]);
float nPtB1 = (float)(nPtBl1[idBloc]);
int level = blLev[idBloc];
// now compute the number of interaction after spliting blocks
//__int2float_rd
float nInteractSubBlockNeg;
float nInteractSubBlockPos;
int nPtBlTotPos = nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks];
int nPtBlTotNeg = nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks];
int nPtBlTotMid0 = nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks];
int nPtBlTotMid1 = nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks];
if (level>0) {
nInteractBefore = nPtB0*nPtB1;
} else {
nInteractBefore=0.5*nPtB0*(nPtB0+1);
nPtBlTotPos = nPtBlPos[idBloc];
nPtBlTotNeg = nPtBlNeg[idBloc];
}
float nInteractSubBlockMid0=(float)(nPtBlMid0[idBloc])*(float)(nPtBlMid0[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+2]);
float nInteractSubBlockMid1=(float)(nPtBlMid1[idBloc])*(float)(nPtBlMid1[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+3]);
//printf("nInteractSubBlockMid0 = %f, car nPtBlMid0Bl0 = %i, et nPtBlMid0Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid0,nPtBlMid0[idBloc],nPtBlMid0[idBloc+nBlocks],blockIdx.x,idBloc);
//printf("nInteractSubBlockMid1 = %f, car nPtBlMid1Bl0 = %i, et nPtBlMid1Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid1,nPtBlMid1[idBloc],nPtBlMid1[idBloc+nBlocks],blockIdx.x,idBloc);
if (level==0) {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+1]);
//nPtB0=
} else {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc+nBlocks])*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc+nBlocks])*(newBlockCvg[4*idBloc+1]);
}
newBlockLvl[4*idBloc+0]=level; // bloc Neg
newBlockLvl[4*idBloc+1]=level; // bloc Pos
newBlockLvl[4*idBloc+2]=level+1; // bloc Mid0
newBlockLvl[4*idBloc+3]=level+1; // bloc Mid1
float nInteractAfter = nInteractSubBlockNeg+nInteractSubBlockPos+nInteractSubBlockMid0+nInteractSubBlockMid1;
// s'il y a plus d'interaction apres la coupure qu'avant ou s'il y a moins d'une certaine quantité d'interaction : option 0 : copy directement les blocs enfants vers le final
// default = trash
whatToDo[4*idBloc+0]=3;
whatToDo[4*idBloc+1]=3;
whatToDo[4*idBloc+2]=3;
whatToDo[4*idBloc+3]=3;
// KEEP = 1
// SPLIT = 0
// DISCARD = 2
// TRASH = 3
if (nInteractAfter>nInteractBefore) {
// KEEP ALL = 1
whatToDo[4*idBloc+0]=1;
whatToDo[4*idBloc+1]=1;
whatToDo[4*idBloc+2]=1;
whatToDo[4*idBloc+3]=1;
} else {
if (nInteractSubBlockPos>0) {
if ((nInteractSubBlockPos>=minInteract)&&((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+1]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+1]=1;
}
} else {
if ((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+1]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+1]=3;
}
}
if (nInteractSubBlockNeg>0) {
if ((nInteractSubBlockNeg>=minInteract)&&((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+0]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+0]=1;
}
} else {
if ((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+0]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+0]=3;
}
}
if (nInteractSubBlockMid0>0) {
if ((nInteractSubBlockMid0>=minInteract)&&((nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+2]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+2]=1;
}
} else {
// trash
whatToDo[4*idBloc+2]=3;
}
if (nInteractSubBlockMid1>0) {
if ((nInteractSubBlockMid1>=minInteract)&&((nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+3]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+3]=1;
}
} else {
// TRASH = 3
//printf("Trash Mid1 \n");
whatToDo[4*idBloc+3]=3;
}
}
//printf("Je suis le Pt %i et j'appart au bloc %i, sachant qu'on est dans le blocGPU %i \n",id_pt,id_bloc, blockIdx.x);
int indexNewBloc = 4*idBloc+0;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotNeg);
//printf("addrBloc = %i \n", addrBloc[indexNewBloc]);
indexNewBloc = 4*idBloc+1;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotPos);
indexNewBloc = 4*idBloc+2;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid0);
indexNewBloc = 4*idBloc+3;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid1);
// s'il y a zero interaction et plus d'une certaine quantité de points -> va vers les ignored : option 1
// s'il y a zero interaction et moins d'une certaine quantité de pointe -> trash : option 2
}
} | code for sm_80
Function : sortBlocks
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x1ac], PT ; /* 0x00006b0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R28, R5, R0, c[0x0][0x170] ; /* 0x00005c00051c7625 */
/* 0x000fcc00078e0200 */
/*0090*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R10, R5, R0, c[0x0][0x180] ; /* 0x00006000050a7625 */
/* 0x000fc800078e0200 */
/*00b0*/ IMAD.WIDE R12, R5.reuse, R0.reuse, c[0x0][0x178] ; /* 0x00005e00050c7625 */
/* 0x0c0fe200078e0200 */
/*00c0*/ LDG.E R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x000ee6000c1e1900 */
/*00d0*/ IMAD.SHL.U32 R3, R5.reuse, 0x4, RZ ; /* 0x0000000405037824 */
/* 0x040fe200078e00ff */
/*00e0*/ LDG.E R7, [R12.64] ; /* 0x000000040c077981 */
/* 0x000f22000c1e1900 */
/*00f0*/ IMAD.WIDE R18, R5, R0, c[0x0][0x160] ; /* 0x0000580005127625 */
/* 0x000fc800078e0200 */
/*0100*/ IMAD.WIDE R20, R3, R0, c[0x0][0x198] ; /* 0x0000660003147625 */
/* 0x000fe200078e0200 */
/*0110*/ LDG.E R2, [R18.64] ; /* 0x0000000412027981 */
/* 0x000166000c1e1900 */
/*0120*/ IMAD.WIDE R14, R0.reuse, c[0x0][0x1ac], R10 ; /* 0x00006b00000e7a25 */
/* 0x040fe200078e020a */
/*0130*/ LDG.E R33, [R20.64] ; /* 0x0000000414217981 */
/* 0x000368000c1e1900 */
/*0140*/ LDG.E R9, [R14.64] ; /* 0x000000040e097981 */
/* 0x000f62000c1e1900 */
/*0150*/ IMAD.WIDE R16, R0, c[0x0][0x1ac], R12 ; /* 0x00006b0000107a25 */
/* 0x000fc600078e020c */
/*0160*/ LDG.E R34, [R20.64+0x4] ; /* 0x0000040414227981 */
/* 0x000368000c1e1900 */
/*0170*/ LDG.E R8, [R16.64] ; /* 0x0000000410087981 */
/* 0x000f62000c1e1900 */
/*0180*/ ISETP.NE.AND P1, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x004fe20003f25270 */
/*0190*/ I2F R22, R6 ; /* 0x0000000600167306 */
/* 0x008fd80000201400 */
/*01a0*/ @!P1 IADD3 R26, R6, 0x1, RZ ; /* 0x00000001061a9810 */
/* 0x000fc80007ffe0ff */
/*01b0*/ @!P1 I2F R19, R26 ; /* 0x0000001a00139306 */
/* 0x001e220000201400 */
/*01c0*/ @!P1 IADD3 R32, R7, 0x1, RZ ; /* 0x0000000107209810 */
/* 0x010fce0007ffe0ff */
/*01d0*/ I2F R4, R7 ; /* 0x0000000700047306 */
/* 0x000fe20000201400 */
/*01e0*/ @!P1 FMUL R36, R22, R19 ; /* 0x0000001316249220 */
/* 0x001fce0000400000 */
/*01f0*/ @!P1 I2F R27, R32 ; /* 0x00000020001b9306 */
/* 0x000e300000201400 */
/*0200*/ @!P1 F2F.F64.F32 R20, R36 ; /* 0x0000002400149310 */
/* 0x002e620000201800 */
/*0210*/ ISETP.GT.AND P0, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fce0003f04270 */
/*0220*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x020ea20000201400 */
/*0230*/ @!P1 FMUL R37, R4, R27 ; /* 0x0000001b04259220 */
/* 0x001fce0000400000 */
/*0240*/ @!P1 I2F.F64 R18, R33 ; /* 0x0000002100129312 */
/* 0x000e220000201c00 */
/*0250*/ @!P1 DMUL R20, R20, 0.5 ; /* 0x3fe0000014149828 */
/* 0x002e0e0000000000 */
/*0260*/ @P1 I2F R23, R9 ; /* 0x0000000900171306 */
/* 0x000e700000201400 */
/*0270*/ @!P1 F2F.F64.F32 R26, R37 ; /* 0x00000025001a9310 */
/* 0x000ee20000201800 */
/*0280*/ @!P1 DMUL R18, R20, R18 ; /* 0x0000001214129228 */
/* 0x0011e20000000000 */
/*0290*/ @!P0 FADD R35, R2, 1 ; /* 0x3f80000002238421 */
/* 0x004fcc0000000000 */
/*02a0*/ @!P0 F2F.F64.F32 R24, R2 ; /* 0x0000000200188310 */
/* 0x000ea20000201800 */
/*02b0*/ @P1 FMUL R32, R22, R23 ; /* 0x0000001716201220 */
/* 0x002fce0000400000 */
/*02c0*/ @!P1 I2F.F64 R20, R34 ; /* 0x0000002200149312 */
/* 0x001e300000201c00 */
/*02d0*/ @P1 I2F R29, R33 ; /* 0x00000021001d1306 */
/* 0x000e620000201400 */
/*02e0*/ @!P1 DMUL R26, R26, 0.5 ; /* 0x3fe000001a1a9828 */
/* 0x008e0e0000000000 */
/*02f0*/ @P1 I2F R31, R8 ; /* 0x00000008001f1306 */
/* 0x000ef00000201400 */
/*0300*/ @!P0 F2F.F64.F32 R22, R35 ; /* 0x0000002300168310 */
/* 0x000f220000201800 */
/*0310*/ @!P0 DMUL R24, R24, 0.5 ; /* 0x3fe0000018188828 */
/* 0x004f220000000000 */
/*0320*/ @P1 FMUL R29, R32, R29 ; /* 0x0000001d201d1220 */
/* 0x002fcc0000400000 */
/*0330*/ @P1 I2F R30, R34 ; /* 0x00000022001e1306 */
/* 0x0002a20000201400 */
/*0340*/ @!P1 DMUL R20, R26, R20 ; /* 0x000000141a149228 */
/* 0x0011620000000000 */
/*0350*/ IMAD.WIDE R32, R5, R0, c[0x0][0x188] ; /* 0x0000620005207625 */
/* 0x000fc800078e0200 */
/*0360*/ IMAD.WIDE R26, R5, R0, c[0x0][0x190] ; /* 0x00006400051a7625 */
/* 0x001fe200078e0200 */
/*0370*/ @!P0 DMUL R22, R24, R22 ; /* 0x0000001618168228 */
/* 0x0101060000000000 */
/*0380*/ @P1 FMUL R31, R31, R4 ; /* 0x000000041f1f1220 */
/* 0x008fe40000400000 */
/*0390*/ IMAD.WIDE R24, R0.reuse, c[0x0][0x1ac], R26 ; /* 0x00006b0000187a25 */
/* 0x041fe200078e021a */
/*03a0*/ LDG.E R4, [R32.64] ; /* 0x0000000420047981 */
/* 0x000ee6000c1e1900 */
/*03b0*/ IMAD.WIDE R34, R0, c[0x0][0x1ac], R32 ; /* 0x00006b0000227a25 */
/* 0x002fe200078e0220 */
/*03c0*/ LDG.E R36, [R24.64] ; /* 0x0000000418247981 */
/* 0x000ee6000c1e1900 */
/*03d0*/ @P1 FMUL R30, R31, R30 ; /* 0x0000001e1f1e1220 */
/* 0x004fe20000400000 */
/*03e0*/ LDG.E R37, [R34.64] ; /* 0x0000000422257981 */
/* 0x000ea2000c1e1900 */
/*03f0*/ @!P1 F2F.F32.F64 R29, R18 ; /* 0x00000012001d9310 */
/* 0x0001e60000301000 */
/*0400*/ LDG.E R31, [R26.64] ; /* 0x000000041a1f7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R18, R5, R0, c[0x0][0x168] ; /* 0x00005a0005127625 */
/* 0x001fcc00078e0200 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0006a2000c1e1900 */
/*0430*/ @!P1 F2F.F32.F64 R30, R20 ; /* 0x00000014001e9310 */
/* 0x0200620000301000 */
/*0440*/ @!P0 MOV R5, R6.reuse ; /* 0x0000000600058202 */
/* 0x080fe40000000f00 */
/*0450*/ @P0 IADD3 R5, R9, R6, RZ ; /* 0x0000000609050210 */
/* 0x000fe20007ffe0ff */
/*0460*/ @!P0 IMAD.MOV.U32 R20, RZ, RZ, R7 ; /* 0x000000ffff148224 */
/* 0x001fe200078e0007 */
/*0470*/ @P0 IADD3 R20, R8, R7, RZ ; /* 0x0000000708140210 */
/* 0x000fc60007ffe0ff */
/*0480*/ @!P0 F2F.F32.F64 R22, R22 ; /* 0x0000001600168310 */
/* 0x0101220000301000 */
/*0490*/ IADD3 R9, R28, 0x1, RZ ; /* 0x000000011c097810 */
/* 0x000fe20007ffe0ff */
/*04a0*/ HFMA2.MMA R23, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff177435 */
/* 0x001fe200000001ff */
/*04b0*/ BSSY B0, 0xd20 ; /* 0x0000086000007945 */
/* 0x000fea0003800000 */
/*04c0*/ I2F R19, R4 ; /* 0x0000000400137306 */
/* 0x008ff00000201400 */
/*04d0*/ I2F R7, R36 ; /* 0x0000002400077306 */
/* 0x000ff00000201400 */
/*04e0*/ I2F R6, R31 ; /* 0x0000001f00067306 */
/* 0x004ff00000201400 */
/*04f0*/ I2F R8, R37 ; /* 0x0000002500087306 */
/* 0x000e300000201400 */
/*0500*/ I2F R21, R18 ; /* 0x0000001200157306 */
/* 0x0004e20000201400 */
/*0510*/ FMUL R19, R8, R19 ; /* 0x0000001308137220 */
/* 0x001fc40000400000 */
/*0520*/ FMUL R18, R7, R6 ; /* 0x0000000607127220 */
/* 0x004fe40000400000 */
/*0530*/ FADD R6, R30, R29 ; /* 0x0000001d1e067221 */
/* 0x002fc80000000000 */
/*0540*/ FADD R7, R19, R6 ; /* 0x0000000613077221 */
/* 0x000fe40000000000 */
/*0550*/ @P0 FMUL R22, R2, R21 ; /* 0x0000001502160220 */
/* 0x008fe40000400000 */
/*0560*/ FADD R7, R18, R7 ; /* 0x0000000712077221 */
/* 0x000fca0000000000 */
/*0570*/ FSETP.GT.AND P0, PT, R7, R22, PT ; /* 0x000000160700720b */
/* 0x010fe20003f04000 */
/*0580*/ IMAD.WIDE R6, R3, R0, c[0x0][0x1a0] ; /* 0x0000680003067625 */
/* 0x000fca00078e0200 */
/*0590*/ STG.E [R6.64+0x8], R9 ; /* 0x0000080906007986 */
/* 0x000fe8000c101904 */
/*05a0*/ STG.E [R6.64+0xc], R9 ; /* 0x00000c0906007986 */
/* 0x0001e8000c101904 */
/*05b0*/ STG.E [R6.64], R28 ; /* 0x0000001c06007986 */
/* 0x0003e8000c101904 */
/*05c0*/ STG.E [R6.64+0x4], R28 ; /* 0x0000041c06007986 */
/* 0x0003e2000c101904 */
/*05d0*/ IMAD.WIDE R8, R3, R0, c[0x0][0x1b8] ; /* 0x00006e0003087625 */
/* 0x001fca00078e0200 */
/*05e0*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0003e8000c101904 */
/*05f0*/ STG.E [R8.64+0x4], R23 ; /* 0x0000041708007986 */
/* 0x0003e8000c101904 */
/*0600*/ STG.E [R8.64+0x8], R23 ; /* 0x0000081708007986 */
/* 0x0003e8000c101904 */
/*0610*/ STG.E [R8.64+0xc], R23 ; /* 0x00000c1708007986 */
/* 0x0003e2000c101904 */
/*0620*/ IMAD.IADD R4, R37, 0x1, R4 ; /* 0x0000000125047824 */
/* 0x000fe200078e0204 */
/*0630*/ IADD3 R31, R36, R31, RZ ; /* 0x0000001f241f7210 */
/* 0x000fc40007ffe0ff */
/*0640*/ SHF.R.S32.HI R22, RZ, 0x1f, R3 ; /* 0x0000001fff167819 */
/* 0x000fe20000011403 */
/*0650*/ @P0 BRA 0xcb0 ; /* 0x0000065000000947 */
/* 0x000fea0003800000 */
/*0660*/ FSETP.GT.AND P0, PT, R30, RZ, PT ; /* 0x000000ff1e00720b */
/* 0x000fe20003f04000 */
/*0670*/ BSSY B1, 0x820 ; /* 0x000001a000017945 */
/* 0x000fd80003800000 */
/*0680*/ @P0 BRA 0x710 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0690*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ IADD3 R6, R12, R17, RZ ; /* 0x000000110c067210 */
/* 0x006fc80007ffe0ff */
/*06c0*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x1b4], PT ; /* 0x00006d0006007a0c */
/* 0x000fda0003f04270 */
/*06d0*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff070424 */
/* 0x000fe200078e00ff */
/*06e0*/ @!P0 STG.E [R8.64+0x4], R23 ; /* 0x0000041708008986 */
/* 0x0001e8000c101904 */
/*06f0*/ @P0 STG.E [R8.64+0x4], R7 ; /* 0x0000040708000986 */
/* 0x0001e2000c101904 */
/*0700*/ BRA 0x810 ; /* 0x0000010000007947 */
/* 0x000fea0003800000 */
/*0710*/ I2F R7, c[0x0][0x1b0] ; /* 0x00006c0000077b06 */
/* 0x002e220000201400 */
/*0720*/ BSSY B2, 0x7f0 ; /* 0x000000c000027945 */
/* 0x000fe20003800000 */
/*0730*/ FSETP.GE.AND P0, PT, R30, R7, PT ; /* 0x000000071e00720b */
/* 0x001fda0003f06000 */
/*0740*/ @!P0 BRA 0x7e0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ea2000c1e1900 */
/*0770*/ FADD R7, R2, R21 ; /* 0x0000001502077221 */
/* 0x000fe20000000000 */
/*0780*/ IADD3 R6, R12, R17, RZ ; /* 0x000000110c067210 */
/* 0x004fcc0007ffe0ff */
/*0790*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e240000201400 */
/*07a0*/ FSETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720b */
/* 0x001fda0003f04000 */
/*07b0*/ @P0 STG.E [R8.64+0x4], RZ ; /* 0x000004ff08000986 */
/* 0x0001e2000c101904 */
/*07c0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*07d0*/ @P0 BRA 0x810 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*07e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07f0*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fca0000000f00 */
/*0800*/ STG.E [R8.64+0x4], R7 ; /* 0x0000040708007986 */
/* 0x0003e4000c101904 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0820*/ FSETP.GT.AND P0, PT, R29, RZ, PT ; /* 0x000000ff1d00720b */
/* 0x000fe20003f04000 */
/*0830*/ BSSY B1, 0xa20 ; /* 0x000001e000017945 */
/* 0x000fd80003800000 */
/*0840*/ @P0 BRA 0x8f0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea4000c1e1900 */
/*0870*/ IMAD.IADD R6, R10, 0x1, R15 ; /* 0x000000010a067824 */
/* 0x004fca00078e020f */
/*0880*/ ISETP.GT.AND P0, PT, R6, c[0x0][0x1b4], PT ; /* 0x00006d0006007a0c */
/* 0x000fda0003f04270 */
/*0890*/ @P0 MOV R7, 0x2 ; /* 0x0000000200070802 */
/* 0x003fe20000000f00 */
/*08a0*/ @!P0 STG.E [R8.64], R23 ; /* 0x0000001708008986 */
/* 0x0001e2000c101904 */
/*08b0*/ @!P0 MOV R13, 0x3 ; /* 0x00000003000d8802 */
/* 0x000fe40000000f00 */
/*08c0*/ @P0 MOV R13, 0x2 ; /* 0x00000002000d0802 */
/* 0x000fe20000000f00 */
/*08d0*/ @P0 STG.E [R8.64], R7 ; /* 0x0000000708000986 */
/* 0x0001e2000c101904 */
/*08e0*/ BRA 0xa10 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*08f0*/ I2F R6, c[0x0][0x1b0] ; /* 0x00006c0000067b06 */
/* 0x000ea20000201400 */
/*0900*/ BSSY B2, 0x9e0 ; /* 0x000000d000027945 */
/* 0x000fe20003800000 */
/*0910*/ FSETP.GE.AND P0, PT, R29, R6, PT ; /* 0x000000061d00720b */
/* 0x004fda0003f06000 */
/*0920*/ @!P0 BRA 0x9d0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0930*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0940*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ea2000c1e1900 */
/*0950*/ FADD R7, R2, R21 ; /* 0x0000001502077221 */
/* 0x003fe40000000000 */
/*0960*/ IMAD.IADD R6, R10, 0x1, R15 ; /* 0x000000010a067824 */
/* 0x004fcc00078e020f */
/*0970*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e240000201400 */
/*0980*/ FSETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720b */
/* 0x001fda0003f04000 */
/*0990*/ @P0 STG.E [R8.64], RZ ; /* 0x000000ff08000986 */
/* 0x0001e2000c101904 */
/*09a0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*09b0*/ @P0 MOV R13, RZ ; /* 0x000000ff000d0202 */
/* 0x000fe20000000f00 */
/*09c0*/ @P0 BRA 0xa10 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*09d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*09e0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x003fe200000001ff */
/*09f0*/ MOV R13, 0x1 ; /* 0x00000001000d7802 */
/* 0x000fcc0000000f00 */
/*0a00*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e8000c101904 */
/*0a10*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.GT.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720b */
/* 0x000fe20003f04000 */
/*0a30*/ BSSY B1, 0xb70 ; /* 0x0000013000017945 */
/* 0x000fd80003800000 */
/*0a40*/ @!P0 STG.E [R8.64+0x8], R23 ; /* 0x0000081708008986 */
/* 0x0003e2000c101904 */
/*0a50*/ @!P0 BRA 0xb60 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0a60*/ I2F R6, c[0x0][0x1b0] ; /* 0x00006c0000067b06 */
/* 0x000ea20000201400 */
/*0a70*/ BSSY B2, 0xb40 ; /* 0x000000c000027945 */
/* 0x000fe20003800000 */
/*0a80*/ FSETP.GE.AND P0, PT, R19, R6, PT ; /* 0x000000061300720b */
/* 0x004fda0003f06000 */
/*0a90*/ @!P0 BRA 0xb30 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDG.E R32, [R32.64] ; /* 0x0000000420207981 */
/* 0x000ea8000c1e1900 */
/*0ab0*/ LDG.E R35, [R34.64] ; /* 0x0000000422237981 */
/* 0x000ea2000c1e1900 */
/*0ac0*/ FADD R7, R2, R21 ; /* 0x0000001502077221 */
/* 0x001fe40000000000 */
/*0ad0*/ IMAD.IADD R6, R32, 0x1, R35 ; /* 0x0000000120067824 */
/* 0x004fcc00078e0223 */
/*0ae0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e240000201400 */
/*0af0*/ FSETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720b */
/* 0x001fda0003f04000 */
/*0b00*/ @P0 STG.E [R8.64+0x8], RZ ; /* 0x000008ff08000986 */
/* 0x0001e2000c101904 */
/*0b10*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0b20*/ @P0 BRA 0xb60 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0b30*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b40*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x001fce00000001ff */
/*0b50*/ STG.E [R8.64+0x8], R7 ; /* 0x0000080708007986 */
/* 0x0001e8000c101904 */
/*0b60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b70*/ FSETP.GT.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720b */
/* 0x000fda0003f04000 */
/*0b80*/ @!P0 STG.E [R8.64+0xc], R23 ; /* 0x00000c1708008986 */
/* 0x0005e2000c101904 */
/*0b90*/ @!P0 BRA 0xd10 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ I2F R7, c[0x0][0x1b0] ; /* 0x00006c0000077b06 */
/* 0x001e220000201400 */
/*0bb0*/ BSSY B1, 0xc80 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*0bc0*/ FSETP.GE.AND P0, PT, R18, R7, PT ; /* 0x000000071200720b */
/* 0x001fda0003f06000 */
/*0bd0*/ @!P0 BRA 0xc70 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0be0*/ LDG.E R26, [R26.64] ; /* 0x000000041a1a7981 */
/* 0x000ee8000c1e1900 */
/*0bf0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ee2000c1e1900 */
/*0c00*/ FADD R21, R2, R21 ; /* 0x0000001502157221 */
/* 0x000fe20000000000 */
/*0c10*/ IADD3 R6, R26, R25, RZ ; /* 0x000000191a067210 */
/* 0x008fcc0007ffe0ff */
/*0c20*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e240000201400 */
/*0c30*/ FSETP.GT.AND P0, PT, R21, R6, PT ; /* 0x000000061500720b */
/* 0x001fda0003f04000 */
/*0c40*/ @P0 STG.E [R8.64+0xc], RZ ; /* 0x00000cff08000986 */
/* 0x0001e2000c101904 */
/*0c50*/ @P0 BREAK B1 ; /* 0x0000000000010942 */
/* 0x000fe20003800000 */
/*0c60*/ @P0 BRA 0xd10 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0c70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c80*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fca0000000f00 */
/*0c90*/ STG.E [R8.64+0xc], R7 ; /* 0x00000c0708007986 */
/* 0x0007e2000c101904 */
/*0ca0*/ BRA 0xd10 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x002fe200078e00ff */
/*0cc0*/ MOV R13, 0x1 ; /* 0x00000001000d7802 */
/* 0x000fc80000000f00 */
/*0cd0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e8000c101904 */
/*0ce0*/ STG.E [R8.64+0x4], R7 ; /* 0x0000040708007986 */
/* 0x0001e8000c101904 */
/*0cf0*/ STG.E [R8.64+0x8], R7 ; /* 0x0000080708007986 */
/* 0x0001e8000c101904 */
/*0d00*/ STG.E [R8.64+0xc], R7 ; /* 0x00000c0708007986 */
/* 0x0001e4000c101904 */
/*0d10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d20*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0d30*/ HFMA2.MMA R10, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0a7435 */
/* 0x000fe200000001ff */
/*0d40*/ IMAD.WIDE.U32 R12, R13, R0, c[0x0][0x1c8] ; /* 0x000072000d0c7625 */
/* 0x000fcc00078e0000 */
/*0d50*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R12.64], R10 ; /* 0x0000000a0c0b79a8 */
/* 0x000f2200081ee1c4 */
/*0d60*/ SHF.L.U32 R6, R3.reuse, 0x2, RZ ; /* 0x0000000203067819 */
/* 0x040fe400000006ff */
/*0d70*/ SHF.L.U64.HI R22, R3, 0x2, R22 ; /* 0x0000000203167819 */
/* 0x000fe40000010216 */
/*0d80*/ IADD3 R2, P0, R6, c[0x0][0x1d8], RZ ; /* 0x0000760006027a10 */
/* 0x000fc80007f1e0ff */
/*0d90*/ IADD3.X R3, R22, c[0x0][0x1dc], RZ, P0, !PT ; /* 0x0000770016037a10 */
/* 0x000fca00007fe4ff */
/*0da0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0109e8000c101904 */
/*0db0*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x000f62000c1e1900 */
/*0dc0*/ IADD3 R6, P0, R6, c[0x0][0x1d0], RZ ; /* 0x0000740006067a10 */
/* 0x000fe20007f1e0ff */
/*0dd0*/ IMAD.WIDE R14, R15, R0, c[0x0][0x1c0] ; /* 0x000070000f0e7625 */
/* 0x020fca00078e0200 */
/*0de0*/ ATOMG.E.ADD.STRONG.GPU PT, R5, [R14.64], R5 ; /* 0x000000050e0579a8 */
/* 0x000f6200081ee1c4 */
/*0df0*/ IADD3.X R7, R22, c[0x0][0x1d4], RZ, P0, !PT ; /* 0x0000750016077a10 */
/* 0x009fca00007fe4ff */
/*0e00*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0201e8000c101904 */
/*0e10*/ LDG.E R13, [R8.64+0x4] ; /* 0x00000404080d7981 */
/* 0x000ee4000c1e1900 */
/*0e20*/ IMAD.WIDE R12, R13, R0, c[0x0][0x1c8] ; /* 0x000072000d0c7625 */
/* 0x008fca00078e0200 */
/*0e30*/ ATOMG.E.ADD.STRONG.GPU PT, R19, [R12.64], R10 ; /* 0x0000000a0c1379a8 */
/* 0x000ee800081ee1c4 */
/*0e40*/ STG.E [R2.64+0x4], R19 ; /* 0x0000041302007986 */
/* 0x0087e8000c101904 */
/*0e50*/ LDG.E R17, [R8.64+0x4] ; /* 0x0000040408117981 */
/* 0x000f64000c1e1900 */
/*0e60*/ IMAD.WIDE R16, R17, R0, c[0x0][0x1c0] ; /* 0x0000700011107625 */
/* 0x020fca00078e0200 */
/*0e70*/ ATOMG.E.ADD.STRONG.GPU PT, R11, [R16.64], R20 ; /* 0x00000014100b79a8 */
/* 0x010f2800081ee1c4 */
/*0e80*/ STG.E [R6.64+0x4], R11 ; /* 0x0000040b06007986 */
/* 0x0109e8000c101904 */
/*0e90*/ LDG.E R15, [R8.64+0x8] ; /* 0x00000804080f7981 */
/* 0x000f64000c1e1900 */
/*0ea0*/ IMAD.WIDE R14, R15, R0, c[0x0][0x1c8] ; /* 0x000072000f0e7625 */
/* 0x020fca00078e0200 */
/*0eb0*/ ATOMG.E.ADD.STRONG.GPU PT, R5, [R14.64], R10 ; /* 0x0000000a0e0579a8 */
/* 0x001f6800081ee1c4 */
/*0ec0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x020fe8000c101904 */
/*0ed0*/ LDG.E R21, [R8.64+0x8] ; /* 0x0000080408157981 */
/* 0x000f64000c1e1900 */
/*0ee0*/ IMAD.WIDE R12, R21, R0, c[0x0][0x1c0] ; /* 0x00007000150c7625 */
/* 0x020fcc00078e0200 */
/*0ef0*/ ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R4 ; /* 0x000000040c0d79a8 */
/* 0x000f6800081ee1c4 */
/*0f00*/ STG.E [R6.64+0x8], R13 ; /* 0x0000080d06007986 */
/* 0x020fe8000c101904 */
/*0f10*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x008ee4000c1e1900 */
/*0f20*/ IMAD.WIDE R16, R19, R0, c[0x0][0x1c8] ; /* 0x0000720013107625 */
/* 0x008fcc00078e0200 */
/*0f30*/ ATOMG.E.ADD.STRONG.GPU PT, R17, [R16.64], R10 ; /* 0x0000000a101179a8 */
/* 0x000ee800081ee1c4 */
/*0f40*/ STG.E [R2.64+0xc], R17 ; /* 0x00000c1102007986 */
/* 0x008fe8000c101904 */
/*0f50*/ LDG.E R11, [R8.64+0xc] ; /* 0x00000c04080b7981 */
/* 0x010ee4000c1e1900 */
/*0f60*/ IMAD.WIDE R14, R11, R0, c[0x0][0x1c0] ; /* 0x000070000b0e7625 */
/* 0x008fcc00078e0200 */
/*0f70*/ ATOMG.E.ADD.STRONG.GPU PT, R15, [R14.64], R31 ; /* 0x0000001f0e0f79a8 */
/* 0x000ee800081ee1c4 */
/*0f80*/ STG.E [R6.64+0xc], R15 ; /* 0x00000c0f06007986 */
/* 0x008fe2000c101904 */
/*0f90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fa0*/ BRA 0xfa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Pointer.to(iGA_nPtBlock0.gpuArray),
Pointer.to(iGA_nPtBlock1.gpuArray),
Pointer.to(iGA_blockLevel.gpuArray),
Pointer.to(iGA_nPtBlPos.gpuArray),
Pointer.to(iGA_nPtBlNeg.gpuArray),
Pointer.to(iGA_nPtBlMid0.gpuArray),
Pointer.to(iGA_nPtBlMid1.gpuArray),
Pointer.to(iGA_newBlockCvg.gpuArray),
Pointer.to(iGA_newBlockLevel.gpuArray),
Pointer.to(new int[]{nDots}), // offset for blocks : 0 or 1
Pointer.to(new int[]{nBlocks}),
// Output values
Pointer.to(iGA_WhatToDoWithTheseBlocks.gpuArray)
*/
extern "C"
__global__ void sortBlocks(// Old tree specs
int* nPtBl0,
int* nPtBl1,
int* blLev,
// New tree specs
int* nPtBlPos,
int* nPtBlNeg,
int* nPtBlMid0,
int* nPtBlMid1,
int* newBlockCvg,
int* newBlockLvl,
int nDots,
int nBlocks,
int minInteract,
int minPointsToKeep,
// Output
int* whatToDo,
int* nPtKeep,
int* nBlocsKeep,
int* addrPt,
int* addrBloc
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocks) {
// do stuff
// first compute the number of interactions before split
float nInteractBefore=0;
float nPtB0 = (float)(nPtBl0[idBloc]);
float nPtB1 = (float)(nPtBl1[idBloc]);
int level = blLev[idBloc];
// now compute the number of interaction after spliting blocks
//__int2float_rd
float nInteractSubBlockNeg;
float nInteractSubBlockPos;
int nPtBlTotPos = nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks];
int nPtBlTotNeg = nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks];
int nPtBlTotMid0 = nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks];
int nPtBlTotMid1 = nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks];
if (level>0) {
nInteractBefore = nPtB0*nPtB1;
} else {
nInteractBefore=0.5*nPtB0*(nPtB0+1);
nPtBlTotPos = nPtBlPos[idBloc];
nPtBlTotNeg = nPtBlNeg[idBloc];
}
float nInteractSubBlockMid0=(float)(nPtBlMid0[idBloc])*(float)(nPtBlMid0[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+2]);
float nInteractSubBlockMid1=(float)(nPtBlMid1[idBloc])*(float)(nPtBlMid1[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+3]);
//printf("nInteractSubBlockMid0 = %f, car nPtBlMid0Bl0 = %i, et nPtBlMid0Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid0,nPtBlMid0[idBloc],nPtBlMid0[idBloc+nBlocks],blockIdx.x,idBloc);
//printf("nInteractSubBlockMid1 = %f, car nPtBlMid1Bl0 = %i, et nPtBlMid1Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid1,nPtBlMid1[idBloc],nPtBlMid1[idBloc+nBlocks],blockIdx.x,idBloc);
if (level==0) {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+1]);
//nPtB0=
} else {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc+nBlocks])*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc+nBlocks])*(newBlockCvg[4*idBloc+1]);
}
newBlockLvl[4*idBloc+0]=level; // bloc Neg
newBlockLvl[4*idBloc+1]=level; // bloc Pos
newBlockLvl[4*idBloc+2]=level+1; // bloc Mid0
newBlockLvl[4*idBloc+3]=level+1; // bloc Mid1
float nInteractAfter = nInteractSubBlockNeg+nInteractSubBlockPos+nInteractSubBlockMid0+nInteractSubBlockMid1;
// s'il y a plus d'interaction apres la coupure qu'avant ou s'il y a moins d'une certaine quantité d'interaction : option 0 : copy directement les blocs enfants vers le final
// default = trash
whatToDo[4*idBloc+0]=3;
whatToDo[4*idBloc+1]=3;
whatToDo[4*idBloc+2]=3;
whatToDo[4*idBloc+3]=3;
// KEEP = 1
// SPLIT = 0
// DISCARD = 2
// TRASH = 3
if (nInteractAfter>nInteractBefore) {
// KEEP ALL = 1
whatToDo[4*idBloc+0]=1;
whatToDo[4*idBloc+1]=1;
whatToDo[4*idBloc+2]=1;
whatToDo[4*idBloc+3]=1;
} else {
if (nInteractSubBlockPos>0) {
if ((nInteractSubBlockPos>=minInteract)&&((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+1]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+1]=1;
}
} else {
if ((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+1]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+1]=3;
}
}
if (nInteractSubBlockNeg>0) {
if ((nInteractSubBlockNeg>=minInteract)&&((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+0]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+0]=1;
}
} else {
if ((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+0]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+0]=3;
}
}
if (nInteractSubBlockMid0>0) {
if ((nInteractSubBlockMid0>=minInteract)&&((nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+2]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+2]=1;
}
} else {
// trash
whatToDo[4*idBloc+2]=3;
}
if (nInteractSubBlockMid1>0) {
if ((nInteractSubBlockMid1>=minInteract)&&((nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+3]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+3]=1;
}
} else {
// TRASH = 3
//printf("Trash Mid1 \n");
whatToDo[4*idBloc+3]=3;
}
}
//printf("Je suis le Pt %i et j'appart au bloc %i, sachant qu'on est dans le blocGPU %i \n",id_pt,id_bloc, blockIdx.x);
int indexNewBloc = 4*idBloc+0;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotNeg);
//printf("addrBloc = %i \n", addrBloc[indexNewBloc]);
indexNewBloc = 4*idBloc+1;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotPos);
indexNewBloc = 4*idBloc+2;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid0);
indexNewBloc = 4*idBloc+3;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid1);
// s'il y a zero interaction et plus d'une certaine quantité de points -> va vers les ignored : option 1
// s'il y a zero interaction et moins d'une certaine quantité de pointe -> trash : option 2
}
} | .file "tmpxft_00194487_00000000-6_gpuSortBlocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_
.type _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_, @function
_Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $344, %rsp
.cfi_def_cfa_offset 352
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 408(%rsp), %rax
movq %rax, 32(%rsp)
movq 416(%rsp), %rax
movq %rax, 24(%rsp)
movq 424(%rsp), %rax
movq %rax, 16(%rsp)
movq 432(%rsp), %rax
movq %rax, 8(%rsp)
movq 440(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 16(%rsp), %rax
movq %rax, 296(%rsp)
leaq 8(%rsp), %rax
movq %rax, 304(%rsp)
movq %rsp, %rax
movq %rax, 312(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 360
pushq 120(%rsp)
.cfi_def_cfa_offset 368
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq sortBlocks(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 352
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_, .-_Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_
.globl sortBlocks
.type sortBlocks, @function
sortBlocks:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 104(%rsp)
.cfi_def_cfa_offset 24
pushq 104(%rsp)
.cfi_def_cfa_offset 32
pushq 104(%rsp)
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
pushq 104(%rsp)
.cfi_def_cfa_offset 56
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sortBlocks, .-sortBlocks
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sortBlocks"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sortBlocks(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Pointer.to(iGA_nPtBlock0.gpuArray),
Pointer.to(iGA_nPtBlock1.gpuArray),
Pointer.to(iGA_blockLevel.gpuArray),
Pointer.to(iGA_nPtBlPos.gpuArray),
Pointer.to(iGA_nPtBlNeg.gpuArray),
Pointer.to(iGA_nPtBlMid0.gpuArray),
Pointer.to(iGA_nPtBlMid1.gpuArray),
Pointer.to(iGA_newBlockCvg.gpuArray),
Pointer.to(iGA_newBlockLevel.gpuArray),
Pointer.to(new int[]{nDots}), // offset for blocks : 0 or 1
Pointer.to(new int[]{nBlocks}),
// Output values
Pointer.to(iGA_WhatToDoWithTheseBlocks.gpuArray)
*/
extern "C"
__global__ void sortBlocks(// Old tree specs
int* nPtBl0,
int* nPtBl1,
int* blLev,
// New tree specs
int* nPtBlPos,
int* nPtBlNeg,
int* nPtBlMid0,
int* nPtBlMid1,
int* newBlockCvg,
int* newBlockLvl,
int nDots,
int nBlocks,
int minInteract,
int minPointsToKeep,
// Output
int* whatToDo,
int* nPtKeep,
int* nBlocsKeep,
int* addrPt,
int* addrBloc
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocks) {
// do stuff
// first compute the number of interactions before split
float nInteractBefore=0;
float nPtB0 = (float)(nPtBl0[idBloc]);
float nPtB1 = (float)(nPtBl1[idBloc]);
int level = blLev[idBloc];
// now compute the number of interaction after spliting blocks
//__int2float_rd
float nInteractSubBlockNeg;
float nInteractSubBlockPos;
int nPtBlTotPos = nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks];
int nPtBlTotNeg = nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks];
int nPtBlTotMid0 = nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks];
int nPtBlTotMid1 = nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks];
if (level>0) {
nInteractBefore = nPtB0*nPtB1;
} else {
nInteractBefore=0.5*nPtB0*(nPtB0+1);
nPtBlTotPos = nPtBlPos[idBloc];
nPtBlTotNeg = nPtBlNeg[idBloc];
}
float nInteractSubBlockMid0=(float)(nPtBlMid0[idBloc])*(float)(nPtBlMid0[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+2]);
float nInteractSubBlockMid1=(float)(nPtBlMid1[idBloc])*(float)(nPtBlMid1[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+3]);
//printf("nInteractSubBlockMid0 = %f, car nPtBlMid0Bl0 = %i, et nPtBlMid0Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid0,nPtBlMid0[idBloc],nPtBlMid0[idBloc+nBlocks],blockIdx.x,idBloc);
//printf("nInteractSubBlockMid1 = %f, car nPtBlMid1Bl0 = %i, et nPtBlMid1Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid1,nPtBlMid1[idBloc],nPtBlMid1[idBloc+nBlocks],blockIdx.x,idBloc);
if (level==0) {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+1]);
//nPtB0=
} else {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc+nBlocks])*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc+nBlocks])*(newBlockCvg[4*idBloc+1]);
}
newBlockLvl[4*idBloc+0]=level; // bloc Neg
newBlockLvl[4*idBloc+1]=level; // bloc Pos
newBlockLvl[4*idBloc+2]=level+1; // bloc Mid0
newBlockLvl[4*idBloc+3]=level+1; // bloc Mid1
float nInteractAfter = nInteractSubBlockNeg+nInteractSubBlockPos+nInteractSubBlockMid0+nInteractSubBlockMid1;
// s'il y a plus d'interaction apres la coupure qu'avant ou s'il y a moins d'une certaine quantité d'interaction : option 0 : copy directement les blocs enfants vers le final
// default = trash
whatToDo[4*idBloc+0]=3;
whatToDo[4*idBloc+1]=3;
whatToDo[4*idBloc+2]=3;
whatToDo[4*idBloc+3]=3;
// KEEP = 1
// SPLIT = 0
// DISCARD = 2
// TRASH = 3
if (nInteractAfter>nInteractBefore) {
// KEEP ALL = 1
whatToDo[4*idBloc+0]=1;
whatToDo[4*idBloc+1]=1;
whatToDo[4*idBloc+2]=1;
whatToDo[4*idBloc+3]=1;
} else {
if (nInteractSubBlockPos>0) {
if ((nInteractSubBlockPos>=minInteract)&&((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+1]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+1]=1;
}
} else {
if ((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+1]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+1]=3;
}
}
if (nInteractSubBlockNeg>0) {
if ((nInteractSubBlockNeg>=minInteract)&&((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+0]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+0]=1;
}
} else {
if ((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+0]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+0]=3;
}
}
if (nInteractSubBlockMid0>0) {
if ((nInteractSubBlockMid0>=minInteract)&&((nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+2]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+2]=1;
}
} else {
// trash
whatToDo[4*idBloc+2]=3;
}
if (nInteractSubBlockMid1>0) {
if ((nInteractSubBlockMid1>=minInteract)&&((nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+3]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+3]=1;
}
} else {
// TRASH = 3
//printf("Trash Mid1 \n");
whatToDo[4*idBloc+3]=3;
}
}
//printf("Je suis le Pt %i et j'appart au bloc %i, sachant qu'on est dans le blocGPU %i \n",id_pt,id_bloc, blockIdx.x);
int indexNewBloc = 4*idBloc+0;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotNeg);
//printf("addrBloc = %i \n", addrBloc[indexNewBloc]);
indexNewBloc = 4*idBloc+1;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotPos);
indexNewBloc = 4*idBloc+2;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid0);
indexNewBloc = 4*idBloc+3;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid1);
// s'il y a zero interaction et plus d'une certaine quantité de points -> va vers les ignored : option 1
// s'il y a zero interaction et moins d'une certaine quantité de pointe -> trash : option 2
}
} | #include <hip/hip_runtime.h>
/*
Pointer.to(iGA_nPtBlock0.gpuArray),
Pointer.to(iGA_nPtBlock1.gpuArray),
Pointer.to(iGA_blockLevel.gpuArray),
Pointer.to(iGA_nPtBlPos.gpuArray),
Pointer.to(iGA_nPtBlNeg.gpuArray),
Pointer.to(iGA_nPtBlMid0.gpuArray),
Pointer.to(iGA_nPtBlMid1.gpuArray),
Pointer.to(iGA_newBlockCvg.gpuArray),
Pointer.to(iGA_newBlockLevel.gpuArray),
Pointer.to(new int[]{nDots}), // offset for blocks : 0 or 1
Pointer.to(new int[]{nBlocks}),
// Output values
Pointer.to(iGA_WhatToDoWithTheseBlocks.gpuArray)
*/
extern "C"
__global__ void sortBlocks(// Old tree specs
int* nPtBl0,
int* nPtBl1,
int* blLev,
// New tree specs
int* nPtBlPos,
int* nPtBlNeg,
int* nPtBlMid0,
int* nPtBlMid1,
int* newBlockCvg,
int* newBlockLvl,
int nDots,
int nBlocks,
int minInteract,
int minPointsToKeep,
// Output
int* whatToDo,
int* nPtKeep,
int* nBlocsKeep,
int* addrPt,
int* addrBloc
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocks) {
// do stuff
// first compute the number of interactions before split
float nInteractBefore=0;
float nPtB0 = (float)(nPtBl0[idBloc]);
float nPtB1 = (float)(nPtBl1[idBloc]);
int level = blLev[idBloc];
// now compute the number of interaction after spliting blocks
//__int2float_rd
float nInteractSubBlockNeg;
float nInteractSubBlockPos;
int nPtBlTotPos = nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks];
int nPtBlTotNeg = nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks];
int nPtBlTotMid0 = nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks];
int nPtBlTotMid1 = nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks];
if (level>0) {
nInteractBefore = nPtB0*nPtB1;
} else {
nInteractBefore=0.5*nPtB0*(nPtB0+1);
nPtBlTotPos = nPtBlPos[idBloc];
nPtBlTotNeg = nPtBlNeg[idBloc];
}
float nInteractSubBlockMid0=(float)(nPtBlMid0[idBloc])*(float)(nPtBlMid0[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+2]);
float nInteractSubBlockMid1=(float)(nPtBlMid1[idBloc])*(float)(nPtBlMid1[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+3]);
//printf("nInteractSubBlockMid0 = %f, car nPtBlMid0Bl0 = %i, et nPtBlMid0Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid0,nPtBlMid0[idBloc],nPtBlMid0[idBloc+nBlocks],blockIdx.x,idBloc);
//printf("nInteractSubBlockMid1 = %f, car nPtBlMid1Bl0 = %i, et nPtBlMid1Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid1,nPtBlMid1[idBloc],nPtBlMid1[idBloc+nBlocks],blockIdx.x,idBloc);
if (level==0) {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+1]);
//nPtB0=
} else {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc+nBlocks])*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc+nBlocks])*(newBlockCvg[4*idBloc+1]);
}
newBlockLvl[4*idBloc+0]=level; // bloc Neg
newBlockLvl[4*idBloc+1]=level; // bloc Pos
newBlockLvl[4*idBloc+2]=level+1; // bloc Mid0
newBlockLvl[4*idBloc+3]=level+1; // bloc Mid1
float nInteractAfter = nInteractSubBlockNeg+nInteractSubBlockPos+nInteractSubBlockMid0+nInteractSubBlockMid1;
// s'il y a plus d'interaction apres la coupure qu'avant ou s'il y a moins d'une certaine quantité d'interaction : option 0 : copy directement les blocs enfants vers le final
// default = trash
whatToDo[4*idBloc+0]=3;
whatToDo[4*idBloc+1]=3;
whatToDo[4*idBloc+2]=3;
whatToDo[4*idBloc+3]=3;
// KEEP = 1
// SPLIT = 0
// DISCARD = 2
// TRASH = 3
if (nInteractAfter>nInteractBefore) {
// KEEP ALL = 1
whatToDo[4*idBloc+0]=1;
whatToDo[4*idBloc+1]=1;
whatToDo[4*idBloc+2]=1;
whatToDo[4*idBloc+3]=1;
} else {
if (nInteractSubBlockPos>0) {
if ((nInteractSubBlockPos>=minInteract)&&((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+1]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+1]=1;
}
} else {
if ((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+1]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+1]=3;
}
}
if (nInteractSubBlockNeg>0) {
if ((nInteractSubBlockNeg>=minInteract)&&((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+0]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+0]=1;
}
} else {
if ((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+0]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+0]=3;
}
}
if (nInteractSubBlockMid0>0) {
if ((nInteractSubBlockMid0>=minInteract)&&((nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+2]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+2]=1;
}
} else {
// trash
whatToDo[4*idBloc+2]=3;
}
if (nInteractSubBlockMid1>0) {
if ((nInteractSubBlockMid1>=minInteract)&&((nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+3]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+3]=1;
}
} else {
// TRASH = 3
//printf("Trash Mid1 \n");
whatToDo[4*idBloc+3]=3;
}
}
//printf("Je suis le Pt %i et j'appart au bloc %i, sachant qu'on est dans le blocGPU %i \n",id_pt,id_bloc, blockIdx.x);
int indexNewBloc = 4*idBloc+0;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotNeg);
//printf("addrBloc = %i \n", addrBloc[indexNewBloc]);
indexNewBloc = 4*idBloc+1;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotPos);
indexNewBloc = 4*idBloc+2;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid0);
indexNewBloc = 4*idBloc+3;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid1);
// s'il y a zero interaction et plus d'une certaine quantité de points -> va vers les ignored : option 1
// s'il y a zero interaction et moins d'une certaine quantité de pointe -> trash : option 2
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
Pointer.to(iGA_nPtBlock0.gpuArray),
Pointer.to(iGA_nPtBlock1.gpuArray),
Pointer.to(iGA_blockLevel.gpuArray),
Pointer.to(iGA_nPtBlPos.gpuArray),
Pointer.to(iGA_nPtBlNeg.gpuArray),
Pointer.to(iGA_nPtBlMid0.gpuArray),
Pointer.to(iGA_nPtBlMid1.gpuArray),
Pointer.to(iGA_newBlockCvg.gpuArray),
Pointer.to(iGA_newBlockLevel.gpuArray),
Pointer.to(new int[]{nDots}), // offset for blocks : 0 or 1
Pointer.to(new int[]{nBlocks}),
// Output values
Pointer.to(iGA_WhatToDoWithTheseBlocks.gpuArray)
*/
extern "C"
__global__ void sortBlocks(// Old tree specs
int* nPtBl0,
int* nPtBl1,
int* blLev,
// New tree specs
int* nPtBlPos,
int* nPtBlNeg,
int* nPtBlMid0,
int* nPtBlMid1,
int* newBlockCvg,
int* newBlockLvl,
int nDots,
int nBlocks,
int minInteract,
int minPointsToKeep,
// Output
int* whatToDo,
int* nPtKeep,
int* nBlocsKeep,
int* addrPt,
int* addrBloc
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocks) {
// do stuff
// first compute the number of interactions before split
float nInteractBefore=0;
float nPtB0 = (float)(nPtBl0[idBloc]);
float nPtB1 = (float)(nPtBl1[idBloc]);
int level = blLev[idBloc];
// now compute the number of interaction after spliting blocks
//__int2float_rd
float nInteractSubBlockNeg;
float nInteractSubBlockPos;
int nPtBlTotPos = nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks];
int nPtBlTotNeg = nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks];
int nPtBlTotMid0 = nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks];
int nPtBlTotMid1 = nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks];
if (level>0) {
nInteractBefore = nPtB0*nPtB1;
} else {
nInteractBefore=0.5*nPtB0*(nPtB0+1);
nPtBlTotPos = nPtBlPos[idBloc];
nPtBlTotNeg = nPtBlNeg[idBloc];
}
float nInteractSubBlockMid0=(float)(nPtBlMid0[idBloc])*(float)(nPtBlMid0[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+2]);
float nInteractSubBlockMid1=(float)(nPtBlMid1[idBloc])*(float)(nPtBlMid1[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+3]);
//printf("nInteractSubBlockMid0 = %f, car nPtBlMid0Bl0 = %i, et nPtBlMid0Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid0,nPtBlMid0[idBloc],nPtBlMid0[idBloc+nBlocks],blockIdx.x,idBloc);
//printf("nInteractSubBlockMid1 = %f, car nPtBlMid1Bl0 = %i, et nPtBlMid1Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid1,nPtBlMid1[idBloc],nPtBlMid1[idBloc+nBlocks],blockIdx.x,idBloc);
if (level==0) {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+1]);
//nPtB0=
} else {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc+nBlocks])*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc+nBlocks])*(newBlockCvg[4*idBloc+1]);
}
newBlockLvl[4*idBloc+0]=level; // bloc Neg
newBlockLvl[4*idBloc+1]=level; // bloc Pos
newBlockLvl[4*idBloc+2]=level+1; // bloc Mid0
newBlockLvl[4*idBloc+3]=level+1; // bloc Mid1
float nInteractAfter = nInteractSubBlockNeg+nInteractSubBlockPos+nInteractSubBlockMid0+nInteractSubBlockMid1;
// s'il y a plus d'interaction apres la coupure qu'avant ou s'il y a moins d'une certaine quantité d'interaction : option 0 : copy directement les blocs enfants vers le final
// default = trash
whatToDo[4*idBloc+0]=3;
whatToDo[4*idBloc+1]=3;
whatToDo[4*idBloc+2]=3;
whatToDo[4*idBloc+3]=3;
// KEEP = 1
// SPLIT = 0
// DISCARD = 2
// TRASH = 3
if (nInteractAfter>nInteractBefore) {
// KEEP ALL = 1
whatToDo[4*idBloc+0]=1;
whatToDo[4*idBloc+1]=1;
whatToDo[4*idBloc+2]=1;
whatToDo[4*idBloc+3]=1;
} else {
if (nInteractSubBlockPos>0) {
if ((nInteractSubBlockPos>=minInteract)&&((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+1]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+1]=1;
}
} else {
if ((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+1]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+1]=3;
}
}
if (nInteractSubBlockNeg>0) {
if ((nInteractSubBlockNeg>=minInteract)&&((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+0]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+0]=1;
}
} else {
if ((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+0]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+0]=3;
}
}
if (nInteractSubBlockMid0>0) {
if ((nInteractSubBlockMid0>=minInteract)&&((nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+2]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+2]=1;
}
} else {
// trash
whatToDo[4*idBloc+2]=3;
}
if (nInteractSubBlockMid1>0) {
if ((nInteractSubBlockMid1>=minInteract)&&((nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+3]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+3]=1;
}
} else {
// TRASH = 3
//printf("Trash Mid1 \n");
whatToDo[4*idBloc+3]=3;
}
}
//printf("Je suis le Pt %i et j'appart au bloc %i, sachant qu'on est dans le blocGPU %i \n",id_pt,id_bloc, blockIdx.x);
int indexNewBloc = 4*idBloc+0;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotNeg);
//printf("addrBloc = %i \n", addrBloc[indexNewBloc]);
indexNewBloc = 4*idBloc+1;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotPos);
indexNewBloc = 4*idBloc+2;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid0);
indexNewBloc = 4*idBloc+3;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid1);
// s'il y a zero interaction et plus d'une certaine quantité de points -> va vers les ignored : option 1
// s'il y a zero interaction et moins d'une certaine quantité de pointe -> trash : option 2
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sortBlocks
.globl sortBlocks
.p2align 8
.type sortBlocks,@function
sortBlocks:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x8c
s_load_b32 s2, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v8
s_cbranch_execz .LBB0_42
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v9, 31, v8
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x20
s_load_b64 s[16:17], s[0:1], 0x30
v_add_nc_u32_e32 v2, s2, v8
s_mov_b32 s2, exec_lo
v_lshlrev_b64 v[0:1], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[14:15], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v24, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v25, vcc_lo, s11, v1, vcc_lo
global_load_b32 v17, v[4:5], off
global_load_b32 v13, v[6:7], off
global_load_b32 v16, v[9:10], off
global_load_b32 v9, v[24:25], off
v_add_co_u32 v10, vcc_lo, s12, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s14, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s15, v1, vcc_lo
v_add_co_u32 v6, vcc_lo, s14, v14
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v15, vcc_lo
v_add_co_u32 v0, vcc_lo, s16, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s16, v14
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v15, vcc_lo
global_load_b32 v12, v[10:11], off
s_clause 0x1
global_load_b32 v34, v[4:5], off
global_load_b32 v35, v[6:7], off
s_clause 0x1
global_load_b32 v32, v[0:1], off
global_load_b32 v33, v[2:3], off
v_add_co_u32 v30, vcc_lo, s10, v14
v_add_co_ci_u32_e32 v31, vcc_lo, s11, v15, vcc_lo
v_add_co_u32 v18, vcc_lo, s12, v14
v_add_co_ci_u32_e32 v19, vcc_lo, s13, v15, vcc_lo
s_waitcnt vmcnt(8)
v_cvt_f32_i32_e32 v38, v17
s_waitcnt vmcnt(6)
v_cmpx_gt_i32_e32 1, v16
s_xor_b32 s2, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[14:15], v38
v_add_f32_e32 v17, 1.0, v38
v_cvt_f64_f32_e32 v[20:21], v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[14:15], 0.5
v_mul_f64 v[14:15], v[14:15], v[20:21]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v40, v[14:15]
s_or_saveexec_b32 s2, s2
v_cvt_f32_i32_e32 v39, v13
s_waitcnt vmcnt(4)
v_dual_mov_b32 v37, v12 :: v_dual_mov_b32 v36, v9
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
global_load_b32 v13, v[18:19], off
global_load_b32 v14, v[30:31], off
s_waitcnt vmcnt(1)
v_dual_mul_f32 v40, v38, v39 :: v_dual_add_nc_u32 v37, v13, v12
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v36, v14, v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x38
v_cvt_f32_i32_e32 v13, v12
v_cvt_f32_i32_e32 v14, v9
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v16
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_7
global_load_b32 v9, v[18:19], off
global_load_b32 v12, v[30:31], off
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v9, v9
v_lshlrev_b32_e32 v20, 2, v8
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, v13, v9
v_or_b32_e32 v22, 1, v20
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v23, 31, v22
v_lshlrev_b64 v[20:21], 2, v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[22:23], 2, v[22:23]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v20, vcc_lo, s2, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
v_add_co_u32 v22, vcc_lo, s2, v22
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
s_clause 0x1
global_load_b32 v15, v[20:21], off
global_load_b32 v17, v[22:23], off
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v13, v15
v_mul_f32_e32 v12, v14, v12
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v14, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v41, v9, v13
v_mul_f32_e32 v46, v12, v14
.LBB0_7:
s_and_not1_saveexec_b32 s4, s4
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v12, 1, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_dual_mul_f32 v12, v13, v12 :: v_dual_add_nc_u32 v9, 1, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v9, v9
v_lshlrev_b32_e32 v20, 2, v8
v_cvt_f64_f32_e32 v[12:13], v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v9, v14, v9
v_or_b32_e32 v22, 1, v20
v_ashrrev_i32_e32 v21, 31, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[14:15], v9
v_ashrrev_i32_e32 v23, 31, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[20:21], 2, v[20:21]
v_lshlrev_b64 v[22:23], 2, v[22:23]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v20, vcc_lo, s2, v20
v_add_co_ci_u32_e32 v21, vcc_lo, s3, v21, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v22, vcc_lo, s2, v22
v_add_co_ci_u32_e32 v23, vcc_lo, s3, v23, vcc_lo
s_clause 0x1
global_load_b32 v17, v[20:21], off
global_load_b32 v22, v[22:23], off
v_mul_f64 v[12:13], v[12:13], 0.5
v_mul_f64 v[14:15], v[14:15], 0.5
s_waitcnt vmcnt(1)
v_cvt_f64_i32_e32 v[20:21], v17
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[22:23], v22
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[12:13], v[20:21]
v_mul_f64 v[14:15], v[14:15], v[22:23]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v41, v[12:13]
v_cvt_f32_f64_e32 v46, v[14:15]
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x40
s_load_b64 s[4:5], s[0:1], 0x58
v_dual_mov_b32 v57, 3 :: v_dual_lshlrev_b32 v20, 2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v58, v46, v41 :: v_dual_add_nc_u32 v17, 1, v16
s_waitcnt vmcnt(3)
v_cvt_f32_i32_e32 v44, v34
v_or_b32_e32 v14, 1, v20
v_ashrrev_i32_e32 v21, 31, v20
v_or_b32_e32 v12, 2, v20
v_or_b32_e32 v8, 3, v20
s_waitcnt vmcnt(2)
v_cvt_f32_i32_e32 v45, v35
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[22:23], 2, v[20:21]
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v42, v32
v_lshlrev_b64 v[26:27], 2, v[14:15]
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v43, v33
v_lshlrev_b64 v[47:48], 2, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v28, vcc_lo, s2, v22
v_add_co_ci_u32_e32 v29, vcc_lo, s3, v23, vcc_lo
v_add_co_u32 v49, vcc_lo, s2, v26
v_lshlrev_b64 v[51:52], 2, v[8:9]
v_add_co_ci_u32_e32 v50, vcc_lo, s3, v27, vcc_lo
v_add_co_u32 v53, vcc_lo, s2, v47
v_add_co_ci_u32_e32 v54, vcc_lo, s3, v48, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v55, vcc_lo, s2, v51
v_add_co_ci_u32_e32 v56, vcc_lo, s3, v52, vcc_lo
s_clause 0x3
global_store_b32 v[28:29], v16, off
global_store_b32 v[49:50], v16, off
global_store_b32 v[53:54], v17, off
global_store_b32 v[55:56], v17, off
v_add_co_u32 v28, vcc_lo, s4, v22
v_add_co_ci_u32_e32 v29, vcc_lo, s5, v23, vcc_lo
v_add_co_u32 v26, vcc_lo, s4, v26
v_add_co_ci_u32_e32 v27, vcc_lo, s5, v27, vcc_lo
v_fmac_f32_e32 v58, v44, v45
v_add_co_u32 v22, vcc_lo, s4, v47
v_add_co_ci_u32_e32 v23, vcc_lo, s5, v48, vcc_lo
v_add_co_u32 v16, vcc_lo, s4, v51
s_delay_alu instid0(VALU_DEP_4)
v_fmac_f32_e32 v58, v42, v43
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v52, vcc_lo
s_clause 0x3
global_store_b32 v[28:29], v57, off
global_store_b32 v[26:27], v57, off
global_store_b32 v[22:23], v57, off
global_store_b32 v[16:17], v57, off
s_mov_b32 s2, exec_lo
v_cmpx_ngt_f32_e32 v58, v40
s_xor_b32 s4, exec_lo, s2
s_cbranch_execz .LBB0_39
s_load_b64 s[2:3], s[0:1], 0x50
s_mov_b32 s5, exec_lo
v_cmpx_nlt_f32_e32 0, v46
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_12
s_clause 0x1
global_load_b32 v24, v[24:25], off
global_load_b32 v25, v[30:31], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v24, v25, v24
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s3, v24
v_cndmask_b32_e64 v47, 3, 2, vcc_lo
.LBB0_12:
s_or_saveexec_b32 s5, s5
s_waitcnt lgkmcnt(0)
v_cvt_f32_i32_e32 v40, s2
s_xor_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_18
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nge_f32_e64 s2, v46, v40
s_mov_b32 s6, exec_lo
v_cmpx_ge_f32_e32 v46, v40
s_cbranch_execz .LBB0_15
s_clause 0x1
global_load_b32 v24, v[24:25], off
global_load_b32 v25, v[30:31], off
s_and_not1_b32 s2, s2, exec_lo
s_mov_b32 s7, 0
s_waitcnt vmcnt(0)
v_dual_add_f32 v25, v38, v39 :: v_dual_add_nc_u32 v24, v25, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v24, v24
v_cmp_ngt_f32_e32 vcc_lo, v25, v24
s_and_b32 s8, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s8
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v47, s7
s_and_saveexec_b32 s6, s2
v_mov_b32_e32 v47, 1
s_or_b32 exec_lo, exec_lo, s6
.LBB0_18:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s2, exec_lo
global_store_b32 v[26:27], v47, off
v_cmpx_nlt_f32_e32 0, v41
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_20
s_clause 0x1
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[18:19], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v10, v11, v10
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s3, v10
v_cndmask_b32_e64 v25, 3, 2, vcc_lo
.LBB0_20:
s_or_saveexec_b32 s2, s2
v_mul_f32_e32 v24, v44, v45
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_26
v_cmp_nge_f32_e64 s3, v41, v40
s_mov_b32 s5, exec_lo
v_cmpx_ge_f32_e32 v41, v40
s_cbranch_execz .LBB0_23
s_clause 0x1
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[18:19], off
s_and_not1_b32 s3, s3, exec_lo
s_mov_b32 s6, 0
s_waitcnt vmcnt(0)
v_dual_add_f32 v11, v38, v39 :: v_dual_add_nc_u32 v10, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v10, v10
v_cmp_ngt_f32_e32 vcc_lo, v11, v10
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s3, s7
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v25, s6
s_and_saveexec_b32 s5, s3
v_mov_b32_e32 v25, 1
s_or_b32 exec_lo, exec_lo, s5
.LBB0_26:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
v_dual_mul_f32 v10, v42, v43 :: v_dual_mov_b32 v47, 3
v_mov_b32_e32 v11, 3
s_mov_b32 s2, exec_lo
global_store_b32 v[28:29], v25, off
v_cmpx_lt_f32_e32 0, v24
s_cbranch_execz .LBB0_32
v_cmp_nge_f32_e64 s3, v24, v40
s_mov_b32 s5, exec_lo
v_cmpx_ge_f32_e32 v24, v40
s_cbranch_execz .LBB0_29
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
s_and_not1_b32 s3, s3, exec_lo
s_mov_b32 s6, 0
s_waitcnt vmcnt(0)
v_dual_add_f32 v5, v38, v39 :: v_dual_add_nc_u32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v4
v_cmp_ngt_f32_e32 vcc_lo, v5, v4
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s3, s7
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v11, s6
s_and_saveexec_b32 s5, s3
v_mov_b32_e32 v11, 1
s_or_b32 exec_lo, exec_lo, s5
.LBB0_32:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s2, exec_lo
global_store_b32 v[22:23], v11, off
v_cmpx_lt_f32_e32 0, v10
s_cbranch_execz .LBB0_38
v_cmp_nge_f32_e64 s3, v10, v40
s_mov_b32 s5, exec_lo
v_cmpx_ge_f32_e32 v10, v40
s_cbranch_execz .LBB0_35
s_clause 0x1
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_and_not1_b32 s3, s3, exec_lo
s_mov_b32 s6, 0
s_waitcnt vmcnt(0)
v_dual_add_f32 v1, v38, v39 :: v_dual_add_nc_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
v_cmp_ngt_f32_e32 vcc_lo, v1, v0
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s3, s3, s7
.LBB0_35:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v47, s6
s_and_saveexec_b32 s5, s3
v_mov_b32_e32 v47, 1
s_or_b32 exec_lo, exec_lo, s5
.LBB0_38:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
.LBB0_39:
s_and_not1_saveexec_b32 s2, s4
v_mov_b32_e32 v47, 1
s_clause 0x2
global_store_b32 v[28:29], v47, off
global_store_b32 v[26:27], v47, off
global_store_b32 v[22:23], v47, off
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[28:29], off
s_load_b256 s[0:7], s[0:1], 0x60
v_mov_b32_e32 v4, 1
global_store_b32 v[16:17], v47, off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v5, v[0:1], v4, off glc
v_lshlrev_b64 v[0:1], 2, v[20:21]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
global_load_b32 v2, v[28:29], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v2, v[2:3], v37, off glc
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
global_load_b32 v0, v[26:27], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v5, v[0:1], v4, off glc
v_lshlrev_b64 v[0:1], 2, v[14:15]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
global_load_b32 v2, v[26:27], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v2, v[2:3], v36, off glc
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
global_load_b32 v0, v[22:23], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v5, v[0:1], v4, off glc
v_lshlrev_b64 v[0:1], 2, v[12:13]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
v_add_nc_u32_e32 v5, v35, v34
global_load_b32 v2, v[22:23], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v2, v[2:3], v5, off glc
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
global_load_b32 v0, v[16:17], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v4, v[0:1], v4, off glc
v_lshlrev_b64 v[0:1], 2, v[8:9]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off
global_load_b32 v2, v[16:17], off
v_add_nc_u32_e32 v4, v33, v32
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v2, v[2:3], v4, off glc
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_42:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sortBlocks
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 384
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 59
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sortBlocks, .Lfunc_end0-sortBlocks
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 120
.size: 8
.value_kind: global_buffer
- .offset: 128
.size: 4
.value_kind: hidden_block_count_x
- .offset: 132
.size: 4
.value_kind: hidden_block_count_y
- .offset: 136
.size: 4
.value_kind: hidden_block_count_z
- .offset: 140
.size: 2
.value_kind: hidden_group_size_x
- .offset: 142
.size: 2
.value_kind: hidden_group_size_y
- .offset: 144
.size: 2
.value_kind: hidden_group_size_z
- .offset: 146
.size: 2
.value_kind: hidden_remainder_x
- .offset: 148
.size: 2
.value_kind: hidden_remainder_y
- .offset: 150
.size: 2
.value_kind: hidden_remainder_z
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 176
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 184
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 192
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 384
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: sortBlocks
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: sortBlocks.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 59
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
Pointer.to(iGA_nPtBlock0.gpuArray),
Pointer.to(iGA_nPtBlock1.gpuArray),
Pointer.to(iGA_blockLevel.gpuArray),
Pointer.to(iGA_nPtBlPos.gpuArray),
Pointer.to(iGA_nPtBlNeg.gpuArray),
Pointer.to(iGA_nPtBlMid0.gpuArray),
Pointer.to(iGA_nPtBlMid1.gpuArray),
Pointer.to(iGA_newBlockCvg.gpuArray),
Pointer.to(iGA_newBlockLevel.gpuArray),
Pointer.to(new int[]{nDots}), // offset for blocks : 0 or 1
Pointer.to(new int[]{nBlocks}),
// Output values
Pointer.to(iGA_WhatToDoWithTheseBlocks.gpuArray)
*/
extern "C"
__global__ void sortBlocks(// Old tree specs
int* nPtBl0,
int* nPtBl1,
int* blLev,
// New tree specs
int* nPtBlPos,
int* nPtBlNeg,
int* nPtBlMid0,
int* nPtBlMid1,
int* newBlockCvg,
int* newBlockLvl,
int nDots,
int nBlocks,
int minInteract,
int minPointsToKeep,
// Output
int* whatToDo,
int* nPtKeep,
int* nBlocsKeep,
int* addrPt,
int* addrBloc
)
{
int idBloc = blockIdx.x*blockDim.x+threadIdx.x;
if (idBloc<nBlocks) {
// do stuff
// first compute the number of interactions before split
float nInteractBefore=0;
float nPtB0 = (float)(nPtBl0[idBloc]);
float nPtB1 = (float)(nPtBl1[idBloc]);
int level = blLev[idBloc];
// now compute the number of interaction after spliting blocks
//__int2float_rd
float nInteractSubBlockNeg;
float nInteractSubBlockPos;
int nPtBlTotPos = nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks];
int nPtBlTotNeg = nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks];
int nPtBlTotMid0 = nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks];
int nPtBlTotMid1 = nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks];
if (level>0) {
nInteractBefore = nPtB0*nPtB1;
} else {
nInteractBefore=0.5*nPtB0*(nPtB0+1);
nPtBlTotPos = nPtBlPos[idBloc];
nPtBlTotNeg = nPtBlNeg[idBloc];
}
float nInteractSubBlockMid0=(float)(nPtBlMid0[idBloc])*(float)(nPtBlMid0[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+2]);
float nInteractSubBlockMid1=(float)(nPtBlMid1[idBloc])*(float)(nPtBlMid1[idBloc+nBlocks]);//*(newBlockCvg[4*idBloc+3]);
//printf("nInteractSubBlockMid0 = %f, car nPtBlMid0Bl0 = %i, et nPtBlMid0Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid0,nPtBlMid0[idBloc],nPtBlMid0[idBloc+nBlocks],blockIdx.x,idBloc);
//printf("nInteractSubBlockMid1 = %f, car nPtBlMid1Bl0 = %i, et nPtBlMid1Bl1 = %i, gpubloc = %i, bloc = %i \n",nInteractSubBlockMid1,nPtBlMid1[idBloc],nPtBlMid1[idBloc+nBlocks],blockIdx.x,idBloc);
if (level==0) {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc]+1)*0.5*(newBlockCvg[4*idBloc+1]);
//nPtB0=
} else {
nInteractSubBlockNeg=(float)(nPtBlNeg[idBloc])*(float)(nPtBlNeg[idBloc+nBlocks])*(newBlockCvg[4*idBloc+0]);
nInteractSubBlockPos=(float)(nPtBlPos[idBloc])*(float)(nPtBlPos[idBloc+nBlocks])*(newBlockCvg[4*idBloc+1]);
}
newBlockLvl[4*idBloc+0]=level; // bloc Neg
newBlockLvl[4*idBloc+1]=level; // bloc Pos
newBlockLvl[4*idBloc+2]=level+1; // bloc Mid0
newBlockLvl[4*idBloc+3]=level+1; // bloc Mid1
float nInteractAfter = nInteractSubBlockNeg+nInteractSubBlockPos+nInteractSubBlockMid0+nInteractSubBlockMid1;
// s'il y a plus d'interaction apres la coupure qu'avant ou s'il y a moins d'une certaine quantité d'interaction : option 0 : copy directement les blocs enfants vers le final
// default = trash
whatToDo[4*idBloc+0]=3;
whatToDo[4*idBloc+1]=3;
whatToDo[4*idBloc+2]=3;
whatToDo[4*idBloc+3]=3;
// KEEP = 1
// SPLIT = 0
// DISCARD = 2
// TRASH = 3
if (nInteractAfter>nInteractBefore) {
// KEEP ALL = 1
whatToDo[4*idBloc+0]=1;
whatToDo[4*idBloc+1]=1;
whatToDo[4*idBloc+2]=1;
whatToDo[4*idBloc+3]=1;
} else {
if (nInteractSubBlockPos>0) {
if ((nInteractSubBlockPos>=minInteract)&&((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+1]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+1]=1;
}
} else {
if ((nPtBlPos[idBloc]+nPtBlPos[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+1]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+1]=3;
}
}
if (nInteractSubBlockNeg>0) {
if ((nInteractSubBlockNeg>=minInteract)&&((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+0]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+0]=1;
}
} else {
if ((nPtBlNeg[idBloc]+nPtBlNeg[idBloc+nBlocks])>minPointsToKeep) {
// DISCARD = 2
whatToDo[4*idBloc+0]=2;
} else {
// TRASH = 3
whatToDo[4*idBloc+0]=3;
}
}
if (nInteractSubBlockMid0>0) {
if ((nInteractSubBlockMid0>=minInteract)&&((nPtBlMid0[idBloc]+nPtBlMid0[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+2]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+2]=1;
}
} else {
// trash
whatToDo[4*idBloc+2]=3;
}
if (nInteractSubBlockMid1>0) {
if ((nInteractSubBlockMid1>=minInteract)&&((nPtBlMid1[idBloc]+nPtBlMid1[idBloc+nBlocks])<(nPtB0+nPtB1))) {
// SPLIT = 0
whatToDo[4*idBloc+3]=0;
} else {
// KEEP = 1
whatToDo[4*idBloc+3]=1;
}
} else {
// TRASH = 3
//printf("Trash Mid1 \n");
whatToDo[4*idBloc+3]=3;
}
}
//printf("Je suis le Pt %i et j'appart au bloc %i, sachant qu'on est dans le blocGPU %i \n",id_pt,id_bloc, blockIdx.x);
int indexNewBloc = 4*idBloc+0;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotNeg);
//printf("addrBloc = %i \n", addrBloc[indexNewBloc]);
indexNewBloc = 4*idBloc+1;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotPos);
indexNewBloc = 4*idBloc+2;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid0);
indexNewBloc = 4*idBloc+3;
//printf("Je suis le Bloc %i et ce qu'on doit faire c'est %i pour le nouveau bloc %i \n",idBloc,whatToDo[indexNewBloc], indexNewBloc);
addrBloc[indexNewBloc]=atomicAdd(& nBlocsKeep[whatToDo[indexNewBloc]], 1 );
addrPt [indexNewBloc]=atomicAdd(& nPtKeep[whatToDo[indexNewBloc]] , nPtBlTotMid1);
// s'il y a zero interaction et plus d'une certaine quantité de points -> va vers les ignored : option 1
// s'il y a zero interaction et moins d'une certaine quantité de pointe -> trash : option 2
}
} | .text
.file "gpuSortBlocks.hip"
.globl __device_stub__sortBlocks # -- Begin function __device_stub__sortBlocks
.p2align 4, 0x90
.type __device_stub__sortBlocks,@function
__device_stub__sortBlocks: # @__device_stub__sortBlocks
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $sortBlocks, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size __device_stub__sortBlocks, .Lfunc_end0-__device_stub__sortBlocks
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sortBlocks, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type sortBlocks,@object # @sortBlocks
.section .rodata,"a",@progbits
.globl sortBlocks
.p2align 3, 0x0
sortBlocks:
.quad __device_stub__sortBlocks
.size sortBlocks, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sortBlocks"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sortBlocks
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sortBlocks
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00194487_00000000-6_gpuSortBlocks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_
.type _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_, @function
_Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $344, %rsp
.cfi_def_cfa_offset 352
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movq 352(%rsp), %rax
movq %rax, 56(%rsp)
movq 360(%rsp), %rax
movq %rax, 48(%rsp)
movq 368(%rsp), %rax
movq %rax, 40(%rsp)
movq 408(%rsp), %rax
movq %rax, 32(%rsp)
movq 416(%rsp), %rax
movq %rax, 24(%rsp)
movq 424(%rsp), %rax
movq %rax, 16(%rsp)
movq 432(%rsp), %rax
movq %rax, 8(%rsp)
movq 440(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 328(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 88(%rsp), %rax
movq %rax, 192(%rsp)
leaq 80(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 64(%rsp), %rax
movq %rax, 216(%rsp)
leaq 56(%rsp), %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rax
movq %rax, 232(%rsp)
leaq 40(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 384(%rsp), %rax
movq %rax, 256(%rsp)
leaq 392(%rsp), %rax
movq %rax, 264(%rsp)
leaq 400(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 16(%rsp), %rax
movq %rax, 296(%rsp)
leaq 8(%rsp), %rax
movq %rax, 304(%rsp)
movq %rsp, %rax
movq %rax, 312(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 328(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $344, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 360
pushq 120(%rsp)
.cfi_def_cfa_offset 368
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq sortBlocks(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 352
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_, .-_Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_
.globl sortBlocks
.type sortBlocks, @function
sortBlocks:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 104(%rsp)
.cfi_def_cfa_offset 24
pushq 104(%rsp)
.cfi_def_cfa_offset 32
pushq 104(%rsp)
.cfi_def_cfa_offset 40
pushq 104(%rsp)
.cfi_def_cfa_offset 48
pushq 104(%rsp)
.cfi_def_cfa_offset 56
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 80
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z60__device_stub__Z10sortBlocksPiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_PiS_S_S_S_S_S_S_S_iiiiS_S_S_S_S_
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size sortBlocks, .-sortBlocks
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sortBlocks"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq sortBlocks(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpuSortBlocks.hip"
.globl __device_stub__sortBlocks # -- Begin function __device_stub__sortBlocks
.p2align 4, 0x90
.type __device_stub__sortBlocks,@function
__device_stub__sortBlocks: # @__device_stub__sortBlocks
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 256(%rsp), %rax
movq %rax, 144(%rsp)
leaq 264(%rsp), %rax
movq %rax, 152(%rsp)
leaq 272(%rsp), %rax
movq %rax, 160(%rsp)
leaq 280(%rsp), %rax
movq %rax, 168(%rsp)
leaq 288(%rsp), %rax
movq %rax, 176(%rsp)
leaq 296(%rsp), %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 328(%rsp), %rax
movq %rax, 216(%rsp)
leaq 336(%rsp), %rax
movq %rax, 224(%rsp)
leaq 344(%rsp), %rax
movq %rax, 232(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $sortBlocks, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end0:
.size __device_stub__sortBlocks, .Lfunc_end0-__device_stub__sortBlocks
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sortBlocks, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type sortBlocks,@object # @sortBlocks
.section .rodata,"a",@progbits
.globl sortBlocks
.p2align 3, 0x0
sortBlocks:
.quad __device_stub__sortBlocks
.size sortBlocks, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sortBlocks"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sortBlocks
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sortBlocks
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void initialize(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = 0;
a[i] = 1 + i;
b[i] = 1 - i;
}
}
__global__ void addVectors(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N){
c[i] = a[i] + b[i];
}
}
int main (int argc, char **argv){
if (argc != 2) exit (1);
int N = atoi(argv[1]);
int block_size = 512;
int grid_size = (N-1) / block_size + 1;
float *a, *b, *c;
cudaMallocManaged (&a, N*sizeof(float));
cudaMallocManaged (&b, N*sizeof(float));
cudaMallocManaged (&c, N*sizeof(float));
initialize<<<grid_size, block_size>>>(N,a,b,c);
cudaDeviceSynchronize();
addVectors<<<grid_size, block_size>>>(N,a,b,c);
cudaDeviceSynchronize();
for (int i = 0; i < 5; i++) {
printf("%f\n", c[i]);
}
cudaFree(a);
cudaFree(b);
cudaFree(c);
} | code for sm_80
Function : _Z10addVectorsiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializeiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R6.reuse, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ IADD3 R8, -R6.reuse, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x040fe20007ffe1ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ I2F R9, R0 ; /* 0x0000000000097306 */
/* 0x000e2e0000201400 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x0c0fe200078e0207 */
/*00c0*/ I2F R11, R8 ; /* 0x00000008000b7306 */
/* 0x000e660000201400 */
/*00d0*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe200078e0207 */
/*00e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe6000c101904 */
/*00f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe8000c101904 */
/*0110*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x002fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void initialize(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = 0;
a[i] = 1 + i;
b[i] = 1 - i;
}
}
__global__ void addVectors(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N){
c[i] = a[i] + b[i];
}
}
int main (int argc, char **argv){
if (argc != 2) exit (1);
int N = atoi(argv[1]);
int block_size = 512;
int grid_size = (N-1) / block_size + 1;
float *a, *b, *c;
cudaMallocManaged (&a, N*sizeof(float));
cudaMallocManaged (&b, N*sizeof(float));
cudaMallocManaged (&c, N*sizeof(float));
initialize<<<grid_size, block_size>>>(N,a,b,c);
cudaDeviceSynchronize();
addVectors<<<grid_size, block_size>>>(N,a,b,c);
cudaDeviceSynchronize();
for (int i = 0; i < 5; i++) {
printf("%f\n", c[i]);
}
cudaFree(a);
cudaFree(b);
cudaFree(c);
} | .file "tmpxft_000e2c8e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
.type _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_, @function
_Z35__device_stub__Z10initializeiPfS_S_iPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10initializeiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_, .-_Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
.globl _Z10initializeiPfS_S_
.type _Z10initializeiPfS_S_, @function
_Z10initializeiPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10initializeiPfS_S_, .-_Z10initializeiPfS_S_
.globl _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
.type _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_, @function
_Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10addVectorsiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_, .-_Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
.globl _Z10addVectorsiPfS_S_
.type _Z10addVectorsiPfS_S_, @function
_Z10addVectorsiPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10addVectorsiPfS_S_, .-_Z10addVectorsiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L27
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movslq %eax, %r12
salq $2, %r12
leaq 8(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 510(%rbx), %eax
subl $1, %ebx
cmovs %eax, %ebx
sarl $9, %ebx
addl $1, %ebx
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L23:
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $20, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $1, %edi
call exit@PLT
.L28:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
jmp .L21
.L29:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10addVectorsiPfS_S_"
.LC2:
.string "_Z10initializeiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addVectorsiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializeiPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
__global__ void initialize(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = 0;
a[i] = 1 + i;
b[i] = 1 - i;
}
}
__global__ void addVectors(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N){
c[i] = a[i] + b[i];
}
}
int main (int argc, char **argv){
if (argc != 2) exit (1);
int N = atoi(argv[1]);
int block_size = 512;
int grid_size = (N-1) / block_size + 1;
float *a, *b, *c;
cudaMallocManaged (&a, N*sizeof(float));
cudaMallocManaged (&b, N*sizeof(float));
cudaMallocManaged (&c, N*sizeof(float));
initialize<<<grid_size, block_size>>>(N,a,b,c);
cudaDeviceSynchronize();
addVectors<<<grid_size, block_size>>>(N,a,b,c);
cudaDeviceSynchronize();
for (int i = 0; i < 5; i++) {
printf("%f\n", c[i]);
}
cudaFree(a);
cudaFree(b);
cudaFree(c);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void initialize(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = 0;
a[i] = 1 + i;
b[i] = 1 - i;
}
}
__global__ void addVectors(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N){
c[i] = a[i] + b[i];
}
}
int main (int argc, char **argv){
if (argc != 2) exit (1);
int N = atoi(argv[1]);
int block_size = 512;
int grid_size = (N-1) / block_size + 1;
float *a, *b, *c;
hipMallocManaged (&a, N*sizeof(float));
hipMallocManaged (&b, N*sizeof(float));
hipMallocManaged (&c, N*sizeof(float));
initialize<<<grid_size, block_size>>>(N,a,b,c);
hipDeviceSynchronize();
addVectors<<<grid_size, block_size>>>(N,a,b,c);
hipDeviceSynchronize();
for (int i = 0; i < 5; i++) {
printf("%f\n", c[i]);
}
hipFree(a);
hipFree(b);
hipFree(c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void initialize(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = 0;
a[i] = 1 + i;
b[i] = 1 - i;
}
}
__global__ void addVectors(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N){
c[i] = a[i] + b[i];
}
}
int main (int argc, char **argv){
if (argc != 2) exit (1);
int N = atoi(argv[1]);
int block_size = 512;
int grid_size = (N-1) / block_size + 1;
float *a, *b, *c;
hipMallocManaged (&a, N*sizeof(float));
hipMallocManaged (&b, N*sizeof(float));
hipMallocManaged (&c, N*sizeof(float));
initialize<<<grid_size, block_size>>>(N,a,b,c);
hipDeviceSynchronize();
addVectors<<<grid_size, block_size>>>(N,a,b,c);
hipDeviceSynchronize();
for (int i = 0; i < 5; i++) {
printf("%f\n", c[i]);
}
hipFree(a);
hipFree(b);
hipFree(c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializeiPfS_S_
.globl _Z10initializeiPfS_S_
.p2align 8
.type _Z10initializeiPfS_S_,@function
_Z10initializeiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, 1, v1
v_sub_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cvt_f32_i32_e32 v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v8, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
global_store_b32 v[0:1], v8, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializeiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializeiPfS_S_, .Lfunc_end0-_Z10initializeiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10addVectorsiPfS_S_
.globl _Z10addVectorsiPfS_S_
.p2align 8
.type _Z10addVectorsiPfS_S_,@function
_Z10addVectorsiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10addVectorsiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10addVectorsiPfS_S_, .Lfunc_end1-_Z10addVectorsiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializeiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializeiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10addVectorsiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10addVectorsiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
__global__ void initialize(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N) {
c[i] = 0;
a[i] = 1 + i;
b[i] = 1 - i;
}
}
__global__ void addVectors(int N, float *a, float *b, float *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < N){
c[i] = a[i] + b[i];
}
}
int main (int argc, char **argv){
if (argc != 2) exit (1);
int N = atoi(argv[1]);
int block_size = 512;
int grid_size = (N-1) / block_size + 1;
float *a, *b, *c;
hipMallocManaged (&a, N*sizeof(float));
hipMallocManaged (&b, N*sizeof(float));
hipMallocManaged (&c, N*sizeof(float));
initialize<<<grid_size, block_size>>>(N,a,b,c);
hipDeviceSynchronize();
addVectors<<<grid_size, block_size>>>(N,a,b,c);
hipDeviceSynchronize();
for (int i = 0; i < 5; i++) {
printf("%f\n", c[i]);
}
hipFree(a);
hipFree(b);
hipFree(c);
} | .text
.file "main.hip"
.globl _Z25__device_stub__initializeiPfS_S_ # -- Begin function _Z25__device_stub__initializeiPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__initializeiPfS_S_,@function
_Z25__device_stub__initializeiPfS_S_: # @_Z25__device_stub__initializeiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10initializeiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__initializeiPfS_S_, .Lfunc_end0-_Z25__device_stub__initializeiPfS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__addVectorsiPfS_S_ # -- Begin function _Z25__device_stub__addVectorsiPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__addVectorsiPfS_S_,@function
_Z25__device_stub__addVectorsiPfS_S_: # @_Z25__device_stub__addVectorsiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addVectorsiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__addVectorsiPfS_S_, .Lfunc_end1-_Z25__device_stub__addVectorsiPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB2_8
# %bb.1:
movabsq $4294967808, %r14 # imm = 0x100000200
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
decl %eax
leal 510(%rbx), %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
sarl $9, %r12d
incl %r12d
movslq %ebx, %r15
shlq $2, %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
leaq (%r12,%r14), %r15
addq $-512, %r15 # imm = 0xFE00
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %ebx, 12(%rsp)
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10initializeiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %ebx, 12(%rsp)
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10addVectorsiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB2_6
# %bb.7:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 192
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializeiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addVectorsiPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializeiPfS_S_,@object # @_Z10initializeiPfS_S_
.section .rodata,"a",@progbits
.globl _Z10initializeiPfS_S_
.p2align 3, 0x0
_Z10initializeiPfS_S_:
.quad _Z25__device_stub__initializeiPfS_S_
.size _Z10initializeiPfS_S_, 8
.type _Z10addVectorsiPfS_S_,@object # @_Z10addVectorsiPfS_S_
.globl _Z10addVectorsiPfS_S_
.p2align 3, 0x0
_Z10addVectorsiPfS_S_:
.quad _Z25__device_stub__addVectorsiPfS_S_
.size _Z10addVectorsiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializeiPfS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10addVectorsiPfS_S_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializeiPfS_S_
.addrsig_sym _Z25__device_stub__addVectorsiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10initializeiPfS_S_
.addrsig_sym _Z10addVectorsiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10addVectorsiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10initializeiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R0, R6.reuse, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x040fe20007ffe0ff */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ IADD3 R8, -R6.reuse, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x040fe20007ffe1ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ I2F R9, R0 ; /* 0x0000000000097306 */
/* 0x000e2e0000201400 */
/*00b0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x0c0fe200078e0207 */
/*00c0*/ I2F R11, R8 ; /* 0x00000008000b7306 */
/* 0x000e660000201400 */
/*00d0*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe200078e0207 */
/*00e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe6000c101904 */
/*00f0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe8000c101904 */
/*0110*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x002fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10initializeiPfS_S_
.globl _Z10initializeiPfS_S_
.p2align 8
.type _Z10initializeiPfS_S_,@function
_Z10initializeiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v3, 1, v1
v_sub_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cvt_f32_i32_e32 v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f32_i32_e32 v8, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_store_b32 v[4:5], v7, off
global_store_b32 v[0:1], v8, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10initializeiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10initializeiPfS_S_, .Lfunc_end0-_Z10initializeiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10addVectorsiPfS_S_
.globl _Z10addVectorsiPfS_S_
.p2align 8
.type _Z10addVectorsiPfS_S_,@function
_Z10addVectorsiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10addVectorsiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10addVectorsiPfS_S_, .Lfunc_end1-_Z10addVectorsiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10initializeiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10initializeiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10addVectorsiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10addVectorsiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e2c8e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
.type _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_, @function
_Z35__device_stub__Z10initializeiPfS_S_iPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10initializeiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_, .-_Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
.globl _Z10initializeiPfS_S_
.type _Z10initializeiPfS_S_, @function
_Z10initializeiPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10initializeiPfS_S_, .-_Z10initializeiPfS_S_
.globl _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
.type _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_, @function
_Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10addVectorsiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_, .-_Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
.globl _Z10addVectorsiPfS_S_
.type _Z10addVectorsiPfS_S_, @function
_Z10addVectorsiPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10addVectorsiPfS_S_, .-_Z10addVectorsiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jne .L27
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
movslq %eax, %r12
salq $2, %r12
leaq 8(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movq %r12, %rsi
call cudaMallocManaged@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 510(%rbx), %eax
subl $1, %ebx
cmovs %eax, %ebx
sarl $9, %ebx
addl $1, %ebx
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L23:
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $20, %rbx
jne .L23
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $1, %edi
call exit@PLT
.L28:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z35__device_stub__Z10initializeiPfS_S_iPfS_S_
jmp .L21
.L29:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z35__device_stub__Z10addVectorsiPfS_S_iPfS_S_
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10addVectorsiPfS_S_"
.LC2:
.string "_Z10initializeiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addVectorsiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10initializeiPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z25__device_stub__initializeiPfS_S_ # -- Begin function _Z25__device_stub__initializeiPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__initializeiPfS_S_,@function
_Z25__device_stub__initializeiPfS_S_: # @_Z25__device_stub__initializeiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10initializeiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__initializeiPfS_S_, .Lfunc_end0-_Z25__device_stub__initializeiPfS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__addVectorsiPfS_S_ # -- Begin function _Z25__device_stub__addVectorsiPfS_S_
.p2align 4, 0x90
.type _Z25__device_stub__addVectorsiPfS_S_,@function
_Z25__device_stub__addVectorsiPfS_S_: # @_Z25__device_stub__addVectorsiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addVectorsiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__addVectorsiPfS_S_, .Lfunc_end1-_Z25__device_stub__addVectorsiPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB2_8
# %bb.1:
movabsq $4294967808, %r14 # imm = 0x100000200
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
decl %eax
leal 510(%rbx), %r12d
testl %eax, %eax
cmovnsl %eax, %r12d
sarl $9, %r12d
incl %r12d
movslq %ebx, %r15
shlq $2, %r15
leaq 32(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
leaq (%r12,%r14), %r15
addq $-512, %r15 # imm = 0xFE00
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %ebx, 12(%rsp)
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10initializeiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %ebx, 12(%rsp)
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10addVectorsiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB2_6
# %bb.7:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 192
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10initializeiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addVectorsiPfS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10initializeiPfS_S_,@object # @_Z10initializeiPfS_S_
.section .rodata,"a",@progbits
.globl _Z10initializeiPfS_S_
.p2align 3, 0x0
_Z10initializeiPfS_S_:
.quad _Z25__device_stub__initializeiPfS_S_
.size _Z10initializeiPfS_S_, 8
.type _Z10addVectorsiPfS_S_,@object # @_Z10addVectorsiPfS_S_
.globl _Z10addVectorsiPfS_S_
.p2align 3, 0x0
_Z10addVectorsiPfS_S_:
.quad _Z25__device_stub__addVectorsiPfS_S_
.size _Z10addVectorsiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10initializeiPfS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10addVectorsiPfS_S_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__initializeiPfS_S_
.addrsig_sym _Z25__device_stub__addVectorsiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10initializeiPfS_S_
.addrsig_sym _Z10addVectorsiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "cuda.h"
#define CEIL(a,b) ((a+b-1)/b)
#define PI 3.1415926
#define EDGE 0
#define NOEDGE 255
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
uch *TheImg, *CopyImg; // Where images are stored in CPU
int ThreshLo=50, ThreshHi=100; // "Edge" vs. "No Edge" thresholds
// Where images and temporary results are stored in GPU
uch *GPUImg, *GPUResultImg;
double *GPUBWImg, *GPUGaussImg, *GPUGradient, *GPUTheta;
struct ImgProp{
ui Hpixels;
ui Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Kernel that calculates a B&W image from an RGB image
// resulting image has a double type for each pixel position
__global__
void BWKernel(double *ImgBW, uch *ImgGPU, ui Hpixels)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
double R, G, B;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
ui RowBytes = (Hpixels * 3 + 3) & (~3);
ui MYrow = MYbid / BlkPerRow;
ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYsrcIndex = MYrow * RowBytes + 3 * MYcol;
ui MYpixIndex = MYrow * Hpixels + MYcol;
B = (double)ImgGPU[MYsrcIndex];
G = (double)ImgGPU[MYsrcIndex + 1];
R = (double)ImgGPU[MYsrcIndex + 2];
ImgBW[MYpixIndex] = (R+G+B)/3.0;
}
__device__
double Gauss[5][5] = { { 2, 4, 5, 4, 2 },
{ 4, 9, 12, 9, 4 },
{ 5, 12, 15, 12, 5 },
{ 4, 9, 12, 9, 4 },
{ 2, 4, 5, 4, 2 } };
// Kernel that calculates a Gauss image from the B&W image
// resulting image has a double type for each pixel position
__global__
void GaussKernel(double *ImgGauss, double *ImgBW, ui Hpixels, ui Vpixels)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
int row, col, indx, i, j;
double G=0.00;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
int MYrow = MYbid / BlkPerRow;
int MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYpixIndex = MYrow * Hpixels + MYcol;
if ((MYrow<2) || (MYrow>Vpixels - 3) || (MYcol<2) || (MYcol>Hpixels - 3)){
ImgGauss[MYpixIndex] = 0.0;
return;
}else{
G = 0.0;
for (i = -2; i <= 2; i++){
for (j = -2; j <= 2; j++){
row = MYrow + i;
col = MYcol + j;
indx = row*Hpixels + col;
G += (ImgBW[indx] * Gauss[i + 2][j + 2]);
}
}
ImgGauss[MYpixIndex] = G / 159.00;
}
}
__device__
double Gx[3][3] = { { -1, 0, 1 },
{ -2, 0, 2 },
{ -1, 0, 1 } };
__device__
double Gy[3][3] = { { -1, -2, -1 },
{ 0, 0, 0 },
{ 1, 2, 1 } };
// Kernel that calculates Gradient, Theta from the Gauss image
// resulting image has a double type for each pixel position
__global__
void SobelKernel(double *ImgGrad, double *ImgTheta, double *ImgGauss, ui Hpixels, ui Vpixels)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
int row, col, indx, i, j;
double GX,GY;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
int MYrow = MYbid / BlkPerRow;
int MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYpixIndex = MYrow * Hpixels + MYcol;
if ((MYrow<1) || (MYrow>Vpixels - 2) || (MYcol<1) || (MYcol>Hpixels - 2)){
ImgGrad[MYpixIndex] = 0.0;
ImgTheta[MYpixIndex] = 0.0;
return;
}else{
GX = 0.0; GY = 0.0;
for (i = -1; i <= 1; i++){
for (j = -1; j <= 1; j++){
row = MYrow + i;
col = MYcol + j;
indx = row*Hpixels + col;
GX += (ImgGauss[indx] * Gx[i + 1][j + 1]);
GY += (ImgGauss[indx] * Gy[i + 1][j + 1]);
}
}
ImgGrad[MYpixIndex] = sqrt(GX*GX + GY*GY);
ImgTheta[MYpixIndex] = atan(GX / GY)*180.0 / PI;
}
}
// Kernel that calculates the threshold image from Gradient, Theta
// resulting image has an RGB for each pixel, same RGB for each pixel
__global__
void ThresholdKernel(uch *ImgResult, double *ImgGrad, double *ImgTheta, ui Hpixels, ui Vpixels, ui ThreshLo, ui ThreshHi)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
unsigned char PIXVAL;
double L, H, G, T;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
ui RowBytes = (Hpixels * 3 + 3) & (~3);
int MYrow = MYbid / BlkPerRow;
int MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYresultIndex = MYrow * RowBytes + 3 * MYcol;
ui MYpixIndex = MYrow * Hpixels + MYcol;
if ((MYrow<1) || (MYrow>Vpixels - 2) || (MYcol<1) || (MYcol>Hpixels - 2)){
ImgResult[MYresultIndex] = NOEDGE;
ImgResult[MYresultIndex + 1] = NOEDGE;
ImgResult[MYresultIndex + 2] = NOEDGE;
return;
}else{
L = (double)ThreshLo; H = (double)ThreshHi;
G = ImgGrad[MYpixIndex];
PIXVAL = NOEDGE;
if (G <= L){ // no edge
PIXVAL = NOEDGE;
}else if (G >= H){ // edge
PIXVAL = EDGE;
}else{
T = ImgTheta[MYpixIndex];
if ((T<-67.5) || (T>67.5)){
// Look at left and right: [row][col-1] and [row][col+1]
PIXVAL = ((ImgGrad[MYpixIndex - 1]>H) || (ImgGrad[MYpixIndex + 1]>H)) ? EDGE : NOEDGE;
}
else if ((T >= -22.5) && (T <= 22.5)){
// Look at top and bottom: [row-1][col] and [row+1][col]
PIXVAL = ((ImgGrad[MYpixIndex - Hpixels]>H) || (ImgGrad[MYpixIndex + Hpixels]>H)) ? EDGE : NOEDGE;
}
else if ((T>22.5) && (T <= 67.5)){
// Look at upper right, lower left: [row-1][col+1] and [row+1][col-1]
PIXVAL = ((ImgGrad[MYpixIndex - Hpixels + 1]>H) || (ImgGrad[MYpixIndex + Hpixels - 1]>H)) ? EDGE : NOEDGE;
}
else if ((T >= -67.5) && (T<-22.5)){
// Look at upper left, lower right: [row-1][col-1] and [row+1][col+1]
PIXVAL = ((ImgGrad[MYpixIndex - Hpixels - 1]>H) || (ImgGrad[MYpixIndex + Hpixels + 1]>H)) ? EDGE : NOEDGE;
}
}
ImgResult[MYresultIndex] = PIXVAL;
ImgResult[MYresultIndex + 1] = PIXVAL;
ImgResult[MYresultIndex + 2] = PIXVAL;
}
}
/*
// helper function that wraps CUDA API calls, reports any error and exits
void chkCUDAErr(cudaError_t error_id)
{
if (error_id != CUDA_SUCCESS){
printf("CUDA ERROR :::%\n", cudaGetErrorString(error_id));
exit(EXIT_FAILURE);
}
}
*/
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
// Write the 1D linear-memory stored image into file.
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
int main(int argc, char **argv)
{
// clock_t CPUStartTime, CPUEndTime, CPUElapsedTime;
// GPU code run times
float totalTime, totalKernelTime, tfrCPUtoGPU, tfrGPUtoCPU;
float kernelExecTimeBW, kernelExecTimeGauss, kernelExecTimeSobel, kernelExecTimeThreshold;
cudaError_t cudaStatus;
cudaEvent_t time1, time2, time2BW, time2Gauss, time2Sobel, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks;
ui GPUDataTfrBW, GPUDataTfrGauss, GPUDataTfrSobel, GPUDataTfrThresh,GPUDataTfrKernel, GPUDataTfrTotal;
cudaDeviceProp GPUprop;
void *GPUptr; // Pointer to the bulk-allocated GPU memory
ul GPUtotalBufferSize;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imedgeG");
switch (argc){
case 6: ThreshHi = atoi(argv[5]);
case 5: ThreshLo = atoi(argv[4]);
case 4: ThrPerBlk = atoi(argv[3]);
case 3: strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
break;
default: printf("\n\nUsage: %s InputFilename OutputFilename [ThrPerBlk] [ThreshLo] [ThreshHi]", ProgName);
printf("\n\nExample: %s Astronaut.bmp Output.bmp", ProgName);
printf("\n\nExample: %s Astronaut.bmp Output.bmp 256", ProgName);
printf("\n\nExample: %s Astronaut.bmp Output.bmp 256 50 100",ProgName);
exit(EXIT_FAILURE);
}
if ((ThrPerBlk < 32) || (ThrPerBlk > 1024)) {
printf("Invalid ThrPerBlk option '%u'. Must be between 32 and 1024. \n", ThrPerBlk);
exit(EXIT_FAILURE);
}
if ((ThreshLo<0) || (ThreshHi>255) || (ThreshLo>ThreshHi)){
printf("\nInvalid Thresholds: Threshold must be between [0...255] ...\n");
printf("\n\nNothing executed ... Exiting ...\n\n");
exit(EXIT_FAILURE);
}
// Create CPU memory to store the input and output images
TheImg = ReadBMPlin(InputFileName); // Read the input image if memory can be allocated
if (TheImg == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
CopyImg = (uch *)malloc(IMAGESIZE);
if (CopyImg == NULL){
printf("Cannot allocate memory for the input image...\n");
free(TheImg);
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
cudaGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
goto EXITERROR;
}
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto EXITERROR;
}
cudaGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui) GPUprop.maxGridSize[0] * (ui) GPUprop.maxGridSize[1] * (ui )GPUprop.maxGridSize[2]/1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks>=5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks>=5) ? 'M':'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
cudaEventCreate(&time1); cudaEventCreate(&time2);
cudaEventCreate(&time2BW); cudaEventCreate(&time2Gauss); cudaEventCreate(&time2Sobel);
cudaEventCreate(&time3); cudaEventCreate(&time4);
cudaEventRecord(time1, 0); // Time stamp at the start of the GPU transfer
// Allocate GPU buffer for the input and output images and the imtermediate results
GPUtotalBufferSize = 4 * sizeof(double)*IMAGEPIX + 2 * sizeof(uch)*IMAGESIZE;
cudaStatus = cudaMalloc((void**)&GPUptr, GPUtotalBufferSize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed! Can't allocate GPU memory");
goto EXITERROR;
}
GPUImg = (uch *)GPUptr;
GPUResultImg = GPUImg + IMAGESIZE;
GPUBWImg = (double *)(GPUResultImg + IMAGESIZE);
GPUGaussImg = GPUBWImg + IMAGEPIX;
GPUGradient = GPUGaussImg + IMAGEPIX;
GPUTheta = GPUGradient + IMAGEPIX;
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(GPUImg, TheImg, IMAGESIZE, cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy CPU to GPU failed!");
goto EXITCUDAERROR;
}
cudaEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
//dim3 dimBlock(ThrPerBlk);
//dim3 dimGrid(ip.Hpixels*BlkPerRow);
BlkPerRow = CEIL(ip.Hpixels, ThrPerBlk);
NumBlocks = IPV*BlkPerRow;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
BWKernel <<< NumBlocks, ThrPerBlk >>> (GPUBWImg, GPUImg, ip.Hpixels);
if ((cudaStatus = cudaDeviceSynchronize()) != cudaSuccess) goto KERNELERROR;
cudaEventRecord(time2BW, 0); // Time stamp after BW image calculation
GPUDataTfrBW = sizeof(double)*IMAGEPIX + sizeof(uch)*IMAGESIZE;
GaussKernel <<< NumBlocks, ThrPerBlk >>> (GPUGaussImg, GPUBWImg, ip.Hpixels, ip.Vpixels);
if ((cudaStatus = cudaDeviceSynchronize()) != cudaSuccess) goto KERNELERROR;
cudaEventRecord(time2Gauss, 0); // Time stamp after Gauss image calculation
GPUDataTfrGauss = 2*sizeof(double)*IMAGEPIX;
SobelKernel <<< NumBlocks, ThrPerBlk >>> (GPUGradient, GPUTheta, GPUGaussImg, ip.Hpixels, ip.Vpixels);
if ((cudaStatus = cudaDeviceSynchronize()) != cudaSuccess) goto KERNELERROR;
cudaEventRecord(time2Sobel, 0); // Time stamp after Gradient, Theta computation
GPUDataTfrSobel = 3 * sizeof(double)*IMAGEPIX;
ThresholdKernel <<< NumBlocks, ThrPerBlk >>> (GPUResultImg, GPUGradient, GPUTheta, ip.Hpixels, ip.Vpixels, ThreshLo, ThreshHi);
if ((cudaStatus = cudaDeviceSynchronize()) != cudaSuccess) goto KERNELERROR;
GPUDataTfrThresh = sizeof(double)*IMAGEPIX + sizeof(uch)*IMAGESIZE;
GPUDataTfrKernel = GPUDataTfrBW + GPUDataTfrGauss + GPUDataTfrSobel + GPUDataTfrThresh;
GPUDataTfrTotal = GPUDataTfrKernel + 2 * IMAGESIZE;
cudaEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = cudaMemcpy(CopyImg, GPUResultImg, IMAGESIZE, cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy GPU to CPU failed!");
goto EXITCUDAERROR;
}
cudaEventRecord(time4, 0);
cudaEventSynchronize(time1); cudaEventSynchronize(time2);
cudaEventSynchronize(time2BW); cudaEventSynchronize(time2Gauss); cudaEventSynchronize(time2Sobel);
cudaEventSynchronize(time3); cudaEventSynchronize(time4);
cudaEventElapsedTime(&totalTime, time1, time4);
cudaEventElapsedTime(&tfrCPUtoGPU, time1, time2);
cudaEventElapsedTime(&kernelExecTimeBW, time2, time2BW);
cudaEventElapsedTime(&kernelExecTimeGauss, time2BW, time2Gauss);
cudaEventElapsedTime(&kernelExecTimeSobel, time2Gauss, time2Sobel);
cudaEventElapsedTime(&kernelExecTimeThreshold, time2Sobel, time3);
cudaEventElapsedTime(&tfrGPUtoCPU, time3, time4);
totalKernelTime = kernelExecTimeBW + kernelExecTimeGauss + kernelExecTimeSobel + kernelExecTimeThreshold;
cudaStatus = cudaDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImg);
free(CopyImg);
exit(EXIT_FAILURE);
}
WriteBMPlin(CopyImg, OutputFileName); // Write the flipped image back to disk
printf("\n\n----------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("----------------------------------------------------------------------------\n");
printf("%s %s %s %u %d %d [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName, ThrPerBlk, ThreshLo, ThreshHi, NumBlocks, BlkPerRow);
printf("----------------------------------------------------------------------------\n");
printf(" CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE,tfrCPUtoGPU));
printf(" GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("----------------------------------------------------------------------------\n");
printf(" BW Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeBW, DATAMB(GPUDataTfrBW), DATABW(GPUDataTfrBW, kernelExecTimeBW));
printf(" Gauss Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeGauss, DATAMB(GPUDataTfrGauss), DATABW(GPUDataTfrGauss, kernelExecTimeGauss));
printf(" Sobel Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeSobel, DATAMB(GPUDataTfrSobel), DATABW(GPUDataTfrSobel, kernelExecTimeSobel));
printf("Threshold Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeThreshold, DATAMB(GPUDataTfrThresh), DATABW(GPUDataTfrThresh, kernelExecTimeThreshold));
printf("----------------------------------------------------------------------------\n");
printf(" Total Kernel-only time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", totalKernelTime, DATAMB(GPUDataTfrKernel), DATABW(GPUDataTfrKernel, totalKernelTime));
printf(" Total time with I/O included =%7.2f ms ... %4d MB ... %6.2f GB/s\n", totalTime, DATAMB(GPUDataTfrTotal), DATABW(GPUDataTfrTotal, totalTime));
printf("----------------------------------------------------------------------------\n");
// Deallocate CPU, GPU memory and destroy events.
cudaFree(GPUptr);
cudaEventDestroy(time1); cudaEventDestroy(time2);
cudaEventDestroy(time2BW); cudaEventDestroy(time2Gauss); cudaEventDestroy(time2Sobel);
cudaEventDestroy(time3); cudaEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
free(TheImg);
free(CopyImg);
exit(EXIT_FAILURE);
}
free(TheImg);
free(CopyImg);
return(EXIT_SUCCESS);
KERNELERROR:
fprintf(stderr, "\n\ncudaDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
EXITCUDAERROR:
cudaFree(GPUptr);
EXITERROR:
free(TheImg);
free(CopyImg);
return(EXIT_FAILURE);
} | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <iostream>
#include <ctype.h>
#include "hip/hip_runtime.h"
#define CEIL(a,b) ((a+b-1)/b)
#define PI 3.1415926
#define EDGE 0
#define NOEDGE 255
#define DATAMB(bytes) (bytes/1024/1024)
#define DATABW(bytes,timems) ((float)bytes/(timems * 1.024*1024.0*1024.0))
typedef unsigned char uch;
typedef unsigned long ul;
typedef unsigned int ui;
uch *TheImg, *CopyImg; // Where images are stored in CPU
int ThreshLo=50, ThreshHi=100; // "Edge" vs. "No Edge" thresholds
// Where images and temporary results are stored in GPU
uch *GPUImg, *GPUResultImg;
double *GPUBWImg, *GPUGaussImg, *GPUGradient, *GPUTheta;
struct ImgProp{
ui Hpixels;
ui Vpixels;
uch HeaderInfo[54];
ul Hbytes;
} ip;
#define IPHB ip.Hbytes
#define IPH ip.Hpixels
#define IPV ip.Vpixels
#define IMAGESIZE (IPHB*IPV)
#define IMAGEPIX (IPH*IPV)
// Kernel that calculates a B&W image from an RGB image
// resulting image has a double type for each pixel position
__global__
void BWKernel(double *ImgBW, uch *ImgGPU, ui Hpixels)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
double R, G, B;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
ui RowBytes = (Hpixels * 3 + 3) & (~3);
ui MYrow = MYbid / BlkPerRow;
ui MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYsrcIndex = MYrow * RowBytes + 3 * MYcol;
ui MYpixIndex = MYrow * Hpixels + MYcol;
B = (double)ImgGPU[MYsrcIndex];
G = (double)ImgGPU[MYsrcIndex + 1];
R = (double)ImgGPU[MYsrcIndex + 2];
ImgBW[MYpixIndex] = (R+G+B)/3.0;
}
__device__
double Gauss[5][5] = { { 2, 4, 5, 4, 2 },
{ 4, 9, 12, 9, 4 },
{ 5, 12, 15, 12, 5 },
{ 4, 9, 12, 9, 4 },
{ 2, 4, 5, 4, 2 } };
// Kernel that calculates a Gauss image from the B&W image
// resulting image has a double type for each pixel position
__global__
void GaussKernel(double *ImgGauss, double *ImgBW, ui Hpixels, ui Vpixels)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
int row, col, indx, i, j;
double G=0.00;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
int MYrow = MYbid / BlkPerRow;
int MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYpixIndex = MYrow * Hpixels + MYcol;
if ((MYrow<2) || (MYrow>Vpixels - 3) || (MYcol<2) || (MYcol>Hpixels - 3)){
ImgGauss[MYpixIndex] = 0.0;
return;
}else{
G = 0.0;
for (i = -2; i <= 2; i++){
for (j = -2; j <= 2; j++){
row = MYrow + i;
col = MYcol + j;
indx = row*Hpixels + col;
G += (ImgBW[indx] * Gauss[i + 2][j + 2]);
}
}
ImgGauss[MYpixIndex] = G / 159.00;
}
}
__device__
double Gx[3][3] = { { -1, 0, 1 },
{ -2, 0, 2 },
{ -1, 0, 1 } };
__device__
double Gy[3][3] = { { -1, -2, -1 },
{ 0, 0, 0 },
{ 1, 2, 1 } };
// Kernel that calculates Gradient, Theta from the Gauss image
// resulting image has a double type for each pixel position
__global__
void SobelKernel(double *ImgGrad, double *ImgTheta, double *ImgGauss, ui Hpixels, ui Vpixels)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
int row, col, indx, i, j;
double GX,GY;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
int MYrow = MYbid / BlkPerRow;
int MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYpixIndex = MYrow * Hpixels + MYcol;
if ((MYrow<1) || (MYrow>Vpixels - 2) || (MYcol<1) || (MYcol>Hpixels - 2)){
ImgGrad[MYpixIndex] = 0.0;
ImgTheta[MYpixIndex] = 0.0;
return;
}else{
GX = 0.0; GY = 0.0;
for (i = -1; i <= 1; i++){
for (j = -1; j <= 1; j++){
row = MYrow + i;
col = MYcol + j;
indx = row*Hpixels + col;
GX += (ImgGauss[indx] * Gx[i + 1][j + 1]);
GY += (ImgGauss[indx] * Gy[i + 1][j + 1]);
}
}
ImgGrad[MYpixIndex] = sqrt(GX*GX + GY*GY);
ImgTheta[MYpixIndex] = atan(GX / GY)*180.0 / PI;
}
}
// Kernel that calculates the threshold image from Gradient, Theta
// resulting image has an RGB for each pixel, same RGB for each pixel
__global__
void ThresholdKernel(uch *ImgResult, double *ImgGrad, double *ImgTheta, ui Hpixels, ui Vpixels, ui ThreshLo, ui ThreshHi)
{
ui ThrPerBlk = blockDim.x;
ui MYbid = blockIdx.x;
ui MYtid = threadIdx.x;
ui MYgtid = ThrPerBlk * MYbid + MYtid;
unsigned char PIXVAL;
double L, H, G, T;
//ui NumBlocks = gridDim.x;
ui BlkPerRow = CEIL(Hpixels, ThrPerBlk);
ui RowBytes = (Hpixels * 3 + 3) & (~3);
int MYrow = MYbid / BlkPerRow;
int MYcol = MYgtid - MYrow*BlkPerRow*ThrPerBlk;
if (MYcol >= Hpixels) return; // col out of range
ui MYresultIndex = MYrow * RowBytes + 3 * MYcol;
ui MYpixIndex = MYrow * Hpixels + MYcol;
if ((MYrow<1) || (MYrow>Vpixels - 2) || (MYcol<1) || (MYcol>Hpixels - 2)){
ImgResult[MYresultIndex] = NOEDGE;
ImgResult[MYresultIndex + 1] = NOEDGE;
ImgResult[MYresultIndex + 2] = NOEDGE;
return;
}else{
L = (double)ThreshLo; H = (double)ThreshHi;
G = ImgGrad[MYpixIndex];
PIXVAL = NOEDGE;
if (G <= L){ // no edge
PIXVAL = NOEDGE;
}else if (G >= H){ // edge
PIXVAL = EDGE;
}else{
T = ImgTheta[MYpixIndex];
if ((T<-67.5) || (T>67.5)){
// Look at left and right: [row][col-1] and [row][col+1]
PIXVAL = ((ImgGrad[MYpixIndex - 1]>H) || (ImgGrad[MYpixIndex + 1]>H)) ? EDGE : NOEDGE;
}
else if ((T >= -22.5) && (T <= 22.5)){
// Look at top and bottom: [row-1][col] and [row+1][col]
PIXVAL = ((ImgGrad[MYpixIndex - Hpixels]>H) || (ImgGrad[MYpixIndex + Hpixels]>H)) ? EDGE : NOEDGE;
}
else if ((T>22.5) && (T <= 67.5)){
// Look at upper right, lower left: [row-1][col+1] and [row+1][col-1]
PIXVAL = ((ImgGrad[MYpixIndex - Hpixels + 1]>H) || (ImgGrad[MYpixIndex + Hpixels - 1]>H)) ? EDGE : NOEDGE;
}
else if ((T >= -67.5) && (T<-22.5)){
// Look at upper left, lower right: [row-1][col-1] and [row+1][col+1]
PIXVAL = ((ImgGrad[MYpixIndex - Hpixels - 1]>H) || (ImgGrad[MYpixIndex + Hpixels + 1]>H)) ? EDGE : NOEDGE;
}
}
ImgResult[MYresultIndex] = PIXVAL;
ImgResult[MYresultIndex + 1] = PIXVAL;
ImgResult[MYresultIndex + 2] = PIXVAL;
}
}
/*
// helper function that wraps CUDA API calls, reports any error and exits
void chkCUDAErr(cudaError_t error_id)
{
if (error_id != CUDA_SUCCESS){
printf("CUDA ERROR :::%\n", cudaGetErrorString(error_id));
exit(EXIT_FAILURE);
}
}
*/
// Read a 24-bit/pixel BMP file into a 1D linear array.
// Allocate memory to store the 1D image and return its pointer.
uch *ReadBMPlin(char* fn)
{
static uch *Img;
FILE* f = fopen(fn, "rb");
if (f == NULL){ printf("\n\n%s NOT FOUND\n\n", fn); exit(EXIT_FAILURE); }
uch HeaderInfo[54];
fread(HeaderInfo, sizeof(uch), 54, f); // read the 54-byte header
// extract image height and width from header
int width = *(int*)&HeaderInfo[18]; ip.Hpixels = width;
int height = *(int*)&HeaderInfo[22]; ip.Vpixels = height;
int RowBytes = (width * 3 + 3) & (~3); ip.Hbytes = RowBytes;
//save header for re-use
memcpy(ip.HeaderInfo, HeaderInfo,54);
printf("\n Input File name: %17s (%u x %u) File Size=%u", fn,
ip.Hpixels, ip.Vpixels, IMAGESIZE);
// allocate memory to store the main image (1 Dimensional array)
Img = (uch *)malloc(IMAGESIZE);
if (Img == NULL) return Img; // Cannot allocate memory
// read the image from disk
fread(Img, sizeof(uch), IMAGESIZE, f);
fclose(f);
return Img;
}
// Write the 1D linear-memory stored image into file.
void WriteBMPlin(uch *Img, char* fn)
{
FILE* f = fopen(fn, "wb");
if (f == NULL){ printf("\n\nFILE CREATION ERROR: %s\n\n", fn); exit(1); }
//write header
fwrite(ip.HeaderInfo, sizeof(uch), 54, f);
//write data
fwrite(Img, sizeof(uch), IMAGESIZE, f);
printf("\nOutput File name: %17s (%u x %u) File Size=%u", fn, ip.Hpixels, ip.Vpixels, IMAGESIZE);
fclose(f);
}
int main(int argc, char **argv)
{
// clock_t CPUStartTime, CPUEndTime, CPUElapsedTime;
// GPU code run times
float totalTime, totalKernelTime, tfrCPUtoGPU, tfrGPUtoCPU;
float kernelExecTimeBW, kernelExecTimeGauss, kernelExecTimeSobel, kernelExecTimeThreshold;
hipError_t cudaStatus;
hipEvent_t time1, time2, time2BW, time2Gauss, time2Sobel, time3, time4;
char InputFileName[255], OutputFileName[255], ProgName[255];
ui BlkPerRow, ThrPerBlk=256, NumBlocks;
ui GPUDataTfrBW, GPUDataTfrGauss, GPUDataTfrSobel, GPUDataTfrThresh,GPUDataTfrKernel, GPUDataTfrTotal;
hipDeviceProp_t GPUprop;
void *GPUptr; // Pointer to the bulk-allocated GPU memory
ul GPUtotalBufferSize;
ul SupportedKBlocks, SupportedMBlocks, MaxThrPerBlk; char SupportedBlocks[100];
strcpy(ProgName, "imedgeG");
switch (argc){
case 6: ThreshHi = atoi(argv[5]);
case 5: ThreshLo = atoi(argv[4]);
case 4: ThrPerBlk = atoi(argv[3]);
case 3: strcpy(InputFileName, argv[1]);
strcpy(OutputFileName, argv[2]);
break;
default: printf("\n\nUsage: %s InputFilename OutputFilename [ThrPerBlk] [ThreshLo] [ThreshHi]", ProgName);
printf("\n\nExample: %s Astronaut.bmp Output.bmp", ProgName);
printf("\n\nExample: %s Astronaut.bmp Output.bmp 256", ProgName);
printf("\n\nExample: %s Astronaut.bmp Output.bmp 256 50 100",ProgName);
exit(EXIT_FAILURE);
}
if ((ThrPerBlk < 32) || (ThrPerBlk > 1024)) {
printf("Invalid ThrPerBlk option '%u'. Must be between 32 and 1024. \n", ThrPerBlk);
exit(EXIT_FAILURE);
}
if ((ThreshLo<0) || (ThreshHi>255) || (ThreshLo>ThreshHi)){
printf("\nInvalid Thresholds: Threshold must be between [0...255] ...\n");
printf("\n\nNothing executed ... Exiting ...\n\n");
exit(EXIT_FAILURE);
}
// Create CPU memory to store the input and output images
TheImg = ReadBMPlin(InputFileName); // Read the input image if memory can be allocated
if (TheImg == NULL){
printf("Cannot allocate memory for the input image...\n");
exit(EXIT_FAILURE);
}
CopyImg = (uch *)malloc(IMAGESIZE);
if (CopyImg == NULL){
printf("Cannot allocate memory for the input image...\n");
free(TheImg);
exit(EXIT_FAILURE);
}
// Choose which GPU to run on, change this on a multi-GPU system.
int NumGPUs = 0;
hipGetDeviceCount(&NumGPUs);
if (NumGPUs == 0){
printf("\nNo CUDA Device is available\n");
goto EXITERROR;
}
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto EXITERROR;
}
hipGetDeviceProperties(&GPUprop, 0);
SupportedKBlocks = (ui) GPUprop.maxGridSize[0] * (ui) GPUprop.maxGridSize[1] * (ui )GPUprop.maxGridSize[2]/1024;
SupportedMBlocks = SupportedKBlocks / 1024;
sprintf(SupportedBlocks, "%u %c", (SupportedMBlocks>=5) ? SupportedMBlocks : SupportedKBlocks, (SupportedMBlocks>=5) ? 'M':'K');
MaxThrPerBlk = (ui)GPUprop.maxThreadsPerBlock;
hipEventCreate(&time1); hipEventCreate(&time2);
hipEventCreate(&time2BW); hipEventCreate(&time2Gauss); hipEventCreate(&time2Sobel);
hipEventCreate(&time3); hipEventCreate(&time4);
hipEventRecord(time1, 0); // Time stamp at the start of the GPU transfer
// Allocate GPU buffer for the input and output images and the imtermediate results
GPUtotalBufferSize = 4 * sizeof(double)*IMAGEPIX + 2 * sizeof(uch)*IMAGESIZE;
cudaStatus = hipMalloc((void**)&GPUptr, GPUtotalBufferSize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed! Can't allocate GPU memory");
goto EXITERROR;
}
GPUImg = (uch *)GPUptr;
GPUResultImg = GPUImg + IMAGESIZE;
GPUBWImg = (double *)(GPUResultImg + IMAGESIZE);
GPUGaussImg = GPUBWImg + IMAGEPIX;
GPUGradient = GPUGaussImg + IMAGEPIX;
GPUTheta = GPUGradient + IMAGEPIX;
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(GPUImg, TheImg, IMAGESIZE, hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy CPU to GPU failed!");
goto EXITCUDAERROR;
}
hipEventRecord(time2, 0); // Time stamp after the CPU --> GPU tfr is done
//dim3 dimBlock(ThrPerBlk);
//dim3 dimGrid(ip.Hpixels*BlkPerRow);
BlkPerRow = CEIL(ip.Hpixels, ThrPerBlk);
NumBlocks = IPV*BlkPerRow;
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
BWKernel <<< NumBlocks, ThrPerBlk >>> (GPUBWImg, GPUImg, ip.Hpixels);
if ((cudaStatus = hipDeviceSynchronize()) != hipSuccess) goto KERNELERROR;
hipEventRecord(time2BW, 0); // Time stamp after BW image calculation
GPUDataTfrBW = sizeof(double)*IMAGEPIX + sizeof(uch)*IMAGESIZE;
GaussKernel <<< NumBlocks, ThrPerBlk >>> (GPUGaussImg, GPUBWImg, ip.Hpixels, ip.Vpixels);
if ((cudaStatus = hipDeviceSynchronize()) != hipSuccess) goto KERNELERROR;
hipEventRecord(time2Gauss, 0); // Time stamp after Gauss image calculation
GPUDataTfrGauss = 2*sizeof(double)*IMAGEPIX;
SobelKernel <<< NumBlocks, ThrPerBlk >>> (GPUGradient, GPUTheta, GPUGaussImg, ip.Hpixels, ip.Vpixels);
if ((cudaStatus = hipDeviceSynchronize()) != hipSuccess) goto KERNELERROR;
hipEventRecord(time2Sobel, 0); // Time stamp after Gradient, Theta computation
GPUDataTfrSobel = 3 * sizeof(double)*IMAGEPIX;
ThresholdKernel <<< NumBlocks, ThrPerBlk >>> (GPUResultImg, GPUGradient, GPUTheta, ip.Hpixels, ip.Vpixels, ThreshLo, ThreshHi);
if ((cudaStatus = hipDeviceSynchronize()) != hipSuccess) goto KERNELERROR;
GPUDataTfrThresh = sizeof(double)*IMAGEPIX + sizeof(uch)*IMAGESIZE;
GPUDataTfrKernel = GPUDataTfrBW + GPUDataTfrGauss + GPUDataTfrSobel + GPUDataTfrThresh;
GPUDataTfrTotal = GPUDataTfrKernel + 2 * IMAGESIZE;
hipEventRecord(time3, 0);
// Copy output (results) from GPU buffer to host (CPU) memory.
cudaStatus = hipMemcpy(CopyImg, GPUResultImg, IMAGESIZE, hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy GPU to CPU failed!");
goto EXITCUDAERROR;
}
hipEventRecord(time4, 0);
hipEventSynchronize(time1); hipEventSynchronize(time2);
hipEventSynchronize(time2BW); hipEventSynchronize(time2Gauss); hipEventSynchronize(time2Sobel);
hipEventSynchronize(time3); hipEventSynchronize(time4);
hipEventElapsedTime(&totalTime, time1, time4);
hipEventElapsedTime(&tfrCPUtoGPU, time1, time2);
hipEventElapsedTime(&kernelExecTimeBW, time2, time2BW);
hipEventElapsedTime(&kernelExecTimeGauss, time2BW, time2Gauss);
hipEventElapsedTime(&kernelExecTimeSobel, time2Gauss, time2Sobel);
hipEventElapsedTime(&kernelExecTimeThreshold, time2Sobel, time3);
hipEventElapsedTime(&tfrGPUtoCPU, time3, time4);
totalKernelTime = kernelExecTimeBW + kernelExecTimeGauss + kernelExecTimeSobel + kernelExecTimeThreshold;
cudaStatus = hipDeviceSynchronize();
//checkError(cudaGetLastError()); // screen for errors in kernel launches
if (cudaStatus != hipSuccess) {
fprintf(stderr, "\n Program failed after cudaDeviceSynchronize()!");
free(TheImg);
free(CopyImg);
exit(EXIT_FAILURE);
}
WriteBMPlin(CopyImg, OutputFileName); // Write the flipped image back to disk
printf("\n\n----------------------------------------------------------------------------\n");
printf("%s ComputeCapab=%d.%d [max %s blocks; %d thr/blk] \n",
GPUprop.name, GPUprop.major, GPUprop.minor, SupportedBlocks, MaxThrPerBlk);
printf("----------------------------------------------------------------------------\n");
printf("%s %s %s %u %d %d [%u BLOCKS, %u BLOCKS/ROW]\n", ProgName, InputFileName, OutputFileName, ThrPerBlk, ThreshLo, ThreshHi, NumBlocks, BlkPerRow);
printf("----------------------------------------------------------------------------\n");
printf(" CPU->GPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrCPUtoGPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE,tfrCPUtoGPU));
printf(" GPU->CPU Transfer =%7.2f ms ... %4d MB ... %6.2f GB/s\n", tfrGPUtoCPU, DATAMB(IMAGESIZE), DATABW(IMAGESIZE, tfrGPUtoCPU));
printf("----------------------------------------------------------------------------\n");
printf(" BW Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeBW, DATAMB(GPUDataTfrBW), DATABW(GPUDataTfrBW, kernelExecTimeBW));
printf(" Gauss Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeGauss, DATAMB(GPUDataTfrGauss), DATABW(GPUDataTfrGauss, kernelExecTimeGauss));
printf(" Sobel Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeSobel, DATAMB(GPUDataTfrSobel), DATABW(GPUDataTfrSobel, kernelExecTimeSobel));
printf("Threshold Kernel Execution Time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", kernelExecTimeThreshold, DATAMB(GPUDataTfrThresh), DATABW(GPUDataTfrThresh, kernelExecTimeThreshold));
printf("----------------------------------------------------------------------------\n");
printf(" Total Kernel-only time =%7.2f ms ... %4d MB ... %6.2f GB/s\n", totalKernelTime, DATAMB(GPUDataTfrKernel), DATABW(GPUDataTfrKernel, totalKernelTime));
printf(" Total time with I/O included =%7.2f ms ... %4d MB ... %6.2f GB/s\n", totalTime, DATAMB(GPUDataTfrTotal), DATABW(GPUDataTfrTotal, totalTime));
printf("----------------------------------------------------------------------------\n");
// Deallocate CPU, GPU memory and destroy events.
hipFree(GPUptr);
hipEventDestroy(time1); hipEventDestroy(time2);
hipEventDestroy(time2BW); hipEventDestroy(time2Gauss); hipEventDestroy(time2Sobel);
hipEventDestroy(time3); hipEventDestroy(time4);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Parallel Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
free(TheImg);
free(CopyImg);
exit(EXIT_FAILURE);
}
free(TheImg);
free(CopyImg);
return(EXIT_SUCCESS);
KERNELERROR:
fprintf(stderr, "\n\nhipDeviceSynchronize returned error code %d after launching the kernel!\n", cudaStatus);
EXITCUDAERROR:
hipFree(GPUptr);
EXITERROR:
free(TheImg);
free(CopyImg);
return(EXIT_FAILURE);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdlib>
#include <assert.h>
#include <sys/time.h>
const int B_SIZE = 1024;
double timer() {
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-06);
}
__global__ void transpose(double *M, double *M_t, int n) {
int Idx = blockIdx.x * B_SIZE + threadIdx.x;
if(Idx < n*n) {
int x = Idx % n;
int y = Idx / n;
int T_index = x * n + y;
M_t[T_index] = M[Idx];
}
}
void print(double *M, int n) {
std::cout << "Print matrix: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << M[i * n + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char ** argv) {
assert(argc == 2);
int n = atoi(argv[1]);
size_t size = n * n * sizeof(double);
double *M = (double*)malloc(size);
//init
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M[i * n + j] = i / j + j % i;
}
}
double *M_t = (double*)malloc(size);
double t1 = timer();
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M_t[j * n + i] = M[i * n + j];
}
}
double t2 = timer();
std::cout << "Cpu time: " << t2-t1 << std::endl;
// print(M, n);
// print(M_t, n);
dim3 block(B_SIZE);
dim3 grid((n * n - 1) / B_SIZE + 1);
double *M_dev, *M_t_dev;
cudaMalloc(&M_dev, size);
cudaMalloc(&M_t_dev, size);
cudaMemcpy(M_dev, M, size, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
transpose<<<grid, block>>>(M_dev, M_t_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(M_t, M_t_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Gpu time is: " << ms << std::endl;
// print(M_t, n);
bool check = true;
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
check *= (M[i*n+j] == M_t[j*n+i]);
}
}
if (check) std::cout << "CHECK PASSED!" << std::endl;
else std::cout << "CHECK FAILED!" << std::endl;
free(M);
free(M_t);
cudaFree(M_dev);
cudaFree(M_t_dev);
return 0;
} | code for sm_80
Function : _Z9transposePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, 0x400, R3 ; /* 0x0000040000007824 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R10, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e020a */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fc80000000000 */
/*00d0*/ I2F.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0130*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0150*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0160*/ LOP3.LUT R4, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000047a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f26270 */
/*0180*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a05 */
/*01a0*/ IMAD R6, R7, R6, R8 ; /* 0x0000000607067224 */
/* 0x000fca00078e0208 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IADD3 R6, R6, -R7.reuse, RZ ; /* 0x800000070606a210 */
/* 0x080fe40007ffe0ff */
/*01d0*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f06070 */
/*01f0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fd60003f45270 */
/*0200*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0220*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff05aa12 */
/* 0x000fc800078e33ff */
/*0230*/ IADD3 R7, -R5, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x000fca0007ffe1ff */
/*0240*/ IMAD R0, R7, c[0x0][0x170], R0 ; /* 0x00005c0007007a24 */
/* 0x000fc800078e0200 */
/*0250*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0260*/ IMAD.WIDE R4, R5, R10, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e020a */
/*0270*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdlib>
#include <assert.h>
#include <sys/time.h>
const int B_SIZE = 1024;
double timer() {
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-06);
}
__global__ void transpose(double *M, double *M_t, int n) {
int Idx = blockIdx.x * B_SIZE + threadIdx.x;
if(Idx < n*n) {
int x = Idx % n;
int y = Idx / n;
int T_index = x * n + y;
M_t[T_index] = M[Idx];
}
}
void print(double *M, int n) {
std::cout << "Print matrix: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << M[i * n + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char ** argv) {
assert(argc == 2);
int n = atoi(argv[1]);
size_t size = n * n * sizeof(double);
double *M = (double*)malloc(size);
//init
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M[i * n + j] = i / j + j % i;
}
}
double *M_t = (double*)malloc(size);
double t1 = timer();
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M_t[j * n + i] = M[i * n + j];
}
}
double t2 = timer();
std::cout << "Cpu time: " << t2-t1 << std::endl;
// print(M, n);
// print(M_t, n);
dim3 block(B_SIZE);
dim3 grid((n * n - 1) / B_SIZE + 1);
double *M_dev, *M_t_dev;
cudaMalloc(&M_dev, size);
cudaMalloc(&M_t_dev, size);
cudaMemcpy(M_dev, M, size, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
transpose<<<grid, block>>>(M_dev, M_t_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(M_t, M_t_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Gpu time is: " << ms << std::endl;
// print(M_t, n);
bool check = true;
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
check *= (M[i*n+j] == M_t[j*n+i]);
}
}
if (check) std::cout << "CHECK PASSED!" << std::endl;
else std::cout << "CHECK FAILED!" << std::endl;
free(M);
free(M_t);
cudaFree(M_dev);
cudaFree(M_t_dev);
return 0;
} | .file "tmpxft_0012f4bb_00000000-6_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5timerv
.type _Z5timerv, @function
_Z5timerv:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5timerv, .-_Z5timerv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Print matrix: \n"
.LC2:
.string " "
.text
.globl _Z5printPdi
.type _Z5printPdi, @function
_Z5printPdi:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movl %esi, 4(%rsp)
movl $15, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %ebx, %ebx
jle .L7
movslq %ebx, %rax
leaq 0(,%rax,8), %r15
addq %r15, %rbp
negq %rax
salq $3, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq .LC2(%rip), %r13
jmp .L9
.L16:
call _ZSt16__throw_bad_castv@PLT
.L12:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L13:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
je .L7
.L9:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L10:
movsd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L10
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L16
cmpb $0, 56(%rbx)
je .L12
movzbl 67(%rbx), %esi
jmp .L13
.L7:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z5printPdi, .-_Z5printPdi
.globl _Z31__device_stub__Z9transposePdS_iPdS_i
.type _Z31__device_stub__Z9transposePdS_iPdS_i, @function
_Z31__device_stub__Z9transposePdS_iPdS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z31__device_stub__Z9transposePdS_iPdS_i, .-_Z31__device_stub__Z9transposePdS_iPdS_i
.globl _Z9transposePdS_i
.type _Z9transposePdS_i, @function
_Z9transposePdS_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9transposePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9transposePdS_i, .-_Z9transposePdS_i
.section .rodata.str1.1
.LC3:
.string "Cpu time: "
.LC5:
.string "Gpu time is: "
.LC6:
.string "CHECK PASSED!"
.LC7:
.string "CHECK FAILED!"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r12d
imull %eax, %eax
movl %eax, 12(%rsp)
movslq %eax, %r14
salq $3, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
testl %r13d, %r13d
jle .L26
movslq %r13d, %rbx
salq $3, %rbx
movq %rax, %r9
movl $0, %edi
leal -1(%r13), %ebp
.L27:
movl $0, %esi
.L28:
movl %edi, %eax
cltd
idivl %esi
movl %eax, %r8d
movl %esi, %eax
cltd
idivl %edi
addl %edx, %r8d
pxor %xmm0, %xmm0
cvtsi2sdl %r8d, %xmm0
movsd %xmm0, (%r9,%rsi,8)
movq %rsi, %rax
addq $1, %rsi
cmpq %rbp, %rax
jne .L28
addl $1, %edi
addq %rbx, %r9
cmpl %r12d, %edi
jne .L27
movq %r14, %rdi
call malloc@PLT
movq %rax, (%rsp)
call _Z5timerv
movsd %xmm0, 16(%rsp)
movq (%rsp), %r8
leaq 8(%r15,%rbp,8), %rcx
movl $0, %edi
notq %rbp
leaq 0(,%rbp,8), %rsi
.L30:
leaq (%rsi,%rcx), %rax
movq %r8, %rdx
.L31:
movsd (%rax), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
addq %rbx, %rdx
cmpq %rcx, %rax
jne .L31
addl $1, %edi
addq $8, %r8
addq %rbx, %rcx
cmpl %r12d, %edi
jne .L30
.L32:
call _Z5timerv
movsd %xmm0, 24(%rsp)
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 24(%rsp), %xmm0
subsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl 12(%rsp), %ebx
leal 1022(%rbx), %eax
subl $1, %ebx
cmovns %ebx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L33:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 56(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r13d, %r13d
jle .L34
movq %rbx, %r11
movslq %r13d, %r8
salq $3, %r8
leal -1(%r13), %ebx
leaq 8(%r15,%rbx,8), %rdi
movl $0, %r10d
movl $1, %esi
notq %rbx
salq $3, %rbx
movl $0, %r9d
.L35:
leaq (%rbx,%rdi), %rax
movq %r11, %rcx
.L36:
movsd (%rax), %xmm0
ucomisd (%rcx), %xmm0
setnp %dl
cmovne %r9d, %edx
andl %edx, %esi
addq $8, %rax
addq %r8, %rcx
cmpq %rdi, %rax
jne .L36
addl $1, %r10d
addq $8, %r11
addq %r8, %rdi
cmpl %r12d, %r10d
jne .L35
testb %sil, %sil
jne .L34
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L39
.L46:
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z31__device_stub__Z9transposePdS_iPdS_i
jmp .L33
.L34:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L39:
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %r14, %rdi
call malloc@PLT
movq %rax, (%rsp)
call _Z5timerv
movsd %xmm0, 16(%rsp)
jmp .L32
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9transposePdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cstdlib>
#include <assert.h>
#include <sys/time.h>
const int B_SIZE = 1024;
double timer() {
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-06);
}
__global__ void transpose(double *M, double *M_t, int n) {
int Idx = blockIdx.x * B_SIZE + threadIdx.x;
if(Idx < n*n) {
int x = Idx % n;
int y = Idx / n;
int T_index = x * n + y;
M_t[T_index] = M[Idx];
}
}
void print(double *M, int n) {
std::cout << "Print matrix: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << M[i * n + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char ** argv) {
assert(argc == 2);
int n = atoi(argv[1]);
size_t size = n * n * sizeof(double);
double *M = (double*)malloc(size);
//init
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M[i * n + j] = i / j + j % i;
}
}
double *M_t = (double*)malloc(size);
double t1 = timer();
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M_t[j * n + i] = M[i * n + j];
}
}
double t2 = timer();
std::cout << "Cpu time: " << t2-t1 << std::endl;
// print(M, n);
// print(M_t, n);
dim3 block(B_SIZE);
dim3 grid((n * n - 1) / B_SIZE + 1);
double *M_dev, *M_t_dev;
cudaMalloc(&M_dev, size);
cudaMalloc(&M_t_dev, size);
cudaMemcpy(M_dev, M, size, cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
transpose<<<grid, block>>>(M_dev, M_t_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(M_t, M_t_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Gpu time is: " << ms << std::endl;
// print(M_t, n);
bool check = true;
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
check *= (M[i*n+j] == M_t[j*n+i]);
}
}
if (check) std::cout << "CHECK PASSED!" << std::endl;
else std::cout << "CHECK FAILED!" << std::endl;
free(M);
free(M_t);
cudaFree(M_dev);
cudaFree(M_t_dev);
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <assert.h>
#include <sys/time.h>
const int B_SIZE = 1024;
double timer() {
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-06);
}
__global__ void transpose(double *M, double *M_t, int n) {
int Idx = blockIdx.x * B_SIZE + threadIdx.x;
if(Idx < n*n) {
int x = Idx % n;
int y = Idx / n;
int T_index = x * n + y;
M_t[T_index] = M[Idx];
}
}
void print(double *M, int n) {
std::cout << "Print matrix: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << M[i * n + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char ** argv) {
assert(argc == 2);
int n = atoi(argv[1]);
size_t size = n * n * sizeof(double);
double *M = (double*)malloc(size);
//init
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M[i * n + j] = i / j + j % i;
}
}
double *M_t = (double*)malloc(size);
double t1 = timer();
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M_t[j * n + i] = M[i * n + j];
}
}
double t2 = timer();
std::cout << "Cpu time: " << t2-t1 << std::endl;
// print(M, n);
// print(M_t, n);
dim3 block(B_SIZE);
dim3 grid((n * n - 1) / B_SIZE + 1);
double *M_dev, *M_t_dev;
hipMalloc(&M_dev, size);
hipMalloc(&M_t_dev, size);
hipMemcpy(M_dev, M, size, hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
transpose<<<grid, block>>>(M_dev, M_t_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(M_t, M_t_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Gpu time is: " << ms << std::endl;
// print(M_t, n);
bool check = true;
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
check *= (M[i*n+j] == M_t[j*n+i]);
}
}
if (check) std::cout << "CHECK PASSED!" << std::endl;
else std::cout << "CHECK FAILED!" << std::endl;
free(M);
free(M_t);
hipFree(M_dev);
hipFree(M_t_dev);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <assert.h>
#include <sys/time.h>
const int B_SIZE = 1024;
double timer() {
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-06);
}
__global__ void transpose(double *M, double *M_t, int n) {
int Idx = blockIdx.x * B_SIZE + threadIdx.x;
if(Idx < n*n) {
int x = Idx % n;
int y = Idx / n;
int T_index = x * n + y;
M_t[T_index] = M[Idx];
}
}
void print(double *M, int n) {
std::cout << "Print matrix: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << M[i * n + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char ** argv) {
assert(argc == 2);
int n = atoi(argv[1]);
size_t size = n * n * sizeof(double);
double *M = (double*)malloc(size);
//init
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M[i * n + j] = i / j + j % i;
}
}
double *M_t = (double*)malloc(size);
double t1 = timer();
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M_t[j * n + i] = M[i * n + j];
}
}
double t2 = timer();
std::cout << "Cpu time: " << t2-t1 << std::endl;
// print(M, n);
// print(M_t, n);
dim3 block(B_SIZE);
dim3 grid((n * n - 1) / B_SIZE + 1);
double *M_dev, *M_t_dev;
hipMalloc(&M_dev, size);
hipMalloc(&M_t_dev, size);
hipMemcpy(M_dev, M, size, hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
transpose<<<grid, block>>>(M_dev, M_t_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(M_t, M_t_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Gpu time is: " << ms << std::endl;
// print(M_t, n);
bool check = true;
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
check *= (M[i*n+j] == M_t[j*n+i]);
}
}
if (check) std::cout << "CHECK PASSED!" << std::endl;
else std::cout << "CHECK FAILED!" << std::endl;
free(M);
free(M_t);
hipFree(M_dev);
hipFree(M_t_dev);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePdS_i
.globl _Z9transposePdS_i
.p2align 8
.type _Z9transposePdS_i,@function
_Z9transposePdS_i:
s_load_b32 s4, s[0:1], 0x10
v_lshl_or_b32 v0, s15, 10, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s4, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v5, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[0:1]
v_add_nc_u32_e32 v6, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v6, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_ashr_i32 s0, s4, 31
s_add_i32 s1, s4, s0
global_load_b64 v[1:2], v[1:2], off
s_xor_b32 s1, s1, s0
v_xor_b32_e32 v5, s0, v5
v_cvt_f32_u32_e32 v3, s1
s_sub_i32 s5, 0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s5, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v3, s1
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s1, v4
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_mul_lo_u32 v4, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_mad_u64_u32 v[4:5], null, v0, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[1:2], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePdS_i, .Lfunc_end0-_Z9transposePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <assert.h>
#include <sys/time.h>
const int B_SIZE = 1024;
double timer() {
struct timeval tp;
struct timezone tzp;
gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-06);
}
__global__ void transpose(double *M, double *M_t, int n) {
int Idx = blockIdx.x * B_SIZE + threadIdx.x;
if(Idx < n*n) {
int x = Idx % n;
int y = Idx / n;
int T_index = x * n + y;
M_t[T_index] = M[Idx];
}
}
void print(double *M, int n) {
std::cout << "Print matrix: \n";
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
std::cout << M[i * n + j] << " ";
}
std::cout << std::endl;
}
}
int main(int argc, char ** argv) {
assert(argc == 2);
int n = atoi(argv[1]);
size_t size = n * n * sizeof(double);
double *M = (double*)malloc(size);
//init
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M[i * n + j] = i / j + j % i;
}
}
double *M_t = (double*)malloc(size);
double t1 = timer();
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
M_t[j * n + i] = M[i * n + j];
}
}
double t2 = timer();
std::cout << "Cpu time: " << t2-t1 << std::endl;
// print(M, n);
// print(M_t, n);
dim3 block(B_SIZE);
dim3 grid((n * n - 1) / B_SIZE + 1);
double *M_dev, *M_t_dev;
hipMalloc(&M_dev, size);
hipMalloc(&M_t_dev, size);
hipMemcpy(M_dev, M, size, hipMemcpyHostToDevice);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
transpose<<<grid, block>>>(M_dev, M_t_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(M_t, M_t_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Gpu time is: " << ms << std::endl;
// print(M_t, n);
bool check = true;
for (int i = 0; i < n; i++) {
for (int j = 0; j < n; j++) {
check *= (M[i*n+j] == M_t[j*n+i]);
}
}
if (check) std::cout << "CHECK PASSED!" << std::endl;
else std::cout << "CHECK FAILED!" << std::endl;
free(M);
free(M_t);
hipFree(M_dev);
hipFree(M_t_dev);
return 0;
} | .text
.file "transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5timerv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5timerv
.p2align 4, 0x90
.type _Z5timerv,@function
_Z5timerv: # @_Z5timerv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5timerv, .Lfunc_end0-_Z5timerv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePdS_i # -- Begin function _Z24__device_stub__transposePdS_i
.p2align 4, 0x90
.type _Z24__device_stub__transposePdS_i,@function
_Z24__device_stub__transposePdS_i: # @_Z24__device_stub__transposePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__transposePdS_i, .Lfunc_end1-_Z24__device_stub__transposePdS_i
.cfi_endproc
# -- End function
.globl _Z5printPdi # -- Begin function _Z5printPdi
.p2align 4, 0x90
.type _Z5printPdi,@function
_Z5printPdi: # @_Z5printPdi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB2_9
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbp
addl %ebx, %r13d
cmpq %r12, %rbp
je .LBB2_9
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r13d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r12
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_10
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_2 Depth=1
cmpb $0, 56(%r15)
je .LBB2_7
# %bb.6: # in Loop: Header=BB2_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB2_8
.LBB2_9: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z5printPdi, .Lfunc_end2-_Z5printPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl %r15d, %r13d
imull %r13d, %r13d
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB3_5
# %bb.1: # %.preheader94.lr.ph
movl %r15d, %r8d
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r14d, %eax
leaq (%rbx,%rax,8), %r9
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %eax
xorl %edx, %edx
divl %esi
movl %eax, %edi
movl %esi, %eax
xorl %edx, %edx
divl %ecx
addl %edi, %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, (%r9,%rsi,8)
incq %rsi
cmpq %rsi, %r8
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rcx
addl %r15d, %r14d
cmpq %r8, %rcx
jne .LBB3_2
.LBB3_5: # %._crit_edge97
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB3_10
# %bb.6: # %.preheader93.lr.ph
movl %r15d, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
movq %r14, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_7: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
movl %edx, %r8d
leaq (%rbx,%r8,8), %r8
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r8,%r10,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r9)
incq %r10
addq %rcx, %r9
cmpq %r10, %rax
jne .LBB3_8
# %bb.9: # %._crit_edge100
# in Loop: Header=BB3_7 Depth=1
incq %rdi
addl %r15d, %edx
addq $8, %rsi
cmpq %rax, %rdi
jne .LBB3_7
.LBB3_10: # %._crit_edge102
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB3_34
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB3_13
# %bb.12:
movzbl 67(%rbp), %ecx
jmp .LBB3_14
.LBB3_13:
movq %rbp, %rdi
movq %r12, 8(%rsp) # 8-byte Spill
movq %r14, %r12
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
movq %r12, %r14
movq 8(%rsp), %r12 # 8-byte Reload
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leal -1(%r13), %eax
addl $1022, %r13d # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $10, %r13d
incl %r13d
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %rbp # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r15d, 76(%rsp)
leaq 144(%rsp), %rax
movq %rax, 16(%rsp)
leaq 136(%rsp), %rax
movq %rax, 24(%rsp)
leaq 76(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9transposePdS_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
callq hipDeviceSynchronize
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipEventSynchronize
movl $0, 16(%rsp)
movq 96(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB3_34
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i77
cmpb $0, 56(%r12)
je .LBB3_19
# %bb.18:
movzbl 67(%r12), %ecx
jmp .LBB3_20
.LBB3_19:
movq %r12, %rdi
movq %r14, %r13
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
movq %r13, %r14
.LBB3_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit80
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_26
# %bb.21: # %.preheader.lr.ph
movl %r15d, %eax
leaq (,%rax,8), %rdx
movb $1, %cl
xorl %esi, %esi
movq %r14, %r12
movq %r14, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_22: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_23 Depth 2
movl %esi, %r9d
leaq (%rbx,%r9,8), %r9
movq %rdi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_23: # Parent Loop BB3_22 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r9,%r11,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r10), %xmm0
setnp %bpl
sete %r14b
andb %bpl, %r14b
andb %r14b, %cl
incq %r11
addq %rdx, %r10
cmpq %r11, %rax
jne .LBB3_23
# %bb.24: # %._crit_edge106
# in Loop: Header=BB3_22 Depth=1
incq %r8
addl %r15d, %esi
addq $8, %rdi
cmpq %rax, %r8
jne .LBB3_22
# %bb.25: # %._crit_edge109.loopexit
testb %cl, %cl
movq %r12, %r14
je .LBB3_29
.LBB3_26: # %.critedge
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_34
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i82
cmpb $0, 56(%r15)
je .LBB3_32
.LBB3_28:
movzbl 67(%r15), %eax
jmp .LBB3_33
.LBB3_29:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_34
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
cmpb $0, 56(%r15)
jne .LBB3_28
.LBB3_32:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit85
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_34:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePdS_i,@object # @_Z9transposePdS_i
.section .rodata,"a",@progbits
.globl _Z9transposePdS_i
.p2align 3, 0x0
_Z9transposePdS_i:
.quad _Z24__device_stub__transposePdS_i
.size _Z9transposePdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Print matrix: \n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cpu time: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Gpu time is: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CHECK PASSED!"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CHECK FAILED!"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePdS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9transposePdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, 0x400, R3 ; /* 0x0000040000007824 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R10, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e020a */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fc80000000000 */
/*00d0*/ I2F.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0120*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0130*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0150*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0160*/ LOP3.LUT R4, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000047a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f26270 */
/*0180*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a05 */
/*01a0*/ IMAD R6, R7, R6, R8 ; /* 0x0000000607067224 */
/* 0x000fca00078e0208 */
/*01b0*/ ISETP.GT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f44070 */
/*01c0*/ @!P2 IADD3 R6, R6, -R7.reuse, RZ ; /* 0x800000070606a210 */
/* 0x080fe40007ffe0ff */
/*01d0*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f06070 */
/*01f0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fd60003f45270 */
/*0200*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0220*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff05aa12 */
/* 0x000fc800078e33ff */
/*0230*/ IADD3 R7, -R5, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x000fca0007ffe1ff */
/*0240*/ IMAD R0, R7, c[0x0][0x170], R0 ; /* 0x00005c0007007a24 */
/* 0x000fc800078e0200 */
/*0250*/ IMAD R5, R0, c[0x0][0x170], R5 ; /* 0x00005c0000057a24 */
/* 0x000fc800078e0205 */
/*0260*/ IMAD.WIDE R4, R5, R10, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e020a */
/*0270*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePdS_i
.globl _Z9transposePdS_i
.p2align 8
.type _Z9transposePdS_i,@function
_Z9transposePdS_i:
s_load_b32 s4, s[0:1], 0x10
v_lshl_or_b32 v0, s15, 10, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s4, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v5, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[0:1]
v_add_nc_u32_e32 v6, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v6, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_ashr_i32 s0, s4, 31
s_add_i32 s1, s4, s0
global_load_b64 v[1:2], v[1:2], off
s_xor_b32 s1, s1, s0
v_xor_b32_e32 v5, s0, v5
v_cvt_f32_u32_e32 v3, s1
s_sub_i32 s5, 0, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, s5, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v3, s1
v_sub_nc_u32_e32 v4, v6, v4
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s1, v4
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_dual_cndmask_b32 v4, v4, v7 :: v_dual_cndmask_b32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v4
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v5
v_mul_lo_u32 v4, v3, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_mad_u64_u32 v[4:5], null, v0, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[3:4], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[1:2], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePdS_i, .Lfunc_end0-_Z9transposePdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012f4bb_00000000-6_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5timerv
.type _Z5timerv, @function
_Z5timerv:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z5timerv, .-_Z5timerv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Print matrix: \n"
.LC2:
.string " "
.text
.globl _Z5printPdi
.type _Z5printPdi, @function
_Z5printPdi:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movl %esi, 4(%rsp)
movl $15, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
testl %ebx, %ebx
jle .L7
movslq %ebx, %rax
leaq 0(,%rax,8), %r15
addq %r15, %rbp
negq %rax
salq $3, %rax
movq %rax, 8(%rsp)
movl $0, %r14d
leaq _ZSt4cout(%rip), %r12
leaq .LC2(%rip), %r13
jmp .L9
.L16:
call _ZSt16__throw_bad_castv@PLT
.L12:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L13:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 4(%rsp)
je .L7
.L9:
movq 8(%rsp), %rax
leaq 0(%rbp,%rax), %rbx
.L10:
movsd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L10
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L16
cmpb $0, 56(%rbx)
je .L12
movzbl 67(%rbx), %esi
jmp .L13
.L7:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z5printPdi, .-_Z5printPdi
.globl _Z31__device_stub__Z9transposePdS_iPdS_i
.type _Z31__device_stub__Z9transposePdS_iPdS_i, @function
_Z31__device_stub__Z9transposePdS_iPdS_i:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9transposePdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z31__device_stub__Z9transposePdS_iPdS_i, .-_Z31__device_stub__Z9transposePdS_iPdS_i
.globl _Z9transposePdS_i
.type _Z9transposePdS_i, @function
_Z9transposePdS_i:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9transposePdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9transposePdS_i, .-_Z9transposePdS_i
.section .rodata.str1.1
.LC3:
.string "Cpu time: "
.LC5:
.string "Gpu time is: "
.LC6:
.string "CHECK PASSED!"
.LC7:
.string "CHECK FAILED!"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %r12d
imull %eax, %eax
movl %eax, 12(%rsp)
movslq %eax, %r14
salq $3, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
testl %r13d, %r13d
jle .L26
movslq %r13d, %rbx
salq $3, %rbx
movq %rax, %r9
movl $0, %edi
leal -1(%r13), %ebp
.L27:
movl $0, %esi
.L28:
movl %edi, %eax
cltd
idivl %esi
movl %eax, %r8d
movl %esi, %eax
cltd
idivl %edi
addl %edx, %r8d
pxor %xmm0, %xmm0
cvtsi2sdl %r8d, %xmm0
movsd %xmm0, (%r9,%rsi,8)
movq %rsi, %rax
addq $1, %rsi
cmpq %rbp, %rax
jne .L28
addl $1, %edi
addq %rbx, %r9
cmpl %r12d, %edi
jne .L27
movq %r14, %rdi
call malloc@PLT
movq %rax, (%rsp)
call _Z5timerv
movsd %xmm0, 16(%rsp)
movq (%rsp), %r8
leaq 8(%r15,%rbp,8), %rcx
movl $0, %edi
notq %rbp
leaq 0(,%rbp,8), %rsi
.L30:
leaq (%rsi,%rcx), %rax
movq %r8, %rdx
.L31:
movsd (%rax), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
addq %rbx, %rdx
cmpq %rcx, %rax
jne .L31
addl $1, %edi
addq $8, %r8
addq %rbx, %rcx
cmpl %r12d, %edi
jne .L30
.L32:
call _Z5timerv
movsd %xmm0, 24(%rsp)
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 24(%rsp), %xmm0
subsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1024, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl 12(%rsp), %ebx
leal 1022(%rbx), %eax
subl $1, %ebx
cmovns %ebx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L33:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 56(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r13d, %r13d
jle .L34
movq %rbx, %r11
movslq %r13d, %r8
salq $3, %r8
leal -1(%r13), %ebx
leaq 8(%r15,%rbx,8), %rdi
movl $0, %r10d
movl $1, %esi
notq %rbx
salq $3, %rbx
movl $0, %r9d
.L35:
leaq (%rbx,%rdi), %rax
movq %r11, %rcx
.L36:
movsd (%rax), %xmm0
ucomisd (%rcx), %xmm0
setnp %dl
cmovne %r9d, %edx
andl %edx, %esi
addq $8, %rax
addq %r8, %rcx
cmpq %rdi, %rax
jne .L36
addl $1, %r10d
addq $8, %r11
addq %r8, %rdi
cmpl %r12d, %r10d
jne .L35
testb %sil, %sil
jne .L34
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L39
.L46:
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z31__device_stub__Z9transposePdS_iPdS_i
jmp .L33
.L34:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L39:
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq %r14, %rdi
call malloc@PLT
movq %rax, (%rsp)
call _Z5timerv
movsd %xmm0, 16(%rsp)
jmp .L32
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9transposePdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5timerv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5timerv
.p2align 4, 0x90
.type _Z5timerv,@function
_Z5timerv: # @_Z5timerv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5timerv, .Lfunc_end0-_Z5timerv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__transposePdS_i # -- Begin function _Z24__device_stub__transposePdS_i
.p2align 4, 0x90
.type _Z24__device_stub__transposePdS_i,@function
_Z24__device_stub__transposePdS_i: # @_Z24__device_stub__transposePdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9transposePdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__transposePdS_i, .Lfunc_end1-_Z24__device_stub__transposePdS_i
.cfi_endproc
# -- End function
.globl _Z5printPdi # -- Begin function _Z5printPdi
.p2align 4, 0x90
.type _Z5printPdi,@function
_Z5printPdi: # @_Z5printPdi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB2_9
# %bb.1: # %.preheader.lr.ph
movl %ebx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbp
addl %ebx, %r13d
cmpq %r12, %rbp
je .LBB2_9
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r13d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq %r14, %r12
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_10
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_2 Depth=1
cmpb $0, 56(%r15)
je .LBB2_7
# %bb.6: # in Loop: Header=BB2_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB2_8
.LBB2_9: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z5printPdi, .Lfunc_end2-_Z5printPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl %r15d, %r13d
imull %r13d, %r13d
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB3_5
# %bb.1: # %.preheader94.lr.ph
movl %r15d, %r8d
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl %r14d, %eax
leaq (%rbx,%rax,8), %r9
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %eax
xorl %edx, %edx
divl %esi
movl %eax, %edi
movl %esi, %eax
xorl %edx, %edx
divl %ecx
addl %edi, %edx
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
movsd %xmm0, (%r9,%rsi,8)
incq %rsi
cmpq %rsi, %r8
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rcx
addl %r15d, %r14d
cmpq %r8, %rcx
jne .LBB3_2
.LBB3_5: # %._crit_edge97
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
testl %r15d, %r15d
jle .LBB3_10
# %bb.6: # %.preheader93.lr.ph
movl %r15d, %eax
leaq (,%rax,8), %rcx
xorl %edx, %edx
movq %r14, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_7: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
movl %edx, %r8d
leaq (%rbx,%r8,8), %r8
movq %rsi, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r8,%r10,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r9)
incq %r10
addq %rcx, %r9
cmpq %r10, %rax
jne .LBB3_8
# %bb.9: # %._crit_edge100
# in Loop: Header=BB3_7 Depth=1
incq %rdi
addl %r15d, %edx
addq $8, %rsi
cmpq %rax, %rdi
jne .LBB3_7
.LBB3_10: # %._crit_edge102
leaq 16(%rsp), %rdi
leaq 80(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB3_34
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB3_13
# %bb.12:
movzbl 67(%rbp), %ecx
jmp .LBB3_14
.LBB3_13:
movq %rbp, %rdi
movq %r12, 8(%rsp) # 8-byte Spill
movq %r14, %r12
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
movq %r12, %r14
movq 8(%rsp), %r12 # 8-byte Reload
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leal -1(%r13), %eax
addl $1022, %r13d # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $10, %r13d
incl %r13d
movabsq $4294967296, %rbp # imm = 0x100000000
orq %rbp, %r13
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 64(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
orq $1024, %rbp # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_16
# %bb.15:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %r15d, 76(%rsp)
leaq 144(%rsp), %rax
movq %rax, 16(%rsp)
leaq 136(%rsp), %rax
movq %rax, 24(%rsp)
leaq 76(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9transposePdS_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_16:
callq hipDeviceSynchronize
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipEventSynchronize
movl $0, 16(%rsp)
movq 96(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB3_34
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i77
cmpb $0, 56(%r12)
je .LBB3_19
# %bb.18:
movzbl 67(%r12), %ecx
jmp .LBB3_20
.LBB3_19:
movq %r12, %rdi
movq %r14, %r13
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
movq %r13, %r14
.LBB3_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit80
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_26
# %bb.21: # %.preheader.lr.ph
movl %r15d, %eax
leaq (,%rax,8), %rdx
movb $1, %cl
xorl %esi, %esi
movq %r14, %r12
movq %r14, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB3_22: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_23 Depth 2
movl %esi, %r9d
leaq (%rbx,%r9,8), %r9
movq %rdi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB3_23: # Parent Loop BB3_22 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r9,%r11,8), %xmm0 # xmm0 = mem[0],zero
ucomisd (%r10), %xmm0
setnp %bpl
sete %r14b
andb %bpl, %r14b
andb %r14b, %cl
incq %r11
addq %rdx, %r10
cmpq %r11, %rax
jne .LBB3_23
# %bb.24: # %._crit_edge106
# in Loop: Header=BB3_22 Depth=1
incq %r8
addl %r15d, %esi
addq $8, %rdi
cmpq %rax, %r8
jne .LBB3_22
# %bb.25: # %._crit_edge109.loopexit
testb %cl, %cl
movq %r12, %r14
je .LBB3_29
.LBB3_26: # %.critedge
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_34
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i82
cmpb $0, 56(%r15)
je .LBB3_32
.LBB3_28:
movzbl 67(%r15), %eax
jmp .LBB3_33
.LBB3_29:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_34
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
cmpb $0, 56(%r15)
jne .LBB3_28
.LBB3_32:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_33: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit85
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_34:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePdS_i,@object # @_Z9transposePdS_i
.section .rodata,"a",@progbits
.globl _Z9transposePdS_i
.p2align 3, 0x0
_Z9transposePdS_i:
.quad _Z24__device_stub__transposePdS_i
.size _Z9transposePdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Print matrix: \n"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cpu time: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Gpu time is: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CHECK PASSED!"
.size .L.str.4, 14
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "CHECK FAILED!"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePdS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main() {
int devices;
cudaGetDeviceCount(&devices);
for (int d = 0; d < devices; ++d) {
cudaDeviceProp p;
cudaGetDeviceProperties(&p, d);
int mp = p.multiProcessorCount, sp = 0;
if (p.major == 2) {
if (p.minor == 1) sp = 48;
else sp = 32;
} else if (p.major == 3) {
sp = 192;
} else if (p.major == 5) {
sp = 128;
}
printf("Device %d: %s\n", d, p.name);
printf(" -> multiprocessor count: %d\n", mp);
printf(" -> stream processor count: %d (total %d)\n", sp, sp * mp);
printf(" -> warp size: %d\n", p.warpSize);
printf(" -> max threads per block: %d\n", p.maxThreadsPerBlock);
printf(" -> max block dimensions: %d x %d x %d\n", p.maxThreadsDim[0], p.maxThreadsDim[1], p.maxThreadsDim[2]);
printf(" -> max grid dimensions: %d x %d x %d\n", p.maxGridSize[0], p.maxGridSize[1], p.maxGridSize[2]);
puts("");
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main() {
int devices;
cudaGetDeviceCount(&devices);
for (int d = 0; d < devices; ++d) {
cudaDeviceProp p;
cudaGetDeviceProperties(&p, d);
int mp = p.multiProcessorCount, sp = 0;
if (p.major == 2) {
if (p.minor == 1) sp = 48;
else sp = 32;
} else if (p.major == 3) {
sp = 192;
} else if (p.major == 5) {
sp = 128;
}
printf("Device %d: %s\n", d, p.name);
printf(" -> multiprocessor count: %d\n", mp);
printf(" -> stream processor count: %d (total %d)\n", sp, sp * mp);
printf(" -> warp size: %d\n", p.warpSize);
printf(" -> max threads per block: %d\n", p.maxThreadsPerBlock);
printf(" -> max block dimensions: %d x %d x %d\n", p.maxThreadsDim[0], p.maxThreadsDim[1], p.maxThreadsDim[2]);
printf(" -> max grid dimensions: %d x %d x %d\n", p.maxGridSize[0], p.maxGridSize[1], p.maxGridSize[2]);
puts("");
}
return 0;
} | .file "tmpxft_0001db09_00000000-6_check_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device %d: %s\n"
.LC1:
.string " -> multiprocessor count: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " -> stream processor count: %d (total %d)\n"
.section .rodata.str1.1
.LC3:
.string " -> warp size: %d\n"
.section .rodata.str1.8
.align 8
.LC4:
.string " -> max threads per block: %d\n"
.align 8
.LC5:
.string " -> max block dimensions: %d x %d x %d\n"
.align 8
.LC6:
.string " -> max grid dimensions: %d x %d x %d\n"
.section .rodata.str1.1
.LC7:
.string ""
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq 16(%rsp), %r13
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L7
.L13:
cmpl $1, 380(%rsp)
movl $32, %r12d
movl $48, %eax
cmove %eax, %r12d
.L6:
movq %r13, %rcx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ecx
imull %r12d, %ecx
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rdi
call puts@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L4
.L7:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 404(%rsp), %ebp
movl 376(%rsp), %eax
cmpl $2, %eax
je .L13
movl $192, %r12d
cmpl $3, %eax
je .L6
cmpl $5, %eax
sete %r12b
movzbl %r12b, %r12d
sall $7, %r12d
jmp .L6
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main() {
int devices;
cudaGetDeviceCount(&devices);
for (int d = 0; d < devices; ++d) {
cudaDeviceProp p;
cudaGetDeviceProperties(&p, d);
int mp = p.multiProcessorCount, sp = 0;
if (p.major == 2) {
if (p.minor == 1) sp = 48;
else sp = 32;
} else if (p.major == 3) {
sp = 192;
} else if (p.major == 5) {
sp = 128;
}
printf("Device %d: %s\n", d, p.name);
printf(" -> multiprocessor count: %d\n", mp);
printf(" -> stream processor count: %d (total %d)\n", sp, sp * mp);
printf(" -> warp size: %d\n", p.warpSize);
printf(" -> max threads per block: %d\n", p.maxThreadsPerBlock);
printf(" -> max block dimensions: %d x %d x %d\n", p.maxThreadsDim[0], p.maxThreadsDim[1], p.maxThreadsDim[2]);
printf(" -> max grid dimensions: %d x %d x %d\n", p.maxGridSize[0], p.maxGridSize[1], p.maxGridSize[2]);
puts("");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
int devices;
hipGetDeviceCount(&devices);
for (int d = 0; d < devices; ++d) {
hipDeviceProp_t p;
hipGetDeviceProperties(&p, d);
int mp = p.multiProcessorCount, sp = 0;
if (p.major == 2) {
if (p.minor == 1) sp = 48;
else sp = 32;
} else if (p.major == 3) {
sp = 192;
} else if (p.major == 5) {
sp = 128;
}
printf("Device %d: %s\n", d, p.name);
printf(" -> multiprocessor count: %d\n", mp);
printf(" -> stream processor count: %d (total %d)\n", sp, sp * mp);
printf(" -> warp size: %d\n", p.warpSize);
printf(" -> max threads per block: %d\n", p.maxThreadsPerBlock);
printf(" -> max block dimensions: %d x %d x %d\n", p.maxThreadsDim[0], p.maxThreadsDim[1], p.maxThreadsDim[2]);
printf(" -> max grid dimensions: %d x %d x %d\n", p.maxGridSize[0], p.maxGridSize[1], p.maxGridSize[2]);
puts("");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
int devices;
hipGetDeviceCount(&devices);
for (int d = 0; d < devices; ++d) {
hipDeviceProp_t p;
hipGetDeviceProperties(&p, d);
int mp = p.multiProcessorCount, sp = 0;
if (p.major == 2) {
if (p.minor == 1) sp = 48;
else sp = 32;
} else if (p.major == 3) {
sp = 192;
} else if (p.major == 5) {
sp = 128;
}
printf("Device %d: %s\n", d, p.name);
printf(" -> multiprocessor count: %d\n", mp);
printf(" -> stream processor count: %d (total %d)\n", sp, sp * mp);
printf(" -> warp size: %d\n", p.warpSize);
printf(" -> max threads per block: %d\n", p.maxThreadsPerBlock);
printf(" -> max block dimensions: %d x %d x %d\n", p.maxThreadsDim[0], p.maxThreadsDim[1], p.maxThreadsDim[2]);
printf(" -> max grid dimensions: %d x %d x %d\n", p.maxGridSize[0], p.maxGridSize[1], p.maxGridSize[2]);
puts("");
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
int devices;
hipGetDeviceCount(&devices);
for (int d = 0; d < devices; ++d) {
hipDeviceProp_t p;
hipGetDeviceProperties(&p, d);
int mp = p.multiProcessorCount, sp = 0;
if (p.major == 2) {
if (p.minor == 1) sp = 48;
else sp = 32;
} else if (p.major == 3) {
sp = 192;
} else if (p.major == 5) {
sp = 128;
}
printf("Device %d: %s\n", d, p.name);
printf(" -> multiprocessor count: %d\n", mp);
printf(" -> stream processor count: %d (total %d)\n", sp, sp * mp);
printf(" -> warp size: %d\n", p.warpSize);
printf(" -> max threads per block: %d\n", p.maxThreadsPerBlock);
printf(" -> max block dimensions: %d x %d x %d\n", p.maxThreadsDim[0], p.maxThreadsDim[1], p.maxThreadsDim[2]);
printf(" -> max grid dimensions: %d x %d x %d\n", p.maxGridSize[0], p.maxGridSize[1], p.maxGridSize[2]);
puts("");
}
return 0;
} | .text
.file "check_GPU.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_9
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl $192, %r14d
.LBB0_8: # in Loop: Header=BB0_2 Depth=1
movl 396(%rsp), %r15d
movl $.L.str, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
imull %r14d, %r15d
movl $.L.str.2, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_9
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 368(%rsp), %eax
cmpl $5, %eax
je .LBB0_7
# %bb.3: # in Loop: Header=BB0_2 Depth=1
cmpl $3, %eax
je .LBB0_4
# %bb.5: # in Loop: Header=BB0_2 Depth=1
xorl %r14d, %r14d
cmpl $2, %eax
jne .LBB0_8
# %bb.6: # in Loop: Header=BB0_2 Depth=1
cmpl $1, 372(%rsp)
sete %r14b
shll $4, %r14d
orl $32, %r14d
jmp .LBB0_8
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_2 Depth=1
movl $128, %r14d
jmp .LBB0_8
.LBB0_9: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device %d: %s\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " -> multiprocessor count: %d\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " -> stream processor count: %d (total %d)\n"
.size .L.str.2, 43
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " -> warp size: %d\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " -> max threads per block: %d\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " -> max block dimensions: %d x %d x %d\n"
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " -> max grid dimensions: %d x %d x %d\n"
.size .L.str.6, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001db09_00000000-6_check_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device %d: %s\n"
.LC1:
.string " -> multiprocessor count: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " -> stream processor count: %d (total %d)\n"
.section .rodata.str1.1
.LC3:
.string " -> warp size: %d\n"
.section .rodata.str1.8
.align 8
.LC4:
.string " -> max threads per block: %d\n"
.align 8
.LC5:
.string " -> max block dimensions: %d x %d x %d\n"
.align 8
.LC6:
.string " -> max grid dimensions: %d x %d x %d\n"
.section .rodata.str1.1
.LC7:
.string ""
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq 16(%rsp), %r13
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L7
.L13:
cmpl $1, 380(%rsp)
movl $32, %r12d
movl $48, %eax
cmove %eax, %r12d
.L6:
movq %r13, %rcx
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %ecx
imull %r12d, %ecx
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rdi
call puts@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L4
.L7:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 404(%rsp), %ebp
movl 376(%rsp), %eax
cmpl $2, %eax
je .L13
movl $192, %r12d
cmpl $3, %eax
je .L6
cmpl $5, %eax
sete %r12b
movzbl %r12b, %r12d
sall $7, %r12d
jmp .L6
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check_GPU.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_9
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl $192, %r14d
.LBB0_8: # in Loop: Header=BB0_2 Depth=1
movl 396(%rsp), %r15d
movl $.L.str, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
imull %r14d, %r15d
movl $.L.str.2, %edi
movl %r14d, %esi
movl %r15d, %edx
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 4(%rsp), %ebp
jge .LBB0_9
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 368(%rsp), %eax
cmpl $5, %eax
je .LBB0_7
# %bb.3: # in Loop: Header=BB0_2 Depth=1
cmpl $3, %eax
je .LBB0_4
# %bb.5: # in Loop: Header=BB0_2 Depth=1
xorl %r14d, %r14d
cmpl $2, %eax
jne .LBB0_8
# %bb.6: # in Loop: Header=BB0_2 Depth=1
cmpl $1, 372(%rsp)
sete %r14b
shll $4, %r14d
orl $32, %r14d
jmp .LBB0_8
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_2 Depth=1
movl $128, %r14d
jmp .LBB0_8
.LBB0_9: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device %d: %s\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " -> multiprocessor count: %d\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " -> stream processor count: %d (total %d)\n"
.size .L.str.2, 43
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " -> warp size: %d\n"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " -> max threads per block: %d\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " -> max block dimensions: %d x %d x %d\n"
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " -> max grid dimensions: %d x %d x %d\n"
.size .L.str.6, 39
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void conductance_move_spikes_towards_synapses_kernel( int* d_spikes_travelling_to_synapse, float current_time_in_seconds, int* circular_spikenum_buffer, int* spikeid_buffer, int bufferloc, int buffersize, int total_number_of_synapses, float* d_time_of_last_spike_to_reach_synapse, int* postsynaptic_neuron_indices, float * neuron_wise_conductance_trace, int * synaptic_decay_id, int total_number_of_neurons, float * d_synaptic_efficacies_or_weights, float * d_biological_conductance_scaling_constants_lambda, float timestep){
int indx = threadIdx.x + blockIdx.x * blockDim.x;
while (indx < circular_spikenum_buffer[bufferloc]) {
int idx = spikeid_buffer[bufferloc*total_number_of_synapses + indx];
// Update Synapses
d_time_of_last_spike_to_reach_synapse[idx] = current_time_in_seconds;
int postsynaptic_neuron_id = postsynaptic_neuron_indices[idx];
int trace_id = synaptic_decay_id[idx];
float synaptic_efficacy = d_biological_conductance_scaling_constants_lambda[idx] * d_synaptic_efficacies_or_weights[idx];
atomicAdd(&neuron_wise_conductance_trace[total_number_of_neurons*trace_id + postsynaptic_neuron_id], synaptic_efficacy);
indx += blockDim.x * gridDim.x;
}
__syncthreads();
} | code for sm_80
Function : _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0205 */
/*0050*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0070*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0206 */
/*0090*/ ISETP.GE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f06270 */
/*00a0*/ @P0 BRA 0x230 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R8, R0, c[0x0][0x188], R7 ; /* 0x0000620000087a24 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R8, R8, R5, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fcc00078e0205 */
/*00d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R23, c[0x0][0x168] ; /* 0x00005a0000177a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.WIDE R10, R8, R5, c[0x0][0x190] ; /* 0x00006400080a7625 */
/* 0x004fc800078e0205 */
/*0100*/ IMAD.WIDE R12, R8.reuse, R5.reuse, c[0x0][0x198] ; /* 0x00006600080c7625 */
/* 0x0c0fe200078e0205 */
/*0110*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0001e6000c101904 */
/*0120*/ IMAD.WIDE R14, R8.reuse, R5.reuse, c[0x0][0x1a8] ; /* 0x00006a00080e7625 */
/* 0x0c0fe400078e0205 */
/*0130*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE R16, R8.reuse, R5.reuse, c[0x0][0x1c0] ; /* 0x0000700008107625 */
/* 0x0c0fe400078e0205 */
/*0150*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0160*/ IMAD.WIDE R18, R8, R5, c[0x0][0x1b8] ; /* 0x00006e0008127625 */
/* 0x000fc400078e0205 */
/*0170*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee2000c1e1900 */
/*0190*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD R8, R14, c[0x0][0x1b0], R13 ; /* 0x00006c000e087a24 */
/* 0x004fc800078e020d */
/*01b0*/ IMAD.WIDE R8, R8, R5, c[0x0][0x1a0] ; /* 0x0000680008087625 */
/* 0x000fc800078e0205 */
/*01c0*/ FMUL R21, R18, R17 ; /* 0x0000001112157220 */
/* 0x008fca0000400000 */
/*01d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64], R21 ; /* 0x000000150800798e */
/* 0x0001e8000c10e784 */
/*01e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ MOV R6, c[0x0][0x0] ; /* 0x0000000000067a02 */
/* 0x000fca0000000f00 */
/*0200*/ IMAD R7, R6, c[0x0][0xc], R7 ; /* 0x0000030006077a24 */
/* 0x000fca00078e0207 */
/*0210*/ ISETP.GE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f06270 */
/*0220*/ @!P0 BRA 0xb0 ; /* 0xfffffe8000008947 */
/* 0x001fea000383ffff */
/*0230*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void conductance_move_spikes_towards_synapses_kernel( int* d_spikes_travelling_to_synapse, float current_time_in_seconds, int* circular_spikenum_buffer, int* spikeid_buffer, int bufferloc, int buffersize, int total_number_of_synapses, float* d_time_of_last_spike_to_reach_synapse, int* postsynaptic_neuron_indices, float * neuron_wise_conductance_trace, int * synaptic_decay_id, int total_number_of_neurons, float * d_synaptic_efficacies_or_weights, float * d_biological_conductance_scaling_constants_lambda, float timestep){
int indx = threadIdx.x + blockIdx.x * blockDim.x;
while (indx < circular_spikenum_buffer[bufferloc]) {
int idx = spikeid_buffer[bufferloc*total_number_of_synapses + indx];
// Update Synapses
d_time_of_last_spike_to_reach_synapse[idx] = current_time_in_seconds;
int postsynaptic_neuron_id = postsynaptic_neuron_indices[idx];
int trace_id = synaptic_decay_id[idx];
float synaptic_efficacy = d_biological_conductance_scaling_constants_lambda[idx] * d_synaptic_efficacies_or_weights[idx];
atomicAdd(&neuron_wise_conductance_trace[total_number_of_neurons*trace_id + postsynaptic_neuron_id], synaptic_efficacy);
indx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .file "tmpxft_00167f3f_00000000-6_conductance_move_spikes_towards_synapses_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f
.type _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f, @function
_Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rdi, 88(%rsp)
movss %xmm0, 84(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 80(%rsp)
movl %r8d, 60(%rsp)
movl %r9d, 56(%rsp)
movss %xmm1, 4(%rsp)
movq 304(%rsp), %rax
movq %rax, 48(%rsp)
movq 312(%rsp), %rax
movq %rax, 40(%rsp)
movq 320(%rsp), %rax
movq %rax, 32(%rsp)
movq 328(%rsp), %rax
movq %rax, 24(%rsp)
movq 344(%rsp), %rax
movq %rax, 16(%rsp)
movq 352(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 84(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 40(%rsp), %rax
movq %rax, 224(%rsp)
leaq 32(%rsp), %rax
movq %rax, 232(%rsp)
leaq 24(%rsp), %rax
movq %rax, 240(%rsp)
leaq 336(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 4(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f, .-_Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f
.globl _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.type _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, @function
_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, .-_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void conductance_move_spikes_towards_synapses_kernel( int* d_spikes_travelling_to_synapse, float current_time_in_seconds, int* circular_spikenum_buffer, int* spikeid_buffer, int bufferloc, int buffersize, int total_number_of_synapses, float* d_time_of_last_spike_to_reach_synapse, int* postsynaptic_neuron_indices, float * neuron_wise_conductance_trace, int * synaptic_decay_id, int total_number_of_neurons, float * d_synaptic_efficacies_or_weights, float * d_biological_conductance_scaling_constants_lambda, float timestep){
int indx = threadIdx.x + blockIdx.x * blockDim.x;
while (indx < circular_spikenum_buffer[bufferloc]) {
int idx = spikeid_buffer[bufferloc*total_number_of_synapses + indx];
// Update Synapses
d_time_of_last_spike_to_reach_synapse[idx] = current_time_in_seconds;
int postsynaptic_neuron_id = postsynaptic_neuron_indices[idx];
int trace_id = synaptic_decay_id[idx];
float synaptic_efficacy = d_biological_conductance_scaling_constants_lambda[idx] * d_synaptic_efficacies_or_weights[idx];
atomicAdd(&neuron_wise_conductance_trace[total_number_of_neurons*trace_id + postsynaptic_neuron_id], synaptic_efficacy);
indx += blockDim.x * gridDim.x;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void conductance_move_spikes_towards_synapses_kernel( int* d_spikes_travelling_to_synapse, float current_time_in_seconds, int* circular_spikenum_buffer, int* spikeid_buffer, int bufferloc, int buffersize, int total_number_of_synapses, float* d_time_of_last_spike_to_reach_synapse, int* postsynaptic_neuron_indices, float * neuron_wise_conductance_trace, int * synaptic_decay_id, int total_number_of_neurons, float * d_synaptic_efficacies_or_weights, float * d_biological_conductance_scaling_constants_lambda, float timestep){
int indx = threadIdx.x + blockIdx.x * blockDim.x;
while (indx < circular_spikenum_buffer[bufferloc]) {
int idx = spikeid_buffer[bufferloc*total_number_of_synapses + indx];
// Update Synapses
d_time_of_last_spike_to_reach_synapse[idx] = current_time_in_seconds;
int postsynaptic_neuron_id = postsynaptic_neuron_indices[idx];
int trace_id = synaptic_decay_id[idx];
float synaptic_efficacy = d_biological_conductance_scaling_constants_lambda[idx] * d_synaptic_efficacies_or_weights[idx];
atomicAdd(&neuron_wise_conductance_trace[total_number_of_neurons*trace_id + postsynaptic_neuron_id], synaptic_efficacy);
indx += blockDim.x * gridDim.x;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void conductance_move_spikes_towards_synapses_kernel( int* d_spikes_travelling_to_synapse, float current_time_in_seconds, int* circular_spikenum_buffer, int* spikeid_buffer, int bufferloc, int buffersize, int total_number_of_synapses, float* d_time_of_last_spike_to_reach_synapse, int* postsynaptic_neuron_indices, float * neuron_wise_conductance_trace, int * synaptic_decay_id, int total_number_of_neurons, float * d_synaptic_efficacies_or_weights, float * d_biological_conductance_scaling_constants_lambda, float timestep){
int indx = threadIdx.x + blockIdx.x * blockDim.x;
while (indx < circular_spikenum_buffer[bufferloc]) {
int idx = spikeid_buffer[bufferloc*total_number_of_synapses + indx];
// Update Synapses
d_time_of_last_spike_to_reach_synapse[idx] = current_time_in_seconds;
int postsynaptic_neuron_id = postsynaptic_neuron_indices[idx];
int trace_id = synaptic_decay_id[idx];
float synaptic_efficacy = d_biological_conductance_scaling_constants_lambda[idx] * d_synaptic_efficacies_or_weights[idx];
atomicAdd(&neuron_wise_conductance_trace[total_number_of_neurons*trace_id + postsynaptic_neuron_id], synaptic_efficacy);
indx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.globl _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.p2align 8
.type _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f,@function
_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f:
s_clause 0x2
s_load_b32 s16, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x7c
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_ashr_i32 s17, s16, 31
s_add_u32 s2, s0, 0x70
s_addc_u32 s3, s1, 0
s_lshl_b64 s[6:7], s[16:17], 2
s_and_b32 s19, s8, 0xffff
s_add_u32 s12, s4, s6
s_addc_u32 s13, s5, s7
v_mad_u64_u32 v[1:2], null, s15, s19, v[0:1]
s_load_b32 s4, s[12:13], 0x0
s_mov_b32 s17, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b32 s20, s[0:1], 0x8
s_load_b64 s[14:15], s[0:1], 0x18
s_load_b32 s21, s[0:1], 0x28
s_load_b32 s22, s[2:3], 0x0
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x30
s_load_b32 s18, s[0:1], 0x50
s_load_b128 s[0:3], s[0:1], 0x58
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s20
s_mov_b32 s20, 0
s_mul_i32 s16, s21, s16
s_mul_i32 s19, s22, s19
.LBB0_2:
v_add_nc_u32_e32 v2, s16, v1
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v5, s18, v[4:5]
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[4:5], v0, off
global_load_b32 v4, v[9:10], off
global_load_b32 v9, v[2:3], off
v_add_co_u32 v2, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v8, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, v4, v9
.LBB0_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v5, v7
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s21, vcc_lo, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s21
global_load_b32 v2, v6, s[12:13]
v_add_nc_u32_e32 v1, s19, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v2
s_or_b32 s20, vcc_lo, s20
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB0_2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 368
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, .Lfunc_end0-_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .offset: 104
.size: 4
.value_kind: by_value
- .offset: 112
.size: 4
.value_kind: hidden_block_count_x
- .offset: 116
.size: 4
.value_kind: hidden_block_count_y
- .offset: 120
.size: 4
.value_kind: hidden_block_count_z
- .offset: 124
.size: 2
.value_kind: hidden_group_size_x
- .offset: 126
.size: 2
.value_kind: hidden_group_size_y
- .offset: 128
.size: 2
.value_kind: hidden_group_size_z
- .offset: 130
.size: 2
.value_kind: hidden_remainder_x
- .offset: 132
.size: 2
.value_kind: hidden_remainder_y
- .offset: 134
.size: 2
.value_kind: hidden_remainder_z
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 176
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 368
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void conductance_move_spikes_towards_synapses_kernel( int* d_spikes_travelling_to_synapse, float current_time_in_seconds, int* circular_spikenum_buffer, int* spikeid_buffer, int bufferloc, int buffersize, int total_number_of_synapses, float* d_time_of_last_spike_to_reach_synapse, int* postsynaptic_neuron_indices, float * neuron_wise_conductance_trace, int * synaptic_decay_id, int total_number_of_neurons, float * d_synaptic_efficacies_or_weights, float * d_biological_conductance_scaling_constants_lambda, float timestep){
int indx = threadIdx.x + blockIdx.x * blockDim.x;
while (indx < circular_spikenum_buffer[bufferloc]) {
int idx = spikeid_buffer[bufferloc*total_number_of_synapses + indx];
// Update Synapses
d_time_of_last_spike_to_reach_synapse[idx] = current_time_in_seconds;
int postsynaptic_neuron_id = postsynaptic_neuron_indices[idx];
int trace_id = synaptic_decay_id[idx];
float synaptic_efficacy = d_biological_conductance_scaling_constants_lambda[idx] * d_synaptic_efficacies_or_weights[idx];
atomicAdd(&neuron_wise_conductance_trace[total_number_of_neurons*trace_id + postsynaptic_neuron_id], synaptic_efficacy);
indx += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.file "conductance_move_spikes_towards_synapses_kernel.hip"
.globl _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f # -- Begin function _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.p2align 4, 0x90
.type _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f,@function
_Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f: # @_Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 224(%rsp), %rax
movq %rax, 152(%rsp)
leaq 232(%rsp), %rax
movq %rax, 160(%rsp)
leaq 240(%rsp), %rax
movq %rax, 168(%rsp)
leaq 248(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, .Lfunc_end0-_Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f,@object # @_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.section .rodata,"a",@progbits
.globl _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.p2align 3, 0x0
_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f:
.quad _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.size _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f"
.size .L__unnamed_1, 79
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0205 */
/*0050*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1900 */
/*0060*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e280000002500 */
/*0070*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0080*/ IMAD R7, R7, c[0x0][0x0], R6 ; /* 0x0000000007077a24 */
/* 0x001fca00078e0206 */
/*0090*/ ISETP.GE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f06270 */
/*00a0*/ @P0 BRA 0x230 ; /* 0x0000018000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R8, R0, c[0x0][0x188], R7 ; /* 0x0000620000087a24 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R8, R8, R5, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fcc00078e0205 */
/*00d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R23, c[0x0][0x168] ; /* 0x00005a0000177a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.WIDE R10, R8, R5, c[0x0][0x190] ; /* 0x00006400080a7625 */
/* 0x004fc800078e0205 */
/*0100*/ IMAD.WIDE R12, R8.reuse, R5.reuse, c[0x0][0x198] ; /* 0x00006600080c7625 */
/* 0x0c0fe200078e0205 */
/*0110*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0001e6000c101904 */
/*0120*/ IMAD.WIDE R14, R8.reuse, R5.reuse, c[0x0][0x1a8] ; /* 0x00006a00080e7625 */
/* 0x0c0fe400078e0205 */
/*0130*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD.WIDE R16, R8.reuse, R5.reuse, c[0x0][0x1c0] ; /* 0x0000700008107625 */
/* 0x0c0fe400078e0205 */
/*0150*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1900 */
/*0160*/ IMAD.WIDE R18, R8, R5, c[0x0][0x1b8] ; /* 0x00006e0008127625 */
/* 0x000fc400078e0205 */
/*0170*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee2000c1e1900 */
/*0190*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*01a0*/ IMAD R8, R14, c[0x0][0x1b0], R13 ; /* 0x00006c000e087a24 */
/* 0x004fc800078e020d */
/*01b0*/ IMAD.WIDE R8, R8, R5, c[0x0][0x1a0] ; /* 0x0000680008087625 */
/* 0x000fc800078e0205 */
/*01c0*/ FMUL R21, R18, R17 ; /* 0x0000001112157220 */
/* 0x008fca0000400000 */
/*01d0*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R8.64], R21 ; /* 0x000000150800798e */
/* 0x0001e8000c10e784 */
/*01e0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ MOV R6, c[0x0][0x0] ; /* 0x0000000000067a02 */
/* 0x000fca0000000f00 */
/*0200*/ IMAD R7, R6, c[0x0][0xc], R7 ; /* 0x0000030006077a24 */
/* 0x000fca00078e0207 */
/*0210*/ ISETP.GE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f06270 */
/*0220*/ @!P0 BRA 0xb0 ; /* 0xfffffe8000008947 */
/* 0x001fea000383ffff */
/*0230*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.globl _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.p2align 8
.type _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f,@function
_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f:
s_clause 0x2
s_load_b32 s16, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x7c
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_ashr_i32 s17, s16, 31
s_add_u32 s2, s0, 0x70
s_addc_u32 s3, s1, 0
s_lshl_b64 s[6:7], s[16:17], 2
s_and_b32 s19, s8, 0xffff
s_add_u32 s12, s4, s6
s_addc_u32 s13, s5, s7
v_mad_u64_u32 v[1:2], null, s15, s19, v[0:1]
s_load_b32 s4, s[12:13], 0x0
s_mov_b32 s17, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_clause 0x2
s_load_b32 s20, s[0:1], 0x8
s_load_b64 s[14:15], s[0:1], 0x18
s_load_b32 s21, s[0:1], 0x28
s_load_b32 s22, s[2:3], 0x0
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x30
s_load_b32 s18, s[0:1], 0x50
s_load_b128 s[0:3], s[0:1], 0x58
v_mov_b32_e32 v6, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s20
s_mov_b32 s20, 0
s_mul_i32 s16, s21, s16
s_mul_i32 s19, s22, s19
.LBB0_2:
v_add_nc_u32_e32 v2, s16, v1
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s14, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v5, s18, v[4:5]
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v8, 31, v7
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[4:5], v0, off
global_load_b32 v4, v[9:10], off
global_load_b32 v9, v[2:3], off
v_add_co_u32 v2, vcc_lo, s8, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v8, vcc_lo
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v7, v4, v9
.LBB0_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v5, v7
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s21, vcc_lo, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s21
global_load_b32 v2, v6, s[12:13]
v_add_nc_u32_e32 v1, s19, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v1, v2
s_or_b32 s20, vcc_lo, s20
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB0_2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s17
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 368
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, .Lfunc_end0-_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .offset: 104
.size: 4
.value_kind: by_value
- .offset: 112
.size: 4
.value_kind: hidden_block_count_x
- .offset: 116
.size: 4
.value_kind: hidden_block_count_y
- .offset: 120
.size: 4
.value_kind: hidden_block_count_z
- .offset: 124
.size: 2
.value_kind: hidden_group_size_x
- .offset: 126
.size: 2
.value_kind: hidden_group_size_y
- .offset: 128
.size: 2
.value_kind: hidden_group_size_z
- .offset: 130
.size: 2
.value_kind: hidden_remainder_x
- .offset: 132
.size: 2
.value_kind: hidden_remainder_y
- .offset: 134
.size: 2
.value_kind: hidden_remainder_z
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 168
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 176
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 368
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00167f3f_00000000-6_conductance_move_spikes_towards_synapses_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f
.type _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f, @function
_Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f:
.LFB2051:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rdi, 88(%rsp)
movss %xmm0, 84(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 80(%rsp)
movl %r8d, 60(%rsp)
movl %r9d, 56(%rsp)
movss %xmm1, 4(%rsp)
movq 304(%rsp), %rax
movq %rax, 48(%rsp)
movq 312(%rsp), %rax
movq %rax, 40(%rsp)
movq 320(%rsp), %rax
movq %rax, 32(%rsp)
movq 328(%rsp), %rax
movq %rax, 24(%rsp)
movq 344(%rsp), %rax
movq %rax, 16(%rsp)
movq 352(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 84(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 40(%rsp), %rax
movq %rax, 224(%rsp)
leaq 32(%rsp), %rax
movq %rax, 232(%rsp)
leaq 24(%rsp), %rax
movq %rax, 240(%rsp)
leaq 336(%rsp), %rax
movq %rax, 248(%rsp)
leaq 16(%rsp), %rax
movq %rax, 256(%rsp)
leaq 8(%rsp), %rax
movq %rax, 264(%rsp)
leaq 4(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f, .-_Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f
.globl _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.type _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, @function
_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 72(%rsp)
.cfi_def_cfa_offset 32
pushq 72(%rsp)
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
pushq 72(%rsp)
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z92__device_stub__Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_fPifS_S_iiiPfS_S0_S_iS0_S0_f
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, .-_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "conductance_move_spikes_towards_synapses_kernel.hip"
.globl _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f # -- Begin function _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.p2align 4, 0x90
.type _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f,@function
_Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f: # @_Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 224(%rsp), %rax
movq %rax, 152(%rsp)
leaq 232(%rsp), %rax
movq %rax, 160(%rsp)
leaq 240(%rsp), %rax
movq %rax, 168(%rsp)
leaq 248(%rsp), %rax
movq %rax, 176(%rsp)
leaq 256(%rsp), %rax
movq %rax, 184(%rsp)
leaq 264(%rsp), %rax
movq %rax, 192(%rsp)
leaq 272(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, .Lfunc_end0-_Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f,@object # @_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.section .rodata,"a",@progbits
.globl _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.p2align 3, 0x0
_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f:
.quad _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.size _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f"
.size .L__unnamed_1, 79
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z62__device_stub__conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z47conductance_move_spikes_towards_synapses_kernelPifS_S_iiiPfS_S0_S_iS0_S0_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
// function to add the elements of two arrays
__global__
void add(int n, float4 *x, float4 *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
//there are no operators for float4 type
for (int j = 0; j < 36; j++){
y[i].x = x[i].x + y[i].x + x[i].z;
y[i].y = x[i].y + y[i].y + x[i].w;
y[i].z = x[i].z + y[i].z + x[i].x;
y[i].w = x[i].w + y[i].w + x[i].y;
}
//add more operations
/*x[i].x = x[i].x + y[i].x;
x[i].y = x[i].y + y[i].y;
x[i].z = x[i].z + y[i].z;
x[i].w = x[i].w + y[i].w;*/
}
}
int main(void)
{
int N = 1<<20; // 1M elements
float4 *x, *y;
cudaMallocManaged(&x, N*sizeof(float4));
cudaMallocManaged(&y, N*sizeof(float4));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i].x = 1.0f;
x[i].y = 1.0f;
x[i].z = 1.0f;
x[i].w = 1.0f;
y[i].x = 2.0f;
y[i].y = 2.0f;
y[i].z = 2.0f;
y[i].w = 2.0f;
}
// Run kernel on 1M elements on the CPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
//sync CUDA and CPU
cudaDeviceSynchronize();
// Check for errors (all values should be 4.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(y[i].x-4.0f));
maxError = fmax(maxError, fabs(y[i].y-4.0f));
maxError = fmax(maxError, fabs(y[i].z-4.0f));
maxError = fmax(maxError, fabs(y[i].w-4.0f));
//save result for x
/*maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));*/
}
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _Z3addiP6float4S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x002fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0205 */
/*00a0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.128 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1d00 */
/*00c0*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000ee2000c1e1b00 */
/*00d0*/ FADD R15, R6, R8 ; /* 0x00000008060f7221 */
/* 0x004fc40000000000 */
/*00e0*/ FADD R6, R7, R9 ; /* 0x0000000907067221 */
/* 0x000fe40000000000 */
/*00f0*/ FADD R8, R12, R15 ; /* 0x0000000f0c087221 */
/* 0x008fe40000000000 */
/*0100*/ FADD R9, R13, R6 ; /* 0x000000060d097221 */
/* 0x000fca0000000000 */
/*0110*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b04 */
/*0120*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1b00 */
/*0130*/ FADD R10, R10, R12 ; /* 0x0000000c0a0a7221 */
/* 0x000fe40000000000 */
/*0140*/ FADD R12, R11, R13 ; /* 0x0000000d0b0c7221 */
/* 0x000fe40000000000 */
/*0150*/ FADD R10, R10, R6 ; /* 0x000000060a0a7221 */
/* 0x004fe40000000000 */
/*0160*/ FADD R11, R7, R12 ; /* 0x0000000c070b7221 */
/* 0x000fca0000000000 */
/*0170*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0003e8000c101b04 */
/*0180*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ FADD R6, R8, R6 ; /* 0x0000000608067221 */
/* 0x000fe40000000000 */
/*01a0*/ FADD R14, R9, R7 ; /* 0x00000007090e7221 */
/* 0x000fe40000000000 */
/*01b0*/ FADD R6, R6, R12 ; /* 0x0000000c06067221 */
/* 0x004fe40000000000 */
/*01c0*/ FADD R7, R13, R14 ; /* 0x0000000e0d077221 */
/* 0x000fca0000000000 */
/*01d0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0005e8000c101b04 */
/*01e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ee2000c1e1b00 */
/*01f0*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0200*/ FADD R14, R11, R13 ; /* 0x0000000d0b0e7221 */
/* 0x000fe40000000000 */
/*0210*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*0220*/ FADD R13, R9, R14 ; /* 0x0000000e090d7221 */
/* 0x000fca0000000000 */
/*0230*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0001e8000c101b04 */
/*0240*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x002ee2000c1e1b00 */
/*0250*/ FADD R8, R6, R8 ; /* 0x0000000806087221 */
/* 0x000fe40000000000 */
/*0260*/ FADD R14, R7, R9 ; /* 0x00000009070e7221 */
/* 0x000fe40000000000 */
/*0270*/ FADD R16, R8, R10 ; /* 0x0000000a08107221 */
/* 0x008fe40000000000 */
/*0280*/ FADD R17, R11, R14 ; /* 0x0000000e0b117221 */
/* 0x000fca0000000000 */
/*0290*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0003e8000c101b04 */
/*02a0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x004ea2000c1e1b00 */
/*02b0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*02c0*/ FADD R8, R13, R11 ; /* 0x0000000b0d087221 */
/* 0x000fe40000000000 */
/*02d0*/ FADD R14, R10, R6 ; /* 0x000000060a0e7221 */
/* 0x004fe40000000000 */
/*02e0*/ FADD R15, R7, R8 ; /* 0x00000008070f7221 */
/* 0x000fca0000000000 */
/*02f0*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0003e8000c101b04 */
/*0300*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x001ea2000c1e1b00 */
/*0310*/ FADD R6, R16, R6 ; /* 0x0000000610067221 */
/* 0x000fe40000000000 */
/*0320*/ FADD R10, R17, R7 ; /* 0x00000007110a7221 */
/* 0x000fe40000000000 */
/*0330*/ FADD R8, R6, R12 ; /* 0x0000000c06087221 */
/* 0x004fe40000000000 */
/*0340*/ FADD R9, R13, R10 ; /* 0x0000000a0d097221 */
/* 0x000fca0000000000 */
/*0350*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003e8000c101b04 */
/*0360*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1b00 */
/*0370*/ FADD R7, R14, R12 ; /* 0x0000000c0e077221 */
/* 0x000fe40000000000 */
/*0380*/ FADD R6, R15, R13 ; /* 0x0000000d0f067221 */
/* 0x000fe40000000000 */
/*0390*/ FADD R12, R7, R10 ; /* 0x0000000a070c7221 */
/* 0x004fe20000000000 */
/*03a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*03b0*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x000fe20000000000 */
/*03c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fc600000001ff */
/*03d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*03e0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003e8000c101b04 */
/*03f0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f26270 */
/*0400*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x002ea2000c1e1b00 */
/*0410*/ FADD R7, R8, R10 ; /* 0x0000000a08077221 */
/* 0x000fe40000000000 */
/*0420*/ FADD R8, R9, R11 ; /* 0x0000000b09087221 */
/* 0x000fe40000000000 */
/*0430*/ FADD R10, R14, R7 ; /* 0x000000070e0a7221 */
/* 0x004fc40000000000 */
/*0440*/ FADD R11, R15, R8 ; /* 0x000000080f0b7221 */
/* 0x000fca0000000000 */
/*0450*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e8000c101b04 */
/*0460*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*0470*/ FADD R12, R14, R12 ; /* 0x0000000c0e0c7221 */
/* 0x000fe40000000000 */
/*0480*/ FADD R14, R15, R13 ; /* 0x0000000d0f0e7221 */
/* 0x000fe40000000000 */
/*0490*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*04a0*/ FADD R13, R9, R14 ; /* 0x0000000e090d7221 */
/* 0x000fca0000000000 */
/*04b0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003e8000c101b04 */
/*04c0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea2000c1e1b00 */
/*04d0*/ FADD R8, R10, R8 ; /* 0x000000080a087221 */
/* 0x000fe40000000000 */
/*04e0*/ FADD R16, R11, R9 ; /* 0x000000090b107221 */
/* 0x000fe40000000000 */
/*04f0*/ FADD R8, R8, R14 ; /* 0x0000000e08087221 */
/* 0x004fe40000000000 */
/*0500*/ FADD R9, R15, R16 ; /* 0x000000100f097221 */
/* 0x000fca0000000000 */
/*0510*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0005e8000c101b04 */
/*0520*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x001ee2000c1e1b00 */
/*0530*/ FADD R14, R12, R14 ; /* 0x0000000e0c0e7221 */
/* 0x000fe40000000000 */
/*0540*/ FADD R16, R13, R15 ; /* 0x0000000f0d107221 */
/* 0x000fe40000000000 */
/*0550*/ FADD R14, R14, R10 ; /* 0x0000000a0e0e7221 */
/* 0x008fe40000000000 */
/*0560*/ FADD R15, R11, R16 ; /* 0x000000100b0f7221 */
/* 0x000fca0000000000 */
/*0570*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0001e8000c101b04 */
/*0580*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x002ee2000c1e1b00 */
/*0590*/ FADD R10, R8, R10 ; /* 0x0000000a080a7221 */
/* 0x000fe40000000000 */
/*05a0*/ FADD R16, R9, R11 ; /* 0x0000000b09107221 */
/* 0x000fe40000000000 */
/*05b0*/ FADD R10, R10, R12 ; /* 0x0000000c0a0a7221 */
/* 0x008fe40000000000 */
/*05c0*/ FADD R11, R13, R16 ; /* 0x000000100d0b7221 */
/* 0x000fca0000000000 */
/*05d0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0003e8000c101b04 */
/*05e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x004ea2000c1e1b00 */
/*05f0*/ FADD R12, R14, R12 ; /* 0x0000000c0e0c7221 */
/* 0x000fe40000000000 */
/*0600*/ FADD R16, R15, R13 ; /* 0x0000000d0f107221 */
/* 0x000fe40000000000 */
/*0610*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*0620*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0630*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0005e8000c101b04 */
/*0640*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x001ee2000c1e1b00 */
/*0650*/ FADD R8, R10, R8 ; /* 0x000000080a087221 */
/* 0x000fe40000000000 */
/*0660*/ FADD R16, R11, R9 ; /* 0x000000090b107221 */
/* 0x000fe40000000000 */
/*0670*/ FADD R8, R8, R14 ; /* 0x0000000e08087221 */
/* 0x008fe40000000000 */
/*0680*/ FADD R9, R15, R16 ; /* 0x000000100f097221 */
/* 0x000fca0000000000 */
/*0690*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b04 */
/*06a0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x002ee2000c1e1b00 */
/*06b0*/ FADD R14, R12, R14 ; /* 0x0000000e0c0e7221 */
/* 0x000fe40000000000 */
/*06c0*/ FADD R16, R13, R15 ; /* 0x0000000f0d107221 */
/* 0x000fe40000000000 */
/*06d0*/ FADD R14, R14, R10 ; /* 0x0000000a0e0e7221 */
/* 0x008fe40000000000 */
/*06e0*/ FADD R15, R11, R16 ; /* 0x000000100b0f7221 */
/* 0x000fca0000000000 */
/*06f0*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0003e8000c101b04 */
/*0700*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x004ea2000c1e1b00 */
/*0710*/ FADD R7, R8, R10 ; /* 0x0000000a08077221 */
/* 0x000fe40000000000 */
/*0720*/ FADD R10, R9, R11 ; /* 0x0000000b090a7221 */
/* 0x000fe40000000000 */
/*0730*/ FADD R16, R12, R7 ; /* 0x000000070c107221 */
/* 0x004fe40000000000 */
/*0740*/ FADD R17, R13, R10 ; /* 0x0000000a0d117221 */
/* 0x000fca0000000000 */
/*0750*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0005e8000c101b04 */
/*0760*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ee2000c1e1b00 */
/*0770*/ FADD R12, R14, R12 ; /* 0x0000000c0e0c7221 */
/* 0x000fe40000000000 */
/*0780*/ FADD R10, R15, R13 ; /* 0x0000000d0f0a7221 */
/* 0x000fe40000000000 */
/*0790*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*07a0*/ FADD R13, R9, R10 ; /* 0x0000000a090d7221 */
/* 0x000fca0000000000 */
/*07b0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0001e8000c101b04 */
/*07c0*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ee2000c1e1b00 */
/*07d0*/ FADD R8, R16, R8 ; /* 0x0000000810087221 */
/* 0x000fe40000000000 */
/*07e0*/ FADD R14, R17, R9 ; /* 0x00000009110e7221 */
/* 0x002fe40000000000 */
/*07f0*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x008fe40000000000 */
/*0800*/ FADD R9, R11, R14 ; /* 0x0000000e0b097221 */
/* 0x000fca0000000000 */
/*0810*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003e8000c101b04 */
/*0820*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ee2000c1e1b00 */
/*0830*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0840*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x004fe40000000000 */
/*0850*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*0860*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*0870*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0005e8000c101b04 */
/*0880*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x001ee2000c1e1b00 */
/*0890*/ FADD R14, R8, R14 ; /* 0x0000000e080e7221 */
/* 0x000fe40000000000 */
/*08a0*/ FADD R16, R9, R15 ; /* 0x0000000f09107221 */
/* 0x000fe40000000000 */
/*08b0*/ FADD R14, R14, R12 ; /* 0x0000000c0e0e7221 */
/* 0x008fe40000000000 */
/*08c0*/ FADD R15, R13, R16 ; /* 0x000000100d0f7221 */
/* 0x000fca0000000000 */
/*08d0*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0001e8000c101b04 */
/*08e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x002ee2000c1e1b00 */
/*08f0*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0900*/ FADD R16, R11, R13 ; /* 0x0000000d0b107221 */
/* 0x000fe40000000000 */
/*0910*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*0920*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0930*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003e8000c101b04 */
/*0940*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x004ea2000c1e1b00 */
/*0950*/ FADD R8, R14, R8 ; /* 0x000000080e087221 */
/* 0x000fe40000000000 */
/*0960*/ FADD R16, R15, R9 ; /* 0x000000090f107221 */
/* 0x000fe40000000000 */
/*0970*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x004fe40000000000 */
/*0980*/ FADD R9, R11, R16 ; /* 0x000000100b097221 */
/* 0x000fca0000000000 */
/*0990*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0005e8000c101b04 */
/*09a0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x001ee2000c1e1b00 */
/*09b0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*09c0*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x000fe40000000000 */
/*09d0*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*09e0*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*09f0*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0001e8000c101b04 */
/*0a00*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x002ee2000c1e1b00 */
/*0a10*/ FADD R7, R8, R14 ; /* 0x0000000e08077221 */
/* 0x000fe40000000000 */
/*0a20*/ FADD R14, R9, R15 ; /* 0x0000000f090e7221 */
/* 0x000fe40000000000 */
/*0a30*/ FADD R16, R12, R7 ; /* 0x000000070c107221 */
/* 0x008fe40000000000 */
/*0a40*/ FADD R17, R13, R14 ; /* 0x0000000e0d117221 */
/* 0x000fca0000000000 */
/*0a50*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0003e8000c101b04 */
/*0a60*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x004ea2000c1e1b00 */
/*0a70*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0a80*/ FADD R14, R11, R13 ; /* 0x0000000d0b0e7221 */
/* 0x000fe40000000000 */
/*0a90*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*0aa0*/ FADD R13, R9, R14 ; /* 0x0000000e090d7221 */
/* 0x000fca0000000000 */
/*0ab0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0005e8000c101b04 */
/*0ac0*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x001ee2000c1e1b00 */
/*0ad0*/ FADD R8, R16, R8 ; /* 0x0000000810087221 */
/* 0x000fe40000000000 */
/*0ae0*/ FADD R14, R17, R9 ; /* 0x00000009110e7221 */
/* 0x000fe40000000000 */
/*0af0*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x008fe40000000000 */
/*0b00*/ FADD R9, R11, R14 ; /* 0x0000000e0b097221 */
/* 0x000fca0000000000 */
/*0b10*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b04 */
/*0b20*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ee2000c1e1b00 */
/*0b30*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0b40*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x002fe40000000000 */
/*0b50*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*0b60*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*0b70*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0003e8000c101b04 */
/*0b80*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x004ea2000c1e1b00 */
/*0b90*/ FADD R14, R8, R14 ; /* 0x0000000e080e7221 */
/* 0x000fe40000000000 */
/*0ba0*/ FADD R16, R9, R15 ; /* 0x0000000f09107221 */
/* 0x000fe40000000000 */
/*0bb0*/ FADD R14, R14, R12 ; /* 0x0000000c0e0e7221 */
/* 0x004fe40000000000 */
/*0bc0*/ FADD R15, R13, R16 ; /* 0x000000100d0f7221 */
/* 0x000fca0000000000 */
/*0bd0*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0005e8000c101b04 */
/*0be0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ee2000c1e1b00 */
/*0bf0*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0c00*/ FADD R16, R11, R13 ; /* 0x0000000d0b107221 */
/* 0x000fe40000000000 */
/*0c10*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*0c20*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0c30*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0001e8000c101b04 */
/*0c40*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x002ee2000c1e1b00 */
/*0c50*/ FADD R8, R14, R8 ; /* 0x000000080e087221 */
/* 0x000fe40000000000 */
/*0c60*/ FADD R18, R15, R9 ; /* 0x000000090f127221 */
/* 0x000fe40000000000 */
/*0c70*/ FADD R16, R8, R10 ; /* 0x0000000a08107221 */
/* 0x008fe40000000000 */
/*0c80*/ FADD R17, R11, R18 ; /* 0x000000120b117221 */
/* 0x000fca0000000000 */
/*0c90*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0003e8000c101b04 */
/*0ca0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x004ea2000c1e1b00 */
/*0cb0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0cc0*/ FADD R8, R13, R11 ; /* 0x0000000b0d087221 */
/* 0x000fe40000000000 */
/*0cd0*/ FADD R18, R10, R14 ; /* 0x0000000e0a127221 */
/* 0x004fe40000000000 */
/*0ce0*/ FADD R19, R15, R8 ; /* 0x000000080f137221 */
/* 0x000fca0000000000 */
/*0cf0*/ STG.E.64 [R4.64+0x8], R18 ; /* 0x0000081204007986 */
/* 0x000fe8000c101b04 */
/*0d00*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000e22000c1e1b00 */
/*0d10*/ FADD R7, R16, R14 ; /* 0x0000000e10077221 */
/* 0x000fe40000000000 */
/*0d20*/ FADD R10, R17, R15 ; /* 0x0000000f110a7221 */
/* 0x000fe40000000000 */
/*0d30*/ FADD R12, R8, R7 ; /* 0x00000007080c7221 */
/* 0x001fe40000000000 */
/*0d40*/ FADD R13, R9, R10 ; /* 0x0000000a090d7221 */
/* 0x000fca0000000000 */
/*0d50*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0001e8000c101b04 */
/*0d60*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1b00 */
/*0d70*/ FADD R8, R8, R18 ; /* 0x0000001208087221 */
/* 0x000fe40000000000 */
/*0d80*/ FADD R14, R9, R19 ; /* 0x00000013090e7221 */
/* 0x000fe40000000000 */
/*0d90*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x004fe40000000000 */
/*0da0*/ FADD R9, R11, R14 ; /* 0x0000000e0b097221 */
/* 0x000fca0000000000 */
/*0db0*/ STG.E.64 [R4.64+0x8], R8 ; /* 0x0000080804007986 */
/* 0x0005e8000c101b04 */
/*0dc0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ee2000c1e1b00 */
/*0dd0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0de0*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x002fe40000000000 */
/*0df0*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*0e00*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*0e10*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0003e8000c101b04 */
/*0e20*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x001ee2000c1e1b00 */
/*0e30*/ FADD R14, R8, R14 ; /* 0x0000000e080e7221 */
/* 0x000fe40000000000 */
/*0e40*/ FADD R16, R9, R15 ; /* 0x0000000f09107221 */
/* 0x000fe40000000000 */
/*0e50*/ FADD R14, R14, R12 ; /* 0x0000000c0e0e7221 */
/* 0x008fe40000000000 */
/*0e60*/ FADD R15, R13, R16 ; /* 0x000000100d0f7221 */
/* 0x000fca0000000000 */
/*0e70*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0001e8000c101b04 */
/*0e80*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x004ea2000c1e1b00 */
/*0e90*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0ea0*/ FADD R16, R11, R13 ; /* 0x0000000d0b107221 */
/* 0x000fe40000000000 */
/*0eb0*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*0ec0*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0ed0*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0005e8000c101b04 */
/*0ee0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x002ee2000c1e1b00 */
/*0ef0*/ FADD R8, R14, R8 ; /* 0x000000080e087221 */
/* 0x000fe40000000000 */
/*0f00*/ FADD R16, R15, R9 ; /* 0x000000090f107221 */
/* 0x000fe40000000000 */
/*0f10*/ FADD R18, R8, R10 ; /* 0x0000000a08127221 */
/* 0x008fe40000000000 */
/*0f20*/ FADD R19, R11, R16 ; /* 0x000000100b137221 */
/* 0x000fca0000000000 */
/*0f30*/ STG.E.64 [R4.64+0x8], R18 ; /* 0x0000081204007986 */
/* 0x0003e8000c101b04 */
/*0f40*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x001ee2000c1e1b00 */
/*0f50*/ FADD R8, R12, R10 ; /* 0x0000000a0c087221 */
/* 0x000fe40000000000 */
/*0f60*/ FADD R10, R13, R11 ; /* 0x0000000b0d0a7221 */
/* 0x000fe40000000000 */
/*0f70*/ FADD R8, R8, R14 ; /* 0x0000000e08087221 */
/* 0x008fe40000000000 */
/*0f80*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x000fca0000000000 */
/*0f90*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003e8000c101b04 */
/*0fa0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1b00 */
/*0fb0*/ FADD R7, R18, R14 ; /* 0x0000000e12077221 */
/* 0x000fe20000000000 */
/*0fc0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe20007ffe0ff */
/*0fd0*/ FADD R14, R19, R15 ; /* 0x0000000f130e7221 */
/* 0x000fc60000000000 */
/*0fe0*/ ISETP.NE.AND P0, PT, R6, 0x24, PT ; /* 0x000000240600780c */
/* 0x000fe20003f05270 */
/*0ff0*/ FADD R12, R7, R10 ; /* 0x0000000a070c7221 */
/* 0x004fe40000000000 */
/*1000*/ FADD R13, R11, R14 ; /* 0x0000000e0b0d7221 */
/* 0x000fca0000000000 */
/*1010*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003ea000c101b04 */
/*1020*/ @P0 BRA 0x400 ; /* 0xfffff3d000000947 */
/* 0x000fea000383ffff */
/*1030*/ @P1 CALL.REL.NOINC 0x1050 ; /* 0x0000001000001944 */
/* 0x000fe20003c00000 */
/*1040*/ BRA 0x70 ; /* 0xfffff02000007947 */
/* 0x000fea000383ffff */
/*1050*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1060*/ BRA 0x1060; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
// function to add the elements of two arrays
__global__
void add(int n, float4 *x, float4 *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
//there are no operators for float4 type
for (int j = 0; j < 36; j++){
y[i].x = x[i].x + y[i].x + x[i].z;
y[i].y = x[i].y + y[i].y + x[i].w;
y[i].z = x[i].z + y[i].z + x[i].x;
y[i].w = x[i].w + y[i].w + x[i].y;
}
//add more operations
/*x[i].x = x[i].x + y[i].x;
x[i].y = x[i].y + y[i].y;
x[i].z = x[i].z + y[i].z;
x[i].w = x[i].w + y[i].w;*/
}
}
int main(void)
{
int N = 1<<20; // 1M elements
float4 *x, *y;
cudaMallocManaged(&x, N*sizeof(float4));
cudaMallocManaged(&y, N*sizeof(float4));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i].x = 1.0f;
x[i].y = 1.0f;
x[i].z = 1.0f;
x[i].w = 1.0f;
y[i].x = 2.0f;
y[i].y = 2.0f;
y[i].z = 2.0f;
y[i].w = 2.0f;
}
// Run kernel on 1M elements on the CPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
//sync CUDA and CPU
cudaDeviceSynchronize();
// Check for errors (all values should be 4.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(y[i].x-4.0f));
maxError = fmax(maxError, fabs(y[i].y-4.0f));
maxError = fmax(maxError, fabs(y[i].z-4.0f));
maxError = fmax(maxError, fabs(y[i].w-4.0f));
//save result for x
/*maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));*/
}
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_0006b951_00000000-6_add_2_4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
.type _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_, @function
_Z32__device_stub__Z3addiP6float4S0_iP6float4S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiP6float4S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_, .-_Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
.globl _Z3addiP6float4S0_
.type _Z3addiP6float4S0_, @function
_Z3addiP6float4S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiP6float4S0_, .-_Z3addiP6float4S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 16(%rsp), %rdx
movss %xmm1, 4(%rdx,%rax)
movq %rax, %rdx
addq 16(%rsp), %rdx
movss %xmm1, 8(%rdx)
movss %xmm1, 12(%rdx)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, 4(%rdx,%rax)
movq %rax, %rdx
addq 24(%rsp), %rdx
movss %xmm0, 8(%rdx)
movss %xmm0, 12(%rdx)
addq $16, %rax
cmpq $16777216, %rax
jne .L12
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 16777216(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movaps %xmm0, %xmm1
movss 4(%rbx), %xmm2
subss .LC3(%rip), %xmm2
andps .LC4(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movss 8(%rbx), %xmm1
subss .LC3(%rip), %xmm1
andps .LC4(%rip), %xmm1
call fmaxf@PLT
movss 12(%rbx), %xmm1
subss .LC3(%rip), %xmm1
andps .LC4(%rip), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $16, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiP6float4S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiP6float4S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
// function to add the elements of two arrays
__global__
void add(int n, float4 *x, float4 *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
//there are no operators for float4 type
for (int j = 0; j < 36; j++){
y[i].x = x[i].x + y[i].x + x[i].z;
y[i].y = x[i].y + y[i].y + x[i].w;
y[i].z = x[i].z + y[i].z + x[i].x;
y[i].w = x[i].w + y[i].w + x[i].y;
}
//add more operations
/*x[i].x = x[i].x + y[i].x;
x[i].y = x[i].y + y[i].y;
x[i].z = x[i].z + y[i].z;
x[i].w = x[i].w + y[i].w;*/
}
}
int main(void)
{
int N = 1<<20; // 1M elements
float4 *x, *y;
cudaMallocManaged(&x, N*sizeof(float4));
cudaMallocManaged(&y, N*sizeof(float4));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i].x = 1.0f;
x[i].y = 1.0f;
x[i].z = 1.0f;
x[i].w = 1.0f;
y[i].x = 2.0f;
y[i].y = 2.0f;
y[i].z = 2.0f;
y[i].w = 2.0f;
}
// Run kernel on 1M elements on the CPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
//sync CUDA and CPU
cudaDeviceSynchronize();
// Check for errors (all values should be 4.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(y[i].x-4.0f));
maxError = fmax(maxError, fabs(y[i].y-4.0f));
maxError = fmax(maxError, fabs(y[i].z-4.0f));
maxError = fmax(maxError, fabs(y[i].w-4.0f));
//save result for x
/*maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));*/
}
std::cout << "Max error: " << maxError << std::endl;
// Free memory
cudaFree(x);
cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// function to add the elements of two arrays
__global__
void add(int n, float4 *x, float4 *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
//there are no operators for float4 type
for (int j = 0; j < 36; j++){
y[i].x = x[i].x + y[i].x + x[i].z;
y[i].y = x[i].y + y[i].y + x[i].w;
y[i].z = x[i].z + y[i].z + x[i].x;
y[i].w = x[i].w + y[i].w + x[i].y;
}
//add more operations
/*x[i].x = x[i].x + y[i].x;
x[i].y = x[i].y + y[i].y;
x[i].z = x[i].z + y[i].z;
x[i].w = x[i].w + y[i].w;*/
}
}
int main(void)
{
int N = 1<<20; // 1M elements
float4 *x, *y;
hipMallocManaged(&x, N*sizeof(float4));
hipMallocManaged(&y, N*sizeof(float4));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i].x = 1.0f;
x[i].y = 1.0f;
x[i].z = 1.0f;
x[i].w = 1.0f;
y[i].x = 2.0f;
y[i].y = 2.0f;
y[i].z = 2.0f;
y[i].w = 2.0f;
}
// Run kernel on 1M elements on the CPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
//sync CUDA and CPU
hipDeviceSynchronize();
// Check for errors (all values should be 4.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(y[i].x-4.0f));
maxError = fmax(maxError, fabs(y[i].y-4.0f));
maxError = fmax(maxError, fabs(y[i].z-4.0f));
maxError = fmax(maxError, fabs(y[i].w-4.0f));
//save result for x
/*maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));*/
}
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// function to add the elements of two arrays
__global__
void add(int n, float4 *x, float4 *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
//there are no operators for float4 type
for (int j = 0; j < 36; j++){
y[i].x = x[i].x + y[i].x + x[i].z;
y[i].y = x[i].y + y[i].y + x[i].w;
y[i].z = x[i].z + y[i].z + x[i].x;
y[i].w = x[i].w + y[i].w + x[i].y;
}
//add more operations
/*x[i].x = x[i].x + y[i].x;
x[i].y = x[i].y + y[i].y;
x[i].z = x[i].z + y[i].z;
x[i].w = x[i].w + y[i].w;*/
}
}
int main(void)
{
int N = 1<<20; // 1M elements
float4 *x, *y;
hipMallocManaged(&x, N*sizeof(float4));
hipMallocManaged(&y, N*sizeof(float4));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i].x = 1.0f;
x[i].y = 1.0f;
x[i].z = 1.0f;
x[i].w = 1.0f;
y[i].x = 2.0f;
y[i].y = 2.0f;
y[i].z = 2.0f;
y[i].w = 2.0f;
}
// Run kernel on 1M elements on the CPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
//sync CUDA and CPU
hipDeviceSynchronize();
// Check for errors (all values should be 4.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(y[i].x-4.0f));
maxError = fmax(maxError, fabs(y[i].y-4.0f));
maxError = fmax(maxError, fabs(y[i].z-4.0f));
maxError = fmax(maxError, fabs(y[i].w-4.0f));
//save result for x
/*maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));*/
}
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiP15HIP_vector_typeIfLj4EES1_
.globl _Z3addiP15HIP_vector_typeIfLj4EES1_
.p2align 8
.type _Z3addiP15HIP_vector_typeIfLj4EES1_,@function
_Z3addiP15HIP_vector_typeIfLj4EES1_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s7, 36
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
global_load_b128 v[6:9], v[4:5], off
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v10, v[2:3], off offset:8
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s7, 0
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v6
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v10
global_store_b32 v[4:5], v0, off
s_clause 0x1
global_load_b32 v0, v[2:3], off offset:4
global_load_b32 v6, v[2:3], off offset:12
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off offset:4
s_clause 0x1
global_load_b32 v0, v[2:3], off offset:8
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off offset:8
s_clause 0x1
global_load_b32 v0, v[2:3], off offset:12
global_load_b32 v6, v[2:3], off offset:4
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off offset:12
s_cbranch_scc0 .LBB0_3
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiP15HIP_vector_typeIfLj4EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiP15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z3addiP15HIP_vector_typeIfLj4EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiP15HIP_vector_typeIfLj4EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiP15HIP_vector_typeIfLj4EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// function to add the elements of two arrays
__global__
void add(int n, float4 *x, float4 *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride){
//there are no operators for float4 type
for (int j = 0; j < 36; j++){
y[i].x = x[i].x + y[i].x + x[i].z;
y[i].y = x[i].y + y[i].y + x[i].w;
y[i].z = x[i].z + y[i].z + x[i].x;
y[i].w = x[i].w + y[i].w + x[i].y;
}
//add more operations
/*x[i].x = x[i].x + y[i].x;
x[i].y = x[i].y + y[i].y;
x[i].z = x[i].z + y[i].z;
x[i].w = x[i].w + y[i].w;*/
}
}
int main(void)
{
int N = 1<<20; // 1M elements
float4 *x, *y;
hipMallocManaged(&x, N*sizeof(float4));
hipMallocManaged(&y, N*sizeof(float4));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i].x = 1.0f;
x[i].y = 1.0f;
x[i].z = 1.0f;
x[i].w = 1.0f;
y[i].x = 2.0f;
y[i].y = 2.0f;
y[i].z = 2.0f;
y[i].w = 2.0f;
}
// Run kernel on 1M elements on the CPU
int blockSize = 256;
int numBlocks = (N + blockSize - 1) / blockSize;
add<<<numBlocks, blockSize>>>(N, x, y);
//sync CUDA and CPU
hipDeviceSynchronize();
// Check for errors (all values should be 4.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++){
maxError = fmax(maxError, fabs(y[i].x-4.0f));
maxError = fmax(maxError, fabs(y[i].y-4.0f));
maxError = fmax(maxError, fabs(y[i].z-4.0f));
maxError = fmax(maxError, fabs(y[i].w-4.0f));
//save result for x
/*maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));
maxError = fmax(maxError, fabs(x[i].w-4.0f));*/
}
std::cout << "Max error: " << maxError << std::endl;
// Free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "add_2_4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_ # -- Begin function _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.p2align 4, 0x90
.type _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_,@function
_Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_: # @_Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiP15HIP_vector_typeIfLj4EES1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0800000 # float -4
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rcx
movl $1065353216, (%rcx,%rax) # imm = 0x3F800000
movq 16(%rsp), %rcx
movl $1065353216, 4(%rcx,%rax) # imm = 0x3F800000
movq 16(%rsp), %rcx
movl $1065353216, 8(%rcx,%rax) # imm = 0x3F800000
movq 16(%rsp), %rcx
movl $1065353216, 12(%rcx,%rax) # imm = 0x3F800000
movq 8(%rsp), %rcx
movl $1073741824, (%rcx,%rax) # imm = 0x40000000
movq 8(%rsp), %rcx
movl $1073741824, 4(%rcx,%rax) # imm = 0x40000000
movq 8(%rsp), %rcx
movl $1073741824, 8(%rcx,%rax) # imm = 0x40000000
movq 8(%rsp), %rcx
movl $1073741824, 12(%rcx,%rax) # imm = 0x40000000
addq $16, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiP15HIP_vector_typeIfLj4EES1_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
movss 4(%rcx,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rcx,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rcx,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
addq $16, %rax
movaps %xmm5, %xmm2
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiP15HIP_vector_typeIfLj4EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiP15HIP_vector_typeIfLj4EES1_,@object # @_Z3addiP15HIP_vector_typeIfLj4EES1_
.section .rodata,"a",@progbits
.globl _Z3addiP15HIP_vector_typeIfLj4EES1_
.p2align 3, 0x0
_Z3addiP15HIP_vector_typeIfLj4EES1_:
.quad _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.size _Z3addiP15HIP_vector_typeIfLj4EES1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiP15HIP_vector_typeIfLj4EES1_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiP15HIP_vector_typeIfLj4EES1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiP6float4S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x002fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe200078e0205 */
/*00a0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.128 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1d00 */
/*00c0*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000ee2000c1e1b00 */
/*00d0*/ FADD R15, R6, R8 ; /* 0x00000008060f7221 */
/* 0x004fc40000000000 */
/*00e0*/ FADD R6, R7, R9 ; /* 0x0000000907067221 */
/* 0x000fe40000000000 */
/*00f0*/ FADD R8, R12, R15 ; /* 0x0000000f0c087221 */
/* 0x008fe40000000000 */
/*0100*/ FADD R9, R13, R6 ; /* 0x000000060d097221 */
/* 0x000fca0000000000 */
/*0110*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b04 */
/*0120*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1b00 */
/*0130*/ FADD R10, R10, R12 ; /* 0x0000000c0a0a7221 */
/* 0x000fe40000000000 */
/*0140*/ FADD R12, R11, R13 ; /* 0x0000000d0b0c7221 */
/* 0x000fe40000000000 */
/*0150*/ FADD R10, R10, R6 ; /* 0x000000060a0a7221 */
/* 0x004fe40000000000 */
/*0160*/ FADD R11, R7, R12 ; /* 0x0000000c070b7221 */
/* 0x000fca0000000000 */
/*0170*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0003e8000c101b04 */
/*0180*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ FADD R6, R8, R6 ; /* 0x0000000608067221 */
/* 0x000fe40000000000 */
/*01a0*/ FADD R14, R9, R7 ; /* 0x00000007090e7221 */
/* 0x000fe40000000000 */
/*01b0*/ FADD R6, R6, R12 ; /* 0x0000000c06067221 */
/* 0x004fe40000000000 */
/*01c0*/ FADD R7, R13, R14 ; /* 0x0000000e0d077221 */
/* 0x000fca0000000000 */
/*01d0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0005e8000c101b04 */
/*01e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ee2000c1e1b00 */
/*01f0*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0200*/ FADD R14, R11, R13 ; /* 0x0000000d0b0e7221 */
/* 0x000fe40000000000 */
/*0210*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*0220*/ FADD R13, R9, R14 ; /* 0x0000000e090d7221 */
/* 0x000fca0000000000 */
/*0230*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0001e8000c101b04 */
/*0240*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x002ee2000c1e1b00 */
/*0250*/ FADD R8, R6, R8 ; /* 0x0000000806087221 */
/* 0x000fe40000000000 */
/*0260*/ FADD R14, R7, R9 ; /* 0x00000009070e7221 */
/* 0x000fe40000000000 */
/*0270*/ FADD R16, R8, R10 ; /* 0x0000000a08107221 */
/* 0x008fe40000000000 */
/*0280*/ FADD R17, R11, R14 ; /* 0x0000000e0b117221 */
/* 0x000fca0000000000 */
/*0290*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0003e8000c101b04 */
/*02a0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x004ea2000c1e1b00 */
/*02b0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*02c0*/ FADD R8, R13, R11 ; /* 0x0000000b0d087221 */
/* 0x000fe40000000000 */
/*02d0*/ FADD R14, R10, R6 ; /* 0x000000060a0e7221 */
/* 0x004fe40000000000 */
/*02e0*/ FADD R15, R7, R8 ; /* 0x00000008070f7221 */
/* 0x000fca0000000000 */
/*02f0*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0003e8000c101b04 */
/*0300*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x001ea2000c1e1b00 */
/*0310*/ FADD R6, R16, R6 ; /* 0x0000000610067221 */
/* 0x000fe40000000000 */
/*0320*/ FADD R10, R17, R7 ; /* 0x00000007110a7221 */
/* 0x000fe40000000000 */
/*0330*/ FADD R8, R6, R12 ; /* 0x0000000c06087221 */
/* 0x004fe40000000000 */
/*0340*/ FADD R9, R13, R10 ; /* 0x0000000a0d097221 */
/* 0x000fca0000000000 */
/*0350*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003e8000c101b04 */
/*0360*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1b00 */
/*0370*/ FADD R7, R14, R12 ; /* 0x0000000c0e077221 */
/* 0x000fe40000000000 */
/*0380*/ FADD R6, R15, R13 ; /* 0x0000000d0f067221 */
/* 0x000fe40000000000 */
/*0390*/ FADD R12, R7, R10 ; /* 0x0000000a070c7221 */
/* 0x004fe20000000000 */
/*03a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*03b0*/ FADD R13, R11, R6 ; /* 0x000000060b0d7221 */
/* 0x000fe20000000000 */
/*03c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fc600000001ff */
/*03d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*03e0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003e8000c101b04 */
/*03f0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f26270 */
/*0400*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x002ea2000c1e1b00 */
/*0410*/ FADD R7, R8, R10 ; /* 0x0000000a08077221 */
/* 0x000fe40000000000 */
/*0420*/ FADD R8, R9, R11 ; /* 0x0000000b09087221 */
/* 0x000fe40000000000 */
/*0430*/ FADD R10, R14, R7 ; /* 0x000000070e0a7221 */
/* 0x004fc40000000000 */
/*0440*/ FADD R11, R15, R8 ; /* 0x000000080f0b7221 */
/* 0x000fca0000000000 */
/*0450*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e8000c101b04 */
/*0460*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1b00 */
/*0470*/ FADD R12, R14, R12 ; /* 0x0000000c0e0c7221 */
/* 0x000fe40000000000 */
/*0480*/ FADD R14, R15, R13 ; /* 0x0000000d0f0e7221 */
/* 0x000fe40000000000 */
/*0490*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*04a0*/ FADD R13, R9, R14 ; /* 0x0000000e090d7221 */
/* 0x000fca0000000000 */
/*04b0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003e8000c101b04 */
/*04c0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea2000c1e1b00 */
/*04d0*/ FADD R8, R10, R8 ; /* 0x000000080a087221 */
/* 0x000fe40000000000 */
/*04e0*/ FADD R16, R11, R9 ; /* 0x000000090b107221 */
/* 0x000fe40000000000 */
/*04f0*/ FADD R8, R8, R14 ; /* 0x0000000e08087221 */
/* 0x004fe40000000000 */
/*0500*/ FADD R9, R15, R16 ; /* 0x000000100f097221 */
/* 0x000fca0000000000 */
/*0510*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0005e8000c101b04 */
/*0520*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x001ee2000c1e1b00 */
/*0530*/ FADD R14, R12, R14 ; /* 0x0000000e0c0e7221 */
/* 0x000fe40000000000 */
/*0540*/ FADD R16, R13, R15 ; /* 0x0000000f0d107221 */
/* 0x000fe40000000000 */
/*0550*/ FADD R14, R14, R10 ; /* 0x0000000a0e0e7221 */
/* 0x008fe40000000000 */
/*0560*/ FADD R15, R11, R16 ; /* 0x000000100b0f7221 */
/* 0x000fca0000000000 */
/*0570*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0001e8000c101b04 */
/*0580*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x002ee2000c1e1b00 */
/*0590*/ FADD R10, R8, R10 ; /* 0x0000000a080a7221 */
/* 0x000fe40000000000 */
/*05a0*/ FADD R16, R9, R11 ; /* 0x0000000b09107221 */
/* 0x000fe40000000000 */
/*05b0*/ FADD R10, R10, R12 ; /* 0x0000000c0a0a7221 */
/* 0x008fe40000000000 */
/*05c0*/ FADD R11, R13, R16 ; /* 0x000000100d0b7221 */
/* 0x000fca0000000000 */
/*05d0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0003e8000c101b04 */
/*05e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x004ea2000c1e1b00 */
/*05f0*/ FADD R12, R14, R12 ; /* 0x0000000c0e0c7221 */
/* 0x000fe40000000000 */
/*0600*/ FADD R16, R15, R13 ; /* 0x0000000d0f107221 */
/* 0x000fe40000000000 */
/*0610*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*0620*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0630*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0005e8000c101b04 */
/*0640*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x001ee2000c1e1b00 */
/*0650*/ FADD R8, R10, R8 ; /* 0x000000080a087221 */
/* 0x000fe40000000000 */
/*0660*/ FADD R16, R11, R9 ; /* 0x000000090b107221 */
/* 0x000fe40000000000 */
/*0670*/ FADD R8, R8, R14 ; /* 0x0000000e08087221 */
/* 0x008fe40000000000 */
/*0680*/ FADD R9, R15, R16 ; /* 0x000000100f097221 */
/* 0x000fca0000000000 */
/*0690*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b04 */
/*06a0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x002ee2000c1e1b00 */
/*06b0*/ FADD R14, R12, R14 ; /* 0x0000000e0c0e7221 */
/* 0x000fe40000000000 */
/*06c0*/ FADD R16, R13, R15 ; /* 0x0000000f0d107221 */
/* 0x000fe40000000000 */
/*06d0*/ FADD R14, R14, R10 ; /* 0x0000000a0e0e7221 */
/* 0x008fe40000000000 */
/*06e0*/ FADD R15, R11, R16 ; /* 0x000000100b0f7221 */
/* 0x000fca0000000000 */
/*06f0*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0003e8000c101b04 */
/*0700*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x004ea2000c1e1b00 */
/*0710*/ FADD R7, R8, R10 ; /* 0x0000000a08077221 */
/* 0x000fe40000000000 */
/*0720*/ FADD R10, R9, R11 ; /* 0x0000000b090a7221 */
/* 0x000fe40000000000 */
/*0730*/ FADD R16, R12, R7 ; /* 0x000000070c107221 */
/* 0x004fe40000000000 */
/*0740*/ FADD R17, R13, R10 ; /* 0x0000000a0d117221 */
/* 0x000fca0000000000 */
/*0750*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0005e8000c101b04 */
/*0760*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ee2000c1e1b00 */
/*0770*/ FADD R12, R14, R12 ; /* 0x0000000c0e0c7221 */
/* 0x000fe40000000000 */
/*0780*/ FADD R10, R15, R13 ; /* 0x0000000d0f0a7221 */
/* 0x000fe40000000000 */
/*0790*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*07a0*/ FADD R13, R9, R10 ; /* 0x0000000a090d7221 */
/* 0x000fca0000000000 */
/*07b0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0001e8000c101b04 */
/*07c0*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ee2000c1e1b00 */
/*07d0*/ FADD R8, R16, R8 ; /* 0x0000000810087221 */
/* 0x000fe40000000000 */
/*07e0*/ FADD R14, R17, R9 ; /* 0x00000009110e7221 */
/* 0x002fe40000000000 */
/*07f0*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x008fe40000000000 */
/*0800*/ FADD R9, R11, R14 ; /* 0x0000000e0b097221 */
/* 0x000fca0000000000 */
/*0810*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003e8000c101b04 */
/*0820*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ee2000c1e1b00 */
/*0830*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0840*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x004fe40000000000 */
/*0850*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*0860*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*0870*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0005e8000c101b04 */
/*0880*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x001ee2000c1e1b00 */
/*0890*/ FADD R14, R8, R14 ; /* 0x0000000e080e7221 */
/* 0x000fe40000000000 */
/*08a0*/ FADD R16, R9, R15 ; /* 0x0000000f09107221 */
/* 0x000fe40000000000 */
/*08b0*/ FADD R14, R14, R12 ; /* 0x0000000c0e0e7221 */
/* 0x008fe40000000000 */
/*08c0*/ FADD R15, R13, R16 ; /* 0x000000100d0f7221 */
/* 0x000fca0000000000 */
/*08d0*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0001e8000c101b04 */
/*08e0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x002ee2000c1e1b00 */
/*08f0*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0900*/ FADD R16, R11, R13 ; /* 0x0000000d0b107221 */
/* 0x000fe40000000000 */
/*0910*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*0920*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0930*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003e8000c101b04 */
/*0940*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x004ea2000c1e1b00 */
/*0950*/ FADD R8, R14, R8 ; /* 0x000000080e087221 */
/* 0x000fe40000000000 */
/*0960*/ FADD R16, R15, R9 ; /* 0x000000090f107221 */
/* 0x000fe40000000000 */
/*0970*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x004fe40000000000 */
/*0980*/ FADD R9, R11, R16 ; /* 0x000000100b097221 */
/* 0x000fca0000000000 */
/*0990*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0005e8000c101b04 */
/*09a0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x001ee2000c1e1b00 */
/*09b0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*09c0*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x000fe40000000000 */
/*09d0*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*09e0*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*09f0*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0001e8000c101b04 */
/*0a00*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x002ee2000c1e1b00 */
/*0a10*/ FADD R7, R8, R14 ; /* 0x0000000e08077221 */
/* 0x000fe40000000000 */
/*0a20*/ FADD R14, R9, R15 ; /* 0x0000000f090e7221 */
/* 0x000fe40000000000 */
/*0a30*/ FADD R16, R12, R7 ; /* 0x000000070c107221 */
/* 0x008fe40000000000 */
/*0a40*/ FADD R17, R13, R14 ; /* 0x0000000e0d117221 */
/* 0x000fca0000000000 */
/*0a50*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0003e8000c101b04 */
/*0a60*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x004ea2000c1e1b00 */
/*0a70*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0a80*/ FADD R14, R11, R13 ; /* 0x0000000d0b0e7221 */
/* 0x000fe40000000000 */
/*0a90*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*0aa0*/ FADD R13, R9, R14 ; /* 0x0000000e090d7221 */
/* 0x000fca0000000000 */
/*0ab0*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0005e8000c101b04 */
/*0ac0*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x001ee2000c1e1b00 */
/*0ad0*/ FADD R8, R16, R8 ; /* 0x0000000810087221 */
/* 0x000fe40000000000 */
/*0ae0*/ FADD R14, R17, R9 ; /* 0x00000009110e7221 */
/* 0x000fe40000000000 */
/*0af0*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x008fe40000000000 */
/*0b00*/ FADD R9, R11, R14 ; /* 0x0000000e0b097221 */
/* 0x000fca0000000000 */
/*0b10*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0001e8000c101b04 */
/*0b20*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ee2000c1e1b00 */
/*0b30*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0b40*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x002fe40000000000 */
/*0b50*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*0b60*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*0b70*/ STG.E.64 [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x0003e8000c101b04 */
/*0b80*/ LDG.E.64 R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x004ea2000c1e1b00 */
/*0b90*/ FADD R14, R8, R14 ; /* 0x0000000e080e7221 */
/* 0x000fe40000000000 */
/*0ba0*/ FADD R16, R9, R15 ; /* 0x0000000f09107221 */
/* 0x000fe40000000000 */
/*0bb0*/ FADD R14, R14, R12 ; /* 0x0000000c0e0e7221 */
/* 0x004fe40000000000 */
/*0bc0*/ FADD R15, R13, R16 ; /* 0x000000100d0f7221 */
/* 0x000fca0000000000 */
/*0bd0*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0005e8000c101b04 */
/*0be0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x001ee2000c1e1b00 */
/*0bf0*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0c00*/ FADD R16, R11, R13 ; /* 0x0000000d0b107221 */
/* 0x000fe40000000000 */
/*0c10*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x008fe40000000000 */
/*0c20*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0c30*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0001e8000c101b04 */
/*0c40*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x002ee2000c1e1b00 */
/*0c50*/ FADD R8, R14, R8 ; /* 0x000000080e087221 */
/* 0x000fe40000000000 */
/*0c60*/ FADD R18, R15, R9 ; /* 0x000000090f127221 */
/* 0x000fe40000000000 */
/*0c70*/ FADD R16, R8, R10 ; /* 0x0000000a08107221 */
/* 0x008fe40000000000 */
/*0c80*/ FADD R17, R11, R18 ; /* 0x000000120b117221 */
/* 0x000fca0000000000 */
/*0c90*/ STG.E.64 [R4.64], R16 ; /* 0x0000001004007986 */
/* 0x0003e8000c101b04 */
/*0ca0*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x004ea2000c1e1b00 */
/*0cb0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0cc0*/ FADD R8, R13, R11 ; /* 0x0000000b0d087221 */
/* 0x000fe40000000000 */
/*0cd0*/ FADD R18, R10, R14 ; /* 0x0000000e0a127221 */
/* 0x004fe40000000000 */
/*0ce0*/ FADD R19, R15, R8 ; /* 0x000000080f137221 */
/* 0x000fca0000000000 */
/*0cf0*/ STG.E.64 [R4.64+0x8], R18 ; /* 0x0000081204007986 */
/* 0x000fe8000c101b04 */
/*0d00*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x000e22000c1e1b00 */
/*0d10*/ FADD R7, R16, R14 ; /* 0x0000000e10077221 */
/* 0x000fe40000000000 */
/*0d20*/ FADD R10, R17, R15 ; /* 0x0000000f110a7221 */
/* 0x000fe40000000000 */
/*0d30*/ FADD R12, R8, R7 ; /* 0x00000007080c7221 */
/* 0x001fe40000000000 */
/*0d40*/ FADD R13, R9, R10 ; /* 0x0000000a090d7221 */
/* 0x000fca0000000000 */
/*0d50*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0001e8000c101b04 */
/*0d60*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1b00 */
/*0d70*/ FADD R8, R8, R18 ; /* 0x0000001208087221 */
/* 0x000fe40000000000 */
/*0d80*/ FADD R14, R9, R19 ; /* 0x00000013090e7221 */
/* 0x000fe40000000000 */
/*0d90*/ FADD R8, R8, R10 ; /* 0x0000000a08087221 */
/* 0x004fe40000000000 */
/*0da0*/ FADD R9, R11, R14 ; /* 0x0000000e0b097221 */
/* 0x000fca0000000000 */
/*0db0*/ STG.E.64 [R4.64+0x8], R8 ; /* 0x0000080804007986 */
/* 0x0005e8000c101b04 */
/*0dc0*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ee2000c1e1b00 */
/*0dd0*/ FADD R10, R12, R10 ; /* 0x0000000a0c0a7221 */
/* 0x000fe40000000000 */
/*0de0*/ FADD R16, R13, R11 ; /* 0x0000000b0d107221 */
/* 0x002fe40000000000 */
/*0df0*/ FADD R10, R10, R14 ; /* 0x0000000e0a0a7221 */
/* 0x008fe40000000000 */
/*0e00*/ FADD R11, R15, R16 ; /* 0x000000100f0b7221 */
/* 0x000fca0000000000 */
/*0e10*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0003e8000c101b04 */
/*0e20*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x001ee2000c1e1b00 */
/*0e30*/ FADD R14, R8, R14 ; /* 0x0000000e080e7221 */
/* 0x000fe40000000000 */
/*0e40*/ FADD R16, R9, R15 ; /* 0x0000000f09107221 */
/* 0x000fe40000000000 */
/*0e50*/ FADD R14, R14, R12 ; /* 0x0000000c0e0e7221 */
/* 0x008fe40000000000 */
/*0e60*/ FADD R15, R13, R16 ; /* 0x000000100d0f7221 */
/* 0x000fca0000000000 */
/*0e70*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0001e8000c101b04 */
/*0e80*/ LDG.E.64 R8, [R2.64+0x8] ; /* 0x0000080402087981 */
/* 0x004ea2000c1e1b00 */
/*0e90*/ FADD R12, R10, R12 ; /* 0x0000000c0a0c7221 */
/* 0x000fe40000000000 */
/*0ea0*/ FADD R16, R11, R13 ; /* 0x0000000d0b107221 */
/* 0x000fe40000000000 */
/*0eb0*/ FADD R12, R12, R8 ; /* 0x000000080c0c7221 */
/* 0x004fe40000000000 */
/*0ec0*/ FADD R13, R9, R16 ; /* 0x00000010090d7221 */
/* 0x000fca0000000000 */
/*0ed0*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0005e8000c101b04 */
/*0ee0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x002ee2000c1e1b00 */
/*0ef0*/ FADD R8, R14, R8 ; /* 0x000000080e087221 */
/* 0x000fe40000000000 */
/*0f00*/ FADD R16, R15, R9 ; /* 0x000000090f107221 */
/* 0x000fe40000000000 */
/*0f10*/ FADD R18, R8, R10 ; /* 0x0000000a08127221 */
/* 0x008fe40000000000 */
/*0f20*/ FADD R19, R11, R16 ; /* 0x000000100b137221 */
/* 0x000fca0000000000 */
/*0f30*/ STG.E.64 [R4.64+0x8], R18 ; /* 0x0000081204007986 */
/* 0x0003e8000c101b04 */
/*0f40*/ LDG.E.64 R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x001ee2000c1e1b00 */
/*0f50*/ FADD R8, R12, R10 ; /* 0x0000000a0c087221 */
/* 0x000fe40000000000 */
/*0f60*/ FADD R10, R13, R11 ; /* 0x0000000b0d0a7221 */
/* 0x000fe40000000000 */
/*0f70*/ FADD R8, R8, R14 ; /* 0x0000000e08087221 */
/* 0x008fe40000000000 */
/*0f80*/ FADD R9, R15, R10 ; /* 0x0000000a0f097221 */
/* 0x000fca0000000000 */
/*0f90*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0003e8000c101b04 */
/*0fa0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea2000c1e1b00 */
/*0fb0*/ FADD R7, R18, R14 ; /* 0x0000000e12077221 */
/* 0x000fe20000000000 */
/*0fc0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe20007ffe0ff */
/*0fd0*/ FADD R14, R19, R15 ; /* 0x0000000f130e7221 */
/* 0x000fc60000000000 */
/*0fe0*/ ISETP.NE.AND P0, PT, R6, 0x24, PT ; /* 0x000000240600780c */
/* 0x000fe20003f05270 */
/*0ff0*/ FADD R12, R7, R10 ; /* 0x0000000a070c7221 */
/* 0x004fe40000000000 */
/*1000*/ FADD R13, R11, R14 ; /* 0x0000000e0b0d7221 */
/* 0x000fca0000000000 */
/*1010*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x0003ea000c101b04 */
/*1020*/ @P0 BRA 0x400 ; /* 0xfffff3d000000947 */
/* 0x000fea000383ffff */
/*1030*/ @P1 CALL.REL.NOINC 0x1050 ; /* 0x0000001000001944 */
/* 0x000fe20003c00000 */
/*1040*/ BRA 0x70 ; /* 0xfffff02000007947 */
/* 0x000fea000383ffff */
/*1050*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1060*/ BRA 0x1060; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiP15HIP_vector_typeIfLj4EES1_
.globl _Z3addiP15HIP_vector_typeIfLj4EES1_
.p2align 8
.type _Z3addiP15HIP_vector_typeIfLj4EES1_,@function
_Z3addiP15HIP_vector_typeIfLj4EES1_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s7, 36
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
global_load_b128 v[6:9], v[4:5], off
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v10, v[2:3], off offset:8
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s7, 0
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v6
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v10
global_store_b32 v[4:5], v0, off
s_clause 0x1
global_load_b32 v0, v[2:3], off offset:4
global_load_b32 v6, v[2:3], off offset:12
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off offset:4
s_clause 0x1
global_load_b32 v0, v[2:3], off offset:8
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off offset:8
s_clause 0x1
global_load_b32 v0, v[2:3], off offset:12
global_load_b32 v6, v[2:3], off offset:4
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off offset:12
s_cbranch_scc0 .LBB0_3
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiP15HIP_vector_typeIfLj4EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiP15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z3addiP15HIP_vector_typeIfLj4EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiP15HIP_vector_typeIfLj4EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiP15HIP_vector_typeIfLj4EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006b951_00000000-6_add_2_4.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
.type _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_, @function
_Z32__device_stub__Z3addiP6float4S0_iP6float4S0_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiP6float4S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_, .-_Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
.globl _Z3addiP6float4S0_
.type _Z3addiP6float4S0_, @function
_Z3addiP6float4S0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiP6float4S0_, .-_Z3addiP6float4S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 16(%rsp), %rdx
movss %xmm1, 4(%rdx,%rax)
movq %rax, %rdx
addq 16(%rsp), %rdx
movss %xmm1, 8(%rdx)
movss %xmm1, 12(%rdx)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, 4(%rdx,%rax)
movq %rax, %rdx
addq 24(%rsp), %rdx
movss %xmm0, 8(%rdx)
movss %xmm0, 12(%rdx)
addq $16, %rax
cmpq $16777216, %rax
jne .L12
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 16777216(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movaps %xmm0, %xmm1
movss 4(%rbx), %xmm2
subss .LC3(%rip), %xmm2
andps .LC4(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movss 8(%rbx), %xmm1
subss .LC3(%rip), %xmm1
andps .LC4(%rip), %xmm1
call fmaxf@PLT
movss 12(%rbx), %xmm1
subss .LC3(%rip), %xmm1
andps .LC4(%rip), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $16, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z32__device_stub__Z3addiP6float4S0_iP6float4S0_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiP6float4S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiP6float4S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_2_4.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_ # -- Begin function _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.p2align 4, 0x90
.type _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_,@function
_Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_: # @_Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiP15HIP_vector_typeIfLj4EES1_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0800000 # float -4
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rcx
movl $1065353216, (%rcx,%rax) # imm = 0x3F800000
movq 16(%rsp), %rcx
movl $1065353216, 4(%rcx,%rax) # imm = 0x3F800000
movq 16(%rsp), %rcx
movl $1065353216, 8(%rcx,%rax) # imm = 0x3F800000
movq 16(%rsp), %rcx
movl $1065353216, 12(%rcx,%rax) # imm = 0x3F800000
movq 8(%rsp), %rcx
movl $1073741824, (%rcx,%rax) # imm = 0x40000000
movq 8(%rsp), %rcx
movl $1073741824, 4(%rcx,%rax) # imm = 0x40000000
movq 8(%rsp), %rcx
movl $1073741824, 8(%rcx,%rax) # imm = 0x40000000
movq 8(%rsp), %rcx
movl $1073741824, 12(%rcx,%rax) # imm = 0x40000000
addq $16, %rax
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiP15HIP_vector_typeIfLj4EES1_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
movss 4(%rcx,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 8(%rcx,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
movss 12(%rcx,%rax), %xmm2 # xmm2 = mem[0],zero,zero,zero
addss %xmm0, %xmm2
andps %xmm1, %xmm2
movaps %xmm2, %xmm3
maxss %xmm5, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andnps %xmm3, %xmm4
andps %xmm2, %xmm5
orps %xmm4, %xmm5
addq $16, %rax
movaps %xmm5, %xmm2
cmpq $16777216, %rax # imm = 0x1000000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiP15HIP_vector_typeIfLj4EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiP15HIP_vector_typeIfLj4EES1_,@object # @_Z3addiP15HIP_vector_typeIfLj4EES1_
.section .rodata,"a",@progbits
.globl _Z3addiP15HIP_vector_typeIfLj4EES1_
.p2align 3, 0x0
_Z3addiP15HIP_vector_typeIfLj4EES1_:
.quad _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.size _Z3addiP15HIP_vector_typeIfLj4EES1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiP15HIP_vector_typeIfLj4EES1_"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiP15HIP_vector_typeIfLj4EES1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiP15HIP_vector_typeIfLj4EES1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <string.h>
#include <ctype.h>
#include <limits.h>
#define INPUT_FILE "inp.txt"
#define Q1A_OUT_FILE "q1a.txt"
#define Q1B_OUT_FILE "q1b.txt"
typedef struct vector {
int *elements;
int capacity;
int size;
} vector;
// Method definitions
void int_vector_init(vector *vector);
int int_vector_add(vector* vector, int element);
void int_vector_free(vector *vector);
int chopString(char *buf, size_t size);
int findMin(vector* vector);
// PART A
__global__ void global_reduce_kernel(int * d_out, int * d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s && myId + s < size) {
// d_in[myId] += d_in[myId + s];
if(d_in[myId+s] < d_in[myId]) {
d_in[myId] = d_in[myId+s];
}
}
__syncthreads(); // make sure all moves at one stage are done!
}
// only thread 0 writes result for this block back to global mem
if (tid == 0) {
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int * d_out, int * d_intermediate, int * d_in,
int size, bool usesSharedMemory) {
// assumes that size is not greater than maxThreadsPerBlock^2
// and that size is a multiple of maxThreadsPerBlock
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
global_reduce_kernel<<<blocks, threads>>>
(d_intermediate, d_in, size);
int powerOfTwo = 1;
while (powerOfTwo < blocks) {
powerOfTwo *= 2;
}
// now we're down to one block left, so reduce it
int newSize = blocks;
threads = powerOfTwo; // launch one thread for each block in prev step
blocks = 1;
global_reduce_kernel<<<blocks, threads>>>
(d_out, d_intermediate, newSize);
}
// PART B
__global__ void partb(int* d_out, int* d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if (myId < size) {
int f = d_in[myId];
d_out[myId] = f % 10;
}
}
int main(int argc, char ** argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
FILE *fp;
if((fp = fopen(INPUT_FILE, "r")) == 0) {
printf("%s cannot be found\n", INPUT_FILE);
exit(-1);
}
char separators[] = " ,";
char buf[100];
char* token;
int offset = 0;
vector *a = (vector*) malloc(sizeof (vector));
int_vector_init(a);
while(fgets(buf + offset, sizeof buf - offset, fp) != NULL) {
//chop off number from string if it ends with digit
offset = chopString(buf, sizeof buf);
int indexOfLastNum = sizeof buf - offset - 1;// -1 to not copy '\0'
//printf("buffer: %s\n", buf);
token = strtok(buf, separators);
while (token != NULL) {
int num = atoi(token);
//printf("%d\n", num);
int_vector_add(a, num);
token = strtok(NULL, separators);
}
memcpy(buf, &buf[indexOfLastNum], offset);
}
int min = findMin(a);
const int ARRAY_BYTES = sizeof(int) * a->size;
// declare GPU memory pointers
int * d_in, * d_in_b, * d_intermediate, * d_out, * d_out_b;
// allocate GPU memory
cudaMalloc((void **) &d_in_b, ARRAY_BYTES);
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_intermediate, ARRAY_BYTES); // overallocated
cudaMalloc((void **) &d_out_b, ARRAY_BYTES);
cudaMalloc((void **) &d_out, sizeof(int));
// transfer the input array to the GPU
cudaMemcpy(d_in, a->elements, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_in_b, a->elements, ARRAY_BYTES, cudaMemcpyHostToDevice);
int whichKernel = 0;
if (argc == 2) {
whichKernel = atoi(argv[1]);
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// launch the kernel
switch(whichKernel) {
case 0:
//printf("Running global reduce\n");
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, false);
cudaEventRecord(stop, 0);
break;
case 1:
//printf("Running reduce with shared mem\n");
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, true);
cudaEventRecord(stop, 0);
break;
default:
fprintf(stderr, "error: ran no kernel\n");
exit(EXIT_FAILURE);
}
// PART B
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (a->size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
partb<<<blocks, threads>>>(d_out_b, d_in_b, a->size);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
// copy back the sum from GPU
int h_out;
cudaMemcpy(&h_out, d_out, sizeof(int), cudaMemcpyDeviceToHost);
int h_out_b[a->size];
cudaMemcpy(h_out_b, d_out_b, ARRAY_BYTES, cudaMemcpyDeviceToHost);
//printf("average time elapsed: %f\n", elapsedTime);
FILE *outFp = fopen(Q1A_OUT_FILE, "w");
if(outFp == NULL) {
printf("can't open file %s to write\n", Q1A_OUT_FILE);
}
fprintf(outFp, "%d\n", h_out);
fclose(outFp);
FILE *outFpB = fopen(Q1B_OUT_FILE, "w");
if (outFpB == NULL) {
printf("can't open file %s to write\n", Q1B_OUT_FILE);
}
bool first = true;
for (int i = 0; i < a->size; i++) {
if (first) {
fprintf(outFpB, "%d", h_out_b[i]);
first = false;
} else {
fprintf(outFpB, ",%d", h_out_b[i]);
}
}
fclose(outFpB);
int_vector_free(a);
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
cudaFree(d_out_b);
return 0;
}
void int_vector_init(vector *vector) {
if(vector == NULL)
{
return;
}
vector -> elements = (int*)malloc(sizeof( int));
vector -> capacity = 1;
vector -> size = 0;
}
int int_vector_add(vector* vector, int element) {
if(vector->size + 1 == vector->capacity)
{
int *temp = (int*)realloc(vector->elements, vector->capacity*2 * sizeof (int));
if(temp == NULL)
{
return 0;
}
vector -> capacity *= 2;
vector -> elements = temp;
}
vector -> elements[vector->size] = element;
vector -> size += 1;
return 1;
}
void int_vector_free(vector *vector){
free(vector->elements);
free(vector);
}
//assumes vector size >= 1
int findMin(vector* vector) {
int min = INT_MAX;
if(vector == NULL)
{
return min;
}
int size = vector->size;
int* arr = vector->elements;
for(int i = 0; i < size; i++)
{
if(arr[i] < min)
{
min = arr[i];
}
}
return min;
}
//returns offset - difference between size and index of last number and offset
int chopString(char *buf, size_t size){
int offset = 0;
int indexOfLastNum = size-2;
if(isdigit(buf[size-2]))
{
int index = size-2;
while(isdigit(buf[index]) && index > 0)
{
index--;
}
buf[index] = '\0';
indexOfLastNum = index+1;
offset = size - indexOfLastNum -1;//-1 to not copy '\0'
} else
{
offset = 0;
}
return offset;
} | code for sm_80
Function : _Z5partbPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.HI R0, R2, 0x66666667, RZ ; /* 0x6666666702007827 */
/* 0x004fca00078e02ff */
/*00b0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*00c0*/ LEA.HI.SX32 R7, R0, R5, 0x1e ; /* 0x0000000500077211 */
/* 0x000fe200078ff2ff */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R7, R7, -0xa, R2 ; /* 0xfffffff607077824 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20global_reduce_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fc800078e0208 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x1b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x000fe2000fffe0ff */
/*00c0*/ BSSY B0, 0x170 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f06070 */
/*00e0*/ ISETP.GE.U32.OR P0, PT, R8, UR4, P0 ; /* 0x0000000408007c0c */
/* 0x000fda0008706470 */
/*00f0*/ @P0 BRA 0x160 ; /* 0x0000006000000947 */
/* 0x001fea0003800000 */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0110*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000eb2000c1e1900 */
/*0120*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0005 */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GE.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e4000c101906 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fea0000010000 */
/*0190*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01a0*/ @P0 BRA 0xb0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*01b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R4, R7, R4, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fca00078e0004 */
/*0200*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <string.h>
#include <ctype.h>
#include <limits.h>
#define INPUT_FILE "inp.txt"
#define Q1A_OUT_FILE "q1a.txt"
#define Q1B_OUT_FILE "q1b.txt"
typedef struct vector {
int *elements;
int capacity;
int size;
} vector;
// Method definitions
void int_vector_init(vector *vector);
int int_vector_add(vector* vector, int element);
void int_vector_free(vector *vector);
int chopString(char *buf, size_t size);
int findMin(vector* vector);
// PART A
__global__ void global_reduce_kernel(int * d_out, int * d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s && myId + s < size) {
// d_in[myId] += d_in[myId + s];
if(d_in[myId+s] < d_in[myId]) {
d_in[myId] = d_in[myId+s];
}
}
__syncthreads(); // make sure all moves at one stage are done!
}
// only thread 0 writes result for this block back to global mem
if (tid == 0) {
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int * d_out, int * d_intermediate, int * d_in,
int size, bool usesSharedMemory) {
// assumes that size is not greater than maxThreadsPerBlock^2
// and that size is a multiple of maxThreadsPerBlock
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
global_reduce_kernel<<<blocks, threads>>>
(d_intermediate, d_in, size);
int powerOfTwo = 1;
while (powerOfTwo < blocks) {
powerOfTwo *= 2;
}
// now we're down to one block left, so reduce it
int newSize = blocks;
threads = powerOfTwo; // launch one thread for each block in prev step
blocks = 1;
global_reduce_kernel<<<blocks, threads>>>
(d_out, d_intermediate, newSize);
}
// PART B
__global__ void partb(int* d_out, int* d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if (myId < size) {
int f = d_in[myId];
d_out[myId] = f % 10;
}
}
int main(int argc, char ** argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
FILE *fp;
if((fp = fopen(INPUT_FILE, "r")) == 0) {
printf("%s cannot be found\n", INPUT_FILE);
exit(-1);
}
char separators[] = " ,";
char buf[100];
char* token;
int offset = 0;
vector *a = (vector*) malloc(sizeof (vector));
int_vector_init(a);
while(fgets(buf + offset, sizeof buf - offset, fp) != NULL) {
//chop off number from string if it ends with digit
offset = chopString(buf, sizeof buf);
int indexOfLastNum = sizeof buf - offset - 1;// -1 to not copy '\0'
//printf("buffer: %s\n", buf);
token = strtok(buf, separators);
while (token != NULL) {
int num = atoi(token);
//printf("%d\n", num);
int_vector_add(a, num);
token = strtok(NULL, separators);
}
memcpy(buf, &buf[indexOfLastNum], offset);
}
int min = findMin(a);
const int ARRAY_BYTES = sizeof(int) * a->size;
// declare GPU memory pointers
int * d_in, * d_in_b, * d_intermediate, * d_out, * d_out_b;
// allocate GPU memory
cudaMalloc((void **) &d_in_b, ARRAY_BYTES);
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_intermediate, ARRAY_BYTES); // overallocated
cudaMalloc((void **) &d_out_b, ARRAY_BYTES);
cudaMalloc((void **) &d_out, sizeof(int));
// transfer the input array to the GPU
cudaMemcpy(d_in, a->elements, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_in_b, a->elements, ARRAY_BYTES, cudaMemcpyHostToDevice);
int whichKernel = 0;
if (argc == 2) {
whichKernel = atoi(argv[1]);
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// launch the kernel
switch(whichKernel) {
case 0:
//printf("Running global reduce\n");
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, false);
cudaEventRecord(stop, 0);
break;
case 1:
//printf("Running reduce with shared mem\n");
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, true);
cudaEventRecord(stop, 0);
break;
default:
fprintf(stderr, "error: ran no kernel\n");
exit(EXIT_FAILURE);
}
// PART B
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (a->size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
partb<<<blocks, threads>>>(d_out_b, d_in_b, a->size);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
// copy back the sum from GPU
int h_out;
cudaMemcpy(&h_out, d_out, sizeof(int), cudaMemcpyDeviceToHost);
int h_out_b[a->size];
cudaMemcpy(h_out_b, d_out_b, ARRAY_BYTES, cudaMemcpyDeviceToHost);
//printf("average time elapsed: %f\n", elapsedTime);
FILE *outFp = fopen(Q1A_OUT_FILE, "w");
if(outFp == NULL) {
printf("can't open file %s to write\n", Q1A_OUT_FILE);
}
fprintf(outFp, "%d\n", h_out);
fclose(outFp);
FILE *outFpB = fopen(Q1B_OUT_FILE, "w");
if (outFpB == NULL) {
printf("can't open file %s to write\n", Q1B_OUT_FILE);
}
bool first = true;
for (int i = 0; i < a->size; i++) {
if (first) {
fprintf(outFpB, "%d", h_out_b[i]);
first = false;
} else {
fprintf(outFpB, ",%d", h_out_b[i]);
}
}
fclose(outFpB);
int_vector_free(a);
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
cudaFree(d_out_b);
return 0;
}
void int_vector_init(vector *vector) {
if(vector == NULL)
{
return;
}
vector -> elements = (int*)malloc(sizeof( int));
vector -> capacity = 1;
vector -> size = 0;
}
int int_vector_add(vector* vector, int element) {
if(vector->size + 1 == vector->capacity)
{
int *temp = (int*)realloc(vector->elements, vector->capacity*2 * sizeof (int));
if(temp == NULL)
{
return 0;
}
vector -> capacity *= 2;
vector -> elements = temp;
}
vector -> elements[vector->size] = element;
vector -> size += 1;
return 1;
}
void int_vector_free(vector *vector){
free(vector->elements);
free(vector);
}
//assumes vector size >= 1
int findMin(vector* vector) {
int min = INT_MAX;
if(vector == NULL)
{
return min;
}
int size = vector->size;
int* arr = vector->elements;
for(int i = 0; i < size; i++)
{
if(arr[i] < min)
{
min = arr[i];
}
}
return min;
}
//returns offset - difference between size and index of last number and offset
int chopString(char *buf, size_t size){
int offset = 0;
int indexOfLastNum = size-2;
if(isdigit(buf[size-2]))
{
int index = size-2;
while(isdigit(buf[index]) && index > 0)
{
index--;
}
buf[index] = '\0';
indexOfLastNum = index+1;
offset = size - indexOfLastNum -1;//-1 to not copy '\0'
} else
{
offset = 0;
}
return offset;
} | .file "tmpxft_000ef479_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15int_vector_initP6vector
.type _Z15int_vector_initP6vector, @function
_Z15int_vector_initP6vector:
.LFB2059:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L6
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, (%rbx)
movl $1, 8(%rbx)
movl $0, 12(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore 3
ret
.cfi_endproc
.LFE2059:
.size _Z15int_vector_initP6vector, .-_Z15int_vector_initP6vector
.globl _Z14int_vector_addP6vectori
.type _Z14int_vector_addP6vectori, @function
_Z14int_vector_addP6vectori:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
movl 8(%rdi), %edx
movl 12(%rdi), %eax
addl $1, %eax
cmpl %edx, %eax
je .L14
.L10:
movslq 12(%rbx), %rdx
movq (%rbx), %rax
movl %ebp, (%rax,%rdx,4)
addl $1, 12(%rbx)
movl $1, %eax
.L9:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leal (%rdx,%rdx), %esi
movslq %esi, %rsi
salq $2, %rsi
movq (%rdi), %rdi
call realloc@PLT
testq %rax, %rax
je .L12
sall 8(%rbx)
movq %rax, (%rbx)
jmp .L10
.L12:
movl $0, %eax
jmp .L9
.cfi_endproc
.LFE2060:
.size _Z14int_vector_addP6vectori, .-_Z14int_vector_addP6vectori
.globl _Z15int_vector_freeP6vector
.type _Z15int_vector_freeP6vector, @function
_Z15int_vector_freeP6vector:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z15int_vector_freeP6vector, .-_Z15int_vector_freeP6vector
.globl _Z7findMinP6vector
.type _Z7findMinP6vector, @function
_Z7findMinP6vector:
.LFB2062:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L20
movl 12(%rdi), %edx
movq (%rdi), %rcx
testl %edx, %edx
jle .L21
movq %rcx, %rax
movslq %edx, %rdx
leaq (%rcx,%rdx,4), %rsi
movl $2147483647, %edx
.L19:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovg %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L19
.L17:
movl %edx, %eax
ret
.L20:
movl $2147483647, %edx
jmp .L17
.L21:
movl $2147483647, %edx
jmp .L17
.cfi_endproc
.LFE2062:
.size _Z7findMinP6vector, .-_Z7findMinP6vector
.globl _Z10chopStringPcm
.type _Z10chopStringPcm, @function
_Z10chopStringPcm:
.LFB2063:
.cfi_startproc
endbr64
movsbl -2(%rdi,%rsi), %eax
subl $48, %eax
movl $0, %edx
cmpl $9, %eax
ja .L23
leal -2(%rsi), %edx
movslq %edx, %rcx
leaq (%rdi,%rcx), %r8
movsbl (%r8), %eax
subl $48, %eax
cmpl $9, %eax
ja .L25
testl %edx, %edx
jle .L25
leaq -1(%rdi,%rcx), %rcx
.L26:
subl $1, %edx
movq %rcx, %r8
subq $1, %rcx
movsbl (%r8), %eax
subl $48, %eax
cmpl $9, %eax
ja .L25
testl %edx, %edx
jg .L26
.L25:
movb $0, (%r8)
subl %edx, %esi
leal -2(%rsi), %edx
.L23:
movl %edx, %eax
ret
.cfi_endproc
.LFE2063:
.size _Z10chopStringPcm, .-_Z10chopStringPcm
.globl _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
.type _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i, @function
_Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20global_reduce_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i, .-_Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
.globl _Z20global_reduce_kernelPiS_i
.type _Z20global_reduce_kernelPiS_i, @function
_Z20global_reduce_kernelPiS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z20global_reduce_kernelPiS_i, .-_Z20global_reduce_kernelPiS_i
.globl _Z6reducePiS_S_ib
.type _Z6reducePiS_S_ib, @function
_Z6reducePiS_S_ib:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %r14
movl %ecx, %ebp
leal 2046(%rcx), %ebx
movl %ecx, %eax
addl $1023, %eax
cmovns %eax, %ebx
sarl $10, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L39:
cmpl $1024, %ebp
jle .L43
movl $1, %eax
.L41:
addl %eax, %eax
cmpl %eax, %ebx
jg .L41
.L40:
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L38:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movl %ebp, %edx
movq %r14, %rsi
movq %r12, %rdi
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
jmp .L39
.L43:
movl $1, %eax
jmp .L40
.L47:
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
jmp .L38
.cfi_endproc
.LFE2057:
.size _Z6reducePiS_S_ib, .-_Z6reducePiS_S_ib
.globl _Z27__device_stub__Z5partbPiS_iPiS_i
.type _Z27__device_stub__Z5partbPiS_iPiS_i, @function
_Z27__device_stub__Z5partbPiS_iPiS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5partbPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z27__device_stub__Z5partbPiS_iPiS_i, .-_Z27__device_stub__Z5partbPiS_iPiS_i
.globl _Z5partbPiS_i
.type _Z5partbPiS_i, @function
_Z5partbPiS_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5partbPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z5partbPiS_i, .-_Z5partbPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "error: no devices supporting CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "inp.txt"
.LC3:
.string "%s cannot be found\n"
.LC4:
.string "error: ran no kernel\n"
.LC5:
.string "w"
.LC6:
.string "q1a.txt"
.LC7:
.string "can't open file %s to write\n"
.LC8:
.string "%d\n"
.LC9:
.string "q1b.txt"
.LC10:
.string "%d"
.LC11:
.string ",%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -268(%rbp)
movq %rsi, -280(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -252(%rbp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, -252(%rbp)
je .L84
movl $0, %edi
call cudaSetDevice@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, -264(%rbp)
testq %rax, %rax
je .L85
movw $11296, -163(%rbp)
movb $0, -161(%rbp)
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rdi
call _Z15int_vector_initP6vector
movl $0, %r14d
movl $100, %r15d
jmp .L59
.L84:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
leaq .LC2(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L60:
movslq %r14d, %rdx
leaq -160(%rbp), %rdi
movslq %r13d, %rsi
addq %rdi, %rsi
movl $100, %ecx
call __memcpy_chk@PLT
.L59:
movslq %r14d, %rax
movl %r15d, %edx
subl %r14d, %edx
movl $100, %esi
cmpq %rsi, %rax
cmovnb %rax, %rsi
subq %rax, %rsi
leaq -160(%rbp,%rax), %rdi
movq -264(%rbp), %rcx
call __fgets_chk@PLT
testq %rax, %rax
je .L86
leaq -160(%rbp), %rbx
movl $100, %esi
movq %rbx, %rdi
call _Z10chopStringPcm
movl %eax, %r14d
movl $99, %r13d
subl %eax, %r13d
leaq -163(%rbp), %rsi
movq %rbx, %rdi
call strtok@PLT
movq %rax, %rdi
testq %rax, %rax
je .L60
leaq -163(%rbp), %rbx
.L61:
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %esi
movq %r12, %rdi
call _Z14int_vector_addP6vectori
movq %rbx, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %rdi
testq %rax, %rax
jne .L61
jmp .L60
.L86:
movl 12(%r12), %ebx
movslq %ebx, %r15
leal 0(,%rbx,4), %r13d
movslq %r13d, %r13
leaq -240(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -248(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -232(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -216(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -224(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq (%r12), %r14
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq -248(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq -240(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $2, -268(%rbp)
je .L87
leaq -208(%rbp), %rdi
call cudaEventCreate@PLT
leaq -200(%rbp), %rdi
call cudaEventCreate@PLT
.L64:
movl $0, %esi
movq -208(%rbp), %rdi
call cudaEventRecord@PLT
movl $0, %r8d
movl %ebx, %ecx
movq -248(%rbp), %rdx
movq -232(%rbp), %rsi
movq -224(%rbp), %rdi
call _Z6reducePiS_S_ib
movl $0, %esi
movq -200(%rbp), %rdi
call cudaEventRecord@PLT
.L67:
movl $1024, -176(%rbp)
movl $1, -172(%rbp)
movl $1, -168(%rbp)
leal 2046(%rbx), %eax
movl %ebx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, -188(%rbp)
movl $1, -184(%rbp)
movl $1, -180(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -176(%rbp), %rdx
movl $1, %ecx
movq -188(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L88
.L68:
movq -200(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -188(%rbp), %rdi
movq -200(%rbp), %rdx
movq -208(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq -176(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -224(%rbp), %rsi
call cudaMemcpy@PLT
salq $2, %r15
leaq 15(%r15), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L69:
cmpq %rdx, %rsp
je .L70
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L69
.L87:
movq -280(%rbp), %rax
movq 8(%rax), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
leaq -208(%rbp), %rdi
call cudaEventCreate@PLT
leaq -200(%rbp), %rdi
call cudaEventCreate@PLT
testl %r14d, %r14d
je .L64
cmpl $1, %r14d
jne .L89
movl $0, %esi
movq -208(%rbp), %rdi
call cudaEventRecord@PLT
movl $1, %r8d
movl %ebx, %ecx
movq -248(%rbp), %rdx
movq -232(%rbp), %rsi
movq -224(%rbp), %rdi
call _Z6reducePiS_S_ib
movl $0, %esi
movq -200(%rbp), %rdi
call cudaEventRecord@PLT
jmp .L67
.L89:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %ebx, %edx
movq -240(%rbp), %rsi
movq -216(%rbp), %rdi
call _Z27__device_stub__Z5partbPiS_iPiS_i
jmp .L68
.L70:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L71
orq $0, -8(%rsp,%rax)
.L71:
movq %rsp, %r14
movl $2, %ecx
movq %r13, %rdx
movq -216(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L90
.L72:
movl -176(%rbp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r13, %rdi
call fclose@PLT
leaq .LC5(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L91
.L73:
testl %ebx, %ebx
jle .L74
movq %r14, %rbx
addq %r15, %r14
movl $1, %eax
leaq .LC11(%rip), %r15
jmp .L77
.L90:
leaq .LC6(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L72
.L91:
leaq .LC9(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L73
.L75:
movl (%rbx), %ecx
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L76:
addq $4, %rbx
movl $0, %eax
cmpq %r14, %rbx
je .L74
.L77:
testb %al, %al
je .L75
movl (%rbx), %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L76
.L74:
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call _Z15int_vector_freeP6vector
movq -248(%rbp), %rdi
call cudaFree@PLT
movq -232(%rbp), %rdi
call cudaFree@PLT
movq -224(%rbp), %rdi
call cudaFree@PLT
movq -216(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L92
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L92:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z5partbPiS_i"
.LC13:
.string "_Z20global_reduce_kernelPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5partbPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z20global_reduce_kernelPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <string.h>
#include <ctype.h>
#include <limits.h>
#define INPUT_FILE "inp.txt"
#define Q1A_OUT_FILE "q1a.txt"
#define Q1B_OUT_FILE "q1b.txt"
typedef struct vector {
int *elements;
int capacity;
int size;
} vector;
// Method definitions
void int_vector_init(vector *vector);
int int_vector_add(vector* vector, int element);
void int_vector_free(vector *vector);
int chopString(char *buf, size_t size);
int findMin(vector* vector);
// PART A
__global__ void global_reduce_kernel(int * d_out, int * d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s && myId + s < size) {
// d_in[myId] += d_in[myId + s];
if(d_in[myId+s] < d_in[myId]) {
d_in[myId] = d_in[myId+s];
}
}
__syncthreads(); // make sure all moves at one stage are done!
}
// only thread 0 writes result for this block back to global mem
if (tid == 0) {
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int * d_out, int * d_intermediate, int * d_in,
int size, bool usesSharedMemory) {
// assumes that size is not greater than maxThreadsPerBlock^2
// and that size is a multiple of maxThreadsPerBlock
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
global_reduce_kernel<<<blocks, threads>>>
(d_intermediate, d_in, size);
int powerOfTwo = 1;
while (powerOfTwo < blocks) {
powerOfTwo *= 2;
}
// now we're down to one block left, so reduce it
int newSize = blocks;
threads = powerOfTwo; // launch one thread for each block in prev step
blocks = 1;
global_reduce_kernel<<<blocks, threads>>>
(d_out, d_intermediate, newSize);
}
// PART B
__global__ void partb(int* d_out, int* d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if (myId < size) {
int f = d_in[myId];
d_out[myId] = f % 10;
}
}
int main(int argc, char ** argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
FILE *fp;
if((fp = fopen(INPUT_FILE, "r")) == 0) {
printf("%s cannot be found\n", INPUT_FILE);
exit(-1);
}
char separators[] = " ,";
char buf[100];
char* token;
int offset = 0;
vector *a = (vector*) malloc(sizeof (vector));
int_vector_init(a);
while(fgets(buf + offset, sizeof buf - offset, fp) != NULL) {
//chop off number from string if it ends with digit
offset = chopString(buf, sizeof buf);
int indexOfLastNum = sizeof buf - offset - 1;// -1 to not copy '\0'
//printf("buffer: %s\n", buf);
token = strtok(buf, separators);
while (token != NULL) {
int num = atoi(token);
//printf("%d\n", num);
int_vector_add(a, num);
token = strtok(NULL, separators);
}
memcpy(buf, &buf[indexOfLastNum], offset);
}
int min = findMin(a);
const int ARRAY_BYTES = sizeof(int) * a->size;
// declare GPU memory pointers
int * d_in, * d_in_b, * d_intermediate, * d_out, * d_out_b;
// allocate GPU memory
cudaMalloc((void **) &d_in_b, ARRAY_BYTES);
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_intermediate, ARRAY_BYTES); // overallocated
cudaMalloc((void **) &d_out_b, ARRAY_BYTES);
cudaMalloc((void **) &d_out, sizeof(int));
// transfer the input array to the GPU
cudaMemcpy(d_in, a->elements, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_in_b, a->elements, ARRAY_BYTES, cudaMemcpyHostToDevice);
int whichKernel = 0;
if (argc == 2) {
whichKernel = atoi(argv[1]);
}
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// launch the kernel
switch(whichKernel) {
case 0:
//printf("Running global reduce\n");
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, false);
cudaEventRecord(stop, 0);
break;
case 1:
//printf("Running reduce with shared mem\n");
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, true);
cudaEventRecord(stop, 0);
break;
default:
fprintf(stderr, "error: ran no kernel\n");
exit(EXIT_FAILURE);
}
// PART B
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (a->size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
partb<<<blocks, threads>>>(d_out_b, d_in_b, a->size);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
// copy back the sum from GPU
int h_out;
cudaMemcpy(&h_out, d_out, sizeof(int), cudaMemcpyDeviceToHost);
int h_out_b[a->size];
cudaMemcpy(h_out_b, d_out_b, ARRAY_BYTES, cudaMemcpyDeviceToHost);
//printf("average time elapsed: %f\n", elapsedTime);
FILE *outFp = fopen(Q1A_OUT_FILE, "w");
if(outFp == NULL) {
printf("can't open file %s to write\n", Q1A_OUT_FILE);
}
fprintf(outFp, "%d\n", h_out);
fclose(outFp);
FILE *outFpB = fopen(Q1B_OUT_FILE, "w");
if (outFpB == NULL) {
printf("can't open file %s to write\n", Q1B_OUT_FILE);
}
bool first = true;
for (int i = 0; i < a->size; i++) {
if (first) {
fprintf(outFpB, "%d", h_out_b[i]);
first = false;
} else {
fprintf(outFpB, ",%d", h_out_b[i]);
}
}
fclose(outFpB);
int_vector_free(a);
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_intermediate);
cudaFree(d_out);
cudaFree(d_out_b);
return 0;
}
void int_vector_init(vector *vector) {
if(vector == NULL)
{
return;
}
vector -> elements = (int*)malloc(sizeof( int));
vector -> capacity = 1;
vector -> size = 0;
}
int int_vector_add(vector* vector, int element) {
if(vector->size + 1 == vector->capacity)
{
int *temp = (int*)realloc(vector->elements, vector->capacity*2 * sizeof (int));
if(temp == NULL)
{
return 0;
}
vector -> capacity *= 2;
vector -> elements = temp;
}
vector -> elements[vector->size] = element;
vector -> size += 1;
return 1;
}
void int_vector_free(vector *vector){
free(vector->elements);
free(vector);
}
//assumes vector size >= 1
int findMin(vector* vector) {
int min = INT_MAX;
if(vector == NULL)
{
return min;
}
int size = vector->size;
int* arr = vector->elements;
for(int i = 0; i < size; i++)
{
if(arr[i] < min)
{
min = arr[i];
}
}
return min;
}
//returns offset - difference between size and index of last number and offset
int chopString(char *buf, size_t size){
int offset = 0;
int indexOfLastNum = size-2;
if(isdigit(buf[size-2]))
{
int index = size-2;
while(isdigit(buf[index]) && index > 0)
{
index--;
}
buf[index] = '\0';
indexOfLastNum = index+1;
offset = size - indexOfLastNum -1;//-1 to not copy '\0'
} else
{
offset = 0;
}
return offset;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <ctype.h>
#include <limits.h>
#define INPUT_FILE "inp.txt"
#define Q1A_OUT_FILE "q1a.txt"
#define Q1B_OUT_FILE "q1b.txt"
typedef struct vector {
int *elements;
int capacity;
int size;
} vector;
// Method definitions
void int_vector_init(vector *vector);
int int_vector_add(vector* vector, int element);
void int_vector_free(vector *vector);
int chopString(char *buf, size_t size);
int findMin(vector* vector);
// PART A
__global__ void global_reduce_kernel(int * d_out, int * d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s && myId + s < size) {
// d_in[myId] += d_in[myId + s];
if(d_in[myId+s] < d_in[myId]) {
d_in[myId] = d_in[myId+s];
}
}
__syncthreads(); // make sure all moves at one stage are done!
}
// only thread 0 writes result for this block back to global mem
if (tid == 0) {
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int * d_out, int * d_intermediate, int * d_in,
int size, bool usesSharedMemory) {
// assumes that size is not greater than maxThreadsPerBlock^2
// and that size is a multiple of maxThreadsPerBlock
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
global_reduce_kernel<<<blocks, threads>>>
(d_intermediate, d_in, size);
int powerOfTwo = 1;
while (powerOfTwo < blocks) {
powerOfTwo *= 2;
}
// now we're down to one block left, so reduce it
int newSize = blocks;
threads = powerOfTwo; // launch one thread for each block in prev step
blocks = 1;
global_reduce_kernel<<<blocks, threads>>>
(d_out, d_intermediate, newSize);
}
// PART B
__global__ void partb(int* d_out, int* d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if (myId < size) {
int f = d_in[myId];
d_out[myId] = f % 10;
}
}
int main(int argc, char ** argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
FILE *fp;
if((fp = fopen(INPUT_FILE, "r")) == 0) {
printf("%s cannot be found\n", INPUT_FILE);
exit(-1);
}
char separators[] = " ,";
char buf[100];
char* token;
int offset = 0;
vector *a = (vector*) malloc(sizeof (vector));
int_vector_init(a);
while(fgets(buf + offset, sizeof buf - offset, fp) != NULL) {
//chop off number from string if it ends with digit
offset = chopString(buf, sizeof buf);
int indexOfLastNum = sizeof buf - offset - 1;// -1 to not copy '\0'
//printf("buffer: %s\n", buf);
token = strtok(buf, separators);
while (token != NULL) {
int num = atoi(token);
//printf("%d\n", num);
int_vector_add(a, num);
token = strtok(NULL, separators);
}
memcpy(buf, &buf[indexOfLastNum], offset);
}
int min = findMin(a);
const int ARRAY_BYTES = sizeof(int) * a->size;
// declare GPU memory pointers
int * d_in, * d_in_b, * d_intermediate, * d_out, * d_out_b;
// allocate GPU memory
hipMalloc((void **) &d_in_b, ARRAY_BYTES);
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_intermediate, ARRAY_BYTES); // overallocated
hipMalloc((void **) &d_out_b, ARRAY_BYTES);
hipMalloc((void **) &d_out, sizeof(int));
// transfer the input array to the GPU
hipMemcpy(d_in, a->elements, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_in_b, a->elements, ARRAY_BYTES, hipMemcpyHostToDevice);
int whichKernel = 0;
if (argc == 2) {
whichKernel = atoi(argv[1]);
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// launch the kernel
switch(whichKernel) {
case 0:
//printf("Running global reduce\n");
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, false);
hipEventRecord(stop, 0);
break;
case 1:
//printf("Running reduce with shared mem\n");
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, true);
hipEventRecord(stop, 0);
break;
default:
fprintf(stderr, "error: ran no kernel\n");
exit(EXIT_FAILURE);
}
// PART B
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (a->size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
partb<<<blocks, threads>>>(d_out_b, d_in_b, a->size);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
// copy back the sum from GPU
int h_out;
hipMemcpy(&h_out, d_out, sizeof(int), hipMemcpyDeviceToHost);
int h_out_b[a->size];
hipMemcpy(h_out_b, d_out_b, ARRAY_BYTES, hipMemcpyDeviceToHost);
//printf("average time elapsed: %f\n", elapsedTime);
FILE *outFp = fopen(Q1A_OUT_FILE, "w");
if(outFp == NULL) {
printf("can't open file %s to write\n", Q1A_OUT_FILE);
}
fprintf(outFp, "%d\n", h_out);
fclose(outFp);
FILE *outFpB = fopen(Q1B_OUT_FILE, "w");
if (outFpB == NULL) {
printf("can't open file %s to write\n", Q1B_OUT_FILE);
}
bool first = true;
for (int i = 0; i < a->size; i++) {
if (first) {
fprintf(outFpB, "%d", h_out_b[i]);
first = false;
} else {
fprintf(outFpB, ",%d", h_out_b[i]);
}
}
fclose(outFpB);
int_vector_free(a);
// free GPU memory allocation
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
hipFree(d_out_b);
return 0;
}
void int_vector_init(vector *vector) {
if(vector == NULL)
{
return;
}
vector -> elements = (int*)malloc(sizeof( int));
vector -> capacity = 1;
vector -> size = 0;
}
int int_vector_add(vector* vector, int element) {
if(vector->size + 1 == vector->capacity)
{
int *temp = (int*)realloc(vector->elements, vector->capacity*2 * sizeof (int));
if(temp == NULL)
{
return 0;
}
vector -> capacity *= 2;
vector -> elements = temp;
}
vector -> elements[vector->size] = element;
vector -> size += 1;
return 1;
}
void int_vector_free(vector *vector){
free(vector->elements);
free(vector);
}
//assumes vector size >= 1
int findMin(vector* vector) {
int min = INT_MAX;
if(vector == NULL)
{
return min;
}
int size = vector->size;
int* arr = vector->elements;
for(int i = 0; i < size; i++)
{
if(arr[i] < min)
{
min = arr[i];
}
}
return min;
}
//returns offset - difference between size and index of last number and offset
int chopString(char *buf, size_t size){
int offset = 0;
int indexOfLastNum = size-2;
if(isdigit(buf[size-2]))
{
int index = size-2;
while(isdigit(buf[index]) && index > 0)
{
index--;
}
buf[index] = '\0';
indexOfLastNum = index+1;
offset = size - indexOfLastNum -1;//-1 to not copy '\0'
} else
{
offset = 0;
}
return offset;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <ctype.h>
#include <limits.h>
#define INPUT_FILE "inp.txt"
#define Q1A_OUT_FILE "q1a.txt"
#define Q1B_OUT_FILE "q1b.txt"
typedef struct vector {
int *elements;
int capacity;
int size;
} vector;
// Method definitions
void int_vector_init(vector *vector);
int int_vector_add(vector* vector, int element);
void int_vector_free(vector *vector);
int chopString(char *buf, size_t size);
int findMin(vector* vector);
// PART A
__global__ void global_reduce_kernel(int * d_out, int * d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s && myId + s < size) {
// d_in[myId] += d_in[myId + s];
if(d_in[myId+s] < d_in[myId]) {
d_in[myId] = d_in[myId+s];
}
}
__syncthreads(); // make sure all moves at one stage are done!
}
// only thread 0 writes result for this block back to global mem
if (tid == 0) {
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int * d_out, int * d_intermediate, int * d_in,
int size, bool usesSharedMemory) {
// assumes that size is not greater than maxThreadsPerBlock^2
// and that size is a multiple of maxThreadsPerBlock
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
global_reduce_kernel<<<blocks, threads>>>
(d_intermediate, d_in, size);
int powerOfTwo = 1;
while (powerOfTwo < blocks) {
powerOfTwo *= 2;
}
// now we're down to one block left, so reduce it
int newSize = blocks;
threads = powerOfTwo; // launch one thread for each block in prev step
blocks = 1;
global_reduce_kernel<<<blocks, threads>>>
(d_out, d_intermediate, newSize);
}
// PART B
__global__ void partb(int* d_out, int* d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if (myId < size) {
int f = d_in[myId];
d_out[myId] = f % 10;
}
}
int main(int argc, char ** argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
FILE *fp;
if((fp = fopen(INPUT_FILE, "r")) == 0) {
printf("%s cannot be found\n", INPUT_FILE);
exit(-1);
}
char separators[] = " ,";
char buf[100];
char* token;
int offset = 0;
vector *a = (vector*) malloc(sizeof (vector));
int_vector_init(a);
while(fgets(buf + offset, sizeof buf - offset, fp) != NULL) {
//chop off number from string if it ends with digit
offset = chopString(buf, sizeof buf);
int indexOfLastNum = sizeof buf - offset - 1;// -1 to not copy '\0'
//printf("buffer: %s\n", buf);
token = strtok(buf, separators);
while (token != NULL) {
int num = atoi(token);
//printf("%d\n", num);
int_vector_add(a, num);
token = strtok(NULL, separators);
}
memcpy(buf, &buf[indexOfLastNum], offset);
}
int min = findMin(a);
const int ARRAY_BYTES = sizeof(int) * a->size;
// declare GPU memory pointers
int * d_in, * d_in_b, * d_intermediate, * d_out, * d_out_b;
// allocate GPU memory
hipMalloc((void **) &d_in_b, ARRAY_BYTES);
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_intermediate, ARRAY_BYTES); // overallocated
hipMalloc((void **) &d_out_b, ARRAY_BYTES);
hipMalloc((void **) &d_out, sizeof(int));
// transfer the input array to the GPU
hipMemcpy(d_in, a->elements, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_in_b, a->elements, ARRAY_BYTES, hipMemcpyHostToDevice);
int whichKernel = 0;
if (argc == 2) {
whichKernel = atoi(argv[1]);
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// launch the kernel
switch(whichKernel) {
case 0:
//printf("Running global reduce\n");
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, false);
hipEventRecord(stop, 0);
break;
case 1:
//printf("Running reduce with shared mem\n");
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, true);
hipEventRecord(stop, 0);
break;
default:
fprintf(stderr, "error: ran no kernel\n");
exit(EXIT_FAILURE);
}
// PART B
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (a->size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
partb<<<blocks, threads>>>(d_out_b, d_in_b, a->size);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
// copy back the sum from GPU
int h_out;
hipMemcpy(&h_out, d_out, sizeof(int), hipMemcpyDeviceToHost);
int h_out_b[a->size];
hipMemcpy(h_out_b, d_out_b, ARRAY_BYTES, hipMemcpyDeviceToHost);
//printf("average time elapsed: %f\n", elapsedTime);
FILE *outFp = fopen(Q1A_OUT_FILE, "w");
if(outFp == NULL) {
printf("can't open file %s to write\n", Q1A_OUT_FILE);
}
fprintf(outFp, "%d\n", h_out);
fclose(outFp);
FILE *outFpB = fopen(Q1B_OUT_FILE, "w");
if (outFpB == NULL) {
printf("can't open file %s to write\n", Q1B_OUT_FILE);
}
bool first = true;
for (int i = 0; i < a->size; i++) {
if (first) {
fprintf(outFpB, "%d", h_out_b[i]);
first = false;
} else {
fprintf(outFpB, ",%d", h_out_b[i]);
}
}
fclose(outFpB);
int_vector_free(a);
// free GPU memory allocation
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
hipFree(d_out_b);
return 0;
}
void int_vector_init(vector *vector) {
if(vector == NULL)
{
return;
}
vector -> elements = (int*)malloc(sizeof( int));
vector -> capacity = 1;
vector -> size = 0;
}
int int_vector_add(vector* vector, int element) {
if(vector->size + 1 == vector->capacity)
{
int *temp = (int*)realloc(vector->elements, vector->capacity*2 * sizeof (int));
if(temp == NULL)
{
return 0;
}
vector -> capacity *= 2;
vector -> elements = temp;
}
vector -> elements[vector->size] = element;
vector -> size += 1;
return 1;
}
void int_vector_free(vector *vector){
free(vector->elements);
free(vector);
}
//assumes vector size >= 1
int findMin(vector* vector) {
int min = INT_MAX;
if(vector == NULL)
{
return min;
}
int size = vector->size;
int* arr = vector->elements;
for(int i = 0; i < size; i++)
{
if(arr[i] < min)
{
min = arr[i];
}
}
return min;
}
//returns offset - difference between size and index of last number and offset
int chopString(char *buf, size_t size){
int offset = 0;
int indexOfLastNum = size-2;
if(isdigit(buf[size-2]))
{
int index = size-2;
while(isdigit(buf[index]) && index > 0)
{
index--;
}
buf[index] = '\0';
indexOfLastNum = index+1;
offset = size - indexOfLastNum -1;//-1 to not copy '\0'
} else
{
offset = 0;
}
return offset;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_reduce_kernelPiS_i
.globl _Z20global_reduce_kernelPiS_i
.p2align 8
.type _Z20global_reduce_kernelPiS_i,@function
_Z20global_reduce_kernelPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_7
s_load_b32 s6, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v6, 0
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_lt_u32 s7, 4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_mov_b32 s7, s3
s_lshr_b32 s3, s3, 1
s_mov_b32 s8, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v5, s3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[7:8], off
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_reduce_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20global_reduce_kernelPiS_i, .Lfunc_end0-_Z20global_reduce_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5partbPiS_i
.globl _Z5partbPiS_i
.p2align 8
.type _Z5partbPiS_i,@function
_Z5partbPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v3, v2, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 2, v3
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 10
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5partbPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5partbPiS_i, .Lfunc_end1-_Z5partbPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_reduce_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20global_reduce_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5partbPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5partbPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <ctype.h>
#include <limits.h>
#define INPUT_FILE "inp.txt"
#define Q1A_OUT_FILE "q1a.txt"
#define Q1B_OUT_FILE "q1b.txt"
typedef struct vector {
int *elements;
int capacity;
int size;
} vector;
// Method definitions
void int_vector_init(vector *vector);
int int_vector_add(vector* vector, int element);
void int_vector_free(vector *vector);
int chopString(char *buf, size_t size);
int findMin(vector* vector);
// PART A
__global__ void global_reduce_kernel(int * d_out, int * d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s && myId + s < size) {
// d_in[myId] += d_in[myId + s];
if(d_in[myId+s] < d_in[myId]) {
d_in[myId] = d_in[myId+s];
}
}
__syncthreads(); // make sure all moves at one stage are done!
}
// only thread 0 writes result for this block back to global mem
if (tid == 0) {
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int * d_out, int * d_intermediate, int * d_in,
int size, bool usesSharedMemory) {
// assumes that size is not greater than maxThreadsPerBlock^2
// and that size is a multiple of maxThreadsPerBlock
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
global_reduce_kernel<<<blocks, threads>>>
(d_intermediate, d_in, size);
int powerOfTwo = 1;
while (powerOfTwo < blocks) {
powerOfTwo *= 2;
}
// now we're down to one block left, so reduce it
int newSize = blocks;
threads = powerOfTwo; // launch one thread for each block in prev step
blocks = 1;
global_reduce_kernel<<<blocks, threads>>>
(d_out, d_intermediate, newSize);
}
// PART B
__global__ void partb(int* d_out, int* d_in, int size) {
int myId = threadIdx.x + blockDim.x * blockIdx.x;
if (myId < size) {
int f = d_in[myId];
d_out[myId] = f % 10;
}
}
int main(int argc, char ** argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
FILE *fp;
if((fp = fopen(INPUT_FILE, "r")) == 0) {
printf("%s cannot be found\n", INPUT_FILE);
exit(-1);
}
char separators[] = " ,";
char buf[100];
char* token;
int offset = 0;
vector *a = (vector*) malloc(sizeof (vector));
int_vector_init(a);
while(fgets(buf + offset, sizeof buf - offset, fp) != NULL) {
//chop off number from string if it ends with digit
offset = chopString(buf, sizeof buf);
int indexOfLastNum = sizeof buf - offset - 1;// -1 to not copy '\0'
//printf("buffer: %s\n", buf);
token = strtok(buf, separators);
while (token != NULL) {
int num = atoi(token);
//printf("%d\n", num);
int_vector_add(a, num);
token = strtok(NULL, separators);
}
memcpy(buf, &buf[indexOfLastNum], offset);
}
int min = findMin(a);
const int ARRAY_BYTES = sizeof(int) * a->size;
// declare GPU memory pointers
int * d_in, * d_in_b, * d_intermediate, * d_out, * d_out_b;
// allocate GPU memory
hipMalloc((void **) &d_in_b, ARRAY_BYTES);
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_intermediate, ARRAY_BYTES); // overallocated
hipMalloc((void **) &d_out_b, ARRAY_BYTES);
hipMalloc((void **) &d_out, sizeof(int));
// transfer the input array to the GPU
hipMemcpy(d_in, a->elements, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_in_b, a->elements, ARRAY_BYTES, hipMemcpyHostToDevice);
int whichKernel = 0;
if (argc == 2) {
whichKernel = atoi(argv[1]);
}
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// launch the kernel
switch(whichKernel) {
case 0:
//printf("Running global reduce\n");
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, false);
hipEventRecord(stop, 0);
break;
case 1:
//printf("Running reduce with shared mem\n");
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_in, a->size, true);
hipEventRecord(stop, 0);
break;
default:
fprintf(stderr, "error: ran no kernel\n");
exit(EXIT_FAILURE);
}
// PART B
const int maxThreadsPerBlock = 1024; //increased from 512 to 1024 to handle 1024^2 values
int threads = maxThreadsPerBlock;
int blocks = (a->size + (maxThreadsPerBlock-1)) / maxThreadsPerBlock;
partb<<<blocks, threads>>>(d_out_b, d_in_b, a->size);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
// copy back the sum from GPU
int h_out;
hipMemcpy(&h_out, d_out, sizeof(int), hipMemcpyDeviceToHost);
int h_out_b[a->size];
hipMemcpy(h_out_b, d_out_b, ARRAY_BYTES, hipMemcpyDeviceToHost);
//printf("average time elapsed: %f\n", elapsedTime);
FILE *outFp = fopen(Q1A_OUT_FILE, "w");
if(outFp == NULL) {
printf("can't open file %s to write\n", Q1A_OUT_FILE);
}
fprintf(outFp, "%d\n", h_out);
fclose(outFp);
FILE *outFpB = fopen(Q1B_OUT_FILE, "w");
if (outFpB == NULL) {
printf("can't open file %s to write\n", Q1B_OUT_FILE);
}
bool first = true;
for (int i = 0; i < a->size; i++) {
if (first) {
fprintf(outFpB, "%d", h_out_b[i]);
first = false;
} else {
fprintf(outFpB, ",%d", h_out_b[i]);
}
}
fclose(outFpB);
int_vector_free(a);
// free GPU memory allocation
hipFree(d_in);
hipFree(d_intermediate);
hipFree(d_out);
hipFree(d_out_b);
return 0;
}
void int_vector_init(vector *vector) {
if(vector == NULL)
{
return;
}
vector -> elements = (int*)malloc(sizeof( int));
vector -> capacity = 1;
vector -> size = 0;
}
int int_vector_add(vector* vector, int element) {
if(vector->size + 1 == vector->capacity)
{
int *temp = (int*)realloc(vector->elements, vector->capacity*2 * sizeof (int));
if(temp == NULL)
{
return 0;
}
vector -> capacity *= 2;
vector -> elements = temp;
}
vector -> elements[vector->size] = element;
vector -> size += 1;
return 1;
}
void int_vector_free(vector *vector){
free(vector->elements);
free(vector);
}
//assumes vector size >= 1
int findMin(vector* vector) {
int min = INT_MAX;
if(vector == NULL)
{
return min;
}
int size = vector->size;
int* arr = vector->elements;
for(int i = 0; i < size; i++)
{
if(arr[i] < min)
{
min = arr[i];
}
}
return min;
}
//returns offset - difference between size and index of last number and offset
int chopString(char *buf, size_t size){
int offset = 0;
int indexOfLastNum = size-2;
if(isdigit(buf[size-2]))
{
int index = size-2;
while(isdigit(buf[index]) && index > 0)
{
index--;
}
buf[index] = '\0';
indexOfLastNum = index+1;
offset = size - indexOfLastNum -1;//-1 to not copy '\0'
} else
{
offset = 0;
}
return offset;
} | .text
.file "q1.hip"
.globl _Z35__device_stub__global_reduce_kernelPiS_i # -- Begin function _Z35__device_stub__global_reduce_kernelPiS_i
.p2align 4, 0x90
.type _Z35__device_stub__global_reduce_kernelPiS_i,@function
_Z35__device_stub__global_reduce_kernelPiS_i: # @_Z35__device_stub__global_reduce_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__global_reduce_kernelPiS_i, .Lfunc_end0-_Z35__device_stub__global_reduce_kernelPiS_i
.cfi_endproc
# -- End function
.globl _Z6reducePiS_S_ib # -- Begin function _Z6reducePiS_S_ib
.p2align 4, 0x90
.type _Z6reducePiS_S_ib,@function
_Z6reducePiS_S_ib: # @_Z6reducePiS_S_ib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, 112(%rsp) # 8-byte Spill
leal 1023(%r12), %eax
leal 2046(%r12), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
movabsq $4294967296, %r15 # imm = 0x100000000
sarl $10, %ebp
leaq (%r15,%rbp), %rdi
leaq 1024(%r15), %rdx
movl $1, %r14d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 72(%rsp)
movq %r13, 64(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
leal (%rax,%rax), %r14d
cmpl %ebp, %eax
jl .LBB1_2
# %bb.3:
movl %eax, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 112(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq %rbx, 64(%rsp)
movl %ebp, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6reducePiS_S_ib, .Lfunc_end1-_Z6reducePiS_S_ib
.cfi_endproc
# -- End function
.globl _Z20__device_stub__partbPiS_i # -- Begin function _Z20__device_stub__partbPiS_i
.p2align 4, 0x90
.type _Z20__device_stub__partbPiS_i,@function
_Z20__device_stub__partbPiS_i: # @_Z20__device_stub__partbPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5partbPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z20__device_stub__partbPiS_i, .Lfunc_end2-_Z20__device_stub__partbPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $312, %rsp # imm = 0x138
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsi, %rbx
movl %edi, %r14d
leaq -124(%rbp), %rdi
callq hipGetDeviceCount
cmpl $0, -124(%rbp)
je .LBB3_1
# %bb.3:
xorl %edi, %edi
callq hipSetDevice
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, -56(%rbp) # 8-byte Spill
testq %rax, %rax
je .LBB3_38
# %bb.4:
movq %rbx, -160(%rbp) # 8-byte Spill
movw $11296, -43(%rbp) # imm = 0x2C20
movb $0, -41(%rbp)
movl $16, %edi
callq malloc
movq %rax, %rbx
testq %rax, %rax
je .LBB3_6
# %bb.5:
movl $4, %edi
callq malloc
movq %rax, (%rbx)
movq $1, 8(%rbx)
.LBB3_6: # %_Z15int_vector_initP6vector.exit
movl %r14d, -88(%rbp) # 4-byte Spill
movq %rbx, -64(%rbp) # 8-byte Spill
leaq -352(%rbp), %rdi
movl $100, %esi
movq -56(%rbp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB3_21
# %bb.7: # %.lr.ph68
leaq -352(%rbp), %rbx
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_20: # %._crit_edge
# in Loop: Header=BB3_8 Depth=1
movslq %r14d, %r13
movl $99, %eax
subl %r13d, %eax
cltq
leaq (%rax,%rbp), %rsi
addq $-352, %rsi # imm = 0xFEA0
leaq -352(%rbp), %rbx
movq %rbx, %rdi
movq %r13, %rdx
callq memcpy@PLT
leaq -352(,%r13), %rdi
addq %rbp, %rdi
movl $100, %esi
subl %r13d, %esi
movq -56(%rbp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB3_21
.LBB3_8: # =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
# Child Loop BB3_14 Depth 2
movsbl -254(%rbp), %eax
addl $-48, %eax
movl $0, %r14d
cmpl $9, %eax
ja .LBB3_13
# %bb.9: # %.preheader.preheader
# in Loop: Header=BB3_8 Depth=1
movl $98, %ecx
movl $-1, %r14d
movl $98, %eax
.p2align 4, 0x90
.LBB3_10: # %.preheader
# Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
incl %r14d
addq $-1, %rax
jae .LBB3_12
# %bb.11: # %.preheader
# in Loop: Header=BB3_10 Depth=2
movsbl -352(%rbp,%rcx), %edx
addl $-48, %edx
movq %rax, %rcx
cmpl $10, %edx
jb .LBB3_10
.LBB3_12: # in Loop: Header=BB3_8 Depth=1
movb $0, -351(%rbp,%rax)
.LBB3_13: # %_Z10chopStringPcm.exit
# in Loop: Header=BB3_8 Depth=1
movq %rbx, %rdi
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_18: # in Loop: Header=BB3_14 Depth=2
movq (%rcx), %rax
movl %r13d, (%rax,%r15,4)
movl %r12d, 12(%rcx)
.LBB3_19: # %_Z14int_vector_addP6vectori.exit
# in Loop: Header=BB3_14 Depth=2
xorl %edi, %edi
.LBB3_14: # %_Z10chopStringPcm.exit
# Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
leaq -43(%rbp), %rsi
callq strtok
testq %rax, %rax
je .LBB3_20
# %bb.15: # %.lr.ph
# in Loop: Header=BB3_14 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq -64(%rbp), %rcx # 8-byte Reload
movslq 12(%rcx), %r15
leal 1(%r15), %r12d
movslq 8(%rcx), %rbx
cmpl %ebx, %r12d
jne .LBB3_18
# %bb.16: # in Loop: Header=BB3_14 Depth=2
movq (%rcx), %rdi
leaq (,%rbx,8), %rsi
callq realloc
testq %rax, %rax
je .LBB3_19
# %bb.17: # in Loop: Header=BB3_14 Depth=2
addl %ebx, %ebx
movq -64(%rbp), %rcx # 8-byte Reload
movl %ebx, 8(%rcx)
movq %rax, (%rcx)
jmp .LBB3_18
.LBB3_21: # %._crit_edge69
movq -64(%rbp), %rbx # 8-byte Reload
movl 12(%rbx), %eax
movq %rax, %r14
leal (,%rax,4), %eax
movslq %eax, %r12
leaq -152(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -80(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -120(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -112(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -72(%rbp), %rdi
movl $4, %esi
callq hipMalloc
movq -80(%rbp), %rdi
movq (%rbx), %r15
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq -152(%rbp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %r13d, %r13d
cmpl $2, -88(%rbp) # 4-byte Folded Reload
jne .LBB3_23
# %bb.22:
movq -160(%rbp), %rax # 8-byte Reload
movq 8(%rax), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB3_23:
leaq -104(%rbp), %rdi
callq hipEventCreate
leaq -96(%rbp), %rdi
callq hipEventCreate
cmpl $1, %r13d
je .LBB3_36
# %bb.24:
testl %r13d, %r13d
jne .LBB3_37
# %bb.25:
movq %r14, %rbx
movq -104(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -72(%rbp), %rdi
movq -120(%rbp), %rsi
movq -80(%rbp), %rdx
jmp .LBB3_26
.LBB3_36:
movq -104(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -72(%rbp), %rdi
movq -120(%rbp), %rsi
movq -80(%rbp), %rdx
movq %r14, %rbx
.LBB3_26:
movl %ebx, %ecx
xorl %r8d, %r8d
callq _Z6reducePiS_S_ib
movq -96(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_28
# %bb.27:
movq -112(%rbp), %rax
movq -152(%rbp), %rcx
movq %rax, -208(%rbp)
movq %rcx, -200(%rbp)
movl %ebx, -128(%rbp)
leaq -208(%rbp), %rax
movq %rax, -240(%rbp)
leaq -200(%rbp), %rax
movq %rax, -232(%rbp)
leaq -128(%rbp), %rax
movq %rax, -224(%rbp)
leaq -144(%rbp), %rdi
leaq -192(%rbp), %rsi
leaq -176(%rbp), %rdx
leaq -168(%rbp), %rcx
callq __hipPopCallConfiguration
movq -144(%rbp), %rsi
movl -136(%rbp), %edx
movq -192(%rbp), %rcx
movl -184(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z5partbPiS_i, %edi
pushq -168(%rbp)
pushq -176(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB3_28:
movq %r15, -56(%rbp) # 8-byte Spill
movq -96(%rbp), %rdi
callq hipEventSynchronize
movq -104(%rbp), %rsi
movq -96(%rbp), %rdx
leaq -240(%rbp), %rdi
callq hipEventElapsedTime
movq -72(%rbp), %rsi
leaq -144(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq %rsp, -88(%rbp) # 8-byte Spill
movq %rsp, %r14
leaq 15(,%rbx,4), %rax
andq $-16, %rax
subq %rax, %r14
movq %r14, %rsp
movq -112(%rbp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r12
testq %rax, %rax
jne .LBB3_30
# %bb.29:
movl $.L.str.7, %edi
movl $.L.str.5, %esi
xorl %eax, %eax
callq printf
.LBB3_30:
movl -144(%rbp), %edx
movl $.L.str.8, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
movq %r12, %rdi
callq fclose
movl $.L.str.9, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r12
testq %rax, %rax
jne .LBB3_32
# %bb.31:
movl $.L.str.7, %edi
movl $.L.str.9, %esi
xorl %eax, %eax
callq printf
.LBB3_32:
testl %ebx, %ebx
jle .LBB3_35
# %bb.33: # %.lr.ph73.preheader
movb $1, %r15b
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_34: # %.lr.ph73
# =>This Inner Loop Header: Depth=1
testb $1, %r15b
movl $.L.str.10, %esi
movl $.L.str.11, %eax
cmoveq %rax, %rsi
movl (%r14,%r13,4), %edx
movzbl %r15b, %r15d
movl $0, %eax
cmovnel %eax, %r15d
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
incq %r13
cmpq %r13, %rbx
jne .LBB3_34
.LBB3_35: # %._crit_edge74
movq %r12, %rdi
callq fclose
movq -56(%rbp), %rdi # 8-byte Reload
callq free
movq -64(%rbp), %rdi # 8-byte Reload
callq free
movq -80(%rbp), %rdi
callq hipFree
movq -120(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
movq -112(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB3_1:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
jmp .LBB3_2
.LBB3_38:
movl $.L.str.3, %edi
movl $.L.str.1, %esi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB3_37:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $21, %esi
.LBB3_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z15int_vector_initP6vector # -- Begin function _Z15int_vector_initP6vector
.p2align 4, 0x90
.type _Z15int_vector_initP6vector,@function
_Z15int_vector_initP6vector: # @_Z15int_vector_initP6vector
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $4, %edi
callq malloc
movq %rax, (%rbx)
movq $1, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB4_2:
retq
.Lfunc_end4:
.size _Z15int_vector_initP6vector, .Lfunc_end4-_Z15int_vector_initP6vector
.cfi_endproc
# -- End function
.globl _Z10chopStringPcm # -- Begin function _Z10chopStringPcm
.p2align 4, 0x90
.type _Z10chopStringPcm,@function
_Z10chopStringPcm: # @_Z10chopStringPcm
.cfi_startproc
# %bb.0:
movsbl -2(%rdi,%rsi), %ecx
addl $-48, %ecx
xorl %eax, %eax
cmpl $9, %ecx
ja .LBB5_5
# %bb.1:
addq $-2, %rsi
movslq %esi, %rcx
movl $-1, %eax
.p2align 4, 0x90
.LBB5_2: # =>This Inner Loop Header: Depth=1
leaq -1(%rcx), %rdx
incl %eax
testq %rcx, %rcx
jle .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movsbl (%rdi,%rcx), %esi
addl $-48, %esi
movq %rdx, %rcx
cmpl $10, %esi
jb .LBB5_2
.LBB5_4:
movb $0, 1(%rdi,%rdx)
.LBB5_5:
retq
.Lfunc_end5:
.size _Z10chopStringPcm, .Lfunc_end5-_Z10chopStringPcm
.cfi_endproc
# -- End function
.globl _Z14int_vector_addP6vectori # -- Begin function _Z14int_vector_addP6vectori
.p2align 4, 0x90
.type _Z14int_vector_addP6vectori,@function
_Z14int_vector_addP6vectori: # @_Z14int_vector_addP6vectori
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl 12(%rdi), %eax
incl %eax
movslq 8(%rdi), %rsi
cmpl %esi, %eax
jne .LBB6_4
# %bb.1:
movq (%rbx), %rdi
shlq $3, %rsi
callq realloc
testq %rax, %rax
je .LBB6_2
# %bb.3:
shll 8(%rbx)
movq %rax, (%rbx)
.LBB6_4:
movq (%rbx), %rax
movslq 12(%rbx), %rcx
movl %ebp, (%rax,%rcx,4)
incl 12(%rbx)
movl $1, %eax
.LBB6_5: # %.critedge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_2:
.cfi_def_cfa_offset 32
xorl %eax, %eax
jmp .LBB6_5
.Lfunc_end6:
.size _Z14int_vector_addP6vectori, .Lfunc_end6-_Z14int_vector_addP6vectori
.cfi_endproc
# -- End function
.globl _Z7findMinP6vector # -- Begin function _Z7findMinP6vector
.p2align 4, 0x90
.type _Z7findMinP6vector,@function
_Z7findMinP6vector: # @_Z7findMinP6vector
.cfi_startproc
# %bb.0:
movl $2147483647, %eax # imm = 0x7FFFFFFF
testq %rdi, %rdi
je .LBB7_4
# %bb.1:
movl 12(%rdi), %ecx
testl %ecx, %ecx
jle .LBB7_4
# %bb.2: # %.lr.ph.preheader
movq (%rdi), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB7_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdx,%rsi,4), %edi
cmpl %eax, %edi
cmovll %edi, %eax
incq %rsi
cmpq %rsi, %rcx
jne .LBB7_3
.LBB7_4: # %.loopexit
retq
.Lfunc_end7:
.size _Z7findMinP6vector, .Lfunc_end7-_Z7findMinP6vector
.cfi_endproc
# -- End function
.globl _Z15int_vector_freeP6vector # -- Begin function _Z15int_vector_freeP6vector
.p2align 4, 0x90
.type _Z15int_vector_freeP6vector,@function
_Z15int_vector_freeP6vector: # @_Z15int_vector_freeP6vector
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
callq free
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end8:
.size _Z15int_vector_freeP6vector, .Lfunc_end8-_Z15int_vector_freeP6vector
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20global_reduce_kernelPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5partbPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20global_reduce_kernelPiS_i,@object # @_Z20global_reduce_kernelPiS_i
.section .rodata,"a",@progbits
.globl _Z20global_reduce_kernelPiS_i
.p2align 3, 0x0
_Z20global_reduce_kernelPiS_i:
.quad _Z35__device_stub__global_reduce_kernelPiS_i
.size _Z20global_reduce_kernelPiS_i, 8
.type _Z5partbPiS_i,@object # @_Z5partbPiS_i
.globl _Z5partbPiS_i
.p2align 3, 0x0
_Z5partbPiS_i:
.quad _Z20__device_stub__partbPiS_i
.size _Z5partbPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error: no devices supporting CUDA.\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "inp.txt"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%s cannot be found\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error: ran no kernel\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "q1a.txt"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "w"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "can't open file %s to write\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d\n"
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "q1b.txt"
.size .L.str.9, 8
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d"
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz ",%d"
.size .L.str.11, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20global_reduce_kernelPiS_i"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5partbPiS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__global_reduce_kernelPiS_i
.addrsig_sym _Z20__device_stub__partbPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20global_reduce_kernelPiS_i
.addrsig_sym _Z5partbPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5partbPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R9, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0209 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD.HI R0, R2, 0x66666667, RZ ; /* 0x6666666702007827 */
/* 0x004fca00078e02ff */
/*00b0*/ SHF.R.U32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fc80000011600 */
/*00c0*/ LEA.HI.SX32 R7, R0, R5, 0x1e ; /* 0x0000000500077211 */
/* 0x000fe200078ff2ff */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD R7, R7, -0xa, R2 ; /* 0xfffffff607077824 */
/* 0x000fca00078e0202 */
/*00f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20global_reduce_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fc800078e0208 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x1b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x000fe2000fffe0ff */
/*00c0*/ BSSY B0, 0x170 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f06070 */
/*00e0*/ ISETP.GE.U32.OR P0, PT, R8, UR4, P0 ; /* 0x0000000408007c0c */
/* 0x000fda0008706470 */
/*00f0*/ @P0 BRA 0x160 ; /* 0x0000006000000947 */
/* 0x001fea0003800000 */
/*0100*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0110*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000eb2000c1e1900 */
/*0120*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0005 */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GE.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e4000c101906 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fea0000010000 */
/*0190*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01a0*/ @P0 BRA 0xb0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*01b0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD.WIDE.U32 R4, R7, R4, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fca00078e0004 */
/*0200*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_reduce_kernelPiS_i
.globl _Z20global_reduce_kernelPiS_i
.p2align 8
.type _Z20global_reduce_kernelPiS_i,@function
_Z20global_reduce_kernelPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_7
s_load_b32 s6, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v6, 0
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_lt_u32 s7, 4
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_3:
s_mov_b32 s7, s3
s_lshr_b32 s3, s3, 1
s_mov_b32 s8, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v5, s3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s6, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_clause 0x1
global_load_b32 v5, v[7:8], off
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v5, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_reduce_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20global_reduce_kernelPiS_i, .Lfunc_end0-_Z20global_reduce_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5partbPiS_i
.globl _Z5partbPiS_i
.p2align 8
.type _Z5partbPiS_i,@function
_Z5partbPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v3, v2, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 31, v3
v_ashrrev_i32_e32 v3, 2, v3
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, 10
v_sub_nc_u32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5partbPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5partbPiS_i, .Lfunc_end1-_Z5partbPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_reduce_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20global_reduce_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5partbPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5partbPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ef479_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15int_vector_initP6vector
.type _Z15int_vector_initP6vector, @function
_Z15int_vector_initP6vector:
.LFB2059:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L6
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, (%rbx)
movl $1, 8(%rbx)
movl $0, 12(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore 3
ret
.cfi_endproc
.LFE2059:
.size _Z15int_vector_initP6vector, .-_Z15int_vector_initP6vector
.globl _Z14int_vector_addP6vectori
.type _Z14int_vector_addP6vectori, @function
_Z14int_vector_addP6vectori:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %ebp
movl 8(%rdi), %edx
movl 12(%rdi), %eax
addl $1, %eax
cmpl %edx, %eax
je .L14
.L10:
movslq 12(%rbx), %rdx
movq (%rbx), %rax
movl %ebp, (%rax,%rdx,4)
addl $1, 12(%rbx)
movl $1, %eax
.L9:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leal (%rdx,%rdx), %esi
movslq %esi, %rsi
salq $2, %rsi
movq (%rdi), %rdi
call realloc@PLT
testq %rax, %rax
je .L12
sall 8(%rbx)
movq %rax, (%rbx)
jmp .L10
.L12:
movl $0, %eax
jmp .L9
.cfi_endproc
.LFE2060:
.size _Z14int_vector_addP6vectori, .-_Z14int_vector_addP6vectori
.globl _Z15int_vector_freeP6vector
.type _Z15int_vector_freeP6vector, @function
_Z15int_vector_freeP6vector:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z15int_vector_freeP6vector, .-_Z15int_vector_freeP6vector
.globl _Z7findMinP6vector
.type _Z7findMinP6vector, @function
_Z7findMinP6vector:
.LFB2062:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L20
movl 12(%rdi), %edx
movq (%rdi), %rcx
testl %edx, %edx
jle .L21
movq %rcx, %rax
movslq %edx, %rdx
leaq (%rcx,%rdx,4), %rsi
movl $2147483647, %edx
.L19:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovg %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L19
.L17:
movl %edx, %eax
ret
.L20:
movl $2147483647, %edx
jmp .L17
.L21:
movl $2147483647, %edx
jmp .L17
.cfi_endproc
.LFE2062:
.size _Z7findMinP6vector, .-_Z7findMinP6vector
.globl _Z10chopStringPcm
.type _Z10chopStringPcm, @function
_Z10chopStringPcm:
.LFB2063:
.cfi_startproc
endbr64
movsbl -2(%rdi,%rsi), %eax
subl $48, %eax
movl $0, %edx
cmpl $9, %eax
ja .L23
leal -2(%rsi), %edx
movslq %edx, %rcx
leaq (%rdi,%rcx), %r8
movsbl (%r8), %eax
subl $48, %eax
cmpl $9, %eax
ja .L25
testl %edx, %edx
jle .L25
leaq -1(%rdi,%rcx), %rcx
.L26:
subl $1, %edx
movq %rcx, %r8
subq $1, %rcx
movsbl (%r8), %eax
subl $48, %eax
cmpl $9, %eax
ja .L25
testl %edx, %edx
jg .L26
.L25:
movb $0, (%r8)
subl %edx, %esi
leal -2(%rsi), %edx
.L23:
movl %edx, %eax
ret
.cfi_endproc
.LFE2063:
.size _Z10chopStringPcm, .-_Z10chopStringPcm
.globl _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
.type _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i, @function
_Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20global_reduce_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i, .-_Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
.globl _Z20global_reduce_kernelPiS_i
.type _Z20global_reduce_kernelPiS_i, @function
_Z20global_reduce_kernelPiS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z20global_reduce_kernelPiS_i, .-_Z20global_reduce_kernelPiS_i
.globl _Z6reducePiS_S_ib
.type _Z6reducePiS_S_ib, @function
_Z6reducePiS_S_ib:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %r14
movl %ecx, %ebp
leal 2046(%rcx), %ebx
movl %ecx, %eax
addl $1023, %eax
cmovns %eax, %ebx
sarl $10, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L39:
cmpl $1024, %ebp
jle .L43
movl $1, %eax
.L41:
addl %eax, %eax
cmpl %eax, %ebx
jg .L41
.L40:
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L38:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movl %ebp, %edx
movq %r14, %rsi
movq %r12, %rdi
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
jmp .L39
.L43:
movl $1, %eax
jmp .L40
.L47:
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
jmp .L38
.cfi_endproc
.LFE2057:
.size _Z6reducePiS_S_ib, .-_Z6reducePiS_S_ib
.globl _Z27__device_stub__Z5partbPiS_iPiS_i
.type _Z27__device_stub__Z5partbPiS_iPiS_i, @function
_Z27__device_stub__Z5partbPiS_iPiS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5partbPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z27__device_stub__Z5partbPiS_iPiS_i, .-_Z27__device_stub__Z5partbPiS_iPiS_i
.globl _Z5partbPiS_i
.type _Z5partbPiS_i, @function
_Z5partbPiS_i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5partbPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z5partbPiS_i, .-_Z5partbPiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "error: no devices supporting CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "inp.txt"
.LC3:
.string "%s cannot be found\n"
.LC4:
.string "error: ran no kernel\n"
.LC5:
.string "w"
.LC6:
.string "q1a.txt"
.LC7:
.string "can't open file %s to write\n"
.LC8:
.string "%d\n"
.LC9:
.string "q1b.txt"
.LC10:
.string "%d"
.LC11:
.string ",%d"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -268(%rbp)
movq %rsi, -280(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
leaq -252(%rbp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, -252(%rbp)
je .L84
movl $0, %edi
call cudaSetDevice@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, -264(%rbp)
testq %rax, %rax
je .L85
movw $11296, -163(%rbp)
movb $0, -161(%rbp)
movl $16, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rdi
call _Z15int_vector_initP6vector
movl $0, %r14d
movl $100, %r15d
jmp .L59
.L84:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
leaq .LC2(%rip), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L60:
movslq %r14d, %rdx
leaq -160(%rbp), %rdi
movslq %r13d, %rsi
addq %rdi, %rsi
movl $100, %ecx
call __memcpy_chk@PLT
.L59:
movslq %r14d, %rax
movl %r15d, %edx
subl %r14d, %edx
movl $100, %esi
cmpq %rsi, %rax
cmovnb %rax, %rsi
subq %rax, %rsi
leaq -160(%rbp,%rax), %rdi
movq -264(%rbp), %rcx
call __fgets_chk@PLT
testq %rax, %rax
je .L86
leaq -160(%rbp), %rbx
movl $100, %esi
movq %rbx, %rdi
call _Z10chopStringPcm
movl %eax, %r14d
movl $99, %r13d
subl %eax, %r13d
leaq -163(%rbp), %rsi
movq %rbx, %rdi
call strtok@PLT
movq %rax, %rdi
testq %rax, %rax
je .L60
leaq -163(%rbp), %rbx
.L61:
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %esi
movq %r12, %rdi
call _Z14int_vector_addP6vectori
movq %rbx, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %rdi
testq %rax, %rax
jne .L61
jmp .L60
.L86:
movl 12(%r12), %ebx
movslq %ebx, %r15
leal 0(,%rbx,4), %r13d
movslq %r13d, %r13
leaq -240(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -248(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -232(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -216(%rbp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq -224(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq (%r12), %r14
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq -248(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq -240(%rbp), %rdi
call cudaMemcpy@PLT
cmpl $2, -268(%rbp)
je .L87
leaq -208(%rbp), %rdi
call cudaEventCreate@PLT
leaq -200(%rbp), %rdi
call cudaEventCreate@PLT
.L64:
movl $0, %esi
movq -208(%rbp), %rdi
call cudaEventRecord@PLT
movl $0, %r8d
movl %ebx, %ecx
movq -248(%rbp), %rdx
movq -232(%rbp), %rsi
movq -224(%rbp), %rdi
call _Z6reducePiS_S_ib
movl $0, %esi
movq -200(%rbp), %rdi
call cudaEventRecord@PLT
.L67:
movl $1024, -176(%rbp)
movl $1, -172(%rbp)
movl $1, -168(%rbp)
leal 2046(%rbx), %eax
movl %ebx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, -188(%rbp)
movl $1, -184(%rbp)
movl $1, -180(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -176(%rbp), %rdx
movl $1, %ecx
movq -188(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L88
.L68:
movq -200(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -188(%rbp), %rdi
movq -200(%rbp), %rdx
movq -208(%rbp), %rsi
call cudaEventElapsedTime@PLT
leaq -176(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -224(%rbp), %rsi
call cudaMemcpy@PLT
salq $2, %r15
leaq 15(%r15), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L69:
cmpq %rdx, %rsp
je .L70
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L69
.L87:
movq -280(%rbp), %rax
movq 8(%rax), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
leaq -208(%rbp), %rdi
call cudaEventCreate@PLT
leaq -200(%rbp), %rdi
call cudaEventCreate@PLT
testl %r14d, %r14d
je .L64
cmpl $1, %r14d
jne .L89
movl $0, %esi
movq -208(%rbp), %rdi
call cudaEventRecord@PLT
movl $1, %r8d
movl %ebx, %ecx
movq -248(%rbp), %rdx
movq -232(%rbp), %rsi
movq -224(%rbp), %rdi
call _Z6reducePiS_S_ib
movl $0, %esi
movq -200(%rbp), %rdi
call cudaEventRecord@PLT
jmp .L67
.L89:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %ebx, %edx
movq -240(%rbp), %rsi
movq -216(%rbp), %rdi
call _Z27__device_stub__Z5partbPiS_iPiS_i
jmp .L68
.L70:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L71
orq $0, -8(%rsp,%rax)
.L71:
movq %rsp, %r14
movl $2, %ecx
movq %r13, %rdx
movq -216(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L90
.L72:
movl -176(%rbp), %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %r13, %rdi
call fclose@PLT
leaq .LC5(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %r13
testq %rax, %rax
je .L91
.L73:
testl %ebx, %ebx
jle .L74
movq %r14, %rbx
addq %r15, %r14
movl $1, %eax
leaq .LC11(%rip), %r15
jmp .L77
.L90:
leaq .LC6(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L72
.L91:
leaq .LC9(%rip), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L73
.L75:
movl (%rbx), %ecx
movq %r15, %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L76:
addq $4, %rbx
movl $0, %eax
cmpq %r14, %rbx
je .L74
.L77:
testb %al, %al
je .L75
movl (%rbx), %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L76
.L74:
movq %r13, %rdi
call fclose@PLT
movq %r12, %rdi
call _Z15int_vector_freeP6vector
movq -248(%rbp), %rdi
call cudaFree@PLT
movq -232(%rbp), %rdi
call cudaFree@PLT
movq -224(%rbp), %rdi
call cudaFree@PLT
movq -216(%rbp), %rdi
call cudaFree@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L92
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L92:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z5partbPiS_i"
.LC13:
.string "_Z20global_reduce_kernelPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z5partbPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z20global_reduce_kernelPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q1.hip"
.globl _Z35__device_stub__global_reduce_kernelPiS_i # -- Begin function _Z35__device_stub__global_reduce_kernelPiS_i
.p2align 4, 0x90
.type _Z35__device_stub__global_reduce_kernelPiS_i,@function
_Z35__device_stub__global_reduce_kernelPiS_i: # @_Z35__device_stub__global_reduce_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__global_reduce_kernelPiS_i, .Lfunc_end0-_Z35__device_stub__global_reduce_kernelPiS_i
.cfi_endproc
# -- End function
.globl _Z6reducePiS_S_ib # -- Begin function _Z6reducePiS_S_ib
.p2align 4, 0x90
.type _Z6reducePiS_S_ib,@function
_Z6reducePiS_S_ib: # @_Z6reducePiS_S_ib
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, 112(%rsp) # 8-byte Spill
leal 1023(%r12), %eax
leal 2046(%r12), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
movabsq $4294967296, %r15 # imm = 0x100000000
sarl $10, %ebp
leaq (%r15,%rbp), %rdi
leaq 1024(%r15), %rdx
movl $1, %r14d
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 72(%rsp)
movq %r13, 64(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
leal (%rax,%rax), %r14d
cmpl %ebp, %eax
jl .LBB1_2
# %bb.3:
movl %eax, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 112(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq %rbx, 64(%rsp)
movl %ebp, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6reducePiS_S_ib, .Lfunc_end1-_Z6reducePiS_S_ib
.cfi_endproc
# -- End function
.globl _Z20__device_stub__partbPiS_i # -- Begin function _Z20__device_stub__partbPiS_i
.p2align 4, 0x90
.type _Z20__device_stub__partbPiS_i,@function
_Z20__device_stub__partbPiS_i: # @_Z20__device_stub__partbPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5partbPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z20__device_stub__partbPiS_i, .Lfunc_end2-_Z20__device_stub__partbPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $312, %rsp # imm = 0x138
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movq %rsi, %rbx
movl %edi, %r14d
leaq -124(%rbp), %rdi
callq hipGetDeviceCount
cmpl $0, -124(%rbp)
je .LBB3_1
# %bb.3:
xorl %edi, %edi
callq hipSetDevice
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, -56(%rbp) # 8-byte Spill
testq %rax, %rax
je .LBB3_38
# %bb.4:
movq %rbx, -160(%rbp) # 8-byte Spill
movw $11296, -43(%rbp) # imm = 0x2C20
movb $0, -41(%rbp)
movl $16, %edi
callq malloc
movq %rax, %rbx
testq %rax, %rax
je .LBB3_6
# %bb.5:
movl $4, %edi
callq malloc
movq %rax, (%rbx)
movq $1, 8(%rbx)
.LBB3_6: # %_Z15int_vector_initP6vector.exit
movl %r14d, -88(%rbp) # 4-byte Spill
movq %rbx, -64(%rbp) # 8-byte Spill
leaq -352(%rbp), %rdi
movl $100, %esi
movq -56(%rbp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB3_21
# %bb.7: # %.lr.ph68
leaq -352(%rbp), %rbx
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_20: # %._crit_edge
# in Loop: Header=BB3_8 Depth=1
movslq %r14d, %r13
movl $99, %eax
subl %r13d, %eax
cltq
leaq (%rax,%rbp), %rsi
addq $-352, %rsi # imm = 0xFEA0
leaq -352(%rbp), %rbx
movq %rbx, %rdi
movq %r13, %rdx
callq memcpy@PLT
leaq -352(,%r13), %rdi
addq %rbp, %rdi
movl $100, %esi
subl %r13d, %esi
movq -56(%rbp), %rdx # 8-byte Reload
callq fgets
testq %rax, %rax
je .LBB3_21
.LBB3_8: # =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
# Child Loop BB3_14 Depth 2
movsbl -254(%rbp), %eax
addl $-48, %eax
movl $0, %r14d
cmpl $9, %eax
ja .LBB3_13
# %bb.9: # %.preheader.preheader
# in Loop: Header=BB3_8 Depth=1
movl $98, %ecx
movl $-1, %r14d
movl $98, %eax
.p2align 4, 0x90
.LBB3_10: # %.preheader
# Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
incl %r14d
addq $-1, %rax
jae .LBB3_12
# %bb.11: # %.preheader
# in Loop: Header=BB3_10 Depth=2
movsbl -352(%rbp,%rcx), %edx
addl $-48, %edx
movq %rax, %rcx
cmpl $10, %edx
jb .LBB3_10
.LBB3_12: # in Loop: Header=BB3_8 Depth=1
movb $0, -351(%rbp,%rax)
.LBB3_13: # %_Z10chopStringPcm.exit
# in Loop: Header=BB3_8 Depth=1
movq %rbx, %rdi
jmp .LBB3_14
.p2align 4, 0x90
.LBB3_18: # in Loop: Header=BB3_14 Depth=2
movq (%rcx), %rax
movl %r13d, (%rax,%r15,4)
movl %r12d, 12(%rcx)
.LBB3_19: # %_Z14int_vector_addP6vectori.exit
# in Loop: Header=BB3_14 Depth=2
xorl %edi, %edi
.LBB3_14: # %_Z10chopStringPcm.exit
# Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
leaq -43(%rbp), %rsi
callq strtok
testq %rax, %rax
je .LBB3_20
# %bb.15: # %.lr.ph
# in Loop: Header=BB3_14 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq -64(%rbp), %rcx # 8-byte Reload
movslq 12(%rcx), %r15
leal 1(%r15), %r12d
movslq 8(%rcx), %rbx
cmpl %ebx, %r12d
jne .LBB3_18
# %bb.16: # in Loop: Header=BB3_14 Depth=2
movq (%rcx), %rdi
leaq (,%rbx,8), %rsi
callq realloc
testq %rax, %rax
je .LBB3_19
# %bb.17: # in Loop: Header=BB3_14 Depth=2
addl %ebx, %ebx
movq -64(%rbp), %rcx # 8-byte Reload
movl %ebx, 8(%rcx)
movq %rax, (%rcx)
jmp .LBB3_18
.LBB3_21: # %._crit_edge69
movq -64(%rbp), %rbx # 8-byte Reload
movl 12(%rbx), %eax
movq %rax, %r14
leal (,%rax,4), %eax
movslq %eax, %r12
leaq -152(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -80(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -120(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -112(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq -72(%rbp), %rdi
movl $4, %esi
callq hipMalloc
movq -80(%rbp), %rdi
movq (%rbx), %r15
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq -152(%rbp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
xorl %r13d, %r13d
cmpl $2, -88(%rbp) # 4-byte Folded Reload
jne .LBB3_23
# %bb.22:
movq -160(%rbp), %rax # 8-byte Reload
movq 8(%rax), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
.LBB3_23:
leaq -104(%rbp), %rdi
callq hipEventCreate
leaq -96(%rbp), %rdi
callq hipEventCreate
cmpl $1, %r13d
je .LBB3_36
# %bb.24:
testl %r13d, %r13d
jne .LBB3_37
# %bb.25:
movq %r14, %rbx
movq -104(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -72(%rbp), %rdi
movq -120(%rbp), %rsi
movq -80(%rbp), %rdx
jmp .LBB3_26
.LBB3_36:
movq -104(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -72(%rbp), %rdi
movq -120(%rbp), %rsi
movq -80(%rbp), %rdx
movq %r14, %rbx
.LBB3_26:
movl %ebx, %ecx
xorl %r8d, %r8d
callq _Z6reducePiS_S_ib
movq -96(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_28
# %bb.27:
movq -112(%rbp), %rax
movq -152(%rbp), %rcx
movq %rax, -208(%rbp)
movq %rcx, -200(%rbp)
movl %ebx, -128(%rbp)
leaq -208(%rbp), %rax
movq %rax, -240(%rbp)
leaq -200(%rbp), %rax
movq %rax, -232(%rbp)
leaq -128(%rbp), %rax
movq %rax, -224(%rbp)
leaq -144(%rbp), %rdi
leaq -192(%rbp), %rsi
leaq -176(%rbp), %rdx
leaq -168(%rbp), %rcx
callq __hipPopCallConfiguration
movq -144(%rbp), %rsi
movl -136(%rbp), %edx
movq -192(%rbp), %rcx
movl -184(%rbp), %r8d
leaq -240(%rbp), %r9
movl $_Z5partbPiS_i, %edi
pushq -168(%rbp)
pushq -176(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB3_28:
movq %r15, -56(%rbp) # 8-byte Spill
movq -96(%rbp), %rdi
callq hipEventSynchronize
movq -104(%rbp), %rsi
movq -96(%rbp), %rdx
leaq -240(%rbp), %rdi
callq hipEventElapsedTime
movq -72(%rbp), %rsi
leaq -144(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq %rsp, -88(%rbp) # 8-byte Spill
movq %rsp, %r14
leaq 15(,%rbx,4), %rax
andq $-16, %rax
subq %rax, %r14
movq %r14, %rsp
movq -112(%rbp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r12
testq %rax, %rax
jne .LBB3_30
# %bb.29:
movl $.L.str.7, %edi
movl $.L.str.5, %esi
xorl %eax, %eax
callq printf
.LBB3_30:
movl -144(%rbp), %edx
movl $.L.str.8, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
movq %r12, %rdi
callq fclose
movl $.L.str.9, %edi
movl $.L.str.6, %esi
callq fopen
movq %rax, %r12
testq %rax, %rax
jne .LBB3_32
# %bb.31:
movl $.L.str.7, %edi
movl $.L.str.9, %esi
xorl %eax, %eax
callq printf
.LBB3_32:
testl %ebx, %ebx
jle .LBB3_35
# %bb.33: # %.lr.ph73.preheader
movb $1, %r15b
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_34: # %.lr.ph73
# =>This Inner Loop Header: Depth=1
testb $1, %r15b
movl $.L.str.10, %esi
movl $.L.str.11, %eax
cmoveq %rax, %rsi
movl (%r14,%r13,4), %edx
movzbl %r15b, %r15d
movl $0, %eax
cmovnel %eax, %r15d
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
incq %r13
cmpq %r13, %rbx
jne .LBB3_34
.LBB3_35: # %._crit_edge74
movq %r12, %rdi
callq fclose
movq -56(%rbp), %rdi # 8-byte Reload
callq free
movq -64(%rbp), %rdi # 8-byte Reload
callq free
movq -80(%rbp), %rdi
callq hipFree
movq -120(%rbp), %rdi
callq hipFree
movq -72(%rbp), %rdi
callq hipFree
movq -112(%rbp), %rdi
callq hipFree
movq -88(%rbp), %rsp # 8-byte Reload
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB3_1:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
jmp .LBB3_2
.LBB3_38:
movl $.L.str.3, %edi
movl $.L.str.1, %esi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB3_37:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $21, %esi
.LBB3_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.globl _Z15int_vector_initP6vector # -- Begin function _Z15int_vector_initP6vector
.p2align 4, 0x90
.type _Z15int_vector_initP6vector,@function
_Z15int_vector_initP6vector: # @_Z15int_vector_initP6vector
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $4, %edi
callq malloc
movq %rax, (%rbx)
movq $1, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB4_2:
retq
.Lfunc_end4:
.size _Z15int_vector_initP6vector, .Lfunc_end4-_Z15int_vector_initP6vector
.cfi_endproc
# -- End function
.globl _Z10chopStringPcm # -- Begin function _Z10chopStringPcm
.p2align 4, 0x90
.type _Z10chopStringPcm,@function
_Z10chopStringPcm: # @_Z10chopStringPcm
.cfi_startproc
# %bb.0:
movsbl -2(%rdi,%rsi), %ecx
addl $-48, %ecx
xorl %eax, %eax
cmpl $9, %ecx
ja .LBB5_5
# %bb.1:
addq $-2, %rsi
movslq %esi, %rcx
movl $-1, %eax
.p2align 4, 0x90
.LBB5_2: # =>This Inner Loop Header: Depth=1
leaq -1(%rcx), %rdx
incl %eax
testq %rcx, %rcx
jle .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movsbl (%rdi,%rcx), %esi
addl $-48, %esi
movq %rdx, %rcx
cmpl $10, %esi
jb .LBB5_2
.LBB5_4:
movb $0, 1(%rdi,%rdx)
.LBB5_5:
retq
.Lfunc_end5:
.size _Z10chopStringPcm, .Lfunc_end5-_Z10chopStringPcm
.cfi_endproc
# -- End function
.globl _Z14int_vector_addP6vectori # -- Begin function _Z14int_vector_addP6vectori
.p2align 4, 0x90
.type _Z14int_vector_addP6vectori,@function
_Z14int_vector_addP6vectori: # @_Z14int_vector_addP6vectori
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl 12(%rdi), %eax
incl %eax
movslq 8(%rdi), %rsi
cmpl %esi, %eax
jne .LBB6_4
# %bb.1:
movq (%rbx), %rdi
shlq $3, %rsi
callq realloc
testq %rax, %rax
je .LBB6_2
# %bb.3:
shll 8(%rbx)
movq %rax, (%rbx)
.LBB6_4:
movq (%rbx), %rax
movslq 12(%rbx), %rcx
movl %ebp, (%rax,%rcx,4)
incl 12(%rbx)
movl $1, %eax
.LBB6_5: # %.critedge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_2:
.cfi_def_cfa_offset 32
xorl %eax, %eax
jmp .LBB6_5
.Lfunc_end6:
.size _Z14int_vector_addP6vectori, .Lfunc_end6-_Z14int_vector_addP6vectori
.cfi_endproc
# -- End function
.globl _Z7findMinP6vector # -- Begin function _Z7findMinP6vector
.p2align 4, 0x90
.type _Z7findMinP6vector,@function
_Z7findMinP6vector: # @_Z7findMinP6vector
.cfi_startproc
# %bb.0:
movl $2147483647, %eax # imm = 0x7FFFFFFF
testq %rdi, %rdi
je .LBB7_4
# %bb.1:
movl 12(%rdi), %ecx
testl %ecx, %ecx
jle .LBB7_4
# %bb.2: # %.lr.ph.preheader
movq (%rdi), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB7_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdx,%rsi,4), %edi
cmpl %eax, %edi
cmovll %edi, %eax
incq %rsi
cmpq %rsi, %rcx
jne .LBB7_3
.LBB7_4: # %.loopexit
retq
.Lfunc_end7:
.size _Z7findMinP6vector, .Lfunc_end7-_Z7findMinP6vector
.cfi_endproc
# -- End function
.globl _Z15int_vector_freeP6vector # -- Begin function _Z15int_vector_freeP6vector
.p2align 4, 0x90
.type _Z15int_vector_freeP6vector,@function
_Z15int_vector_freeP6vector: # @_Z15int_vector_freeP6vector
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
callq free
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end8:
.size _Z15int_vector_freeP6vector, .Lfunc_end8-_Z15int_vector_freeP6vector
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20global_reduce_kernelPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5partbPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20global_reduce_kernelPiS_i,@object # @_Z20global_reduce_kernelPiS_i
.section .rodata,"a",@progbits
.globl _Z20global_reduce_kernelPiS_i
.p2align 3, 0x0
_Z20global_reduce_kernelPiS_i:
.quad _Z35__device_stub__global_reduce_kernelPiS_i
.size _Z20global_reduce_kernelPiS_i, 8
.type _Z5partbPiS_i,@object # @_Z5partbPiS_i
.globl _Z5partbPiS_i
.p2align 3, 0x0
_Z5partbPiS_i:
.quad _Z20__device_stub__partbPiS_i
.size _Z5partbPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error: no devices supporting CUDA.\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "inp.txt"
.size .L.str.1, 8
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.L.str.2:
.asciz "r"
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.L.str.3:
.asciz "%s cannot be found\n"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "error: ran no kernel\n"
.size .L.str.4, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "q1a.txt"
.size .L.str.5, 8
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.L.str.6:
.asciz "w"
.size .L.str.6, 2
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.asciz "can't open file %s to write\n"
.size .L.str.7, 29
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.L.str.8:
.asciz "%d\n"
.size .L.str.8, 4
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.L.str.9:
.asciz "q1b.txt"
.size .L.str.9, 8
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d"
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz ",%d"
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.asciz "_Z20global_reduce_kernelPiS_i"
.size .L__unnamed_1, 30
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.L__unnamed_2:
.asciz "_Z5partbPiS_i"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__global_reduce_kernelPiS_i
.addrsig_sym _Z20__device_stub__partbPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20global_reduce_kernelPiS_i
.addrsig_sym _Z5partbPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
CPU code, still some bugs.
*/
//#include <cuda_runtime.h>
//#include <vector>
//#include <string>
//#include <set>
//
//#include "load_obj.h"
//#include "collision.cuh"
//#include "check.cuh"
//#include "./common/book.h"
//#include "cpu.cuh"
//
//#define COL_MAX_LEN 1000000
//
//void printElapsedTime(cudaEvent_t* start, cudaEvent_t* stop, const char* opname) {
// printf("\nTime of %s: ", opname);
// float elapsedTime;
// HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime, *start, *stop));
// printf("%3.1f ms\n", elapsedTime);
//}
//
//void makeAndPrintSet(unsigned int* data, unsigned int num, const char* title)
//{
// set<unsigned int> dset;
// for (int i = 0; i < num; i++) {
// dset.insert(data[i]);
// }
//
// printf("\n\n%s£¨%u points in total£©:\n", title, dset.size());
// set<unsigned int>::iterator it;
// for (it = dset.begin(); it != dset.end(); it++) {
// printf("%u\n", *it);
// }
//}
//
//int main()
//{
// cudaEvent_t start, stop, m_start, m_stop;
// HANDLE_ERROR(cudaEventCreate(&start));
// HANDLE_ERROR(cudaEventCreate(&stop));
// HANDLE_ERROR(cudaEventCreate(&m_start));
// HANDLE_ERROR(cudaEventCreate(&m_stop));
//
// HANDLE_ERROR(cudaEventRecord(m_start, 0));
//
// const std::string file_path = "F:/¼á¹ûÔÆÎļþ/Îҵļá¹ûÔÆ/ÑÐÒ»ÉÏ/cuda/projects/CollisionDetection/flag-2000-changed.obj";
//
// std::vector<vec3f> vertexes;
// std::vector<Triangle> triangles;
// std::vector<unsigned long long int> mortons;
//
// loadObj(file_path, vertexes, triangles, mortons);
// const unsigned int m_size = mortons.size();
// const unsigned int v_size = vertexes.size();
//
// vec3f* v_ptr = &vertexes[0]; // new vec3f[v_size];
// Triangle* t_ptr = &triangles[0]; // new Triangle[m_size];
// unsigned long long int* m_ptr = &mortons[0]; // new unsigned long long int[m_size];
// Node* leaf_nodes = new Node[m_size];
// Node* internal_nodes = new Node[m_size-1];
// unsigned int* collision_list = new unsigned int[10000];
// unsigned int test_val;
//
// memset(collision_list, 0, 10000 * sizeof(unsigned int));
//
// /* Ìî³äÒ¶½Úµã */
// fillLeafNodesCpu(t_ptr, m_size, leaf_nodes);
//
// /* Éú³ÉBVH */
// printf("\n- before generateHierarchyParallel, wrongParentNum = %u\n", collision_list[0]);
// generateHierarchyParallelCpu(m_ptr, m_size, leaf_nodes, internal_nodes, collision_list);
// printf("\n- generateHierarchyParallel check result: wrongParentNum = %u, with total nodes=%u\n\n", collision_list[0], m_size-1);
//
// /* ¼ÆËã°üΧºÐ */
// calBoundingBoxCpu(leaf_nodes, v_ptr, m_size);
//
// /* ÄÚ²¿½ÚµãºÍÒ¶½Úµã×Ô¼ì */
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkInternalNodesCpu(internal_nodes, m_size - 1, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3], &collision_list[4]);
// printf("\n- Internal node check result: nullParentnum = %u, wrongBoundCount=%u, nullChildCount=%u, notInternalCount=%u, uninitBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], collision_list[4], m_size-1);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkLeafNodesCpu(leaf_nodes, m_size, &collision_list[0], &collision_list[1], &collision_list[2], &collision_list[3]);
// printf("\n- Leaf node check result: nullParentnum = %u, nullTriangle=%u, notLeafCount=%u, illegalBoxCount=%u, with total nodes=%u\n\n", collision_list[0], collision_list[1], collision_list[2], collision_list[3], m_size);
//
// memset(collision_list, 0, sizeof(unsigned int) * 5);
// checkTriangleIdxCpu(leaf_nodes, v_ptr, m_size, 632674, &collision_list[0]);
// printf("\n- Triangle check result: illegal triangle vidx num = %u, with total triangles=%u\n\n", collision_list[0], mortons.size());
// printf("\n$ triangle num = %u, mortons num = %u, vertex num = %u\n\n", triangles.size(), mortons.size(), vertexes.size());
//
// /* Ñ°ÕÒÅöײµã¶Ô */
// //findCollisionsCpu(internal_nodes, leaf_nodes, v_ptr, m_size, &test_val, collision_list);
// ////HANDLE_ERROR(cudaMemcpy(temp_nums, test_val, sizeof(unsigned int), cudaMemcpyDeviceToHost));
// ////HANDLE_ERROR(cudaMemcpy(h_collision_list, collision_list, 1000 * sizeof(unsigned int), cudaMemcpyDeviceToHost));
// //printf("\n\n- contact val = %u\n", test_val);
//
// //printf("\nCollision pair (%u triangle pairs in total):\n", test_val);
// //for (int i = 0; i < test_val; i++) {
// // printf("%07u - %07u\n", collision_list[2 * i], collision_list[2 * i + 1]);
// //}
//
// //makeAndPrintSet(collision_list, 2 * test_val, "Collision Triangles:");
//
// std::cout << "- Successfully Return" << std::endl;
//
// HANDLE_ERROR(cudaEventRecord(m_stop, 0)); HANDLE_ERROR(cudaEventSynchronize(m_stop));
// printElapsedTime(&m_start, &m_stop, "Total Time");
//
// printf("\n test for clzll: %u\n", clzll(4567, 1));
//
// //printf("\n test for __builtin_clz: %u\n", __builtin_clz(1278));
//
// return 0;
//} | code for sm_80 |
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