system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "point.cuh"
Point::Point() {}
Point::Point(double x_, double y_, bool border_x, bool border_y):
x(x_), y(y_), borderX(border_x), borderY(border_y) {}
double Point::getX() const {
return x;
}
double Point::getY() const {
return y;
}
bool Point::isBorderX() const {
return borderX;
}
bool Point::isBorderY() const {
return borderY;
}
double Point::distance(Point &other) {
double deltaX = x - other.x;
double deltaY = y - other.y;
return pow(deltaX * deltaX + deltaY * deltaY, 0.5);
}
void Point::move(double deltaX, double deltaY) {
x += deltaX;
y += deltaY;
}
__device__ bool Point::operator==(const Point& other) const {
return x == other.x && y == other.y;
}
__device__ bool Point::operator!=(const Point &other) const {
return !(*this == other);
}
ostream& operator<<(ostream& os, const Point &p) {
os << "(" << p.x << ", " << p.y << ")";
return os;
} | .file "tmpxft_0006a054_00000000-6_point.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3966:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3966:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN5PointC2Ev
.type _ZN5PointC2Ev, @function
_ZN5PointC2Ev:
.LFB3950:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3950:
.size _ZN5PointC2Ev, .-_ZN5PointC2Ev
.globl _ZN5PointC1Ev
.set _ZN5PointC1Ev,_ZN5PointC2Ev
.align 2
.globl _ZN5PointC2Eddbb
.type _ZN5PointC2Eddbb, @function
_ZN5PointC2Eddbb:
.LFB3953:
.cfi_startproc
endbr64
movsd %xmm0, (%rdi)
movsd %xmm1, 8(%rdi)
movb %sil, 16(%rdi)
movb %dl, 17(%rdi)
ret
.cfi_endproc
.LFE3953:
.size _ZN5PointC2Eddbb, .-_ZN5PointC2Eddbb
.globl _ZN5PointC1Eddbb
.set _ZN5PointC1Eddbb,_ZN5PointC2Eddbb
.align 2
.globl _ZNK5Point4getXEv
.type _ZNK5Point4getXEv, @function
_ZNK5Point4getXEv:
.LFB3955:
.cfi_startproc
endbr64
movsd (%rdi), %xmm0
ret
.cfi_endproc
.LFE3955:
.size _ZNK5Point4getXEv, .-_ZNK5Point4getXEv
.align 2
.globl _ZNK5Point4getYEv
.type _ZNK5Point4getYEv, @function
_ZNK5Point4getYEv:
.LFB3956:
.cfi_startproc
endbr64
movsd 8(%rdi), %xmm0
ret
.cfi_endproc
.LFE3956:
.size _ZNK5Point4getYEv, .-_ZNK5Point4getYEv
.align 2
.globl _ZNK5Point9isBorderXEv
.type _ZNK5Point9isBorderXEv, @function
_ZNK5Point9isBorderXEv:
.LFB3957:
.cfi_startproc
endbr64
movzbl 16(%rdi), %eax
ret
.cfi_endproc
.LFE3957:
.size _ZNK5Point9isBorderXEv, .-_ZNK5Point9isBorderXEv
.align 2
.globl _ZNK5Point9isBorderYEv
.type _ZNK5Point9isBorderYEv, @function
_ZNK5Point9isBorderYEv:
.LFB3958:
.cfi_startproc
endbr64
movzbl 17(%rdi), %eax
ret
.cfi_endproc
.LFE3958:
.size _ZNK5Point9isBorderYEv, .-_ZNK5Point9isBorderYEv
.align 2
.globl _ZN5Point8distanceERS_
.type _ZN5Point8distanceERS_, @function
_ZN5Point8distanceERS_:
.LFB3959:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsd (%rdi), %xmm0
subsd (%rsi), %xmm0
movsd 8(%rdi), %xmm1
subsd 8(%rsi), %xmm1
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
movsd .LC0(%rip), %xmm1
call pow@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3959:
.size _ZN5Point8distanceERS_, .-_ZN5Point8distanceERS_
.align 2
.globl _ZN5Point4moveEdd
.type _ZN5Point4moveEdd, @function
_ZN5Point4moveEdd:
.LFB3960:
.cfi_startproc
endbr64
addsd (%rdi), %xmm0
movsd %xmm0, (%rdi)
addsd 8(%rdi), %xmm1
movsd %xmm1, 8(%rdi)
ret
.cfi_endproc
.LFE3960:
.size _ZN5Point4moveEdd, .-_ZN5Point4moveEdd
.align 2
.globl _ZNK5PointeqERKS_
.type _ZNK5PointeqERKS_, @function
_ZNK5PointeqERKS_:
.LFB3961:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3961:
.size _ZNK5PointeqERKS_, .-_ZNK5PointeqERKS_
.align 2
.globl _ZNK5PointneERKS_
.type _ZNK5PointneERKS_, @function
_ZNK5PointneERKS_:
.LFB3962:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3962:
.size _ZNK5PointneERKS_, .-_ZNK5PointneERKS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "("
.LC2:
.string ", "
.LC3:
.string ")"
.text
.globl _ZlsRSoRK5Point
.type _ZlsRSoRK5Point, @function
_ZlsRSoRK5Point:
.LFB3963:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq %rsi, %r12
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%r12), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%r12), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3963:
.size _ZlsRSoRK5Point, .-_ZlsRSoRK5Point
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3989:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3989:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "point.cuh"
Point::Point() {}
Point::Point(double x_, double y_, bool border_x, bool border_y):
x(x_), y(y_), borderX(border_x), borderY(border_y) {}
double Point::getX() const {
return x;
}
double Point::getY() const {
return y;
}
bool Point::isBorderX() const {
return borderX;
}
bool Point::isBorderY() const {
return borderY;
}
double Point::distance(Point &other) {
double deltaX = x - other.x;
double deltaY = y - other.y;
return pow(deltaX * deltaX + deltaY * deltaY, 0.5);
}
void Point::move(double deltaX, double deltaY) {
x += deltaX;
y += deltaY;
}
__device__ bool Point::operator==(const Point& other) const {
return x == other.x && y == other.y;
}
__device__ bool Point::operator!=(const Point &other) const {
return !(*this == other);
}
ostream& operator<<(ostream& os, const Point &p) {
os << "(" << p.x << ", " << p.y << ")";
return os;
} | #ifndef point_cuh
#define point_cuh
#ifdef __HIPCC__
#define CUDA_HOSTDEV __host__ __device__
#define CUDA_DEV __device__
#else
#define CUDA_HOSTDEV
#define CUDA_DEV
#endif
#include <math.h>
#include <iostream>
#include <iomanip>
using namespace std;
/**
* represent a point (x,y) on the plane
* mutable; allows perturbing vertices
*/
class Point {
private:
double x, y;
// determine if point is on edge of image and thus cannot move
bool borderX, borderY;
public:
CUDA_HOSTDEV Point();
CUDA_HOSTDEV Point(double x, double y, bool borderX = false, bool borderY = false);
CUDA_HOSTDEV double getX() const;
CUDA_HOSTDEV double getY() const;
// return true if point was constructed on a vertical image edge
bool isBorderX() const;
bool isBorderY() const;
CUDA_HOSTDEV double distance(Point &other);
void move(double deltaX, double deltaY);
CUDA_DEV bool operator==(const Point &other) const;
CUDA_DEV bool operator!=(const Point &other) const;
friend ostream& operator<<(ostream& os, const Point &p);
};
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef point_cuh
#define point_cuh
#ifdef __HIPCC__
#define CUDA_HOSTDEV __host__ __device__
#define CUDA_DEV __device__
#else
#define CUDA_HOSTDEV
#define CUDA_DEV
#endif
#include <math.h>
#include <iostream>
#include <iomanip>
using namespace std;
/**
* represent a point (x,y) on the plane
* mutable; allows perturbing vertices
*/
class Point {
private:
double x, y;
// determine if point is on edge of image and thus cannot move
bool borderX, borderY;
public:
CUDA_HOSTDEV Point();
CUDA_HOSTDEV Point(double x, double y, bool borderX = false, bool borderY = false);
CUDA_HOSTDEV double getX() const;
CUDA_HOSTDEV double getY() const;
// return true if point was constructed on a vertical image edge
bool isBorderX() const;
bool isBorderY() const;
CUDA_HOSTDEV double distance(Point &other);
void move(double deltaX, double deltaY);
CUDA_DEV bool operator==(const Point &other) const;
CUDA_DEV bool operator!=(const Point &other) const;
friend ostream& operator<<(ostream& os, const Point &p);
};
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef point_cuh
#define point_cuh
#ifdef __HIPCC__
#define CUDA_HOSTDEV __host__ __device__
#define CUDA_DEV __device__
#else
#define CUDA_HOSTDEV
#define CUDA_DEV
#endif
#include <math.h>
#include <iostream>
#include <iomanip>
using namespace std;
/**
* represent a point (x,y) on the plane
* mutable; allows perturbing vertices
*/
class Point {
private:
double x, y;
// determine if point is on edge of image and thus cannot move
bool borderX, borderY;
public:
CUDA_HOSTDEV Point();
CUDA_HOSTDEV Point(double x, double y, bool borderX = false, bool borderY = false);
CUDA_HOSTDEV double getX() const;
CUDA_HOSTDEV double getY() const;
// return true if point was constructed on a vertical image edge
bool isBorderX() const;
bool isBorderY() const;
CUDA_HOSTDEV double distance(Point &other);
void move(double deltaX, double deltaY);
CUDA_DEV bool operator==(const Point &other) const;
CUDA_DEV bool operator!=(const Point &other) const;
friend ostream& operator<<(ostream& os, const Point &p);
};
#endif | .text
.file "point.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006a054_00000000-6_point.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3966:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3966:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN5PointC2Ev
.type _ZN5PointC2Ev, @function
_ZN5PointC2Ev:
.LFB3950:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE3950:
.size _ZN5PointC2Ev, .-_ZN5PointC2Ev
.globl _ZN5PointC1Ev
.set _ZN5PointC1Ev,_ZN5PointC2Ev
.align 2
.globl _ZN5PointC2Eddbb
.type _ZN5PointC2Eddbb, @function
_ZN5PointC2Eddbb:
.LFB3953:
.cfi_startproc
endbr64
movsd %xmm0, (%rdi)
movsd %xmm1, 8(%rdi)
movb %sil, 16(%rdi)
movb %dl, 17(%rdi)
ret
.cfi_endproc
.LFE3953:
.size _ZN5PointC2Eddbb, .-_ZN5PointC2Eddbb
.globl _ZN5PointC1Eddbb
.set _ZN5PointC1Eddbb,_ZN5PointC2Eddbb
.align 2
.globl _ZNK5Point4getXEv
.type _ZNK5Point4getXEv, @function
_ZNK5Point4getXEv:
.LFB3955:
.cfi_startproc
endbr64
movsd (%rdi), %xmm0
ret
.cfi_endproc
.LFE3955:
.size _ZNK5Point4getXEv, .-_ZNK5Point4getXEv
.align 2
.globl _ZNK5Point4getYEv
.type _ZNK5Point4getYEv, @function
_ZNK5Point4getYEv:
.LFB3956:
.cfi_startproc
endbr64
movsd 8(%rdi), %xmm0
ret
.cfi_endproc
.LFE3956:
.size _ZNK5Point4getYEv, .-_ZNK5Point4getYEv
.align 2
.globl _ZNK5Point9isBorderXEv
.type _ZNK5Point9isBorderXEv, @function
_ZNK5Point9isBorderXEv:
.LFB3957:
.cfi_startproc
endbr64
movzbl 16(%rdi), %eax
ret
.cfi_endproc
.LFE3957:
.size _ZNK5Point9isBorderXEv, .-_ZNK5Point9isBorderXEv
.align 2
.globl _ZNK5Point9isBorderYEv
.type _ZNK5Point9isBorderYEv, @function
_ZNK5Point9isBorderYEv:
.LFB3958:
.cfi_startproc
endbr64
movzbl 17(%rdi), %eax
ret
.cfi_endproc
.LFE3958:
.size _ZNK5Point9isBorderYEv, .-_ZNK5Point9isBorderYEv
.align 2
.globl _ZN5Point8distanceERS_
.type _ZN5Point8distanceERS_, @function
_ZN5Point8distanceERS_:
.LFB3959:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movsd (%rdi), %xmm0
subsd (%rsi), %xmm0
movsd 8(%rdi), %xmm1
subsd 8(%rsi), %xmm1
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
movsd .LC0(%rip), %xmm1
call pow@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3959:
.size _ZN5Point8distanceERS_, .-_ZN5Point8distanceERS_
.align 2
.globl _ZN5Point4moveEdd
.type _ZN5Point4moveEdd, @function
_ZN5Point4moveEdd:
.LFB3960:
.cfi_startproc
endbr64
addsd (%rdi), %xmm0
movsd %xmm0, (%rdi)
addsd 8(%rdi), %xmm1
movsd %xmm1, 8(%rdi)
ret
.cfi_endproc
.LFE3960:
.size _ZN5Point4moveEdd, .-_ZN5Point4moveEdd
.align 2
.globl _ZNK5PointeqERKS_
.type _ZNK5PointeqERKS_, @function
_ZNK5PointeqERKS_:
.LFB3961:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3961:
.size _ZNK5PointeqERKS_, .-_ZNK5PointeqERKS_
.align 2
.globl _ZNK5PointneERKS_
.type _ZNK5PointneERKS_, @function
_ZNK5PointneERKS_:
.LFB3962:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3962:
.size _ZNK5PointneERKS_, .-_ZNK5PointneERKS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "("
.LC2:
.string ", "
.LC3:
.string ")"
.text
.globl _ZlsRSoRK5Point
.type _ZlsRSoRK5Point, @function
_ZlsRSoRK5Point:
.LFB3963:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movq %rsi, %r12
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%r12), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $2, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%r12), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3963:
.size _ZlsRSoRK5Point, .-_ZlsRSoRK5Point
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3989:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3989:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1071644672
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "point.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a, int *b,int *c)
{
*c = *a + *b;
}
int main()
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size =sizeof(int);// Allocate space for device copies of a, b, c
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
// Setup input values
a = 26754;
b = 73456;
// Copy inputs to device
cudaMemcpy(d_a, &a, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size,cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
add <<<1, 1 >>>(d_a,d_b,d_c);
// Copy result back to host
cudaMemcpy(&c,d_c, size,cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("toplam sonucu : %d\n", c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a, int *b,int *c)
{
*c = *a + *b;
}
int main()
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size =sizeof(int);// Allocate space for device copies of a, b, c
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
// Setup input values
a = 26754;
b = 73456;
// Copy inputs to device
cudaMemcpy(d_a, &a, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size,cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
add <<<1, 1 >>>(d_a,d_b,d_c);
// Copy result back to host
cudaMemcpy(&c,d_c, size,cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("toplam sonucu : %d\n", c);
return 0;
} | .file "tmpxft_000669eb_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "toplam sonucu : %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $26754, (%rsp)
movl $73456, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a, int *b,int *c)
{
*c = *a + *b;
}
int main()
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size =sizeof(int);// Allocate space for device copies of a, b, c
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
// Setup input values
a = 26754;
b = 73456;
// Copy inputs to device
cudaMemcpy(d_a, &a, size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &b, size,cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
add <<<1, 1 >>>(d_a,d_b,d_c);
// Copy result back to host
cudaMemcpy(&c,d_c, size,cudaMemcpyDeviceToHost);
// Cleanup
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("toplam sonucu : %d\n", c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a, int *b,int *c)
{
*c = *a + *b;
}
int main()
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size =sizeof(int);// Allocate space for device copies of a, b, c
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
// Setup input values
a = 26754;
b = 73456;
// Copy inputs to device
hipMemcpy(d_a, &a, size,hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size,hipMemcpyHostToDevice);
// Launch add() kernel on GPU
add <<<1, 1 >>>(d_a,d_b,d_c);
// Copy result back to host
hipMemcpy(&c,d_c, size,hipMemcpyDeviceToHost);
// Cleanup
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("toplam sonucu : %d\n", c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a, int *b,int *c)
{
*c = *a + *b;
}
int main()
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size =sizeof(int);// Allocate space for device copies of a, b, c
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
// Setup input values
a = 26754;
b = 73456;
// Copy inputs to device
hipMemcpy(d_a, &a, size,hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size,hipMemcpyHostToDevice);
// Launch add() kernel on GPU
add <<<1, 1 >>>(d_a,d_b,d_c);
// Copy result back to host
hipMemcpy(&c,d_c, size,hipMemcpyDeviceToHost);
// Cleanup
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("toplam sonucu : %d\n", c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a, int *b,int *c)
{
*c = *a + *b;
}
int main()
{
int a, b, c; // host copies of a, b, c
int *d_a, *d_b, *d_c; // device copies of a, b, c
int size =sizeof(int);// Allocate space for device copies of a, b, c
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
// Setup input values
a = 26754;
b = 73456;
// Copy inputs to device
hipMemcpy(d_a, &a, size,hipMemcpyHostToDevice);
hipMemcpy(d_b, &b, size,hipMemcpyHostToDevice);
// Launch add() kernel on GPU
add <<<1, 1 >>>(d_a,d_b,d_c);
// Copy result back to host
hipMemcpy(&c,d_c, size,hipMemcpyDeviceToHost);
// Cleanup
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("toplam sonucu : %d\n", c);
return 0;
} | .text
.file "kernel.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $26754, 28(%rsp) # imm = 0x6882
movl $73456, 24(%rsp) # imm = 0x11EF0
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "toplam sonucu : %d\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000669eb_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "toplam sonucu : %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $26754, (%rsp)
movl $73456, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $26754, 28(%rsp) # imm = 0x6882
movl $73456, 24(%rsp) # imm = 0x11EF0
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "toplam sonucu : %d\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calcReluBackwardGPU( float *dz_next_layer, float *dz_in, float *dz, float *in, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < elements ){
dz_in[id] += dz_next_layer[id];
dz[id] += (in[id] < 0) ? (0) : (1.0 * dz_in[id]);
}
/* original
for( unsigned i = 0; i < data_size; ++i ){
dz_in.data[i] += dz_next_layer.data[i];
dz.data[i] += (in.data[i] < 0) ? (0) : (1.0 * dz_in.data[i]);
}
*/
} | code for sm_80
Function : _Z19calcReluBackwardGPUPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R10, R0, R7, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R15, R6, R3 ; /* 0x00000003060f7221 */
/* 0x004fe40000000000 */
/*0100*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc600078e0207 */
/*0110*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x000fe8000c101904 */
/*0120*/ LDG.E R0, [R10.64] ; /* 0x000000040a007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0140*/ F2F.F64.F32 R8, R15 ; /* 0x0000000f00087310 */
/* 0x000e300000201800 */
/*0150*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x004e620000201800 */
/*0160*/ FSETP.GEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x008fc80003f0e000 */
/*0170*/ FSEL R2, R8, RZ, P0 ; /* 0x000000ff08027208 */
/* 0x001fe40000000000 */
/*0180*/ FSEL R3, R9, RZ, P0 ; /* 0x000000ff09037208 */
/* 0x000fcc0000000000 */
/*0190*/ DADD R12, R12, R2 ; /* 0x000000000c0c7229 */
/* 0x002e140000000002 */
/*01a0*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x001e240000301000 */
/*01b0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x001fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calcReluBackwardGPU( float *dz_next_layer, float *dz_in, float *dz, float *in, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < elements ){
dz_in[id] += dz_next_layer[id];
dz[id] += (in[id] < 0) ? (0) : (1.0 * dz_in[id]);
}
/* original
for( unsigned i = 0; i < data_size; ++i ){
dz_in.data[i] += dz_next_layer.data[i];
dz.data[i] += (in.data[i] < 0) ? (0) : (1.0 * dz_in.data[i]);
}
*/
} | .file "tmpxft_001a271b_00000000-6_calcReluBackwardGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i
.type _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i, @function
_Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19calcReluBackwardGPUPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i, .-_Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i
.globl _Z19calcReluBackwardGPUPfS_S_S_i
.type _Z19calcReluBackwardGPUPfS_S_S_i, @function
_Z19calcReluBackwardGPUPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19calcReluBackwardGPUPfS_S_S_i, .-_Z19calcReluBackwardGPUPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19calcReluBackwardGPUPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcReluBackwardGPUPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calcReluBackwardGPU( float *dz_next_layer, float *dz_in, float *dz, float *in, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < elements ){
dz_in[id] += dz_next_layer[id];
dz[id] += (in[id] < 0) ? (0) : (1.0 * dz_in[id]);
}
/* original
for( unsigned i = 0; i < data_size; ++i ){
dz_in.data[i] += dz_next_layer.data[i];
dz.data[i] += (in.data[i] < 0) ? (0) : (1.0 * dz_in.data[i]);
}
*/
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcReluBackwardGPU( float *dz_next_layer, float *dz_in, float *dz, float *in, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < elements ){
dz_in[id] += dz_next_layer[id];
dz[id] += (in[id] < 0) ? (0) : (1.0 * dz_in[id]);
}
/* original
for( unsigned i = 0; i < data_size; ++i ){
dz_in.data[i] += dz_next_layer.data[i];
dz.data[i] += (in.data[i] < 0) ? (0) : (1.0 * dz_in.data[i]);
}
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcReluBackwardGPU( float *dz_next_layer, float *dz_in, float *dz, float *in, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < elements ){
dz_in[id] += dz_next_layer[id];
dz[id] += (in[id] < 0) ? (0) : (1.0 * dz_in[id]);
}
/* original
for( unsigned i = 0; i < data_size; ++i ){
dz_in.data[i] += dz_next_layer.data[i];
dz.data[i] += (in.data[i] < 0) ? (0) : (1.0 * dz_in.data[i]);
}
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19calcReluBackwardGPUPfS_S_S_i
.globl _Z19calcReluBackwardGPUPfS_S_S_i
.p2align 8
.type _Z19calcReluBackwardGPUPfS_S_S_i,@function
_Z19calcReluBackwardGPUPfS_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v2, v3
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[4:5], v6, off
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b32 v4, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v7, v[0:1], off
v_cvt_f64_f32_e32 v[0:1], v6
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
v_add_f64 v[0:1], v[0:1], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcReluBackwardGPUPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19calcReluBackwardGPUPfS_S_S_i, .Lfunc_end0-_Z19calcReluBackwardGPUPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcReluBackwardGPUPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calcReluBackwardGPUPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calcReluBackwardGPU( float *dz_next_layer, float *dz_in, float *dz, float *in, int elements )
{
int id = (blockIdx.x + blockIdx.y*gridDim.x) * blockDim.x + threadIdx.x;
if( id < elements ){
dz_in[id] += dz_next_layer[id];
dz[id] += (in[id] < 0) ? (0) : (1.0 * dz_in[id]);
}
/* original
for( unsigned i = 0; i < data_size; ++i ){
dz_in.data[i] += dz_next_layer.data[i];
dz.data[i] += (in.data[i] < 0) ? (0) : (1.0 * dz_in.data[i]);
}
*/
} | .text
.file "calcReluBackwardGPU.hip"
.globl _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i # -- Begin function _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.p2align 4, 0x90
.type _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i,@function
_Z34__device_stub__calcReluBackwardGPUPfS_S_S_i: # @_Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19calcReluBackwardGPUPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i, .Lfunc_end0-_Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcReluBackwardGPUPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19calcReluBackwardGPUPfS_S_S_i,@object # @_Z19calcReluBackwardGPUPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z19calcReluBackwardGPUPfS_S_S_i
.p2align 3, 0x0
_Z19calcReluBackwardGPUPfS_S_S_i:
.quad _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.size _Z19calcReluBackwardGPUPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19calcReluBackwardGPUPfS_S_S_i"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19calcReluBackwardGPUPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19calcReluBackwardGPUPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R10, R0, R7, c[0x0][0x170] ; /* 0x00005c00000a7625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R15, R6, R3 ; /* 0x00000003060f7221 */
/* 0x004fe40000000000 */
/*0100*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc600078e0207 */
/*0110*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x000fe8000c101904 */
/*0120*/ LDG.E R0, [R10.64] ; /* 0x000000040a007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0140*/ F2F.F64.F32 R8, R15 ; /* 0x0000000f00087310 */
/* 0x000e300000201800 */
/*0150*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x004e620000201800 */
/*0160*/ FSETP.GEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x008fc80003f0e000 */
/*0170*/ FSEL R2, R8, RZ, P0 ; /* 0x000000ff08027208 */
/* 0x001fe40000000000 */
/*0180*/ FSEL R3, R9, RZ, P0 ; /* 0x000000ff09037208 */
/* 0x000fcc0000000000 */
/*0190*/ DADD R12, R12, R2 ; /* 0x000000000c0c7229 */
/* 0x002e140000000002 */
/*01a0*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x001e240000301000 */
/*01b0*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x001fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19calcReluBackwardGPUPfS_S_S_i
.globl _Z19calcReluBackwardGPUPfS_S_S_i
.p2align 8
.type _Z19calcReluBackwardGPUPfS_S_S_i,@function
_Z19calcReluBackwardGPUPfS_S_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v6, v2, v3
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[4:5], v6, off
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b32 v4, v[2:3], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v7, v[0:1], off
v_cvt_f64_f32_e32 v[0:1], v6
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[4:5], v4
s_waitcnt vmcnt(0)
v_cmp_ngt_f32_e32 vcc_lo, 0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
v_add_f64 v[0:1], v[0:1], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[2:3], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19calcReluBackwardGPUPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19calcReluBackwardGPUPfS_S_S_i, .Lfunc_end0-_Z19calcReluBackwardGPUPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19calcReluBackwardGPUPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19calcReluBackwardGPUPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a271b_00000000-6_calcReluBackwardGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i
.type _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i, @function
_Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19calcReluBackwardGPUPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i, .-_Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i
.globl _Z19calcReluBackwardGPUPfS_S_S_i
.type _Z19calcReluBackwardGPUPfS_S_S_i, @function
_Z19calcReluBackwardGPUPfS_S_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z19calcReluBackwardGPUPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19calcReluBackwardGPUPfS_S_S_i, .-_Z19calcReluBackwardGPUPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19calcReluBackwardGPUPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19calcReluBackwardGPUPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calcReluBackwardGPU.hip"
.globl _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i # -- Begin function _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.p2align 4, 0x90
.type _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i,@function
_Z34__device_stub__calcReluBackwardGPUPfS_S_S_i: # @_Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19calcReluBackwardGPUPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i, .Lfunc_end0-_Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19calcReluBackwardGPUPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19calcReluBackwardGPUPfS_S_S_i,@object # @_Z19calcReluBackwardGPUPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z19calcReluBackwardGPUPfS_S_S_i
.p2align 3, 0x0
_Z19calcReluBackwardGPUPfS_S_S_i:
.quad _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.size _Z19calcReluBackwardGPUPfS_S_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19calcReluBackwardGPUPfS_S_S_i"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__calcReluBackwardGPUPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19calcReluBackwardGPUPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>
#include<cuda_runtime.h>
namespace Neighbours
{
class FileHandle
{
public:
int InputSize(void)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
int N = 0;
while(fgets(line, 30, input) != NULL)
N++;
fclose(input);
return N;
}
void ReadFromFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
for(int i = 0; i < (*N); i++)
{
fgets(line, 30, input);
sscanf(line, "%lf %lf %lf", &x[i], &y[i], &z[i]);
b[i] = true;
}
fclose(input);
printf("Data imported from input.txt successfully!\n");
}
void WriteToFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *output = NULL;
output = fopen("output.txt", "w");
for(int i = 0; i < (*N); i++)
{
if(b[i] == true)
fprintf(output, "%.1lf %.1lf %.1lf\n", x[i], y[i], z[i]);
}
fclose(output);
printf("Data exported to output.txt successfully!\n");
}
};
__global__ void kernel(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < *d_N)
{
if((pow((*x)-d_xx[index], 2) + pow((*y)-d_yy[index], 2) + pow((*z)-d_zz[index], 2)) > pow(*r, 2))
d_bb[index] = false;
}
}
class NeighbourSearch
{
public:
void FindNeighbours(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int grid_size, block_size = 256;
grid_size = ((*d_N) + block_size) / block_size;
kernel<<<grid_size, block_size>>>(d_xx, d_yy, d_zz, d_bb, d_N, x, y, z, r);
cudaDeviceSynchronize();
}
};
} // namespace Neighbours
int main()
{
Neighbours::FileHandle fh = Neighbours::FileHandle();
double *x, *y, *z;
double *r;
double *xx, *yy, *zz;
bool *bb;
int *N;
cudaMallocManaged(&N, sizeof(int));
*N = fh.InputSize();
cudaMallocManaged(&x, sizeof(double));
cudaMallocManaged(&y, sizeof(double));
cudaMallocManaged(&z, sizeof(double));
cudaMallocManaged(&r, sizeof(double));
cudaMallocManaged(&xx, sizeof(double)*(*N));
cudaMallocManaged(&yy, sizeof(double)*(*N));
cudaMallocManaged(&zz, sizeof(double)*(*N));
cudaMallocManaged(&bb, sizeof(double)*(*N));
fh.ReadFromFile(xx, yy, zz, bb, N);
Neighbours::NeighbourSearch ns = Neighbours::NeighbourSearch();
while(1)
{
printf("Enter the x, y and z coordinates of the point and the search distance:\t");
scanf("%lf %lf %lf %lf", x, y, z, r);
if((*r) <= 0)
break;
else
{
ns.FindNeighbours(xx, yy, zz, bb, N, x, y, z, r);
fh.WriteToFile(xx, yy, zz, bb, N);
}
}
cudaFree(xx);
cudaFree(yy);
cudaFree(zz);
cudaFree(bb);
cudaFree(N);
cudaFree(x);
cudaFree(y);
cudaFree(z);
cudaFree(r);
printf("Program terminated.\n");
return 0;
} | code for sm_80
Function : _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff077624 */
/* 0x000fe400078e00ff */
/*00d0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*00e0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ BSSY B0, 0x170 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0110*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0120*/ MOV R2, 0x160 ; /* 0x0000016000027802 */
/* 0x000fe20000000f00 */
/*0130*/ DADD R8, -R4, R6 ; /* 0x0000000004087229 */
/* 0x004e0c0000000106 */
/*0140*/ DADD R10, -RZ, |R8| ; /* 0x00000000ff0a7229 */
/* 0x00104c0000000508 */
/*0150*/ CALL.REL.NOINC 0x930 ; /* 0x000007d000007944 */
/* 0x003fea0003c00000 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ DADD R4, R8.reuse, 2 ; /* 0x4000000008047429 */
/* 0x040e220000000000 */
/*0180*/ BSSY B0, 0x290 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*0190*/ DSETP.NEU.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800722a */
/* 0x000e4c0003f0d000 */
/*01a0*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x001fc800078ec0ff */
/*01b0*/ ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fc80003f25270 */
/*01c0*/ @!P0 CS2R R20, SRZ ; /* 0x0000000000148805 */
/* 0x002fd2000001ff00 */
/*01d0*/ @P1 BRA 0x280 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*01e0*/ DSETP.GTU.AND P0, PT, |R8|, +INF , PT ; /* 0x7ff000000800742a */
/* 0x000e1c0003f0c200 */
/*01f0*/ @P0 BRA 0x270 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0200*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0210*/ LOP3.LUT R2, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09027812 */
/* 0x000fc800078ec0ff */
/*0220*/ ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; /* 0x7ff000000200780c */
/* 0x000fda0000705670 */
/*0230*/ @P0 BRA 0x280 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R20, RZ, RZ, 0x0 ; /* 0x00000000ff147424 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R21, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff157424 */
/* 0x000fe200078e00ff */
/*0260*/ BRA 0x280 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0270*/ DADD R20, R8, 2 ; /* 0x4000000008147429 */
/* 0x00004c0000000000 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.SHL.U32 R4, R0.reuse, 0x8, RZ ; /* 0x0000000800047824 */
/* 0x040fe200078e00ff */
/*02a0*/ SHF.L.U64.HI R5, R0, 0x3, R3 ; /* 0x0000000300057819 */
/* 0x000fe20000010203 */
/*02b0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fe200078e00ff */
/*02d0*/ IADD3 R14, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a00040e7a10 */
/* 0x000fc80007f1e0ff */
/*02e0*/ IADD3.X R15, R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00050f7a10 */
/* 0x000fe200007fe4ff */
/*02f0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1b00 */
/*0300*/ LDG.E.64 R6, [R14.64] ; /* 0x000000040e067981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DSETP.NEU.AND P0, PT, R8, 1, PT ; /* 0x3ff000000800742a */
/* 0x000ee20003f0d000 */
/*0320*/ BSSY B0, 0x3a0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0330*/ MOV R2, 0x390 ; /* 0x0000039000027802 */
/* 0x000fc80000000f00 */
/*0340*/ FSEL R8, R20, RZ, P0 ; /* 0x000000ff14087208 */
/* 0x00bfe40000000000 */
/*0350*/ FSEL R9, R21, 1.875, P0 ; /* 0x3ff0000015097808 */
/* 0x000fe20000000000 */
/*0360*/ DADD R6, -R6, R12 ; /* 0x0000000006067229 */
/* 0x004e0c000000010c */
/*0370*/ DADD R10, -RZ, |R6| ; /* 0x00000000ff0a7229 */
/* 0x00104c0000000506 */
/*0380*/ CALL.REL.NOINC 0x930 ; /* 0x000005a000007944 */
/* 0x003fea0003c00000 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ DADD R10, R6.reuse, 2 ; /* 0x40000000060a7429 */
/* 0x040e220000000000 */
/*03b0*/ BSSY B0, 0x4c0 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*03c0*/ DSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e4c0003f0d000 */
/*03d0*/ LOP3.LUT R10, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0a7812 */
/* 0x001fc800078ec0ff */
/*03e0*/ ISETP.NE.AND P1, PT, R10, 0x7ff00000, PT ; /* 0x7ff000000a00780c */
/* 0x000fc80003f25270 */
/*03f0*/ @!P0 CS2R R20, SRZ ; /* 0x0000000000148805 */
/* 0x002fd2000001ff00 */
/*0400*/ @P1 BRA 0x4b0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0410*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*0420*/ @P0 BRA 0x4a0 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0430*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0440*/ LOP3.LUT R2, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07027812 */
/* 0x000fc800078ec0ff */
/*0450*/ ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; /* 0x7ff000000200780c */
/* 0x000fda0000705670 */
/*0460*/ @P0 BRA 0x4b0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.MOV.U32 R20, RZ, RZ, 0x0 ; /* 0x00000000ff147424 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R21, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff157424 */
/* 0x000fe200078e00ff */
/*0490*/ BRA 0x4b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*04a0*/ DADD R20, R6, 2 ; /* 0x4000000006147429 */
/* 0x00004c0000000000 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R14, P0, R4, c[0x0][0x170], RZ ; /* 0x00005c00040e7a10 */
/* 0x000fe20007f1e0ff */
/*04d0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x198] ; /* 0x00006600ff0c7624 */
/* 0x000fe400078e00ff */
/*04e0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x19c] ; /* 0x00006700ff0d7624 */
/* 0x000fe200078e00ff */
/*04f0*/ IADD3.X R15, R5, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00050f7a10 */
/* 0x000fca00007fe4ff */
/*0500*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1b00 */
/*0510*/ LDG.E.64 R4, [R14.64] ; /* 0x000000040e047981 */
/* 0x000ea2000c1e1b00 */
/*0520*/ DSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3ff000000600742a */
/* 0x000ee20003f0d000 */
/*0530*/ BSSY B0, 0x5c0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0540*/ MOV R2, 0x5b0 ; /* 0x000005b000027802 */
/* 0x000fc80000000f00 */
/*0550*/ FSEL R6, R20, RZ, P0 ; /* 0x000000ff14067208 */
/* 0x00bfe40000000000 */
/*0560*/ FSEL R7, R21, 1.875, P0 ; /* 0x3ff0000015077808 */
/* 0x000fcc0000000000 */
/*0570*/ DADD R8, R8, R6 ; /* 0x0000000008087229 */
/* 0x000fc80000000006 */
/*0580*/ DADD R4, -R4, R12 ; /* 0x0000000004047229 */
/* 0x004e0c000000010c */
/*0590*/ DADD R10, -RZ, |R4| ; /* 0x00000000ff0a7229 */
/* 0x00104c0000000504 */
/*05a0*/ CALL.REL.NOINC 0x930 ; /* 0x0000038000007944 */
/* 0x003fea0003c00000 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ DADD R6, R4.reuse, 2 ; /* 0x4000000004067429 */
/* 0x040e220000000000 */
/*05d0*/ BSSY B0, 0x6e0 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*05e0*/ DSETP.NEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e4c0003f0d000 */
/*05f0*/ LOP3.LUT R6, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007067812 */
/* 0x001fc800078ec0ff */
/*0600*/ ISETP.NE.AND P1, PT, R6, 0x7ff00000, PT ; /* 0x7ff000000600780c */
/* 0x000fc80003f25270 */
/*0610*/ @!P0 CS2R R20, SRZ ; /* 0x0000000000148805 */
/* 0x002fd2000001ff00 */
/*0620*/ @P1 BRA 0x6d0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0630*/ DSETP.GTU.AND P0, PT, |R4|, +INF , PT ; /* 0x7ff000000400742a */
/* 0x000e1c0003f0c200 */
/*0640*/ @P0 BRA 0x6c0 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0650*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0660*/ LOP3.LUT R2, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05027812 */
/* 0x000fc800078ec0ff */
/*0670*/ ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; /* 0x7ff000000200780c */
/* 0x000fda0000705670 */
/*0680*/ @P0 BRA 0x6d0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.MOV.U32 R20, RZ, RZ, 0x0 ; /* 0x00000000ff147424 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff157424 */
/* 0x000fe200078e00ff */
/*06b0*/ BRA 0x6d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06c0*/ DADD R20, R4, 2 ; /* 0x4000000004147429 */
/* 0x00004c0000000000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x1a0] ; /* 0x00006800ff067624 */
/* 0x000fe400078e00ff */
/*06f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x1a4] ; /* 0x00006900ff077624 */
/* 0x000fcc00078e00ff */
/*0700*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0710*/ DSETP.NEU.AND P0, PT, R4, 1, PT ; /* 0x3ff000000400742a */
/* 0x000ee20003f0d000 */
/*0720*/ BSSY B0, 0x7a0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0730*/ MOV R2, 0x790 ; /* 0x0000079000027802 */
/* 0x000fc80000000f00 */
/*0740*/ FSEL R4, R20, RZ, P0 ; /* 0x000000ff14047208 */
/* 0x00bfe40000000000 */
/*0750*/ FSEL R5, R21, 1.875, P0 ; /* 0x3ff0000015057808 */
/* 0x000fcc0000000000 */
/*0760*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x0000480000000004 */
/*0770*/ DADD R10, -RZ, |R6| ; /* 0x00000000ff0a7229 */
/* 0x00408c0000000506 */
/*0780*/ CALL.REL.NOINC 0x930 ; /* 0x000001a000007944 */
/* 0x007fea0003c00000 */
/*0790*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07a0*/ DADD R4, R6, 2 ; /* 0x4000000006047429 */
/* 0x000e080000000000 */
/*07b0*/ DSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e4c0003f0d000 */
/*07c0*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x001fc800078ec0ff */
/*07d0*/ ISETP.NE.AND P1, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fc80003f25270 */
/*07e0*/ @!P0 CS2R R20, SRZ ; /* 0x0000000000148805 */
/* 0x002fd2000001ff00 */
/*07f0*/ @P1 BRA 0x8a0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0800*/ DSETP.GTU.AND P0, PT, |R6|, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e1c0003f0c200 */
/*0810*/ @P0 BRA 0x890 ; /* 0x0000007000000947 */
/* 0x001fea0003800000 */
/*0820*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0830*/ LOP3.LUT R2, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07027812 */
/* 0x000fc800078ec0ff */
/*0840*/ ISETP.NE.OR P0, PT, R2, 0x7ff00000, P0 ; /* 0x7ff000000200780c */
/* 0x000fda0000705670 */
/*0850*/ @P0 BRA 0x8a0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0860*/ IMAD.MOV.U32 R20, RZ, RZ, 0x0 ; /* 0x00000000ff147424 */
/* 0x000fe400078e00ff */
/*0870*/ IMAD.MOV.U32 R21, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff157424 */
/* 0x000fe200078e00ff */
/*0880*/ BRA 0x8a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0890*/ DADD R20, R6, 2 ; /* 0x4000000006147429 */
/* 0x0000480000000000 */
/*08a0*/ DSETP.NEU.AND P0, PT, R6, 1, PT ; /* 0x3ff000000600742a */
/* 0x000e8c0003f0d000 */
/*08b0*/ FSEL R4, R20, RZ, P0 ; /* 0x000000ff14047208 */
/* 0x006fe40000000000 */
/*08c0*/ FSEL R5, R21, 1.875, P0 ; /* 0x3ff0000015057808 */
/* 0x000fcc0000000000 */
/*08d0*/ DSETP.GT.AND P0, PT, R8, R4, PT ; /* 0x000000040800722a */
/* 0x000e5c0003f04000 */
/*08e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x002fea0003800000 */
/*08f0*/ IADD3 R2, P0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a10 */
/* 0x000fc80007f1e0ff */
/*0900*/ IADD3.X R3, R3, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0003037a10 */
/* 0x000fca00007fe4ff */
/*0910*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ SHF.R.U32.HI R26, RZ, 0x14, R11 ; /* 0x00000014ff1a7819 */
/* 0x000fc8000001160b */
/*0940*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fda0003f05270 */
/*0950*/ @!P0 DMUL R24, R10, 1.80143985094819840000e+16 ; /* 0x435000000a188828 */
/* 0x000e140000000000 */
/*0960*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, R25 ; /* 0x000000ffff0b8224 */
/* 0x001fe200078e0019 */
/*0970*/ @!P0 LEA.HI R26, R25, 0xffffffca, RZ, 0xc ; /* 0xffffffca191a8811 */
/* 0x000fe200078f60ff */
/*0980*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, R24 ; /* 0x000000ffff0a8224 */
/* 0x000fc600078e0018 */
/*0990*/ LOP3.LUT R11, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b0b7812 */
/* 0x000fe200078ec0ff */
/*09a0*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e000a */
/*09b0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*09c0*/ LOP3.LUT R15, R11, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000b0f7812 */
/* 0x000fc800078efcff */
/*09d0*/ ISETP.GE.U32.AND P1, PT, R15, 0x3ff6a09f, PT ; /* 0x3ff6a09f0f00780c */
/* 0x000fda0003f26070 */
/*09e0*/ @P1 IADD3 R11, R15, -0x100000, RZ ; /* 0xfff000000f0b1810 */
/* 0x000fca0007ffe0ff */
/*09f0*/ @P1 IMAD.MOV.U32 R15, RZ, RZ, R11 ; /* 0x000000ffff0f1224 */
/* 0x000fcc00078e000b */
/*0a00*/ DADD R16, R14, 1 ; /* 0x3ff000000e107429 */
/* 0x000e080000000000 */
/*0a10*/ DADD R14, R14, -1 ; /* 0xbff000000e0e7429 */
/* 0x000fe40000000000 */
/*0a20*/ MUFU.RCP64H R11, R17 ; /* 0x00000011000b7308 */
/* 0x001e240000001800 */
/*0a30*/ DFMA R20, -R16, R10, 1 ; /* 0x3ff000001014742b */
/* 0x001e0c000000010a */
/*0a40*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e0c0000000014 */
/*0a50*/ DFMA R20, R10, R20, R10 ; /* 0x000000140a14722b */
/* 0x001064000000000a */
/*0a60*/ IMAD.MOV.U32 R10, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff0a7424 */
/* 0x001fe400078e00ff */
/*0a70*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff0b7424 */
/* 0x000fe400078e00ff */
/*0a80*/ DMUL R12, R20, R14 ; /* 0x0000000e140c7228 */
/* 0x002e0c0000000000 */
/*0a90*/ DFMA R12, R20, R14, R12 ; /* 0x0000000e140c722b */
/* 0x001e0c000000000c */
/*0aa0*/ DMUL R18, R12, R12 ; /* 0x0000000c0c127228 */
/* 0x001e0c0000000000 */
/*0ab0*/ DFMA R10, R18, R10, c[0x2][0x0] ; /* 0x00800000120a762b */
/* 0x001e0c000000000a */
/*0ac0*/ DFMA R16, R18, R10, c[0x2][0x8] ; /* 0x008002001210762b */
/* 0x001e08000000000a */
/*0ad0*/ DADD R10, R14, -R12 ; /* 0x000000000e0a7229 */
/* 0x000e48000000080c */
/*0ae0*/ DFMA R16, R18, R16, c[0x2][0x10] ; /* 0x008004001210762b */
/* 0x001e080000000010 */
/*0af0*/ DADD R10, R10, R10 ; /* 0x000000000a0a7229 */
/* 0x002e48000000000a */
/*0b00*/ DFMA R16, R18, R16, c[0x2][0x18] ; /* 0x008006001210762b */
/* 0x001e080000000010 */
/*0b10*/ DFMA R10, R14, -R12, R10 ; /* 0x8000000c0e0a722b */
/* 0x002e48000000000a */
/*0b20*/ DFMA R16, R18, R16, c[0x2][0x20] ; /* 0x008008001210762b */
/* 0x001e080000000010 */
/*0b30*/ DMUL R10, R20, R10 ; /* 0x0000000a140a7228 */
/* 0x002fc80000000000 */
/*0b40*/ DFMA R16, R18, R16, c[0x2][0x28] ; /* 0x00800a001210762b */
/* 0x001e080000000010 */
/*0b50*/ DMUL R20, R12, R12 ; /* 0x0000000c0c147228 */
/* 0x000fc80000000000 */
/*0b60*/ DFMA R14, R18, R16, c[0x2][0x30] ; /* 0x00800c00120e762b */
/* 0x001e0c0000000010 */
/*0b70*/ DADD R22, -R14, c[0x2][0x30] ; /* 0x00800c000e167629 */
/* 0x001e0c0000000100 */
/*0b80*/ DFMA R22, R18, R16, R22 ; /* 0x000000101216722b */
/* 0x0010640000000016 */
/*0b90*/ IADD3 R19, R11, 0x100000, RZ ; /* 0x001000000b137810 */
/* 0x001fe20007ffe0ff */
/*0ba0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe200078e000a */
/*0bb0*/ DFMA R16, R12, R12, -R20 ; /* 0x0000000c0c10722b */
/* 0x000e080000000814 */
/*0bc0*/ DADD R22, RZ, R22 ; /* 0x00000000ff167229 */
/* 0x002e480000000016 */
/*0bd0*/ DFMA R18, R12, R18, R16 ; /* 0x000000120c12722b */
/* 0x001fc80000000010 */
/*0be0*/ DMUL R16, R12, R20 ; /* 0x000000140c107228 */
/* 0x000e080000000000 */
/*0bf0*/ DADD R22, R22, c[0x2][0x38] ; /* 0x00800e0016167629 */
/* 0x002fc80000000000 */
/*0c00*/ DFMA R24, R12, R20, -R16 ; /* 0x000000140c18722b */
/* 0x001e0c0000000810 */
/*0c10*/ DFMA R24, R10, R20, R24 ; /* 0x000000140a18722b */
/* 0x001e080000000018 */
/*0c20*/ DADD R20, R14, R22 ; /* 0x000000000e147229 */
/* 0x000e480000000016 */
/*0c30*/ DFMA R18, R12, R18, R24 ; /* 0x000000120c12722b */
/* 0x001fc80000000018 */
/*0c40*/ DADD R24, R14, -R20 ; /* 0x000000000e187229 */
/* 0x002e080000000814 */
/*0c50*/ DMUL R14, R20, R16 ; /* 0x00000010140e7228 */
/* 0x000e480000000000 */
/*0c60*/ DADD R24, R22, R24 ; /* 0x0000000016187229 */
/* 0x001fc80000000018 */
/*0c70*/ DFMA R22, R20, R16, -R14 ; /* 0x000000101416722b */
/* 0x002e0c000000080e */
/*0c80*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x001e0c0000000016 */
/*0c90*/ DFMA R24, R24, R16, R18 ; /* 0x000000101818722b */
/* 0x001e0c0000000012 */
/*0ca0*/ DADD R18, R14, R24 ; /* 0x000000000e127229 */
/* 0x001e0c0000000018 */
/*0cb0*/ DADD R16, R12, R18 ; /* 0x000000000c107229 */
/* 0x001e080000000012 */
/*0cc0*/ DADD R14, R14, -R18 ; /* 0x000000000e0e7229 */
/* 0x000e480000000812 */
/*0cd0*/ DADD R12, R12, -R16 ; /* 0x000000000c0c7229 */
/* 0x001e080000000810 */
/*0ce0*/ DADD R14, R24, R14 ; /* 0x00000000180e7229 */
/* 0x002fc8000000000e */
/*0cf0*/ DADD R12, R18, R12 ; /* 0x00000000120c7229 */
/* 0x001064000000000c */
/*0d00*/ IADD3 R18, R26.reuse, -0x3ff, RZ ; /* 0xfffffc011a127810 */
/* 0x041fe40007ffe0ff */
/*0d10*/ @P1 IADD3 R18, R26, -0x3fe, RZ ; /* 0xfffffc021a121810 */
/* 0x000fe40007ffe0ff */
/*0d20*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x002064000000000c */
/*0d30*/ LOP3.LUT R14, R18, 0x80000000, RZ, 0x3c, !PT ; /* 0x80000000120e7812 */
/* 0x001fe200078e3cff */
/*0d40*/ IMAD.MOV.U32 R15, RZ, RZ, 0x43300000 ; /* 0x43300000ff0f7424 */
/* 0x000fc600078e00ff */
/*0d50*/ DADD R18, R10, R12 ; /* 0x000000000a127229 */
/* 0x002e08000000000c */
/*0d60*/ DADD R12, R14, c[0x2][0x40] ; /* 0x008010000e0c7629 */
/* 0x000fc80000000000 */
/*0d70*/ DADD R14, R16, R18 ; /* 0x00000000100e7229 */
/* 0x001e0c0000000012 */
/*0d80*/ DFMA R10, R12, c[0x2][0x48], R14 ; /* 0x008012000c0a7a2b */
/* 0x001e08000000000e */
/*0d90*/ DADD R20, R16, -R14 ; /* 0x0000000010147229 */
/* 0x000e48000000080e */
/*0da0*/ DFMA R16, -R12, c[0x2][0x48], R10 ; /* 0x008012000c107a2b */
/* 0x001e08000000010a */
/*0db0*/ DADD R20, R18, R20 ; /* 0x0000000012147229 */
/* 0x002fc80000000014 */
/*0dc0*/ DADD R16, -R14, R16 ; /* 0x000000000e107229 */
/* 0x001e0c0000000110 */
/*0dd0*/ DADD R14, R20, -R16 ; /* 0x00000000140e7229 */
/* 0x001e0c0000000810 */
/*0de0*/ DFMA R14, R12, c[0x2][0x50], R14 ; /* 0x008014000c0e7a2b */
/* 0x001e0c000000000e */
/*0df0*/ DADD R12, R10, R14 ; /* 0x000000000a0c7229 */
/* 0x001e0c000000000e */
/*0e00*/ DADD R10, R10, -R12 ; /* 0x000000000a0a7229 */
/* 0x001e08000000080c */
/*0e10*/ DMUL R18, R12, 2 ; /* 0x400000000c127828 */
/* 0x000e480000000000 */
/*0e20*/ DADD R10, R14, R10 ; /* 0x000000000e0a7229 */
/* 0x0011e4000000000a */
/*0e30*/ IMAD.MOV.U32 R14, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0e7424 */
/* 0x001fe400078e00ff */
/*0e40*/ DFMA R16, R12, 2, -R18 ; /* 0x400000000c10782b */
/* 0x0020620000000812 */
/*0e50*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0f7424 */
/* 0x000fe400078e00ff */
/*0e60*/ IMAD.MOV.U32 R12, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff0c7424 */
/* 0x001fe400078e00ff */
/*0e70*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff0d7424 */
/* 0x000fe200078e00ff */
/*0e80*/ DFMA R16, R10, 2, R16 ; /* 0x400000000a10782b */
/* 0x002e0c0000000010 */
/*0e90*/ DADD R10, R18, R16 ; /* 0x00000000120a7229 */
/* 0x001e0c0000000010 */
/*0ea0*/ DFMA R14, R10, R14, 6.75539944105574400000e+15 ; /* 0x433800000a0e742b */
/* 0x001e08000000000e */
/*0eb0*/ FSETP.GEU.AND P0, PT, |R11|, 4.1917929649353027344, PT ; /* 0x4086232b0b00780b */
/* 0x000fe40003f0e200 */
/*0ec0*/ DADD R22, R14, -6.75539944105574400000e+15 ; /* 0xc33800000e167429 */
/* 0x001e0c0000000000 */
/*0ed0*/ DFMA R20, R22, c[0x2][0x58], R10 ; /* 0x0080160016147a2b */
/* 0x001e0c000000000a */
/*0ee0*/ DFMA R20, R22, c[0x2][0x60], R20 ; /* 0x0080180016147a2b */
/* 0x001e0c0000000014 */
/*0ef0*/ DFMA R12, R20, R12, c[0x2][0x68] ; /* 0x00801a00140c762b */
/* 0x001e0c000000000c */
/*0f00*/ DFMA R12, R20, R12, c[0x2][0x70] ; /* 0x00801c00140c762b */
/* 0x001e0c000000000c */
/*0f10*/ DFMA R12, R20, R12, c[0x2][0x78] ; /* 0x00801e00140c762b */
/* 0x001e0c000000000c */
/*0f20*/ DFMA R12, R20, R12, c[0x2][0x80] ; /* 0x00802000140c762b */
/* 0x001e0c000000000c */
/*0f30*/ DFMA R12, R20, R12, c[0x2][0x88] ; /* 0x00802200140c762b */
/* 0x001e0c000000000c */
/*0f40*/ DFMA R12, R20, R12, c[0x2][0x90] ; /* 0x00802400140c762b */
/* 0x001e0c000000000c */
/*0f50*/ DFMA R12, R20, R12, c[0x2][0x98] ; /* 0x00802600140c762b */
/* 0x001e0c000000000c */
/*0f60*/ DFMA R12, R20, R12, c[0x2][0xa0] ; /* 0x00802800140c762b */
/* 0x001e0c000000000c */
/*0f70*/ DFMA R12, R20, R12, c[0x2][0xa8] ; /* 0x00802a00140c762b */
/* 0x001e0c000000000c */
/*0f80*/ DFMA R12, R20, R12, 1 ; /* 0x3ff00000140c742b */
/* 0x001e0c000000000c */
/*0f90*/ DFMA R12, R20, R12, 1 ; /* 0x3ff00000140c742b */
/* 0x001e14000000000c */
/*0fa0*/ IMAD R21, R14, 0x100000, R13 ; /* 0x001000000e157824 */
/* 0x001fe400078e020d */
/*0fb0*/ IMAD.MOV.U32 R20, RZ, RZ, R12 ; /* 0x000000ffff147224 */
/* 0x000fe200078e000c */
/*0fc0*/ @!P0 BRA 0x1090 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0fd0*/ FSETP.GEU.AND P1, PT, |R11|, 4.2275390625, PT ; /* 0x408748000b00780b */
/* 0x000fe20003f2e200 */
/*0fe0*/ DADD R20, R10, +INF ; /* 0x7ff000000a147429 */
/* 0x000fc80000000000 */
/*0ff0*/ DSETP.GEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x000e0c0003f0e000 */
/*1000*/ FSEL R20, R20, RZ, P0 ; /* 0x000000ff14147208 */
/* 0x001fe40000000000 */
/*1010*/ @!P1 LEA.HI R15, R14, R14, RZ, 0x1 ; /* 0x0000000e0e0f9211 */
/* 0x000fe400078f08ff */
/*1020*/ FSEL R21, R21, RZ, P0 ; /* 0x000000ff15157208 */
/* 0x000fe40000000000 */
/*1030*/ @!P1 SHF.R.S32.HI R15, RZ, 0x1, R15 ; /* 0x00000001ff0f9819 */
/* 0x000fca000001140f */
/*1040*/ @!P1 IMAD R13, R15, 0x100000, R13 ; /* 0x001000000f0d9824 */
/* 0x000fe400078e020d */
/*1050*/ @!P1 IMAD.IADD R15, R14, 0x1, -R15 ; /* 0x000000010e0f9824 */
/* 0x000fe400078e0a0f */
/*1060*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fc600078e00ff */
/*1070*/ @!P1 LEA R15, R15, 0x3ff00000, 0x14 ; /* 0x3ff000000f0f9811 */
/* 0x000fcc00078ea0ff */
/*1080*/ @!P1 DMUL R20, R12, R14 ; /* 0x0000000e0c149228 */
/* 0x0000540000000000 */
/*1090*/ LOP3.LUT R12, R21, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff150c7812 */
/* 0x003fe200078ec0ff */
/*10a0*/ DADD R10, R18, -R10 ; /* 0x00000000120a7229 */
/* 0x000e06000000080a */
/*10b0*/ ISETP.NE.AND P0, PT, R12, 0x7ff00000, PT ; /* 0x7ff000000c00780c */
/* 0x000fc60003f05270 */
/*10c0*/ DADD R10, R16, R10 ; /* 0x00000000100a7229 */
/* 0x001e22000000000a */
/*10d0*/ ISETP.EQ.AND P0, PT, R20, RZ, !P0 ; /* 0x000000ff1400720c */
/* 0x000fda0004702270 */
/*10e0*/ @!P0 DFMA R20, R10, R20, R20 ; /* 0x000000140a14822b */
/* 0x0010640000000014 */
/*10f0*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e0002 */
/*1100*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*1110*/ RET.REL.NODEC R10 0x0 ; /* 0xffffeee00a007950 */
/* 0x002fea0003c3ffff */
/*1120*/ BRA 0x1120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>
#include<cuda_runtime.h>
namespace Neighbours
{
class FileHandle
{
public:
int InputSize(void)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
int N = 0;
while(fgets(line, 30, input) != NULL)
N++;
fclose(input);
return N;
}
void ReadFromFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
for(int i = 0; i < (*N); i++)
{
fgets(line, 30, input);
sscanf(line, "%lf %lf %lf", &x[i], &y[i], &z[i]);
b[i] = true;
}
fclose(input);
printf("Data imported from input.txt successfully!\n");
}
void WriteToFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *output = NULL;
output = fopen("output.txt", "w");
for(int i = 0; i < (*N); i++)
{
if(b[i] == true)
fprintf(output, "%.1lf %.1lf %.1lf\n", x[i], y[i], z[i]);
}
fclose(output);
printf("Data exported to output.txt successfully!\n");
}
};
__global__ void kernel(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < *d_N)
{
if((pow((*x)-d_xx[index], 2) + pow((*y)-d_yy[index], 2) + pow((*z)-d_zz[index], 2)) > pow(*r, 2))
d_bb[index] = false;
}
}
class NeighbourSearch
{
public:
void FindNeighbours(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int grid_size, block_size = 256;
grid_size = ((*d_N) + block_size) / block_size;
kernel<<<grid_size, block_size>>>(d_xx, d_yy, d_zz, d_bb, d_N, x, y, z, r);
cudaDeviceSynchronize();
}
};
} // namespace Neighbours
int main()
{
Neighbours::FileHandle fh = Neighbours::FileHandle();
double *x, *y, *z;
double *r;
double *xx, *yy, *zz;
bool *bb;
int *N;
cudaMallocManaged(&N, sizeof(int));
*N = fh.InputSize();
cudaMallocManaged(&x, sizeof(double));
cudaMallocManaged(&y, sizeof(double));
cudaMallocManaged(&z, sizeof(double));
cudaMallocManaged(&r, sizeof(double));
cudaMallocManaged(&xx, sizeof(double)*(*N));
cudaMallocManaged(&yy, sizeof(double)*(*N));
cudaMallocManaged(&zz, sizeof(double)*(*N));
cudaMallocManaged(&bb, sizeof(double)*(*N));
fh.ReadFromFile(xx, yy, zz, bb, N);
Neighbours::NeighbourSearch ns = Neighbours::NeighbourSearch();
while(1)
{
printf("Enter the x, y and z coordinates of the point and the search distance:\t");
scanf("%lf %lf %lf %lf", x, y, z, r);
if((*r) <= 0)
break;
else
{
ns.FindNeighbours(xx, yy, zz, bb, N, x, y, z, r);
fh.WriteToFile(xx, yy, zz, bb, N);
}
}
cudaFree(xx);
cudaFree(yy);
cudaFree(zz);
cudaFree(bb);
cudaFree(N);
cudaFree(x);
cudaFree(y);
cudaFree(z);
cudaFree(r);
printf("Program terminated.\n");
return 0;
} | .file "tmpxft_000f9406_00000000-6_main_v2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
.type _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_, @function
_Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_, .-_Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
.globl _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.type _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, @function
_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, .-_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "input.txt"
.LC2:
.string "%lf %lf %lf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Data imported from input.txt successfully!\n"
.align 8
.LC4:
.string "Enter the x, y and z coordinates of the point and the search distance:\t"
.section .rodata.str1.1
.LC5:
.string "%lf %lf %lf %lf"
.LC7:
.string "w"
.LC8:
.string "output.txt"
.LC9:
.string "%.1lf %.1lf %.1lf\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Data exported to output.txt successfully!\n"
.section .rodata.str1.1
.LC11:
.string "Program terminated.\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 96(%rsp), %r13
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq 128(%rsp), %r12
.L12:
movq %rbp, %rcx
movl $30, %edx
movl $30, %esi
movq %r12, %rdi
call __fgets_chk@PLT
testq %rax, %rax
je .L26
addl $1, %ebx
jmp .L12
.L26:
movq %rbp, %rdi
call fclose@PLT
movl %ebx, 0(%r13)
leaq 32(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 64(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 72(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 80(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 88(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %r15
movq 88(%rsp), %rax
movq %rax, 16(%rsp)
movq 80(%rsp), %rbp
movq 72(%rsp), %r12
movq 64(%rsp), %r13
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
cmpl $0, (%r15)
jle .L14
movl $0, %ebx
.L15:
leaq 128(%rsp), %r14
movq 8(%rsp), %rcx
movl $30, %edx
movl $30, %esi
movq %r14, %rdi
call __fgets_chk@PLT
movq %rbp, %r8
movq %r12, %rcx
movq %r13, %rdx
leaq .LC2(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rsp), %rax
movb $1, (%rax,%rbx)
addq $1, %rbx
addq $8, %r13
addq $8, %r12
addq $8, %rbp
cmpl %ebx, (%r15)
jg .L15
.L14:
movq 8(%rsp), %rdi
call fclose@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L28:
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq %rbx
.cfi_def_cfa_offset 256
pushq %r15
.cfi_def_cfa_offset 264
pushq %r14
.cfi_def_cfa_offset 272
movq %r13, %r9
movq %rbp, %r8
movq %r12, %rcx
movq 40(%rsp), %rdx
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 240
jmp .L17
.L27:
movsd (%r15,%rbx,8), %xmm0
movsd 0(%r13,%rbx,8), %xmm2
movsd (%r14,%rbx,8), %xmm1
leaq .LC9(%rip), %rdx
movl $2, %esi
movq 8(%rsp), %rdi
movl $3, %eax
call __fprintf_chk@PLT
.L19:
addq $1, %rbx
cmpl %ebx, 0(%rbp)
jle .L18
.L20:
cmpb $0, (%r12,%rbx)
je .L19
jmp .L27
.L18:
movq 8(%rsp), %rdi
call fclose@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %r8
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq 56(%rsp), %rbx
pxor %xmm0, %xmm0
comisd (%rbx), %xmm0
jnb .L16
movq 48(%rsp), %r15
movq 40(%rsp), %r14
movq 32(%rsp), %r13
movq 96(%rsp), %rbp
movq 88(%rsp), %r12
movq 80(%rsp), %rax
movq %rax, 8(%rsp)
movq 72(%rsp), %rax
movq %rax, 16(%rsp)
movq 64(%rsp), %rax
movq %rax, 24(%rsp)
movl 0(%rbp), %edx
leal 511(%rdx), %eax
addl $256, %edx
cmovns %edx, %eax
sarl $8, %eax
movl $256, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl %eax, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
call cudaDeviceSynchronize@PLT
movq 96(%rsp), %rbp
movq 88(%rsp), %r12
movq 80(%rsp), %r13
movq 72(%rsp), %r14
movq 64(%rsp), %r15
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
cmpl $0, 0(%rbp)
jle .L18
movl $0, %ebx
jmp .L20
.L16:
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<cuda.h>
#include<cuda_runtime.h>
namespace Neighbours
{
class FileHandle
{
public:
int InputSize(void)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
int N = 0;
while(fgets(line, 30, input) != NULL)
N++;
fclose(input);
return N;
}
void ReadFromFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
for(int i = 0; i < (*N); i++)
{
fgets(line, 30, input);
sscanf(line, "%lf %lf %lf", &x[i], &y[i], &z[i]);
b[i] = true;
}
fclose(input);
printf("Data imported from input.txt successfully!\n");
}
void WriteToFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *output = NULL;
output = fopen("output.txt", "w");
for(int i = 0; i < (*N); i++)
{
if(b[i] == true)
fprintf(output, "%.1lf %.1lf %.1lf\n", x[i], y[i], z[i]);
}
fclose(output);
printf("Data exported to output.txt successfully!\n");
}
};
__global__ void kernel(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < *d_N)
{
if((pow((*x)-d_xx[index], 2) + pow((*y)-d_yy[index], 2) + pow((*z)-d_zz[index], 2)) > pow(*r, 2))
d_bb[index] = false;
}
}
class NeighbourSearch
{
public:
void FindNeighbours(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int grid_size, block_size = 256;
grid_size = ((*d_N) + block_size) / block_size;
kernel<<<grid_size, block_size>>>(d_xx, d_yy, d_zz, d_bb, d_N, x, y, z, r);
cudaDeviceSynchronize();
}
};
} // namespace Neighbours
int main()
{
Neighbours::FileHandle fh = Neighbours::FileHandle();
double *x, *y, *z;
double *r;
double *xx, *yy, *zz;
bool *bb;
int *N;
cudaMallocManaged(&N, sizeof(int));
*N = fh.InputSize();
cudaMallocManaged(&x, sizeof(double));
cudaMallocManaged(&y, sizeof(double));
cudaMallocManaged(&z, sizeof(double));
cudaMallocManaged(&r, sizeof(double));
cudaMallocManaged(&xx, sizeof(double)*(*N));
cudaMallocManaged(&yy, sizeof(double)*(*N));
cudaMallocManaged(&zz, sizeof(double)*(*N));
cudaMallocManaged(&bb, sizeof(double)*(*N));
fh.ReadFromFile(xx, yy, zz, bb, N);
Neighbours::NeighbourSearch ns = Neighbours::NeighbourSearch();
while(1)
{
printf("Enter the x, y and z coordinates of the point and the search distance:\t");
scanf("%lf %lf %lf %lf", x, y, z, r);
if((*r) <= 0)
break;
else
{
ns.FindNeighbours(xx, yy, zz, bb, N, x, y, z, r);
fh.WriteToFile(xx, yy, zz, bb, N);
}
}
cudaFree(xx);
cudaFree(yy);
cudaFree(zz);
cudaFree(bb);
cudaFree(N);
cudaFree(x);
cudaFree(y);
cudaFree(z);
cudaFree(r);
printf("Program terminated.\n");
return 0;
} | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<hip/hip_runtime.h>
namespace Neighbours
{
class FileHandle
{
public:
int InputSize(void)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
int N = 0;
while(fgets(line, 30, input) != NULL)
N++;
fclose(input);
return N;
}
void ReadFromFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
for(int i = 0; i < (*N); i++)
{
fgets(line, 30, input);
sscanf(line, "%lf %lf %lf", &x[i], &y[i], &z[i]);
b[i] = true;
}
fclose(input);
printf("Data imported from input.txt successfully!\n");
}
void WriteToFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *output = NULL;
output = fopen("output.txt", "w");
for(int i = 0; i < (*N); i++)
{
if(b[i] == true)
fprintf(output, "%.1lf %.1lf %.1lf\n", x[i], y[i], z[i]);
}
fclose(output);
printf("Data exported to output.txt successfully!\n");
}
};
__global__ void kernel(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < *d_N)
{
if((pow((*x)-d_xx[index], 2) + pow((*y)-d_yy[index], 2) + pow((*z)-d_zz[index], 2)) > pow(*r, 2))
d_bb[index] = false;
}
}
class NeighbourSearch
{
public:
void FindNeighbours(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int grid_size, block_size = 256;
grid_size = ((*d_N) + block_size) / block_size;
kernel<<<grid_size, block_size>>>(d_xx, d_yy, d_zz, d_bb, d_N, x, y, z, r);
hipDeviceSynchronize();
}
};
} // namespace Neighbours
int main()
{
Neighbours::FileHandle fh = Neighbours::FileHandle();
double *x, *y, *z;
double *r;
double *xx, *yy, *zz;
bool *bb;
int *N;
hipMallocManaged(&N, sizeof(int));
*N = fh.InputSize();
hipMallocManaged(&x, sizeof(double));
hipMallocManaged(&y, sizeof(double));
hipMallocManaged(&z, sizeof(double));
hipMallocManaged(&r, sizeof(double));
hipMallocManaged(&xx, sizeof(double)*(*N));
hipMallocManaged(&yy, sizeof(double)*(*N));
hipMallocManaged(&zz, sizeof(double)*(*N));
hipMallocManaged(&bb, sizeof(double)*(*N));
fh.ReadFromFile(xx, yy, zz, bb, N);
Neighbours::NeighbourSearch ns = Neighbours::NeighbourSearch();
while(1)
{
printf("Enter the x, y and z coordinates of the point and the search distance:\t");
scanf("%lf %lf %lf %lf", x, y, z, r);
if((*r) <= 0)
break;
else
{
ns.FindNeighbours(xx, yy, zz, bb, N, x, y, z, r);
fh.WriteToFile(xx, yy, zz, bb, N);
}
}
hipFree(xx);
hipFree(yy);
hipFree(zz);
hipFree(bb);
hipFree(N);
hipFree(x);
hipFree(y);
hipFree(z);
hipFree(r);
printf("Program terminated.\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<math.h>
#include<hip/hip_runtime.h>
namespace Neighbours
{
class FileHandle
{
public:
int InputSize(void)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
int N = 0;
while(fgets(line, 30, input) != NULL)
N++;
fclose(input);
return N;
}
void ReadFromFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *input = NULL;
input = fopen("input.txt", "r");
char line[30];
for(int i = 0; i < (*N); i++)
{
fgets(line, 30, input);
sscanf(line, "%lf %lf %lf", &x[i], &y[i], &z[i]);
b[i] = true;
}
fclose(input);
printf("Data imported from input.txt successfully!\n");
}
void WriteToFile(double *x, double *y, double *z, bool *b, int *N)
{
FILE *output = NULL;
output = fopen("output.txt", "w");
for(int i = 0; i < (*N); i++)
{
if(b[i] == true)
fprintf(output, "%.1lf %.1lf %.1lf\n", x[i], y[i], z[i]);
}
fclose(output);
printf("Data exported to output.txt successfully!\n");
}
};
__global__ void kernel(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if(index < *d_N)
{
if((pow((*x)-d_xx[index], 2) + pow((*y)-d_yy[index], 2) + pow((*z)-d_zz[index], 2)) > pow(*r, 2))
d_bb[index] = false;
}
}
class NeighbourSearch
{
public:
void FindNeighbours(double *d_xx, double *d_yy, double *d_zz, bool *d_bb, int *d_N, double *x, double *y, double *z, double *r)
{
int grid_size, block_size = 256;
grid_size = ((*d_N) + block_size) / block_size;
kernel<<<grid_size, block_size>>>(d_xx, d_yy, d_zz, d_bb, d_N, x, y, z, r);
hipDeviceSynchronize();
}
};
} // namespace Neighbours
int main()
{
Neighbours::FileHandle fh = Neighbours::FileHandle();
double *x, *y, *z;
double *r;
double *xx, *yy, *zz;
bool *bb;
int *N;
hipMallocManaged(&N, sizeof(int));
*N = fh.InputSize();
hipMallocManaged(&x, sizeof(double));
hipMallocManaged(&y, sizeof(double));
hipMallocManaged(&z, sizeof(double));
hipMallocManaged(&r, sizeof(double));
hipMallocManaged(&xx, sizeof(double)*(*N));
hipMallocManaged(&yy, sizeof(double)*(*N));
hipMallocManaged(&zz, sizeof(double)*(*N));
hipMallocManaged(&bb, sizeof(double)*(*N));
fh.ReadFromFile(xx, yy, zz, bb, N);
Neighbours::NeighbourSearch ns = Neighbours::NeighbourSearch();
while(1)
{
printf("Enter the x, y and z coordinates of the point and the search distance:\t");
scanf("%lf %lf %lf %lf", x, y, z, r);
if((*r) <= 0)
break;
else
{
ns.FindNeighbours(xx, yy, zz, bb, N, x, y, z, r);
fh.WriteToFile(xx, yy, zz, bb, N);
}
}
hipFree(xx);
hipFree(yy);
hipFree(zz);
hipFree(bb);
hipFree(N);
hipFree(x);
hipFree(y);
hipFree(z);
hipFree(r);
printf("Program terminated.\n");
return 0;
} | .text
.file "main_v2.hip"
.globl _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_ # -- Begin function _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.p2align 4, 0x90
.type _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_,@function
_ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_: # @_ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_, .Lfunc_end0-_ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %rbx
movl $-1, %ebp
leaq 80(%rsp), %r14
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $30, %esi
movq %rbx, %rdx
callq fgets
incl %ebp
testq %rax, %rax
jne .LBB1_1
# %bb.2: # %_ZN10Neighbours10FileHandle9InputSizeEv.exit
movq %rbx, %rdi
callq fclose
movq (%rsp), %rax
movl %ebp, (%rax)
leaq 64(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 56(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 48(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 32(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 24(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq 40(%rsp), %rbx
movq 32(%rsp), %r14
movq 24(%rsp), %r15
movq 16(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq (%rsp), %r12
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r13
cmpl $0, (%r12)
jle .LBB1_5
# %bb.3: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 80(%rsp), %rdi
movl $30, %esi
movq %r13, %rdx
callq fgets
movl $.L.str.5, %esi
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movq %r14, %rcx
movq %r15, %r8
xorl %eax, %eax
callq __isoc23_sscanf
movq 72(%rsp), %rax # 8-byte Reload
movb $1, (%rax,%rbp)
incq %rbp
movslq (%r12), %rax
addq $8, %r15
addq $8, %r14
addq $8, %rbx
cmpq %rax, %rbp
jl .LBB1_4
.LBB1_5: # %_ZN10Neighbours10FileHandle12ReadFromFileEPdS1_S1_PbPi.exit
movq %r13, %rdi
callq fclose
movl $.Lstr.1, %edi
callq puts@PLT
movb $0, 80(%rsp)
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_12: # %_ZN10Neighbours10FileHandle11WriteToFileEPdS1_S1_PbPi.exit
# in Loop: Header=BB1_6 Depth=1
movq %r14, %rdi
callq fclose
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_6: # %_ZN10Neighbours10FileHandle12ReadFromFileEPdS1_S1_PbPi.exit
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 64(%rsp), %rsi
movq 56(%rsp), %rdx
movq 48(%rsp), %rcx
movq 8(%rsp), %r8
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq 8(%rsp), %rax
xorpd %xmm0, %xmm0
ucomisd (%rax), %xmm0
jae .LBB1_13
# %bb.7: # %.lr.ph
# in Loop: Header=BB1_6 Depth=1
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movq 24(%rsp), %rcx
movq 16(%rsp), %r8
movq (%rsp), %r9
leaq 80(%rsp), %rdi
pushq %rax
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq 40(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 32(%rsp), %r12
movq 24(%rsp), %r13
movq 16(%rsp), %rbp
movq (%rsp), %rbx
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r14
cmpl $0, (%rbx)
jle .LBB1_12
# %bb.8: # %.lr.ph.i2.preheader
# in Loop: Header=BB1_6 Depth=1
xorl %r15d, %r15d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=2
incq %r15
movslq (%rbx), %rax
cmpq %rax, %r15
jge .LBB1_12
.LBB1_9: # %.lr.ph.i2
# Parent Loop BB1_6 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rbp,%r15)
je .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=2
movq 72(%rsp), %rax # 8-byte Reload
movsd (%rax,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r12,%r15,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r13,%r15,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.9, %esi
movq %r14, %rdi
movb $3, %al
callq fprintf
jmp .LBB1_11
.LBB1_13: # %._crit_edge
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .text._ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_,"axG",@progbits,_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_,comdat
.weak _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_ # -- Begin function _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
.p2align 4, 0x90
.type _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_,@function
_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_: # @_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $208, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movl (%r9), %edi
leal 256(%rdi), %eax
addl $511, %edi # imm = 0x1FF
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movq %r13, 120(%rsp)
movq %r12, 112(%rsp)
movq %r15, 104(%rsp)
movq %r14, 96(%rsp)
movq %rbx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
addq $208, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_, .Lfunc_end2-_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_,@object # @_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.section .rodata,"a",@progbits
.globl _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.p2align 3, 0x0
_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_:
.quad _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.size _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the x, y and z coordinates of the point and the search distance:\t"
.size .L.str, 72
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf %lf %lf %lf"
.size .L.str.1, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "input.txt"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lf %lf %lf"
.size .L.str.5, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "output.txt"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "w"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%.1lf %.1lf %.1lf\n"
.size .L.str.9, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Program terminated."
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Data imported from input.txt successfully!"
.size .Lstr.1, 43
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Data exported to output.txt successfully!"
.size .Lstr.2, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f9406_00000000-6_main_v2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
.type _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_, @function
_Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_, .-_Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
.globl _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.type _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, @function
_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, .-_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "input.txt"
.LC2:
.string "%lf %lf %lf"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Data imported from input.txt successfully!\n"
.align 8
.LC4:
.string "Enter the x, y and z coordinates of the point and the search distance:\t"
.section .rodata.str1.1
.LC5:
.string "%lf %lf %lf %lf"
.LC7:
.string "w"
.LC8:
.string "output.txt"
.LC9:
.string "%.1lf %.1lf %.1lf\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "Data exported to output.txt successfully!\n"
.section .rodata.str1.1
.LC11:
.string "Program terminated.\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 96(%rsp), %r13
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq 128(%rsp), %r12
.L12:
movq %rbp, %rcx
movl $30, %edx
movl $30, %esi
movq %r12, %rdi
call __fgets_chk@PLT
testq %rax, %rax
je .L26
addl $1, %ebx
jmp .L12
.L26:
movq %rbp, %rdi
call fclose@PLT
movl %ebx, 0(%r13)
leaq 32(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 64(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 72(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 80(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %rax
movslq (%rax), %rsi
salq $3, %rsi
leaq 88(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq 96(%rsp), %r15
movq 88(%rsp), %rax
movq %rax, 16(%rsp)
movq 80(%rsp), %rbp
movq 72(%rsp), %r12
movq 64(%rsp), %r13
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
cmpl $0, (%r15)
jle .L14
movl $0, %ebx
.L15:
leaq 128(%rsp), %r14
movq 8(%rsp), %rcx
movl $30, %edx
movl $30, %esi
movq %r14, %rdi
call __fgets_chk@PLT
movq %rbp, %r8
movq %r12, %rcx
movq %r13, %rdx
leaq .LC2(%rip), %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
movq 16(%rsp), %rax
movb $1, (%rax,%rbx)
addq $1, %rbx
addq $8, %r13
addq $8, %r12
addq $8, %rbp
cmpl %ebx, (%r15)
jg .L15
.L14:
movq 8(%rsp), %rdi
call fclose@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L28:
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq %rbx
.cfi_def_cfa_offset 256
pushq %r15
.cfi_def_cfa_offset 264
pushq %r14
.cfi_def_cfa_offset 272
movq %r13, %r9
movq %rbp, %r8
movq %r12, %rcx
movq 40(%rsp), %rdx
movq 48(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z61__device_stub__ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_PdS_S_PbPiS_S_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 240
jmp .L17
.L27:
movsd (%r15,%rbx,8), %xmm0
movsd 0(%r13,%rbx,8), %xmm2
movsd (%r14,%rbx,8), %xmm1
leaq .LC9(%rip), %rdx
movl $2, %esi
movq 8(%rsp), %rdi
movl $3, %eax
call __fprintf_chk@PLT
.L19:
addq $1, %rbx
cmpl %ebx, 0(%rbp)
jle .L18
.L20:
cmpb $0, (%r12,%rbx)
je .L19
jmp .L27
.L18:
movq 8(%rsp), %rdi
call fclose@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %r8
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
leaq .LC5(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq 56(%rsp), %rbx
pxor %xmm0, %xmm0
comisd (%rbx), %xmm0
jnb .L16
movq 48(%rsp), %r15
movq 40(%rsp), %r14
movq 32(%rsp), %r13
movq 96(%rsp), %rbp
movq 88(%rsp), %r12
movq 80(%rsp), %rax
movq %rax, 8(%rsp)
movq 72(%rsp), %rax
movq %rax, 16(%rsp)
movq 64(%rsp), %rax
movq %rax, 24(%rsp)
movl 0(%rbp), %edx
leal 511(%rdx), %eax
addl $256, %edx
cmovns %edx, %eax
sarl $8, %eax
movl $256, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl %eax, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L17:
call cudaDeviceSynchronize@PLT
movq 96(%rsp), %rbp
movq 88(%rsp), %r12
movq 80(%rsp), %r13
movq 72(%rsp), %r14
movq 64(%rsp), %r15
leaq .LC7(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
cmpl $0, 0(%rbp)
jle .L18
movl $0, %ebx
jmp .L20
.L16:
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main_v2.hip"
.globl _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_ # -- Begin function _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.p2align 4, 0x90
.type _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_,@function
_ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_: # @_ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_, .Lfunc_end0-_ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x0000000000000000 # double 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %rbx
movl $-1, %ebp
leaq 80(%rsp), %r14
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $30, %esi
movq %rbx, %rdx
callq fgets
incl %ebp
testq %rax, %rax
jne .LBB1_1
# %bb.2: # %_ZN10Neighbours10FileHandle9InputSizeEv.exit
movq %rbx, %rdi
callq fclose
movq (%rsp), %rax
movl %ebp, (%rax)
leaq 64(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 56(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 48(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 40(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 32(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 24(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movslq (%rax), %rsi
shlq $3, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq 40(%rsp), %rbx
movq 32(%rsp), %r14
movq 24(%rsp), %r15
movq 16(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq (%rsp), %r12
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r13
cmpl $0, (%r12)
jle .LBB1_5
# %bb.3: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
leaq 80(%rsp), %rdi
movl $30, %esi
movq %r13, %rdx
callq fgets
movl $.L.str.5, %esi
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movq %r14, %rcx
movq %r15, %r8
xorl %eax, %eax
callq __isoc23_sscanf
movq 72(%rsp), %rax # 8-byte Reload
movb $1, (%rax,%rbp)
incq %rbp
movslq (%r12), %rax
addq $8, %r15
addq $8, %r14
addq $8, %rbx
cmpq %rax, %rbp
jl .LBB1_4
.LBB1_5: # %_ZN10Neighbours10FileHandle12ReadFromFileEPdS1_S1_PbPi.exit
movq %r13, %rdi
callq fclose
movl $.Lstr.1, %edi
callq puts@PLT
movb $0, 80(%rsp)
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_12: # %_ZN10Neighbours10FileHandle11WriteToFileEPdS1_S1_PbPi.exit
# in Loop: Header=BB1_6 Depth=1
movq %r14, %rdi
callq fclose
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_6: # %_ZN10Neighbours10FileHandle12ReadFromFileEPdS1_S1_PbPi.exit
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 64(%rsp), %rsi
movq 56(%rsp), %rdx
movq 48(%rsp), %rcx
movq 8(%rsp), %r8
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq 8(%rsp), %rax
xorpd %xmm0, %xmm0
ucomisd (%rax), %xmm0
jae .LBB1_13
# %bb.7: # %.lr.ph
# in Loop: Header=BB1_6 Depth=1
movq 40(%rsp), %rsi
movq 32(%rsp), %rdx
movq 24(%rsp), %rcx
movq 16(%rsp), %r8
movq (%rsp), %r9
leaq 80(%rsp), %rdi
pushq %rax
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq 40(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 32(%rsp), %r12
movq 24(%rsp), %r13
movq 16(%rsp), %rbp
movq (%rsp), %rbx
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r14
cmpl $0, (%rbx)
jle .LBB1_12
# %bb.8: # %.lr.ph.i2.preheader
# in Loop: Header=BB1_6 Depth=1
xorl %r15d, %r15d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=2
incq %r15
movslq (%rbx), %rax
cmpq %rax, %r15
jge .LBB1_12
.LBB1_9: # %.lr.ph.i2
# Parent Loop BB1_6 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rbp,%r15)
je .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=2
movq 72(%rsp), %rax # 8-byte Reload
movsd (%rax,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd (%r12,%r15,8), %xmm1 # xmm1 = mem[0],zero
movsd (%r13,%r15,8), %xmm2 # xmm2 = mem[0],zero
movl $.L.str.9, %esi
movq %r14, %rdi
movb $3, %al
callq fprintf
jmp .LBB1_11
.LBB1_13: # %._crit_edge
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .text._ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_,"axG",@progbits,_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_,comdat
.weak _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_ # -- Begin function _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
.p2align 4, 0x90
.type _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_,@function
_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_: # @_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $208, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movl (%r9), %edi
leal 256(%rdi), %eax
addl $511, %edi # imm = 0x1FF
testl %eax, %eax
cmovnsl %eax, %edi
sarl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 280(%rsp), %rax
movq 272(%rsp), %rcx
movq 264(%rsp), %rdx
movq 256(%rsp), %rsi
movq %r13, 120(%rsp)
movq %r12, 112(%rsp)
movq %r15, 104(%rsp)
movq %r14, 96(%rsp)
movq %rbx, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rax
movq %rax, 192(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
addq $208, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_, .Lfunc_end2-_ZN10Neighbours15NeighbourSearch14FindNeighboursEPdS1_S1_PbPiS1_S1_S1_S1_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_,@object # @_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.section .rodata,"a",@progbits
.globl _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.p2align 3, 0x0
_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_:
.quad _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.size _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the x, y and z coordinates of the point and the search distance:\t"
.size .L.str, 72
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%lf %lf %lf %lf"
.size .L.str.1, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "input.txt"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lf %lf %lf"
.size .L.str.5, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "output.txt"
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "w"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%.1lf %.1lf %.1lf\n"
.size .L.str.9, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Program terminated."
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Data imported from input.txt successfully!"
.size .Lstr.1, 43
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Data exported to output.txt successfully!"
.size .Lstr.2, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN10Neighbours21__device_stub__kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN10Neighbours6kernelEPdS0_S0_PbPiS0_S0_S0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
struct Target
{
int2 min;
int2 max;
__device__ bool contains(int2 pos) const
{
return pos.x >= min.x && pos.x <= max.x
&& pos.y >= min.y && pos.y <= max.y;
}
};
__device__ bool simulate(Target target, int2 init_vel)
{
int2 vel = init_vel;
int2 pos = make_int2(0, 0);
int max_y = 0;
while (pos.y >= target.min.y) {
pos.x += vel.x;
pos.y += vel.y;
vel.x += vel.x != 0 ? (vel.x > 0 ? -1 : 1) : 0;
vel.y -= 1;
max_y = max(pos.y, max_y);
if (target.contains(pos)) return true;
}
return false;
}
__global__ void find_max_y(Target target, int x0, int y0, int *p_max_y)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
bool hit = simulate(target, make_int2(x0 + x, y0 + y));
if (hit) {
atomicAdd(p_max_y, 1);
}
}
int main(int argc, char **argv)
{
Target target;
scanf("target area: x=%d..%d, y=%d..%d", &target.min.x, &target.max.x, &target.min.y, &target.max.y);
int mx = abs(target.min.x);
int my = abs(target.min.y);
int *p_max_y;
cudaMallocManaged(&p_max_y, sizeof(int));
*p_max_y = 0;
dim3 block_threads = { 8, 8 };
dim3 num_blocks = { (mx*4+block_threads.x-1)/block_threads.x, (my*4+block_threads.y-1)/block_threads.y };
int x0 = mx * -2, y0 = my * -2;
find_max_y<<<num_blocks, block_threads>>>(target, x0, y0, p_max_y);
int max_y = 0;
cudaMemcpy(&max_y, p_max_y, sizeof(int), cudaMemcpyDefault);
cudaFree(p_max_y);
printf("%d\n", max_y);
return 0;
} | code for sm_80
Function : _Z10find_max_y6TargetiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x1e0 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, -0x1 ; /* 0xffffffffff067424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00a0*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe400078e0205 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3 R2, R2, c[0x0][0x174], RZ ; /* 0x00005d0002027a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.IADD R5, R5, 0x1, R0 ; /* 0x0000000105057824 */
/* 0x000fe200078e0200 */
/*0110*/ ISETP.GT.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f24270 */
/*0120*/ IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103037824 */
/* 0x000fe200078e0202 */
/*0130*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*0140*/ ISETP.GT.AND P0, PT, R5.reuse, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x040fe40003f04270 */
/*0150*/ SEL R4, R6, 0x1, P1 ; /* 0x0000000106047807 */
/* 0x000fe40000800000 */
/*0160*/ ISETP.LT.OR P0, PT, R5, c[0x0][0x160], P0 ; /* 0x0000580005007a0c */
/* 0x000fe40000701670 */
/*0170*/ SEL R7, R4, RZ, P2 ; /* 0x000000ff04077207 */
/* 0x000fc40001000000 */
/*0180*/ ISETP.LT.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fe40000701670 */
/*0190*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.IADD R0, R7, 0x1, R0 ; /* 0x0000000107007824 */
/* 0x000fe200078e0200 */
/*01b0*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x16c], P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0000704670 */
/*01c0*/ @P0 BRA 0xe0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*01f0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0210*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0220*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fc800078e00ff */
/*0240*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0250*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
struct Target
{
int2 min;
int2 max;
__device__ bool contains(int2 pos) const
{
return pos.x >= min.x && pos.x <= max.x
&& pos.y >= min.y && pos.y <= max.y;
}
};
__device__ bool simulate(Target target, int2 init_vel)
{
int2 vel = init_vel;
int2 pos = make_int2(0, 0);
int max_y = 0;
while (pos.y >= target.min.y) {
pos.x += vel.x;
pos.y += vel.y;
vel.x += vel.x != 0 ? (vel.x > 0 ? -1 : 1) : 0;
vel.y -= 1;
max_y = max(pos.y, max_y);
if (target.contains(pos)) return true;
}
return false;
}
__global__ void find_max_y(Target target, int x0, int y0, int *p_max_y)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
bool hit = simulate(target, make_int2(x0 + x, y0 + y));
if (hit) {
atomicAdd(p_max_y, 1);
}
}
int main(int argc, char **argv)
{
Target target;
scanf("target area: x=%d..%d, y=%d..%d", &target.min.x, &target.max.x, &target.min.y, &target.max.y);
int mx = abs(target.min.x);
int my = abs(target.min.y);
int *p_max_y;
cudaMallocManaged(&p_max_y, sizeof(int));
*p_max_y = 0;
dim3 block_threads = { 8, 8 };
dim3 num_blocks = { (mx*4+block_threads.x-1)/block_threads.x, (my*4+block_threads.y-1)/block_threads.y };
int x0 = mx * -2, y0 = my * -2;
find_max_y<<<num_blocks, block_threads>>>(target, x0, y0, p_max_y);
int max_y = 0;
cudaMemcpy(&max_y, p_max_y, sizeof(int), cudaMemcpyDefault);
cudaFree(p_max_y);
printf("%d\n", max_y);
return 0;
} | .file "tmpxft_0008196d_00000000-6_part2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8simulate6Target4int2
.type _Z8simulate6Target4int2, @function
_Z8simulate6Target4int2:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8simulate6Target4int2, .-_Z8simulate6Target4int2
.globl _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
.type _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi, @function
_Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10find_max_y6TargetiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi, .-_Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
.globl _Z10find_max_y6TargetiiPi
.type _Z10find_max_y6TargetiiPi, @function
_Z10find_max_y6TargetiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl %edx, %esi
movl %ecx, %edx
movq %r8, %rcx
movq %rsp, %rdi
call _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10find_max_y6TargetiiPi, .-_Z10find_max_y6TargetiiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "target area: x=%d..%d, y=%d..%d"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rsi
leaq 36(%rsp), %rcx
leaq 40(%rsp), %rdx
leaq 44(%rsp), %r8
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 32(%rsp), %eax
movl %eax, %ebx
negl %ebx
cmovs %eax, %ebx
movl 36(%rsp), %eax
movl %eax, %ebp
negl %ebp
cmovs %eax, %ebp
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rax
movl $0, (%rax)
leal 7(,%rbx,4), %eax
shrl $3, %eax
movl %eax, 20(%rsp)
leal 7(,%rbp,4), %eax
shrl $3, %eax
movl %eax, 24(%rsp)
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
movl $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $4, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl 48(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 48(%rsp)
imull $-2, %ebp, %edx
imull $-2, %ebx, %esi
leaq 48(%rsp), %rdi
movq (%rsp), %rcx
call _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10find_max_y6TargetiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10find_max_y6TargetiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
struct Target
{
int2 min;
int2 max;
__device__ bool contains(int2 pos) const
{
return pos.x >= min.x && pos.x <= max.x
&& pos.y >= min.y && pos.y <= max.y;
}
};
__device__ bool simulate(Target target, int2 init_vel)
{
int2 vel = init_vel;
int2 pos = make_int2(0, 0);
int max_y = 0;
while (pos.y >= target.min.y) {
pos.x += vel.x;
pos.y += vel.y;
vel.x += vel.x != 0 ? (vel.x > 0 ? -1 : 1) : 0;
vel.y -= 1;
max_y = max(pos.y, max_y);
if (target.contains(pos)) return true;
}
return false;
}
__global__ void find_max_y(Target target, int x0, int y0, int *p_max_y)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
bool hit = simulate(target, make_int2(x0 + x, y0 + y));
if (hit) {
atomicAdd(p_max_y, 1);
}
}
int main(int argc, char **argv)
{
Target target;
scanf("target area: x=%d..%d, y=%d..%d", &target.min.x, &target.max.x, &target.min.y, &target.max.y);
int mx = abs(target.min.x);
int my = abs(target.min.y);
int *p_max_y;
cudaMallocManaged(&p_max_y, sizeof(int));
*p_max_y = 0;
dim3 block_threads = { 8, 8 };
dim3 num_blocks = { (mx*4+block_threads.x-1)/block_threads.x, (my*4+block_threads.y-1)/block_threads.y };
int x0 = mx * -2, y0 = my * -2;
find_max_y<<<num_blocks, block_threads>>>(target, x0, y0, p_max_y);
int max_y = 0;
cudaMemcpy(&max_y, p_max_y, sizeof(int), cudaMemcpyDefault);
cudaFree(p_max_y);
printf("%d\n", max_y);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
struct Target
{
int2 min;
int2 max;
__device__ bool contains(int2 pos) const
{
return pos.x >= min.x && pos.x <= max.x
&& pos.y >= min.y && pos.y <= max.y;
}
};
__device__ bool simulate(Target target, int2 init_vel)
{
int2 vel = init_vel;
int2 pos = make_int2(0, 0);
int max_y = 0;
while (pos.y >= target.min.y) {
pos.x += vel.x;
pos.y += vel.y;
vel.x += vel.x != 0 ? (vel.x > 0 ? -1 : 1) : 0;
vel.y -= 1;
max_y = max(pos.y, max_y);
if (target.contains(pos)) return true;
}
return false;
}
__global__ void find_max_y(Target target, int x0, int y0, int *p_max_y)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
bool hit = simulate(target, make_int2(x0 + x, y0 + y));
if (hit) {
atomicAdd(p_max_y, 1);
}
}
int main(int argc, char **argv)
{
Target target;
scanf("target area: x=%d..%d, y=%d..%d", &target.min.x, &target.max.x, &target.min.y, &target.max.y);
int mx = abs(target.min.x);
int my = abs(target.min.y);
int *p_max_y;
hipMallocManaged(&p_max_y, sizeof(int));
*p_max_y = 0;
dim3 block_threads = { 8, 8 };
dim3 num_blocks = { (mx*4+block_threads.x-1)/block_threads.x, (my*4+block_threads.y-1)/block_threads.y };
int x0 = mx * -2, y0 = my * -2;
find_max_y<<<num_blocks, block_threads>>>(target, x0, y0, p_max_y);
int max_y = 0;
hipMemcpy(&max_y, p_max_y, sizeof(int), hipMemcpyDefault);
hipFree(p_max_y);
printf("%d\n", max_y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
struct Target
{
int2 min;
int2 max;
__device__ bool contains(int2 pos) const
{
return pos.x >= min.x && pos.x <= max.x
&& pos.y >= min.y && pos.y <= max.y;
}
};
__device__ bool simulate(Target target, int2 init_vel)
{
int2 vel = init_vel;
int2 pos = make_int2(0, 0);
int max_y = 0;
while (pos.y >= target.min.y) {
pos.x += vel.x;
pos.y += vel.y;
vel.x += vel.x != 0 ? (vel.x > 0 ? -1 : 1) : 0;
vel.y -= 1;
max_y = max(pos.y, max_y);
if (target.contains(pos)) return true;
}
return false;
}
__global__ void find_max_y(Target target, int x0, int y0, int *p_max_y)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
bool hit = simulate(target, make_int2(x0 + x, y0 + y));
if (hit) {
atomicAdd(p_max_y, 1);
}
}
int main(int argc, char **argv)
{
Target target;
scanf("target area: x=%d..%d, y=%d..%d", &target.min.x, &target.max.x, &target.min.y, &target.max.y);
int mx = abs(target.min.x);
int my = abs(target.min.y);
int *p_max_y;
hipMallocManaged(&p_max_y, sizeof(int));
*p_max_y = 0;
dim3 block_threads = { 8, 8 };
dim3 num_blocks = { (mx*4+block_threads.x-1)/block_threads.x, (my*4+block_threads.y-1)/block_threads.y };
int x0 = mx * -2, y0 = my * -2;
find_max_y<<<num_blocks, block_threads>>>(target, x0, y0, p_max_y);
int max_y = 0;
hipMemcpy(&max_y, p_max_y, sizeof(int), hipMemcpyDefault);
hipFree(p_max_y);
printf("%d\n", max_y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10find_max_y6TargetiiPi
.globl _Z10find_max_y6TargetiiPi
.p2align 8
.type _Z10find_max_y6TargetiiPi,@function
_Z10find_max_y6TargetiiPi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_add3_u32 v0, s14, s2, v2
v_add3_u32 v2, s15, s3, v3
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s14
s_or_b32 s6, s2, s6
s_and_not1_b32 s2, s13, exec_lo
s_and_b32 s3, s12, exec_lo
s_and_not1_b32 s4, s7, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 s13, s2, s3
s_or_b32 s7, s4, s5
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_4
.LBB0_2:
v_cmp_gt_i32_e32 vcc_lo, s9, v1
s_or_b32 s12, s12, exec_lo
s_or_b32 s14, s14, exec_lo
s_mov_b32 s15, exec_lo
v_cmpx_le_i32_e64 s9, v1
s_cbranch_execz .LBB0_1
v_cmp_gt_i32_e64 s2, 1, v0
v_add_nc_u32_e32 v3, v3, v0
v_add_nc_u32_e32 v1, v2, v1
v_cmp_ne_u32_e64 s4, 0, v0
v_add_nc_u32_e32 v2, -1, v2
v_cndmask_b32_e64 v4, -1, 1, s2
v_cmp_le_i32_e64 s2, s8, v3
v_cmp_le_i32_e64 s3, s9, v1
v_cmp_ge_i32_e64 s5, s11, v1
s_and_not1_b32 s12, s12, exec_lo
v_cndmask_b32_e64 v4, 0, v4, s4
v_cmp_ge_i32_e64 s4, s10, v3
s_and_b32 s2, s2, s3
s_and_not1_b32 s3, s14, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v4, v0
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s5
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s3, s2
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
s_xor_b32 s3, s13, -1
s_xor_b32 s2, s7, -1
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_8
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x18
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10find_max_y6TargetiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10find_max_y6TargetiiPi, .Lfunc_end0-_Z10find_max_y6TargetiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10find_max_y6TargetiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10find_max_y6TargetiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
struct Target
{
int2 min;
int2 max;
__device__ bool contains(int2 pos) const
{
return pos.x >= min.x && pos.x <= max.x
&& pos.y >= min.y && pos.y <= max.y;
}
};
__device__ bool simulate(Target target, int2 init_vel)
{
int2 vel = init_vel;
int2 pos = make_int2(0, 0);
int max_y = 0;
while (pos.y >= target.min.y) {
pos.x += vel.x;
pos.y += vel.y;
vel.x += vel.x != 0 ? (vel.x > 0 ? -1 : 1) : 0;
vel.y -= 1;
max_y = max(pos.y, max_y);
if (target.contains(pos)) return true;
}
return false;
}
__global__ void find_max_y(Target target, int x0, int y0, int *p_max_y)
{
int x = blockDim.x*blockIdx.x + threadIdx.x;
int y = blockDim.y*blockIdx.y + threadIdx.y;
bool hit = simulate(target, make_int2(x0 + x, y0 + y));
if (hit) {
atomicAdd(p_max_y, 1);
}
}
int main(int argc, char **argv)
{
Target target;
scanf("target area: x=%d..%d, y=%d..%d", &target.min.x, &target.max.x, &target.min.y, &target.max.y);
int mx = abs(target.min.x);
int my = abs(target.min.y);
int *p_max_y;
hipMallocManaged(&p_max_y, sizeof(int));
*p_max_y = 0;
dim3 block_threads = { 8, 8 };
dim3 num_blocks = { (mx*4+block_threads.x-1)/block_threads.x, (my*4+block_threads.y-1)/block_threads.y };
int x0 = mx * -2, y0 = my * -2;
find_max_y<<<num_blocks, block_threads>>>(target, x0, y0, p_max_y);
int max_y = 0;
hipMemcpy(&max_y, p_max_y, sizeof(int), hipMemcpyDefault);
hipFree(p_max_y);
printf("%d\n", max_y);
return 0;
} | .text
.file "part2.hip"
.globl _Z25__device_stub__find_max_y6TargetiiPi # -- Begin function _Z25__device_stub__find_max_y6TargetiiPi
.p2align 4, 0x90
.type _Z25__device_stub__find_max_y6TargetiiPi,@function
_Z25__device_stub__find_max_y6TargetiiPi: # @_Z25__device_stub__find_max_y6TargetiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10find_max_y6TargetiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__find_max_y6TargetiiPi, .Lfunc_end0-_Z25__device_stub__find_max_y6TargetiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdx
leaq 20(%rsp), %rcx
leaq 28(%rsp), %r8
leaq 16(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %eax
movl 20(%rsp), %ecx
movl %eax, %ebx
negl %ebx
cmovsl %eax, %ebx
movl %ecx, %r14d
negl %r14d
cmovsl %ecx, %r14d
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movl $0, (%rax)
leal 7(,%rbx,4), %eax
shrl $3, %eax
leal 7(,%r14,4), %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
addl %r14d, %r14d
negl %r14d
addl %ebx, %ebx
negl %ebx
movups 16(%rsp), %xmm0
movq (%rsp), %rax
movups %xmm0, 120(%rsp)
movl %ebx, 12(%rsp)
movl %r14d, 8(%rsp)
movq %rax, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 12(%rsp), %rax
movq %rax, 40(%rsp)
leaq 8(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 56(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10find_max_y6TargetiiPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $0, 32(%rsp)
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $4, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movl 32(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10find_max_y6TargetiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10find_max_y6TargetiiPi,@object # @_Z10find_max_y6TargetiiPi
.section .rodata,"a",@progbits
.globl _Z10find_max_y6TargetiiPi
.p2align 3, 0x0
_Z10find_max_y6TargetiiPi:
.quad _Z25__device_stub__find_max_y6TargetiiPi
.size _Z10find_max_y6TargetiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "target area: x=%d..%d, y=%d..%d"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10find_max_y6TargetiiPi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__find_max_y6TargetiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10find_max_y6TargetiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10find_max_y6TargetiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ BSSY B0, 0x1e0 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, -0x1 ; /* 0xffffffffff067424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00a0*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fe400078e0205 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3 R2, R2, c[0x0][0x174], RZ ; /* 0x00005d0002027a10 */
/* 0x000fe40007ffe0ff */
/*00e0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.IADD R5, R5, 0x1, R0 ; /* 0x0000000105057824 */
/* 0x000fe200078e0200 */
/*0110*/ ISETP.GT.AND P1, PT, R0.reuse, RZ, PT ; /* 0x000000ff0000720c */
/* 0x040fe20003f24270 */
/*0120*/ IMAD.IADD R3, R3, 0x1, R2 ; /* 0x0000000103037824 */
/* 0x000fe200078e0202 */
/*0130*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*0140*/ ISETP.GT.AND P0, PT, R5.reuse, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x040fe40003f04270 */
/*0150*/ SEL R4, R6, 0x1, P1 ; /* 0x0000000106047807 */
/* 0x000fe40000800000 */
/*0160*/ ISETP.LT.OR P0, PT, R5, c[0x0][0x160], P0 ; /* 0x0000580005007a0c */
/* 0x000fe40000701670 */
/*0170*/ SEL R7, R4, RZ, P2 ; /* 0x000000ff04077207 */
/* 0x000fc40001000000 */
/*0180*/ ISETP.LT.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fe40000701670 */
/*0190*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.IADD R0, R7, 0x1, R0 ; /* 0x0000000107007824 */
/* 0x000fe200078e0200 */
/*01b0*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x16c], P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0000704670 */
/*01c0*/ @P0 BRA 0xe0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*01f0*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0210*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0220*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fc800078e00ff */
/*0240*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0250*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10find_max_y6TargetiiPi
.globl _Z10find_max_y6TargetiiPi
.p2align 8
.type _Z10find_max_y6TargetiiPi,@function
_Z10find_max_y6TargetiiPi:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b128 s[8:11], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_mul_i32 s14, s14, s5
s_mul_i32 s15, s15, s4
v_add3_u32 v0, s14, s2, v2
v_add3_u32 v2, s15, s3, v3
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s14
s_or_b32 s6, s2, s6
s_and_not1_b32 s2, s13, exec_lo
s_and_b32 s3, s12, exec_lo
s_and_not1_b32 s4, s7, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_or_b32 s13, s2, s3
s_or_b32 s7, s4, s5
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_4
.LBB0_2:
v_cmp_gt_i32_e32 vcc_lo, s9, v1
s_or_b32 s12, s12, exec_lo
s_or_b32 s14, s14, exec_lo
s_mov_b32 s15, exec_lo
v_cmpx_le_i32_e64 s9, v1
s_cbranch_execz .LBB0_1
v_cmp_gt_i32_e64 s2, 1, v0
v_add_nc_u32_e32 v3, v3, v0
v_add_nc_u32_e32 v1, v2, v1
v_cmp_ne_u32_e64 s4, 0, v0
v_add_nc_u32_e32 v2, -1, v2
v_cndmask_b32_e64 v4, -1, 1, s2
v_cmp_le_i32_e64 s2, s8, v3
v_cmp_le_i32_e64 s3, s9, v1
v_cmp_ge_i32_e64 s5, s11, v1
s_and_not1_b32 s12, s12, exec_lo
v_cndmask_b32_e64 v4, 0, v4, s4
v_cmp_ge_i32_e64 s4, s10, v3
s_and_b32 s2, s2, s3
s_and_not1_b32 s3, s14, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v4, v0
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s5
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s3, s2
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
s_xor_b32 s3, s13, -1
s_xor_b32 s2, s7, -1
s_and_saveexec_b32 s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_8
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x18
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10find_max_y6TargetiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10find_max_y6TargetiiPi, .Lfunc_end0-_Z10find_max_y6TargetiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10find_max_y6TargetiiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10find_max_y6TargetiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008196d_00000000-6_part2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8simulate6Target4int2
.type _Z8simulate6Target4int2, @function
_Z8simulate6Target4int2:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8simulate6Target4int2, .-_Z8simulate6Target4int2
.globl _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
.type _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi, @function
_Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10find_max_y6TargetiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi, .-_Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
.globl _Z10find_max_y6TargetiiPi
.type _Z10find_max_y6TargetiiPi, @function
_Z10find_max_y6TargetiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl %edx, %esi
movl %ecx, %edx
movq %r8, %rcx
movq %rsp, %rdi
call _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10find_max_y6TargetiiPi, .-_Z10find_max_y6TargetiiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "target area: x=%d..%d, y=%d..%d"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rsi
leaq 36(%rsp), %rcx
leaq 40(%rsp), %rdx
leaq 44(%rsp), %r8
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
movl 32(%rsp), %eax
movl %eax, %ebx
negl %ebx
cmovs %eax, %ebx
movl 36(%rsp), %eax
movl %eax, %ebp
negl %ebp
cmovs %eax, %ebp
movq %rsp, %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq (%rsp), %rax
movl $0, (%rax)
leal 7(,%rbx,4), %eax
shrl $3, %eax
movl %eax, 20(%rsp)
leal 7(,%rbp,4), %eax
shrl $3, %eax
movl %eax, 24(%rsp)
movl $8, 8(%rsp)
movl $8, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
movl $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $4, %ecx
movl $4, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl 48(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movdqa 32(%rsp), %xmm0
movaps %xmm0, 48(%rsp)
imull $-2, %ebp, %edx
imull $-2, %ebx, %esi
leaq 48(%rsp), %rdi
movq (%rsp), %rcx
call _Z39__device_stub__Z10find_max_y6TargetiiPiR6TargetiiPi
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10find_max_y6TargetiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10find_max_y6TargetiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "part2.hip"
.globl _Z25__device_stub__find_max_y6TargetiiPi # -- Begin function _Z25__device_stub__find_max_y6TargetiiPi
.p2align 4, 0x90
.type _Z25__device_stub__find_max_y6TargetiiPi,@function
_Z25__device_stub__find_max_y6TargetiiPi: # @_Z25__device_stub__find_max_y6TargetiiPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10find_max_y6TargetiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__find_max_y6TargetiiPi, .Lfunc_end0-_Z25__device_stub__find_max_y6TargetiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdx
leaq 20(%rsp), %rcx
leaq 28(%rsp), %r8
leaq 16(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 16(%rsp), %eax
movl 20(%rsp), %ecx
movl %eax, %ebx
negl %ebx
cmovsl %eax, %ebx
movl %ecx, %r14d
negl %r14d
cmovsl %ecx, %r14d
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
movl $0, (%rax)
leal 7(,%rbx,4), %eax
shrl $3, %eax
leal 7(,%r14,4), %edi
shrl $3, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738376, %rdx # imm = 0x800000008
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
addl %r14d, %r14d
negl %r14d
addl %ebx, %ebx
negl %ebx
movups 16(%rsp), %xmm0
movq (%rsp), %rax
movups %xmm0, 120(%rsp)
movl %ebx, 12(%rsp)
movl %r14d, 8(%rsp)
movq %rax, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 12(%rsp), %rax
movq %rax, 40(%rsp)
leaq 8(%rsp), %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 56(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z10find_max_y6TargetiiPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $0, 32(%rsp)
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $4, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
movl 32(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10find_max_y6TargetiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10find_max_y6TargetiiPi,@object # @_Z10find_max_y6TargetiiPi
.section .rodata,"a",@progbits
.globl _Z10find_max_y6TargetiiPi
.p2align 3, 0x0
_Z10find_max_y6TargetiiPi:
.quad _Z25__device_stub__find_max_y6TargetiiPi
.size _Z10find_max_y6TargetiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "target area: x=%d..%d, y=%d..%d"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10find_max_y6TargetiiPi"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__find_max_y6TargetiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10find_max_y6TargetiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
float cuda_sum(const std::vector<float>& data) {
thrust::device_vector<float> d_data = data;
return thrust::reduce(d_data.cbegin(), d_data.cend(), 0);
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
float cuda_sum(const std::vector<float>& data) {
thrust::device_vector<float> d_data = data;
return thrust::reduce(d_data.cbegin(), d_data.cend(), 0);
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void CumulatePositionOfNewObjects(float* mask , float* maskNewIds , float* maskOut, int mask_size, int mask_cols, float* centers, int centers_size, int centers_columns){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % mask_cols;
int irow = idx / mask_cols;
int i_mask, i_obj;
if (idx<mask_size){
i_mask = mask[idx];
i_obj = maskNewIds[i_mask];
maskOut[idx] = i_obj;
if (i_obj*centers_columns+2<centers_size){
atomicAdd(centers + 0 + i_obj*centers_columns , (float)icol);
atomicAdd(centers + 1 + i_obj*centers_columns , (float)irow);
atomicAdd(centers + 2 + i_obj*centers_columns , 1.0f);
}
}
} | code for sm_80
Function : _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R3, R3, c[0x0][0xc], R0 ; /* 0x0000030003037a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R6, R3, R0, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fcc00078e0200 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ F2I.TRUNC.NTZ R9, R6 ; /* 0x0000000600097305 */
/* 0x004e24000020f100 */
/*00d0*/ IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x001fcc00078e0200 */
/*00e0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R10, R3, R0, c[0x0][0x170] ; /* 0x00005c00030a7625 */
/* 0x000fe200078e0200 */
/*0100*/ F2I.TRUNC.NTZ R2, R8 ; /* 0x0000000800027305 */
/* 0x004e26000020f100 */
/*0110*/ IMAD R5, R2, c[0x0][0x18c], RZ ; /* 0x0000630002057a24 */
/* 0x001fca00078e02ff */
/*0120*/ I2F R13, R2 ; /* 0x00000002000d7306 */
/* 0x000e220000201400 */
/*0130*/ IADD3 R4, R5, 0x2, RZ ; /* 0x0000000205047810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x188], PT ; /* 0x0000620004007a0c */
/* 0x000fe20003f06270 */
/*0150*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0011d8000c101904 */
/*0160*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0170*/ IABS R9, c[0x0][0x17c] ; /* 0x00005f0000097a13 */
/* 0x000fc80000000000 */
/*0180*/ I2F.RP R2, R9 ; /* 0x0000000900027306 */
/* 0x000e700000209400 */
/*0190*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x002e640000001000 */
/*01a0*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x002fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002a4000021f000 */
/*01c0*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x002fe20000000f00 */
/*01d0*/ IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff047224 */
/* 0x004fc800078e0a07 */
/*01e0*/ IMAD R11, R4, R9, RZ ; /* 0x00000009040b7224 */
/* 0x001fe200078e02ff */
/*01f0*/ IABS R4, R3 ; /* 0x0000000300047213 */
/* 0x000fc60000000000 */
/*0200*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fcc00078e0006 */
/*0210*/ IMAD.HI.U32 R7, R7, R4, RZ ; /* 0x0000000407077227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R2, RZ, RZ, -R7 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a07 */
/*0230*/ IMAD R2, R9, R2, R4 ; /* 0x0000000209027224 */
/* 0x000fca00078e0204 */
/*0240*/ ISETP.GT.U32.AND P2, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f44070 */
/*0250*/ @!P2 IADD3 R2, R2, -R9.reuse, RZ ; /* 0x800000090202a210 */
/* 0x080fe40007ffe0ff */
/*0260*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*0280*/ LOP3.LUT R2, R3, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0003027a12 */
/* 0x000fe400078e3cff */
/*0290*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*02a0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*02b0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fcc0007ffe0ff */
/*02c0*/ @!P1 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff079224 */
/* 0x000fe200078e0a07 */
/*02d0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff07aa12 */
/* 0x000fc800078e33ff */
/*02e0*/ IADD3 R4, -R7, RZ, RZ ; /* 0x000000ff07047210 */
/* 0x000fe40007ffe1ff */
/*02f0*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000fe60000201400 */
/*0300*/ IMAD R4, R4, c[0x0][0x17c], R3 ; /* 0x00005f0004047a24 */
/* 0x000fe400078e0203 */
/*0310*/ IMAD.WIDE R2, R5, R0, c[0x0][0x180] ; /* 0x0000600005027625 */
/* 0x000fc600078e0200 */
/*0320*/ I2F R9, R4 ; /* 0x0000000400097306 */
/* 0x000e220000201400 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x000fe200078e00ff */
/*0340*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x001fe8000c10e784 */
/*0350*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64+0x4], R7 ; /* 0x000004070200798e */
/* 0x000fe8000c10e784 */
/*0360*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64+0x8], R5 ; /* 0x000008050200798e */
/* 0x000fe2000c10e784 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void CumulatePositionOfNewObjects(float* mask , float* maskNewIds , float* maskOut, int mask_size, int mask_cols, float* centers, int centers_size, int centers_columns){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % mask_cols;
int irow = idx / mask_cols;
int i_mask, i_obj;
if (idx<mask_size){
i_mask = mask[idx];
i_obj = maskNewIds[i_mask];
maskOut[idx] = i_obj;
if (i_obj*centers_columns+2<centers_size){
atomicAdd(centers + 0 + i_obj*centers_columns , (float)icol);
atomicAdd(centers + 1 + i_obj*centers_columns , (float)irow);
atomicAdd(centers + 2 + i_obj*centers_columns , 1.0f);
}
}
} | .file "tmpxft_0014bea5_00000000-6_CumulatePositionOfNewObjects.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii
.type _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii, @function
_Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii, .-_Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii
.globl _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.type _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, @function
_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, .-_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void CumulatePositionOfNewObjects(float* mask , float* maskNewIds , float* maskOut, int mask_size, int mask_cols, float* centers, int centers_size, int centers_columns){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % mask_cols;
int irow = idx / mask_cols;
int i_mask, i_obj;
if (idx<mask_size){
i_mask = mask[idx];
i_obj = maskNewIds[i_mask];
maskOut[idx] = i_obj;
if (i_obj*centers_columns+2<centers_size){
atomicAdd(centers + 0 + i_obj*centers_columns , (float)icol);
atomicAdd(centers + 1 + i_obj*centers_columns , (float)irow);
atomicAdd(centers + 2 + i_obj*centers_columns , 1.0f);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CumulatePositionOfNewObjects(float* mask , float* maskNewIds , float* maskOut, int mask_size, int mask_cols, float* centers, int centers_size, int centers_columns){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % mask_cols;
int irow = idx / mask_cols;
int i_mask, i_obj;
if (idx<mask_size){
i_mask = mask[idx];
i_obj = maskNewIds[i_mask];
maskOut[idx] = i_obj;
if (i_obj*centers_columns+2<centers_size){
atomicAdd(centers + 0 + i_obj*centers_columns , (float)icol);
atomicAdd(centers + 1 + i_obj*centers_columns , (float)irow);
atomicAdd(centers + 2 + i_obj*centers_columns , 1.0f);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CumulatePositionOfNewObjects(float* mask , float* maskNewIds , float* maskOut, int mask_size, int mask_cols, float* centers, int centers_size, int centers_columns){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % mask_cols;
int irow = idx / mask_cols;
int i_mask, i_obj;
if (idx<mask_size){
i_mask = mask[idx];
i_obj = maskNewIds[i_mask];
maskOut[idx] = i_obj;
if (i_obj*centers_columns+2<centers_size){
atomicAdd(centers + 0 + i_obj*centers_columns , (float)icol);
atomicAdd(centers + 1 + i_obj*centers_columns , (float)irow);
atomicAdd(centers + 2 + i_obj*centers_columns , 1.0f);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.globl _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.p2align 8
.type _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii,@function
_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
s_load_b64 s[4:5], s[0:1], 0x28
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v0, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s5
v_cvt_f32_i32_e32 v1, v1
global_store_b32 v[3:4], v1, off
v_add_nc_u32_e32 v5, 2, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v1, 31, v0
s_load_b32 s0, s[0:1], 0x1c
v_ashrrev_i32_e32 v9, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v8, v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v8, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_ashr_i32 s1, s0, 31
s_add_i32 s4, s0, s1
global_load_b32 v6, v[3:4], off
s_xor_b32 s4, s4, s1
v_xor_b32_e32 v9, s1, v9
v_cvt_f32_u32_e32 v5, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, s5, v5
v_mul_hi_u32 v7, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v7
v_mad_u64_u32 v[7:8], null, v10, v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v8, s4
v_add_nc_u32_e32 v7, 1, v8
v_sub_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v10, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v7, v8, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v10 :: v_dual_add_nc_u32 v8, 1, v7
v_cmp_le_u32_e32 vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v7, v8, vcc_lo
v_xor_b32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v5, v9
v_mul_lo_u32 v5, v7, s0
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_cvt_f32_i32_e32 v2, v2
.LBB0_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v6, v2
global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_cvt_f32_i32_e32 v6, v7
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v5, v[2:3], off offset:4
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_5:
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v6
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[0:1], off offset:8
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v3
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, .Lfunc_end0-_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CumulatePositionOfNewObjects(float* mask , float* maskNewIds , float* maskOut, int mask_size, int mask_cols, float* centers, int centers_size, int centers_columns){
int idx = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
int icol = idx % mask_cols;
int irow = idx / mask_cols;
int i_mask, i_obj;
if (idx<mask_size){
i_mask = mask[idx];
i_obj = maskNewIds[i_mask];
maskOut[idx] = i_obj;
if (i_obj*centers_columns+2<centers_size){
atomicAdd(centers + 0 + i_obj*centers_columns , (float)icol);
atomicAdd(centers + 1 + i_obj*centers_columns , (float)irow);
atomicAdd(centers + 2 + i_obj*centers_columns , 1.0f);
}
}
} | .text
.file "CumulatePositionOfNewObjects.hip"
.globl _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii # -- Begin function _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.p2align 4, 0x90
.type _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii,@function
_Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii: # @_Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii, .Lfunc_end0-_Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii,@object # @_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.section .rodata,"a",@progbits
.globl _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.p2align 3, 0x0
_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii:
.quad _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.size _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R3, R3, c[0x0][0xc], R0 ; /* 0x0000030003037a24 */
/* 0x001fc800078e0200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R6, R3, R0, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fcc00078e0200 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ F2I.TRUNC.NTZ R9, R6 ; /* 0x0000000600097305 */
/* 0x004e24000020f100 */
/*00d0*/ IMAD.WIDE R8, R9, R0, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x001fcc00078e0200 */
/*00e0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.WIDE R10, R3, R0, c[0x0][0x170] ; /* 0x00005c00030a7625 */
/* 0x000fe200078e0200 */
/*0100*/ F2I.TRUNC.NTZ R2, R8 ; /* 0x0000000800027305 */
/* 0x004e26000020f100 */
/*0110*/ IMAD R5, R2, c[0x0][0x18c], RZ ; /* 0x0000630002057a24 */
/* 0x001fca00078e02ff */
/*0120*/ I2F R13, R2 ; /* 0x00000002000d7306 */
/* 0x000e220000201400 */
/*0130*/ IADD3 R4, R5, 0x2, RZ ; /* 0x0000000205047810 */
/* 0x000fc80007ffe0ff */
/*0140*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x188], PT ; /* 0x0000620004007a0c */
/* 0x000fe20003f06270 */
/*0150*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x0011d8000c101904 */
/*0160*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0170*/ IABS R9, c[0x0][0x17c] ; /* 0x00005f0000097a13 */
/* 0x000fc80000000000 */
/*0180*/ I2F.RP R2, R9 ; /* 0x0000000900027306 */
/* 0x000e700000209400 */
/*0190*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x002e640000001000 */
/*01a0*/ IADD3 R6, R2, 0xffffffe, RZ ; /* 0x0ffffffe02067810 */
/* 0x002fcc0007ffe0ff */
/*01b0*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002a4000021f000 */
/*01c0*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x002fe20000000f00 */
/*01d0*/ IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff047224 */
/* 0x004fc800078e0a07 */
/*01e0*/ IMAD R11, R4, R9, RZ ; /* 0x00000009040b7224 */
/* 0x001fe200078e02ff */
/*01f0*/ IABS R4, R3 ; /* 0x0000000300047213 */
/* 0x000fc60000000000 */
/*0200*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fcc00078e0006 */
/*0210*/ IMAD.HI.U32 R7, R7, R4, RZ ; /* 0x0000000407077227 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.MOV R2, RZ, RZ, -R7 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a07 */
/*0230*/ IMAD R2, R9, R2, R4 ; /* 0x0000000209027224 */
/* 0x000fca00078e0204 */
/*0240*/ ISETP.GT.U32.AND P2, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f44070 */
/*0250*/ @!P2 IADD3 R2, R2, -R9.reuse, RZ ; /* 0x800000090202a210 */
/* 0x080fe40007ffe0ff */
/*0260*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fe40007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*0280*/ LOP3.LUT R2, R3, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0003027a12 */
/* 0x000fe400078e3cff */
/*0290*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*02a0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*02b0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fcc0007ffe0ff */
/*02c0*/ @!P1 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff079224 */
/* 0x000fe200078e0a07 */
/*02d0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff07aa12 */
/* 0x000fc800078e33ff */
/*02e0*/ IADD3 R4, -R7, RZ, RZ ; /* 0x000000ff07047210 */
/* 0x000fe40007ffe1ff */
/*02f0*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000fe60000201400 */
/*0300*/ IMAD R4, R4, c[0x0][0x17c], R3 ; /* 0x00005f0004047a24 */
/* 0x000fe400078e0203 */
/*0310*/ IMAD.WIDE R2, R5, R0, c[0x0][0x180] ; /* 0x0000600005027625 */
/* 0x000fc600078e0200 */
/*0320*/ I2F R9, R4 ; /* 0x0000000400097306 */
/* 0x000e220000201400 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff057424 */
/* 0x000fe200078e00ff */
/*0340*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R9 ; /* 0x000000090200798e */
/* 0x001fe8000c10e784 */
/*0350*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64+0x4], R7 ; /* 0x000004070200798e */
/* 0x000fe8000c10e784 */
/*0360*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64+0x8], R5 ; /* 0x000008050200798e */
/* 0x000fe2000c10e784 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.globl _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.p2align 8
.type _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii,@function
_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x30
s_load_b32 s3, s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
s_load_b64 s[4:5], s[0:1], 0x28
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v0, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s5
v_cvt_f32_i32_e32 v1, v1
global_store_b32 v[3:4], v1, off
v_add_nc_u32_e32 v5, 2, v0
v_cmp_gt_i32_e32 vcc_lo, s4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v1, 31, v0
s_load_b32 s0, s[0:1], 0x1c
v_ashrrev_i32_e32 v9, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_nc_u32_e32 v8, v2, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v8, v9
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_ashr_i32 s1, s0, 31
s_add_i32 s4, s0, s1
global_load_b32 v6, v[3:4], off
s_xor_b32 s4, s4, s1
v_xor_b32_e32 v9, s1, v9
v_cvt_f32_u32_e32 v5, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v7, s5, v5
v_mul_hi_u32 v7, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v7
v_mad_u64_u32 v[7:8], null, v10, v5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v8, s4
v_add_nc_u32_e32 v7, 1, v8
v_sub_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v10, s4, v5
v_cmp_le_u32_e32 vcc_lo, s4, v5
v_cndmask_b32_e32 v7, v8, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v10 :: v_dual_add_nc_u32 v8, 1, v7
v_cmp_le_u32_e32 vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v7, v8, vcc_lo
v_xor_b32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v7, v5, v9
v_mul_lo_u32 v5, v7, s0
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v5
v_cvt_f32_i32_e32 v2, v2
.LBB0_3:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v6, v2
global_atomic_cmpswap_b32 v5, v[3:4], v[5:6], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_cvt_f32_i32_e32 v6, v7
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v5, v[2:3], off offset:4
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_5:
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v5, v6
global_atomic_cmpswap_b32 v4, v[2:3], v[4:5], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v5
v_mov_b32_e32 v5, v4
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v3, v[0:1], off offset:8
v_add_co_u32 v0, vcc_lo, v0, 8
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_7:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v3
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_7
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, .Lfunc_end0-_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014bea5_00000000-6_CumulatePositionOfNewObjects.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii
.type _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii, @function
_Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii, .-_Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii
.globl _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.type _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, @function
_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z28CumulatePositionOfNewObjectsPfS_S_iiS_iiPfS_S_iiS_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, .-_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CumulatePositionOfNewObjects.hip"
.globl _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii # -- Begin function _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.p2align 4, 0x90
.type _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii,@function
_Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii: # @_Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii, .Lfunc_end0-_Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii,@object # @_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.section .rodata,"a",@progbits
.globl _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.p2align 3, 0x0
_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii:
.quad _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.size _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__CumulatePositionOfNewObjectsPfS_S_iiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28CumulatePositionOfNewObjectsPfS_S_iiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void _l1reg32(int n, double l1, float *w, float *dw) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (w[i] > 0) dw[i] += l1;
else if (w[i] < 0) dw[i] -= l1;
i += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z8_l1reg32idPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x1c0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*00d0*/ @P0 BRA 0x160 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00e0*/ FSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f0e000 */
/*00f0*/ @P0 BRA 0x1b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0110*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e240000201800 */
/*0120*/ DADD R2, R2, -c[0x0][0x168] ; /* 0x80005a0002027629 */
/* 0x001e140000000000 */
/*0130*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0140*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e2000c101904 */
/*0150*/ BRA 0x1b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0170*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e240000201800 */
/*0180*/ DADD R2, R2, c[0x0][0x168] ; /* 0x00005a0002027629 */
/* 0x001e140000000000 */
/*0190*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e4000c101904 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x001fca0000000f00 */
/*01d0*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*01f0*/ @!P0 BRA 0x70 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void _l1reg32(int n, double l1, float *w, float *dw) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (w[i] > 0) dw[i] += l1;
else if (w[i] < 0) dw[i] -= l1;
i += blockDim.x * gridDim.x;
}
} | .file "tmpxft_000a0ea0_00000000-6__l1reg32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8_l1reg32idPfS_idPfS_
.type _Z31__device_stub__Z8_l1reg32idPfS_idPfS_, @function
_Z31__device_stub__Z8_l1reg32idPfS_idPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8_l1reg32idPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8_l1reg32idPfS_idPfS_, .-_Z31__device_stub__Z8_l1reg32idPfS_idPfS_
.globl _Z8_l1reg32idPfS_
.type _Z8_l1reg32idPfS_, @function
_Z8_l1reg32idPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8_l1reg32idPfS_idPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8_l1reg32idPfS_, .-_Z8_l1reg32idPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8_l1reg32idPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8_l1reg32idPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void _l1reg32(int n, double l1, float *w, float *dw) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (w[i] > 0) dw[i] += l1;
else if (w[i] < 0) dw[i] -= l1;
i += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _l1reg32(int n, double l1, float *w, float *dw) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (w[i] > 0) dw[i] += l1;
else if (w[i] < 0) dw[i] -= l1;
i += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _l1reg32(int n, double l1, float *w, float *dw) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (w[i] > 0) dw[i] += l1;
else if (w[i] < 0) dw[i] -= l1;
i += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8_l1reg32idPfS_
.globl _Z8_l1reg32idPfS_
.p2align 8
.type _Z8_l1reg32idPfS_,@function
_Z8_l1reg32idPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_11
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s9
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_11
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s9, 0
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f32_e32 0, v0
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_7
s_mov_b32 s11, exec_lo
v_cmpx_gt_f32_e32 0, v0
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_6
v_add_co_u32 v2, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s9, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v0
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -s[4:5]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s9, s9, exec_lo
.LBB0_7:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_9
v_add_co_u32 v2, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
s_or_b32 s9, s9, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v0
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], s[4:5]
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
s_and_saveexec_b32 s10, s9
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[4:5]
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8_l1reg32idPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8_l1reg32idPfS_, .Lfunc_end0-_Z8_l1reg32idPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8_l1reg32idPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8_l1reg32idPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _l1reg32(int n, double l1, float *w, float *dw) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (w[i] > 0) dw[i] += l1;
else if (w[i] < 0) dw[i] -= l1;
i += blockDim.x * gridDim.x;
}
} | .text
.file "_l1reg32.hip"
.globl _Z23__device_stub___l1reg32idPfS_ # -- Begin function _Z23__device_stub___l1reg32idPfS_
.p2align 4, 0x90
.type _Z23__device_stub___l1reg32idPfS_,@function
_Z23__device_stub___l1reg32idPfS_: # @_Z23__device_stub___l1reg32idPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movsd %xmm0, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8_l1reg32idPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub___l1reg32idPfS_, .Lfunc_end0-_Z23__device_stub___l1reg32idPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8_l1reg32idPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8_l1reg32idPfS_,@object # @_Z8_l1reg32idPfS_
.section .rodata,"a",@progbits
.globl _Z8_l1reg32idPfS_
.p2align 3, 0x0
_Z8_l1reg32idPfS_:
.quad _Z23__device_stub___l1reg32idPfS_
.size _Z8_l1reg32idPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8_l1reg32idPfS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub___l1reg32idPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8_l1reg32idPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8_l1reg32idPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x1c0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*00d0*/ @P0 BRA 0x160 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00e0*/ FSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f0e000 */
/*00f0*/ @P0 BRA 0x1b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0110*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e240000201800 */
/*0120*/ DADD R2, R2, -c[0x0][0x168] ; /* 0x80005a0002027629 */
/* 0x001e140000000000 */
/*0130*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0140*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e2000c101904 */
/*0150*/ BRA 0x1b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0170*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e240000201800 */
/*0180*/ DADD R2, R2, c[0x0][0x168] ; /* 0x00005a0002027629 */
/* 0x001e140000000000 */
/*0190*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0011e4000c101904 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ MOV R3, c[0x0][0x0] ; /* 0x0000000000037a02 */
/* 0x001fca0000000f00 */
/*01d0*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*01f0*/ @!P0 BRA 0x70 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8_l1reg32idPfS_
.globl _Z8_l1reg32idPfS_
.p2align 8
.type _Z8_l1reg32idPfS_,@function
_Z8_l1reg32idPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_11
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s9
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_11
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s9, 0
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v7, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f32_e32 0, v0
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_7
s_mov_b32 s11, exec_lo
v_cmpx_gt_f32_e32 0, v0
s_xor_b32 s11, exec_lo, s11
s_cbranch_execz .LBB0_6
v_add_co_u32 v2, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
s_mov_b32 s9, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v0
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -s[4:5]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s9, s9, exec_lo
.LBB0_7:
s_and_not1_saveexec_b32 s10, s10
s_cbranch_execz .LBB0_9
v_add_co_u32 v2, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo
s_or_b32 s9, s9, exec_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v0
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], s[4:5]
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
s_and_saveexec_b32 s10, s9
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[4:5]
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8_l1reg32idPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8_l1reg32idPfS_, .Lfunc_end0-_Z8_l1reg32idPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8_l1reg32idPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8_l1reg32idPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a0ea0_00000000-6__l1reg32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8_l1reg32idPfS_idPfS_
.type _Z31__device_stub__Z8_l1reg32idPfS_idPfS_, @function
_Z31__device_stub__Z8_l1reg32idPfS_idPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movsd %xmm0, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8_l1reg32idPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8_l1reg32idPfS_idPfS_, .-_Z31__device_stub__Z8_l1reg32idPfS_idPfS_
.globl _Z8_l1reg32idPfS_
.type _Z8_l1reg32idPfS_, @function
_Z8_l1reg32idPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8_l1reg32idPfS_idPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8_l1reg32idPfS_, .-_Z8_l1reg32idPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8_l1reg32idPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8_l1reg32idPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "_l1reg32.hip"
.globl _Z23__device_stub___l1reg32idPfS_ # -- Begin function _Z23__device_stub___l1reg32idPfS_
.p2align 4, 0x90
.type _Z23__device_stub___l1reg32idPfS_,@function
_Z23__device_stub___l1reg32idPfS_: # @_Z23__device_stub___l1reg32idPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movsd %xmm0, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8_l1reg32idPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub___l1reg32idPfS_, .Lfunc_end0-_Z23__device_stub___l1reg32idPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8_l1reg32idPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8_l1reg32idPfS_,@object # @_Z8_l1reg32idPfS_
.section .rodata,"a",@progbits
.globl _Z8_l1reg32idPfS_
.p2align 3, 0x0
_Z8_l1reg32idPfS_:
.quad _Z23__device_stub___l1reg32idPfS_
.size _Z8_l1reg32idPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8_l1reg32idPfS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub___l1reg32idPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8_l1reg32idPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include "kernels.cuh"
__global__ void build_binary_tree(int *x, int *child, int *root, unsigned int n)
{
//Instantiate variables
unsigned int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
unsigned int stride = blockDim.x*gridDim.x;
unsigned int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
} | code for sm_80
Function : _Z17build_binary_treePiS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*00a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0a7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fce00078e0000 */
/*00d0*/ LOP3.LUT P0, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe2000780c0ff */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ BSSY B0, 0x180 ; /* 0x0000007000007945 */
/* 0x000fe80003800000 */
/*0110*/ IMAD.WIDE.U32 R2, R4, R13, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e000d */
/*0120*/ @!P0 BRA 0x170 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0130*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x024fc80003f04270 */
/*0160*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD R4, R12, 0x2, R11 ; /* 0x000000020c047824 */
/* 0x000fc800078e020b */
/*0190*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e020d */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ BSSY B0, 0x2b0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f06270 */
/*01d0*/ @!P0 BRA 0x2a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*01f0*/ BSSY B1, 0x2a0 ; /* 0x000000a000017945 */
/* 0x000fe40003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x020fe20003f04270 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0004 */
/*0220*/ SHF.L.U32 R8, R4, 0x1, RZ ; /* 0x0000000104087819 */
/* 0x000fe400000006ff */
/*0230*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0240*/ LOP3.LUT R8, R8, 0xfffffffe, R11, 0xe2, !PT ; /* 0xfffffffe08087812 */
/* 0x000fca00078ee20b */
/*0250*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0260*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.GT.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f04270 */
/*0280*/ @P0 BRA 0x200 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.NE.AND P0, PT, R4, -0x2, PT ; /* 0xfffffffe0400780c */
/* 0x000fe40003f05270 */
/*02c0*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fd6000000000a */
/*02d0*/ @!P0 BRA 0x3b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD R8, R12, 0x2, R11 ; /* 0x000000020c087824 */
/* 0x000fe200078e020b */
/*02f0*/ MOV R5, 0xfffffffe ; /* 0xfffffffe00057802 */
/* 0x000fc60000000f00 */
/*0300*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0310*/ ATOMG.E.CAS.STRONG.GPU PT, R5, [R8], R4, R5 ; /* 0x00000004080573a9 */
/* 0x000ea400001ee105 */
/*0320*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x004fda0003f05270 */
/*0330*/ @P0 BRA 0x3b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fd400078e00ff */
/*0370*/ @P0 BRA 0x3a0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea8000c1e1900 */
/*0390*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0041e4000c101904 */
/*03a0*/ IMAD R7, R4, c[0x0][0xc], R7 ; /* 0x0000030004077a24 */
/* 0x000fca00078e0207 */
/*03b0*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fe20007ffe0ff */
/*03c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*03f0*/ @!P0 BRA 0xd0 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "kernels.cuh"
__global__ void build_binary_tree(int *x, int *child, int *root, unsigned int n)
{
//Instantiate variables
unsigned int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
unsigned int stride = blockDim.x*gridDim.x;
unsigned int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
} | .file "tmpxft_0001150a_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j
.type _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j, @function
_Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17build_binary_treePiS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j, .-_Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j
.globl _Z17build_binary_treePiS_S_j
.type _Z17build_binary_treePiS_S_j, @function
_Z17build_binary_treePiS_S_j:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z17build_binary_treePiS_S_j, .-_Z17build_binary_treePiS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17build_binary_treePiS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17build_binary_treePiS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "kernels.cuh"
__global__ void build_binary_tree(int *x, int *child, int *root, unsigned int n)
{
//Instantiate variables
unsigned int bodyIndex = threadIdx.x + blockIdx.x*blockDim.x;
unsigned int stride = blockDim.x*gridDim.x;
unsigned int offset = 0;
bool newBody = true;
int rootValue = *root;
// build binary tree
int childPath;
int temp;
offset = 0;
while((bodyIndex + offset) < n){
if(newBody){
newBody = false;
temp = 0;
childPath = 0;
if(x[bodyIndex + offset] > rootValue){
childPath = 1;
}
}
int childIndex = child[temp*2 + childPath];
// traverse tree until we hit leaf node
while(childIndex >= 0){
temp = childIndex;
childPath = 0;
if(x[bodyIndex + offset] > temp){
childPath = 1;
}
childIndex = child[2*temp + childPath];
}
if(childIndex != -2){
int locked = temp*2 + childPath;
if(atomicCAS(&child[locked], childIndex, -2) == childIndex){
if(childIndex == -1){
child[locked] = x[bodyIndex + offset];
}
offset += stride;
newBody = true;
}
}
__syncthreads(); // not strictly needed
}
} | #ifndef __KERNELS_CUH__
#define __KERNELS_CUH__
__global__ void build_binary_tree(int *x, int *child, int *root, unsigned int n);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef __KERNELS_CUH__
#define __KERNELS_CUH__
__global__ void build_binary_tree(int *x, int *child, int *root, unsigned int n);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef __KERNELS_CUH__
#define __KERNELS_CUH__
__global__ void build_binary_tree(int *x, int *child, int *root, unsigned int n);
#endif | .text
.file "kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17build_binary_treePiS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000162000c1e1900 */
/*00a0*/ HFMA2.MMA R10, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0a7435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fce00078e0000 */
/*00d0*/ LOP3.LUT P0, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe2000780c0ff */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00f0*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0100*/ BSSY B0, 0x180 ; /* 0x0000007000007945 */
/* 0x000fe80003800000 */
/*0110*/ IMAD.WIDE.U32 R2, R4, R13, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x001fcc00078e000d */
/*0120*/ @!P0 BRA 0x170 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0130*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GT.AND P0, PT, R5, R6, PT ; /* 0x000000060500720c */
/* 0x024fc80003f04270 */
/*0160*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD R4, R12, 0x2, R11 ; /* 0x000000020c047824 */
/* 0x000fc800078e020b */
/*0190*/ IMAD.WIDE R4, R4, R13, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e020d */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ BSSY B0, 0x2b0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f06270 */
/*01d0*/ @!P0 BRA 0x2a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*01e0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*01f0*/ BSSY B1, 0x2a0 ; /* 0x000000a000017945 */
/* 0x000fe40003800000 */
/*0200*/ ISETP.GT.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x020fe20003f04270 */
/*0210*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0004 */
/*0220*/ SHF.L.U32 R8, R4, 0x1, RZ ; /* 0x0000000104087819 */
/* 0x000fe400000006ff */
/*0230*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*0240*/ LOP3.LUT R8, R8, 0xfffffffe, R11, 0xe2, !PT ; /* 0xfffffffe08087812 */
/* 0x000fca00078ee20b */
/*0250*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0260*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1900 */
/*0270*/ ISETP.GT.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fda0003f04270 */
/*0280*/ @P0 BRA 0x200 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0290*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.NE.AND P0, PT, R4, -0x2, PT ; /* 0xfffffffe0400780c */
/* 0x000fe40003f05270 */
/*02c0*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fd6000000000a */
/*02d0*/ @!P0 BRA 0x3b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD R8, R12, 0x2, R11 ; /* 0x000000020c087824 */
/* 0x000fe200078e020b */
/*02f0*/ MOV R5, 0xfffffffe ; /* 0xfffffffe00057802 */
/* 0x000fc60000000f00 */
/*0300*/ IMAD.WIDE R8, R8, R13, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e020d */
/*0310*/ ATOMG.E.CAS.STRONG.GPU PT, R5, [R8], R4, R5 ; /* 0x00000004080573a9 */
/* 0x000ea400001ee105 */
/*0320*/ ISETP.NE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x004fda0003f05270 */
/*0330*/ @P0 BRA 0x3b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0340*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x000fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fd400078e00ff */
/*0370*/ @P0 BRA 0x3a0 ; /* 0x0000002000000947 */
/* 0x000fea0003800000 */
/*0380*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea8000c1e1900 */
/*0390*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0041e4000c101904 */
/*03a0*/ IMAD R7, R4, c[0x0][0xc], R7 ; /* 0x0000030004077a24 */
/* 0x000fca00078e0207 */
/*03b0*/ IADD3 R4, R0, R7, RZ ; /* 0x0000000700047210 */
/* 0x000fe20007ffe0ff */
/*03c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*03f0*/ @!P0 BRA 0xd0 ; /* 0xfffffcd000008947 */
/* 0x000fea000383ffff */
/*0400*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0410*/ BRA 0x410; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001150a_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j
.type _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j, @function
_Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17build_binary_treePiS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j, .-_Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j
.globl _Z17build_binary_treePiS_S_j
.type _Z17build_binary_treePiS_S_j, @function
_Z17build_binary_treePiS_S_j:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17build_binary_treePiS_S_jPiS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z17build_binary_treePiS_S_j, .-_Z17build_binary_treePiS_S_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17build_binary_treePiS_S_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17build_binary_treePiS_S_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <curand_kernel.h>
#include <chrono>
#define host_t float
#define device_t float*
#define t_size sizeof(host_t)
#define size_t unsigned long
#define time_point_t std::chrono::time_point<std::chrono::high_resolution_clock>
template<typename A, typename B>
struct pair_t { A first; B second; };
host_t fZero(size_t x, size_t y, size_t w) { return 0; }
host_t fIndex(size_t x, size_t y, size_t w) { return (y * w + x); }
void printMatrix(FILE* file, host_t* matrix, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
void fillMatrix(host_t* matrix, size_t width, size_t height, host_t(*function)(size_t, size_t, size_t)) {
for (size_t y = 0; y < height; y++)
for (size_t x = 0; x < width; x++)
matrix[y * width + x] = function(x, y, width);
}
pair_t<size_t, size_t> compare(host_t* a, host_t* b, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++) {
if (a[y * width + x] != b[y * width + x]) {
printf("missmatch %f %f\n", a[y * width + x], b[y * width + x]);
return pair_t<size_t, size_t>{x, y};
}
}
}
return pair_t<size_t, size_t>{width, height};
}
void printWindow(FILE* file, host_t* matrix, size_t width, size_t w_start, size_t h_start, size_t w_width, size_t w_height) {
for (size_t y = w_start; y < w_height; y++) {
for (size_t x = h_start; x < w_width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
struct shared_t {
device_t device_ptr;
host_t *host_ptr;
size_t count;
size_t bytes;
shared_t(size_t element_count, bool cuda):
host_ptr{(host_t*) malloc(element_count * t_size)},
device_ptr{nullptr},
count{element_count},
bytes{element_count * t_size} {
if (cuda) {
cudaMalloc(&device_ptr, bytes);
}
printf("[shared_t] host:%p device:%p count:%lu bytes:%lu\n",
host_ptr, device_ptr, element_count, bytes);
}
~shared_t() {
printf("[shared_t] dispose %p %p\n", host_ptr, device_ptr);
if (host_ptr != nullptr)
free(host_ptr);
if (device_ptr != nullptr)
cudaFree(device_ptr);
}
int sync(cudaMemcpyKind kind) {
if (host_ptr == nullptr) {
printf("[shared_t] host_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 1;
}
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 2;
}
if (kind == cudaMemcpyDeviceToHost)
return cudaMemcpy(host_ptr, device_ptr, bytes, kind);
else
return cudaMemcpy(device_ptr, host_ptr, bytes, kind);
}
int upload() {
auto result = sync(cudaMemcpyHostToDevice);
if (result == cudaSuccess)
return 0;
printf("[shared_t] upload of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int download() {
auto result = sync(cudaMemcpyDeviceToHost);
if (result == cudaSuccess)
return 0;
printf("[shared_t] download of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int randomize() {
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr for randomize (host:%p, device:%p)\n",
host_ptr, device_ptr);
return 1;
}
curandGenerator_t generator;
auto r_gen_create = curandCreateGenerator(&generator, CURAND_RNG_PSEUDO_DEFAULT);
if (r_gen_create != CURAND_STATUS_SUCCESS) {
printf("[shared_t] create generator failed %d\n", r_gen_create);
return r_gen_create;
}
auto r_gen = curandGenerateNormal(generator, device_ptr, count, 40, 20);
if (r_gen != CURAND_STATUS_SUCCESS) {
printf("[shared_t] generate failed %d\n", r_gen);
}
auto r_destroy = curandDestroyGenerator(generator);
if (r_destroy != CURAND_STATUS_SUCCESS) {
printf("[shared_t] destroy generator failed %d\n", r_destroy);
return r_destroy;
}
return 0;
}
device_t device() const {
if (device_ptr == nullptr)
printf("[shared_t] device() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return device_ptr;
}
host_t* host() const {
if (host_ptr == nullptr)
printf("[shared_t] host() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return host_ptr;
}
};
struct measure_t {
bool use_cuda;
time_point_t tp_start;
time_point_t tp_end;
cudaEvent_t e_start;
cudaEvent_t e_end;
float mcs_value;
float cuda_mcs_value;
measure_t(bool cuda):
use_cuda{cuda} {
if (use_cuda) {
auto r_start = cudaEventCreate(&e_start);
auto r_end = cudaEventCreate(&e_end);
printf("[measure_t] create cuda events start:%d end:%d\n", r_start, r_end);
if (r_start != cudaSuccess || r_end != cudaSuccess) {
if (r_start != cudaSuccess && r_end == cudaSuccess)
cudaEventDestroy(e_end);
if (r_start == cudaSuccess && r_end != cudaSuccess)
cudaEventDestroy(e_start);
printf("[measure_t] disabling cuda events\n");
use_cuda = false;
}
}
}
~measure_t() {
if (use_cuda) {
auto r_end = cudaEventDestroy(e_end);
auto r_start = cudaEventDestroy(e_start);
printf("[measure_t] dispose cuda events start:%d end:%d\n", r_start, r_end);
}
}
void start() {
tp_start = std::chrono::high_resolution_clock::now();
if (use_cuda)
cudaEventRecord(e_start, 0);
}
void end() {
tp_end = std::chrono::high_resolution_clock::now();
mcs_value = std::chrono::duration_cast<std::chrono::microseconds>(tp_end - tp_start).count() * 1.0;
if (use_cuda) {
auto r_record = cudaEventRecord(e_end, 0);
auto r_sync = cudaEventSynchronize(e_end);
float elapsed = 0;
auto r_time = cudaEventElapsedTime(&elapsed, e_start, e_end);
if (r_record != cudaSuccess || r_sync != cudaSuccess || r_time != cudaSuccess) {
printf("[measure_t] cuda stop event is failed record:%d sync:%d time:%d\n",
r_record, r_sync, r_time);
return;
}
cuda_mcs_value = elapsed * 1000.0;
}
}
float mcs() const { return mcs_value; }
float cuda_mcs() const { return cuda_mcs_value; }
float ms() const { return mcs_value / 1000.0; }
float cuda_ms() { return cuda_mcs_value / 1000.0; }
};
__global__ void transformKernel(const device_t input, device_t output, size_t width, size_t threads) {
const size_t i = blockIdx.x * threads + threadIdx.x;
/* *block* vector index is equal to linear index */
/* but *block* index is 4 linear indecices */
const size_t y = i * 4 / width;
/* every *block* index is 4 linear indices */
const size_t x = 4 * (i % (width / 4));
/* every input vector is 2 output vectors */
const size_t oy = y * 2;
/* every *block* index is 2 linear indices */
const size_t ox = i * 2 % (width / 2);
/* aligned view into *block* */
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
__host__ void transformCpu(const host_t* input, host_t* output, size_t width, size_t height) {
const size_t iter = width * height / 4;
for (size_t i = 0; i < iter; i++) {
const size_t y = i * 4 / width;
const size_t x = 4 * (i % (width / 4));
const size_t oy = y * 2;
const size_t ox = i * 2 % (width / 2);
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
}
int main() {
const size_t height = 8444;
const size_t width = 4213;
const size_t count = height * width;
const size_t o_width = width / 2;
const size_t o_height = height * 2;
FILE* matrix_file = stdout;
if (width > 32 || height > 32) {
printf("[warning] matrix will not be printed because sizes are too big\n");
matrix_file = fopen("/dev/null", "w");
}
shared_t input{count, true};
shared_t output{count, true};
shared_t check{count, false};
measure_t measure{true};
measure_t cpu_measure{false};
/* generate random numbers in device memory */
if (input.randomize() != 0)
return 4;
/* copy it to host memory */
if (input.download() != 0)
return 3;
fillMatrix(output.host(), width, height, fZero);
fillMatrix(check.host(), width, height, fZero);
/* copy data into the device */
if (input.upload() != 0)
return 1;
/* output copy isn't necessary */
if (output.upload() != 0)
return 1;
/* calculate kernel start params */
const size_t iter_count = count / 4;
size_t thread_count = iter_count < 1024 ? iter_count : 1024;
for (; thread_count >= 2; thread_count--)
if (iter_count % thread_count == 0)
break;
printf("thread count: %lu\n", thread_count);
/* execute kernel on the device */
measure.start();
transformKernel<<<iter_count / thread_count, thread_count>>>(
input.device(),
output.device(),
width,
thread_count
);
measure.end();
cpu_measure.start();
transformCpu(input.host(), check.host(), width, height);
cpu_measure.end();
/* copy data from the device */
if (output.download() != 0)
return 2;
/* input copy isn't necessary */
if (input.download() != 0)
return 2;
fprintf(matrix_file, "input: \n");
printMatrix(matrix_file, input.host(), width, height);
fprintf(matrix_file, "output: \n");
printMatrix(matrix_file, output.host(), o_width, o_height);
fprintf(matrix_file, "check: \n");
printMatrix(matrix_file, check.host(), o_width, o_height);
printf("measure device: %f mcs\n", measure.cuda_mcs());
printf("measure host: %f mcs\n", cpu_measure.mcs());
auto result = compare(output.host(), check.host(), o_width, o_height);
if (result.first < o_width || result.second < o_height) {
printf("compare missmatch on %lu %lu\n", result.first, result.second);
} else {
printf("compare check passed!\n");
}
printf("input window: \n");
printWindow(stdout, input.host(), o_width, 0, 0, 4, 1);
printf("output window: \n");
printWindow(stdout, output.host(), o_width, 0, 0, 2, 2);
printf("check window: \n");
printWindow(stdout, check.host(), o_width, 0, 0, 2, 2);
/* all shared_t objects is allocated on the stack */
/* so, destructor will automatically free all memory */
return 0;
} | code for sm_80
Function : _Z15transformKernelPKfPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0030*/ BSSY B0, 0x250 ; /* 0x0000021000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0050*/ IMAD.WIDE.U32 R2, R5, c[0x0][0x178], R2 ; /* 0x00005e0005027a25 */
/* 0x001fc800078e0002 */
/*0060*/ IMAD R5, R5, c[0x0][0x17c], R3 ; /* 0x00005f0005057a24 */
/* 0x000fca00078e0203 */
/*0070*/ SHF.L.U64.HI R6, R2, 0x2, R5 ; /* 0x0000000202067819 */
/* 0x000fc80000010205 */
/*0080*/ LOP3.LUT R0, R6, c[0x0][0x174], RZ, 0xfc, !PT ; /* 0x00005d0006007a12 */
/* 0x000fc800078efcff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*00a0*/ IMAD.SHL.U32 R0, R2, 0x4, RZ ; /* 0x0000000402007824 */
/* 0x000fd800078e00ff */
/*00b0*/ @!P0 BRA 0x110 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00c0*/ MOV R4, 0xe0 ; /* 0x000000e000047802 */
/* 0x000fe40000000f00 */
/*00d0*/ CALL.REL.NOINC 0x940 ; /* 0x0000086000007944 */
/* 0x000fea0003c00000 */
/*00e0*/ MOV R6, R0 ; /* 0x0000000000067202 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, R9 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0009 */
/*0100*/ BRA 0x240 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0110*/ I2F.U32.RP R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000209000 */
/*0120*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fce0003f45070 */
/*0130*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R6, R4, 0xffffffe, RZ ; /* 0x0ffffffe04067810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a07 */
/*0180*/ IMAD R9, R9, c[0x0][0x170], RZ ; /* 0x00005c0009097a24 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fcc00078e0006 */
/*01a0*/ IMAD.HI.U32 R6, R7, R0, RZ ; /* 0x0000000007067227 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R7, -R6, RZ, RZ ; /* 0x000000ff06077210 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R0, R7, c[0x0][0x170], R0 ; /* 0x00005c0007007a24 */
/* 0x000fe400078e0200 */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IADD3 R0, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000000a10 */
/* 0x000fe40007ffe0ff */
/*0200*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f26070 */
/*0220*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*0230*/ @!P2 LOP3.LUT R6, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff06aa12 */
/* 0x000fe400078e33ff */
/*0240*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0250*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0260*/ BSSY B0, 0x480 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0270*/ USHF.R.U32.HI UR6, URZ, 0x2, UR5 ; /* 0x000000023f067899 */
/* 0x000fe40008011605 */
/*0280*/ USHF.R.U64 UR4, UR4, 0x2, UR5 ; /* 0x0000000204047899 */
/* 0x000fc80008001205 */
/*0290*/ LOP3.LUT R0, R5, UR6, RZ, 0xfc, !PT ; /* 0x0000000605007c12 */
/* 0x000fc8000f8efcff */
/*02a0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05070 */
/*02b0*/ @!P0 BRA 0x340 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0002 */
/*02d0*/ MOV R11, UR6 ; /* 0x00000006000b7c02 */
/* 0x000fe20008000f00 */
/*02e0*/ IMAD.U32 R10, RZ, RZ, UR4 ; /* 0x00000004ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ MOV R4, 0x310 ; /* 0x0000031000047802 */
/* 0x000fe40000000f00 */
/*0300*/ CALL.REL.NOINC 0xd80 ; /* 0x00000a7000007944 */
/* 0x000fea0003c00000 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, R13 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000d */
/*0330*/ BRA 0x470 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0340*/ I2F.U32.RP R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008209000 */
/*0350*/ ISETP.NE.U32.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fce000bf25070 */
/*0360*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0370*/ IADD3 R8, R0, 0xffffffe, RZ ; /* 0x0ffffffe00087810 */
/* 0x001fcc0007ffe0ff */
/*0380*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0390*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x001fe200000001ff */
/*03a0*/ IMAD.MOV R11, RZ, RZ, -R9 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a09 */
/*03b0*/ IMAD R11, R11, UR4, RZ ; /* 0x000000040b0b7c24 */
/* 0x000fca000f8e02ff */
/*03c0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fcc00078e0008 */
/*03d0*/ IMAD.HI.U32 R9, R9, R2, RZ ; /* 0x0000000209097227 */
/* 0x000fc800078e00ff */
/*03e0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0a09 */
/*03f0*/ IMAD R4, R9, UR4, R2 ; /* 0x0000000409047c24 */
/* 0x000fe4000f8e0202 */
/*0400*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc600078e00ff */
/*0410*/ ISETP.GE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06070 */
/*0420*/ @P0 IADD3 R4, R4, -UR4, RZ ; /* 0x8000000404040c10 */
/* 0x000fc8000fffe0ff */
/*0430*/ ISETP.GE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06070 */
/*0440*/ @P0 IADD3 R4, R4, -UR4, RZ ; /* 0x8000000404040c10 */
/* 0x000fe4000fffe0ff */
/*0450*/ @!P1 LOP3.LUT R4, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff049c12 */
/* 0x000fca000f8e33ff */
/*0460*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0490*/ SHF.L.U64.HI R5, R2.reuse, 0x1, R5 ; /* 0x0000000102057819 */
/* 0x040fe20000010205 */
/*04a0*/ USHF.R.U32.HI UR8, URZ, 0x1, UR5 ; /* 0x000000013f087899 */
/* 0x000fe20008011605 */
/*04b0*/ BSSY B0, 0x6d0 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*04c0*/ USHF.R.U64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe20008001205 */
/*04d0*/ SHF.L.U32 R4, R2, 0x1, RZ ; /* 0x0000000102047819 */
/* 0x000fe200000006ff */
/*04e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*04f0*/ LOP3.LUT R0, R5, UR8, RZ, 0xfc, !PT ; /* 0x0000000805007c12 */
/* 0x000fc8000f8efcff */
/*0500*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05070 */
/*0510*/ @!P0 BRA 0x5a0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0520*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0004 */
/*0530*/ MOV R4, 0x570 ; /* 0x0000057000047802 */
/* 0x000fe20000000f00 */
/*0540*/ IMAD.U32 R10, RZ, RZ, UR4 ; /* 0x00000004ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0550*/ IMAD.U32 R11, RZ, RZ, UR8 ; /* 0x00000008ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0560*/ CALL.REL.NOINC 0xd80 ; /* 0x0000081000007944 */
/* 0x000fea0003c00000 */
/*0570*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*0580*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*0590*/ BRA 0x6c0 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*05a0*/ I2F.U32.RP R0, UR4 ; /* 0x0000000400007d06 */
/* 0x000e220008209000 */
/*05b0*/ ISETP.NE.U32.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fce000bf25070 */
/*05c0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*05d0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*05e0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*05f0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0600*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0610*/ IMAD R5, R5, UR4, RZ ; /* 0x0000000405057c24 */
/* 0x000fc8000f8e02ff */
/*0620*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*0630*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0640*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fca00078e00ff */
/*0650*/ IADD3 R3, -R3, RZ, RZ ; /* 0x000000ff03037210 */
/* 0x000fca0007ffe1ff */
/*0660*/ IMAD R4, R3, UR4, R4 ; /* 0x0000000403047c24 */
/* 0x000fca000f8e0204 */
/*0670*/ ISETP.GE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06070 */
/*0680*/ @P0 IADD3 R4, R4, -UR4, RZ ; /* 0x8000000404040c10 */
/* 0x000fc8000fffe0ff */
/*0690*/ ISETP.GE.U32.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06070 */
/*06a0*/ @P0 IADD3 R4, R4, -UR4, RZ ; /* 0x8000000404040c10 */
/* 0x000fe4000fffe0ff */
/*06b0*/ @!P1 LOP3.LUT R4, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff049c12 */
/* 0x000fe4000f8e33ff */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ SHF.L.U64.HI R9, R8.reuse, 0x2, R9 ; /* 0x0000000208097819 */
/* 0x040fe20000010209 */
/*06e0*/ IMAD.SHL.U32 R8, R8, 0x4, RZ ; /* 0x0000000408087824 */
/* 0x000fe400078e00ff */
/*06f0*/ IMAD R3, R7, c[0x0][0x170], RZ ; /* 0x00005c0007037a24 */
/* 0x000fe400078e02ff */
/*0700*/ IMAD.WIDE.U32 R8, R6, c[0x0][0x170], R8 ; /* 0x00005c0006087a25 */
/* 0x000fc800078e0008 */
/*0710*/ IMAD R3, R6, c[0x0][0x174], R3 ; /* 0x00005d0006037a24 */
/* 0x000fe200078e0203 */
/*0720*/ LEA R2, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008027a11 */
/* 0x000fc800078010ff */
/*0730*/ IADD3 R3, R9, R3, RZ ; /* 0x0000000309037210 */
/* 0x000fc80007ffe0ff */
/*0740*/ LEA.HI.X R3, R8, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590008037a11 */
/* 0x000fca00000f1403 */
/*0750*/ LDG.E R11, [R2.64] ; /* 0x00000006020b7981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD.SHL.U32 R10, R6.reuse, 0x2, RZ ; /* 0x00000002060a7824 */
/* 0x040fe200078e00ff */
/*0770*/ SHF.L.U64.HI R0, R6, 0x1, R7 ; /* 0x0000000106007819 */
/* 0x000fc80000010207 */
/*0780*/ LOP3.LUT R6, R10, 0x1, RZ, 0xfc, !PT ; /* 0x000000010a067812 */
/* 0x000fe200078efcff */
/*0790*/ IMAD R17, R0, c[0x0][0x170], RZ ; /* 0x00005c0000117a24 */
/* 0x000fc800078e02ff */
/*07a0*/ IMAD R9, R6.reuse, c[0x0][0x174], R17 ; /* 0x00005d0006097a24 */
/* 0x040fe400078e0211 */
/*07b0*/ IMAD.WIDE.U32 R6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a25 */
/* 0x000fc800078e00ff */
/*07c0*/ IMAD.IADD R9, R7, 0x1, R9 ; /* 0x0000000107097824 */
/* 0x000fca00078e0209 */
/*07d0*/ SHF.R.U64 R7, R6, 0x1, R9.reuse ; /* 0x0000000106077819 */
/* 0x100fe40000001209 */
/*07e0*/ SHF.R.U32.HI R9, RZ, 0x1, R9 ; /* 0x00000001ff097819 */
/* 0x000fe40000011609 */
/*07f0*/ IADD3 R0, P0, R4, R7, RZ ; /* 0x0000000704007210 */
/* 0x000fc80007f1e0ff */
/*0800*/ IADD3.X R7, R5, R9, RZ, P0, !PT ; /* 0x0000000905077210 */
/* 0x000fe400007fe4ff */
/*0810*/ LEA R6, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000067a11 */
/* 0x000fc800078010ff */
/*0820*/ LEA.HI.X R7, R0, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0000077a11 */
/* 0x000fca00000f1407 */
/*0830*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x004fe8000c101906 */
/*0840*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000406020d7981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IMAD.WIDE.U32 R8, R10, c[0x0][0x170], RZ ; /* 0x00005c000a087a25 */
/* 0x000fc800078e00ff */
/*0860*/ IMAD R17, R10, c[0x0][0x174], R17 ; /* 0x00005d000a117a24 */
/* 0x000fc800078e0211 */
/*0870*/ IMAD.IADD R17, R9, 0x1, R17 ; /* 0x0000000109117824 */
/* 0x000fca00078e0211 */
/*0880*/ SHF.R.U64 R9, R8, 0x1, R17.reuse ; /* 0x0000000108097819 */
/* 0x100fe20000001211 */
/*0890*/ STG.E [R6.64+0x4], R13 ; /* 0x0000040d06007986 */
/* 0x004fe8000c101906 */
/*08a0*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000806020f7981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ SHF.R.U32.HI R17, RZ, 0x1, R17 ; /* 0x00000001ff117819 */
/* 0x000fe40000011611 */
/*08c0*/ IADD3 R0, P0, R4, R9, RZ ; /* 0x0000000904007210 */
/* 0x000fca0007f1e0ff */
/*08d0*/ IMAD.X R5, R5, 0x1, R17, P0 ; /* 0x0000000105057824 */
/* 0x000fe200000e0611 */
/*08e0*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*08f0*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f1405 */
/*0900*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x004fe8000c101906 */
/*0910*/ LDG.E R3, [R2.64+0xc] ; /* 0x00000c0602037981 */
/* 0x000ea8000c1e1900 */
/*0920*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x004fe2000c101906 */
/*0930*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0940*/ I2F.U64.RP R7, c[0x0][0x170] ; /* 0x00005c0000077b12 */
/* 0x000e300000309000 */
/*0950*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0960*/ IADD3 R8, R7, 0x1ffffffe, RZ ; /* 0x1ffffffe07087810 */
/* 0x001fcc0007ffe0ff */
/*0970*/ F2I.U64.TRUNC R8, R8 ; /* 0x0000000800087311 */
/* 0x000e24000020d800 */
/*0980*/ IMAD.WIDE.U32 R10, R8, c[0x0][0x170], RZ ; /* 0x00005c00080a7a25 */
/* 0x001fc800078e00ff */
/*0990*/ IMAD R11, R8, c[0x0][0x174], R11 ; /* 0x00005d00080b7a24 */
/* 0x000fe200078e020b */
/*09a0*/ IADD3 R13, P0, RZ, -R10, RZ ; /* 0x8000000aff0d7210 */
/* 0x000fc60007f1e0ff */
/*09b0*/ IMAD R11, R9, c[0x0][0x170], R11 ; /* 0x00005c00090b7a24 */
/* 0x000fe400078e020b */
/*09c0*/ IMAD.HI.U32 R10, R8, R13, RZ ; /* 0x0000000d080a7227 */
/* 0x000fc600078e00ff */
/*09d0*/ IADD3.X R15, RZ, ~R11, RZ, P0, !PT ; /* 0x8000000bff0f7210 */
/* 0x000fe200007fe4ff */
/*09e0*/ IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0008 */
/*09f0*/ IMAD.WIDE.U32 R10, P0, R8, R15, R10 ; /* 0x0000000f080a7225 */
/* 0x000fc8000780000a */
/*0a00*/ IMAD R17, R9.reuse, R15, RZ ; /* 0x0000000f09117224 */
/* 0x040fe400078e02ff */
/*0a10*/ IMAD.HI.U32 R10, P1, R9, R13, R10 ; /* 0x0000000d090a7227 */
/* 0x000fc8000782000a */
/*0a20*/ IMAD.HI.U32 R7, R9, R15, RZ ; /* 0x0000000f09077227 */
/* 0x000fe200078e00ff */
/*0a30*/ IADD3 R11, P2, R17, R10, RZ ; /* 0x0000000a110b7210 */
/* 0x000fc60007f5e0ff */
/*0a40*/ IMAD.X R7, R7, 0x1, R9, P0 ; /* 0x0000000107077824 */
/* 0x000fe400000e0609 */
/*0a50*/ IMAD.WIDE.U32 R8, R11, c[0x0][0x170], RZ ; /* 0x00005c000b087a25 */
/* 0x000fc600078e00ff */
/*0a60*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2407 */
/*0a70*/ IMAD R10, R11, c[0x0][0x174], R9 ; /* 0x00005d000b0a7a24 */
/* 0x000fe200078e0209 */
/*0a80*/ IADD3 R9, P0, RZ, -R8, RZ ; /* 0x80000008ff097210 */
/* 0x000fc60007f1e0ff */
/*0a90*/ IMAD R8, R7, c[0x0][0x170], R10 ; /* 0x00005c0007087a24 */
/* 0x000fe400078e020a */
/*0aa0*/ IMAD.HI.U32 R10, R11, R9, RZ ; /* 0x000000090b0a7227 */
/* 0x000fc600078e00ff */
/*0ab0*/ IADD3.X R8, RZ, ~R8, RZ, P0, !PT ; /* 0x80000008ff087210 */
/* 0x000fca00007fe4ff */
/*0ac0*/ IMAD.WIDE.U32 R10, P0, R11, R8, R10 ; /* 0x000000080b0a7225 */
/* 0x000fc8000780000a */
/*0ad0*/ IMAD R12, R7.reuse, R8, RZ ; /* 0x00000008070c7224 */
/* 0x040fe400078e02ff */
/*0ae0*/ IMAD.HI.U32 R11, P1, R7, R9, R10 ; /* 0x00000009070b7227 */
/* 0x000fc8000782000a */
/*0af0*/ IMAD.HI.U32 R8, R7, R8, RZ ; /* 0x0000000807087227 */
/* 0x000fe200078e00ff */
/*0b00*/ IADD3 R11, P2, R12, R11, RZ ; /* 0x0000000b0c0b7210 */
/* 0x000fc60007f5e0ff */
/*0b10*/ IMAD.X R7, R8, 0x1, R7, P0 ; /* 0x0000000108077824 */
/* 0x000fe400000e0607 */
/*0b20*/ IMAD.HI.U32 R8, R11, R0, RZ ; /* 0x000000000b087227 */
/* 0x000fc600078e00ff */
/*0b30*/ IADD3.X R7, RZ, RZ, R7, P2, P1 ; /* 0x000000ffff077210 */
/* 0x000fe200017e2407 */
/*0b40*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc800078e00ff */
/*0b50*/ IMAD.WIDE.U32 R8, R11, R6, R8 ; /* 0x000000060b087225 */
/* 0x000fc800078e0008 */
/*0b60*/ IMAD R11, R7.reuse, R6, RZ ; /* 0x00000006070b7224 */
/* 0x040fe400078e02ff */
/*0b70*/ IMAD.HI.U32 R8, P0, R7, R0, R8 ; /* 0x0000000007087227 */
/* 0x000fc80007800008 */
/*0b80*/ IMAD.HI.U32 R7, R7, R6, RZ ; /* 0x0000000607077227 */
/* 0x000fe200078e00ff */
/*0b90*/ IADD3 R11, P1, R11, R8, RZ ; /* 0x000000080b0b7210 */
/* 0x000fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, R7, RZ, RZ, P0, !PT ; /* 0x000000ff07077210 */
/* 0x000fe200007fe4ff */
/*0bb0*/ IMAD.WIDE.U32 R8, R11, c[0x0][0x170], RZ ; /* 0x00005c000b087a25 */
/* 0x000fc800078e00ff */
/*0bc0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0bd0*/ IADD3 R13, P1, -R8, R0, RZ ; /* 0x00000000080d7210 */
/* 0x000fe20007f3e1ff */
/*0be0*/ IMAD R10, R11, c[0x0][0x174], R9 ; /* 0x00005d000b0a7a24 */
/* 0x000fc600078e0209 */
/*0bf0*/ ISETP.GE.U32.AND P0, PT, R13, c[0x0][0x170], PT ; /* 0x00005c000d007a0c */
/* 0x000fe20003f06070 */
/*0c00*/ IMAD R9, R7, c[0x0][0x170], R10 ; /* 0x00005c0007097a24 */
/* 0x000fe200078e020a */
/*0c10*/ IADD3 R8, P2, R13, -c[0x0][0x170], RZ ; /* 0x80005c000d087a10 */
/* 0x000fc60007f5e0ff */
/*0c20*/ IMAD.X R10, R6, 0x1, ~R9, P1 ; /* 0x00000001060a7824 */
/* 0x000fe200008e0e09 */
/*0c30*/ IADD3 R0, P1, R11, 0x1, RZ ; /* 0x000000010b007810 */
/* 0x000fc80007f3e0ff */
/*0c40*/ ISETP.GE.U32.AND.EX P0, PT, R10.reuse, c[0x0][0x174], PT, P0 ; /* 0x00005d000a007a0c */
/* 0x040fe40003f06100 */
/*0c50*/ IADD3.X R9, R10, ~c[0x0][0x174], RZ, P2, !PT ; /* 0x80005d000a097a10 */
/* 0x000fe400017fe4ff */
/*0c60*/ IADD3.X R6, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff067210 */
/* 0x000fe40000ffe4ff */
/*0c70*/ SEL R8, R8, R13, P0 ; /* 0x0000000d08087207 */
/* 0x000fe40000000000 */
/*0c80*/ SEL R11, R0, R11, P0 ; /* 0x0000000b000b7207 */
/* 0x000fe40000000000 */
/*0c90*/ SEL R9, R9, R10, P0 ; /* 0x0000000a09097207 */
/* 0x000fc40000000000 */
/*0ca0*/ SEL R6, R6, R7, P0 ; /* 0x0000000706067207 */
/* 0x000fe20000000000 */
/*0cb0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0cc0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f06070 */
/*0cd0*/ IADD3 R0, P2, R11, 0x1, RZ ; /* 0x000000010b007810 */
/* 0x000fe40007f5e0ff */
/*0ce0*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x174], PT, P0 ; /* 0x00005d0009007a0c */
/* 0x000fe40003f06100 */
/*0cf0*/ ISETP.NE.U32.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f25070 */
/*0d00*/ IMAD.X R9, RZ, RZ, R6, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0606 */
/*0d10*/ SEL R0, R0, R11, P0 ; /* 0x0000000b00007207 */
/* 0x000fc40000000000 */
/*0d20*/ ISETP.NE.AND.EX P1, PT, RZ, c[0x0][0x174], PT, P1 ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25310 */
/*0d30*/ SEL R9, R9, R6, P0 ; /* 0x0000000609097207 */
/* 0x000fe20000000000 */
/*0d40*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0d50*/ SEL R0, R0, 0xffffffff, P1 ; /* 0xffffffff00007807 */
/* 0x000fe40000800000 */
/*0d60*/ SEL R9, R9, 0xffffffff, P1 ; /* 0xffffffff09097807 */
/* 0x000fe20000800000 */
/*0d70*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff28006007950 */
/* 0x000fec0003c3ffff */
/*0d80*/ I2F.U64.RP R16, R10 ; /* 0x0000000a00107312 */
/* 0x000e300000309000 */
/*0d90*/ MUFU.RCP R16, R16 ; /* 0x0000001000107308 */
/* 0x001e240000001000 */
/*0da0*/ IADD3 R12, R16, 0x1ffffffe, RZ ; /* 0x1ffffffe100c7810 */
/* 0x001fcc0007ffe0ff */
/*0db0*/ F2I.U64.TRUNC R12, R12 ; /* 0x0000000c000c7311 */
/* 0x000e24000020d800 */
/*0dc0*/ IMAD.WIDE.U32 R14, R12, R10, RZ ; /* 0x0000000a0c0e7225 */
/* 0x001fc800078e00ff */
/*0dd0*/ IMAD R15, R12, R11, R15 ; /* 0x0000000b0c0f7224 */
/* 0x000fe200078e020f */
/*0de0*/ IADD3 R17, P0, RZ, -R14, RZ ; /* 0x8000000eff117210 */
/* 0x000fc60007f1e0ff */
/*0df0*/ IMAD R15, R13, R10, R15 ; /* 0x0000000a0d0f7224 */
/* 0x000fe400078e020f */
/*0e00*/ IMAD.HI.U32 R14, R12, R17, RZ ; /* 0x000000110c0e7227 */
/* 0x000fc800078e00ff */
/*0e10*/ IMAD.X R19, RZ, RZ, ~R15, P0 ; /* 0x000000ffff137224 */
/* 0x000fe400000e0e0f */
/*0e20*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000c */
/*0e30*/ IMAD R21, R13, R19.reuse, RZ ; /* 0x000000130d157224 */
/* 0x080fe400078e02ff */
/*0e40*/ IMAD.WIDE.U32 R14, P0, R12, R19, R14 ; /* 0x000000130c0e7225 */
/* 0x000fc8000780000e */
/*0e50*/ IMAD.HI.U32 R19, R13, R19, RZ ; /* 0x000000130d137227 */
/* 0x000fc800078e00ff */
/*0e60*/ IMAD.HI.U32 R14, P1, R13, R17, R14 ; /* 0x000000110d0e7227 */
/* 0x000fca000782000e */
/*0e70*/ IADD3 R15, P2, R21, R14, RZ ; /* 0x0000000e150f7210 */
/* 0x000fe40007f5e0ff */
/*0e80*/ IADD3.X R14, R19, R13, RZ, P0, !PT ; /* 0x0000000d130e7210 */
/* 0x000fc600007fe4ff */
/*0e90*/ IMAD.WIDE.U32 R12, R15, R10, RZ ; /* 0x0000000a0f0c7225 */
/* 0x000fe200078e00ff */
/*0ea0*/ IADD3.X R17, RZ, RZ, R14, P2, P1 ; /* 0x000000ffff117210 */
/* 0x000fc600017e240e */
/*0eb0*/ IMAD R13, R15, R11, R13 ; /* 0x0000000b0f0d7224 */
/* 0x000fe200078e020d */
/*0ec0*/ IADD3 R19, P0, RZ, -R12, RZ ; /* 0x8000000cff137210 */
/* 0x000fc60007f1e0ff */
/*0ed0*/ IMAD R13, R17, R10, R13 ; /* 0x0000000a110d7224 */
/* 0x000fe400078e020d */
/*0ee0*/ IMAD.HI.U32 R14, R15, R19, RZ ; /* 0x000000130f0e7227 */
/* 0x000fc800078e00ff */
/*0ef0*/ IMAD.X R12, RZ, RZ, ~R13, P0 ; /* 0x000000ffff0c7224 */
/* 0x000fe200000e0e0d */
/*0f00*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fc60000000f00 */
/*0f10*/ IMAD.WIDE.U32 R14, P0, R15, R12, R14 ; /* 0x0000000c0f0e7225 */
/* 0x000fc8000780000e */
/*0f20*/ IMAD R16, R17.reuse, R12, RZ ; /* 0x0000000c11107224 */
/* 0x040fe400078e02ff */
/*0f30*/ IMAD.HI.U32 R15, P1, R17, R19, R14 ; /* 0x00000013110f7227 */
/* 0x000fc8000782000e */
/*0f40*/ IMAD.HI.U32 R12, R17, R12, RZ ; /* 0x0000000c110c7227 */
/* 0x000fe200078e00ff */
/*0f50*/ IADD3 R15, P2, R16, R15, RZ ; /* 0x0000000f100f7210 */
/* 0x000fc60007f5e0ff */
/*0f60*/ IMAD.X R17, R12, 0x1, R17, P0 ; /* 0x000000010c117824 */
/* 0x000fe400000e0611 */
/*0f70*/ IMAD.HI.U32 R12, R15, R0, RZ ; /* 0x000000000f0c7227 */
/* 0x000fc600078e00ff */
/*0f80*/ IADD3.X R17, RZ, RZ, R17, P2, P1 ; /* 0x000000ffff117210 */
/* 0x000fc600017e2411 */
/*0f90*/ IMAD.WIDE.U32 R12, R15, R5, R12 ; /* 0x000000050f0c7225 */
/* 0x000fc800078e000c */
/*0fa0*/ IMAD R15, R17.reuse, R5, RZ ; /* 0x00000005110f7224 */
/* 0x040fe400078e02ff */
/*0fb0*/ IMAD.HI.U32 R12, P0, R17, R0, R12 ; /* 0x00000000110c7227 */
/* 0x000fc8000780000c */
/*0fc0*/ IMAD.HI.U32 R14, R17, R5, RZ ; /* 0x00000005110e7227 */
/* 0x000fe200078e00ff */
/*0fd0*/ IADD3 R15, P1, R15, R12, RZ ; /* 0x0000000c0f0f7210 */
/* 0x000fc60007f3e0ff */
/*0fe0*/ IMAD.X R14, RZ, RZ, R14, P0 ; /* 0x000000ffff0e7224 */
/* 0x000fe400000e060e */
/*0ff0*/ IMAD.WIDE.U32 R12, R15, R10, RZ ; /* 0x0000000a0f0c7225 */
/* 0x000fc800078e00ff */
/*1000*/ IMAD.X R17, RZ, RZ, R14, P1 ; /* 0x000000ffff117224 */
/* 0x000fe400008e060e */
/*1010*/ IMAD R15, R15, R11, R13 ; /* 0x0000000b0f0f7224 */
/* 0x000fe200078e020d */
/*1020*/ IADD3 R13, P1, -R12, R0, RZ ; /* 0x000000000c0d7210 */
/* 0x000fc60007f3e1ff */
/*1030*/ IMAD R0, R17, R10.reuse, R15 ; /* 0x0000000a11007224 */
/* 0x080fe200078e020f */
/*1040*/ ISETP.GE.U32.AND P0, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x000fc80003f06070 */
/*1050*/ IADD3.X R0, ~R0, R5, RZ, P1, !PT ; /* 0x0000000500007210 */
/* 0x000fe40000ffe5ff */
/*1060*/ IADD3 R15, P1, -R10, R13, RZ ; /* 0x0000000d0a0f7210 */
/* 0x000fe40007f3e1ff */
/*1070*/ ISETP.GE.U32.AND.EX P0, PT, R0, R11, PT, P0 ; /* 0x0000000b0000720c */
/* 0x000fc60003f06100 */
/*1080*/ IMAD.X R12, R0, 0x1, ~R11.reuse, P1 ; /* 0x00000001000c7824 */
/* 0x100fe200008e0e0b */
/*1090*/ SEL R15, R15, R13, P0 ; /* 0x0000000d0f0f7207 */
/* 0x000fe40000000000 */
/*10a0*/ ISETP.NE.U32.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f25070 */
/*10b0*/ SEL R12, R12, R0, P0 ; /* 0x000000000c0c7207 */
/* 0x000fe40000000000 */
/*10c0*/ IADD3 R0, P2, -R10, R15, RZ ; /* 0x0000000f0a007210 */
/* 0x000fe40007f5e1ff */
/*10d0*/ ISETP.GE.U32.AND P0, PT, R15, R10, PT ; /* 0x0000000a0f00720c */
/* 0x000fe40003f06070 */
/*10e0*/ ISETP.NE.AND.EX P1, PT, R11, RZ, PT, P1 ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25310 */
/*10f0*/ IMAD.X R13, R12.reuse, 0x1, ~R11, P2 ; /* 0x000000010c0d7824 */
/* 0x040fe200010e0e0b */
/*1100*/ ISETP.GE.U32.AND.EX P0, PT, R12, R11, PT, P0 ; /* 0x0000000b0c00720c */
/* 0x000fe20003f06100 */
/*1110*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe200078e00ff */
/*1120*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fc40000000f00 */
/*1130*/ SEL R0, R0, R15, P0 ; /* 0x0000000f00007207 */
/* 0x000fe40000000000 */
/*1140*/ SEL R13, R13, R12, P0 ; /* 0x0000000c0d0d7207 */
/* 0x000fe40000000000 */
/*1150*/ SEL R0, R0, 0xffffffff, P1 ; /* 0xffffffff00007807 */
/* 0x000fe40000800000 */
/*1160*/ SEL R13, R13, 0xffffffff, P1 ; /* 0xffffffff0d0d7807 */
/* 0x000fe20000800000 */
/*1170*/ RET.REL.NODEC R10 0x0 ; /* 0xffffee800a007950 */
/* 0x000fec0003c3ffff */
/*1180*/ BRA 0x1180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <curand_kernel.h>
#include <chrono>
#define host_t float
#define device_t float*
#define t_size sizeof(host_t)
#define size_t unsigned long
#define time_point_t std::chrono::time_point<std::chrono::high_resolution_clock>
template<typename A, typename B>
struct pair_t { A first; B second; };
host_t fZero(size_t x, size_t y, size_t w) { return 0; }
host_t fIndex(size_t x, size_t y, size_t w) { return (y * w + x); }
void printMatrix(FILE* file, host_t* matrix, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
void fillMatrix(host_t* matrix, size_t width, size_t height, host_t(*function)(size_t, size_t, size_t)) {
for (size_t y = 0; y < height; y++)
for (size_t x = 0; x < width; x++)
matrix[y * width + x] = function(x, y, width);
}
pair_t<size_t, size_t> compare(host_t* a, host_t* b, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++) {
if (a[y * width + x] != b[y * width + x]) {
printf("missmatch %f %f\n", a[y * width + x], b[y * width + x]);
return pair_t<size_t, size_t>{x, y};
}
}
}
return pair_t<size_t, size_t>{width, height};
}
void printWindow(FILE* file, host_t* matrix, size_t width, size_t w_start, size_t h_start, size_t w_width, size_t w_height) {
for (size_t y = w_start; y < w_height; y++) {
for (size_t x = h_start; x < w_width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
struct shared_t {
device_t device_ptr;
host_t *host_ptr;
size_t count;
size_t bytes;
shared_t(size_t element_count, bool cuda):
host_ptr{(host_t*) malloc(element_count * t_size)},
device_ptr{nullptr},
count{element_count},
bytes{element_count * t_size} {
if (cuda) {
cudaMalloc(&device_ptr, bytes);
}
printf("[shared_t] host:%p device:%p count:%lu bytes:%lu\n",
host_ptr, device_ptr, element_count, bytes);
}
~shared_t() {
printf("[shared_t] dispose %p %p\n", host_ptr, device_ptr);
if (host_ptr != nullptr)
free(host_ptr);
if (device_ptr != nullptr)
cudaFree(device_ptr);
}
int sync(cudaMemcpyKind kind) {
if (host_ptr == nullptr) {
printf("[shared_t] host_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 1;
}
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 2;
}
if (kind == cudaMemcpyDeviceToHost)
return cudaMemcpy(host_ptr, device_ptr, bytes, kind);
else
return cudaMemcpy(device_ptr, host_ptr, bytes, kind);
}
int upload() {
auto result = sync(cudaMemcpyHostToDevice);
if (result == cudaSuccess)
return 0;
printf("[shared_t] upload of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int download() {
auto result = sync(cudaMemcpyDeviceToHost);
if (result == cudaSuccess)
return 0;
printf("[shared_t] download of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int randomize() {
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr for randomize (host:%p, device:%p)\n",
host_ptr, device_ptr);
return 1;
}
curandGenerator_t generator;
auto r_gen_create = curandCreateGenerator(&generator, CURAND_RNG_PSEUDO_DEFAULT);
if (r_gen_create != CURAND_STATUS_SUCCESS) {
printf("[shared_t] create generator failed %d\n", r_gen_create);
return r_gen_create;
}
auto r_gen = curandGenerateNormal(generator, device_ptr, count, 40, 20);
if (r_gen != CURAND_STATUS_SUCCESS) {
printf("[shared_t] generate failed %d\n", r_gen);
}
auto r_destroy = curandDestroyGenerator(generator);
if (r_destroy != CURAND_STATUS_SUCCESS) {
printf("[shared_t] destroy generator failed %d\n", r_destroy);
return r_destroy;
}
return 0;
}
device_t device() const {
if (device_ptr == nullptr)
printf("[shared_t] device() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return device_ptr;
}
host_t* host() const {
if (host_ptr == nullptr)
printf("[shared_t] host() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return host_ptr;
}
};
struct measure_t {
bool use_cuda;
time_point_t tp_start;
time_point_t tp_end;
cudaEvent_t e_start;
cudaEvent_t e_end;
float mcs_value;
float cuda_mcs_value;
measure_t(bool cuda):
use_cuda{cuda} {
if (use_cuda) {
auto r_start = cudaEventCreate(&e_start);
auto r_end = cudaEventCreate(&e_end);
printf("[measure_t] create cuda events start:%d end:%d\n", r_start, r_end);
if (r_start != cudaSuccess || r_end != cudaSuccess) {
if (r_start != cudaSuccess && r_end == cudaSuccess)
cudaEventDestroy(e_end);
if (r_start == cudaSuccess && r_end != cudaSuccess)
cudaEventDestroy(e_start);
printf("[measure_t] disabling cuda events\n");
use_cuda = false;
}
}
}
~measure_t() {
if (use_cuda) {
auto r_end = cudaEventDestroy(e_end);
auto r_start = cudaEventDestroy(e_start);
printf("[measure_t] dispose cuda events start:%d end:%d\n", r_start, r_end);
}
}
void start() {
tp_start = std::chrono::high_resolution_clock::now();
if (use_cuda)
cudaEventRecord(e_start, 0);
}
void end() {
tp_end = std::chrono::high_resolution_clock::now();
mcs_value = std::chrono::duration_cast<std::chrono::microseconds>(tp_end - tp_start).count() * 1.0;
if (use_cuda) {
auto r_record = cudaEventRecord(e_end, 0);
auto r_sync = cudaEventSynchronize(e_end);
float elapsed = 0;
auto r_time = cudaEventElapsedTime(&elapsed, e_start, e_end);
if (r_record != cudaSuccess || r_sync != cudaSuccess || r_time != cudaSuccess) {
printf("[measure_t] cuda stop event is failed record:%d sync:%d time:%d\n",
r_record, r_sync, r_time);
return;
}
cuda_mcs_value = elapsed * 1000.0;
}
}
float mcs() const { return mcs_value; }
float cuda_mcs() const { return cuda_mcs_value; }
float ms() const { return mcs_value / 1000.0; }
float cuda_ms() { return cuda_mcs_value / 1000.0; }
};
__global__ void transformKernel(const device_t input, device_t output, size_t width, size_t threads) {
const size_t i = blockIdx.x * threads + threadIdx.x;
/* *block* vector index is equal to linear index */
/* but *block* index is 4 linear indecices */
const size_t y = i * 4 / width;
/* every *block* index is 4 linear indices */
const size_t x = 4 * (i % (width / 4));
/* every input vector is 2 output vectors */
const size_t oy = y * 2;
/* every *block* index is 2 linear indices */
const size_t ox = i * 2 % (width / 2);
/* aligned view into *block* */
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
__host__ void transformCpu(const host_t* input, host_t* output, size_t width, size_t height) {
const size_t iter = width * height / 4;
for (size_t i = 0; i < iter; i++) {
const size_t y = i * 4 / width;
const size_t x = 4 * (i % (width / 4));
const size_t oy = y * 2;
const size_t ox = i * 2 % (width / 2);
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
}
int main() {
const size_t height = 8444;
const size_t width = 4213;
const size_t count = height * width;
const size_t o_width = width / 2;
const size_t o_height = height * 2;
FILE* matrix_file = stdout;
if (width > 32 || height > 32) {
printf("[warning] matrix will not be printed because sizes are too big\n");
matrix_file = fopen("/dev/null", "w");
}
shared_t input{count, true};
shared_t output{count, true};
shared_t check{count, false};
measure_t measure{true};
measure_t cpu_measure{false};
/* generate random numbers in device memory */
if (input.randomize() != 0)
return 4;
/* copy it to host memory */
if (input.download() != 0)
return 3;
fillMatrix(output.host(), width, height, fZero);
fillMatrix(check.host(), width, height, fZero);
/* copy data into the device */
if (input.upload() != 0)
return 1;
/* output copy isn't necessary */
if (output.upload() != 0)
return 1;
/* calculate kernel start params */
const size_t iter_count = count / 4;
size_t thread_count = iter_count < 1024 ? iter_count : 1024;
for (; thread_count >= 2; thread_count--)
if (iter_count % thread_count == 0)
break;
printf("thread count: %lu\n", thread_count);
/* execute kernel on the device */
measure.start();
transformKernel<<<iter_count / thread_count, thread_count>>>(
input.device(),
output.device(),
width,
thread_count
);
measure.end();
cpu_measure.start();
transformCpu(input.host(), check.host(), width, height);
cpu_measure.end();
/* copy data from the device */
if (output.download() != 0)
return 2;
/* input copy isn't necessary */
if (input.download() != 0)
return 2;
fprintf(matrix_file, "input: \n");
printMatrix(matrix_file, input.host(), width, height);
fprintf(matrix_file, "output: \n");
printMatrix(matrix_file, output.host(), o_width, o_height);
fprintf(matrix_file, "check: \n");
printMatrix(matrix_file, check.host(), o_width, o_height);
printf("measure device: %f mcs\n", measure.cuda_mcs());
printf("measure host: %f mcs\n", cpu_measure.mcs());
auto result = compare(output.host(), check.host(), o_width, o_height);
if (result.first < o_width || result.second < o_height) {
printf("compare missmatch on %lu %lu\n", result.first, result.second);
} else {
printf("compare check passed!\n");
}
printf("input window: \n");
printWindow(stdout, input.host(), o_width, 0, 0, 4, 1);
printf("output window: \n");
printWindow(stdout, output.host(), o_width, 0, 0, 2, 2);
printf("check window: \n");
printWindow(stdout, check.host(), o_width, 0, 0, 2, 2);
/* all shared_t objects is allocated on the stack */
/* so, destructor will automatically free all memory */
return 0;
} | .file "tmpxft_00089e91_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z5fZerommm
.type _Z5fZerommm, @function
_Z5fZerommm:
.LFB2370:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
ret
.cfi_endproc
.LFE2370:
.size _Z5fZerommm, .-_Z5fZerommm
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2405:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2405:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6fIndexmmm
.type _Z6fIndexmmm, @function
_Z6fIndexmmm:
.LFB2371:
.cfi_startproc
endbr64
imulq %rdx, %rsi
addq %rdi, %rsi
js .L5
pxor %xmm0, %xmm0
cvtsi2ssq %rsi, %xmm0
ret
.L5:
movq %rsi, %rax
shrq %rax
andl $1, %esi
orq %rsi, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
ret
.cfi_endproc
.LFE2371:
.size _Z6fIndexmmm, .-_Z6fIndexmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%03.0f "
.LC2:
.string "\n"
.text
.globl _Z11printMatrixP8_IO_FILEPfmm
.type _Z11printMatrixP8_IO_FILEPfmm, @function
_Z11printMatrixP8_IO_FILEPfmm:
.LFB2372:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rcx, (%rsp)
testq %rcx, %rcx
je .L8
movq %rdx, %r13
leaq 0(,%rdx,4), %rax
movq %rax, 8(%rsp)
movq %rsi, %rbp
movl $0, %r15d
leaq .LC1(%rip), %r14
jmp .L9
.L10:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L10
.L11:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %r15
movq 8(%rsp), %rax
addq %rax, %rbp
cmpq %r15, (%rsp)
je .L8
.L9:
movl $0, %ebx
testq %r13, %r13
jne .L10
jmp .L11
.L8:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2372:
.size _Z11printMatrixP8_IO_FILEPfmm, .-_Z11printMatrixP8_IO_FILEPfmm
.globl _Z10fillMatrixPfmmPFfmmmE
.type _Z10fillMatrixPfmmPFfmmmE, @function
_Z10fillMatrixPfmmPFfmmmE:
.LFB2373:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdx, 8(%rsp)
testq %rdx, %rdx
je .L16
movq %rsi, %rbp
movq %rcx, %r14
leaq 0(,%rsi,4), %r15
movq %rdi, %r13
movl $0, %r12d
jmp .L18
.L19:
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call *%r14
movss %xmm0, 0(%r13,%rbx,4)
addq $1, %rbx
cmpq %rbx, %rbp
jne .L19
.L20:
addq $1, %r12
addq %r15, %r13
cmpq %r12, 8(%rsp)
je .L16
.L18:
movl $0, %ebx
testq %rbp, %rbp
jne .L19
jmp .L20
.L16:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2373:
.size _Z10fillMatrixPfmmPFfmmmE, .-_Z10fillMatrixPfmmPFfmmmE
.section .rodata.str1.1
.LC3:
.string "missmatch %f %f\n"
.text
.globl _Z7comparePfS_mm
.type _Z7comparePfS_mm, @function
_Z7comparePfS_mm:
.LFB2374:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
testq %rcx, %rcx
je .L32
leaq 0(,%rdx,4), %rax
movl $0, %ebp
.L27:
movl $0, %ebx
testq %rdx, %rdx
je .L31
.L30:
movss (%rdi,%rbx,4), %xmm0
movss (%rsi,%rbx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L35
jne .L35
addq $1, %rbx
cmpq %rbx, %rdx
jne .L30
.L31:
addq $1, %rbp
addq %rax, %rdi
addq %rax, %rsi
cmpq %rbp, %rcx
jne .L27
movq %rdx, %rbx
movq %rcx, %rbp
jmp .L26
.L35:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
.L26:
movq %rbx, %rax
movq %rbp, %rdx
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq %rdx, %rbx
movq %rcx, %rbp
jmp .L26
.cfi_endproc
.LFE2374:
.size _Z7comparePfS_mm, .-_Z7comparePfS_mm
.globl _Z11printWindowP8_IO_FILEPfmmmmm
.type _Z11printWindowP8_IO_FILEPfmmmmm, @function
_Z11printWindowP8_IO_FILEPfmmmmm:
.LFB2375:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %r8, (%rsp)
cmpq 80(%rsp), %rcx
jnb .L40
movq %rsi, %rbp
movq %rcx, %r15
movq %r9, %r13
leaq 0(,%rdx,4), %rax
movq %rax, 8(%rsp)
imulq %rcx, %rax
addq %rax, %rbp
leaq .LC1(%rip), %r14
jmp .L41
.L42:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L42
.L43:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %r15
movq 8(%rsp), %rax
addq %rax, %rbp
cmpq %r15, 80(%rsp)
je .L40
.L41:
movq (%rsp), %rax
movq %rax, %rbx
cmpq %r13, %rax
jb .L42
jmp .L43
.L40:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2375:
.size _Z11printWindowP8_IO_FILEPfmmmmm, .-_Z11printWindowP8_IO_FILEPfmmmmm
.section .rodata._ZN8shared_tC2Emb.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "[shared_t] host:%p device:%p count:%lu bytes:%lu\n"
.section .text._ZN8shared_tC2Emb,"axG",@progbits,_ZN8shared_tC5Emb,comdat
.align 2
.weak _ZN8shared_tC2Emb
.type _ZN8shared_tC2Emb, @function
_ZN8shared_tC2Emb:
.LFB2377:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %rbp
movl %edx, %r12d
movq $0, (%rdi)
leaq 0(,%rsi,4), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, 8(%rbx)
movq %rbp, 16(%rbx)
movq %r13, 24(%rbx)
testb %r12b, %r12b
jne .L51
.L49:
movq (%rbx), %rcx
movq 8(%rbx), %rdx
movq 24(%rbx), %r9
movq %rbp, %r8
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq %r13, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
jmp .L49
.cfi_endproc
.LFE2377:
.size _ZN8shared_tC2Emb, .-_ZN8shared_tC2Emb
.weak _ZN8shared_tC1Emb
.set _ZN8shared_tC1Emb,_ZN8shared_tC2Emb
.section .rodata._ZN8shared_tD2Ev.str1.1,"aMS",@progbits,1
.LC5:
.string "[shared_t] dispose %p %p\n"
.section .text._ZN8shared_tD2Ev,"axG",@progbits,_ZN8shared_tD5Ev,comdat
.align 2
.weak _ZN8shared_tD2Ev
.type _ZN8shared_tD2Ev, @function
_ZN8shared_tD2Ev:
.LFB2380:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2380
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rcx
movq 8(%rdi), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %rdi
testq %rdi, %rdi
je .L53
call free@PLT
.L53:
movq (%rbx), %rdi
testq %rdi, %rdi
je .L52
call cudaFree@PLT
.L52:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2380:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN8shared_tD2Ev,"aG",@progbits,_ZN8shared_tD5Ev,comdat
.LLSDA2380:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2380-.LLSDACSB2380
.LLSDACSB2380:
.LLSDACSE2380:
.section .text._ZN8shared_tD2Ev,"axG",@progbits,_ZN8shared_tD5Ev,comdat
.size _ZN8shared_tD2Ev, .-_ZN8shared_tD2Ev
.weak _ZN8shared_tD1Ev
.set _ZN8shared_tD1Ev,_ZN8shared_tD2Ev
.section .rodata._ZN8shared_t6uploadEv.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "[shared_t] host_ptr is nullptr (host:%p, device:%p)\n"
.align 8
.LC7:
.string "[shared_t] device_ptr is nullptr (host:%p, device:%p)\n"
.align 8
.LC8:
.string "[shared_t] upload of (%p, %p, %lu) failed %d\n"
.section .text._ZN8shared_t6uploadEv,"axG",@progbits,_ZN8shared_t6uploadEv,comdat
.align 2
.weak _ZN8shared_t6uploadEv
.type _ZN8shared_t6uploadEv, @function
_ZN8shared_t6uploadEv:
.LFB2383:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq 8(%rdi), %rsi
testq %rsi, %rsi
je .L63
movq (%rdi), %rdi
testq %rdi, %rdi
je .L64
movq 24(%rbx), %rdx
movl $1, %ecx
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L61
.L56:
movl %ebp, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
movq (%rdi), %rcx
movl $0, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebp
.L61:
movq 8(%rbx), %rcx
movq (%rbx), %rdx
movl %ebp, %r9d
movq 24(%rbx), %r8
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L64:
movl $0, %ecx
movq %rsi, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ebp
jmp .L61
.cfi_endproc
.LFE2383:
.size _ZN8shared_t6uploadEv, .-_ZN8shared_t6uploadEv
.section .rodata._ZN8shared_t8downloadEv.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "[shared_t] download of (%p, %p, %lu) failed %d\n"
.section .text._ZN8shared_t8downloadEv,"axG",@progbits,_ZN8shared_t8downloadEv,comdat
.align 2
.weak _ZN8shared_t8downloadEv
.type _ZN8shared_t8downloadEv, @function
_ZN8shared_t8downloadEv:
.LFB2384:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq 8(%rdi), %rdi
testq %rdi, %rdi
je .L72
movq (%rbx), %rsi
testq %rsi, %rsi
je .L73
movq 24(%rbx), %rdx
movl $2, %ecx
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L70
.L65:
movl %ebp, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
movq (%rbx), %rcx
movl $0, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebp
.L70:
movq 8(%rbx), %rcx
movq (%rbx), %rdx
movl %ebp, %r9d
movq 24(%rbx), %r8
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L65
.L73:
movl $0, %ecx
movq %rdi, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ebp
jmp .L70
.cfi_endproc
.LFE2384:
.size _ZN8shared_t8downloadEv, .-_ZN8shared_t8downloadEv
.section .rodata._ZN8shared_t9randomizeEv.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "[shared_t] device_ptr is nullptr for randomize (host:%p, device:%p)\n"
.align 8
.LC11:
.string "[shared_t] create generator failed %d\n"
.align 8
.LC14:
.string "[shared_t] generate failed %d\n"
.align 8
.LC15:
.string "[shared_t] destroy generator failed %d\n"
.section .text._ZN8shared_t9randomizeEv,"axG",@progbits,_ZN8shared_t9randomizeEv,comdat
.align 2
.weak _ZN8shared_t9randomizeEv
.type _ZN8shared_t9randomizeEv, @function
_ZN8shared_t9randomizeEv:
.LFB2385:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
cmpq $0, (%rdi)
je .L82
movq %rsp, %rdi
movl $100, %esi
call curandCreateGenerator@PLT
testl %eax, %eax
jne .L83
movq 16(%rbx), %rdx
movq (%rbx), %rsi
movss .LC12(%rip), %xmm1
movss .LC13(%rip), %xmm0
movq (%rsp), %rdi
call curandGenerateNormal@PLT
testl %eax, %eax
jne .L84
.L78:
movq (%rsp), %rdi
call curandDestroyGenerator@PLT
movl $0, %ebx
testl %eax, %eax
jne .L85
.L74:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L86
movl %ebx, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
movq 8(%rdi), %rdx
movl $0, %ecx
leaq .LC10(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %ebx
jmp .L74
.L83:
movl %eax, %ebx
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L74
.L84:
movl %eax, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L78
.L85:
movl %eax, %ebx
movl %eax, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L74
.L86:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2385:
.size _ZN8shared_t9randomizeEv, .-_ZN8shared_t9randomizeEv
.section .rodata._ZNK8shared_t6deviceEv.str1.8,"aMS",@progbits,1
.align 8
.LC16:
.string "[shared_t] device() has to return nullptr (host:%p, device:%p)\n"
.section .text._ZNK8shared_t6deviceEv,"axG",@progbits,_ZNK8shared_t6deviceEv,comdat
.align 2
.weak _ZNK8shared_t6deviceEv
.type _ZNK8shared_t6deviceEv, @function
_ZNK8shared_t6deviceEv:
.LFB2386:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $0, (%rdi)
je .L90
.L88:
movq (%rbx), %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
movq 8(%rdi), %rdx
movl $0, %ecx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L88
.cfi_endproc
.LFE2386:
.size _ZNK8shared_t6deviceEv, .-_ZNK8shared_t6deviceEv
.section .rodata._ZNK8shared_t4hostEv.str1.8,"aMS",@progbits,1
.align 8
.LC17:
.string "[shared_t] host() has to return nullptr (host:%p, device:%p)\n"
.section .text._ZNK8shared_t4hostEv,"axG",@progbits,_ZNK8shared_t4hostEv,comdat
.align 2
.weak _ZNK8shared_t4hostEv
.type _ZNK8shared_t4hostEv, @function
_ZNK8shared_t4hostEv:
.LFB2387:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $0, 8(%rdi)
je .L94
.L92:
movq 8(%rbx), %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
movq (%rdi), %rcx
movl $0, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L92
.cfi_endproc
.LFE2387:
.size _ZNK8shared_t4hostEv, .-_ZNK8shared_t4hostEv
.section .rodata._ZN9measure_tC2Eb.str1.8,"aMS",@progbits,1
.align 8
.LC18:
.string "[measure_t] create cuda events start:%d end:%d\n"
.align 8
.LC19:
.string "[measure_t] disabling cuda events\n"
.section .text._ZN9measure_tC2Eb,"axG",@progbits,_ZN9measure_tC5Eb,comdat
.align 2
.weak _ZN9measure_tC2Eb
.type _ZN9measure_tC2Eb, @function
_ZN9measure_tC2Eb:
.LFB2390:
.cfi_startproc
endbr64
movb %sil, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testb %sil, %sil
jne .L103
ret
.L103:
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 24(%rdi), %rdi
call cudaEventCreate@PLT
movl %eax, %ebp
leaq 32(%rbx), %rdi
call cudaEventCreate@PLT
movl %eax, %r12d
movl %eax, %ecx
movl %ebp, %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %eax
orl %r12d, %eax
je .L95
testl %ebp, %ebp
je .L97
testl %r12d, %r12d
je .L104
.L97:
testl %ebp, %ebp
jne .L98
testl %r12d, %r12d
je .L98
movq 24(%rbx), %rdi
call cudaEventDestroy@PLT
jmp .L98
.L104:
movq 32(%rbx), %rdi
call cudaEventDestroy@PLT
.L98:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movb $0, (%rbx)
.L95:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2390:
.size _ZN9measure_tC2Eb, .-_ZN9measure_tC2Eb
.weak _ZN9measure_tC1Eb
.set _ZN9measure_tC1Eb,_ZN9measure_tC2Eb
.section .rodata._ZN9measure_tD2Ev.str1.8,"aMS",@progbits,1
.align 8
.LC20:
.string "[measure_t] dispose cuda events start:%d end:%d\n"
.section .text._ZN9measure_tD2Ev,"axG",@progbits,_ZN9measure_tD5Ev,comdat
.align 2
.weak _ZN9measure_tD2Ev
.type _ZN9measure_tD2Ev, @function
_ZN9measure_tD2Ev:
.LFB2393:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2393
endbr64
cmpb $0, (%rdi)
jne .L111
ret
.L111:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq 32(%rdi), %rdi
call cudaEventDestroy@PLT
movl %eax, %ebp
movq 24(%rbx), %rdi
call cudaEventDestroy@PLT
movl %eax, %edx
movl %ebp, %ecx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2393:
.section .gcc_except_table._ZN9measure_tD2Ev,"aG",@progbits,_ZN9measure_tD5Ev,comdat
.LLSDA2393:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2393-.LLSDACSB2393
.LLSDACSB2393:
.LLSDACSE2393:
.section .text._ZN9measure_tD2Ev,"axG",@progbits,_ZN9measure_tD5Ev,comdat
.size _ZN9measure_tD2Ev, .-_ZN9measure_tD2Ev
.weak _ZN9measure_tD1Ev
.set _ZN9measure_tD1Ev,_ZN9measure_tD2Ev
.section .text._ZN9measure_t5startEv,"axG",@progbits,_ZN9measure_t5startEv,comdat
.align 2
.weak _ZN9measure_t5startEv
.type _ZN9measure_t5startEv, @function
_ZN9measure_t5startEv:
.LFB2395:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rbx)
cmpb $0, (%rbx)
jne .L115
.L112:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L115:
.cfi_restore_state
movq 24(%rbx), %rdi
movl $0, %esi
call cudaEventRecord@PLT
jmp .L112
.cfi_endproc
.LFE2395:
.size _ZN9measure_t5startEv, .-_ZN9measure_t5startEv
.section .rodata._ZN9measure_t3endEv.str1.8,"aMS",@progbits,1
.align 8
.LC21:
.string "[measure_t] cuda stop event is failed record:%d sync:%d time:%d\n"
.section .text._ZN9measure_t3endEv,"axG",@progbits,_ZN9measure_t3endEv,comdat
.align 2
.weak _ZN9measure_t3endEv
.type _ZN9measure_t3endEv, @function
_ZN9measure_t3endEv:
.LFB2396:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rcx
movq %rax, 16(%rbx)
subq 8(%rbx), %rcx
movabsq $2361183241434822607, %rdx
movq %rcx, %rax
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 40(%rbx)
cmpb $0, (%rbx)
jne .L121
.L116:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L122
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L121:
.cfi_restore_state
movq 32(%rbx), %rdi
movl $0, %esi
call cudaEventRecord@PLT
movl %eax, %ebp
movq 32(%rbx), %rdi
call cudaEventSynchronize@PLT
movl %eax, %r12d
movl $0x00000000, 4(%rsp)
movq 32(%rbx), %rdx
movq 24(%rbx), %rsi
leaq 4(%rsp), %rdi
call cudaEventElapsedTime@PLT
movl %eax, %r8d
movl %ebp, %eax
orl %r12d, %eax
orl %r8d, %eax
jne .L123
movss .LC22(%rip), %xmm0
mulss 4(%rsp), %xmm0
movss %xmm0, 44(%rbx)
jmp .L116
.L123:
movl %r12d, %ecx
movl %ebp, %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L116
.L122:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2396:
.size _ZN9measure_t3endEv, .-_ZN9measure_t3endEv
.text
.globl _Z12transformCpuPKfPfmm
.type _Z12transformCpuPKfPfmm, @function
_Z12transformCpuPKfPfmm:
.LFB2401:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
imulq %rdx, %rcx
movq %rcx, %rbx
shrq $2, %rbx
cmpq $3, %rcx
jbe .L124
movq %rdi, %r8
movq %rsi, %r9
movq %rdx, %rdi
movq %rdx, %r11
shrq $2, %r11
movq %rdx, %r10
shrq %r10
movl $0, %ecx
.L126:
leaq 0(,%rcx,4), %rax
movl $0, %edx
divq %rdi
movq %rax, %rsi
leaq (%rcx,%rcx), %rax
movl $0, %edx
divq %r10
movq %rdx, %rbp
movq %rcx, %rax
movl $0, %edx
divq %r11
movq %rdi, %rax
imulq %rsi, %rax
leaq (%rax,%rdx,4), %r12
leaq 0(,%r12,4), %rax
leaq 1(%rsi,%rsi), %rdx
imulq %rdi, %rdx
movq %rdx, %rsi
shrq %rsi
addq %rbp, %rsi
movss (%r8,%r12,4), %xmm0
movss %xmm0, (%r9,%rsi,4)
movss 4(%r8,%rax), %xmm0
movss %xmm0, 4(%r9,%rsi,4)
subq %rdi, %rdx
shrq %rdx
addq %rbp, %rdx
movss 8(%r8,%rax), %xmm0
movss %xmm0, (%r9,%rdx,4)
movss 12(%r8,%rax), %xmm0
movss %xmm0, 4(%r9,%rdx,4)
addq $1, %rcx
cmpq %rbx, %rcx
jb .L126
.L124:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2401:
.size _Z12transformCpuPKfPfmm, .-_Z12transformCpuPKfPfmm
.globl _Z40__device_stub__Z15transformKernelPKfPfmmPKfPfmm
.type _Z40__device_stub__Z15transformKernelPKfPfmmPKfPfmm, @function
_Z40__device_stub__Z15transformKernelPKfPfmmPKfPfmm:
.LFB2427:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L133
.L129:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L134
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L133:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15transformKernelPKfPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L129
.L134:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2427:
.size _Z40__device_stub__Z15transformKernelPKfPfmmPKfPfmm, .-_Z40__device_stub__Z15transformKernelPKfPfmmPKfPfmm
.globl _Z15transformKernelPKfPfmm
.type _Z15transformKernelPKfPfmm, @function
_Z15transformKernelPKfPfmm:
.LFB2428:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15transformKernelPKfPfmmPKfPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2428:
.size _Z15transformKernelPKfPfmm, .-_Z15transformKernelPKfPfmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC23:
.string "[warning] matrix will not be printed because sizes are too big\n"
.section .rodata.str1.1
.LC24:
.string "w"
.LC25:
.string "/dev/null"
.LC26:
.string "thread count: %lu\n"
.LC27:
.string "input: \n"
.LC28:
.string "output: \n"
.LC29:
.string "check: \n"
.LC30:
.string "measure device: %f mcs\n"
.LC31:
.string "measure host: %f mcs\n"
.LC32:
.string "compare missmatch on %lu %lu\n"
.LC33:
.string "compare check passed!\n"
.LC34:
.string "input window: \n"
.LC35:
.string "output window: \n"
.LC36:
.string "check window: \n"
.text
.globl main
.type main, @function
main:
.LFB2402:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2402
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset 14, -24
.cfi_offset 12, -32
.cfi_offset 3, -40
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq .LC23(%rip), %rsi
movl $2, %edi
.LEHB0:
call __printf_chk@PLT
leaq .LC24(%rip), %rsi
leaq .LC25(%rip), %rdi
call fopen@PLT
movq %rax, %r14
leaq -240(%rbp), %rdi
movl $1, %edx
movl $35574572, %esi
call _ZN8shared_tC1Emb
.LEHE0:
leaq -208(%rbp), %rdi
movl $1, %edx
movl $35574572, %esi
.LEHB1:
call _ZN8shared_tC1Emb
.LEHE1:
leaq -176(%rbp), %rdi
movl $0, %edx
movl $35574572, %esi
.LEHB2:
call _ZN8shared_tC1Emb
.LEHE2:
leaq -144(%rbp), %rdi
movl $1, %esi
.LEHB3:
call _ZN9measure_tC1Eb
.LEHE3:
leaq -96(%rbp), %rdi
movl $0, %esi
.LEHB4:
call _ZN9measure_tC1Eb
.LEHE4:
leaq -240(%rbp), %rdi
.LEHB5:
call _ZN8shared_t9randomizeEv
testl %eax, %eax
jne .L153
leaq -240(%rbp), %rdi
call _ZN8shared_t8downloadEv
testl %eax, %eax
jne .L154
leaq -208(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rdi
leaq _Z5fZerommm(%rip), %rcx
movl $8444, %edx
movl $4213, %esi
call _Z10fillMatrixPfmmPFfmmmE
leaq -176(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rdi
leaq _Z5fZerommm(%rip), %rcx
movl $8444, %edx
movl $4213, %esi
call _Z10fillMatrixPfmmPFfmmmE
leaq -240(%rbp), %rdi
call _ZN8shared_t6uploadEv
movl $1, %ebx
testl %eax, %eax
jne .L138
leaq -208(%rbp), %rdi
call _ZN8shared_t6uploadEv
testl %eax, %eax
jne .L156
movl $1024, %ebx
movl $8893643, %ecx
.L139:
subq $1, %rbx
cmpq $1, %rbx
je .L140
movq %rcx, %rax
movl $0, %edx
divq %rbx
testq %rdx, %rdx
jne .L139
.L140:
movq %rbx, %rdx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -144(%rbp), %rdi
call _ZN9measure_t5startEv
movl %ebx, -252(%rbp)
movl $1, -248(%rbp)
movl $8893643, %eax
movl $0, %edx
divq %rbx
movl %eax, -264(%rbp)
movl $1, -260(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -252(%rbp), %rdx
movl $1, %ecx
movq -264(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L142
leaq -208(%rbp), %rdi
call _ZNK8shared_t6deviceEv
movq %rax, %r12
leaq -240(%rbp), %rdi
call _ZNK8shared_t6deviceEv
movq %rax, %rdi
movq %rbx, %rcx
movl $4213, %edx
movq %r12, %rsi
call _Z40__device_stub__Z15transformKernelPKfPfmmPKfPfmm
.L142:
leaq -144(%rbp), %rdi
call _ZN9measure_t3endEv
leaq -96(%rbp), %rdi
call _ZN9measure_t5startEv
leaq -176(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rbx
leaq -240(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rdi
movl $8444, %ecx
movl $4213, %edx
movq %rbx, %rsi
call _Z12transformCpuPKfPfmm
leaq -96(%rbp), %rdi
call _ZN9measure_t3endEv
leaq -208(%rbp), %rdi
call _ZN8shared_t8downloadEv
testl %eax, %eax
jne .L157
leaq -240(%rbp), %rdi
call _ZN8shared_t8downloadEv
movl %eax, %ebx
testl %eax, %eax
jne .L158
leaq .LC27(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq -240(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rsi
movl $8444, %ecx
movl $4213, %edx
movq %r14, %rdi
call _Z11printMatrixP8_IO_FILEPfmm
leaq .LC28(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq -208(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rsi
movl $16888, %ecx
movl $2106, %edx
movq %r14, %rdi
call _Z11printMatrixP8_IO_FILEPfmm
leaq .LC29(%rip), %rdx
movl $2, %esi
movq %r14, %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq -176(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rsi
movl $16888, %ecx
movl $2106, %edx
movq %r14, %rdi
call _Z11printMatrixP8_IO_FILEPfmm
pxor %xmm0, %xmm0
cvtss2sd -100(%rbp), %xmm0
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -56(%rbp), %xmm0
leaq .LC31(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq -176(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %r12
leaq -208(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rdi
movl $16888, %ecx
movl $2106, %edx
movq %r12, %rsi
call _Z7comparePfS_mm
movq %rdx, %rcx
cmpq $16887, %rdx
jbe .L164
cmpq $2105, %rax
ja .L143
.L164:
movq %rax, %rdx
leaq .LC32(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L145
.L143:
leaq .LC33(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L145:
leaq .LC34(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -240(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rsi
subq $8, %rsp
pushq $1
movl $4, %r9d
movl $0, %r8d
movl $0, %ecx
movl $2106, %edx
movq stdout(%rip), %rdi
.cfi_escape 0x2e,0x10
call _Z11printWindowP8_IO_FILEPfmmmmm
addq $16, %rsp
leaq .LC35(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
leaq -208(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rsi
subq $8, %rsp
pushq $2
movl $2, %r9d
movl $0, %r8d
movl $0, %ecx
movl $2106, %edx
movq stdout(%rip), %rdi
.cfi_escape 0x2e,0x10
call _Z11printWindowP8_IO_FILEPfmmmmm
addq $16, %rsp
leaq .LC36(%rip), %rsi
movl $2, %edi
movl $0, %eax
.cfi_escape 0x2e,0
call __printf_chk@PLT
leaq -176(%rbp), %rdi
call _ZNK8shared_t4hostEv
movq %rax, %rsi
subq $8, %rsp
pushq $2
movl $2, %r9d
movl $0, %r8d
movl $0, %ecx
movl $2106, %edx
movq stdout(%rip), %rdi
.cfi_escape 0x2e,0x10
call _Z11printWindowP8_IO_FILEPfmmmmm
.LEHE5:
addq $16, %rsp
jmp .L138
.L153:
movl $4, %ebx
.L138:
leaq -96(%rbp), %rdi
call _ZN9measure_tD1Ev
leaq -144(%rbp), %rdi
call _ZN9measure_tD1Ev
leaq -176(%rbp), %rdi
call _ZN8shared_tD1Ev
leaq -208(%rbp), %rdi
call _ZN8shared_tD1Ev
leaq -240(%rbp), %rdi
call _ZN8shared_tD1Ev
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L167
movl %ebx, %eax
leaq -24(%rbp), %rsp
popq %rbx
popq %r12
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L154:
.cfi_restore_state
movl $3, %ebx
jmp .L138
.L156:
movl $1, %ebx
jmp .L138
.L157:
movl $2, %ebx
jmp .L138
.L158:
movl $2, %ebx
jmp .L138
.L163:
endbr64
movq %rax, %rbx
leaq -96(%rbp), %rdi
call _ZN9measure_tD1Ev
.L147:
leaq -144(%rbp), %rdi
call _ZN9measure_tD1Ev
.L148:
leaq -176(%rbp), %rdi
call _ZN8shared_tD1Ev
.L149:
leaq -208(%rbp), %rdi
call _ZN8shared_tD1Ev
.L150:
leaq -240(%rbp), %rdi
call _ZN8shared_tD1Ev
movq -40(%rbp), %rax
subq %fs:40, %rax
je .L151
call __stack_chk_fail@PLT
.L162:
endbr64
movq %rax, %rbx
jmp .L147
.L161:
endbr64
movq %rax, %rbx
jmp .L148
.L160:
endbr64
movq %rax, %rbx
jmp .L149
.L159:
endbr64
movq %rax, %rbx
jmp .L150
.L151:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L167:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2402:
.section .gcc_except_table,"a",@progbits
.LLSDA2402:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2402-.LLSDACSB2402
.LLSDACSB2402:
.uleb128 .LEHB0-.LFB2402
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2402
.uleb128 .LEHE1-.LEHB1
.uleb128 .L159-.LFB2402
.uleb128 0
.uleb128 .LEHB2-.LFB2402
.uleb128 .LEHE2-.LEHB2
.uleb128 .L160-.LFB2402
.uleb128 0
.uleb128 .LEHB3-.LFB2402
.uleb128 .LEHE3-.LEHB3
.uleb128 .L161-.LFB2402
.uleb128 0
.uleb128 .LEHB4-.LFB2402
.uleb128 .LEHE4-.LEHB4
.uleb128 .L162-.LFB2402
.uleb128 0
.uleb128 .LEHB5-.LFB2402
.uleb128 .LEHE5-.LEHB5
.uleb128 .L163-.LFB2402
.uleb128 0
.uleb128 .LEHB6-.LFB2402
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE2402:
.text
.size main, .-main
.section .rodata.str1.1
.LC37:
.string "_Z15transformKernelPKfPfmm"
.LC38:
.string "precalc_xorwow_matrix"
.LC39:
.string "precalc_xorwow_offset_matrix"
.LC40:
.string "mrg32k3aM1"
.LC41:
.string "mrg32k3aM2"
.LC42:
.string "mrg32k3aM1SubSeq"
.LC43:
.string "mrg32k3aM2SubSeq"
.LC44:
.string "mrg32k3aM1Seq"
.LC45:
.string "mrg32k3aM2Seq"
.LC46:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2430:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC37(%rip), %rdx
movq %rdx, %rcx
leaq _Z15transformKernelPKfPfmm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC38(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC39(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC40(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC41(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC42(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC43(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC44(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC45(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC46(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2430:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC12:
.long 1101004800
.align 4
.LC13:
.long 1109393408
.align 4
.LC22:
.long 1148846080
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <curand_kernel.h>
#include <chrono>
#define host_t float
#define device_t float*
#define t_size sizeof(host_t)
#define size_t unsigned long
#define time_point_t std::chrono::time_point<std::chrono::high_resolution_clock>
template<typename A, typename B>
struct pair_t { A first; B second; };
host_t fZero(size_t x, size_t y, size_t w) { return 0; }
host_t fIndex(size_t x, size_t y, size_t w) { return (y * w + x); }
void printMatrix(FILE* file, host_t* matrix, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
void fillMatrix(host_t* matrix, size_t width, size_t height, host_t(*function)(size_t, size_t, size_t)) {
for (size_t y = 0; y < height; y++)
for (size_t x = 0; x < width; x++)
matrix[y * width + x] = function(x, y, width);
}
pair_t<size_t, size_t> compare(host_t* a, host_t* b, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++) {
if (a[y * width + x] != b[y * width + x]) {
printf("missmatch %f %f\n", a[y * width + x], b[y * width + x]);
return pair_t<size_t, size_t>{x, y};
}
}
}
return pair_t<size_t, size_t>{width, height};
}
void printWindow(FILE* file, host_t* matrix, size_t width, size_t w_start, size_t h_start, size_t w_width, size_t w_height) {
for (size_t y = w_start; y < w_height; y++) {
for (size_t x = h_start; x < w_width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
struct shared_t {
device_t device_ptr;
host_t *host_ptr;
size_t count;
size_t bytes;
shared_t(size_t element_count, bool cuda):
host_ptr{(host_t*) malloc(element_count * t_size)},
device_ptr{nullptr},
count{element_count},
bytes{element_count * t_size} {
if (cuda) {
cudaMalloc(&device_ptr, bytes);
}
printf("[shared_t] host:%p device:%p count:%lu bytes:%lu\n",
host_ptr, device_ptr, element_count, bytes);
}
~shared_t() {
printf("[shared_t] dispose %p %p\n", host_ptr, device_ptr);
if (host_ptr != nullptr)
free(host_ptr);
if (device_ptr != nullptr)
cudaFree(device_ptr);
}
int sync(cudaMemcpyKind kind) {
if (host_ptr == nullptr) {
printf("[shared_t] host_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 1;
}
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 2;
}
if (kind == cudaMemcpyDeviceToHost)
return cudaMemcpy(host_ptr, device_ptr, bytes, kind);
else
return cudaMemcpy(device_ptr, host_ptr, bytes, kind);
}
int upload() {
auto result = sync(cudaMemcpyHostToDevice);
if (result == cudaSuccess)
return 0;
printf("[shared_t] upload of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int download() {
auto result = sync(cudaMemcpyDeviceToHost);
if (result == cudaSuccess)
return 0;
printf("[shared_t] download of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int randomize() {
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr for randomize (host:%p, device:%p)\n",
host_ptr, device_ptr);
return 1;
}
curandGenerator_t generator;
auto r_gen_create = curandCreateGenerator(&generator, CURAND_RNG_PSEUDO_DEFAULT);
if (r_gen_create != CURAND_STATUS_SUCCESS) {
printf("[shared_t] create generator failed %d\n", r_gen_create);
return r_gen_create;
}
auto r_gen = curandGenerateNormal(generator, device_ptr, count, 40, 20);
if (r_gen != CURAND_STATUS_SUCCESS) {
printf("[shared_t] generate failed %d\n", r_gen);
}
auto r_destroy = curandDestroyGenerator(generator);
if (r_destroy != CURAND_STATUS_SUCCESS) {
printf("[shared_t] destroy generator failed %d\n", r_destroy);
return r_destroy;
}
return 0;
}
device_t device() const {
if (device_ptr == nullptr)
printf("[shared_t] device() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return device_ptr;
}
host_t* host() const {
if (host_ptr == nullptr)
printf("[shared_t] host() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return host_ptr;
}
};
struct measure_t {
bool use_cuda;
time_point_t tp_start;
time_point_t tp_end;
cudaEvent_t e_start;
cudaEvent_t e_end;
float mcs_value;
float cuda_mcs_value;
measure_t(bool cuda):
use_cuda{cuda} {
if (use_cuda) {
auto r_start = cudaEventCreate(&e_start);
auto r_end = cudaEventCreate(&e_end);
printf("[measure_t] create cuda events start:%d end:%d\n", r_start, r_end);
if (r_start != cudaSuccess || r_end != cudaSuccess) {
if (r_start != cudaSuccess && r_end == cudaSuccess)
cudaEventDestroy(e_end);
if (r_start == cudaSuccess && r_end != cudaSuccess)
cudaEventDestroy(e_start);
printf("[measure_t] disabling cuda events\n");
use_cuda = false;
}
}
}
~measure_t() {
if (use_cuda) {
auto r_end = cudaEventDestroy(e_end);
auto r_start = cudaEventDestroy(e_start);
printf("[measure_t] dispose cuda events start:%d end:%d\n", r_start, r_end);
}
}
void start() {
tp_start = std::chrono::high_resolution_clock::now();
if (use_cuda)
cudaEventRecord(e_start, 0);
}
void end() {
tp_end = std::chrono::high_resolution_clock::now();
mcs_value = std::chrono::duration_cast<std::chrono::microseconds>(tp_end - tp_start).count() * 1.0;
if (use_cuda) {
auto r_record = cudaEventRecord(e_end, 0);
auto r_sync = cudaEventSynchronize(e_end);
float elapsed = 0;
auto r_time = cudaEventElapsedTime(&elapsed, e_start, e_end);
if (r_record != cudaSuccess || r_sync != cudaSuccess || r_time != cudaSuccess) {
printf("[measure_t] cuda stop event is failed record:%d sync:%d time:%d\n",
r_record, r_sync, r_time);
return;
}
cuda_mcs_value = elapsed * 1000.0;
}
}
float mcs() const { return mcs_value; }
float cuda_mcs() const { return cuda_mcs_value; }
float ms() const { return mcs_value / 1000.0; }
float cuda_ms() { return cuda_mcs_value / 1000.0; }
};
__global__ void transformKernel(const device_t input, device_t output, size_t width, size_t threads) {
const size_t i = blockIdx.x * threads + threadIdx.x;
/* *block* vector index is equal to linear index */
/* but *block* index is 4 linear indecices */
const size_t y = i * 4 / width;
/* every *block* index is 4 linear indices */
const size_t x = 4 * (i % (width / 4));
/* every input vector is 2 output vectors */
const size_t oy = y * 2;
/* every *block* index is 2 linear indices */
const size_t ox = i * 2 % (width / 2);
/* aligned view into *block* */
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
__host__ void transformCpu(const host_t* input, host_t* output, size_t width, size_t height) {
const size_t iter = width * height / 4;
for (size_t i = 0; i < iter; i++) {
const size_t y = i * 4 / width;
const size_t x = 4 * (i % (width / 4));
const size_t oy = y * 2;
const size_t ox = i * 2 % (width / 2);
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
}
int main() {
const size_t height = 8444;
const size_t width = 4213;
const size_t count = height * width;
const size_t o_width = width / 2;
const size_t o_height = height * 2;
FILE* matrix_file = stdout;
if (width > 32 || height > 32) {
printf("[warning] matrix will not be printed because sizes are too big\n");
matrix_file = fopen("/dev/null", "w");
}
shared_t input{count, true};
shared_t output{count, true};
shared_t check{count, false};
measure_t measure{true};
measure_t cpu_measure{false};
/* generate random numbers in device memory */
if (input.randomize() != 0)
return 4;
/* copy it to host memory */
if (input.download() != 0)
return 3;
fillMatrix(output.host(), width, height, fZero);
fillMatrix(check.host(), width, height, fZero);
/* copy data into the device */
if (input.upload() != 0)
return 1;
/* output copy isn't necessary */
if (output.upload() != 0)
return 1;
/* calculate kernel start params */
const size_t iter_count = count / 4;
size_t thread_count = iter_count < 1024 ? iter_count : 1024;
for (; thread_count >= 2; thread_count--)
if (iter_count % thread_count == 0)
break;
printf("thread count: %lu\n", thread_count);
/* execute kernel on the device */
measure.start();
transformKernel<<<iter_count / thread_count, thread_count>>>(
input.device(),
output.device(),
width,
thread_count
);
measure.end();
cpu_measure.start();
transformCpu(input.host(), check.host(), width, height);
cpu_measure.end();
/* copy data from the device */
if (output.download() != 0)
return 2;
/* input copy isn't necessary */
if (input.download() != 0)
return 2;
fprintf(matrix_file, "input: \n");
printMatrix(matrix_file, input.host(), width, height);
fprintf(matrix_file, "output: \n");
printMatrix(matrix_file, output.host(), o_width, o_height);
fprintf(matrix_file, "check: \n");
printMatrix(matrix_file, check.host(), o_width, o_height);
printf("measure device: %f mcs\n", measure.cuda_mcs());
printf("measure host: %f mcs\n", cpu_measure.mcs());
auto result = compare(output.host(), check.host(), o_width, o_height);
if (result.first < o_width || result.second < o_height) {
printf("compare missmatch on %lu %lu\n", result.first, result.second);
} else {
printf("compare check passed!\n");
}
printf("input window: \n");
printWindow(stdout, input.host(), o_width, 0, 0, 4, 1);
printf("output window: \n");
printWindow(stdout, output.host(), o_width, 0, 0, 2, 2);
printf("check window: \n");
printWindow(stdout, check.host(), o_width, 0, 0, 2, 2);
/* all shared_t objects is allocated on the stack */
/* so, destructor will automatically free all memory */
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand_kernel.h>
#include <chrono>
#define host_t float
#define device_t float*
#define t_size sizeof(host_t)
#define size_t unsigned long
#define time_point_t std::chrono::time_point<std::chrono::high_resolution_clock>
template<typename A, typename B>
struct pair_t { A first; B second; };
host_t fZero(size_t x, size_t y, size_t w) { return 0; }
host_t fIndex(size_t x, size_t y, size_t w) { return (y * w + x); }
void printMatrix(FILE* file, host_t* matrix, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
void fillMatrix(host_t* matrix, size_t width, size_t height, host_t(*function)(size_t, size_t, size_t)) {
for (size_t y = 0; y < height; y++)
for (size_t x = 0; x < width; x++)
matrix[y * width + x] = function(x, y, width);
}
pair_t<size_t, size_t> compare(host_t* a, host_t* b, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++) {
if (a[y * width + x] != b[y * width + x]) {
printf("missmatch %f %f\n", a[y * width + x], b[y * width + x]);
return pair_t<size_t, size_t>{x, y};
}
}
}
return pair_t<size_t, size_t>{width, height};
}
void printWindow(FILE* file, host_t* matrix, size_t width, size_t w_start, size_t h_start, size_t w_width, size_t w_height) {
for (size_t y = w_start; y < w_height; y++) {
for (size_t x = h_start; x < w_width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
struct shared_t {
device_t device_ptr;
host_t *host_ptr;
size_t count;
size_t bytes;
shared_t(size_t element_count, bool cuda):
host_ptr{(host_t*) malloc(element_count * t_size)},
device_ptr{nullptr},
count{element_count},
bytes{element_count * t_size} {
if (cuda) {
hipMalloc(&device_ptr, bytes);
}
printf("[shared_t] host:%p device:%p count:%lu bytes:%lu\n",
host_ptr, device_ptr, element_count, bytes);
}
~shared_t() {
printf("[shared_t] dispose %p %p\n", host_ptr, device_ptr);
if (host_ptr != nullptr)
free(host_ptr);
if (device_ptr != nullptr)
hipFree(device_ptr);
}
int sync(hipMemcpyKind kind) {
if (host_ptr == nullptr) {
printf("[shared_t] host_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 1;
}
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 2;
}
if (kind == hipMemcpyDeviceToHost)
return hipMemcpy(host_ptr, device_ptr, bytes, kind);
else
return hipMemcpy(device_ptr, host_ptr, bytes, kind);
}
int upload() {
auto result = sync(hipMemcpyHostToDevice);
if (result == hipSuccess)
return 0;
printf("[shared_t] upload of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int download() {
auto result = sync(hipMemcpyDeviceToHost);
if (result == hipSuccess)
return 0;
printf("[shared_t] download of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int randomize() {
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr for randomize (host:%p, device:%p)\n",
host_ptr, device_ptr);
return 1;
}
hiprandGenerator_t generator;
auto r_gen_create = hiprandCreateGenerator(&generator, HIPRAND_RNG_PSEUDO_DEFAULT);
if (r_gen_create != HIPRAND_STATUS_SUCCESS) {
printf("[shared_t] create generator failed %d\n", r_gen_create);
return r_gen_create;
}
auto r_gen = hiprandGenerateNormal(generator, device_ptr, count, 40, 20);
if (r_gen != HIPRAND_STATUS_SUCCESS) {
printf("[shared_t] generate failed %d\n", r_gen);
}
auto r_destroy = hiprandDestroyGenerator(generator);
if (r_destroy != HIPRAND_STATUS_SUCCESS) {
printf("[shared_t] destroy generator failed %d\n", r_destroy);
return r_destroy;
}
return 0;
}
device_t device() const {
if (device_ptr == nullptr)
printf("[shared_t] device() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return device_ptr;
}
host_t* host() const {
if (host_ptr == nullptr)
printf("[shared_t] host() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return host_ptr;
}
};
struct measure_t {
bool use_cuda;
time_point_t tp_start;
time_point_t tp_end;
hipEvent_t e_start;
hipEvent_t e_end;
float mcs_value;
float cuda_mcs_value;
measure_t(bool cuda):
use_cuda{cuda} {
if (use_cuda) {
auto r_start = hipEventCreate(&e_start);
auto r_end = hipEventCreate(&e_end);
printf("[measure_t] create cuda events start:%d end:%d\n", r_start, r_end);
if (r_start != hipSuccess || r_end != hipSuccess) {
if (r_start != hipSuccess && r_end == hipSuccess)
hipEventDestroy(e_end);
if (r_start == hipSuccess && r_end != hipSuccess)
hipEventDestroy(e_start);
printf("[measure_t] disabling cuda events\n");
use_cuda = false;
}
}
}
~measure_t() {
if (use_cuda) {
auto r_end = hipEventDestroy(e_end);
auto r_start = hipEventDestroy(e_start);
printf("[measure_t] dispose cuda events start:%d end:%d\n", r_start, r_end);
}
}
void start() {
tp_start = std::chrono::high_resolution_clock::now();
if (use_cuda)
hipEventRecord(e_start, 0);
}
void end() {
tp_end = std::chrono::high_resolution_clock::now();
mcs_value = std::chrono::duration_cast<std::chrono::microseconds>(tp_end - tp_start).count() * 1.0;
if (use_cuda) {
auto r_record = hipEventRecord(e_end, 0);
auto r_sync = hipEventSynchronize(e_end);
float elapsed = 0;
auto r_time = hipEventElapsedTime(&elapsed, e_start, e_end);
if (r_record != hipSuccess || r_sync != hipSuccess || r_time != hipSuccess) {
printf("[measure_t] cuda stop event is failed record:%d sync:%d time:%d\n",
r_record, r_sync, r_time);
return;
}
cuda_mcs_value = elapsed * 1000.0;
}
}
float mcs() const { return mcs_value; }
float cuda_mcs() const { return cuda_mcs_value; }
float ms() const { return mcs_value / 1000.0; }
float cuda_ms() { return cuda_mcs_value / 1000.0; }
};
__global__ void transformKernel(const device_t input, device_t output, size_t width, size_t threads) {
const size_t i = blockIdx.x * threads + threadIdx.x;
/* *block* vector index is equal to linear index */
/* but *block* index is 4 linear indecices */
const size_t y = i * 4 / width;
/* every *block* index is 4 linear indices */
const size_t x = 4 * (i % (width / 4));
/* every input vector is 2 output vectors */
const size_t oy = y * 2;
/* every *block* index is 2 linear indices */
const size_t ox = i * 2 % (width / 2);
/* aligned view into *block* */
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
__host__ void transformCpu(const host_t* input, host_t* output, size_t width, size_t height) {
const size_t iter = width * height / 4;
for (size_t i = 0; i < iter; i++) {
const size_t y = i * 4 / width;
const size_t x = 4 * (i % (width / 4));
const size_t oy = y * 2;
const size_t ox = i * 2 % (width / 2);
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
}
int main() {
const size_t height = 8444;
const size_t width = 4213;
const size_t count = height * width;
const size_t o_width = width / 2;
const size_t o_height = height * 2;
FILE* matrix_file = stdout;
if (width > 32 || height > 32) {
printf("[warning] matrix will not be printed because sizes are too big\n");
matrix_file = fopen("/dev/null", "w");
}
shared_t input{count, true};
shared_t output{count, true};
shared_t check{count, false};
measure_t measure{true};
measure_t cpu_measure{false};
/* generate random numbers in device memory */
if (input.randomize() != 0)
return 4;
/* copy it to host memory */
if (input.download() != 0)
return 3;
fillMatrix(output.host(), width, height, fZero);
fillMatrix(check.host(), width, height, fZero);
/* copy data into the device */
if (input.upload() != 0)
return 1;
/* output copy isn't necessary */
if (output.upload() != 0)
return 1;
/* calculate kernel start params */
const size_t iter_count = count / 4;
size_t thread_count = iter_count < 1024 ? iter_count : 1024;
for (; thread_count >= 2; thread_count--)
if (iter_count % thread_count == 0)
break;
printf("thread count: %lu\n", thread_count);
/* execute kernel on the device */
measure.start();
transformKernel<<<iter_count / thread_count, thread_count>>>(
input.device(),
output.device(),
width,
thread_count
);
measure.end();
cpu_measure.start();
transformCpu(input.host(), check.host(), width, height);
cpu_measure.end();
/* copy data from the device */
if (output.download() != 0)
return 2;
/* input copy isn't necessary */
if (input.download() != 0)
return 2;
fprintf(matrix_file, "input: \n");
printMatrix(matrix_file, input.host(), width, height);
fprintf(matrix_file, "output: \n");
printMatrix(matrix_file, output.host(), o_width, o_height);
fprintf(matrix_file, "check: \n");
printMatrix(matrix_file, check.host(), o_width, o_height);
printf("measure device: %f mcs\n", measure.cuda_mcs());
printf("measure host: %f mcs\n", cpu_measure.mcs());
auto result = compare(output.host(), check.host(), o_width, o_height);
if (result.first < o_width || result.second < o_height) {
printf("compare missmatch on %lu %lu\n", result.first, result.second);
} else {
printf("compare check passed!\n");
}
printf("input window: \n");
printWindow(stdout, input.host(), o_width, 0, 0, 4, 1);
printf("output window: \n");
printWindow(stdout, output.host(), o_width, 0, 0, 2, 2);
printf("check window: \n");
printWindow(stdout, check.host(), o_width, 0, 0, 2, 2);
/* all shared_t objects is allocated on the stack */
/* so, destructor will automatically free all memory */
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand_kernel.h>
#include <chrono>
#define host_t float
#define device_t float*
#define t_size sizeof(host_t)
#define size_t unsigned long
#define time_point_t std::chrono::time_point<std::chrono::high_resolution_clock>
template<typename A, typename B>
struct pair_t { A first; B second; };
host_t fZero(size_t x, size_t y, size_t w) { return 0; }
host_t fIndex(size_t x, size_t y, size_t w) { return (y * w + x); }
void printMatrix(FILE* file, host_t* matrix, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
void fillMatrix(host_t* matrix, size_t width, size_t height, host_t(*function)(size_t, size_t, size_t)) {
for (size_t y = 0; y < height; y++)
for (size_t x = 0; x < width; x++)
matrix[y * width + x] = function(x, y, width);
}
pair_t<size_t, size_t> compare(host_t* a, host_t* b, size_t width, size_t height) {
for (size_t y = 0; y < height; y++) {
for (size_t x = 0; x < width; x++) {
if (a[y * width + x] != b[y * width + x]) {
printf("missmatch %f %f\n", a[y * width + x], b[y * width + x]);
return pair_t<size_t, size_t>{x, y};
}
}
}
return pair_t<size_t, size_t>{width, height};
}
void printWindow(FILE* file, host_t* matrix, size_t width, size_t w_start, size_t h_start, size_t w_width, size_t w_height) {
for (size_t y = w_start; y < w_height; y++) {
for (size_t x = h_start; x < w_width; x++)
fprintf(file, "%03.0f ", matrix[y * width + x]);
fprintf(file, "\n");
}
fprintf(file, "\n");
}
struct shared_t {
device_t device_ptr;
host_t *host_ptr;
size_t count;
size_t bytes;
shared_t(size_t element_count, bool cuda):
host_ptr{(host_t*) malloc(element_count * t_size)},
device_ptr{nullptr},
count{element_count},
bytes{element_count * t_size} {
if (cuda) {
hipMalloc(&device_ptr, bytes);
}
printf("[shared_t] host:%p device:%p count:%lu bytes:%lu\n",
host_ptr, device_ptr, element_count, bytes);
}
~shared_t() {
printf("[shared_t] dispose %p %p\n", host_ptr, device_ptr);
if (host_ptr != nullptr)
free(host_ptr);
if (device_ptr != nullptr)
hipFree(device_ptr);
}
int sync(hipMemcpyKind kind) {
if (host_ptr == nullptr) {
printf("[shared_t] host_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 1;
}
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr (host:%p, device:%p)\n", host_ptr, device_ptr);
return 2;
}
if (kind == hipMemcpyDeviceToHost)
return hipMemcpy(host_ptr, device_ptr, bytes, kind);
else
return hipMemcpy(device_ptr, host_ptr, bytes, kind);
}
int upload() {
auto result = sync(hipMemcpyHostToDevice);
if (result == hipSuccess)
return 0;
printf("[shared_t] upload of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int download() {
auto result = sync(hipMemcpyDeviceToHost);
if (result == hipSuccess)
return 0;
printf("[shared_t] download of (%p, %p, %lu) failed %d\n",
device_ptr, host_ptr, bytes, result);
return result;
}
int randomize() {
if (device_ptr == nullptr) {
printf("[shared_t] device_ptr is nullptr for randomize (host:%p, device:%p)\n",
host_ptr, device_ptr);
return 1;
}
hiprandGenerator_t generator;
auto r_gen_create = hiprandCreateGenerator(&generator, HIPRAND_RNG_PSEUDO_DEFAULT);
if (r_gen_create != HIPRAND_STATUS_SUCCESS) {
printf("[shared_t] create generator failed %d\n", r_gen_create);
return r_gen_create;
}
auto r_gen = hiprandGenerateNormal(generator, device_ptr, count, 40, 20);
if (r_gen != HIPRAND_STATUS_SUCCESS) {
printf("[shared_t] generate failed %d\n", r_gen);
}
auto r_destroy = hiprandDestroyGenerator(generator);
if (r_destroy != HIPRAND_STATUS_SUCCESS) {
printf("[shared_t] destroy generator failed %d\n", r_destroy);
return r_destroy;
}
return 0;
}
device_t device() const {
if (device_ptr == nullptr)
printf("[shared_t] device() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return device_ptr;
}
host_t* host() const {
if (host_ptr == nullptr)
printf("[shared_t] host() has to return nullptr (host:%p, device:%p)\n",
host_ptr, device_ptr);
return host_ptr;
}
};
struct measure_t {
bool use_cuda;
time_point_t tp_start;
time_point_t tp_end;
hipEvent_t e_start;
hipEvent_t e_end;
float mcs_value;
float cuda_mcs_value;
measure_t(bool cuda):
use_cuda{cuda} {
if (use_cuda) {
auto r_start = hipEventCreate(&e_start);
auto r_end = hipEventCreate(&e_end);
printf("[measure_t] create cuda events start:%d end:%d\n", r_start, r_end);
if (r_start != hipSuccess || r_end != hipSuccess) {
if (r_start != hipSuccess && r_end == hipSuccess)
hipEventDestroy(e_end);
if (r_start == hipSuccess && r_end != hipSuccess)
hipEventDestroy(e_start);
printf("[measure_t] disabling cuda events\n");
use_cuda = false;
}
}
}
~measure_t() {
if (use_cuda) {
auto r_end = hipEventDestroy(e_end);
auto r_start = hipEventDestroy(e_start);
printf("[measure_t] dispose cuda events start:%d end:%d\n", r_start, r_end);
}
}
void start() {
tp_start = std::chrono::high_resolution_clock::now();
if (use_cuda)
hipEventRecord(e_start, 0);
}
void end() {
tp_end = std::chrono::high_resolution_clock::now();
mcs_value = std::chrono::duration_cast<std::chrono::microseconds>(tp_end - tp_start).count() * 1.0;
if (use_cuda) {
auto r_record = hipEventRecord(e_end, 0);
auto r_sync = hipEventSynchronize(e_end);
float elapsed = 0;
auto r_time = hipEventElapsedTime(&elapsed, e_start, e_end);
if (r_record != hipSuccess || r_sync != hipSuccess || r_time != hipSuccess) {
printf("[measure_t] cuda stop event is failed record:%d sync:%d time:%d\n",
r_record, r_sync, r_time);
return;
}
cuda_mcs_value = elapsed * 1000.0;
}
}
float mcs() const { return mcs_value; }
float cuda_mcs() const { return cuda_mcs_value; }
float ms() const { return mcs_value / 1000.0; }
float cuda_ms() { return cuda_mcs_value / 1000.0; }
};
__global__ void transformKernel(const device_t input, device_t output, size_t width, size_t threads) {
const size_t i = blockIdx.x * threads + threadIdx.x;
/* *block* vector index is equal to linear index */
/* but *block* index is 4 linear indecices */
const size_t y = i * 4 / width;
/* every *block* index is 4 linear indices */
const size_t x = 4 * (i % (width / 4));
/* every input vector is 2 output vectors */
const size_t oy = y * 2;
/* every *block* index is 2 linear indices */
const size_t ox = i * 2 % (width / 2);
/* aligned view into *block* */
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
__host__ void transformCpu(const host_t* input, host_t* output, size_t width, size_t height) {
const size_t iter = width * height / 4;
for (size_t i = 0; i < iter; i++) {
const size_t y = i * 4 / width;
const size_t x = 4 * (i % (width / 4));
const size_t oy = y * 2;
const size_t ox = i * 2 % (width / 2);
output[(1 + oy) * width / 2 + ox + 0] = input[y * width + x + 0];
output[(1 + oy) * width / 2 + ox + 1] = input[y * width + x + 1];
output[(0 + oy) * width / 2 + ox + 0] = input[y * width + x + 2];
output[(0 + oy) * width / 2 + ox + 1] = input[y * width + x + 3];
}
}
int main() {
const size_t height = 8444;
const size_t width = 4213;
const size_t count = height * width;
const size_t o_width = width / 2;
const size_t o_height = height * 2;
FILE* matrix_file = stdout;
if (width > 32 || height > 32) {
printf("[warning] matrix will not be printed because sizes are too big\n");
matrix_file = fopen("/dev/null", "w");
}
shared_t input{count, true};
shared_t output{count, true};
shared_t check{count, false};
measure_t measure{true};
measure_t cpu_measure{false};
/* generate random numbers in device memory */
if (input.randomize() != 0)
return 4;
/* copy it to host memory */
if (input.download() != 0)
return 3;
fillMatrix(output.host(), width, height, fZero);
fillMatrix(check.host(), width, height, fZero);
/* copy data into the device */
if (input.upload() != 0)
return 1;
/* output copy isn't necessary */
if (output.upload() != 0)
return 1;
/* calculate kernel start params */
const size_t iter_count = count / 4;
size_t thread_count = iter_count < 1024 ? iter_count : 1024;
for (; thread_count >= 2; thread_count--)
if (iter_count % thread_count == 0)
break;
printf("thread count: %lu\n", thread_count);
/* execute kernel on the device */
measure.start();
transformKernel<<<iter_count / thread_count, thread_count>>>(
input.device(),
output.device(),
width,
thread_count
);
measure.end();
cpu_measure.start();
transformCpu(input.host(), check.host(), width, height);
cpu_measure.end();
/* copy data from the device */
if (output.download() != 0)
return 2;
/* input copy isn't necessary */
if (input.download() != 0)
return 2;
fprintf(matrix_file, "input: \n");
printMatrix(matrix_file, input.host(), width, height);
fprintf(matrix_file, "output: \n");
printMatrix(matrix_file, output.host(), o_width, o_height);
fprintf(matrix_file, "check: \n");
printMatrix(matrix_file, check.host(), o_width, o_height);
printf("measure device: %f mcs\n", measure.cuda_mcs());
printf("measure host: %f mcs\n", cpu_measure.mcs());
auto result = compare(output.host(), check.host(), o_width, o_height);
if (result.first < o_width || result.second < o_height) {
printf("compare missmatch on %lu %lu\n", result.first, result.second);
} else {
printf("compare check passed!\n");
}
printf("input window: \n");
printWindow(stdout, input.host(), o_width, 0, 0, 4, 1);
printf("output window: \n");
printWindow(stdout, output.host(), o_width, 0, 0, 2, 2);
printf("check window: \n");
printWindow(stdout, check.host(), o_width, 0, 0, 2, 2);
/* all shared_t objects is allocated on the stack */
/* so, destructor will automatically free all memory */
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15transformKernelPKfPfmm
.globl _Z15transformKernelPKfPfmm
.p2align 8
.type _Z15transformKernelPKfPfmm,@function
_Z15transformKernelPKfPfmm:
s_load_b128 s[4:7], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s6, v[0:1]
v_mov_b32_e32 v0, v3
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s7, v[0:1]
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v7, s5, v5
v_cmpx_ne_u64_e32 0, v[6:7]
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v0, s4
v_cvt_f32_u32_e32 v1, s5
s_sub_u32 s2, 0, s4
s_subb_u32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v1, 0x4f800000, v0
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x2f800000, v0
v_trunc_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v0, v1, 0xcf800000, v0
v_cvt_u32_f32_e32 v1, v1
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s2, v1
v_mul_hi_u32 v7, s2, v0
v_mul_lo_u32 v8, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v7, v6
v_mul_lo_u32 v7, s2, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v1, v7
v_mul_lo_u32 v7, v1, v7
v_mul_hi_u32 v12, v1, v6
v_mul_lo_u32 v6, v1, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, s2, v0
v_mul_lo_u32 v8, s6, v0
v_mul_lo_u32 v7, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, s2, v0
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v0, v7
v_mul_lo_u32 v9, v0, v6
v_mul_hi_u32 v10, v0, v6
v_mul_hi_u32 v11, v1, v7
v_mul_lo_u32 v7, v1, v7
v_mul_hi_u32 v12, v1, v6
v_mul_lo_u32 v6, v1, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v10, vcc_lo, v1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v11, v4, v8
v_mad_u64_u32 v[6:7], null, v5, v8, 0
v_mad_u64_u32 v[0:1], null, v4, v10, 0
v_mad_u64_u32 v[8:9], null, v5, v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v11, v0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v0, vcc_lo, v1, v7, vcc_lo
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v0, v8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, s5, v6
v_mad_u64_u32 v[0:1], null, s4, v6, 0
v_mul_lo_u32 v9, s4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v0, vcc_lo, v4, v0
v_add3_u32 v1, v1, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v5, v1
v_subrev_co_ci_u32_e64 v4, s2, s5, v8, vcc_lo
v_add_co_u32 v8, s2, v6, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s2, 0, v7, s2
v_sub_co_u32 v10, s2, v0, s4
v_sub_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
v_subrev_co_ci_u32_e64 v4, s2, 0, v4, s2
v_cmp_le_u32_e32 vcc_lo, s4, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e64 s2, s5, v1
v_cndmask_b32_e64 v5, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_cndmask_b32_e64 v10, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e64 v0, 0, -1, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v1
v_cndmask_b32_e64 v11, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v0, v11, v0, s2
v_cndmask_b32_e32 v4, v10, v5, vcc_lo
v_add_co_u32 v5, vcc_lo, v6, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v1, v10, v9 :: v_dual_cndmask_b32 v4, v5, v8
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_dual_cndmask_b32 v1, v7, v1 :: v_dual_cndmask_b32 v0, v6, v4
.LBB0_2:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_4
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s3, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s3, v0
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s4
v_sub_nc_u32_e32 v1, v4, v1
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v1
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_lshr_b64 s[6:7], s[4:5], 2
v_mov_b32_e32 v4, 0
v_or_b32_e32 v5, s7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[4:5]
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_6
v_cvt_f32_u32_e32 v4, s6
v_cvt_f32_u32_e32 v5, s7
s_sub_u32 s2, 0, s6
s_subb_u32 s8, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0x4f800000, v4
v_rcp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x5f7ffffc, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x2f800000, v4
v_trunc_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v5, 0xcf800000, v4
v_cvt_u32_f32_e32 v5, v5
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s2, v5
v_mul_hi_u32 v7, s2, v4
v_mul_lo_u32 v8, s8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v7, v6
v_mul_lo_u32 v7, s2, v4
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v4, v7
v_mul_lo_u32 v9, v4, v6
v_mul_hi_u32 v10, v4, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v6, s2, v4
v_mul_lo_u32 v8, s8, v4
v_mul_lo_u32 v7, s2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v6, v7
v_mul_lo_u32 v7, s2, v4
v_add_nc_u32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v8, v4, v7
v_mul_lo_u32 v9, v4, v6
v_mul_hi_u32 v10, v4, v6
v_mul_hi_u32 v11, v5, v7
v_mul_lo_u32 v7, v5, v7
v_mul_hi_u32 v12, v5, v6
v_mul_lo_u32 v6, v5, v6
v_add_co_u32 v8, vcc_lo, v8, v9
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v8, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v7, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v10, vcc_lo, v5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v11, v2, v8
v_mad_u64_u32 v[6:7], null, v3, v8, 0
v_mad_u64_u32 v[4:5], null, v2, v10, 0
v_mad_u64_u32 v[8:9], null, v3, v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v11, v4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, v4, v6
v_add_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v4, v8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v8, s7, v6
v_mad_u64_u32 v[4:5], null, s6, v6, 0
v_mul_lo_u32 v6, s6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v4, vcc_lo, v2, v4
v_add3_u32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v6, v3, v5
v_subrev_co_ci_u32_e64 v6, s2, s7, v6, vcc_lo
v_sub_co_ci_u32_e32 v5, vcc_lo, v3, v5, vcc_lo
v_sub_co_u32 v7, vcc_lo, v4, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v8, s2, 0, v6, vcc_lo
v_cmp_le_u32_e64 s2, s6, v4
v_subrev_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v5
v_cndmask_b32_e64 v9, 0, -1, s2
v_cmp_le_u32_e64 s2, s6, v7
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, 0, -1, s2
v_cmp_le_u32_e64 s2, s7, v8
v_cndmask_b32_e64 v11, 0, -1, s2
v_cmp_eq_u32_e64 s2, s7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_sub_co_u32 v11, vcc_lo, v7, s6
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v10
v_cndmask_b32_e64 v9, v12, v9, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v7, v11
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v5, v5, v6 :: v_dual_cndmask_b32 v4, v4, v7
.LBB0_6:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_8
v_alignbit_b32 v4, s5, s4, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v5, v4
v_sub_nc_u32_e32 v6, 0, v4
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v2, v5
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v2, v5
v_sub_nc_u32_e32 v6, v5, v4
v_cmp_ge_u32_e32 vcc_lo, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_sub_nc_u32_e32 v6, v5, v4
v_cmp_ge_u32_e32 vcc_lo, v5, v4
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v4, v5, v6 :: v_dual_mov_b32 v5, 0
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_lshr_b64 s[6:7], s[4:5], 1
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v7, s7, v3
v_cmp_ne_u64_e32 vcc_lo, 0, v[6:7]
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s2
s_cbranch_execz .LBB0_10
v_cvt_f32_u32_e32 v6, s6
v_cvt_f32_u32_e32 v7, s7
s_sub_u32 s2, 0, s6
s_subb_u32 s8, 0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v6, v7, 0x4f800000, v6
v_rcp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x5f7ffffc, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x2f800000, v6
v_trunc_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v6, v7, 0xcf800000, v6
v_cvt_u32_f32_e32 v7, v7
v_cvt_u32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v8, s2, v7
v_mul_hi_u32 v9, s2, v6
v_mul_lo_u32 v10, s8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v9, v8
v_mul_lo_u32 v9, s2, v6
v_add_nc_u32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v6, v9
v_mul_lo_u32 v11, v6, v8
v_mul_hi_u32 v12, v6, v8
v_mul_hi_u32 v13, v7, v9
v_mul_lo_u32 v9, v7, v9
v_mul_hi_u32 v14, v7, v8
v_mul_lo_u32 v8, v7, v8
v_add_co_u32 v10, vcc_lo, v10, v11
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, v8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v8, s2, v6
v_mul_lo_u32 v10, s8, v6
v_mul_lo_u32 v9, s2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v8, v9
v_mul_lo_u32 v9, s2, v6
v_add_nc_u32_e32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v10, v6, v9
v_mul_lo_u32 v11, v6, v8
v_mul_hi_u32 v12, v6, v8
v_mul_hi_u32 v13, v7, v9
v_mul_lo_u32 v9, v7, v9
v_mul_hi_u32 v14, v7, v8
v_mul_lo_u32 v8, v7, v8
v_add_co_u32 v10, vcc_lo, v10, v11
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v9, vcc_lo, v11, v13, vcc_lo
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v9, v8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v6, v8
v_add_co_ci_u32_e32 v12, vcc_lo, v7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v13, v2, v10
v_mad_u64_u32 v[8:9], null, v3, v10, 0
v_mad_u64_u32 v[6:7], null, v2, v12, 0
v_mad_u64_u32 v[10:11], null, v3, v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v13, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, v8
v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, v10
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v10, s7, v8
v_mad_u64_u32 v[6:7], null, s6, v8, 0
v_mul_lo_u32 v8, s6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v2, vcc_lo, v2, v6
v_add3_u32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v3, v7
v_subrev_co_ci_u32_e64 v6, s2, s7, v8, vcc_lo
v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v7, vcc_lo
v_sub_co_u32 v7, vcc_lo, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v8, s2, 0, v6, vcc_lo
v_cmp_le_u32_e64 s2, s6, v2
v_subrev_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_cndmask_b32_e64 v9, 0, -1, s2
v_cmp_le_u32_e64 s2, s6, v7
v_cndmask_b32_e64 v12, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v10, 0, -1, s2
v_cmp_le_u32_e64 s2, s7, v8
v_cndmask_b32_e64 v11, 0, -1, s2
v_cmp_eq_u32_e64 s2, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v10, vcc_lo
v_sub_co_u32 v11, vcc_lo, v7, s6
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v10
v_cndmask_b32_e64 v9, v12, v9, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v8, v6, vcc_lo
v_cndmask_b32_e32 v8, v7, v11, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v7, v3, v6 :: v_dual_cndmask_b32 v6, v2, v8
.LBB0_10:
s_and_not1_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_12
v_alignbit_b32 v3, s5, s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v6, v3
v_sub_nc_u32_e32 v7, 0, v3
v_rcp_iflag_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v6, v6
v_mul_lo_u32 v7, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v7, v6, v7
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v2, v6
v_mul_lo_u32 v6, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v6
v_sub_nc_u32_e32 v6, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_sub_nc_u32_e32 v6, v2, v3
v_cmp_ge_u32_e32 vcc_lo, v2, v3
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v6, v2, v6, vcc_lo
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v8, v1, s4
v_mul_lo_u32 v9, v0, s5
v_mad_u64_u32 v[2:3], null, v0, s4, 0
v_lshlrev_b64 v[4:5], 4, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v9, v8
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v5, vcc_lo
v_lshlrev_b64 v[4:5], 1, v[0:1]
v_alignbit_b32 v0, v1, v0, 31
global_load_b32 v10, v[2:3], off
v_or_b32_e32 v11, 1, v4
v_mul_lo_u32 v5, v5, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v12, v11, s5
v_mad_u64_u32 v[8:9], null, v11, s4, 0
v_add3_u32 v9, v9, v12, v5
v_lshlrev_b64 v[5:6], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 1, v[8:9]
v_and_b32_e32 v8, -4, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v7, v5
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[7:8], v10, off
global_load_b32 v9, v[2:3], off offset:4
s_waitcnt vmcnt(0)
global_store_b32 v[7:8], v9, off offset:4
global_load_b32 v7, v[2:3], off offset:8
v_mul_lo_u32 v8, v0, s4
v_mul_lo_u32 v9, v4, s5
v_mad_u64_u32 v[0:1], null, v4, s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v1, v9, v8
v_lshlrev_b64 v[0:1], 1, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
global_load_b32 v2, v[2:3], off offset:12
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15transformKernelPKfPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15transformKernelPKfPfmm, .Lfunc_end0-_Z15transformKernelPKfPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15transformKernelPKfPfmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15transformKernelPKfPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
__global__ void axpy() {
}
int main(int argc, char* argv[]) {
// Launch the kernel.
axpy<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z4axpyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
__global__ void axpy() {
}
int main(int argc, char* argv[]) {
// Launch the kernel.
axpy<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_0013395b_00000000-6_basic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4axpyvv
.type _Z22__device_stub__Z4axpyvv, @function
_Z22__device_stub__Z4axpyvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4axpyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z4axpyvv, .-_Z22__device_stub__Z4axpyvv
.globl _Z4axpyv
.type _Z4axpyv, @function
_Z4axpyv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4axpyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4axpyv, .-_Z4axpyv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4axpyvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4axpyv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
__global__ void axpy() {
}
int main(int argc, char* argv[]) {
// Launch the kernel.
axpy<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void axpy() {
}
int main(int argc, char* argv[]) {
// Launch the kernel.
axpy<<<1, 10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void axpy() {
}
int main(int argc, char* argv[]) {
// Launch the kernel.
axpy<<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyv
.globl _Z4axpyv
.p2align 8
.type _Z4axpyv,@function
_Z4axpyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4axpyv, .Lfunc_end0-_Z4axpyv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z4axpyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
__global__ void axpy() {
}
int main(int argc, char* argv[]) {
// Launch the kernel.
axpy<<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.file "basic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__axpyv # -- Begin function _Z19__device_stub__axpyv
.p2align 4, 0x90
.type _Z19__device_stub__axpyv,@function
_Z19__device_stub__axpyv: # @_Z19__device_stub__axpyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4axpyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__axpyv, .Lfunc_end0-_Z19__device_stub__axpyv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4axpyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4axpyv,@object # @_Z4axpyv
.section .rodata,"a",@progbits
.globl _Z4axpyv
.p2align 3, 0x0
_Z4axpyv:
.quad _Z19__device_stub__axpyv
.size _Z4axpyv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4axpyv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4axpyv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4axpyv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4axpyv
.globl _Z4axpyv
.p2align 8
.type _Z4axpyv,@function
_Z4axpyv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4axpyv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4axpyv, .Lfunc_end0-_Z4axpyv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4axpyv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z4axpyv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013395b_00000000-6_basic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4axpyvv
.type _Z22__device_stub__Z4axpyvv, @function
_Z22__device_stub__Z4axpyvv:
.LFB3694:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4axpyv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z4axpyvv, .-_Z22__device_stub__Z4axpyvv
.globl _Z4axpyv
.type _Z4axpyv, @function
_Z4axpyv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4axpyvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z4axpyv, .-_Z4axpyv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4axpyvv
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4axpyv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4axpyv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "basic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__axpyv # -- Begin function _Z19__device_stub__axpyv
.p2align 4, 0x90
.type _Z19__device_stub__axpyv,@function
_Z19__device_stub__axpyv: # @_Z19__device_stub__axpyv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4axpyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__axpyv, .Lfunc_end0-_Z19__device_stub__axpyv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4axpyv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4axpyv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4axpyv,@object # @_Z4axpyv
.section .rodata,"a",@progbits
.globl _Z4axpyv
.p2align 3, 0x0
_Z4axpyv:
.quad _Z19__device_stub__axpyv
.size _Z4axpyv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4axpyv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__axpyv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4axpyv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //This file contains code for performing convolution on a GPU
//Author:-Ajay Singh
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__global__ void convolution_1D_basic_kernel(float *N, float *M, float *P, int mask_width, int size){
int i=threadIdx.x+blockIdx.x*blockDim.x;
int start_pos=(int)(i-(mask_width/2));
float pvalue;
for(int j=start_pos; j<start_pos+mask_width; j++){
if(j>=0 && j<size)
pvalue+=M[j-start_pos]*N[j];
}
P[i]=pvalue;
}
#define size 10000
#define mask_width 100
int main(){
float mask[mask_width];
float arr[size];
float Output[size];
float *Pd, *arrd, *Md;
double elapsed;
for(int i=0; i<size; i++){
if(i<mask_width){
mask[i]=i/size;
}
arr[i]=(i*i)/size;
}
if(cudaMalloc((void **)&Pd, sizeof(float)*size)!=cudaSuccess){
printf("error while allocating Pd\n");
}
if(cudaMalloc((void **)&Md, sizeof(float)*mask_width)!=cudaSuccess){
printf("error while allocating Md\n");
}
if(cudaMalloc((void **)&arrd, sizeof(float)*size)!=cudaSuccess){
printf("error while allocating arrd\n");
}
if(cudaMemcpy(arrd, arr, sizeof(float)*size, cudaMemcpyHostToDevice)!=cudaSuccess){
printf("error while copyting arr from host to device\n");
}
if(cudaMemcpy(Md, mask, sizeof(float)*mask_width, cudaMemcpyHostToDevice)!=cudaSuccess){
printf("error while copyting mask from host to device\n");
}
elapsed= -clock();
convolution_1D_basic_kernel<<<size/20, 20>>>(arrd, Md, Pd, mask_width, size);
elapsed+=clock();
if(cudaMemcpy(Output, Pd, sizeof(float)*size, cudaMemcpyDeviceToHost)!=cudaSuccess){
printf("error while copyting arr from host to device\n");
}
printf("Time Taken = %lf\n",elapsed);
cudaFree(arrd);
cudaFree(Pd);
cudaFree(Md);
return 0;
} | code for sm_80
Function : _Z27convolution_1D_basic_kernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe40003f06270 */
/*0070*/ LEA.HI R2, R2, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e0002027a11 */
/* 0x000fe200078f08ff */
/*0080*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fcc000f8e023f */
/*0090*/ IADD3 R0, R7, UR4, RZ ; /* 0x0000000407007c10 */
/* 0x002fc8000fffe0ff */
/*00a0*/ @!P0 BRA 0x5e0 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fe20000011402 */
/*00c0*/ ULOP3.LUT UR5, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f057292 */
/* 0x000fe2000f8e333f */
/*00d0*/ BSSY B0, 0x320 ; /* 0x0000024000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IADD3 R2, -R3.reuse, c[0x0][0x178], R0.reuse ; /* 0x00005e0003027a10 */
/* 0x140fe20007ffe100 */
/*00f0*/ IMAD.IADD R10, R0, 0x1, -R3 ; /* 0x00000001000a7824 */
/* 0x000fe200078e0a03 */
/*0100*/ IADD3 R5, -R3, 0x1, R0 ; /* 0x0000000103057810 */
/* 0x000fc80007ffe100 */
/*0110*/ IMNMX R2, R2, R5, !PT ; /* 0x0000000502027217 */
/* 0x000fca0007800200 */
/*0120*/ IMAD.IADD R2, R3, 0x1, R2 ; /* 0x0000000103027824 */
/* 0x000fe400078e0202 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fc600078e000a */
/*0140*/ IADD3 R4, R2, -UR4, -R7 ; /* 0x8000000402047c10 */
/* 0x000fe4000fffe807 */
/*0150*/ IADD3 R2, -R7, UR5, R2 ; /* 0x0000000507027c10 */
/* 0x000fe4000fffe102 */
/*0160*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe4000780c0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd60003f26070 */
/*0180*/ @!P0 BRA 0x310 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*01b0*/ IMAD.WIDE R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0203 */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0003 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0002 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fca00078e000a */
/*0210*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fc80003f06270 */
/*0220*/ ISETP.LT.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000701670 */
/*0230*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff058224 */
/* 0x000fe400078e0009 */
/*0240*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff068224 */
/* 0x000fe400078e000b */
/*0250*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff078224 */
/* 0x000fe400078e000c */
/*0260*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x0000a8000c1e1900 */
/*0270*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000606068981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc40007ffe0ff */
/*0290*/ IADD3 R11, P2, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ ISETP.NE.AND P4, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f85270 */
/*02b0*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe20007f7e0ff */
/*02c0*/ IMAD.X R12, RZ, RZ, R12, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e060c */
/*02d0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc60007ffe0ff */
/*02e0*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe400018e0609 */
/*02f0*/ @!P0 FFMA R2, R5, R6, R2 ; /* 0x0000000605028223 */
/* 0x004fc80000000002 */
/*0300*/ @P4 BRA 0x210 ; /* 0xffffff0000004947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ BSSY B0, 0x5e0 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe200078e00ff */
/*0350*/ @!P1 BRA 0x5d0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.IADD R4, R10.reuse, 0x1, -R3.reuse ; /* 0x000000010a047824 */
/* 0x140fe200078e0a03 */
/*0370*/ IADD3 R10, R10, c[0x0][0x178], RZ ; /* 0x00005e000a0a7a10 */
/* 0x000fe20007ffe0ff */
/*0380*/ IMAD.MOV.U32 R19, RZ, RZ, R3 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0003 */
/*0390*/ IMAD.WIDE R4, R4, 0x4, RZ ; /* 0x0000000404047825 */
/* 0x000fca00078e02ff */
/*03a0*/ IADD3 R11, P0, -R4, c[0x0][0x168], RZ ; /* 0x00005a00040b7a10 */
/* 0x000fc80007f1e1ff */
/*03b0*/ IADD3.X R12, ~R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00050c7a10 */
/* 0x000fe400007fe5ff */
/*03c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*03d0*/ IMAD.WIDE R6, R19, 0x4, R8 ; /* 0x0000000413067825 */
/* 0x000fe200078e0208 */
/*03e0*/ IADD3 R4, R3.reuse, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x040fe40007ffe0ff */
/*03f0*/ ISETP.LT.OR P0, PT, R3.reuse, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x040fe40000701670 */
/*0400*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe40003f26270 */
/*0410*/ IADD3 R5, R3.reuse, 0x2, RZ ; /* 0x0000000203057810 */
/* 0x040fe40007ffe0ff */
/*0420*/ IADD3 R4, R3, 0x3, RZ ; /* 0x0000000303047810 */
/* 0x000fc40007ffe0ff */
/*0430*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f46270 */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000c */
/*0450*/ ISETP.GE.AND P3, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f66270 */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000b */
/*0470*/ ISETP.LT.OR P1, PT, R3.reuse, -0x1, P1 ; /* 0xffffffff0300780c */
/* 0x040fe20000f21670 */
/*0480*/ @!P0 LDG.E R12, [R6.64] ; /* 0x00000006060c8981 */
/* 0x000ea2000c1e1900 */
/*0490*/ ISETP.LT.OR P2, PT, R3.reuse, -0x2, P2 ; /* 0xfffffffe0300780c */
/* 0x040fe40001741670 */
/*04a0*/ ISETP.LT.OR P3, PT, R3.reuse, -0x3, P3 ; /* 0xfffffffd0300780c */
/* 0x040fe20001f61670 */
/*04b0*/ @!P0 LDG.E R11, [R4.64] ; /* 0x00000006040b8981 */
/* 0x000eb0000c1e1900 */
/*04c0*/ @!P1 LDG.E R13, [R6.64+0x4] ; /* 0x00000406060d9981 */
/* 0x000ee8000c1e1900 */
/*04d0*/ @!P1 LDG.E R14, [R4.64+0x4] ; /* 0x00000406040e9981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ @!P2 LDG.E R15, [R6.64+0x8] ; /* 0x00000806060fa981 */
/* 0x000f28000c1e1900 */
/*04f0*/ @!P2 LDG.E R16, [R4.64+0x8] ; /* 0x000008060410a981 */
/* 0x000f28000c1e1900 */
/*0500*/ @!P3 LDG.E R17, [R6.64+0xc] ; /* 0x00000c060611b981 */
/* 0x000f68000c1e1900 */
/*0510*/ @!P3 LDG.E R18, [R4.64+0xc] ; /* 0x00000c060412b981 */
/* 0x000f62000c1e1900 */
/*0520*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0530*/ IADD3 R8, P4, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fca0007f9e0ff */
/*0540*/ IMAD.X R9, RZ, RZ, R9, P4 ; /* 0x000000ffff097224 */
/* 0x000fe400020e0609 */
/*0550*/ @!P0 FFMA R2, R11, R12, R2 ; /* 0x0000000c0b028223 */
/* 0x004fe20000000002 */
/*0560*/ ISETP.GE.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fc60003f06270 */
/*0570*/ @!P1 FFMA R2, R13, R14, R2 ; /* 0x0000000e0d029223 */
/* 0x008fe20000000002 */
/*0580*/ IADD3 R11, P1, R4, 0x10, RZ ; /* 0x00000010040b7810 */
/* 0x000fc60007f3e0ff */
/*0590*/ @!P2 FFMA R2, R15, R16, R2 ; /* 0x000000100f02a223 */
/* 0x010fe40000000002 */
/*05a0*/ IMAD.X R12, RZ, RZ, R5, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe400008e0605 */
/*05b0*/ @!P3 FFMA R2, R17, R18, R2 ; /* 0x000000121102b223 */
/* 0x020fe40000000002 */
/*05c0*/ @!P0 BRA 0x3c0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*0600*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //This file contains code for performing convolution on a GPU
//Author:-Ajay Singh
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__global__ void convolution_1D_basic_kernel(float *N, float *M, float *P, int mask_width, int size){
int i=threadIdx.x+blockIdx.x*blockDim.x;
int start_pos=(int)(i-(mask_width/2));
float pvalue;
for(int j=start_pos; j<start_pos+mask_width; j++){
if(j>=0 && j<size)
pvalue+=M[j-start_pos]*N[j];
}
P[i]=pvalue;
}
#define size 10000
#define mask_width 100
int main(){
float mask[mask_width];
float arr[size];
float Output[size];
float *Pd, *arrd, *Md;
double elapsed;
for(int i=0; i<size; i++){
if(i<mask_width){
mask[i]=i/size;
}
arr[i]=(i*i)/size;
}
if(cudaMalloc((void **)&Pd, sizeof(float)*size)!=cudaSuccess){
printf("error while allocating Pd\n");
}
if(cudaMalloc((void **)&Md, sizeof(float)*mask_width)!=cudaSuccess){
printf("error while allocating Md\n");
}
if(cudaMalloc((void **)&arrd, sizeof(float)*size)!=cudaSuccess){
printf("error while allocating arrd\n");
}
if(cudaMemcpy(arrd, arr, sizeof(float)*size, cudaMemcpyHostToDevice)!=cudaSuccess){
printf("error while copyting arr from host to device\n");
}
if(cudaMemcpy(Md, mask, sizeof(float)*mask_width, cudaMemcpyHostToDevice)!=cudaSuccess){
printf("error while copyting mask from host to device\n");
}
elapsed= -clock();
convolution_1D_basic_kernel<<<size/20, 20>>>(arrd, Md, Pd, mask_width, size);
elapsed+=clock();
if(cudaMemcpy(Output, Pd, sizeof(float)*size, cudaMemcpyDeviceToHost)!=cudaSuccess){
printf("error while copyting arr from host to device\n");
}
printf("Time Taken = %lf\n",elapsed);
cudaFree(arrd);
cudaFree(Pd);
cudaFree(Md);
return 0;
} | .file "tmpxft_000050b6_00000000-6_1dConv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
.type _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii, @function
_Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_1D_basic_kernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii, .-_Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.type _Z27convolution_1D_basic_kernelPfS_S_ii, @function
_Z27convolution_1D_basic_kernelPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z27convolution_1D_basic_kernelPfS_S_ii, .-_Z27convolution_1D_basic_kernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "error while allocating Pd\n"
.LC1:
.string "error while allocating Md\n"
.LC2:
.string "error while allocating arrd\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "error while copyting arr from host to device\n"
.align 8
.LC4:
.string "error while copyting mask from host to device\n"
.section .rodata.str1.1
.LC5:
.string "Time Taken = %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77840
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2656, %rsp
.cfi_def_cfa_offset 80496
movq %fs:40, %rax
movq %rax, 80472(%rsp)
xorl %eax, %eax
movl $0, %edx
.L15:
cmpl $99, %edx
jle .L25
movl %edx, %ecx
imull %edx, %ecx
movslq %ecx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 464(%rsp,%rdx,4)
addq $1, %rdx
cmpq $10000, %rdx
jne .L15
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
.L16:
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
.L17:
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
.L18:
leaq 464(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
.L19:
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $400, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
.L20:
call clock@PLT
negq %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd %xmm1, 8(%rsp)
movl $20, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $500, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd 8(%rsp), %xmm0
movq %xmm0, %rbx
leaq 40464(%rsp), %rdi
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
.L22:
movq %rbx, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 80472(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $80480, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movslq %edx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 64(%rsp,%rdx,4)
movl %edx, %ecx
imull %edx, %ecx
movslq %ecx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 464(%rsp,%rdx,4)
addq $1, %rdx
jmp .L15
.L26:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L29:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L30:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L31:
movl $10000, %r8d
movl $100, %ecx
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
jmp .L21
.L32:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z27convolution_1D_basic_kernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_1D_basic_kernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //This file contains code for performing convolution on a GPU
//Author:-Ajay Singh
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__global__ void convolution_1D_basic_kernel(float *N, float *M, float *P, int mask_width, int size){
int i=threadIdx.x+blockIdx.x*blockDim.x;
int start_pos=(int)(i-(mask_width/2));
float pvalue;
for(int j=start_pos; j<start_pos+mask_width; j++){
if(j>=0 && j<size)
pvalue+=M[j-start_pos]*N[j];
}
P[i]=pvalue;
}
#define size 10000
#define mask_width 100
int main(){
float mask[mask_width];
float arr[size];
float Output[size];
float *Pd, *arrd, *Md;
double elapsed;
for(int i=0; i<size; i++){
if(i<mask_width){
mask[i]=i/size;
}
arr[i]=(i*i)/size;
}
if(cudaMalloc((void **)&Pd, sizeof(float)*size)!=cudaSuccess){
printf("error while allocating Pd\n");
}
if(cudaMalloc((void **)&Md, sizeof(float)*mask_width)!=cudaSuccess){
printf("error while allocating Md\n");
}
if(cudaMalloc((void **)&arrd, sizeof(float)*size)!=cudaSuccess){
printf("error while allocating arrd\n");
}
if(cudaMemcpy(arrd, arr, sizeof(float)*size, cudaMemcpyHostToDevice)!=cudaSuccess){
printf("error while copyting arr from host to device\n");
}
if(cudaMemcpy(Md, mask, sizeof(float)*mask_width, cudaMemcpyHostToDevice)!=cudaSuccess){
printf("error while copyting mask from host to device\n");
}
elapsed= -clock();
convolution_1D_basic_kernel<<<size/20, 20>>>(arrd, Md, Pd, mask_width, size);
elapsed+=clock();
if(cudaMemcpy(Output, Pd, sizeof(float)*size, cudaMemcpyDeviceToHost)!=cudaSuccess){
printf("error while copyting arr from host to device\n");
}
printf("Time Taken = %lf\n",elapsed);
cudaFree(arrd);
cudaFree(Pd);
cudaFree(Md);
return 0;
} | //This file contains code for performing convolution on a GPU
//Author:-Ajay Singh
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__global__ void convolution_1D_basic_kernel(float *N, float *M, float *P, int mask_width, int size){
int i=threadIdx.x+blockIdx.x*blockDim.x;
int start_pos=(int)(i-(mask_width/2));
float pvalue;
for(int j=start_pos; j<start_pos+mask_width; j++){
if(j>=0 && j<size)
pvalue+=M[j-start_pos]*N[j];
}
P[i]=pvalue;
}
#define size 10000
#define mask_width 100
int main(){
float mask[mask_width];
float arr[size];
float Output[size];
float *Pd, *arrd, *Md;
double elapsed;
for(int i=0; i<size; i++){
if(i<mask_width){
mask[i]=i/size;
}
arr[i]=(i*i)/size;
}
if(hipMalloc((void **)&Pd, sizeof(float)*size)!=hipSuccess){
printf("error while allocating Pd\n");
}
if(hipMalloc((void **)&Md, sizeof(float)*mask_width)!=hipSuccess){
printf("error while allocating Md\n");
}
if(hipMalloc((void **)&arrd, sizeof(float)*size)!=hipSuccess){
printf("error while allocating arrd\n");
}
if(hipMemcpy(arrd, arr, sizeof(float)*size, hipMemcpyHostToDevice)!=hipSuccess){
printf("error while copyting arr from host to device\n");
}
if(hipMemcpy(Md, mask, sizeof(float)*mask_width, hipMemcpyHostToDevice)!=hipSuccess){
printf("error while copyting mask from host to device\n");
}
elapsed= -clock();
convolution_1D_basic_kernel<<<size/20, 20>>>(arrd, Md, Pd, mask_width, size);
elapsed+=clock();
if(hipMemcpy(Output, Pd, sizeof(float)*size, hipMemcpyDeviceToHost)!=hipSuccess){
printf("error while copyting arr from host to device\n");
}
printf("Time Taken = %lf\n",elapsed);
hipFree(arrd);
hipFree(Pd);
hipFree(Md);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //This file contains code for performing convolution on a GPU
//Author:-Ajay Singh
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__global__ void convolution_1D_basic_kernel(float *N, float *M, float *P, int mask_width, int size){
int i=threadIdx.x+blockIdx.x*blockDim.x;
int start_pos=(int)(i-(mask_width/2));
float pvalue;
for(int j=start_pos; j<start_pos+mask_width; j++){
if(j>=0 && j<size)
pvalue+=M[j-start_pos]*N[j];
}
P[i]=pvalue;
}
#define size 10000
#define mask_width 100
int main(){
float mask[mask_width];
float arr[size];
float Output[size];
float *Pd, *arrd, *Md;
double elapsed;
for(int i=0; i<size; i++){
if(i<mask_width){
mask[i]=i/size;
}
arr[i]=(i*i)/size;
}
if(hipMalloc((void **)&Pd, sizeof(float)*size)!=hipSuccess){
printf("error while allocating Pd\n");
}
if(hipMalloc((void **)&Md, sizeof(float)*mask_width)!=hipSuccess){
printf("error while allocating Md\n");
}
if(hipMalloc((void **)&arrd, sizeof(float)*size)!=hipSuccess){
printf("error while allocating arrd\n");
}
if(hipMemcpy(arrd, arr, sizeof(float)*size, hipMemcpyHostToDevice)!=hipSuccess){
printf("error while copyting arr from host to device\n");
}
if(hipMemcpy(Md, mask, sizeof(float)*mask_width, hipMemcpyHostToDevice)!=hipSuccess){
printf("error while copyting mask from host to device\n");
}
elapsed= -clock();
convolution_1D_basic_kernel<<<size/20, 20>>>(arrd, Md, Pd, mask_width, size);
elapsed+=clock();
if(hipMemcpy(Output, Pd, sizeof(float)*size, hipMemcpyDeviceToHost)!=hipSuccess){
printf("error while copyting arr from host to device\n");
}
printf("Time Taken = %lf\n",elapsed);
hipFree(arrd);
hipFree(Pd);
hipFree(Md);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27convolution_1D_basic_kernelPfS_S_ii
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.p2align 8
.type _Z27convolution_1D_basic_kernelPfS_S_ii,@function
_Z27convolution_1D_basic_kernelPfS_S_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x1c
s_lshr_b32 s8, s2, 31
v_mov_b32_e32 v3, 0
s_add_i32 s8, s2, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s8, s8, 1
v_subrev_nc_u32_e32 v2, s8, v1
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, s2, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v2, v4
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_5
.LBB0_3:
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, vcc_lo, s2
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_load_b32 s9, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s9, v5
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_branch .LBB0_7
.LBB0_6:
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_1D_basic_kernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27convolution_1D_basic_kernelPfS_S_ii, .Lfunc_end0-_Z27convolution_1D_basic_kernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27convolution_1D_basic_kernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27convolution_1D_basic_kernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //This file contains code for performing convolution on a GPU
//Author:-Ajay Singh
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<time.h>
__global__ void convolution_1D_basic_kernel(float *N, float *M, float *P, int mask_width, int size){
int i=threadIdx.x+blockIdx.x*blockDim.x;
int start_pos=(int)(i-(mask_width/2));
float pvalue;
for(int j=start_pos; j<start_pos+mask_width; j++){
if(j>=0 && j<size)
pvalue+=M[j-start_pos]*N[j];
}
P[i]=pvalue;
}
#define size 10000
#define mask_width 100
int main(){
float mask[mask_width];
float arr[size];
float Output[size];
float *Pd, *arrd, *Md;
double elapsed;
for(int i=0; i<size; i++){
if(i<mask_width){
mask[i]=i/size;
}
arr[i]=(i*i)/size;
}
if(hipMalloc((void **)&Pd, sizeof(float)*size)!=hipSuccess){
printf("error while allocating Pd\n");
}
if(hipMalloc((void **)&Md, sizeof(float)*mask_width)!=hipSuccess){
printf("error while allocating Md\n");
}
if(hipMalloc((void **)&arrd, sizeof(float)*size)!=hipSuccess){
printf("error while allocating arrd\n");
}
if(hipMemcpy(arrd, arr, sizeof(float)*size, hipMemcpyHostToDevice)!=hipSuccess){
printf("error while copyting arr from host to device\n");
}
if(hipMemcpy(Md, mask, sizeof(float)*mask_width, hipMemcpyHostToDevice)!=hipSuccess){
printf("error while copyting mask from host to device\n");
}
elapsed= -clock();
convolution_1D_basic_kernel<<<size/20, 20>>>(arrd, Md, Pd, mask_width, size);
elapsed+=clock();
if(hipMemcpy(Output, Pd, sizeof(float)*size, hipMemcpyDeviceToHost)!=hipSuccess){
printf("error while copyting arr from host to device\n");
}
printf("Time Taken = %lf\n",elapsed);
hipFree(arrd);
hipFree(Pd);
hipFree(Md);
return 0;
} | .text
.file "1dConv.hip"
.globl _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii # -- Begin function _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.p2align 4, 0x90
.type _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii,@function
_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii: # @_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii, .Lfunc_end0-_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $80520, %rsp # imm = 0x13A88
.cfi_def_cfa_offset 80544
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
movl $3518437209, %ecx # imm = 0xD1B71759
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl %eax, %edx
imull %edx, %edx
imulq %rcx, %rdx
shrq $45, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 40512(%rsp,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpq $99, %rax
ja .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl $0, 112(%rsp,%rax,4)
jmp .LBB1_3
.LBB1_4:
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_6:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_8:
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB1_10
# %bb.9:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_10:
movq 16(%rsp), %rdi
leaq 40512(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_12
# %bb.11:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB1_12:
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_14:
callq clock
movq %rax, %rbx
movabsq $4294967316, %rdx # imm = 0x100000014
leaq 480(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 36(%rsp)
movl $10000, 32(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 512(%rsp)
leaq 96(%rsp), %rax
movq %rax, 520(%rsp)
leaq 88(%rsp), %rax
movq %rax, 528(%rsp)
leaq 36(%rsp), %rax
movq %rax, 536(%rsp)
leaq 32(%rsp), %rax
movq %rax, 544(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 512(%rsp), %r9
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
callq clock
movq %rax, %r14
movq 24(%rsp), %rsi
leaq 512(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_18
# %bb.17:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB1_18:
negq %rbx
cvtsi2sd %rbx, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80520, %rsp # imm = 0x13A88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27convolution_1D_basic_kernelPfS_S_ii,@object # @_Z27convolution_1D_basic_kernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.p2align 3, 0x0
_Z27convolution_1D_basic_kernelPfS_S_ii:
.quad _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.size _Z27convolution_1D_basic_kernelPfS_S_ii, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Time Taken = %lf\n"
.size .L.str.5, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27convolution_1D_basic_kernelPfS_S_ii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "error while allocating Pd"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "error while allocating Md"
.size .Lstr.1, 26
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "error while allocating arrd"
.size .Lstr.2, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "error while copyting mask from host to device"
.size .Lstr.4, 46
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "error while copyting arr from host to device"
.size .Lstr.5, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27convolution_1D_basic_kernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27convolution_1D_basic_kernelPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe40003f06270 */
/*0070*/ LEA.HI R2, R2, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e0002027a11 */
/* 0x000fe200078f08ff */
/*0080*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fcc000f8e023f */
/*0090*/ IADD3 R0, R7, UR4, RZ ; /* 0x0000000407007c10 */
/* 0x002fc8000fffe0ff */
/*00a0*/ @!P0 BRA 0x5e0 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*00b0*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fe20000011402 */
/*00c0*/ ULOP3.LUT UR5, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f057292 */
/* 0x000fe2000f8e333f */
/*00d0*/ BSSY B0, 0x320 ; /* 0x0000024000007945 */
/* 0x000fe40003800000 */
/*00e0*/ IADD3 R2, -R3.reuse, c[0x0][0x178], R0.reuse ; /* 0x00005e0003027a10 */
/* 0x140fe20007ffe100 */
/*00f0*/ IMAD.IADD R10, R0, 0x1, -R3 ; /* 0x00000001000a7824 */
/* 0x000fe200078e0a03 */
/*0100*/ IADD3 R5, -R3, 0x1, R0 ; /* 0x0000000103057810 */
/* 0x000fc80007ffe100 */
/*0110*/ IMNMX R2, R2, R5, !PT ; /* 0x0000000502027217 */
/* 0x000fca0007800200 */
/*0120*/ IMAD.IADD R2, R3, 0x1, R2 ; /* 0x0000000103027824 */
/* 0x000fe400078e0202 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fc600078e000a */
/*0140*/ IADD3 R4, R2, -UR4, -R7 ; /* 0x8000000402047c10 */
/* 0x000fe4000fffe807 */
/*0150*/ IADD3 R2, -R7, UR5, R2 ; /* 0x0000000507027c10 */
/* 0x000fe4000fffe102 */
/*0160*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe4000780c0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fd60003f26070 */
/*0180*/ @!P0 BRA 0x310 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0004 */
/*01b0*/ IMAD.WIDE R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e0203 */
/*01c0*/ IMAD.MOV.U32 R12, RZ, RZ, R3 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0003 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0002 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*01f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fca00078e000a */
/*0210*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fc80003f06270 */
/*0220*/ ISETP.LT.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000701670 */
/*0230*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff058224 */
/* 0x000fe400078e0009 */
/*0240*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff068224 */
/* 0x000fe400078e000b */
/*0250*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, R12 ; /* 0x000000ffff078224 */
/* 0x000fe400078e000c */
/*0260*/ @!P0 LDG.E R5, [R4.64] ; /* 0x0000000604058981 */
/* 0x0000a8000c1e1900 */
/*0270*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000606068981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc40007ffe0ff */
/*0290*/ IADD3 R11, P2, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ ISETP.NE.AND P4, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f85270 */
/*02b0*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x001fe20007f7e0ff */
/*02c0*/ IMAD.X R12, RZ, RZ, R12, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe200010e060c */
/*02d0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc60007ffe0ff */
/*02e0*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe400018e0609 */
/*02f0*/ @!P0 FFMA R2, R5, R6, R2 ; /* 0x0000000605028223 */
/* 0x004fc80000000002 */
/*0300*/ @P4 BRA 0x210 ; /* 0xffffff0000004947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ BSSY B0, 0x5e0 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe200078e00ff */
/*0350*/ @!P1 BRA 0x5d0 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.IADD R4, R10.reuse, 0x1, -R3.reuse ; /* 0x000000010a047824 */
/* 0x140fe200078e0a03 */
/*0370*/ IADD3 R10, R10, c[0x0][0x178], RZ ; /* 0x00005e000a0a7a10 */
/* 0x000fe20007ffe0ff */
/*0380*/ IMAD.MOV.U32 R19, RZ, RZ, R3 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0003 */
/*0390*/ IMAD.WIDE R4, R4, 0x4, RZ ; /* 0x0000000404047825 */
/* 0x000fca00078e02ff */
/*03a0*/ IADD3 R11, P0, -R4, c[0x0][0x168], RZ ; /* 0x00005a00040b7a10 */
/* 0x000fc80007f1e1ff */
/*03b0*/ IADD3.X R12, ~R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b00050c7a10 */
/* 0x000fe400007fe5ff */
/*03c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*03d0*/ IMAD.WIDE R6, R19, 0x4, R8 ; /* 0x0000000413067825 */
/* 0x000fe200078e0208 */
/*03e0*/ IADD3 R4, R3.reuse, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x040fe40007ffe0ff */
/*03f0*/ ISETP.LT.OR P0, PT, R3.reuse, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x040fe40000701670 */
/*0400*/ ISETP.GE.AND P1, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe40003f26270 */
/*0410*/ IADD3 R5, R3.reuse, 0x2, RZ ; /* 0x0000000203057810 */
/* 0x040fe40007ffe0ff */
/*0420*/ IADD3 R4, R3, 0x3, RZ ; /* 0x0000000303047810 */
/* 0x000fc40007ffe0ff */
/*0430*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x17c], PT ; /* 0x00005f0005007a0c */
/* 0x000fe20003f46270 */
/*0440*/ IMAD.MOV.U32 R5, RZ, RZ, R12 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000c */
/*0450*/ ISETP.GE.AND P3, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f66270 */
/*0460*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000b */
/*0470*/ ISETP.LT.OR P1, PT, R3.reuse, -0x1, P1 ; /* 0xffffffff0300780c */
/* 0x040fe20000f21670 */
/*0480*/ @!P0 LDG.E R12, [R6.64] ; /* 0x00000006060c8981 */
/* 0x000ea2000c1e1900 */
/*0490*/ ISETP.LT.OR P2, PT, R3.reuse, -0x2, P2 ; /* 0xfffffffe0300780c */
/* 0x040fe40001741670 */
/*04a0*/ ISETP.LT.OR P3, PT, R3.reuse, -0x3, P3 ; /* 0xfffffffd0300780c */
/* 0x040fe20001f61670 */
/*04b0*/ @!P0 LDG.E R11, [R4.64] ; /* 0x00000006040b8981 */
/* 0x000eb0000c1e1900 */
/*04c0*/ @!P1 LDG.E R13, [R6.64+0x4] ; /* 0x00000406060d9981 */
/* 0x000ee8000c1e1900 */
/*04d0*/ @!P1 LDG.E R14, [R4.64+0x4] ; /* 0x00000406040e9981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ @!P2 LDG.E R15, [R6.64+0x8] ; /* 0x00000806060fa981 */
/* 0x000f28000c1e1900 */
/*04f0*/ @!P2 LDG.E R16, [R4.64+0x8] ; /* 0x000008060410a981 */
/* 0x000f28000c1e1900 */
/*0500*/ @!P3 LDG.E R17, [R6.64+0xc] ; /* 0x00000c060611b981 */
/* 0x000f68000c1e1900 */
/*0510*/ @!P3 LDG.E R18, [R4.64+0xc] ; /* 0x00000c060412b981 */
/* 0x000f62000c1e1900 */
/*0520*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0530*/ IADD3 R8, P4, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fca0007f9e0ff */
/*0540*/ IMAD.X R9, RZ, RZ, R9, P4 ; /* 0x000000ffff097224 */
/* 0x000fe400020e0609 */
/*0550*/ @!P0 FFMA R2, R11, R12, R2 ; /* 0x0000000c0b028223 */
/* 0x004fe20000000002 */
/*0560*/ ISETP.GE.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fc60003f06270 */
/*0570*/ @!P1 FFMA R2, R13, R14, R2 ; /* 0x0000000e0d029223 */
/* 0x008fe20000000002 */
/*0580*/ IADD3 R11, P1, R4, 0x10, RZ ; /* 0x00000010040b7810 */
/* 0x000fc60007f3e0ff */
/*0590*/ @!P2 FFMA R2, R15, R16, R2 ; /* 0x000000100f02a223 */
/* 0x010fe40000000002 */
/*05a0*/ IMAD.X R12, RZ, RZ, R5, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe400008e0605 */
/*05b0*/ @!P3 FFMA R2, R17, R18, R2 ; /* 0x000000121102b223 */
/* 0x020fe40000000002 */
/*05c0*/ @!P0 BRA 0x3c0 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*05d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*05f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*0600*/ STG.E [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27convolution_1D_basic_kernelPfS_S_ii
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.p2align 8
.type _Z27convolution_1D_basic_kernelPfS_S_ii,@function
_Z27convolution_1D_basic_kernelPfS_S_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x1c
s_lshr_b32 s8, s2, 31
v_mov_b32_e32 v3, 0
s_add_i32 s8, s2, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s8, s8, 1
v_subrev_nc_u32_e32 v2, s8, v1
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, s2, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 1, v2
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v2, v4
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_5
.LBB0_3:
v_cmp_lt_i32_e32 vcc_lo, -1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, vcc_lo, s2
s_and_saveexec_b32 s2, s9
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_load_b32 s9, s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s9, v5
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_branch .LBB0_7
.LBB0_6:
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27convolution_1D_basic_kernelPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27convolution_1D_basic_kernelPfS_S_ii, .Lfunc_end0-_Z27convolution_1D_basic_kernelPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27convolution_1D_basic_kernelPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27convolution_1D_basic_kernelPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000050b6_00000000-6_1dConv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
.type _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii, @function
_Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z27convolution_1D_basic_kernelPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii, .-_Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.type _Z27convolution_1D_basic_kernelPfS_S_ii, @function
_Z27convolution_1D_basic_kernelPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z27convolution_1D_basic_kernelPfS_S_ii, .-_Z27convolution_1D_basic_kernelPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "error while allocating Pd\n"
.LC1:
.string "error while allocating Md\n"
.LC2:
.string "error while allocating arrd\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "error while copyting arr from host to device\n"
.align 8
.LC4:
.string "error while copyting mask from host to device\n"
.section .rodata.str1.1
.LC5:
.string "Time Taken = %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77840
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2656, %rsp
.cfi_def_cfa_offset 80496
movq %fs:40, %rax
movq %rax, 80472(%rsp)
xorl %eax, %eax
movl $0, %edx
.L15:
cmpl $99, %edx
jle .L25
movl %edx, %ecx
imull %edx, %ecx
movslq %ecx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 464(%rsp,%rdx,4)
addq $1, %rdx
cmpq $10000, %rdx
jne .L15
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
.L16:
leaq 32(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
.L17:
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
.L18:
leaq 464(%rsp), %rsi
movl $1, %ecx
movl $40000, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
.L19:
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $400, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
.L20:
call clock@PLT
negq %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd %xmm1, 8(%rsp)
movl $20, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $500, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L21:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd 8(%rsp), %xmm0
movq %xmm0, %rbx
leaq 40464(%rsp), %rdi
movl $2, %ecx
movl $40000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
.L22:
movq %rbx, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 80472(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $80480, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movslq %edx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 64(%rsp,%rdx,4)
movl %edx, %ecx
imull %edx, %ecx
movslq %ecx, %rax
imulq $1759218605, %rax, %rax
sarq $44, %rax
sarl $31, %ecx
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 464(%rsp,%rdx,4)
addq $1, %rdx
jmp .L15
.L26:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L27:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L29:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L19
.L30:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L31:
movl $10000, %r8d
movl $100, %ecx
movq 16(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z53__device_stub__Z27convolution_1D_basic_kernelPfS_S_iiPfS_S_ii
jmp .L21
.L32:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC6:
.string "_Z27convolution_1D_basic_kernelPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z27convolution_1D_basic_kernelPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "1dConv.hip"
.globl _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii # -- Begin function _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.p2align 4, 0x90
.type _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii,@function
_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii: # @_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii, .Lfunc_end0-_Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $80520, %rsp # imm = 0x13A88
.cfi_def_cfa_offset 80544
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
movl $3518437209, %ecx # imm = 0xD1B71759
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl %eax, %edx
imull %edx, %edx
imulq %rcx, %rdx
shrq $45, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, 40512(%rsp,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpq $99, %rax
ja .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl $0, 112(%rsp,%rax,4)
jmp .LBB1_3
.LBB1_4:
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_6:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl $.Lstr.1, %edi
callq puts@PLT
.LBB1_8:
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %eax, %eax
je .LBB1_10
# %bb.9:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB1_10:
movq 16(%rsp), %rdi
leaq 40512(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_12
# %bb.11:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB1_12:
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $400, %edx # imm = 0x190
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_14
# %bb.13:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB1_14:
callq clock
movq %rax, %rbx
movabsq $4294967316, %rdx # imm = 0x100000014
leaq 480(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_16
# %bb.15:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $100, 36(%rsp)
movl $10000, 32(%rsp) # imm = 0x2710
leaq 104(%rsp), %rax
movq %rax, 512(%rsp)
leaq 96(%rsp), %rax
movq %rax, 520(%rsp)
leaq 88(%rsp), %rax
movq %rax, 528(%rsp)
leaq 36(%rsp), %rax
movq %rax, 536(%rsp)
leaq 32(%rsp), %rax
movq %rax, 544(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 512(%rsp), %r9
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_16:
callq clock
movq %rax, %r14
movq 24(%rsp), %rsi
leaq 512(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_18
# %bb.17:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB1_18:
negq %rbx
cvtsi2sd %rbx, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
addsd %xmm1, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80520, %rsp # imm = 0x13A88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27convolution_1D_basic_kernelPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27convolution_1D_basic_kernelPfS_S_ii,@object # @_Z27convolution_1D_basic_kernelPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z27convolution_1D_basic_kernelPfS_S_ii
.p2align 3, 0x0
_Z27convolution_1D_basic_kernelPfS_S_ii:
.quad _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.size _Z27convolution_1D_basic_kernelPfS_S_ii, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Time Taken = %lf\n"
.size .L.str.5, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z27convolution_1D_basic_kernelPfS_S_ii"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "error while allocating Pd"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "error while allocating Md"
.size .Lstr.1, 26
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "error while allocating arrd"
.size .Lstr.2, 28
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "error while copyting mask from host to device"
.size .Lstr.4, 46
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "error while copyting arr from host to device"
.size .Lstr.5, 45
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__convolution_1D_basic_kernelPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27convolution_1D_basic_kernelPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // https://devblogs.nvidia.com/even-easier-introduction-cuda/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <math.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add(int n, float * x, float *y)
{
for (int i = 0; i < n; i++)
{
y[i] = x[i] + y[i];
}
}
__global__
void add2(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = 0; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
__global__
void add3(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
printf("below is our codes:\n");
int N = 1 << 20;
float *x, *y;
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
add <<<1, 1 >>> (N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
/*for (auto i : *y)
{
std::cout << i << " ";
}
std::cout << std::endl;*/
std::cout <<"Result is" << *y << std::endl;
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
;
// Free memory
cudaFree(x);
cudaFree(y);
//---------------------------
int N2 = 1 << 20;
float *x2, *y2;
cudaMallocManaged(&x2, N2 * sizeof(float));
cudaMallocManaged(&y2, N2 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N2; i++) {
x2[i] = 1.0f;
y2[i] = 2.0f;
}
add2 <<<1, 256 >>> (N2, x2, y2);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
std::cout << "Result2 is " << *y2 << std::endl;
// Free memory
cudaFree(x2);
cudaFree(y2);
//---------------------------
int N3 = 1 << 20;
float *x3, *y3;
cudaMallocManaged(&x3, N3 * sizeof(float));
cudaMallocManaged(&y3, N3 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N3; i++) {
x3[i] = 4.0f;
y3[i] = 2.0f;
}
add2 <<<1, 256 >>> (N3, x3, y3);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
std::cout << "Result3 is " << *y3 << std::endl;
// Free memory
cudaFree(x3);
cudaFree(y3);
int N4 = 1 << 20;
float *x4, *y4;
int blocksize = 256;
int numofblock = (N4 + blocksize - 1) / blocksize;
cudaMallocManaged(&x4, N4 * sizeof(float));
cudaMallocManaged(&y4, N4 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N4; i++) {
x4[i] = 4.0f;
y4[i] = 9.0f;
}
add3 <<<numofblock, blocksize >>> (N4, x4, y4);
cudaDeviceSynchronize();
std::cout << "Result4 is " << *y4 << std::endl;
// Free memory
cudaFree(x4);
cudaFree(y4);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | .file "tmpxft_00125270_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "cudaMalloc failed!"
.LC2:
.string "cudaMemcpy failed!"
.LC3:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "cudaDeviceSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z11addWithCudaPiPKiS1_j
.type _Z11addWithCudaPiPKiS1_j, @function
_Z11addWithCudaPiPKiS1_j:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L24
movl %ebp, %r15d
salq $2, %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L25
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L29
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L19:
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L31
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L32
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L13
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L24:
movl %eax, %ebx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L30:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L19
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L32:
movl %eax, %ecx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z11addWithCudaPiPKiS1_j, .-_Z11addWithCudaPiPKiS1_j
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z3addiPfS_, .-_Z3addiPfS_
.globl _Z26__device_stub__Z4add2iPfS_iPfS_
.type _Z26__device_stub__Z4add2iPfS_iPfS_, @function
_Z26__device_stub__Z4add2iPfS_iPfS_:
.LFB3699:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4add2iPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z26__device_stub__Z4add2iPfS_iPfS_, .-_Z26__device_stub__Z4add2iPfS_iPfS_
.globl _Z4add2iPfS_
.type _Z4add2iPfS_, @function
_Z4add2iPfS_:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4add2iPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z4add2iPfS_, .-_Z4add2iPfS_
.globl _Z26__device_stub__Z4add3iPfS_iPfS_
.type _Z26__device_stub__Z4add3iPfS_iPfS_, @function
_Z26__device_stub__Z4add3iPfS_iPfS_:
.LFB3701:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4add3iPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z26__device_stub__Z4add3iPfS_iPfS_, .-_Z26__device_stub__Z4add3iPfS_iPfS_
.globl _Z4add3iPfS_
.type _Z4add3iPfS_, @function
_Z4add3iPfS_:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4add3iPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z4add3iPfS_, .-_Z4add3iPfS_
.section .rodata.str1.1
.LC6:
.string "addWithCuda failed!"
.section .rodata.str1.8
.align 8
.LC7:
.string "{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n"
.section .rodata.str1.1
.LC8:
.string "cudaDeviceReset failed!"
.LC9:
.string "below is our codes:\n"
.LC12:
.string "Result is"
.LC15:
.string "Max error: "
.LC16:
.string "Result2 is "
.LC18:
.string "Result3 is "
.LC20:
.string "Result4 is "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $216, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl $1, 112(%rsp)
movl $2, 116(%rsp)
movl $3, 120(%rsp)
movl $4, 124(%rsp)
movl $5, 128(%rsp)
movl $10, 144(%rsp)
movl $20, 148(%rsp)
movl $30, 152(%rsp)
movl $40, 156(%rsp)
movl $50, 160(%rsp)
pxor %xmm0, %xmm0
movaps %xmm0, 176(%rsp)
movl $0, 192(%rsp)
leaq 144(%rsp), %rdx
leaq 112(%rsp), %rsi
leaq 176(%rsp), %rdi
movl $5, %ecx
call _Z11addWithCudaPiPKiS1_j
testl %eax, %eax
jne .L78
subq $8, %rsp
.cfi_def_cfa_offset 248
movl 200(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 256
movl 204(%rsp), %r9d
movl 200(%rsp), %r8d
movl 196(%rsp), %ecx
movl 192(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L79
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC10(%rip), %xmm1
movss .LC11(%rip), %xmm0
.L62:
movq 24(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 32(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L62
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L63:
call cudaDeviceSynchronize@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L64:
movss (%rbx), %xmm0
subss .LC13(%rip), %xmm0
andps .LC14(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L64
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC10(%rip), %xmm1
movss .LC11(%rip), %xmm0
.L65:
movq 40(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 48(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L65
movl $256, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L81
.L66:
call cudaDeviceSynchronize@PLT
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 64(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC17(%rip), %xmm1
movss .LC11(%rip), %xmm0
.L67:
movq 56(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 64(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L67
movl $256, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L68:
call cudaDeviceSynchronize@PLT
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
leaq 72(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 80(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC17(%rip), %xmm1
movss .LC19(%rip), %xmm0
.L69:
movq 72(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 80(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L69
movl $256, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $4096, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L83
.L70:
call cudaDeviceSynchronize@PLT
leaq .LC20(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 80(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L58:
movq 200(%rsp), %rdx
subq %fs:40, %rdx
jne .L84
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L58
.L79:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L58
.L80:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L63
.L81:
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z4add2iPfS_iPfS_
jmp .L66
.L82:
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z4add2iPfS_iPfS_
jmp .L68
.L83:
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movl $1048576, %edi
call _Z26__device_stub__Z4add3iPfS_iPfS_
jmp .L70
.L84:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z4add3iPfS_"
.LC23:
.string "_Z4add2iPfS_"
.LC24:
.string "_Z3addiPfS_"
.LC25:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add3iPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z4add2iPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC10:
.long 1065353216
.align 4
.LC11:
.long 1073741824
.align 4
.LC13:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC14:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4
.align 4
.LC17:
.long 1082130432
.align 4
.LC19:
.long 1091567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // https://devblogs.nvidia.com/even-easier-introduction-cuda/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <math.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add(int n, float * x, float *y)
{
for (int i = 0; i < n; i++)
{
y[i] = x[i] + y[i];
}
}
__global__
void add2(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = 0; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
__global__
void add3(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = cudaDeviceReset();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceReset failed!");
return 1;
}
printf("below is our codes:\n");
int N = 1 << 20;
float *x, *y;
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
add <<<1, 1 >>> (N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
/*for (auto i : *y)
{
std::cout << i << " ";
}
std::cout << std::endl;*/
std::cout <<"Result is" << *y << std::endl;
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
;
// Free memory
cudaFree(x);
cudaFree(y);
//---------------------------
int N2 = 1 << 20;
float *x2, *y2;
cudaMallocManaged(&x2, N2 * sizeof(float));
cudaMallocManaged(&y2, N2 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N2; i++) {
x2[i] = 1.0f;
y2[i] = 2.0f;
}
add2 <<<1, 256 >>> (N2, x2, y2);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
std::cout << "Result2 is " << *y2 << std::endl;
// Free memory
cudaFree(x2);
cudaFree(y2);
//---------------------------
int N3 = 1 << 20;
float *x3, *y3;
cudaMallocManaged(&x3, N3 * sizeof(float));
cudaMallocManaged(&y3, N3 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N3; i++) {
x3[i] = 4.0f;
y3[i] = 2.0f;
}
add2 <<<1, 256 >>> (N3, x3, y3);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
std::cout << "Result3 is " << *y3 << std::endl;
// Free memory
cudaFree(x3);
cudaFree(y3);
int N4 = 1 << 20;
float *x4, *y4;
int blocksize = 256;
int numofblock = (N4 + blocksize - 1) / blocksize;
cudaMallocManaged(&x4, N4 * sizeof(float));
cudaMallocManaged(&y4, N4 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N4; i++) {
x4[i] = 4.0f;
y4[i] = 9.0f;
}
add3 <<<numofblock, blocksize >>> (N4, x4, y4);
cudaDeviceSynchronize();
std::cout << "Result4 is " << *y4 << std::endl;
// Free memory
cudaFree(x4);
cudaFree(y4);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaDeviceSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | // https://devblogs.nvidia.com/even-easier-introduction-cuda/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <math.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add(int n, float * x, float *y)
{
for (int i = 0; i < n; i++)
{
y[i] = x[i] + y[i];
}
}
__global__
void add2(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = 0; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
__global__
void add3(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
hipError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
printf("below is our codes:\n");
int N = 1 << 20;
float *x, *y;
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
add <<<1, 1 >>> (N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
/*for (auto i : *y)
{
std::cout << i << " ";
}
std::cout << std::endl;*/
std::cout <<"Result is" << *y << std::endl;
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
;
// Free memory
hipFree(x);
hipFree(y);
//---------------------------
int N2 = 1 << 20;
float *x2, *y2;
hipMallocManaged(&x2, N2 * sizeof(float));
hipMallocManaged(&y2, N2 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N2; i++) {
x2[i] = 1.0f;
y2[i] = 2.0f;
}
add2 <<<1, 256 >>> (N2, x2, y2);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "Result2 is " << *y2 << std::endl;
// Free memory
hipFree(x2);
hipFree(y2);
//---------------------------
int N3 = 1 << 20;
float *x3, *y3;
hipMallocManaged(&x3, N3 * sizeof(float));
hipMallocManaged(&y3, N3 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N3; i++) {
x3[i] = 4.0f;
y3[i] = 2.0f;
}
add2 <<<1, 256 >>> (N3, x3, y3);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "Result3 is " << *y3 << std::endl;
// Free memory
hipFree(x3);
hipFree(y3);
int N4 = 1 << 20;
float *x4, *y4;
int blocksize = 256;
int numofblock = (N4 + blocksize - 1) / blocksize;
hipMallocManaged(&x4, N4 * sizeof(float));
hipMallocManaged(&y4, N4 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N4; i++) {
x4[i] = 4.0f;
y4[i] = 9.0f;
}
add3 <<<numofblock, blocksize >>> (N4, x4, y4);
hipDeviceSynchronize();
std::cout << "Result4 is " << *y4 << std::endl;
// Free memory
hipFree(x4);
hipFree(y4);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // https://devblogs.nvidia.com/even-easier-introduction-cuda/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <math.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add(int n, float * x, float *y)
{
for (int i = 0; i < n; i++)
{
y[i] = x[i] + y[i];
}
}
__global__
void add2(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = 0; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
__global__
void add3(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
hipError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
printf("below is our codes:\n");
int N = 1 << 20;
float *x, *y;
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
add <<<1, 1 >>> (N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
/*for (auto i : *y)
{
std::cout << i << " ";
}
std::cout << std::endl;*/
std::cout <<"Result is" << *y << std::endl;
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
;
// Free memory
hipFree(x);
hipFree(y);
//---------------------------
int N2 = 1 << 20;
float *x2, *y2;
hipMallocManaged(&x2, N2 * sizeof(float));
hipMallocManaged(&y2, N2 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N2; i++) {
x2[i] = 1.0f;
y2[i] = 2.0f;
}
add2 <<<1, 256 >>> (N2, x2, y2);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "Result2 is " << *y2 << std::endl;
// Free memory
hipFree(x2);
hipFree(y2);
//---------------------------
int N3 = 1 << 20;
float *x3, *y3;
hipMallocManaged(&x3, N3 * sizeof(float));
hipMallocManaged(&y3, N3 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N3; i++) {
x3[i] = 4.0f;
y3[i] = 2.0f;
}
add2 <<<1, 256 >>> (N3, x3, y3);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "Result3 is " << *y3 << std::endl;
// Free memory
hipFree(x3);
hipFree(y3);
int N4 = 1 << 20;
float *x4, *y4;
int blocksize = 256;
int numofblock = (N4 + blocksize - 1) / blocksize;
hipMallocManaged(&x4, N4 * sizeof(float));
hipMallocManaged(&y4, N4 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N4; i++) {
x4[i] = 4.0f;
y4[i] = 9.0f;
}
add3 <<<numofblock, blocksize >>> (N4, x4, y4);
hipDeviceSynchronize();
std::cout << "Result4 is " << *y4 << std::endl;
// Free memory
hipFree(x4);
hipFree(y4);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB1_3
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
.LBB1_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z3addiPfS_, .Lfunc_end1-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4add2iPfS_
.globl _Z4add2iPfS_
.p2align 8
.type _Z4add2iPfS_,@function
_Z4add2iPfS_:
s_load_b32 s6, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
s_cbranch_scc1 .LBB2_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s7, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s10, s7
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b64 s[4:5], 0
s_lshl_b32 s9, s8, 2
.LBB2_2:
s_add_u32 s12, s0, s4
s_addc_u32 s13, s1, s5
s_add_u32 s14, s2, s4
s_addc_u32 s15, s3, s5
s_clause 0x1
global_load_b32 v1, v0, s[12:13]
global_load_b32 v2, v0, s[14:15]
s_add_i32 s10, s10, s8
s_add_u32 s4, s4, s9
s_addc_u32 s5, s5, s7
s_cmp_ge_i32 s10, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[14:15]
s_cbranch_scc0 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add2iPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z4add2iPfS_, .Lfunc_end2-_Z4add2iPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4add3iPfS_
.globl _Z4add3iPfS_
.p2align 8
.type _Z4add3iPfS_,@function
_Z4add3iPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB3_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB3_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e64 s0, s10, v1
global_store_b32 v[6:7], v0, off
s_or_b32 s1, s0, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4add3iPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z4add3iPfS_, .Lfunc_end3-_Z4add3iPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add2iPfS_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4add2iPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4add3iPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4add3iPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // https://devblogs.nvidia.com/even-easier-introduction-cuda/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <math.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
__global__
void add(int n, float * x, float *y)
{
for (int i = 0; i < n; i++)
{
y[i] = x[i] + y[i];
}
}
__global__
void add2(int n, float *x, float *y)
{
int index = threadIdx.x;
int stride = blockDim.x;
for (int i = 0; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
__global__
void add3(int n, float *x, float *y)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i+=stride)
{
y[i] = x[i] + y[i];
}
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
// Add vectors in parallel.
hipError_t cudaStatus = addWithCuda(c, a, b, arraySize);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addWithCuda failed!");
return 1;
}
printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
c[0], c[1], c[2], c[3], c[4]);
// cudaDeviceReset must be called before exiting in order for profiling and
// tracing tools such as Nsight and Visual Profiler to show complete traces.
cudaStatus = hipDeviceReset();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceReset failed!");
return 1;
}
printf("below is our codes:\n");
int N = 1 << 20;
float *x, *y;
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; i++) {
x[i] = 1.0f;
y[i] = 2.0f;
}
add <<<1, 1 >>> (N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
/*for (auto i : *y)
{
std::cout << i << " ";
}
std::cout << std::endl;*/
std::cout <<"Result is" << *y << std::endl;
// Check for errors (all values should be 3.0f)
float maxError = 0.0f;
for (int i = 0; i < N; i++)
maxError = fmax(maxError, fabs(y[i] - 3.0f));
std::cout << "Max error: " << maxError << std::endl;
;
// Free memory
hipFree(x);
hipFree(y);
//---------------------------
int N2 = 1 << 20;
float *x2, *y2;
hipMallocManaged(&x2, N2 * sizeof(float));
hipMallocManaged(&y2, N2 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N2; i++) {
x2[i] = 1.0f;
y2[i] = 2.0f;
}
add2 <<<1, 256 >>> (N2, x2, y2);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "Result2 is " << *y2 << std::endl;
// Free memory
hipFree(x2);
hipFree(y2);
//---------------------------
int N3 = 1 << 20;
float *x3, *y3;
hipMallocManaged(&x3, N3 * sizeof(float));
hipMallocManaged(&y3, N3 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N3; i++) {
x3[i] = 4.0f;
y3[i] = 2.0f;
}
add2 <<<1, 256 >>> (N3, x3, y3);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
std::cout << "Result3 is " << *y3 << std::endl;
// Free memory
hipFree(x3);
hipFree(y3);
int N4 = 1 << 20;
float *x4, *y4;
int blocksize = 256;
int numofblock = (N4 + blocksize - 1) / blocksize;
hipMallocManaged(&x4, N4 * sizeof(float));
hipMallocManaged(&y4, N4 * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N4; i++) {
x4[i] = 4.0f;
y4[i] = 9.0f;
}
add3 <<<numofblock, blocksize >>> (N4, x4, y4);
hipDeviceSynchronize();
std::cout << "Result4 is " << *y4 << std::endl;
// Free memory
hipFree(x4);
hipFree(y4);
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// Check for any errors launching the kernel
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
goto Error;
}
// cudaDeviceSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z18__device_stub__addiPfS_, .Lfunc_end1-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__add2iPfS_ # -- Begin function _Z19__device_stub__add2iPfS_
.p2align 4, 0x90
.type _Z19__device_stub__add2iPfS_,@function
_Z19__device_stub__add2iPfS_: # @_Z19__device_stub__add2iPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4add2iPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z19__device_stub__add2iPfS_, .Lfunc_end2-_Z19__device_stub__add2iPfS_
.cfi_endproc
# -- End function
.globl _Z19__device_stub__add3iPfS_ # -- Begin function _Z19__device_stub__add3iPfS_
.p2align 4, 0x90
.type _Z19__device_stub__add3iPfS_,@function
_Z19__device_stub__add3iPfS_: # @_Z19__device_stub__add3iPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4add3iPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z19__device_stub__add3iPfS_, .Lfunc_end3-_Z19__device_stub__add3iPfS_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI4_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI4_1:
.long 10 # 0xa
.long 20 # 0x14
.long 30 # 0x1e
.long 40 # 0x28
.LCPI4_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_2:
.long 0xc0400000 # float -3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 224(%rsp)
movl $5, 240(%rsp)
movaps .LCPI4_1(%rip), %xmm0 # xmm0 = [10,20,30,40]
movaps %xmm0, 192(%rsp)
movl $50, 208(%rsp)
xorps %xmm0, %xmm0
movaps %xmm0, 160(%rsp)
movl $0, 176(%rsp)
leaq 160(%rsp), %rdi
leaq 224(%rsp), %rsi
leaq 192(%rsp), %rdx
movl $5, %ecx
callq _Z11addWithCudaPiPKiS1_j
testl %eax, %eax
jne .LBB4_1
# %bb.3:
movl 160(%rsp), %esi
movl 164(%rsp), %edx
movl 168(%rsp), %ecx
movl 172(%rsp), %r8d
movl 176(%rsp), %r9d
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
callq hipDeviceReset
testl %eax, %eax
jne .LBB4_4
# %bb.5:
movl $.Lstr, %edi
callq puts@PLT
leaq 144(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 88(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 144(%rsp), %rax
xorl %ecx, %ecx
movq 88(%rsp), %rdx
.p2align 4, 0x90
.LBB4_6: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB4_6
# %bb.7:
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8:
movq 144(%rsp), %rax
movq 88(%rsp), %rcx
movl $1048576, 80(%rsp) # imm = 0x100000
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 88(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_45
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_12
# %bb.11:
movzbl 67(%r14), %ecx
jmp .LBB4_13
.LBB4_12:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB4_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 88(%rsp), %rcx
movss .LCPI4_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI4_3(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB4_14: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB4_14
# %bb.15:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $11, %edx
movaps %xmm5, 256(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 256(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_45
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r14)
je .LBB4_18
# %bb.17:
movzbl 67(%r14), %ecx
jmp .LBB4_19
.LBB4_18:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB4_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 144(%rsp), %rdi
callq hipFree
movq 88(%rsp), %rdi
callq hipFree
leaq 80(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 136(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 80(%rsp), %rax
xorl %ecx, %ecx
movq 136(%rsp), %rdx
.p2align 4, 0x90
.LBB4_20: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB4_20
# %bb.21:
leaq 255(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 80(%rsp), %rax
movq 136(%rsp), %rcx
movl $1048576, 72(%rsp) # imm = 0x100000
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4add2iPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 136(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_45
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r15)
je .LBB4_26
# %bb.25:
movzbl 67(%r15), %ecx
jmp .LBB4_27
.LBB4_26:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 80(%rsp), %rdi
callq hipFree
movq 136(%rsp), %rdi
callq hipFree
leaq 72(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 128(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 72(%rsp), %rax
xorl %ecx, %ecx
movq 128(%rsp), %rdx
.p2align 4, 0x90
.LBB4_28: # =>This Inner Loop Header: Depth=1
movl $1082130432, (%rax,%rcx,4) # imm = 0x40800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB4_28
# %bb.29:
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_31
# %bb.30:
movq 72(%rsp), %rax
movq 128(%rsp), %rcx
movl $1048576, 64(%rsp) # imm = 0x100000
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4add2iPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_31:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 128(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB4_45
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
cmpb $0, 56(%r15)
je .LBB4_34
# %bb.33:
movzbl 67(%r15), %ecx
jmp .LBB4_35
.LBB4_34:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB4_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 72(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipFree
leaq 64(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 120(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 64(%rsp), %rax
xorl %ecx, %ecx
movq 120(%rsp), %rdx
.p2align 4, 0x90
.LBB4_36: # =>This Inner Loop Header: Depth=1
movl $1082130432, (%rax,%rcx,4) # imm = 0x40800000
movl $1091567616, (%rdx,%rcx,4) # imm = 0x41100000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB4_36
# %bb.37:
addq $4095, %rbx # imm = 0xFFF
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_39
# %bb.38:
movq 64(%rsp), %rax
movq 120(%rsp), %rcx
movl $1048576, 156(%rsp) # imm = 0x100000
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 156(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4add3iPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_39:
callq hipDeviceSynchronize
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 120(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB4_45
# %bb.40: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i104
cmpb $0, 56(%rbx)
je .LBB4_42
# %bb.41:
movzbl 67(%rbx), %ecx
jmp .LBB4_43
.LBB4_42:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB4_43: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit107
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 64(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipFree
xorl %eax, %eax
.LBB4_44:
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 320
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $19, %esi
jmp .LBB4_2
.LBB4_4:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $22, %esi
.LBB4_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB4_44
.LBB4_45:
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKiS1_j # -- Begin function _Z11addWithCudaPiPKiS1_j
.p2align 4, 0x90
.type _Z11addWithCudaPiPKiS1_j,@function
_Z11addWithCudaPiPKiS1_j: # @_Z11addWithCudaPiPKiS1_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_18
# %bb.1:
movl %ebp, %r15d
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_13
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_13
# %bb.6:
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r15
orq $1, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
callq hipGetLastError
testl %eax, %eax
jne .LBB5_19
# %bb.9:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_20
# %bb.10:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB5_17
# %bb.11:
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB5_16
.LBB5_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.10, %edi
jmp .LBB5_14
.LBB5_13:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
.LBB5_14:
movl $17, %esi
.LBB5_15:
movl $1, %edx
.LBB5_16:
callq fwrite@PLT
.LBB5_17:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_18:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.9, %edi
movl $63, %esi
jmp .LBB5_15
.LBB5_19:
movq stderr(%rip), %r14
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movq %r14, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB5_17
.LBB5_20:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB5_17
.Lfunc_end5:
.size _Z11addWithCudaPiPKiS1_j, .Lfunc_end5-_Z11addWithCudaPiPKiS1_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add2iPfS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4add3iPfS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type _Z4add2iPfS_,@object # @_Z4add2iPfS_
.globl _Z4add2iPfS_
.p2align 3, 0x0
_Z4add2iPfS_:
.quad _Z19__device_stub__add2iPfS_
.size _Z4add2iPfS_, 8
.type _Z4add3iPfS_,@object # @_Z4add3iPfS_
.globl _Z4add3iPfS_
.p2align 3, 0x0
_Z4add3iPfS_:
.quad _Z19__device_stub__add3iPfS_
.size _Z4add3iPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "addWithCuda failed!"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n"
.size .L.str.1, 51
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipDeviceReset failed!"
.size .L.str.2, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Result is"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Max error: "
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Result2 is "
.size .L.str.6, 12
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Result3 is "
.size .L.str.7, 12
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Result4 is "
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.9, 64
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "hipMalloc failed!"
.size .L.str.10, 18
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "hipMemcpy failed!"
.size .L.str.11, 18
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "addKernel launch failed: %s\n"
.size .L.str.12, 29
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.13, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z3addiPfS_"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z4add2iPfS_"
.size .L__unnamed_3, 13
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z4add3iPfS_"
.size .L__unnamed_4, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "below is our codes:"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym _Z19__device_stub__add2iPfS_
.addrsig_sym _Z19__device_stub__add3iPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym _Z3addiPfS_
.addrsig_sym _Z4add2iPfS_
.addrsig_sym _Z4add3iPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int *c)
{
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int i,a[10000],b[10000],c[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
printf("Enter array elements of array B\n");
for(i=0;i<n;i++)
scanf("%d",&b[i]);
int *d_a,*d_b,*d_c;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMalloc((void **)&d_c,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
add<<<1,n>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*n,cudaMemcpyDeviceToHost);
printf("Sum array is :");
for(i=0;i<n;i++)
printf("%d\t",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int *c)
{
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int i,a[10000],b[10000],c[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
printf("Enter array elements of array B\n");
for(i=0;i<n;i++)
scanf("%d",&b[i]);
int *d_a,*d_b,*d_c;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMalloc((void **)&d_c,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
add<<<1,n>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*n,cudaMemcpyDeviceToHost);
printf("Sum array is :");
for(i=0;i<n;i++)
printf("%d\t",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000eea0e_00000000-6_ArraySum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of N:"
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter array elements of array A\n"
.align 8
.LC3:
.string "Enter array elements of array B\n"
.section .rodata.str1.1
.LC4:
.string "Sum array is :"
.LC5:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -118784(%rsp), %r11
.cfi_def_cfa 11, 118816
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1296, %rsp
.cfi_def_cfa_offset 120112
movq %fs:40, %rax
movq %rax, 120072(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L12
leaq 64(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 12(%rsp)
jg .L13
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %esi
testl %esi, %esi
jle .L14
leaq 40064(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L15:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 12(%rsp), %esi
addq $4, %rbp
cmpl %ebx, %esi
jg .L15
.L14:
sall $2, %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 40064(%rsp), %rsi
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 80064(%rsp), %rdi
movl $2, %ecx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L18:
movl 80064(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L18
.L17:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 120072(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $120080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int *c)
{
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int i,a[10000],b[10000],c[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
printf("Enter array elements of array B\n");
for(i=0;i<n;i++)
scanf("%d",&b[i]);
int *d_a,*d_b,*d_c;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMalloc((void **)&d_c,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
add<<<1,n>>>(d_a,d_b,d_c);
cudaMemcpy(c,d_c,size*n,cudaMemcpyDeviceToHost);
printf("Sum array is :");
for(i=0;i<n;i++)
printf("%d\t",c[i]);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int *c)
{
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int i,a[10000],b[10000],c[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
printf("Enter array elements of array B\n");
for(i=0;i<n;i++)
scanf("%d",&b[i]);
int *d_a,*d_b,*d_c;
int size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMalloc((void **)&d_c,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
add<<<1,n>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size*n,hipMemcpyDeviceToHost);
printf("Sum array is :");
for(i=0;i<n;i++)
printf("%d\t",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int *c)
{
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int i,a[10000],b[10000],c[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
printf("Enter array elements of array B\n");
for(i=0;i<n;i++)
scanf("%d",&b[i]);
int *d_a,*d_b,*d_c;
int size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMalloc((void **)&d_c,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
add<<<1,n>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size*n,hipMemcpyDeviceToHost);
printf("Sum array is :");
for(i=0;i<n;i++)
printf("%d\t",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void add(int *a,int *b,int *c)
{
int tid = threadIdx.x;
c[tid] = a[tid] + b[tid];
}
int main(void)
{
int i,a[10000],b[10000],c[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
printf("Enter array elements of array B\n");
for(i=0;i<n;i++)
scanf("%d",&b[i]);
int *d_a,*d_b,*d_c;
int size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMalloc((void **)&d_c,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
add<<<1,n>>>(d_a,d_b,d_c);
hipMemcpy(c,d_c,size*n,hipMemcpyDeviceToHost);
printf("Sum array is :");
for(i=0;i<n;i++)
printf("%d\t",c[i]);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "ArraySum.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120120, %rsp # imm = 0x1D538
.cfi_def_cfa_offset 120144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 80112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph24.preheader
leaq 40112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph24
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_5
.LBB1_6: # %._crit_edge25
shll $2, %eax
movslq %eax, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 80112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 40112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph28.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph28
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge29
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120120, %rsp # imm = 0x1D538
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter value of N:"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Sum array is :"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter array elements of array A"
.size .Lstr, 32
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter array elements of array B"
.size .Lstr.1, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eea0e_00000000-6_ArraySum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of N:"
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter array elements of array A\n"
.align 8
.LC3:
.string "Enter array elements of array B\n"
.section .rodata.str1.1
.LC4:
.string "Sum array is :"
.LC5:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -118784(%rsp), %r11
.cfi_def_cfa 11, 118816
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1296, %rsp
.cfi_def_cfa_offset 120112
movq %fs:40, %rax
movq %rax, 120072(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 12(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L12
leaq 64(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 12(%rsp)
jg .L13
.L12:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %esi
testl %esi, %esi
jle .L14
leaq 40064(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L15:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 12(%rsp), %esi
addq $4, %rbp
cmpl %ebx, %esi
jg .L15
.L14:
sall $2, %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 40064(%rsp), %rsi
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L16:
movl 12(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 80064(%rsp), %rdi
movl $2, %ecx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC5(%rip), %rbp
.L18:
movl 80064(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 12(%rsp)
jg .L18
.L17:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 120072(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $120080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L16
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ArraySum.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120120, %rsp # imm = 0x1D538
.cfi_def_cfa_offset 120144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 80112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph24.preheader
leaq 40112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph24
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_5
.LBB1_6: # %._crit_edge25
shll $2, %eax
movslq %eax, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 80112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 40112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.9: # %.lr.ph28.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # %.lr.ph28
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_10
.LBB1_11: # %._crit_edge29
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120120, %rsp # imm = 0x1D538
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter value of N:"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Sum array is :"
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter array elements of array A"
.size .Lstr, 32
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter array elements of array B"
.size .Lstr.1, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | using namespace std;
#include <iostream>
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <fstream>
//#include "cuPrintf.cu"
#define B0 -2.647866f
#define B1 -0.374927f
#define B2 0.061601f
#define B3 -0.001511f
const long MAX_THREADS = 512;
const long MAX_BLOCK= 65535;
extern "C" void botrix_index (float *tempday_h, float* precday_h, int n, float* output);
extern "C" void init ();
void checkCUDAError(const char* msg);
__global__ void calculate_index(float* tempday, float* precday, int n)
{
int id;
float x, y;
id=(blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
x=tempday[id];
y=precday[id];
if (id<n)
{
if (x!=-9999 && y!=-9999)
{
if (y>=4 && x<40)
{
if (x<12)
x=12;
if (x>32)
x=32;
tempday[id]=powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))) / (1+powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))));
}
else
tempday[id]=0;
}
else
tempday[id]=-9999;
}
}
void init()
{
cudaSetDevice(0);
}
void botrix_index(float *tempday_h, float* precday_h, int n, float* output)
{
float *tempday_d, *precday_d;
long n_threads;
int n_blocks;
int dim_blocks;
dim3 dim_grid;
//selezione device da utilizzare
// cudaSetDevice(0);
//settaggio parametri
n_threads=n;
if (n_threads>MAX_BLOCK*MAX_BLOCK*MAX_THREADS)
{
printf("Troppi threads!\n");
exit(0);
}
dim_blocks=MAX_THREADS;
n_blocks=n_threads/MAX_THREADS+(n_threads%MAX_THREADS==0?0:1);
if (n_blocks<=MAX_BLOCK)
{
dim_grid.x=n_blocks;
dim_grid.y=1;
dim_grid.z=1;
}
else
{
dim_grid.x=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.y=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.z=1;
}
printf("Numero threads per blocco: %d\n",dim_blocks);
printf("Dimensioni grid: x %d, y %d\n",dim_grid.x,dim_grid.y);
//stampa input
// cout << "tempday\n";
// for (int i=0; i<n; i++)
// {
// cout<<tempday_h[i]<<" ";
// }
// cout << endl;
// cout << "precday\n";
// for (int i=0; i<n; i++)
// {
// cout<<precday_h[i]<<" ";
// }
// cout << endl;
//allocazione
cudaMalloc((void**) &precday_d, n*sizeof(float));
cudaMalloc((void**) &tempday_d, n*sizeof(float));
checkCUDAError("Allocazione");
//trasferimento su device
cudaMemcpy(tempday_d,tempday_h, sizeof(float)*n, cudaMemcpyHostToDevice);
cudaMemcpy(precday_d,precday_h, sizeof(float)*n, cudaMemcpyHostToDevice);
checkCUDAError("Trasferimento su device");
//lancio kernel
//cudaPrintfInit();
calculate_index <<< dim_grid, dim_blocks >>>(tempday_d, precday_d, n);
//cudaPrintfDisplay(stdout, true);
checkCUDAError("Kernel");
//trasferimento da device
cudaMemcpy(output,tempday_d, sizeof(float)*n, cudaMemcpyDeviceToHost);
checkCUDAError("Trasferimento da device");
// cout << "output\n";
// for (int i=0; i<n; i++)
// {
// cout<<output[i]<<" ";
// }
// cout << endl;
//deallocazione
cudaFree(precday_d);
cudaFree(tempday_d);
}
int main(int argc, char **argv)
{
fstream tempday, precday;
int n;
float *tempday_h, *precday_h, *output;
//lettura parametri
if (argc<3)
{
printf("./a.out tempday.txt precday.txt lunghezza\n");
exit(0);
}
tempday.open(argv[1],ios::in);
precday.open(argv[2],ios::in);
sscanf(argv[3],"%d",&n);
//allocazione
precday_h = (float*) malloc (n*sizeof(float));
tempday_h = (float*) malloc (n*sizeof(float));
output = (float*) malloc (n*sizeof(float));
checkCUDAError("Allocazione");
//inizializzazione
for (int i=0; i<n; i++)
{
tempday >> tempday_h[i];
precday >> precday_h[i];
}
botrix_index(tempday_h,precday_h,n,output);
//stampa
cout << "Risultato botrite:\n";
for (int i=0; i<n; i++)
{
cout<<output[i]<<" ";
}
//deallocazione
free(precday_h);
free(tempday_h);
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | code for sm_80
Function : _Z15calculate_indexPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc400078e00ff */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ FSETP.NEU.AND P0, PT, R4, -9999, PT ; /* 0xc61c3c000400780b */
/* 0x004fc80003f0d000 */
/*00f0*/ FSETP.NEU.AND P0, PT, R0, -9999, P0 ; /* 0xc61c3c000000780b */
/* 0x008fda000070d000 */
/*0100*/ @!P0 MOV R7, 0xc61c3c00 ; /* 0xc61c3c0000078802 */
/* 0x000fca0000000f00 */
/*0110*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ FSETP.GE.AND P0, PT, R4, 4, PT ; /* 0x408000000400780b */
/* 0x000fc80003f06000 */
/*0140*/ FSETP.LT.AND P0, PT, R0, 40, P0 ; /* 0x422000000000780b */
/* 0x000fda0000701000 */
/*0150*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0003e2000c101904 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ FMNMX.NAN R0, R0, 12, !PT ; /* 0x4140000000007809 */
/* 0x000fe20007820000 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ebff66f ; /* 0x3ebff66fff057424 */
/* 0x000fe200078e00ff */
/*0190*/ BSSY B0, 0x550 ; /* 0x000003b000007945 */
/* 0x000fe20003800000 */
/*01a0*/ FMUL R6, R4, 0.061601001769304275513 ; /* 0x3d7c515504067820 */
/* 0x000fe20000400000 */
/*01b0*/ FMNMX.NAN R0, R0, 32, PT ; /* 0x4200000000007809 */
/* 0x000fe20003820000 */
/*01c0*/ FFMA R5, R4.reuse, -R5, -2.6478660106658935547 ; /* 0xc02976a304057423 */
/* 0x040fe40000000805 */
/*01d0*/ FMUL R4, R4, -0.0015109999803826212883 ; /* 0xbac60cbf04047820 */
/* 0x000fe40000400000 */
/*01e0*/ FFMA R5, R0, R6, R5 ; /* 0x0000000600057223 */
/* 0x000fc40000000005 */
/*01f0*/ FMUL R0, R0, R0 ; /* 0x0000000000007220 */
/* 0x000fc80000400000 */
/*0200*/ FFMA R0, R0, R4, R5 ; /* 0x0000000400007223 */
/* 0x000fe40000000005 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff047424 */
/* 0x000fc600078e00ff */
/*0220*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f0d000 */
/*0230*/ @!P0 BRA 0x540 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0240*/ HFMA2.MMA R6, -RZ, RZ, 0.25, 0 ; /* 0x34000000ff067435 */
/* 0x000fe200000001ff */
/*0250*/ MOV R11, 0x3e9be32a ; /* 0x3e9be32a000b7802 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3dbdd9bd ; /* 0x3dbdd9bdff087424 */
/* 0x000fe200078e00ff */
/*0270*/ FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f4c200 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a2c32e4 ; /* 0x3a2c32e4ff057424 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3eb7e150 ; /* 0x3eb7e150ff047424 */
/* 0x000fe400078e00ff */
/*02a0*/ FFMA R5, R8, R5, 0.0032181653659790754318 ; /* 0x3b52e7db08057423 */
/* 0x000fe40000000005 */
/*02b0*/ FFMA R6, R6, 8388608, RZ ; /* 0x4b00000006067823 */
/* 0x000fc400000000ff */
/*02c0*/ FFMA R4, R4, -R11, 0.10934674739837646484 ; /* 0x3ddff13004047423 */
/* 0x000fe4000000080b */
/*02d0*/ FFMA R7, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b077823 */
/* 0x001fe40000000006 */
/*02e0*/ FFMA R5, R5, R8.reuse, 0.018033718690276145935 ; /* 0x3c93bb7305057423 */
/* 0x080fe40000000008 */
/*02f0*/ FADD R6, R6, -R7 ; /* 0x8000000706067221 */
/* 0x000fe40000000000 */
/*0300*/ FMUL R4, R4, 0.42388311028480529785 ; /* 0x3ed9073504047820 */
/* 0x000fe40000400000 */
/*0310*/ FFMA R5, R5, R8, 0.12022458761930465698 ; /* 0x3df6384f05057423 */
/* 0x000fc40000000008 */
/*0320*/ FFMA R9, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b097823 */
/* 0x000fe40000000006 */
/*0330*/ FMUL R5, R5, 0.092700459063053131104 ; /* 0x3dbdd9bd05057820 */
/* 0x000fe40000400000 */
/*0340*/ FFMA R6, R4, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b04067823 */
/* 0x000fe40000000009 */
/*0350*/ FMUL R9, R5, 3 ; /* 0x4040000005097820 */
/* 0x000fe40000400000 */
/*0360*/ FFMA R6, R11, 1.9251366722983220825e-08, R6 ; /* 0x32a55e340b067823 */
/* 0x000fe40000000006 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff087424 */
/* 0x000fc400078e00ff */
/*0380*/ FFMA R6, R4, R9, R6 ; /* 0x0000000904067223 */
/* 0x000fc80000000006 */
/*0390*/ FFMA R6, R5, 0.3044674992561340332, R6 ; /* 0x3e9be32a05067823 */
/* 0x000fc80000000006 */
/*03a0*/ FADD R5, R7, R6 ; /* 0x0000000607057221 */
/* 0x000fc80000000000 */
/*03b0*/ FMUL R4, R0.reuse, R5.reuse ; /* 0x0000000500047220 */
/* 0x0c0fe40000400000 */
/*03c0*/ FADD R7, -R7, R5 ; /* 0x0000000507077221 */
/* 0x000fe40000000100 */
/*03d0*/ FRND R9, R4 ; /* 0x0000000400097307 */
/* 0x000e220000201000 */
/*03e0*/ FFMA R5, R0, R5, -R4 ; /* 0x0000000500057223 */
/* 0x000fe20000000804 */
/*03f0*/ FSETP.GT.AND P0, PT, |R4|, 152, PT ; /* 0x431800000400780b */
/* 0x000fe20003f04200 */
/*0400*/ FADD R7, R6, -R7 ; /* 0x8000000706077221 */
/* 0x000fc80000000000 */
/*0410*/ FFMA R6, R0, R7, R5 ; /* 0x0000000700067223 */
/* 0x000fe40000000005 */
/*0420*/ F2I.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000ea20000203100 */
/*0430*/ FADD R5, R4, -R9 ; /* 0x8000000904057221 */
/* 0x001fe20000000000 */
/*0440*/ FSETP.GT.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fc60003f24000 */
/*0450*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x000fc80000000000 */
/*0460*/ FFMA R6, R5, R8, 0.0013391353422775864601 ; /* 0x3aaf85ed05067423 */
/* 0x000fc80000000008 */
/*0470*/ FFMA R6, R5, R6, 0.0096188392490148544312 ; /* 0x3c1d985605067423 */
/* 0x000fc80000000006 */
/*0480*/ FFMA R6, R5, R6, 0.055503588169813156128 ; /* 0x3d6357bb05067423 */
/* 0x000fc80000000006 */
/*0490*/ FFMA R8, R5.reuse, R6, 0.24022644758224487305 ; /* 0x3e75fdec05087423 */
/* 0x040fe20000000006 */
/*04a0*/ SEL R6, RZ, 0x83000000, P1 ; /* 0x83000000ff067807 */
/* 0x000fe40000800000 */
/*04b0*/ FSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f2e000 */
/*04c0*/ FFMA R10, R5, R8, 0.69314718246459960938 ; /* 0x3f317218050a7423 */
/* 0x000fe20000000008 */
/*04d0*/ IADD3 R8, R6, 0x7f000000, RZ ; /* 0x7f00000006087810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LEA R7, R7, -R6, 0x17 ; /* 0x8000000607077211 */
/* 0x004fe200078eb8ff */
/*04f0*/ FFMA R5, R5, R10, 1 ; /* 0x3f80000005057423 */
/* 0x000fe2000000000a */
/*0500*/ FSEL R4, RZ, +INF , !P1 ; /* 0x7f800000ff047808 */
/* 0x000fc60004800000 */
/*0510*/ FMUL R8, R8, R5 ; /* 0x0000000508087220 */
/* 0x000fc80000400000 */
/*0520*/ @!P0 FMUL R4, R7, R8 ; /* 0x0000000807048220 */
/* 0x000fe40000400000 */
/*0530*/ @P2 FADD R4, R0, 2.7182817459106445312 ; /* 0x402df85400042421 */
/* 0x000fe40000000000 */
/*0540*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0550*/ FADD R11, R4, 1 ; /* 0x3f800000040b7421 */
/* 0x000fe20000000000 */
/*0560*/ BSSY B0, 0x640 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0570*/ MUFU.RCP R0, R11 ; /* 0x0000000b00007308 */
/* 0x000eb00000001000 */
/*0580*/ FCHK P0, R4, R11 ; /* 0x0000000b04007302 */
/* 0x000ee20000000000 */
/*0590*/ FFMA R5, -R11, R0, 1 ; /* 0x3f8000000b057423 */
/* 0x004fc80000000100 */
/*05a0*/ FFMA R5, R0, R5, R0 ; /* 0x0000000500057223 */
/* 0x000fc80000000000 */
/*05b0*/ FFMA R0, R5, R4, RZ ; /* 0x0000000405007223 */
/* 0x000fc800000000ff */
/*05c0*/ FFMA R6, -R11, R0, R4 ; /* 0x000000000b067223 */
/* 0x000fc80000000104 */
/*05d0*/ FFMA R5, R5, R6, R0 ; /* 0x0000000605057223 */
/* 0x000fe20000000000 */
/*05e0*/ @!P0 BRA 0x630 ; /* 0x0000004000008947 */
/* 0x008fea0003800000 */
/*05f0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0600*/ MOV R0, 0x620 ; /* 0x0000062000007802 */
/* 0x000fe40000000f00 */
/*0610*/ CALL.REL.NOINC 0x660 ; /* 0x0000004000007944 */
/* 0x003fea0003c00000 */
/*0620*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0640*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ SHF.R.U32.HI R5, RZ, 0x17, R11 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160b */
/*0670*/ BSSY B1, 0xcd0 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*0680*/ SHF.R.U32.HI R4, RZ, 0x17, R9 ; /* 0x00000017ff047819 */
/* 0x000fe20000011609 */
/*0690*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000b */
/*06a0*/ LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050d7812 */
/* 0x000fe400078ec0ff */
/*06b0*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe400078ec0ff */
/*06c0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ IADD3 R8, R10, -0x1, RZ ; /* 0xffffffff0a087810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fe40003f04070 */
/*06f0*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*0700*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*0710*/ @!P0 MOV R7, RZ ; /* 0x000000ff00078202 */
/* 0x000fe20000000f00 */
/*0720*/ @!P0 BRA 0x8b0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0730*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe20003f1c200 */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000b */
/*0750*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0770*/ @P0 BRA 0xcb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0790*/ @!P0 BRA 0xc90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*07a0*/ FSETP.NEU.FTZ.AND P2, PT, |R9|.reuse, +INF , PT ; /* 0x7f8000000900780b */
/* 0x040fe40003f5d200 */
/*07b0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*07d0*/ @!P1 BRA !P2, 0xc90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*07f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0800*/ @P1 BRA 0xc70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0820*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0830*/ @P0 BRA 0xc40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0850*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0860*/ @P0 MOV R7, RZ ; /* 0x000000ff00070202 */
/* 0x000fe20000000f00 */
/*0870*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0880*/ @!P0 FFMA R5, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009058823 */
/* 0x000fe400000000ff */
/*0890*/ @!P1 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004069823 */
/* 0x000fe200000000ff */
/*08a0*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*08c0*/ BSSY B2, 0xc30 ; /* 0x0000036000027945 */
/* 0x000fe60003800000 */
/*08d0*/ IADD3 R9, -R9, R6, RZ ; /* 0x0000000609097210 */
/* 0x000fc40007ffe1ff */
/*08e0*/ IADD3 R6, R10, -0x7f, RZ ; /* 0xffffff810a067810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0900*/ FADD.FTZ R8, -R9, -RZ ; /* 0x800000ff09087221 */
/* 0x000fe40000010100 */
/*0910*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*0920*/ IADD3 R6, R6, 0x7f, -R13 ; /* 0x0000007f06067810 */
/* 0x000fca0007ffe80d */
/*0930*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*0940*/ FFMA R11, R4, R8, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000008 */
/*0950*/ FFMA R10, R4, R11, R4 ; /* 0x0000000b040a7223 */
/* 0x000fc80000000004 */
/*0960*/ FFMA R4, R5, R10, RZ ; /* 0x0000000a05047223 */
/* 0x000fc800000000ff */
/*0970*/ FFMA R11, R8, R4, R5 ; /* 0x00000004080b7223 */
/* 0x000fc80000000005 */
/*0980*/ FFMA R11, R10, R11, R4 ; /* 0x0000000b0a0b7223 */
/* 0x000fc80000000004 */
/*0990*/ FFMA R8, R8, R11, R5 ; /* 0x0000000b08087223 */
/* 0x000fc80000000005 */
/*09a0*/ FFMA R4, R10, R8, R11 ; /* 0x000000080a047223 */
/* 0x000fca000000000b */
/*09b0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*09c0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*09d0*/ IADD3 R9, R5, R6, RZ ; /* 0x0000000605097210 */
/* 0x000fc80007ffe0ff */
/*09e0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0a00*/ @!P0 BRA 0xc10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0a20*/ @P0 BRA 0xbe0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0a40*/ @P0 BRA 0xc20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0a60*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0a70*/ @!P0 BRA 0xc20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a80*/ FFMA.RZ R5, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a057223 */
/* 0x1c0fe2000000c00b */
/*0a90*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0aa0*/ FFMA.RM R6, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a067223 */
/* 0x1c0fe2000000400b */
/*0ab0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0ac0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0ad0*/ FFMA.RP R5, R10, R8, R11 ; /* 0x000000080a057223 */
/* 0x000fe2000000800b */
/*0ae0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0b00*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0b10*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0b20*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0b30*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0b40*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0b50*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0b60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b70*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0b80*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0b90*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0ba0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fc800078ec0ff */
/*0bb0*/ IADD3 R5, R8, R5, RZ ; /* 0x0000000508057210 */
/* 0x000fc80007ffe0ff */
/*0bc0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xc20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0bf0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0c00*/ BRA 0xc20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c10*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*0c20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xcc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fc800078e4805 */
/*0c50*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0c60*/ BRA 0xcc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fe200078e4805 */
/*0c80*/ BRA 0xcc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c90*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0ca0*/ BRA 0xcc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ FADD.FTZ R4, R9, R4 ; /* 0x0000000409047221 */
/* 0x000fe40000010000 */
/*0cc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cd0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0ce0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x001fe20000000f00 */
/*0cf0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0000 */
/*0d00*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2f004007950 */
/* 0x000fea0003c3ffff */
/*0d10*/ BRA 0xd10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | using namespace std;
#include <iostream>
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <fstream>
//#include "cuPrintf.cu"
#define B0 -2.647866f
#define B1 -0.374927f
#define B2 0.061601f
#define B3 -0.001511f
const long MAX_THREADS = 512;
const long MAX_BLOCK= 65535;
extern "C" void botrix_index (float *tempday_h, float* precday_h, int n, float* output);
extern "C" void init ();
void checkCUDAError(const char* msg);
__global__ void calculate_index(float* tempday, float* precday, int n)
{
int id;
float x, y;
id=(blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
x=tempday[id];
y=precday[id];
if (id<n)
{
if (x!=-9999 && y!=-9999)
{
if (y>=4 && x<40)
{
if (x<12)
x=12;
if (x>32)
x=32;
tempday[id]=powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))) / (1+powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))));
}
else
tempday[id]=0;
}
else
tempday[id]=-9999;
}
}
void init()
{
cudaSetDevice(0);
}
void botrix_index(float *tempday_h, float* precday_h, int n, float* output)
{
float *tempday_d, *precday_d;
long n_threads;
int n_blocks;
int dim_blocks;
dim3 dim_grid;
//selezione device da utilizzare
// cudaSetDevice(0);
//settaggio parametri
n_threads=n;
if (n_threads>MAX_BLOCK*MAX_BLOCK*MAX_THREADS)
{
printf("Troppi threads!\n");
exit(0);
}
dim_blocks=MAX_THREADS;
n_blocks=n_threads/MAX_THREADS+(n_threads%MAX_THREADS==0?0:1);
if (n_blocks<=MAX_BLOCK)
{
dim_grid.x=n_blocks;
dim_grid.y=1;
dim_grid.z=1;
}
else
{
dim_grid.x=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.y=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.z=1;
}
printf("Numero threads per blocco: %d\n",dim_blocks);
printf("Dimensioni grid: x %d, y %d\n",dim_grid.x,dim_grid.y);
//stampa input
// cout << "tempday\n";
// for (int i=0; i<n; i++)
// {
// cout<<tempday_h[i]<<" ";
// }
// cout << endl;
// cout << "precday\n";
// for (int i=0; i<n; i++)
// {
// cout<<precday_h[i]<<" ";
// }
// cout << endl;
//allocazione
cudaMalloc((void**) &precday_d, n*sizeof(float));
cudaMalloc((void**) &tempday_d, n*sizeof(float));
checkCUDAError("Allocazione");
//trasferimento su device
cudaMemcpy(tempday_d,tempday_h, sizeof(float)*n, cudaMemcpyHostToDevice);
cudaMemcpy(precday_d,precday_h, sizeof(float)*n, cudaMemcpyHostToDevice);
checkCUDAError("Trasferimento su device");
//lancio kernel
//cudaPrintfInit();
calculate_index <<< dim_grid, dim_blocks >>>(tempday_d, precday_d, n);
//cudaPrintfDisplay(stdout, true);
checkCUDAError("Kernel");
//trasferimento da device
cudaMemcpy(output,tempday_d, sizeof(float)*n, cudaMemcpyDeviceToHost);
checkCUDAError("Trasferimento da device");
// cout << "output\n";
// for (int i=0; i<n; i++)
// {
// cout<<output[i]<<" ";
// }
// cout << endl;
//deallocazione
cudaFree(precday_d);
cudaFree(tempday_d);
}
int main(int argc, char **argv)
{
fstream tempday, precday;
int n;
float *tempday_h, *precday_h, *output;
//lettura parametri
if (argc<3)
{
printf("./a.out tempday.txt precday.txt lunghezza\n");
exit(0);
}
tempday.open(argv[1],ios::in);
precday.open(argv[2],ios::in);
sscanf(argv[3],"%d",&n);
//allocazione
precday_h = (float*) malloc (n*sizeof(float));
tempday_h = (float*) malloc (n*sizeof(float));
output = (float*) malloc (n*sizeof(float));
checkCUDAError("Allocazione");
//inizializzazione
for (int i=0; i<n; i++)
{
tempday >> tempday_h[i];
precday >> precday_h[i];
}
botrix_index(tempday_h,precday_h,n,output);
//stampa
cout << "Risultato botrite:\n";
for (int i=0; i<n; i++)
{
cout<<output[i]<<" ";
}
//deallocazione
free(precday_h);
free(tempday_h);
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .file "tmpxft_000a8c0a_00000000-6_botrixindex.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl init
.type init, @function
init:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %edi
call cudaSetDevice@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size init, .-init
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB3803:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L8
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3803:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z38__device_stub__Z15calculate_indexPfS_iPfS_i
.type _Z38__device_stub__Z15calculate_indexPfS_iPfS_i, @function
_Z38__device_stub__Z15calculate_indexPfS_iPfS_i:
.LFB3828:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15calculate_indexPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z38__device_stub__Z15calculate_indexPfS_iPfS_i, .-_Z38__device_stub__Z15calculate_indexPfS_iPfS_i
.globl _Z15calculate_indexPfS_i
.type _Z15calculate_indexPfS_i, @function
_Z15calculate_indexPfS_i:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15calculate_indexPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z15calculate_indexPfS_i, .-_Z15calculate_indexPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Numero threads per blocco: %d\n"
.section .rodata.str1.1
.LC6:
.string "Dimensioni grid: x %d, y %d\n"
.LC7:
.string "Allocazione"
.LC8:
.string "Trasferimento su device"
.LC9:
.string "Kernel"
.LC10:
.string "Trasferimento da device"
.text
.globl botrix_index
.type botrix_index, @function
botrix_index:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %r12d
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
testl $511, %edx
setne %bpl
movzbl %bpl, %ebp
movslq %edx, %rdx
leaq 511(%rdx), %rax
testq %rdx, %rdx
cmovns %rdx, %rax
sarq $9, %rax
addl %eax, %ebp
movl $1, %r15d
cmpl $65535, %ebp
jg .L30
.L18:
movl $512, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl %r15d, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
leaq .LC9(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pxor %xmm5, %xmm5
cvtsi2sdl %ebp, %xmm5
movsd %xmm5, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm5, %xmm0
ja .L28
sqrtsd %xmm5, %xmm5
movapd %xmm5, %xmm0
movapd %xmm5, %xmm3
movsd .LC11(%rip), %xmm2
movapd %xmm5, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L21
cvttsd2siq %xmm5, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm5, %xmm2
orpd %xmm2, %xmm3
.L21:
cvttsd2siq %xmm3, %rbp
.L22:
movapd %xmm0, %xmm3
movsd .LC11(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L23
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L23:
cvttsd2siq %xmm3, %r15
jmp .L18
.L28:
movsd 8(%rsp), %xmm0
call sqrt@PLT
call ceil@PLT
cvttsd2siq %xmm0, %rbp
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L22
.L31:
movl %r12d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z15calculate_indexPfS_iPfS_i
jmp .L24
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size botrix_index, .-botrix_index
.section .rodata.str1.1
.LC12:
.string "_Z15calculate_indexPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calculate_indexPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC13:
.string "./a.out tempday.txt precday.txt lunghezza\n"
.section .rodata.str1.1
.LC14:
.string "%d"
.LC15:
.string "Risultato botrite:\n"
.LC16:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
.LEHB0:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
leaq 560(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
cmpl $2, %ebp
jg .L36
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L36:
movq 8(%rbx), %rsi
leaq 32(%rsp), %rdi
movl $8, %edx
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movq 16(%rbx), %rsi
leaq 560(%rsp), %rdi
movl $8, %edx
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 28(%rsp), %rdx
movq 24(%rbx), %rdi
leaq .LC14(%rip), %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movslq 28(%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl 28(%rsp), %edx
testl %edx, %edx
jle .L37
movq %r15, %rbp
movl $0, %ebx
leaq 32(%rsp), %r14
jmp .L38
.L51:
leaq 560(%rsp), %rdi
movq %rbp, %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
addl $1, %ebx
movl 28(%rsp), %edx
addq $4, %r12
addq $4, %rbp
cmpl %ebx, %edx
jle .L37
.L38:
movq %r12, %rsi
movq %r14, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L51
.L37:
movq %r13, %rcx
movq %r15, %rsi
movq 8(%rsp), %rdi
call botrix_index
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 28(%rsp)
jle .L39
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC16(%rip), %r12
jmp .L40
.L52:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 28(%rsp)
jle .L39
.L40:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
.LEHE2:
jmp .L52
.L39:
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
leaq 560(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 32(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 560(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
.L42:
leaq 32(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
je .L43
call __stack_chk_fail@PLT
.L45:
endbr64
movq %rax, %rbx
jmp .L42
.L43:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3802:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB0-.LFB3802
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3802
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB3802
.uleb128 0
.uleb128 .LEHB2-.LFB3802
.uleb128 .LEHE2-.LEHB2
.uleb128 .L46-.LFB3802
.uleb128 0
.uleb128 .LEHB3-.LFB3802
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1127219200
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC11:
.long -1
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | using namespace std;
#include <iostream>
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <fstream>
//#include "cuPrintf.cu"
#define B0 -2.647866f
#define B1 -0.374927f
#define B2 0.061601f
#define B3 -0.001511f
const long MAX_THREADS = 512;
const long MAX_BLOCK= 65535;
extern "C" void botrix_index (float *tempday_h, float* precday_h, int n, float* output);
extern "C" void init ();
void checkCUDAError(const char* msg);
__global__ void calculate_index(float* tempday, float* precday, int n)
{
int id;
float x, y;
id=(blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
x=tempday[id];
y=precday[id];
if (id<n)
{
if (x!=-9999 && y!=-9999)
{
if (y>=4 && x<40)
{
if (x<12)
x=12;
if (x>32)
x=32;
tempday[id]=powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))) / (1+powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))));
}
else
tempday[id]=0;
}
else
tempday[id]=-9999;
}
}
void init()
{
cudaSetDevice(0);
}
void botrix_index(float *tempday_h, float* precday_h, int n, float* output)
{
float *tempday_d, *precday_d;
long n_threads;
int n_blocks;
int dim_blocks;
dim3 dim_grid;
//selezione device da utilizzare
// cudaSetDevice(0);
//settaggio parametri
n_threads=n;
if (n_threads>MAX_BLOCK*MAX_BLOCK*MAX_THREADS)
{
printf("Troppi threads!\n");
exit(0);
}
dim_blocks=MAX_THREADS;
n_blocks=n_threads/MAX_THREADS+(n_threads%MAX_THREADS==0?0:1);
if (n_blocks<=MAX_BLOCK)
{
dim_grid.x=n_blocks;
dim_grid.y=1;
dim_grid.z=1;
}
else
{
dim_grid.x=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.y=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.z=1;
}
printf("Numero threads per blocco: %d\n",dim_blocks);
printf("Dimensioni grid: x %d, y %d\n",dim_grid.x,dim_grid.y);
//stampa input
// cout << "tempday\n";
// for (int i=0; i<n; i++)
// {
// cout<<tempday_h[i]<<" ";
// }
// cout << endl;
// cout << "precday\n";
// for (int i=0; i<n; i++)
// {
// cout<<precday_h[i]<<" ";
// }
// cout << endl;
//allocazione
cudaMalloc((void**) &precday_d, n*sizeof(float));
cudaMalloc((void**) &tempday_d, n*sizeof(float));
checkCUDAError("Allocazione");
//trasferimento su device
cudaMemcpy(tempday_d,tempday_h, sizeof(float)*n, cudaMemcpyHostToDevice);
cudaMemcpy(precday_d,precday_h, sizeof(float)*n, cudaMemcpyHostToDevice);
checkCUDAError("Trasferimento su device");
//lancio kernel
//cudaPrintfInit();
calculate_index <<< dim_grid, dim_blocks >>>(tempday_d, precday_d, n);
//cudaPrintfDisplay(stdout, true);
checkCUDAError("Kernel");
//trasferimento da device
cudaMemcpy(output,tempday_d, sizeof(float)*n, cudaMemcpyDeviceToHost);
checkCUDAError("Trasferimento da device");
// cout << "output\n";
// for (int i=0; i<n; i++)
// {
// cout<<output[i]<<" ";
// }
// cout << endl;
//deallocazione
cudaFree(precday_d);
cudaFree(tempday_d);
}
int main(int argc, char **argv)
{
fstream tempday, precday;
int n;
float *tempday_h, *precday_h, *output;
//lettura parametri
if (argc<3)
{
printf("./a.out tempday.txt precday.txt lunghezza\n");
exit(0);
}
tempday.open(argv[1],ios::in);
precday.open(argv[2],ios::in);
sscanf(argv[3],"%d",&n);
//allocazione
precday_h = (float*) malloc (n*sizeof(float));
tempday_h = (float*) malloc (n*sizeof(float));
output = (float*) malloc (n*sizeof(float));
checkCUDAError("Allocazione");
//inizializzazione
for (int i=0; i<n; i++)
{
tempday >> tempday_h[i];
precday >> precday_h[i];
}
botrix_index(tempday_h,precday_h,n,output);
//stampa
cout << "Risultato botrite:\n";
for (int i=0; i<n; i++)
{
cout<<output[i]<<" ";
}
//deallocazione
free(precday_h);
free(tempday_h);
return 0;
}
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | using namespace std;
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <fstream>
//#include "cuPrintf.cu"
#define B0 -2.647866f
#define B1 -0.374927f
#define B2 0.061601f
#define B3 -0.001511f
const long MAX_THREADS = 512;
const long MAX_BLOCK= 65535;
extern "C" void botrix_index (float *tempday_h, float* precday_h, int n, float* output);
extern "C" void init ();
void checkCUDAError(const char* msg);
__global__ void calculate_index(float* tempday, float* precday, int n)
{
int id;
float x, y;
id=(blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
x=tempday[id];
y=precday[id];
if (id<n)
{
if (x!=-9999 && y!=-9999)
{
if (y>=4 && x<40)
{
if (x<12)
x=12;
if (x>32)
x=32;
tempday[id]=powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))) / (1+powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))));
}
else
tempday[id]=0;
}
else
tempday[id]=-9999;
}
}
void init()
{
hipSetDevice(0);
}
void botrix_index(float *tempday_h, float* precday_h, int n, float* output)
{
float *tempday_d, *precday_d;
long n_threads;
int n_blocks;
int dim_blocks;
dim3 dim_grid;
//selezione device da utilizzare
// cudaSetDevice(0);
//settaggio parametri
n_threads=n;
if (n_threads>MAX_BLOCK*MAX_BLOCK*MAX_THREADS)
{
printf("Troppi threads!\n");
exit(0);
}
dim_blocks=MAX_THREADS;
n_blocks=n_threads/MAX_THREADS+(n_threads%MAX_THREADS==0?0:1);
if (n_blocks<=MAX_BLOCK)
{
dim_grid.x=n_blocks;
dim_grid.y=1;
dim_grid.z=1;
}
else
{
dim_grid.x=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.y=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.z=1;
}
printf("Numero threads per blocco: %d\n",dim_blocks);
printf("Dimensioni grid: x %d, y %d\n",dim_grid.x,dim_grid.y);
//stampa input
// cout << "tempday\n";
// for (int i=0; i<n; i++)
// {
// cout<<tempday_h[i]<<" ";
// }
// cout << endl;
// cout << "precday\n";
// for (int i=0; i<n; i++)
// {
// cout<<precday_h[i]<<" ";
// }
// cout << endl;
//allocazione
hipMalloc((void**) &precday_d, n*sizeof(float));
hipMalloc((void**) &tempday_d, n*sizeof(float));
checkCUDAError("Allocazione");
//trasferimento su device
hipMemcpy(tempday_d,tempday_h, sizeof(float)*n, hipMemcpyHostToDevice);
hipMemcpy(precday_d,precday_h, sizeof(float)*n, hipMemcpyHostToDevice);
checkCUDAError("Trasferimento su device");
//lancio kernel
//cudaPrintfInit();
calculate_index <<< dim_grid, dim_blocks >>>(tempday_d, precday_d, n);
//cudaPrintfDisplay(stdout, true);
checkCUDAError("Kernel");
//trasferimento da device
hipMemcpy(output,tempday_d, sizeof(float)*n, hipMemcpyDeviceToHost);
checkCUDAError("Trasferimento da device");
// cout << "output\n";
// for (int i=0; i<n; i++)
// {
// cout<<output[i]<<" ";
// }
// cout << endl;
//deallocazione
hipFree(precday_d);
hipFree(tempday_d);
}
int main(int argc, char **argv)
{
fstream tempday, precday;
int n;
float *tempday_h, *precday_h, *output;
//lettura parametri
if (argc<3)
{
printf("./a.out tempday.txt precday.txt lunghezza\n");
exit(0);
}
tempday.open(argv[1],ios::in);
precday.open(argv[2],ios::in);
sscanf(argv[3],"%d",&n);
//allocazione
precday_h = (float*) malloc (n*sizeof(float));
tempday_h = (float*) malloc (n*sizeof(float));
output = (float*) malloc (n*sizeof(float));
checkCUDAError("Allocazione");
//inizializzazione
for (int i=0; i<n; i++)
{
tempday >> tempday_h[i];
precday >> precday_h[i];
}
botrix_index(tempday_h,precday_h,n,output);
//stampa
cout << "Risultato botrite:\n";
for (int i=0; i<n; i++)
{
cout<<output[i]<<" ";
}
//deallocazione
free(precday_h);
free(tempday_h);
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | using namespace std;
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <fstream>
//#include "cuPrintf.cu"
#define B0 -2.647866f
#define B1 -0.374927f
#define B2 0.061601f
#define B3 -0.001511f
const long MAX_THREADS = 512;
const long MAX_BLOCK= 65535;
extern "C" void botrix_index (float *tempday_h, float* precday_h, int n, float* output);
extern "C" void init ();
void checkCUDAError(const char* msg);
__global__ void calculate_index(float* tempday, float* precday, int n)
{
int id;
float x, y;
id=(blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
x=tempday[id];
y=precday[id];
if (id<n)
{
if (x!=-9999 && y!=-9999)
{
if (y>=4 && x<40)
{
if (x<12)
x=12;
if (x>32)
x=32;
tempday[id]=powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))) / (1+powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))));
}
else
tempday[id]=0;
}
else
tempday[id]=-9999;
}
}
void init()
{
hipSetDevice(0);
}
void botrix_index(float *tempday_h, float* precday_h, int n, float* output)
{
float *tempday_d, *precday_d;
long n_threads;
int n_blocks;
int dim_blocks;
dim3 dim_grid;
//selezione device da utilizzare
// cudaSetDevice(0);
//settaggio parametri
n_threads=n;
if (n_threads>MAX_BLOCK*MAX_BLOCK*MAX_THREADS)
{
printf("Troppi threads!\n");
exit(0);
}
dim_blocks=MAX_THREADS;
n_blocks=n_threads/MAX_THREADS+(n_threads%MAX_THREADS==0?0:1);
if (n_blocks<=MAX_BLOCK)
{
dim_grid.x=n_blocks;
dim_grid.y=1;
dim_grid.z=1;
}
else
{
dim_grid.x=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.y=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.z=1;
}
printf("Numero threads per blocco: %d\n",dim_blocks);
printf("Dimensioni grid: x %d, y %d\n",dim_grid.x,dim_grid.y);
//stampa input
// cout << "tempday\n";
// for (int i=0; i<n; i++)
// {
// cout<<tempday_h[i]<<" ";
// }
// cout << endl;
// cout << "precday\n";
// for (int i=0; i<n; i++)
// {
// cout<<precday_h[i]<<" ";
// }
// cout << endl;
//allocazione
hipMalloc((void**) &precday_d, n*sizeof(float));
hipMalloc((void**) &tempday_d, n*sizeof(float));
checkCUDAError("Allocazione");
//trasferimento su device
hipMemcpy(tempday_d,tempday_h, sizeof(float)*n, hipMemcpyHostToDevice);
hipMemcpy(precday_d,precday_h, sizeof(float)*n, hipMemcpyHostToDevice);
checkCUDAError("Trasferimento su device");
//lancio kernel
//cudaPrintfInit();
calculate_index <<< dim_grid, dim_blocks >>>(tempday_d, precday_d, n);
//cudaPrintfDisplay(stdout, true);
checkCUDAError("Kernel");
//trasferimento da device
hipMemcpy(output,tempday_d, sizeof(float)*n, hipMemcpyDeviceToHost);
checkCUDAError("Trasferimento da device");
// cout << "output\n";
// for (int i=0; i<n; i++)
// {
// cout<<output[i]<<" ";
// }
// cout << endl;
//deallocazione
hipFree(precday_d);
hipFree(tempday_d);
}
int main(int argc, char **argv)
{
fstream tempday, precday;
int n;
float *tempday_h, *precday_h, *output;
//lettura parametri
if (argc<3)
{
printf("./a.out tempday.txt precday.txt lunghezza\n");
exit(0);
}
tempday.open(argv[1],ios::in);
precday.open(argv[2],ios::in);
sscanf(argv[3],"%d",&n);
//allocazione
precday_h = (float*) malloc (n*sizeof(float));
tempday_h = (float*) malloc (n*sizeof(float));
output = (float*) malloc (n*sizeof(float));
checkCUDAError("Allocazione");
//inizializzazione
for (int i=0; i<n; i++)
{
tempday >> tempday_h[i];
precday >> precday_h[i];
}
botrix_index(tempday_h,precday_h,n,output);
//stampa
cout << "Risultato botrite:\n";
for (int i=0; i<n; i++)
{
cout<<output[i]<<" ";
}
//deallocazione
free(precday_h);
free(tempday_h);
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calculate_indexPfS_i
.globl _Z15calculate_indexPfS_i
.p2align 8
.type _Z15calculate_indexPfS_i,@function
_Z15calculate_indexPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[0:1], off
global_load_b32 v2, v[4:5], off
v_mov_b32_e32 v4, 0xc61c3c00
s_waitcnt vmcnt(1)
v_cmp_neq_f32_e32 vcc_lo, 0xc61c3c00, v3
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e64 s0, 0xc61c3c00, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_5
v_cmp_le_f32_e32 vcc_lo, 4.0, v2
v_cmp_gt_f32_e64 s0, 0x42200000, v3
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_4
v_cmp_ngt_f32_e32 vcc_lo, 0x41400000, v3
s_mov_b32 s0, 0xbebff66f
s_mov_b32 s3, 0x3e76c4e1
v_fmaak_f32 v5, s0, v2, 0xc02976a3
v_cndmask_b32_e32 v3, 0x41400000, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 0x42000000, v3
v_cndmask_b32_e32 v3, 0x42000000, v3, vcc_lo
v_mul_f32_e32 v4, 0x3d7c5155, v2
v_dual_mul_f32 v2, 0xbac60cbf, v2 :: v_dual_fmac_f32 v5, v4, v3
v_mul_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v2, v3
v_cmp_eq_f32_e32 vcc_lo, 0, v5
v_cndmask_b32_e64 v2, 0x402df854, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v3, v2
v_frexp_exp_i32_f32_e32 v2, v2
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, 0, 1, s0
v_subrev_co_ci_u32_e64 v2, s0, 0, v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v3, v3, v4
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, 1.0, v3
v_add_f32_e32 v7, -1.0, v3
v_rcp_f32_e32 v6, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v8, v7, v6 :: v_dual_add_f32 v9, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, v4, v8 :: v_dual_sub_f32 v3, v3, v9
v_fma_f32 v4, v8, v4, -v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v8, v3
v_add_f32_e32 v3, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v3, v10
v_dual_sub_f32 v4, v10, v4 :: v_dual_sub_f32 v9, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v9
v_sub_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v4, v3
v_add_f32_e32 v3, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v6, v3
v_add_f32_e32 v4, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v4, v8
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v4, v4 :: v_dual_add_f32 v8, v3, v3
v_fma_f32 v6, v4, v4, -v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v4, v8
v_add_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmaak_f32 v9, s3, v8, 0x3e91f4c4
v_mul_f32_e32 v12, v4, v8
v_sub_f32_e32 v7, v8, v7
v_fmaak_f32 v9, v8, v9, 0x3ecccdef
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v13, v8, v4, -v12
v_sub_f32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v10, v8, v9
v_fmac_f32_e32 v13, v8, v3
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v7, v8, v9, -v10
v_fmac_f32_e32 v13, v6, v4
v_ldexp_f32 v4, v4, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v9
v_dual_add_f32 v8, v12, v13 :: v_dual_add_f32 v9, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v9, v10 :: v_dual_add_f32 v11, 0x3f2aaaaa, v9
v_dual_sub_f32 v7, v7, v10 :: v_dual_add_f32 v10, 0xbf2aaaaa, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, 0x31739010, v7
v_sub_f32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v7, v9
v_add_f32_e32 v6, v11, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v9, v11, v6
v_mul_f32_e32 v10, v8, v6
v_sub_f32_e32 v11, v8, v12
v_add_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, v8, v6, -v10
v_sub_f32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v7
v_fmac_f32_e32 v9, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v10, v9
v_add_f32_e32 v7, v4, v6
v_sub_f32_e32 v8, v6, v10
v_mul_f32_e32 v10, 0x3f317218, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v7, v4
v_sub_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, v2, 0x3f317218, -v10
v_sub_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v8 :: v_dual_fmamk_f32 v2, v2, 0xb102e308, v9
v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v3
v_sub_f32_e32 v10, v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, v4, v6 :: v_dual_sub_f32 v7, v6, v7
v_dual_sub_f32 v2, v2, v10 :: v_dual_sub_f32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v7, v2, v3
v_sub_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v8, v9
v_sub_f32_e32 v6, v6, v9
v_sub_f32_e32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v6, v4
v_sub_f32_e32 v6, v7, v2
v_add_f32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
v_dual_add_f32 v9, v8, v4 :: v_dual_sub_f32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v9, v8
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v4, v6
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v2
v_mul_f32_e32 v6, v5, v3
v_sub_f32_e32 v4, v3, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v5, v3, -v6
v_sub_f32_e32 v2, v2, v4
v_cmp_class_f32_e64 s0, v6, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v2
v_add_f32_e32 v2, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v2, v6, s0
v_cmp_eq_f32_e64 s0, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, 0, 0x37000000, s0
v_cmp_neq_f32_e64 s0, 0x7f800000, |v4|
v_sub_f32_e32 v8, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v9, 0x3fb8aa3b, v8 :: v_dual_sub_f32 v2, v2, v6
v_fma_f32 v10, v8, 0x3fb8aa3b, -v9
v_rndne_f32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v2, v3, v2
v_dual_fmamk_f32 v10, v8, 0x32a5705f, v10 :: v_dual_sub_f32 v9, v9, v11
v_cvt_i32_f32_e32 v6, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v2, 0, v2, s0
v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v8
v_add_f32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v2, v7, v2
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0, v3, s0
v_cmp_nlt_f32_e64 s0, 0x42b17218, v8
v_cndmask_b32_e64 v3, 0x7f800000, v3, s0
v_cmp_eq_f32_e64 s0, |v5|, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v3, v2, v3
v_cndmask_b32_e64 v4, 0, |v5|, s0
v_cmp_class_f32_e64 s0, v5, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v4, 1.0, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v3
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v5, v5
v_cndmask_b32_e64 v2, |v2|, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
v_add_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v4, v4, v3, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
global_store_b32 v[0:1], v4, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calculate_indexPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calculate_indexPfS_i, .Lfunc_end0-_Z15calculate_indexPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calculate_indexPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15calculate_indexPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | using namespace std;
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
#include <math.h>
#include <fstream>
//#include "cuPrintf.cu"
#define B0 -2.647866f
#define B1 -0.374927f
#define B2 0.061601f
#define B3 -0.001511f
const long MAX_THREADS = 512;
const long MAX_BLOCK= 65535;
extern "C" void botrix_index (float *tempday_h, float* precday_h, int n, float* output);
extern "C" void init ();
void checkCUDAError(const char* msg);
__global__ void calculate_index(float* tempday, float* precday, int n)
{
int id;
float x, y;
id=(blockIdx.y*gridDim.x+blockIdx.x)*blockDim.x+threadIdx.x;
x=tempday[id];
y=precday[id];
if (id<n)
{
if (x!=-9999 && y!=-9999)
{
if (y>=4 && x<40)
{
if (x<12)
x=12;
if (x>32)
x=32;
tempday[id]=powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))) / (1+powf(M_E,(B0+(B1*y)+(B2*y*x)+(B3*y*(x*x)))));
}
else
tempday[id]=0;
}
else
tempday[id]=-9999;
}
}
void init()
{
hipSetDevice(0);
}
void botrix_index(float *tempday_h, float* precday_h, int n, float* output)
{
float *tempday_d, *precday_d;
long n_threads;
int n_blocks;
int dim_blocks;
dim3 dim_grid;
//selezione device da utilizzare
// cudaSetDevice(0);
//settaggio parametri
n_threads=n;
if (n_threads>MAX_BLOCK*MAX_BLOCK*MAX_THREADS)
{
printf("Troppi threads!\n");
exit(0);
}
dim_blocks=MAX_THREADS;
n_blocks=n_threads/MAX_THREADS+(n_threads%MAX_THREADS==0?0:1);
if (n_blocks<=MAX_BLOCK)
{
dim_grid.x=n_blocks;
dim_grid.y=1;
dim_grid.z=1;
}
else
{
dim_grid.x=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.y=(unsigned int) ceil(sqrt(n_blocks));
dim_grid.z=1;
}
printf("Numero threads per blocco: %d\n",dim_blocks);
printf("Dimensioni grid: x %d, y %d\n",dim_grid.x,dim_grid.y);
//stampa input
// cout << "tempday\n";
// for (int i=0; i<n; i++)
// {
// cout<<tempday_h[i]<<" ";
// }
// cout << endl;
// cout << "precday\n";
// for (int i=0; i<n; i++)
// {
// cout<<precday_h[i]<<" ";
// }
// cout << endl;
//allocazione
hipMalloc((void**) &precday_d, n*sizeof(float));
hipMalloc((void**) &tempday_d, n*sizeof(float));
checkCUDAError("Allocazione");
//trasferimento su device
hipMemcpy(tempday_d,tempday_h, sizeof(float)*n, hipMemcpyHostToDevice);
hipMemcpy(precday_d,precday_h, sizeof(float)*n, hipMemcpyHostToDevice);
checkCUDAError("Trasferimento su device");
//lancio kernel
//cudaPrintfInit();
calculate_index <<< dim_grid, dim_blocks >>>(tempday_d, precday_d, n);
//cudaPrintfDisplay(stdout, true);
checkCUDAError("Kernel");
//trasferimento da device
hipMemcpy(output,tempday_d, sizeof(float)*n, hipMemcpyDeviceToHost);
checkCUDAError("Trasferimento da device");
// cout << "output\n";
// for (int i=0; i<n; i++)
// {
// cout<<output[i]<<" ";
// }
// cout << endl;
//deallocazione
hipFree(precday_d);
hipFree(tempday_d);
}
int main(int argc, char **argv)
{
fstream tempday, precday;
int n;
float *tempday_h, *precday_h, *output;
//lettura parametri
if (argc<3)
{
printf("./a.out tempday.txt precday.txt lunghezza\n");
exit(0);
}
tempday.open(argv[1],ios::in);
precday.open(argv[2],ios::in);
sscanf(argv[3],"%d",&n);
//allocazione
precday_h = (float*) malloc (n*sizeof(float));
tempday_h = (float*) malloc (n*sizeof(float));
output = (float*) malloc (n*sizeof(float));
checkCUDAError("Allocazione");
//inizializzazione
for (int i=0; i<n; i++)
{
tempday >> tempday_h[i];
precday >> precday_h[i];
}
botrix_index(tempday_h,precday_h,n,output);
//stampa
cout << "Risultato botrite:\n";
for (int i=0; i<n; i++)
{
cout<<output[i]<<" ";
}
//deallocazione
free(precday_h);
free(tempday_h);
return 0;
}
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg,
hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
} | .text
.file "botrixindex.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__calculate_indexPfS_i # -- Begin function _Z30__device_stub__calculate_indexPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__calculate_indexPfS_i,@function
_Z30__device_stub__calculate_indexPfS_i: # @_Z30__device_stub__calculate_indexPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15calculate_indexPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__calculate_indexPfS_i, .Lfunc_end0-_Z30__device_stub__calculate_indexPfS_i
.cfi_endproc
# -- End function
.globl init # -- Begin function init
.p2align 4, 0x90
.type init,@function
init: # @init
.cfi_startproc
# %bb.0:
xorl %edi, %edi
jmp hipSetDevice # TAILCALL
.Lfunc_end1:
.size init, .Lfunc_end1-init
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function botrix_index
.LCPI2_0:
.quad 0x0000000000000000 # double 0
.text
.globl botrix_index
.p2align 4, 0x90
.type botrix_index,@function
botrix_index: # @botrix_index
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r12
movl %edx, %ebp
movq %rsi, 56(%rsp) # 8-byte Spill
movq %rdi, %r13
movslq %edx, %r14
leaq 511(%r14), %rax
testq %r14, %r14
cmovnsq %r14, %rax
movabsq $4294967296, %r15 # imm = 0x100000000
sarq $9, %rax
movl %edx, %ecx
andl $511, %ecx # imm = 0x1FF
cmpq $1, %rcx
sbbq $-1, %rax
cmpq $65535, %rax # imm = 0xFFFF
jg .LBB2_2
# %bb.1:
movl %eax, %ebx
orq %r15, %rbx
jmp .LBB2_7
.LBB2_2:
movq %r12, 48(%rsp) # 8-byte Spill
cvtsi2sd %eax, %xmm1
sqrtsd %xmm1, %xmm0
xorpd %xmm2, %xmm2
movsd %xmm1, 16(%rsp) # 8-byte Spill
ucomisd %xmm2, %xmm1
movsd %xmm0, 40(%rsp) # 8-byte Spill
jae .LBB2_4
# %bb.3: # %call.sqrt
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sqrt
.LBB2_4: # %.split
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %r12d
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd .LCPI2_0(%rip), %xmm0
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB2_6
# %bb.5: # %call.sqrt43
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sqrt
.LBB2_6: # %.split.split
callq ceil@PLT
cvttsd2si %xmm0, %rbx
shlq $32, %rbx
orq %r12, %rbx
movq 48(%rsp), %r12 # 8-byte Reload
.LBB2_7:
movl $.L.str.1, %edi
movl $512, %esi # imm = 0x200
xorl %eax, %eax
callq printf
movq %rbx, %rdx
shrq $32, %rdx
movl $.L.str.2, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
shlq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.10: # %_Z14checkCUDAErrorPKc.exit
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.12: # %_Z14checkCUDAErrorPKc.exit23
addq $512, %r15 # imm = 0x200
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %ebp, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15calculate_indexPfS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_15
# %bb.16: # %_Z14checkCUDAErrorPKc.exit25
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_17
# %bb.18: # %_Z14checkCUDAErrorPKc.exit27
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.3, %edx
jmp .LBB2_9
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.4, %edx
jmp .LBB2_9
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.5, %edx
jmp .LBB2_9
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %edx
.LBB2_9:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size botrix_index, .Lfunc_end2-botrix_index
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 1136
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 552(%rsp), %r15
movq %r15, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
.Ltmp0:
leaq 24(%rsp), %r14
movq %r14, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
.Ltmp1:
# %bb.1:
cmpl $2, %ebp
jle .LBB4_2
# %bb.5:
movq 8(%rbx), %rsi
leaq 576(%rsp), %rdi
.Ltmp3:
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp4:
# %bb.6: # %.noexc
movq 552(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB4_8
# %bb.7:
movl 32(%r15), %esi
orl $4, %esi
.LBB4_8: # %.invoke55
.Ltmp5:
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp6:
# %bb.9: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
movq 16(%rbx), %rsi
leaq 48(%rsp), %rdi
.Ltmp7:
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp8:
# %bb.10: # %.noexc31
movq 24(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB4_12
# %bb.11:
movl 32(%r14), %esi
orl $4, %esi
.LBB4_12: # %.invoke
.Ltmp9:
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp10:
# %bb.13: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit34
movq 24(%rbx), %rdi
leaq 4(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movslq 4(%rsp), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq %rbx, %rdi
callq malloc
movq %rax, %r15
.Ltmp11:
callq hipGetLastError
.Ltmp12:
# %bb.14: # %.noexc36
testl %eax, %eax
jne .LBB4_29
# %bb.15: # %_Z14checkCUDAErrorPKc.exit.preheader
movl 4(%rsp), %edx
testl %edx, %edx
jle .LBB4_21
# %bb.16: # %.lr.ph.preheader
movq %r14, %rbx
xorl %r14d, %r14d
leaq 552(%rsp), %r12
leaq 24(%rsp), %r13
movq %rbp, 8(%rsp) # 8-byte Spill
movq %rbx, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_17: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp15:
movq %r12, %rdi
movq %rbp, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp16:
# %bb.18: # %_ZNSirsERf.exit
# in Loop: Header=BB4_17 Depth=1
.Ltmp17:
movq %r13, %rdi
movq %rbx, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp18:
# %bb.19: # %_ZNSirsERf.exit40
# in Loop: Header=BB4_17 Depth=1
incq %r14
movslq 4(%rsp), %rdx
addq $4, %rbx
addq $4, %rbp
cmpq %rdx, %r14
jl .LBB4_17
# %bb.20:
movq 16(%rsp), %r14 # 8-byte Reload
movq 8(%rsp), %rbp # 8-byte Reload
.LBB4_21: # %_Z14checkCUDAErrorPKc.exit._crit_edge
.Ltmp20:
movq %rbp, %rdi
movq %r14, %rsi
# kill: def $edx killed $edx killed $rdx
movq %r15, %rcx
callq botrix_index
.Ltmp21:
# %bb.22:
.Ltmp22:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.23: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit.preheader
cmpl $0, 4(%rsp)
jle .LBB4_28
# %bb.24: # %.lr.ph48.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_25: # %.lr.ph48
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp25:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp26:
# %bb.26: # %_ZNSolsEf.exit
# in Loop: Header=BB4_25 Depth=1
.Ltmp27:
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
# %bb.27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
# in Loop: Header=BB4_25 Depth=1
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB4_25
.LBB4_28: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit._crit_edge
movq %r14, %rdi
callq free
movq %rbp, %rdi
callq free
leaq 24(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
leaq 552(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 816(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 1136
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB4_29:
movq stderr(%rip), %rbx
.Ltmp13:
movl %eax, %edi
callq hipGetErrorString
.Ltmp14:
# %bb.30: # %.noexc37
movl $.L.str.11, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_3:
.Ltmp2:
movq %rax, %rbx
jmp .LBB4_34
.LBB4_4:
.Ltmp24:
jmp .LBB4_33
.LBB4_32:
.Ltmp29:
jmp .LBB4_33
.LBB4_31:
.Ltmp19:
.LBB4_33:
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
.LBB4_34:
leaq 552(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 816(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp18-.Ltmp15 # Call between .Ltmp15 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp20 # Call between .Ltmp20 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp28-.Ltmp25 # Call between .Ltmp25 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end4-.Ltmp14 # Call between .Ltmp14 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calculate_indexPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calculate_indexPfS_i,@object # @_Z15calculate_indexPfS_i
.section .rodata,"a",@progbits
.globl _Z15calculate_indexPfS_i
.p2align 3, 0x0
_Z15calculate_indexPfS_i:
.quad _Z30__device_stub__calculate_indexPfS_i
.size _Z15calculate_indexPfS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Numero threads per blocco: %d\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Dimensioni grid: x %d, y %d\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocazione"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Trasferimento su device"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Kernel"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Trasferimento da device"
.size .L.str.6, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Risultato botrite:\n"
.size .L.str.9, 20
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " "
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.11, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15calculate_indexPfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "./a.out tempday.txt precday.txt lunghezza"
.size .Lstr, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calculate_indexPfS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z15calculate_indexPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15calculate_indexPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc400078e00ff */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R3, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x040fe200078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ FSETP.NEU.AND P0, PT, R4, -9999, PT ; /* 0xc61c3c000400780b */
/* 0x004fc80003f0d000 */
/*00f0*/ FSETP.NEU.AND P0, PT, R0, -9999, P0 ; /* 0xc61c3c000000780b */
/* 0x008fda000070d000 */
/*0100*/ @!P0 MOV R7, 0xc61c3c00 ; /* 0xc61c3c0000078802 */
/* 0x000fca0000000f00 */
/*0110*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ FSETP.GE.AND P0, PT, R4, 4, PT ; /* 0x408000000400780b */
/* 0x000fc80003f06000 */
/*0140*/ FSETP.LT.AND P0, PT, R0, 40, P0 ; /* 0x422000000000780b */
/* 0x000fda0000701000 */
/*0150*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0003e2000c101904 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ FMNMX.NAN R0, R0, 12, !PT ; /* 0x4140000000007809 */
/* 0x000fe20007820000 */
/*0180*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ebff66f ; /* 0x3ebff66fff057424 */
/* 0x000fe200078e00ff */
/*0190*/ BSSY B0, 0x550 ; /* 0x000003b000007945 */
/* 0x000fe20003800000 */
/*01a0*/ FMUL R6, R4, 0.061601001769304275513 ; /* 0x3d7c515504067820 */
/* 0x000fe20000400000 */
/*01b0*/ FMNMX.NAN R0, R0, 32, PT ; /* 0x4200000000007809 */
/* 0x000fe20003820000 */
/*01c0*/ FFMA R5, R4.reuse, -R5, -2.6478660106658935547 ; /* 0xc02976a304057423 */
/* 0x040fe40000000805 */
/*01d0*/ FMUL R4, R4, -0.0015109999803826212883 ; /* 0xbac60cbf04047820 */
/* 0x000fe40000400000 */
/*01e0*/ FFMA R5, R0, R6, R5 ; /* 0x0000000600057223 */
/* 0x000fc40000000005 */
/*01f0*/ FMUL R0, R0, R0 ; /* 0x0000000000007220 */
/* 0x000fc80000400000 */
/*0200*/ FFMA R0, R0, R4, R5 ; /* 0x0000000400007223 */
/* 0x000fe40000000005 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff047424 */
/* 0x000fc600078e00ff */
/*0220*/ FSETP.NEU.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f0d000 */
/*0230*/ @!P0 BRA 0x540 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0240*/ HFMA2.MMA R6, -RZ, RZ, 0.25, 0 ; /* 0x34000000ff067435 */
/* 0x000fe200000001ff */
/*0250*/ MOV R11, 0x3e9be32a ; /* 0x3e9be32a000b7802 */
/* 0x000fe20000000f00 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, 0x3dbdd9bd ; /* 0x3dbdd9bdff087424 */
/* 0x000fe200078e00ff */
/*0270*/ FSETP.GTU.AND P2, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fe20003f4c200 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a2c32e4 ; /* 0x3a2c32e4ff057424 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3eb7e150 ; /* 0x3eb7e150ff047424 */
/* 0x000fe400078e00ff */
/*02a0*/ FFMA R5, R8, R5, 0.0032181653659790754318 ; /* 0x3b52e7db08057423 */
/* 0x000fe40000000005 */
/*02b0*/ FFMA R6, R6, 8388608, RZ ; /* 0x4b00000006067823 */
/* 0x000fc400000000ff */
/*02c0*/ FFMA R4, R4, -R11, 0.10934674739837646484 ; /* 0x3ddff13004047423 */
/* 0x000fe4000000080b */
/*02d0*/ FFMA R7, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b077823 */
/* 0x001fe40000000006 */
/*02e0*/ FFMA R5, R5, R8.reuse, 0.018033718690276145935 ; /* 0x3c93bb7305057423 */
/* 0x080fe40000000008 */
/*02f0*/ FADD R6, R6, -R7 ; /* 0x8000000706067221 */
/* 0x000fe40000000000 */
/*0300*/ FMUL R4, R4, 0.42388311028480529785 ; /* 0x3ed9073504047820 */
/* 0x000fe40000400000 */
/*0310*/ FFMA R5, R5, R8, 0.12022458761930465698 ; /* 0x3df6384f05057423 */
/* 0x000fc40000000008 */
/*0320*/ FFMA R9, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b097823 */
/* 0x000fe40000000006 */
/*0330*/ FMUL R5, R5, 0.092700459063053131104 ; /* 0x3dbdd9bd05057820 */
/* 0x000fe40000400000 */
/*0340*/ FFMA R6, R4, 1.4426950216293334961, R9 ; /* 0x3fb8aa3b04067823 */
/* 0x000fe40000000009 */
/*0350*/ FMUL R9, R5, 3 ; /* 0x4040000005097820 */
/* 0x000fe40000400000 */
/*0360*/ FFMA R6, R11, 1.9251366722983220825e-08, R6 ; /* 0x32a55e340b067823 */
/* 0x000fe40000000006 */
/*0370*/ IMAD.MOV.U32 R8, RZ, RZ, 0x391fcb8e ; /* 0x391fcb8eff087424 */
/* 0x000fc400078e00ff */
/*0380*/ FFMA R6, R4, R9, R6 ; /* 0x0000000904067223 */
/* 0x000fc80000000006 */
/*0390*/ FFMA R6, R5, 0.3044674992561340332, R6 ; /* 0x3e9be32a05067823 */
/* 0x000fc80000000006 */
/*03a0*/ FADD R5, R7, R6 ; /* 0x0000000607057221 */
/* 0x000fc80000000000 */
/*03b0*/ FMUL R4, R0.reuse, R5.reuse ; /* 0x0000000500047220 */
/* 0x0c0fe40000400000 */
/*03c0*/ FADD R7, -R7, R5 ; /* 0x0000000507077221 */
/* 0x000fe40000000100 */
/*03d0*/ FRND R9, R4 ; /* 0x0000000400097307 */
/* 0x000e220000201000 */
/*03e0*/ FFMA R5, R0, R5, -R4 ; /* 0x0000000500057223 */
/* 0x000fe20000000804 */
/*03f0*/ FSETP.GT.AND P0, PT, |R4|, 152, PT ; /* 0x431800000400780b */
/* 0x000fe20003f04200 */
/*0400*/ FADD R7, R6, -R7 ; /* 0x8000000706077221 */
/* 0x000fc80000000000 */
/*0410*/ FFMA R6, R0, R7, R5 ; /* 0x0000000700067223 */
/* 0x000fe40000000005 */
/*0420*/ F2I.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000ea20000203100 */
/*0430*/ FADD R5, R4, -R9 ; /* 0x8000000904057221 */
/* 0x001fe20000000000 */
/*0440*/ FSETP.GT.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720b */
/* 0x000fc60003f24000 */
/*0450*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x000fc80000000000 */
/*0460*/ FFMA R6, R5, R8, 0.0013391353422775864601 ; /* 0x3aaf85ed05067423 */
/* 0x000fc80000000008 */
/*0470*/ FFMA R6, R5, R6, 0.0096188392490148544312 ; /* 0x3c1d985605067423 */
/* 0x000fc80000000006 */
/*0480*/ FFMA R6, R5, R6, 0.055503588169813156128 ; /* 0x3d6357bb05067423 */
/* 0x000fc80000000006 */
/*0490*/ FFMA R8, R5.reuse, R6, 0.24022644758224487305 ; /* 0x3e75fdec05087423 */
/* 0x040fe20000000006 */
/*04a0*/ SEL R6, RZ, 0x83000000, P1 ; /* 0x83000000ff067807 */
/* 0x000fe40000800000 */
/*04b0*/ FSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f2e000 */
/*04c0*/ FFMA R10, R5, R8, 0.69314718246459960938 ; /* 0x3f317218050a7423 */
/* 0x000fe20000000008 */
/*04d0*/ IADD3 R8, R6, 0x7f000000, RZ ; /* 0x7f00000006087810 */
/* 0x000fe40007ffe0ff */
/*04e0*/ LEA R7, R7, -R6, 0x17 ; /* 0x8000000607077211 */
/* 0x004fe200078eb8ff */
/*04f0*/ FFMA R5, R5, R10, 1 ; /* 0x3f80000005057423 */
/* 0x000fe2000000000a */
/*0500*/ FSEL R4, RZ, +INF , !P1 ; /* 0x7f800000ff047808 */
/* 0x000fc60004800000 */
/*0510*/ FMUL R8, R8, R5 ; /* 0x0000000508087220 */
/* 0x000fc80000400000 */
/*0520*/ @!P0 FMUL R4, R7, R8 ; /* 0x0000000807048220 */
/* 0x000fe40000400000 */
/*0530*/ @P2 FADD R4, R0, 2.7182817459106445312 ; /* 0x402df85400042421 */
/* 0x000fe40000000000 */
/*0540*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0550*/ FADD R11, R4, 1 ; /* 0x3f800000040b7421 */
/* 0x000fe20000000000 */
/*0560*/ BSSY B0, 0x640 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0570*/ MUFU.RCP R0, R11 ; /* 0x0000000b00007308 */
/* 0x000eb00000001000 */
/*0580*/ FCHK P0, R4, R11 ; /* 0x0000000b04007302 */
/* 0x000ee20000000000 */
/*0590*/ FFMA R5, -R11, R0, 1 ; /* 0x3f8000000b057423 */
/* 0x004fc80000000100 */
/*05a0*/ FFMA R5, R0, R5, R0 ; /* 0x0000000500057223 */
/* 0x000fc80000000000 */
/*05b0*/ FFMA R0, R5, R4, RZ ; /* 0x0000000405007223 */
/* 0x000fc800000000ff */
/*05c0*/ FFMA R6, -R11, R0, R4 ; /* 0x000000000b067223 */
/* 0x000fc80000000104 */
/*05d0*/ FFMA R5, R5, R6, R0 ; /* 0x0000000605057223 */
/* 0x000fe20000000000 */
/*05e0*/ @!P0 BRA 0x630 ; /* 0x0000004000008947 */
/* 0x008fea0003800000 */
/*05f0*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0004 */
/*0600*/ MOV R0, 0x620 ; /* 0x0000062000007802 */
/* 0x000fe40000000f00 */
/*0610*/ CALL.REL.NOINC 0x660 ; /* 0x0000004000007944 */
/* 0x003fea0003c00000 */
/*0620*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0006 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0640*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ SHF.R.U32.HI R5, RZ, 0x17, R11 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160b */
/*0670*/ BSSY B1, 0xcd0 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*0680*/ SHF.R.U32.HI R4, RZ, 0x17, R9 ; /* 0x00000017ff047819 */
/* 0x000fe20000011609 */
/*0690*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000b */
/*06a0*/ LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050d7812 */
/* 0x000fe400078ec0ff */
/*06b0*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe400078ec0ff */
/*06c0*/ IADD3 R12, R13, -0x1, RZ ; /* 0xffffffff0d0c7810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ IADD3 R8, R10, -0x1, RZ ; /* 0xffffffff0a087810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fe40003f04070 */
/*06f0*/ MOV R5, R9 ; /* 0x0000000900057202 */
/* 0x000fe40000000f00 */
/*0700*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*0710*/ @!P0 MOV R7, RZ ; /* 0x000000ff00078202 */
/* 0x000fe20000000f00 */
/*0720*/ @!P0 BRA 0x8b0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0730*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fe20003f1c200 */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R11 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000b */
/*0750*/ FSETP.GTU.FTZ.AND P1, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fc80003f3c200 */
/*0760*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0770*/ @P0 BRA 0xcb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0780*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0790*/ @!P0 BRA 0xc90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*07a0*/ FSETP.NEU.FTZ.AND P2, PT, |R9|.reuse, +INF , PT ; /* 0x7f8000000900780b */
/* 0x040fe40003f5d200 */
/*07b0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fd60003f1d200 */
/*07d0*/ @!P1 BRA !P2, 0xc90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*07e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*07f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0800*/ @P1 BRA 0xc70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0820*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0830*/ @P0 BRA 0xc40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0840*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0850*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0860*/ @P0 MOV R7, RZ ; /* 0x000000ff00070202 */
/* 0x000fe20000000f00 */
/*0870*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0880*/ @!P0 FFMA R5, R9, 1.84467440737095516160e+19, RZ ; /* 0x5f80000009058823 */
/* 0x000fe400000000ff */
/*0890*/ @!P1 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004069823 */
/* 0x000fe200000000ff */
/*08a0*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*08b0*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*08c0*/ BSSY B2, 0xc30 ; /* 0x0000036000027945 */
/* 0x000fe60003800000 */
/*08d0*/ IADD3 R9, -R9, R6, RZ ; /* 0x0000000609097210 */
/* 0x000fc40007ffe1ff */
/*08e0*/ IADD3 R6, R10, -0x7f, RZ ; /* 0xffffff810a067810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*0900*/ FADD.FTZ R8, -R9, -RZ ; /* 0x800000ff09087221 */
/* 0x000fe40000010100 */
/*0910*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*0920*/ IADD3 R6, R6, 0x7f, -R13 ; /* 0x0000007f06067810 */
/* 0x000fca0007ffe80d */
/*0930*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*0940*/ FFMA R11, R4, R8, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000008 */
/*0950*/ FFMA R10, R4, R11, R4 ; /* 0x0000000b040a7223 */
/* 0x000fc80000000004 */
/*0960*/ FFMA R4, R5, R10, RZ ; /* 0x0000000a05047223 */
/* 0x000fc800000000ff */
/*0970*/ FFMA R11, R8, R4, R5 ; /* 0x00000004080b7223 */
/* 0x000fc80000000005 */
/*0980*/ FFMA R11, R10, R11, R4 ; /* 0x0000000b0a0b7223 */
/* 0x000fc80000000004 */
/*0990*/ FFMA R8, R8, R11, R5 ; /* 0x0000000b08087223 */
/* 0x000fc80000000005 */
/*09a0*/ FFMA R4, R10, R8, R11 ; /* 0x000000080a047223 */
/* 0x000fca000000000b */
/*09b0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*09c0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*09d0*/ IADD3 R9, R5, R6, RZ ; /* 0x0000000605097210 */
/* 0x000fc80007ffe0ff */
/*09e0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*0a00*/ @!P0 BRA 0xc10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0a20*/ @P0 BRA 0xbe0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0a40*/ @P0 BRA 0xc20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0a50*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0a60*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0a70*/ @!P0 BRA 0xc20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0a80*/ FFMA.RZ R5, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a057223 */
/* 0x1c0fe2000000c00b */
/*0a90*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0aa0*/ FFMA.RM R6, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a067223 */
/* 0x1c0fe2000000400b */
/*0ab0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0ac0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0ad0*/ FFMA.RP R5, R10, R8, R11 ; /* 0x000000080a057223 */
/* 0x000fe2000000800b */
/*0ae0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*0af0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0b00*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0b10*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0b20*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0b30*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0b40*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0b50*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0b60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0b70*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0b80*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0b90*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0ba0*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fc800078ec0ff */
/*0bb0*/ IADD3 R5, R8, R5, RZ ; /* 0x0000000508057210 */
/* 0x000fc80007ffe0ff */
/*0bc0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0bd0*/ BRA 0xc20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0be0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0bf0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0c00*/ BRA 0xc20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0c10*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*0c20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c30*/ BRA 0xcc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fc800078e4805 */
/*0c50*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0c60*/ BRA 0xcc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fe200078e4805 */
/*0c80*/ BRA 0xcc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c90*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0ca0*/ BRA 0xcc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0cb0*/ FADD.FTZ R4, R9, R4 ; /* 0x0000000409047221 */
/* 0x000fe40000010000 */
/*0cc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cd0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0ce0*/ MOV R6, R4 ; /* 0x0000000400067202 */
/* 0x001fe20000000f00 */
/*0cf0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0000 */
/*0d00*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2f004007950 */
/* 0x000fea0003c3ffff */
/*0d10*/ BRA 0xd10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15calculate_indexPfS_i
.globl _Z15calculate_indexPfS_i
.p2align 8
.type _Z15calculate_indexPfS_i,@function
_Z15calculate_indexPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[0:1], off
global_load_b32 v2, v[4:5], off
v_mov_b32_e32 v4, 0xc61c3c00
s_waitcnt vmcnt(1)
v_cmp_neq_f32_e32 vcc_lo, 0xc61c3c00, v3
s_waitcnt vmcnt(0)
v_cmp_neq_f32_e64 s0, 0xc61c3c00, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_5
v_cmp_le_f32_e32 vcc_lo, 4.0, v2
v_cmp_gt_f32_e64 s0, 0x42200000, v3
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB0_4
v_cmp_ngt_f32_e32 vcc_lo, 0x41400000, v3
s_mov_b32 s0, 0xbebff66f
s_mov_b32 s3, 0x3e76c4e1
v_fmaak_f32 v5, s0, v2, 0xc02976a3
v_cndmask_b32_e32 v3, 0x41400000, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 0x42000000, v3
v_cndmask_b32_e32 v3, 0x42000000, v3, vcc_lo
v_mul_f32_e32 v4, 0x3d7c5155, v2
v_dual_mul_f32 v2, 0xbac60cbf, v2 :: v_dual_fmac_f32 v5, v4, v3
v_mul_f32_e32 v3, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v2, v3
v_cmp_eq_f32_e32 vcc_lo, 0, v5
v_cndmask_b32_e64 v2, 0x402df854, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e32 v3, v2
v_frexp_exp_i32_f32_e32 v2, v2
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, 0, 1, s0
v_subrev_co_ci_u32_e64 v2, s0, 0, v2, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v3, v3, v4
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, 1.0, v3
v_add_f32_e32 v7, -1.0, v3
v_rcp_f32_e32 v6, v4
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v8, v7, v6 :: v_dual_add_f32 v9, -1.0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, v4, v8 :: v_dual_sub_f32 v3, v3, v9
v_fma_f32 v4, v8, v4, -v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v8, v3
v_add_f32_e32 v3, v10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v10, v3, v10
v_dual_sub_f32 v4, v10, v4 :: v_dual_sub_f32 v9, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v9
v_sub_f32_e32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v4, v3
v_add_f32_e32 v3, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v6, v3
v_add_f32_e32 v4, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v4, v8
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v7, v4, v4 :: v_dual_add_f32 v8, v3, v3
v_fma_f32 v6, v4, v4, -v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v4, v8
v_add_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmaak_f32 v9, s3, v8, 0x3e91f4c4
v_mul_f32_e32 v12, v4, v8
v_sub_f32_e32 v7, v8, v7
v_fmaak_f32 v9, v8, v9, 0x3ecccdef
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v13, v8, v4, -v12
v_sub_f32_e32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v10, v8, v9
v_fmac_f32_e32 v13, v8, v3
v_ldexp_f32 v3, v3, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v7, v8, v9, -v10
v_fmac_f32_e32 v13, v6, v4
v_ldexp_f32 v4, v4, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v6, v9
v_dual_add_f32 v8, v12, v13 :: v_dual_add_f32 v9, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v9, v10 :: v_dual_add_f32 v11, 0x3f2aaaaa, v9
v_dual_sub_f32 v7, v7, v10 :: v_dual_add_f32 v10, 0xbf2aaaaa, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, 0x31739010, v7
v_sub_f32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v7, v9
v_add_f32_e32 v6, v11, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v9, v11, v6
v_mul_f32_e32 v10, v8, v6
v_sub_f32_e32 v11, v8, v12
v_add_f32_e32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, v8, v6, -v10
v_sub_f32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v8, v7
v_fmac_f32_e32 v9, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v10, v9
v_add_f32_e32 v7, v4, v6
v_sub_f32_e32 v8, v6, v10
v_mul_f32_e32 v10, 0x3f317218, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v4, v7, v4
v_sub_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, v2, 0x3f317218, -v10
v_sub_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v8 :: v_dual_fmamk_f32 v2, v2, 0xb102e308, v9
v_dual_add_f32 v3, v3, v4 :: v_dual_add_f32 v4, v10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v7, v3
v_sub_f32_e32 v10, v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v8, v4, v6 :: v_dual_sub_f32 v7, v6, v7
v_dual_sub_f32 v2, v2, v10 :: v_dual_sub_f32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v7, v2, v3
v_sub_f32_e32 v9, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v8, v9
v_sub_f32_e32 v6, v6, v9
v_sub_f32_e32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v6, v4
v_sub_f32_e32 v6, v7, v2
v_add_f32_e32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v6
v_sub_f32_e32 v3, v3, v6
v_dual_add_f32 v9, v8, v4 :: v_dual_sub_f32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v9, v8
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v4, v6
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v9, v2
v_mul_f32_e32 v6, v5, v3
v_sub_f32_e32 v4, v3, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v5, v3, -v6
v_sub_f32_e32 v2, v2, v4
v_cmp_class_f32_e64 s0, v6, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v2
v_add_f32_e32 v2, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, v2, v6, s0
v_cmp_eq_f32_e64 s0, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, 0, 0x37000000, s0
v_cmp_neq_f32_e64 s0, 0x7f800000, |v4|
v_sub_f32_e32 v8, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v9, 0x3fb8aa3b, v8 :: v_dual_sub_f32 v2, v2, v6
v_fma_f32 v10, v8, 0x3fb8aa3b, -v9
v_rndne_f32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v2, v3, v2
v_dual_fmamk_f32 v10, v8, 0x32a5705f, v10 :: v_dual_sub_f32 v9, v9, v11
v_cvt_i32_f32_e32 v6, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v2, 0, v2, s0
v_cmp_ngt_f32_e64 s0, 0xc2ce8ed0, v8
v_add_f32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v2, v7, v2
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, 0, v3, s0
v_cmp_nlt_f32_e64 s0, 0x42b17218, v8
v_cndmask_b32_e64 v3, 0x7f800000, v3, s0
v_cmp_eq_f32_e64 s0, |v5|, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v3, v2, v3
v_cndmask_b32_e64 v4, 0, |v5|, s0
v_cmp_class_f32_e64 s0, v5, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v4, 1.0, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v3
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v5, v5
v_cndmask_b32_e64 v2, |v2|, v4, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, 0x7fc00000, v2, vcc_lo
v_add_f32_e32 v3, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v3, v3, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v3, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v4, v4, v3, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
global_store_b32 v[0:1], v4, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15calculate_indexPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15calculate_indexPfS_i, .Lfunc_end0-_Z15calculate_indexPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15calculate_indexPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15calculate_indexPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a8c0a_00000000-6_botrixindex.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3806:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3806:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl init
.type init, @function
init:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %edi
call cudaSetDevice@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size init, .-init
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB3803:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L8
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3803:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z38__device_stub__Z15calculate_indexPfS_iPfS_i
.type _Z38__device_stub__Z15calculate_indexPfS_iPfS_i, @function
_Z38__device_stub__Z15calculate_indexPfS_iPfS_i:
.LFB3828:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15calculate_indexPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3828:
.size _Z38__device_stub__Z15calculate_indexPfS_iPfS_i, .-_Z38__device_stub__Z15calculate_indexPfS_iPfS_i
.globl _Z15calculate_indexPfS_i
.type _Z15calculate_indexPfS_i, @function
_Z15calculate_indexPfS_i:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15calculate_indexPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _Z15calculate_indexPfS_i, .-_Z15calculate_indexPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "Numero threads per blocco: %d\n"
.section .rodata.str1.1
.LC6:
.string "Dimensioni grid: x %d, y %d\n"
.LC7:
.string "Allocazione"
.LC8:
.string "Trasferimento su device"
.LC9:
.string "Kernel"
.LC10:
.string "Trasferimento da device"
.text
.globl botrix_index
.type botrix_index, @function
botrix_index:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %r12d
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
testl $511, %edx
setne %bpl
movzbl %bpl, %ebp
movslq %edx, %rdx
leaq 511(%rdx), %rax
testq %rdx, %rdx
cmovns %rdx, %rax
sarq $9, %rax
addl %eax, %ebp
movl $1, %r15d
cmpl $65535, %ebp
jg .L30
.L18:
movl $512, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl %ebp, 32(%rsp)
movl %r15d, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
leaq .LC9(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC10(%rip), %rdi
call _Z14checkCUDAErrorPKc
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pxor %xmm5, %xmm5
cvtsi2sdl %ebp, %xmm5
movsd %xmm5, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm5, %xmm0
ja .L28
sqrtsd %xmm5, %xmm5
movapd %xmm5, %xmm0
movapd %xmm5, %xmm3
movsd .LC11(%rip), %xmm2
movapd %xmm5, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L21
cvttsd2siq %xmm5, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm5, %xmm2
orpd %xmm2, %xmm3
.L21:
cvttsd2siq %xmm3, %rbp
.L22:
movapd %xmm0, %xmm3
movsd .LC11(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC2(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L23
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC4(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L23:
cvttsd2siq %xmm3, %r15
jmp .L18
.L28:
movsd 8(%rsp), %xmm0
call sqrt@PLT
call ceil@PLT
cvttsd2siq %xmm0, %rbp
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L22
.L31:
movl %r12d, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z38__device_stub__Z15calculate_indexPfS_iPfS_i
jmp .L24
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size botrix_index, .-botrix_index
.section .rodata.str1.1
.LC12:
.string "_Z15calculate_indexPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3831:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15calculate_indexPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3831:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.8
.align 8
.LC13:
.string "./a.out tempday.txt precday.txt lunghezza\n"
.section .rodata.str1.1
.LC14:
.string "%d"
.LC15:
.string "Risultato botrite:\n"
.LC16:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1112, %rsp
.cfi_def_cfa_offset 1168
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
.LEHB0:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE0:
leaq 560(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
cmpl $2, %ebp
jg .L36
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L36:
movq 8(%rbx), %rsi
leaq 32(%rsp), %rdi
movl $8, %edx
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movq 16(%rbx), %rsi
leaq 560(%rsp), %rdi
movl $8, %edx
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
leaq 28(%rsp), %rdx
movq 24(%rbx), %rdi
leaq .LC14(%rip), %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movslq 28(%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
leaq .LC7(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl 28(%rsp), %edx
testl %edx, %edx
jle .L37
movq %r15, %rbp
movl $0, %ebx
leaq 32(%rsp), %r14
jmp .L38
.L51:
leaq 560(%rsp), %rdi
movq %rbp, %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
addl $1, %ebx
movl 28(%rsp), %edx
addq $4, %r12
addq $4, %rbp
cmpl %ebx, %edx
jle .L37
.L38:
movq %r12, %rsi
movq %r14, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L51
.L37:
movq %r13, %rcx
movq %r15, %rsi
movq 8(%rsp), %rdi
call botrix_index
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 28(%rsp)
jle .L39
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
leaq .LC16(%rip), %r12
jmp .L40
.L52:
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpl %ebx, 28(%rsp)
jle .L39
.L40:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
.LEHE2:
jmp .L52
.L39:
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
leaq 560(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 32(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $1112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 560(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
.L42:
leaq 32(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
je .L43
call __stack_chk_fail@PLT
.L45:
endbr64
movq %rax, %rbx
jmp .L42
.L43:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3802:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB0-.LFB3802
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3802
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB3802
.uleb128 0
.uleb128 .LEHB2-.LFB3802
.uleb128 .LEHE2-.LEHB2
.uleb128 .L46-.LFB3802
.uleb128 0
.uleb128 .LEHB3-.LFB3802
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1127219200
.align 8
.LC4:
.long 0
.long 1072693248
.align 8
.LC11:
.long -1
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "botrixindex.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__calculate_indexPfS_i # -- Begin function _Z30__device_stub__calculate_indexPfS_i
.p2align 4, 0x90
.type _Z30__device_stub__calculate_indexPfS_i,@function
_Z30__device_stub__calculate_indexPfS_i: # @_Z30__device_stub__calculate_indexPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15calculate_indexPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__calculate_indexPfS_i, .Lfunc_end0-_Z30__device_stub__calculate_indexPfS_i
.cfi_endproc
# -- End function
.globl init # -- Begin function init
.p2align 4, 0x90
.type init,@function
init: # @init
.cfi_startproc
# %bb.0:
xorl %edi, %edi
jmp hipSetDevice # TAILCALL
.Lfunc_end1:
.size init, .Lfunc_end1-init
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function botrix_index
.LCPI2_0:
.quad 0x0000000000000000 # double 0
.text
.globl botrix_index
.p2align 4, 0x90
.type botrix_index,@function
botrix_index: # @botrix_index
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r12
movl %edx, %ebp
movq %rsi, 56(%rsp) # 8-byte Spill
movq %rdi, %r13
movslq %edx, %r14
leaq 511(%r14), %rax
testq %r14, %r14
cmovnsq %r14, %rax
movabsq $4294967296, %r15 # imm = 0x100000000
sarq $9, %rax
movl %edx, %ecx
andl $511, %ecx # imm = 0x1FF
cmpq $1, %rcx
sbbq $-1, %rax
cmpq $65535, %rax # imm = 0xFFFF
jg .LBB2_2
# %bb.1:
movl %eax, %ebx
orq %r15, %rbx
jmp .LBB2_7
.LBB2_2:
movq %r12, 48(%rsp) # 8-byte Spill
cvtsi2sd %eax, %xmm1
sqrtsd %xmm1, %xmm0
xorpd %xmm2, %xmm2
movsd %xmm1, 16(%rsp) # 8-byte Spill
ucomisd %xmm2, %xmm1
movsd %xmm0, 40(%rsp) # 8-byte Spill
jae .LBB2_4
# %bb.3: # %call.sqrt
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sqrt
.LBB2_4: # %.split
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %r12d
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd .LCPI2_0(%rip), %xmm0
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
jae .LBB2_6
# %bb.5: # %call.sqrt43
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sqrt
.LBB2_6: # %.split.split
callq ceil@PLT
cvttsd2si %xmm0, %rbx
shlq $32, %rbx
orq %r12, %rbx
movq 48(%rsp), %r12 # 8-byte Reload
.LBB2_7:
movl $.L.str.1, %edi
movl $512, %esi # imm = 0x200
xorl %eax, %eax
callq printf
movq %rbx, %rdx
shrq $32, %rdx
movl $.L.str.2, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
shlq $2, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_8
# %bb.10: # %_Z14checkCUDAErrorPKc.exit
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_11
# %bb.12: # %_Z14checkCUDAErrorPKc.exit23
addq $512, %r15 # imm = 0x200
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl %ebp, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z15calculate_indexPfS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
jne .LBB2_15
# %bb.16: # %_Z14checkCUDAErrorPKc.exit25
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB2_17
# %bb.18: # %_Z14checkCUDAErrorPKc.exit27
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 208
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.3, %edx
jmp .LBB2_9
.LBB2_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.4, %edx
jmp .LBB2_9
.LBB2_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.5, %edx
jmp .LBB2_9
.LBB2_17:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %edx
.LBB2_9:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size botrix_index, .Lfunc_end2-botrix_index
.cfi_endproc
# -- End function
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z14checkCUDAErrorPKc, .Lfunc_end3-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 1136
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 552(%rsp), %r15
movq %r15, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
.Ltmp0:
leaq 24(%rsp), %r14
movq %r14, %rdi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
.Ltmp1:
# %bb.1:
cmpl $2, %ebp
jle .LBB4_2
# %bb.5:
movq 8(%rbx), %rsi
leaq 576(%rsp), %rdi
.Ltmp3:
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp4:
# %bb.6: # %.noexc
movq 552(%rsp), %rcx
addq -24(%rcx), %r15
xorl %esi, %esi
testq %rax, %rax
jne .LBB4_8
# %bb.7:
movl 32(%r15), %esi
orl $4, %esi
.LBB4_8: # %.invoke55
.Ltmp5:
movq %r15, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp6:
# %bb.9: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
movq 16(%rbx), %rsi
leaq 48(%rsp), %rdi
.Ltmp7:
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp8:
# %bb.10: # %.noexc31
movq 24(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB4_12
# %bb.11:
movl 32(%r14), %esi
orl $4, %esi
.LBB4_12: # %.invoke
.Ltmp9:
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp10:
# %bb.13: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit34
movq 24(%rbx), %rdi
leaq 4(%rsp), %rdx
movl $.L.str.8, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movslq 4(%rsp), %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq %rbx, %rdi
callq malloc
movq %rax, %r15
.Ltmp11:
callq hipGetLastError
.Ltmp12:
# %bb.14: # %.noexc36
testl %eax, %eax
jne .LBB4_29
# %bb.15: # %_Z14checkCUDAErrorPKc.exit.preheader
movl 4(%rsp), %edx
testl %edx, %edx
jle .LBB4_21
# %bb.16: # %.lr.ph.preheader
movq %r14, %rbx
xorl %r14d, %r14d
leaq 552(%rsp), %r12
leaq 24(%rsp), %r13
movq %rbp, 8(%rsp) # 8-byte Spill
movq %rbx, 16(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB4_17: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp15:
movq %r12, %rdi
movq %rbp, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp16:
# %bb.18: # %_ZNSirsERf.exit
# in Loop: Header=BB4_17 Depth=1
.Ltmp17:
movq %r13, %rdi
movq %rbx, %rsi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp18:
# %bb.19: # %_ZNSirsERf.exit40
# in Loop: Header=BB4_17 Depth=1
incq %r14
movslq 4(%rsp), %rdx
addq $4, %rbx
addq $4, %rbp
cmpq %rdx, %r14
jl .LBB4_17
# %bb.20:
movq 16(%rsp), %r14 # 8-byte Reload
movq 8(%rsp), %rbp # 8-byte Reload
.LBB4_21: # %_Z14checkCUDAErrorPKc.exit._crit_edge
.Ltmp20:
movq %rbp, %rdi
movq %r14, %rsi
# kill: def $edx killed $edx killed $rdx
movq %r15, %rcx
callq botrix_index
.Ltmp21:
# %bb.22:
.Ltmp22:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.23: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit.preheader
cmpl $0, 4(%rsp)
jle .LBB4_28
# %bb.24: # %.lr.ph48.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_25: # %.lr.ph48
# =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp25:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp26:
# %bb.26: # %_ZNSolsEf.exit
# in Loop: Header=BB4_25 Depth=1
.Ltmp27:
movl $.L.str.10, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
# %bb.27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit44
# in Loop: Header=BB4_25 Depth=1
incq %rbx
movslq 4(%rsp), %rax
cmpq %rax, %rbx
jl .LBB4_25
.LBB4_28: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit._crit_edge
movq %r14, %rdi
callq free
movq %rbp, %rdi
callq free
leaq 24(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
leaq 552(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 816(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
xorl %eax, %eax
addq $1080, %rsp # imm = 0x438
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_2:
.cfi_def_cfa_offset 1136
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.LBB4_29:
movq stderr(%rip), %rbx
.Ltmp13:
movl %eax, %edi
callq hipGetErrorString
.Ltmp14:
# %bb.30: # %.noexc37
movl $.L.str.11, %esi
movl $.L.str.3, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB4_3:
.Ltmp2:
movq %rax, %rbx
jmp .LBB4_34
.LBB4_4:
.Ltmp24:
jmp .LBB4_33
.LBB4_32:
.Ltmp29:
jmp .LBB4_33
.LBB4_31:
.Ltmp19:
.LBB4_33:
movq %rax, %rbx
leaq 24(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 288(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
.LBB4_34:
leaq 552(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 816(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp18-.Ltmp15 # Call between .Ltmp15 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp20 # Call between .Ltmp20 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp28-.Ltmp25 # Call between .Ltmp25 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end4-.Ltmp14 # Call between .Ltmp14 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15calculate_indexPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15calculate_indexPfS_i,@object # @_Z15calculate_indexPfS_i
.section .rodata,"a",@progbits
.globl _Z15calculate_indexPfS_i
.p2align 3, 0x0
_Z15calculate_indexPfS_i:
.quad _Z30__device_stub__calculate_indexPfS_i
.size _Z15calculate_indexPfS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Numero threads per blocco: %d\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Dimensioni grid: x %d, y %d\n"
.size .L.str.2, 30
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocazione"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Trasferimento su device"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Kernel"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Trasferimento da device"
.size .L.str.6, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Risultato botrite:\n"
.size .L.str.9, 20
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " "
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Cuda error: %s: %s.\n"
.size .L.str.11, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15calculate_indexPfS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "./a.out tempday.txt precday.txt lunghezza"
.size .Lstr, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__calculate_indexPfS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z15calculate_indexPfS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include "cuda.h"
//device function
__global__ void kernelAddVectors(int N, double *a, double *b, double *c) {
int threadid = threadIdx.x; //thread number
int blockid = blockIdx.x; //block number
int Nblock = blockDim.x; //number of threads in a block
int id = threadid + blockid*Nblock;
if (id < N) {
c[id] = a[id] + b[id];
}
}
int main(int argc, char **argv) {
// get vector size from command line argument
int N = atoi(argv[1]);
//seed RNG
double seed = clock();
srand48(seed);
double *h_a, *h_b, *h_c; //host vectors
// allocate storage
h_a = (double *) malloc(N*sizeof(double));
h_b = (double *) malloc(N*sizeof(double));
h_c = (double *) malloc(N*sizeof(double));
//populate a and b
for (int n=0;n<N;n++) {
h_a[n] = drand48();
h_b[n] = drand48();
}
double hostStart = clock();
// c = a + b
for (int n=0;n<N;n++) {
h_c[n] = h_a[n] + h_b[n];
}
double hostEnd = clock();
double hostTime = (hostEnd - hostStart)/(double) CLOCKS_PER_SEC;
size_t inputMem = 2*N*sizeof(double); //number of bytes the operation inputs
size_t outMem = 1*N*sizeof(double); //number of bytes the operation outputs
size_t totalMem = (inputMem+outMem);
printf("The host took %f seconds to add a and b \n", hostTime);
printf("The efective bandwidth of the host was: %f GB/s\n", totalMem/(1E9*hostTime));
//Device arrays
double *d_a, *d_b, *d_c;
//allocate memory on the Device with cudaMalloc
cudaMalloc(&d_a,N*sizeof(double));
cudaMalloc(&d_b,N*sizeof(double));
cudaMalloc(&d_c,N*sizeof(double));
double copyStart = clock();
//copy data from the host to the device
cudaMemcpy(d_a,h_a,N*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,N*sizeof(double),cudaMemcpyHostToDevice);
double copyEnd = clock();
double copyTime = (copyEnd-copyStart)/(double)CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data to device. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", inputMem/(1E9*copyTime));
//at this point the data is allocated and populated on the device
int Nthreads = atoi(argv[2]); //get the number of threads per block from command line
int Nblocks = (N+Nthreads-1)/Nthreads;
double deviceStart = clock();
kernelAddVectors <<<Nblocks ,Nthreads >>>(N, d_a, d_b, d_c);
cudaDeviceSynchronize();
double deviceEnd = clock();
double deviceTime = (deviceEnd-deviceStart)/(double) CLOCKS_PER_SEC;
printf("The device took %f seconds to add a and b \n", deviceTime);
printf("The efective bandwidth of the device was: %f GB/s\n", totalMem/(1E9*deviceTime));
printf("The device was %f times faster\n", hostTime/deviceTime);
copyStart = clock();
cudaMemcpy(h_c,d_c,N*sizeof(double),cudaMemcpyDeviceToHost);
copyEnd = clock();
copyTime = (copyEnd-copyStart)/(double) CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data back to the host. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", outMem/(1E9*copyTime));
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | code for sm_80
Function : _Z16kernelAddVectorsiPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x001fca00078e0208 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include "cuda.h"
//device function
__global__ void kernelAddVectors(int N, double *a, double *b, double *c) {
int threadid = threadIdx.x; //thread number
int blockid = blockIdx.x; //block number
int Nblock = blockDim.x; //number of threads in a block
int id = threadid + blockid*Nblock;
if (id < N) {
c[id] = a[id] + b[id];
}
}
int main(int argc, char **argv) {
// get vector size from command line argument
int N = atoi(argv[1]);
//seed RNG
double seed = clock();
srand48(seed);
double *h_a, *h_b, *h_c; //host vectors
// allocate storage
h_a = (double *) malloc(N*sizeof(double));
h_b = (double *) malloc(N*sizeof(double));
h_c = (double *) malloc(N*sizeof(double));
//populate a and b
for (int n=0;n<N;n++) {
h_a[n] = drand48();
h_b[n] = drand48();
}
double hostStart = clock();
// c = a + b
for (int n=0;n<N;n++) {
h_c[n] = h_a[n] + h_b[n];
}
double hostEnd = clock();
double hostTime = (hostEnd - hostStart)/(double) CLOCKS_PER_SEC;
size_t inputMem = 2*N*sizeof(double); //number of bytes the operation inputs
size_t outMem = 1*N*sizeof(double); //number of bytes the operation outputs
size_t totalMem = (inputMem+outMem);
printf("The host took %f seconds to add a and b \n", hostTime);
printf("The efective bandwidth of the host was: %f GB/s\n", totalMem/(1E9*hostTime));
//Device arrays
double *d_a, *d_b, *d_c;
//allocate memory on the Device with cudaMalloc
cudaMalloc(&d_a,N*sizeof(double));
cudaMalloc(&d_b,N*sizeof(double));
cudaMalloc(&d_c,N*sizeof(double));
double copyStart = clock();
//copy data from the host to the device
cudaMemcpy(d_a,h_a,N*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,N*sizeof(double),cudaMemcpyHostToDevice);
double copyEnd = clock();
double copyTime = (copyEnd-copyStart)/(double)CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data to device. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", inputMem/(1E9*copyTime));
//at this point the data is allocated and populated on the device
int Nthreads = atoi(argv[2]); //get the number of threads per block from command line
int Nblocks = (N+Nthreads-1)/Nthreads;
double deviceStart = clock();
kernelAddVectors <<<Nblocks ,Nthreads >>>(N, d_a, d_b, d_c);
cudaDeviceSynchronize();
double deviceEnd = clock();
double deviceTime = (deviceEnd-deviceStart)/(double) CLOCKS_PER_SEC;
printf("The device took %f seconds to add a and b \n", deviceTime);
printf("The efective bandwidth of the device was: %f GB/s\n", totalMem/(1E9*deviceTime));
printf("The device was %f times faster\n", hostTime/deviceTime);
copyStart = clock();
cudaMemcpy(h_c,d_c,N*sizeof(double),cudaMemcpyDeviceToHost);
copyEnd = clock();
copyTime = (copyEnd-copyStart)/(double) CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data back to the host. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", outMem/(1E9*copyTime));
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | .file "tmpxft_0004c0a4_00000000-6_addVectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
.type _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_, @function
_Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16kernelAddVectorsiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_, .-_Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
.globl _Z16kernelAddVectorsiPdS_S_
.type _Z16kernelAddVectorsiPdS_S_, @function
_Z16kernelAddVectorsiPdS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16kernelAddVectorsiPdS_S_, .-_Z16kernelAddVectorsiPdS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The host took %f seconds to add a and b \n"
.align 8
.LC3:
.string "The efective bandwidth of the host was: %f GB/s\n"
.align 8
.LC4:
.string "It took %f seconds to copy the data to device. \n"
.align 8
.LC5:
.string "The efective bandwidth of the copy was: %f GB/s\n"
.align 8
.LC6:
.string "The device took %f seconds to add a and b \n"
.align 8
.LC7:
.string "The efective bandwidth of the device was: %f GB/s\n"
.align 8
.LC8:
.string "The device was %f times faster\n"
.align 8
.LC9:
.string "It took %f seconds to copy the data back to the host. \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, 32(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl %eax, 44(%rsp)
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cvttsd2siq %xmm0, %rdi
call srand48@PLT
movslq %ebx, %r14
salq $3, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L12
leal -1(%rbx), %r13d
movl $0, %ebx
.L13:
call drand48@PLT
movsd %xmm0, 0(%rbp,%rbx,8)
call drand48@PLT
movsd %xmm0, (%r12,%rbx,8)
movq %rbx, %rax
addq $1, %rbx
cmpq %r13, %rax
jne .L13
call clock@PLT
pxor %xmm7, %xmm7
cvtsi2sdq %rax, %xmm7
movsd %xmm7, (%rsp)
movl $0, %eax
.L14:
movsd 0(%rbp,%rax,8), %xmm0
addsd (%r12,%rax,8), %xmm0
movsd %xmm0, (%r15,%rax,8)
movq %rax, %rdx
addq $1, %rax
cmpq %r13, %rdx
jne .L14
.L22:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd (%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rsp)
movl 8(%rsp), %eax
leal (%rax,%rax), %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq (%r14,%rbx), %r13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %r13, %r13
js .L15
pxor %xmm7, %xmm7
cvtsi2sdq %r13, %xmm7
movsd %xmm7, 16(%rsp)
.L16:
movsd (%rsp), %xmm1
mulsd .LC2(%rip), %xmm1
movsd 16(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
call clock@PLT
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
movsd %xmm3, 24(%rsp)
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 24(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %r13
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %rbx, %rbx
js .L17
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L18:
movq %r13, %xmm1
mulsd .LC2(%rip), %xmm1
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rax
movq 16(%rax), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 8(%rsp), %rax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, %r13d
call clock@PLT
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movsd %xmm4, 8(%rsp)
movl %ebx, 92(%rsp)
movl $1, 96(%rsp)
movl %r13d, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm1
mulsd .LC2(%rip), %xmm1
movsd 16(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
divsd 8(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm6, %xmm6
cvtsi2sdq %rax, %xmm6
movsd %xmm6, (%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 72(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd (%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %r14, %r14
js .L20
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
.L21:
movq %rbx, %xmm1
mulsd .LC2(%rip), %xmm1
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
shrq %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
addsd %xmm0, %xmm0
movsd %xmm0, 16(%rsp)
jmp .L16
.L17:
shrq %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
addsd %xmm0, %xmm0
jmp .L18
.L28:
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movl 44(%rsp), %edi
call _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
jmp .L19
.L20:
shrq %r14
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
addsd %xmm0, %xmm0
jmp .L21
.L12:
call clock@PLT
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movsd %xmm2, (%rsp)
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "_Z16kernelAddVectorsiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernelAddVectorsiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC2:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include "cuda.h"
//device function
__global__ void kernelAddVectors(int N, double *a, double *b, double *c) {
int threadid = threadIdx.x; //thread number
int blockid = blockIdx.x; //block number
int Nblock = blockDim.x; //number of threads in a block
int id = threadid + blockid*Nblock;
if (id < N) {
c[id] = a[id] + b[id];
}
}
int main(int argc, char **argv) {
// get vector size from command line argument
int N = atoi(argv[1]);
//seed RNG
double seed = clock();
srand48(seed);
double *h_a, *h_b, *h_c; //host vectors
// allocate storage
h_a = (double *) malloc(N*sizeof(double));
h_b = (double *) malloc(N*sizeof(double));
h_c = (double *) malloc(N*sizeof(double));
//populate a and b
for (int n=0;n<N;n++) {
h_a[n] = drand48();
h_b[n] = drand48();
}
double hostStart = clock();
// c = a + b
for (int n=0;n<N;n++) {
h_c[n] = h_a[n] + h_b[n];
}
double hostEnd = clock();
double hostTime = (hostEnd - hostStart)/(double) CLOCKS_PER_SEC;
size_t inputMem = 2*N*sizeof(double); //number of bytes the operation inputs
size_t outMem = 1*N*sizeof(double); //number of bytes the operation outputs
size_t totalMem = (inputMem+outMem);
printf("The host took %f seconds to add a and b \n", hostTime);
printf("The efective bandwidth of the host was: %f GB/s\n", totalMem/(1E9*hostTime));
//Device arrays
double *d_a, *d_b, *d_c;
//allocate memory on the Device with cudaMalloc
cudaMalloc(&d_a,N*sizeof(double));
cudaMalloc(&d_b,N*sizeof(double));
cudaMalloc(&d_c,N*sizeof(double));
double copyStart = clock();
//copy data from the host to the device
cudaMemcpy(d_a,h_a,N*sizeof(double),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,N*sizeof(double),cudaMemcpyHostToDevice);
double copyEnd = clock();
double copyTime = (copyEnd-copyStart)/(double)CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data to device. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", inputMem/(1E9*copyTime));
//at this point the data is allocated and populated on the device
int Nthreads = atoi(argv[2]); //get the number of threads per block from command line
int Nblocks = (N+Nthreads-1)/Nthreads;
double deviceStart = clock();
kernelAddVectors <<<Nblocks ,Nthreads >>>(N, d_a, d_b, d_c);
cudaDeviceSynchronize();
double deviceEnd = clock();
double deviceTime = (deviceEnd-deviceStart)/(double) CLOCKS_PER_SEC;
printf("The device took %f seconds to add a and b \n", deviceTime);
printf("The efective bandwidth of the device was: %f GB/s\n", totalMem/(1E9*deviceTime));
printf("The device was %f times faster\n", hostTime/deviceTime);
copyStart = clock();
cudaMemcpy(h_c,d_c,N*sizeof(double),cudaMemcpyDeviceToHost);
copyEnd = clock();
copyTime = (copyEnd-copyStart)/(double) CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data back to the host. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", outMem/(1E9*copyTime));
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include "hip/hip_runtime.h"
//device function
__global__ void kernelAddVectors(int N, double *a, double *b, double *c) {
int threadid = threadIdx.x; //thread number
int blockid = blockIdx.x; //block number
int Nblock = blockDim.x; //number of threads in a block
int id = threadid + blockid*Nblock;
if (id < N) {
c[id] = a[id] + b[id];
}
}
int main(int argc, char **argv) {
// get vector size from command line argument
int N = atoi(argv[1]);
//seed RNG
double seed = clock();
srand48(seed);
double *h_a, *h_b, *h_c; //host vectors
// allocate storage
h_a = (double *) malloc(N*sizeof(double));
h_b = (double *) malloc(N*sizeof(double));
h_c = (double *) malloc(N*sizeof(double));
//populate a and b
for (int n=0;n<N;n++) {
h_a[n] = drand48();
h_b[n] = drand48();
}
double hostStart = clock();
// c = a + b
for (int n=0;n<N;n++) {
h_c[n] = h_a[n] + h_b[n];
}
double hostEnd = clock();
double hostTime = (hostEnd - hostStart)/(double) CLOCKS_PER_SEC;
size_t inputMem = 2*N*sizeof(double); //number of bytes the operation inputs
size_t outMem = 1*N*sizeof(double); //number of bytes the operation outputs
size_t totalMem = (inputMem+outMem);
printf("The host took %f seconds to add a and b \n", hostTime);
printf("The efective bandwidth of the host was: %f GB/s\n", totalMem/(1E9*hostTime));
//Device arrays
double *d_a, *d_b, *d_c;
//allocate memory on the Device with cudaMalloc
hipMalloc(&d_a,N*sizeof(double));
hipMalloc(&d_b,N*sizeof(double));
hipMalloc(&d_c,N*sizeof(double));
double copyStart = clock();
//copy data from the host to the device
hipMemcpy(d_a,h_a,N*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,N*sizeof(double),hipMemcpyHostToDevice);
double copyEnd = clock();
double copyTime = (copyEnd-copyStart)/(double)CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data to device. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", inputMem/(1E9*copyTime));
//at this point the data is allocated and populated on the device
int Nthreads = atoi(argv[2]); //get the number of threads per block from command line
int Nblocks = (N+Nthreads-1)/Nthreads;
double deviceStart = clock();
kernelAddVectors <<<Nblocks ,Nthreads >>>(N, d_a, d_b, d_c);
hipDeviceSynchronize();
double deviceEnd = clock();
double deviceTime = (deviceEnd-deviceStart)/(double) CLOCKS_PER_SEC;
printf("The device took %f seconds to add a and b \n", deviceTime);
printf("The efective bandwidth of the device was: %f GB/s\n", totalMem/(1E9*deviceTime));
printf("The device was %f times faster\n", hostTime/deviceTime);
copyStart = clock();
hipMemcpy(h_c,d_c,N*sizeof(double),hipMemcpyDeviceToHost);
copyEnd = clock();
copyTime = (copyEnd-copyStart)/(double) CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data back to the host. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", outMem/(1E9*copyTime));
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include "hip/hip_runtime.h"
//device function
__global__ void kernelAddVectors(int N, double *a, double *b, double *c) {
int threadid = threadIdx.x; //thread number
int blockid = blockIdx.x; //block number
int Nblock = blockDim.x; //number of threads in a block
int id = threadid + blockid*Nblock;
if (id < N) {
c[id] = a[id] + b[id];
}
}
int main(int argc, char **argv) {
// get vector size from command line argument
int N = atoi(argv[1]);
//seed RNG
double seed = clock();
srand48(seed);
double *h_a, *h_b, *h_c; //host vectors
// allocate storage
h_a = (double *) malloc(N*sizeof(double));
h_b = (double *) malloc(N*sizeof(double));
h_c = (double *) malloc(N*sizeof(double));
//populate a and b
for (int n=0;n<N;n++) {
h_a[n] = drand48();
h_b[n] = drand48();
}
double hostStart = clock();
// c = a + b
for (int n=0;n<N;n++) {
h_c[n] = h_a[n] + h_b[n];
}
double hostEnd = clock();
double hostTime = (hostEnd - hostStart)/(double) CLOCKS_PER_SEC;
size_t inputMem = 2*N*sizeof(double); //number of bytes the operation inputs
size_t outMem = 1*N*sizeof(double); //number of bytes the operation outputs
size_t totalMem = (inputMem+outMem);
printf("The host took %f seconds to add a and b \n", hostTime);
printf("The efective bandwidth of the host was: %f GB/s\n", totalMem/(1E9*hostTime));
//Device arrays
double *d_a, *d_b, *d_c;
//allocate memory on the Device with cudaMalloc
hipMalloc(&d_a,N*sizeof(double));
hipMalloc(&d_b,N*sizeof(double));
hipMalloc(&d_c,N*sizeof(double));
double copyStart = clock();
//copy data from the host to the device
hipMemcpy(d_a,h_a,N*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,N*sizeof(double),hipMemcpyHostToDevice);
double copyEnd = clock();
double copyTime = (copyEnd-copyStart)/(double)CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data to device. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", inputMem/(1E9*copyTime));
//at this point the data is allocated and populated on the device
int Nthreads = atoi(argv[2]); //get the number of threads per block from command line
int Nblocks = (N+Nthreads-1)/Nthreads;
double deviceStart = clock();
kernelAddVectors <<<Nblocks ,Nthreads >>>(N, d_a, d_b, d_c);
hipDeviceSynchronize();
double deviceEnd = clock();
double deviceTime = (deviceEnd-deviceStart)/(double) CLOCKS_PER_SEC;
printf("The device took %f seconds to add a and b \n", deviceTime);
printf("The efective bandwidth of the device was: %f GB/s\n", totalMem/(1E9*deviceTime));
printf("The device was %f times faster\n", hostTime/deviceTime);
copyStart = clock();
hipMemcpy(h_c,d_c,N*sizeof(double),hipMemcpyDeviceToHost);
copyEnd = clock();
copyTime = (copyEnd-copyStart)/(double) CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data back to the host. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", outMem/(1E9*copyTime));
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kernelAddVectorsiPdS_S_
.globl _Z16kernelAddVectorsiPdS_S_
.p2align 8
.type _Z16kernelAddVectorsiPdS_S_,@function
_Z16kernelAddVectorsiPdS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernelAddVectorsiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kernelAddVectorsiPdS_S_, .Lfunc_end0-_Z16kernelAddVectorsiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernelAddVectorsiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kernelAddVectorsiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#include "hip/hip_runtime.h"
//device function
__global__ void kernelAddVectors(int N, double *a, double *b, double *c) {
int threadid = threadIdx.x; //thread number
int blockid = blockIdx.x; //block number
int Nblock = blockDim.x; //number of threads in a block
int id = threadid + blockid*Nblock;
if (id < N) {
c[id] = a[id] + b[id];
}
}
int main(int argc, char **argv) {
// get vector size from command line argument
int N = atoi(argv[1]);
//seed RNG
double seed = clock();
srand48(seed);
double *h_a, *h_b, *h_c; //host vectors
// allocate storage
h_a = (double *) malloc(N*sizeof(double));
h_b = (double *) malloc(N*sizeof(double));
h_c = (double *) malloc(N*sizeof(double));
//populate a and b
for (int n=0;n<N;n++) {
h_a[n] = drand48();
h_b[n] = drand48();
}
double hostStart = clock();
// c = a + b
for (int n=0;n<N;n++) {
h_c[n] = h_a[n] + h_b[n];
}
double hostEnd = clock();
double hostTime = (hostEnd - hostStart)/(double) CLOCKS_PER_SEC;
size_t inputMem = 2*N*sizeof(double); //number of bytes the operation inputs
size_t outMem = 1*N*sizeof(double); //number of bytes the operation outputs
size_t totalMem = (inputMem+outMem);
printf("The host took %f seconds to add a and b \n", hostTime);
printf("The efective bandwidth of the host was: %f GB/s\n", totalMem/(1E9*hostTime));
//Device arrays
double *d_a, *d_b, *d_c;
//allocate memory on the Device with cudaMalloc
hipMalloc(&d_a,N*sizeof(double));
hipMalloc(&d_b,N*sizeof(double));
hipMalloc(&d_c,N*sizeof(double));
double copyStart = clock();
//copy data from the host to the device
hipMemcpy(d_a,h_a,N*sizeof(double),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,N*sizeof(double),hipMemcpyHostToDevice);
double copyEnd = clock();
double copyTime = (copyEnd-copyStart)/(double)CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data to device. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", inputMem/(1E9*copyTime));
//at this point the data is allocated and populated on the device
int Nthreads = atoi(argv[2]); //get the number of threads per block from command line
int Nblocks = (N+Nthreads-1)/Nthreads;
double deviceStart = clock();
kernelAddVectors <<<Nblocks ,Nthreads >>>(N, d_a, d_b, d_c);
hipDeviceSynchronize();
double deviceEnd = clock();
double deviceTime = (deviceEnd-deviceStart)/(double) CLOCKS_PER_SEC;
printf("The device took %f seconds to add a and b \n", deviceTime);
printf("The efective bandwidth of the device was: %f GB/s\n", totalMem/(1E9*deviceTime));
printf("The device was %f times faster\n", hostTime/deviceTime);
copyStart = clock();
hipMemcpy(h_c,d_c,N*sizeof(double),hipMemcpyDeviceToHost);
copyEnd = clock();
copyTime = (copyEnd-copyStart)/(double) CLOCKS_PER_SEC;
printf("It took %f seconds to copy the data back to the host. \n",copyTime);
printf("The efective bandwidth of the copy was: %f GB/s\n", outMem/(1E9*copyTime));
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_a);
free(h_b);
free(h_c);
} | .text
.file "addVectors.hip"
.globl _Z31__device_stub__kernelAddVectorsiPdS_S_ # -- Begin function _Z31__device_stub__kernelAddVectorsiPdS_S_
.p2align 4, 0x90
.type _Z31__device_stub__kernelAddVectorsiPdS_S_,@function
_Z31__device_stub__kernelAddVectorsiPdS_S_: # @_Z31__device_stub__kernelAddVectorsiPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16kernelAddVectorsiPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__kernelAddVectorsiPdS_S_, .Lfunc_end0-_Z31__device_stub__kernelAddVectorsiPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 24(%rsp) # 8-byte Spill
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
callq clock
cvtsi2sd %rax, %xmm0
cvttsd2si %xmm0, %rdi
callq srand48
movq %rbx, %r12
movslq %ebx, %r13
leaq (,%r13,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, 64(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r15
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq drand48
movsd %xmm0, (%rbx,%rbp,8)
callq drand48
movsd %xmm0, (%r14,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_2
.LBB1_3: # %._crit_edge
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB1_6
# %bb.4: # %.lr.ph76.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph76
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%rcx,8), %xmm0
movsd %xmm0, (%r15,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_5
.LBB1_6: # %._crit_edge77
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
leal (%r12,%r12), %eax
movq %r12, 8(%rsp) # 8-byte Spill
movslq %eax, %r13
movq 64(%rsp), %r12 # 8-byte Reload
leaq (%r12,%r13,8), %rbp
shlq $3, %r13
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbp, %xmm0
punpckldq .LCPI1_1(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_2(%rip), %xmm0
movapd %xmm0, %xmm2
unpckhpd %xmm0, %xmm2 # xmm2 = xmm2[1],xmm0[1]
addsd %xmm0, %xmm2
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm1
movapd %xmm2, 176(%rsp) # 16-byte Spill
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r13, %xmm1
punpckldq .LCPI1_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_2(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 8(%rsp), %rax # 8-byte Reload
addl %ebp, %eax
decl %eax
cltd
idivl %ebp
movl %eax, %r13d
callq clock
movq %rax, 24(%rsp) # 8-byte Spill
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
movl %ebp, %edx
orq %rax, %rdx
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 8(%rsp), %rsi # 8-byte Reload
movl %esi, 60(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16kernelAddVectorsiPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
callq clock
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movapd %xmm1, %xmm0
movb $1, %al
callq printf
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
movapd 176(%rsp), %xmm0 # 16-byte Reload
divsd %xmm2, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r12, %xmm1
punpckldq .LCPI1_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_2(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernelAddVectorsiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kernelAddVectorsiPdS_S_,@object # @_Z16kernelAddVectorsiPdS_S_
.section .rodata,"a",@progbits
.globl _Z16kernelAddVectorsiPdS_S_
.p2align 3, 0x0
_Z16kernelAddVectorsiPdS_S_:
.quad _Z31__device_stub__kernelAddVectorsiPdS_S_
.size _Z16kernelAddVectorsiPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The host took %f seconds to add a and b \n"
.size .L.str, 42
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The efective bandwidth of the host was: %f GB/s\n"
.size .L.str.1, 49
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "It took %f seconds to copy the data to device. \n"
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The efective bandwidth of the copy was: %f GB/s\n"
.size .L.str.3, 49
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "The device took %f seconds to add a and b \n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The efective bandwidth of the device was: %f GB/s\n"
.size .L.str.5, 51
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The device was %f times faster\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "It took %f seconds to copy the data back to the host. \n"
.size .L.str.7, 56
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16kernelAddVectorsiPdS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kernelAddVectorsiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kernelAddVectorsiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16kernelAddVectorsiPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x001fca00078e0208 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x160], PT ; /* 0x0000580008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kernelAddVectorsiPdS_S_
.globl _Z16kernelAddVectorsiPdS_S_
.p2align 8
.type _Z16kernelAddVectorsiPdS_S_,@function
_Z16kernelAddVectorsiPdS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16kernelAddVectorsiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16kernelAddVectorsiPdS_S_, .Lfunc_end0-_Z16kernelAddVectorsiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16kernelAddVectorsiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16kernelAddVectorsiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c0a4_00000000-6_addVectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
.type _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_, @function
_Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16kernelAddVectorsiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_, .-_Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
.globl _Z16kernelAddVectorsiPdS_S_
.type _Z16kernelAddVectorsiPdS_S_, @function
_Z16kernelAddVectorsiPdS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16kernelAddVectorsiPdS_S_, .-_Z16kernelAddVectorsiPdS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "The host took %f seconds to add a and b \n"
.align 8
.LC3:
.string "The efective bandwidth of the host was: %f GB/s\n"
.align 8
.LC4:
.string "It took %f seconds to copy the data to device. \n"
.align 8
.LC5:
.string "The efective bandwidth of the copy was: %f GB/s\n"
.align 8
.LC6:
.string "The device took %f seconds to add a and b \n"
.align 8
.LC7:
.string "The efective bandwidth of the device was: %f GB/s\n"
.align 8
.LC8:
.string "The device was %f times faster\n"
.align 8
.LC9:
.string "It took %f seconds to copy the data back to the host. \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %rsi, 32(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
movl %eax, 44(%rsp)
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
cvttsd2siq %xmm0, %rdi
call srand48@PLT
movslq %ebx, %r14
salq $3, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movq %r14, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L12
leal -1(%rbx), %r13d
movl $0, %ebx
.L13:
call drand48@PLT
movsd %xmm0, 0(%rbp,%rbx,8)
call drand48@PLT
movsd %xmm0, (%r12,%rbx,8)
movq %rbx, %rax
addq $1, %rbx
cmpq %r13, %rax
jne .L13
call clock@PLT
pxor %xmm7, %xmm7
cvtsi2sdq %rax, %xmm7
movsd %xmm7, (%rsp)
movl $0, %eax
.L14:
movsd 0(%rbp,%rax,8), %xmm0
addsd (%r12,%rax,8), %xmm0
movsd %xmm0, (%r15,%rax,8)
movq %rax, %rdx
addq $1, %rax
cmpq %r13, %rdx
jne .L14
.L22:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd (%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rsp)
movl 8(%rsp), %eax
leal (%rax,%rax), %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq (%r14,%rbx), %r13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %r13, %r13
js .L15
pxor %xmm7, %xmm7
cvtsi2sdq %r13, %xmm7
movsd %xmm7, 16(%rsp)
.L16:
movsd (%rsp), %xmm1
mulsd .LC2(%rip), %xmm1
movsd 16(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
call clock@PLT
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
movsd %xmm3, 24(%rsp)
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 24(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %r13
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %rbx, %rbx
js .L17
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L18:
movq %r13, %xmm1
mulsd .LC2(%rip), %xmm1
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rax
movq 16(%rax), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq 8(%rsp), %rax
leal -1(%rbx,%rax), %eax
cltd
idivl %ebx
movl %eax, %r13d
call clock@PLT
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movsd %xmm4, 8(%rsp)
movl %ebx, 92(%rsp)
movl $1, 96(%rsp)
movl %r13d, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaDeviceSynchronize@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm1
mulsd .LC2(%rip), %xmm1
movsd 16(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
divsd 8(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
pxor %xmm6, %xmm6
cvtsi2sdq %rax, %xmm6
movsd %xmm6, (%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 72(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
subsd (%rsp), %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %r14, %r14
js .L20
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
.L21:
movq %rbx, %xmm1
mulsd .LC2(%rip), %xmm1
divsd %xmm1, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
shrq %r13
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
addsd %xmm0, %xmm0
movsd %xmm0, 16(%rsp)
jmp .L16
.L17:
shrq %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
addsd %xmm0, %xmm0
jmp .L18
.L28:
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movl 44(%rsp), %edi
call _Z41__device_stub__Z16kernelAddVectorsiPdS_S_iPdS_S_
jmp .L19
.L20:
shrq %r14
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
addsd %xmm0, %xmm0
jmp .L21
.L12:
call clock@PLT
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
movsd %xmm2, (%rsp)
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC10:
.string "_Z16kernelAddVectorsiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16kernelAddVectorsiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC2:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addVectors.hip"
.globl _Z31__device_stub__kernelAddVectorsiPdS_S_ # -- Begin function _Z31__device_stub__kernelAddVectorsiPdS_S_
.p2align 4, 0x90
.type _Z31__device_stub__kernelAddVectorsiPdS_S_,@function
_Z31__device_stub__kernelAddVectorsiPdS_S_: # @_Z31__device_stub__kernelAddVectorsiPdS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16kernelAddVectorsiPdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__kernelAddVectorsiPdS_S_, .Lfunc_end0-_Z31__device_stub__kernelAddVectorsiPdS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI1_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 24(%rsp) # 8-byte Spill
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
callq clock
cvtsi2sd %rax, %xmm0
cvttsd2si %xmm0, %rdi
callq srand48
movq %rbx, %r12
movslq %ebx, %r13
leaq (,%r13,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, 64(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r15
testl %r13d, %r13d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %r12d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq drand48
movsd %xmm0, (%rbx,%rbp,8)
callq drand48
movsd %xmm0, (%r14,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_2
.LBB1_3: # %._crit_edge
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB1_6
# %bb.4: # %.lr.ph76.preheader
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.lr.ph76
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%rcx,8), %xmm0
movsd %xmm0, (%r15,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_5
.LBB1_6: # %._crit_edge77
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
leal (%r12,%r12), %eax
movq %r12, 8(%rsp) # 8-byte Spill
movslq %eax, %r13
movq 64(%rsp), %r12 # 8-byte Reload
leaq (%r12,%r13,8), %rbp
shlq $3, %r13
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbp, %xmm0
punpckldq .LCPI1_1(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_2(%rip), %xmm0
movapd %xmm0, %xmm2
unpckhpd %xmm0, %xmm2 # xmm2 = xmm2[1],xmm0[1]
addsd %xmm0, %xmm2
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm1
movapd %xmm2, 176(%rsp) # 16-byte Spill
movapd %xmm2, %xmm0
divsd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r13, %xmm1
punpckldq .LCPI1_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_2(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rax # 8-byte Reload
movq 16(%rax), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 8(%rsp), %rax # 8-byte Reload
addl %ebp, %eax
decl %eax
cltd
idivl %ebp
movl %eax, %r13d
callq clock
movq %rax, 24(%rsp) # 8-byte Spill
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
movl %ebp, %edx
orq %rax, %rdx
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 8(%rsp), %rsi # 8-byte Reload
movl %esi, 60(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 60(%rsp), %rax
movq %rax, 144(%rsp)
leaq 136(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16kernelAddVectorsiPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
callq clock
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movl $.L.str.4, %edi
movapd %xmm1, %xmm0
movb $1, %al
callq printf
movsd 8(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movsd .LCPI1_3(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
movapd 176(%rsp), %xmm0 # 16-byte Reload
divsd %xmm2, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.6, %edi
movb $1, %al
callq printf
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd (%rsp), %xmm0 # 8-byte Folded Reload
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r12, %xmm1
punpckldq .LCPI1_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_2(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI1_3(%rip), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16kernelAddVectorsiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16kernelAddVectorsiPdS_S_,@object # @_Z16kernelAddVectorsiPdS_S_
.section .rodata,"a",@progbits
.globl _Z16kernelAddVectorsiPdS_S_
.p2align 3, 0x0
_Z16kernelAddVectorsiPdS_S_:
.quad _Z31__device_stub__kernelAddVectorsiPdS_S_
.size _Z16kernelAddVectorsiPdS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The host took %f seconds to add a and b \n"
.size .L.str, 42
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "The efective bandwidth of the host was: %f GB/s\n"
.size .L.str.1, 49
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "It took %f seconds to copy the data to device. \n"
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The efective bandwidth of the copy was: %f GB/s\n"
.size .L.str.3, 49
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "The device took %f seconds to add a and b \n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "The efective bandwidth of the device was: %f GB/s\n"
.size .L.str.5, 51
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "The device was %f times faster\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "It took %f seconds to copy the data back to the host. \n"
.size .L.str.7, 56
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16kernelAddVectorsiPdS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__kernelAddVectorsiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16kernelAddVectorsiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void update_core(double *f, double *g, double *c, int nx, int ny) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int i = tid / ny;
int j = tid % ny;
if (i > 0 && j > 0 && i < nx-1 && j < ny-1) {
f[tid] = c[tid] * (g[tid-ny] + g[tid+ny] + g[tid-1] + g[tid+1]
- 4*g[tid]) + 2*g[tid] - f[tid];
}
}
__global__ void update_src(double *f, double val, int idx0) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
f[idx0] += val;
}
} | code for sm_80
Function : _Z10update_srcPddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x002fca00078e0a00 */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ DADD R4, R4, c[0x0][0x168] ; /* 0x00005a0004047629 */
/* 0x004e0e0000000000 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11update_corePdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x17c] ; /* 0x00005f0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0030*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0040*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe4000fffe13f */
/*0080*/ UIADD3 UR5, -UR5, UR7, URZ ; /* 0x0000000705057290 */
/* 0x000fc4000fffe13f */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*00a0*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*00b0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*00c0*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fe40000000000 */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0120*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0140*/ IMAD R0, R7, R5, R0 ; /* 0x0000000507007224 */
/* 0x000fca00078e0200 */
/*0150*/ ISETP.GT.U32.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f44070 */
/*0160*/ @!P2 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x800000070000a210 */
/* 0x080fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06070 */
/*0190*/ LOP3.LUT R0, R4, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0004007a12 */
/* 0x000fe400078e3cff */
/*01a0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*01b0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*01d0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01e0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff03aa12 */
/* 0x000fca00078e33ff */
/*01f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0200*/ IMAD R0, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005007a24 */
/* 0x000fca00078e0204 */
/*0210*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*0220*/ ISETP.LT.OR P0, PT, R3, 0x1, !P0 ; /* 0x000000010300780c */
/* 0x000fc80004701670 */
/*0230*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fc80008706670 */
/*0240*/ ISETP.GE.OR P0, PT, R0, UR5, P0 ; /* 0x0000000500007c0c */
/* 0x000fda0008706670 */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0260*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0270*/ IADD3 R10, R4.reuse, c[0x0][0x17c], RZ ; /* 0x00005f00040a7a10 */
/* 0x040fe20007ffe0ff */
/*0280*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0290*/ IADD3 R8, R4, -c[0x0][0x17c], RZ ; /* 0x80005f0004087a10 */
/* 0x000fce0007ffe0ff */
/*02a0*/ IMAD.WIDE R10, R10, R5, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e0205 */
/*02b0*/ IMAD.WIDE R8, R8, R5.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe400078e0205 */
/*02c0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ IMAD.WIDE R14, R4.reuse, R5.reuse, c[0x0][0x168] ; /* 0x00005a00040e7625 */
/* 0x0c0fe400078e0205 */
/*02e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*02f0*/ LDG.E.64 R16, [R14.64+-0x8] ; /* 0xfffff8040e107981 */
/* 0x000ee8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R14.64+0x8] ; /* 0x000008040e127981 */
/* 0x000f22000c1e1b00 */
/*0310*/ IMAD.WIDE R6, R4, R5, c[0x0][0x170] ; /* 0x00005c0004067625 */
/* 0x000fc600078e0205 */
/*0320*/ LDG.E.64 R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000f68000c1e1b00 */
/*0330*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1b00 */
/*0340*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0350*/ LDG.E.64 R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000f62000c1e1b00 */
/*0360*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004ecc0000000008 */
/*0370*/ DADD R12, R12, R16 ; /* 0x000000000c0c7229 */
/* 0x008f0c0000000010 */
/*0380*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x010f4c0000000012 */
/*0390*/ DFMA R12, R2, -4, R12 ; /* 0xc0100000020c782b */
/* 0x020e0c000000000c */
/*03a0*/ DMUL R12, R12, R6 ; /* 0x000000060c0c7228 */
/* 0x001e0c0000000000 */
/*03b0*/ DFMA R12, R2, 2, R12 ; /* 0x40000000020c782b */
/* 0x001e0c000000000c */
/*03c0*/ DADD R12, R12, -R20 ; /* 0x000000000c0c7229 */
/* 0x001e0e0000000814 */
/*03d0*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x001fe2000c101b04 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ BRA 0x3f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void update_core(double *f, double *g, double *c, int nx, int ny) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int i = tid / ny;
int j = tid % ny;
if (i > 0 && j > 0 && i < nx-1 && j < ny-1) {
f[tid] = c[tid] * (g[tid-ny] + g[tid+ny] + g[tid-1] + g[tid+1]
- 4*g[tid]) + 2*g[tid] - f[tid];
}
}
__global__ void update_src(double *f, double val, int idx0) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
f[idx0] += val;
}
} | .file "tmpxft_0011fb9f_00000000-6_pycuda_wave_fd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii
.type _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii, @function
_Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11update_corePdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii, .-_Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii
.globl _Z11update_corePdS_S_ii
.type _Z11update_corePdS_S_ii, @function
_Z11update_corePdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11update_corePdS_S_ii, .-_Z11update_corePdS_S_ii
.globl _Z32__device_stub__Z10update_srcPddiPddi
.type _Z32__device_stub__Z10update_srcPddiPddi, @function
_Z32__device_stub__Z10update_srcPddiPddi:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10update_srcPddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z10update_srcPddiPddi, .-_Z32__device_stub__Z10update_srcPddiPddi
.globl _Z10update_srcPddi
.type _Z10update_srcPddi, @function
_Z10update_srcPddi:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10update_srcPddiPddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10update_srcPddi, .-_Z10update_srcPddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10update_srcPddi"
.LC1:
.string "_Z11update_corePdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10update_srcPddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11update_corePdS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void update_core(double *f, double *g, double *c, int nx, int ny) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int i = tid / ny;
int j = tid % ny;
if (i > 0 && j > 0 && i < nx-1 && j < ny-1) {
f[tid] = c[tid] * (g[tid-ny] + g[tid+ny] + g[tid-1] + g[tid+1]
- 4*g[tid]) + 2*g[tid] - f[tid];
}
}
__global__ void update_src(double *f, double val, int idx0) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
f[idx0] += val;
}
} | #include <hip/hip_runtime.h>
__global__ void update_core(double *f, double *g, double *c, int nx, int ny) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int i = tid / ny;
int j = tid % ny;
if (i > 0 && j > 0 && i < nx-1 && j < ny-1) {
f[tid] = c[tid] * (g[tid-ny] + g[tid+ny] + g[tid-1] + g[tid+1]
- 4*g[tid]) + 2*g[tid] - f[tid];
}
}
__global__ void update_src(double *f, double val, int idx0) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
f[idx0] += val;
}
} |
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