system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <climits>
#include <cuda_runtime.h>
__device__ void
vectorAdd1(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__device__ void
vectorAdd2(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__global__ void
scheduler(int* d_A1, int* d_B1, int* d_C1, int size1, int* d_A2, int* d_B2, int* d_C2, int size2, int* mapBlk, int* mapKernel, int gridDim_A, int blockDim_A, int gridDim_B, int blockDim_B ){
if(mapKernel[blockIdx.x] == 0)
vectorAdd1(d_A1, d_B1, d_C1, size1, mapBlk, blockDim_A);
else
vectorAdd2(d_A2, d_B2, d_C2, size2, mapBlk, blockDim_A);
}
int main(){
const int numElements = 1000000;
size_t size = numElements*sizeof(int);
int blocks = 2000;
int threads = 1000;
int* mapKernel = new int[blocks];
int* mapBlk = new int[blocks];
/*Będą wykonywały się na zmianę po jednym bloku*/
for(int blkA =0, blkB = 0, i = 0; i < blocks; i++)
{
mapKernel[i] = i%2;
if(mapKernel[i] == 0)
mapBlk[i] = blkA++;
else
mapBlk[i] = blkB++;
}
/*Alokowanie pamięci na wektory na hoście*/
int* h_A1 = (int*)malloc(size);
int* h_B1 = (int*)malloc(size);
int* h_C1 = (int*)malloc(size);
int* h_A2 = (int*)malloc(size);
int* h_B2 = (int*)malloc(size);
int* h_C2 = (int*)malloc(size);
/*Wylosowanie liczb do wektorów*/
srand( time(NULL));
for(int i = 0; i < numElements; i++){
h_A1[i] = (int)rand()%10000;
h_B1[i] = (int)rand()%10000;
h_A2[i] = (int)rand()%10000;
h_B2[i] = (int)rand()%10000;
}
int* d_A1 = NULL;
int* d_B1 = NULL;
int* d_C1 = NULL;
int* d_A2 = NULL;
int* d_B2 = NULL;
int* d_C2 = NULL;
cudaError_t err = cudaSuccess;
err = cudaMalloc((void**)&d_A1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_B1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_C1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_A2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_B2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_C2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Memcpy host to device*/
printf("Kopiowanie wektorów z hosta do urzadzenia...\n");
err = cudaMemcpy(d_A1, h_A1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B1, h_B1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A2, h_A2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B2, h_B2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Skopiowanie tablic mapujacych do urzadzenia*/
size_t mapSize = blocks*sizeof(int);
int* d_mapKernel = NULL;
int* d_mapBlk = NULL;
printf("Kopiowanie tablic mapujacych do urzadzenia...\n");
err = cudaMalloc((void**)&d_mapKernel,mapSize);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_mapBlk, mapSize);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_mapKernel, mapKernel, mapSize, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_mapBlk, mapBlk, mapSize, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Launching kernel!!!*/
scheduler<<<blocks,threads>>>(d_A1, d_B1, d_C1, size, d_A2, d_B2, d_C2, size, d_mapBlk, d_mapKernel, blocks, threads, blocks, threads );
/*Memcpy device to host*/
err = cudaMemcpy(h_C1, d_C1, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_C2, d_C2, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Checking the resultes*/
for(int i = 0; i < numElements; i++)
{
int w1,w2;
w1 = h_A1[i]+h_B1[i];
w2 = h_A2[i]+h_B2[i];
if( w1 != h_C1[i])
{
printf("nr %d Wynik 1 niepoprawny %d + %d != %d!!\n",i, h_A1[i], h_B1[i], h_C1[i] );
return 1;
}
if( w2 != h_C2[i])
{
printf("nr %d Wynik 2 niepoprawny %d + %d != %d!!\n",i,h_A2[i], h_B2[i], h_C2[i] );
return 1;
}
}
printf("Wynik poprawny!!\n");
return 0;
} | code for sm_80
Function : _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x1a8] ; /* 0x00006a0004027625 */
/* 0x001fcc00078e0009 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x1a0] ; /* 0x0000680004047625 */
/* 0x000fcc00078e0009 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*0080*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ee20000002100 */
/*0090*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fe20003f05270 */
/*00a0*/ IMAD R6, R4, c[0x0][0x1b4], R7 ; /* 0x00006d0004067a24 */
/* 0x008fd800078e0207 */
/*00b0*/ @!P0 BRA 0x160 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x198], PT ; /* 0x0000660006007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.WIDE R4, R6, R9, c[0x0][0x188] ; /* 0x0000620006047625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R2, R6.reuse, R9.reuse, c[0x0][0x180] ; /* 0x0000600006027625 */
/* 0x0c0fe400078e0209 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R6, R9, c[0x0][0x190] ; /* 0x0000640006067625 */
/* 0x000fe200078e0209 */
/*0130*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.WIDE R4, R6, R9, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0209 */
/*0190*/ IMAD.WIDE R2, R6.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0209 */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0209 */
/*01d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*01e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <climits>
#include <cuda_runtime.h>
__device__ void
vectorAdd1(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__device__ void
vectorAdd2(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__global__ void
scheduler(int* d_A1, int* d_B1, int* d_C1, int size1, int* d_A2, int* d_B2, int* d_C2, int size2, int* mapBlk, int* mapKernel, int gridDim_A, int blockDim_A, int gridDim_B, int blockDim_B ){
if(mapKernel[blockIdx.x] == 0)
vectorAdd1(d_A1, d_B1, d_C1, size1, mapBlk, blockDim_A);
else
vectorAdd2(d_A2, d_B2, d_C2, size2, mapBlk, blockDim_A);
}
int main(){
const int numElements = 1000000;
size_t size = numElements*sizeof(int);
int blocks = 2000;
int threads = 1000;
int* mapKernel = new int[blocks];
int* mapBlk = new int[blocks];
/*Będą wykonywały się na zmianę po jednym bloku*/
for(int blkA =0, blkB = 0, i = 0; i < blocks; i++)
{
mapKernel[i] = i%2;
if(mapKernel[i] == 0)
mapBlk[i] = blkA++;
else
mapBlk[i] = blkB++;
}
/*Alokowanie pamięci na wektory na hoście*/
int* h_A1 = (int*)malloc(size);
int* h_B1 = (int*)malloc(size);
int* h_C1 = (int*)malloc(size);
int* h_A2 = (int*)malloc(size);
int* h_B2 = (int*)malloc(size);
int* h_C2 = (int*)malloc(size);
/*Wylosowanie liczb do wektorów*/
srand( time(NULL));
for(int i = 0; i < numElements; i++){
h_A1[i] = (int)rand()%10000;
h_B1[i] = (int)rand()%10000;
h_A2[i] = (int)rand()%10000;
h_B2[i] = (int)rand()%10000;
}
int* d_A1 = NULL;
int* d_B1 = NULL;
int* d_C1 = NULL;
int* d_A2 = NULL;
int* d_B2 = NULL;
int* d_C2 = NULL;
cudaError_t err = cudaSuccess;
err = cudaMalloc((void**)&d_A1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_B1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_C1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_A2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_B2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_C2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Memcpy host to device*/
printf("Kopiowanie wektorów z hosta do urzadzenia...\n");
err = cudaMemcpy(d_A1, h_A1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B1, h_B1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A2, h_A2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B2, h_B2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Skopiowanie tablic mapujacych do urzadzenia*/
size_t mapSize = blocks*sizeof(int);
int* d_mapKernel = NULL;
int* d_mapBlk = NULL;
printf("Kopiowanie tablic mapujacych do urzadzenia...\n");
err = cudaMalloc((void**)&d_mapKernel,mapSize);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_mapBlk, mapSize);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_mapKernel, mapKernel, mapSize, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_mapBlk, mapBlk, mapSize, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Launching kernel!!!*/
scheduler<<<blocks,threads>>>(d_A1, d_B1, d_C1, size, d_A2, d_B2, d_C2, size, d_mapBlk, d_mapKernel, blocks, threads, blocks, threads );
/*Memcpy device to host*/
err = cudaMemcpy(h_C1, d_C1, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_C2, d_C2, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Checking the resultes*/
for(int i = 0; i < numElements; i++)
{
int w1,w2;
w1 = h_A1[i]+h_B1[i];
w2 = h_A2[i]+h_B2[i];
if( w1 != h_C1[i])
{
printf("nr %d Wynik 1 niepoprawny %d + %d != %d!!\n",i, h_A1[i], h_B1[i], h_C1[i] );
return 1;
}
if( w2 != h_C2[i])
{
printf("nr %d Wynik 2 niepoprawny %d + %d != %d!!\n",i,h_A2[i], h_B2[i], h_C2[i] );
return 1;
}
}
printf("Wynik poprawny!!\n");
return 0;
} | .file "tmpxft_001a5964_00000000-6_source.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10vectorAdd1PiS_S_iS_i
.type _Z10vectorAdd1PiS_S_iS_i, @function
_Z10vectorAdd1PiS_S_iS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10vectorAdd1PiS_S_iS_i, .-_Z10vectorAdd1PiS_S_iS_i
.globl _Z10vectorAdd2PiS_S_iS_i
.type _Z10vectorAdd2PiS_S_iS_i, @function
_Z10vectorAdd2PiS_S_iS_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z10vectorAdd2PiS_S_iS_i, .-_Z10vectorAdd2PiS_S_iS_i
.globl _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
.type _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii, @function
_Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii:
.LFB3696:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 52(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 320(%rsp), %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z9schedulerPiS_S_iS_S_S_iS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii, .-_Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
.globl _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.type _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, @function
_Z9schedulerPiS_S_iS_S_S_iS_S_iiii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, .-_Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n"
.align 8
.LC1:
.string "Kopiowanie wektor\303\263w z hosta do urzadzenia...\n"
.align 8
.LC2:
.string "Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n"
.align 8
.LC3:
.string "Kopiowanie tablic mapujacych do urzadzenia...\n"
.align 8
.LC4:
.string "Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n"
.align 8
.LC5:
.string "Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n"
.align 8
.LC6:
.string "Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n"
.align 8
.LC7:
.string "nr %d Wynik 1 niepoprawny %d + %d != %d!!\n"
.align 8
.LC8:
.string "nr %d Wynik 2 niepoprawny %d + %d != %d!!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "Wynik poprawny!!\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $8000, %edi
call _Znam@PLT
movq %rax, %r15
movl $8000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %eax
movl $0, %edi
movl $0, %esi
jmp .L18
.L16:
movl %edi, %ecx
leal 1(%rdi), %edi
.L17:
movl %edx, (%r15,%rax,4)
movq 8(%rsp), %rbx
movl %ecx, (%rbx,%rax,4)
addq $1, %rax
cmpq $2000, %rax
je .L46
.L18:
movl %eax, %ecx
shrl $31, %ecx
leal (%rcx,%rax), %edx
andl $1, %edx
subl %ecx, %edx
testb $1, %al
jne .L16
movl %esi, %ecx
leal 1(%rsi), %esi
jmp .L17
.L46:
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000000, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $4000000, %edi
call malloc@PLT
movq %rax, %r14
movl $4000000, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebx
.L19:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, (%r14,%rbx)
addq $4, %rbx
cmpq $4000000, %rbx
jne .L19
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L48
leaq 48(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L49
leaq 56(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L50
leaq 64(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L51
leaq 72(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L52
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L53
movl $1, %ecx
movl $4000000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L54
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L55
movl $1, %ecx
movl $4000000, %edx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L56
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L57
leaq 88(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
movl $1, %ecx
movl $8000, %edx
movq %r15, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L59
movl $1, %ecx
movl $8000, %edx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L60
movl $1000, 108(%rsp)
movl $1, 112(%rsp)
movl $2000, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L34:
movl $2, %ecx
movl $4000000, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L62
movl $2, %ecx
movl $4000000, %edx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
movl $0, %eax
.L36:
movl 0(%rbp,%rax,4), %esi
movl (%r12,%rax,4), %r8d
movl 0(%r13,%rax,4), %ecx
movl (%r14,%rax,4), %edx
leal (%rcx,%rdx), %r11d
movq 16(%rsp), %rbx
movl (%rbx,%rax,4), %r9d
leal (%rsi,%r8), %r10d
cmpl %r10d, %r9d
jne .L64
movq 24(%rsp), %rsi
movl (%rsi,%rax,4), %r9d
cmpl %r11d, %r9d
jne .L65
addq $1, %rax
cmpq $1000000, %rax
jne .L36
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L15
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
pushq $1000
.cfi_def_cfa_offset 200
pushq $2000
.cfi_def_cfa_offset 208
pushq $1000
.cfi_def_cfa_offset 216
pushq $2000
.cfi_def_cfa_offset 224
pushq 112(%rsp)
.cfi_def_cfa_offset 232
pushq 128(%rsp)
.cfi_def_cfa_offset 240
pushq $4000000
.cfi_def_cfa_offset 248
pushq 128(%rsp)
.cfi_def_cfa_offset 256
movq 128(%rsp), %r9
movq 120(%rsp), %r8
movl $4000000, %ecx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
addq $64, %rsp
.cfi_def_cfa_offset 192
jmp .L34
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %esi, %ecx
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L15:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L66
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl %edx, %r8d
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L15
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z9schedulerPiS_S_iS_S_S_iS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9schedulerPiS_S_iS_S_S_iS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <climits>
#include <cuda_runtime.h>
__device__ void
vectorAdd1(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__device__ void
vectorAdd2(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__global__ void
scheduler(int* d_A1, int* d_B1, int* d_C1, int size1, int* d_A2, int* d_B2, int* d_C2, int size2, int* mapBlk, int* mapKernel, int gridDim_A, int blockDim_A, int gridDim_B, int blockDim_B ){
if(mapKernel[blockIdx.x] == 0)
vectorAdd1(d_A1, d_B1, d_C1, size1, mapBlk, blockDim_A);
else
vectorAdd2(d_A2, d_B2, d_C2, size2, mapBlk, blockDim_A);
}
int main(){
const int numElements = 1000000;
size_t size = numElements*sizeof(int);
int blocks = 2000;
int threads = 1000;
int* mapKernel = new int[blocks];
int* mapBlk = new int[blocks];
/*Będą wykonywały się na zmianę po jednym bloku*/
for(int blkA =0, blkB = 0, i = 0; i < blocks; i++)
{
mapKernel[i] = i%2;
if(mapKernel[i] == 0)
mapBlk[i] = blkA++;
else
mapBlk[i] = blkB++;
}
/*Alokowanie pamięci na wektory na hoście*/
int* h_A1 = (int*)malloc(size);
int* h_B1 = (int*)malloc(size);
int* h_C1 = (int*)malloc(size);
int* h_A2 = (int*)malloc(size);
int* h_B2 = (int*)malloc(size);
int* h_C2 = (int*)malloc(size);
/*Wylosowanie liczb do wektorów*/
srand( time(NULL));
for(int i = 0; i < numElements; i++){
h_A1[i] = (int)rand()%10000;
h_B1[i] = (int)rand()%10000;
h_A2[i] = (int)rand()%10000;
h_B2[i] = (int)rand()%10000;
}
int* d_A1 = NULL;
int* d_B1 = NULL;
int* d_C1 = NULL;
int* d_A2 = NULL;
int* d_B2 = NULL;
int* d_C2 = NULL;
cudaError_t err = cudaSuccess;
err = cudaMalloc((void**)&d_A1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_B1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_C1, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_A2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_B2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_C2, size);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Memcpy host to device*/
printf("Kopiowanie wektorów z hosta do urzadzenia...\n");
err = cudaMemcpy(d_A1, h_A1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B1, h_B1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A2, h_A2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B2, h_B2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Skopiowanie tablic mapujacych do urzadzenia*/
size_t mapSize = blocks*sizeof(int);
int* d_mapKernel = NULL;
int* d_mapBlk = NULL;
printf("Kopiowanie tablic mapujacych do urzadzenia...\n");
err = cudaMalloc((void**)&d_mapKernel,mapSize);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void**)&d_mapBlk, mapSize);
if(err != cudaSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_mapKernel, mapKernel, mapSize, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_mapBlk, mapBlk, mapSize, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Launching kernel!!!*/
scheduler<<<blocks,threads>>>(d_A1, d_B1, d_C1, size, d_A2, d_B2, d_C2, size, d_mapBlk, d_mapKernel, blocks, threads, blocks, threads );
/*Memcpy device to host*/
err = cudaMemcpy(h_C1, d_C1, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_C2, d_C2, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Checking the resultes*/
for(int i = 0; i < numElements; i++)
{
int w1,w2;
w1 = h_A1[i]+h_B1[i];
w2 = h_A2[i]+h_B2[i];
if( w1 != h_C1[i])
{
printf("nr %d Wynik 1 niepoprawny %d + %d != %d!!\n",i, h_A1[i], h_B1[i], h_C1[i] );
return 1;
}
if( w2 != h_C2[i])
{
printf("nr %d Wynik 2 niepoprawny %d + %d != %d!!\n",i,h_A2[i], h_B2[i], h_C2[i] );
return 1;
}
}
printf("Wynik poprawny!!\n");
return 0;
} | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <climits>
#include <hip/hip_runtime.h>
__device__ void
vectorAdd1(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__device__ void
vectorAdd2(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__global__ void
scheduler(int* d_A1, int* d_B1, int* d_C1, int size1, int* d_A2, int* d_B2, int* d_C2, int size2, int* mapBlk, int* mapKernel, int gridDim_A, int blockDim_A, int gridDim_B, int blockDim_B ){
if(mapKernel[blockIdx.x] == 0)
vectorAdd1(d_A1, d_B1, d_C1, size1, mapBlk, blockDim_A);
else
vectorAdd2(d_A2, d_B2, d_C2, size2, mapBlk, blockDim_A);
}
int main(){
const int numElements = 1000000;
size_t size = numElements*sizeof(int);
int blocks = 2000;
int threads = 1000;
int* mapKernel = new int[blocks];
int* mapBlk = new int[blocks];
/*Będą wykonywały się na zmianę po jednym bloku*/
for(int blkA =0, blkB = 0, i = 0; i < blocks; i++)
{
mapKernel[i] = i%2;
if(mapKernel[i] == 0)
mapBlk[i] = blkA++;
else
mapBlk[i] = blkB++;
}
/*Alokowanie pamięci na wektory na hoście*/
int* h_A1 = (int*)malloc(size);
int* h_B1 = (int*)malloc(size);
int* h_C1 = (int*)malloc(size);
int* h_A2 = (int*)malloc(size);
int* h_B2 = (int*)malloc(size);
int* h_C2 = (int*)malloc(size);
/*Wylosowanie liczb do wektorów*/
srand( time(NULL));
for(int i = 0; i < numElements; i++){
h_A1[i] = (int)rand()%10000;
h_B1[i] = (int)rand()%10000;
h_A2[i] = (int)rand()%10000;
h_B2[i] = (int)rand()%10000;
}
int* d_A1 = NULL;
int* d_B1 = NULL;
int* d_C1 = NULL;
int* d_A2 = NULL;
int* d_B2 = NULL;
int* d_C2 = NULL;
hipError_t err = hipSuccess;
err = hipMalloc((void**)&d_A1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_B1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_C1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_A2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_B2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_C2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Memcpy host to device*/
printf("Kopiowanie wektorów z hosta do urzadzenia...\n");
err = hipMemcpy(d_A1, h_A1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B1, h_B1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A2, h_A2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B2, h_B2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Skopiowanie tablic mapujacych do urzadzenia*/
size_t mapSize = blocks*sizeof(int);
int* d_mapKernel = NULL;
int* d_mapBlk = NULL;
printf("Kopiowanie tablic mapujacych do urzadzenia...\n");
err = hipMalloc((void**)&d_mapKernel,mapSize);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_mapBlk, mapSize);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_mapKernel, mapKernel, mapSize, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_mapBlk, mapBlk, mapSize, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Launching kernel!!!*/
scheduler<<<blocks,threads>>>(d_A1, d_B1, d_C1, size, d_A2, d_B2, d_C2, size, d_mapBlk, d_mapKernel, blocks, threads, blocks, threads );
/*Memcpy device to host*/
err = hipMemcpy(h_C1, d_C1, size, hipMemcpyDeviceToHost);
if(err != hipSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_C2, d_C2, size, hipMemcpyDeviceToHost);
if(err != hipSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Checking the resultes*/
for(int i = 0; i < numElements; i++)
{
int w1,w2;
w1 = h_A1[i]+h_B1[i];
w2 = h_A2[i]+h_B2[i];
if( w1 != h_C1[i])
{
printf("nr %d Wynik 1 niepoprawny %d + %d != %d!!\n",i, h_A1[i], h_B1[i], h_C1[i] );
return 1;
}
if( w2 != h_C2[i])
{
printf("nr %d Wynik 2 niepoprawny %d + %d != %d!!\n",i,h_A2[i], h_B2[i], h_C2[i] );
return 1;
}
}
printf("Wynik poprawny!!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <climits>
#include <hip/hip_runtime.h>
__device__ void
vectorAdd1(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__device__ void
vectorAdd2(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__global__ void
scheduler(int* d_A1, int* d_B1, int* d_C1, int size1, int* d_A2, int* d_B2, int* d_C2, int size2, int* mapBlk, int* mapKernel, int gridDim_A, int blockDim_A, int gridDim_B, int blockDim_B ){
if(mapKernel[blockIdx.x] == 0)
vectorAdd1(d_A1, d_B1, d_C1, size1, mapBlk, blockDim_A);
else
vectorAdd2(d_A2, d_B2, d_C2, size2, mapBlk, blockDim_A);
}
int main(){
const int numElements = 1000000;
size_t size = numElements*sizeof(int);
int blocks = 2000;
int threads = 1000;
int* mapKernel = new int[blocks];
int* mapBlk = new int[blocks];
/*Będą wykonywały się na zmianę po jednym bloku*/
for(int blkA =0, blkB = 0, i = 0; i < blocks; i++)
{
mapKernel[i] = i%2;
if(mapKernel[i] == 0)
mapBlk[i] = blkA++;
else
mapBlk[i] = blkB++;
}
/*Alokowanie pamięci na wektory na hoście*/
int* h_A1 = (int*)malloc(size);
int* h_B1 = (int*)malloc(size);
int* h_C1 = (int*)malloc(size);
int* h_A2 = (int*)malloc(size);
int* h_B2 = (int*)malloc(size);
int* h_C2 = (int*)malloc(size);
/*Wylosowanie liczb do wektorów*/
srand( time(NULL));
for(int i = 0; i < numElements; i++){
h_A1[i] = (int)rand()%10000;
h_B1[i] = (int)rand()%10000;
h_A2[i] = (int)rand()%10000;
h_B2[i] = (int)rand()%10000;
}
int* d_A1 = NULL;
int* d_B1 = NULL;
int* d_C1 = NULL;
int* d_A2 = NULL;
int* d_B2 = NULL;
int* d_C2 = NULL;
hipError_t err = hipSuccess;
err = hipMalloc((void**)&d_A1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_B1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_C1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_A2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_B2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_C2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Memcpy host to device*/
printf("Kopiowanie wektorów z hosta do urzadzenia...\n");
err = hipMemcpy(d_A1, h_A1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B1, h_B1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A2, h_A2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B2, h_B2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Skopiowanie tablic mapujacych do urzadzenia*/
size_t mapSize = blocks*sizeof(int);
int* d_mapKernel = NULL;
int* d_mapBlk = NULL;
printf("Kopiowanie tablic mapujacych do urzadzenia...\n");
err = hipMalloc((void**)&d_mapKernel,mapSize);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_mapBlk, mapSize);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_mapKernel, mapKernel, mapSize, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_mapBlk, mapBlk, mapSize, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Launching kernel!!!*/
scheduler<<<blocks,threads>>>(d_A1, d_B1, d_C1, size, d_A2, d_B2, d_C2, size, d_mapBlk, d_mapKernel, blocks, threads, blocks, threads );
/*Memcpy device to host*/
err = hipMemcpy(h_C1, d_C1, size, hipMemcpyDeviceToHost);
if(err != hipSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_C2, d_C2, size, hipMemcpyDeviceToHost);
if(err != hipSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Checking the resultes*/
for(int i = 0; i < numElements; i++)
{
int w1,w2;
w1 = h_A1[i]+h_B1[i];
w2 = h_A2[i]+h_B2[i];
if( w1 != h_C1[i])
{
printf("nr %d Wynik 1 niepoprawny %d + %d != %d!!\n",i, h_A1[i], h_B1[i], h_C1[i] );
return 1;
}
if( w2 != h_C2[i])
{
printf("nr %d Wynik 2 niepoprawny %d + %d != %d!!\n",i,h_A2[i], h_B2[i], h_C2[i] );
return 1;
}
}
printf("Wynik poprawny!!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.globl _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.p2align 8
.type _Z9schedulerPiS_S_iS_S_S_iS_S_iiii,@function
_Z9schedulerPiS_S_iS_S_S_iS_S_iiii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x40
s_load_b32 s8, s[0:1], 0x54
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, s8, v[0:1]
s_cmp_lg_u32 s3, 0
s_cbranch_scc0 .LBB0_5
s_load_b32 s2, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_5:
.LBB0_6:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 96
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, .Lfunc_end0-_Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 96
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9schedulerPiS_S_iS_S_S_iS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <climits>
#include <hip/hip_runtime.h>
__device__ void
vectorAdd1(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__device__ void
vectorAdd2(int* d_A, int* d_B, int* d_C, int size, int* mapBlk, int blockDim){
int vId = threadIdx.x + mapBlk[blockIdx.x]*blockDim;
if(vId < size){
d_C[vId] = d_A[vId] + d_B[vId];
}
for(int i =0; i<100000;i++);
}
__global__ void
scheduler(int* d_A1, int* d_B1, int* d_C1, int size1, int* d_A2, int* d_B2, int* d_C2, int size2, int* mapBlk, int* mapKernel, int gridDim_A, int blockDim_A, int gridDim_B, int blockDim_B ){
if(mapKernel[blockIdx.x] == 0)
vectorAdd1(d_A1, d_B1, d_C1, size1, mapBlk, blockDim_A);
else
vectorAdd2(d_A2, d_B2, d_C2, size2, mapBlk, blockDim_A);
}
int main(){
const int numElements = 1000000;
size_t size = numElements*sizeof(int);
int blocks = 2000;
int threads = 1000;
int* mapKernel = new int[blocks];
int* mapBlk = new int[blocks];
/*Będą wykonywały się na zmianę po jednym bloku*/
for(int blkA =0, blkB = 0, i = 0; i < blocks; i++)
{
mapKernel[i] = i%2;
if(mapKernel[i] == 0)
mapBlk[i] = blkA++;
else
mapBlk[i] = blkB++;
}
/*Alokowanie pamięci na wektory na hoście*/
int* h_A1 = (int*)malloc(size);
int* h_B1 = (int*)malloc(size);
int* h_C1 = (int*)malloc(size);
int* h_A2 = (int*)malloc(size);
int* h_B2 = (int*)malloc(size);
int* h_C2 = (int*)malloc(size);
/*Wylosowanie liczb do wektorów*/
srand( time(NULL));
for(int i = 0; i < numElements; i++){
h_A1[i] = (int)rand()%10000;
h_B1[i] = (int)rand()%10000;
h_A2[i] = (int)rand()%10000;
h_B2[i] = (int)rand()%10000;
}
int* d_A1 = NULL;
int* d_B1 = NULL;
int* d_C1 = NULL;
int* d_A2 = NULL;
int* d_B2 = NULL;
int* d_C2 = NULL;
hipError_t err = hipSuccess;
err = hipMalloc((void**)&d_A1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_B1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_C1, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_A2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_B2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_C2, size);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Memcpy host to device*/
printf("Kopiowanie wektorów z hosta do urzadzenia...\n");
err = hipMemcpy(d_A1, h_A1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B1, h_B1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A2, h_A2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B2, h_B2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Skopiowanie tablic mapujacych do urzadzenia*/
size_t mapSize = blocks*sizeof(int);
int* d_mapKernel = NULL;
int* d_mapBlk = NULL;
printf("Kopiowanie tablic mapujacych do urzadzenia...\n");
err = hipMalloc((void**)&d_mapKernel,mapSize);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void**)&d_mapBlk, mapSize);
if(err != hipSuccess)
{
printf("Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_mapKernel, mapKernel, mapSize, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_mapBlk, mapBlk, mapSize, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Launching kernel!!!*/
scheduler<<<blocks,threads>>>(d_A1, d_B1, d_C1, size, d_A2, d_B2, d_C2, size, d_mapBlk, d_mapKernel, blocks, threads, blocks, threads );
/*Memcpy device to host*/
err = hipMemcpy(h_C1, d_C1, size, hipMemcpyDeviceToHost);
if(err != hipSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_C2, d_C2, size, hipMemcpyDeviceToHost);
if(err != hipSuccess){
printf("Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/*Checking the resultes*/
for(int i = 0; i < numElements; i++)
{
int w1,w2;
w1 = h_A1[i]+h_B1[i];
w2 = h_A2[i]+h_B2[i];
if( w1 != h_C1[i])
{
printf("nr %d Wynik 1 niepoprawny %d + %d != %d!!\n",i, h_A1[i], h_B1[i], h_C1[i] );
return 1;
}
if( w2 != h_C2[i])
{
printf("nr %d Wynik 2 niepoprawny %d + %d != %d!!\n",i,h_A2[i], h_B2[i], h_C2[i] );
return 1;
}
}
printf("Wynik poprawny!!\n");
return 0;
} | .text
.file "source.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii # -- Begin function _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.p2align 4, 0x90
.type _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii,@function
_Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii: # @_Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9schedulerPiS_S_iS_S_S_iS_S_iiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii, .Lfunc_end0-_Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r15
movl $8000, %edi # imm = 0x1F40
callq _Znam
xorl %r8d, %r8d
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r8d, %esi
andl $1, %esi
movl %esi, (%r15,%r8,4)
movl %edx, %edi
cmovel %ecx, %edi
addl %esi, %edx
xorl $1, %esi
addl %esi, %ecx
movl %edi, (%rax,%r8,4)
incq %r8
cmpq $2000, %r8 # imm = 0x7D0
jne .LBB1_1
# %bb.2:
movq %rax, 120(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbp
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r13
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%rbp,%r12,4)
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%r13,%r12,4)
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1000000, %r12 # imm = 0xF4240
jne .LBB1_3
# %bb.4:
movq %rbp, 8(%rsp) # 8-byte Spill
movq $0, 72(%rsp)
movq $0, 64(%rsp)
movq $0, 56(%rsp)
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
leaq 72(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.7:
leaq 64(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.8:
movq %r13, %r12
leaq 56(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.9:
leaq 48(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.10:
leaq 40(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.11:
leaq 32(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.12:
movl $.Lstr, %edi
callq puts@PLT
movq 72(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq 8(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 64(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.15:
movq 48(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.16:
movq 40(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.17:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl $.Lstr.1, %edi
callq puts@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.18:
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.19:
movq 24(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21:
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq 120(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23:
movabsq $4294968296, %rdx # imm = 0x1000003E8
leaq 1000(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_25
# %bb.24:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
movq 32(%rsp), %r8
movq 16(%rsp), %r9
movq 24(%rsp), %r10
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movl $4000000, 100(%rsp) # imm = 0x3D0900
movq %rsi, 208(%rsp)
movq %rdi, 200(%rsp)
movq %r8, 192(%rsp)
movl $4000000, 96(%rsp) # imm = 0x3D0900
movq %r9, 184(%rsp)
movq %r10, 176(%rsp)
movl $2000, 92(%rsp) # imm = 0x7D0
movl $1000, 88(%rsp) # imm = 0x3E8
movl $2000, 84(%rsp) # imm = 0x7D0
movl $1000, 80(%rsp) # imm = 0x3E8
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 100(%rsp), %rax
movq %rax, 264(%rsp)
leaq 208(%rsp), %rax
movq %rax, 272(%rsp)
leaq 200(%rsp), %rax
movq %rax, 280(%rsp)
leaq 192(%rsp), %rax
movq %rax, 288(%rsp)
leaq 96(%rsp), %rax
movq %rax, 296(%rsp)
leaq 184(%rsp), %rax
movq %rax, 304(%rsp)
leaq 176(%rsp), %rax
movq %rax, 312(%rsp)
leaq 92(%rsp), %rax
movq %rax, 320(%rsp)
leaq 88(%rsp), %rax
movq %rax, 328(%rsp)
leaq 84(%rsp), %rax
movq %rax, 336(%rsp)
leaq 80(%rsp), %rax
movq %rax, 344(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z9schedulerPiS_S_iS_S_S_iS_S_iiii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_25:
movq 56(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 112(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_26
# %bb.27:
movq 32(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 104(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_26
# %bb.28: # %.preheader.preheader
xorl %r15d, %r15d
xorl %r12d, %r12d
xorl %eax, %eax
movq 8(%rsp), %r9 # 8-byte Reload
.p2align 4, 0x90
.LBB1_30: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r9,%r15,4), %edx
movl (%r14,%r15,4), %ecx
leal (%rcx,%rdx), %esi
movq 112(%rsp), %rdi # 8-byte Reload
movl (%rdi,%r15,4), %r8d
cmpl %r8d, %esi
jne .LBB1_31
# %bb.32: # in Loop: Header=BB1_30 Depth=1
movl (%r13,%r15,4), %edx
movl (%rbx,%r15,4), %ecx
leal (%rcx,%rdx), %esi
movq 104(%rsp), %rdi # 8-byte Reload
movl (%rdi,%r15,4), %r8d
movb $1, %bpl
cmpl %r8d, %esi
je .LBB1_35
# %bb.33: # in Loop: Header=BB1_30 Depth=1
xorl %ebp, %ebp
movl $.L.str.8, %edi
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_31: # in Loop: Header=BB1_30 Depth=1
xorl %ebp, %ebp
movl $.L.str.7, %edi
.LBB1_34: # in Loop: Header=BB1_30 Depth=1
movl %r15d, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movq 8(%rsp), %r9 # 8-byte Reload
movl $1, %eax
.LBB1_35: # in Loop: Header=BB1_30 Depth=1
testb %bpl, %bpl
je .LBB1_36
# %bb.29: # in Loop: Header=BB1_30 Depth=1
cmpq $999999, %r15 # imm = 0xF423F
leaq 1(%r15), %rcx
setae %r12b
movq %rcx, %r15
cmpq $1000000, %rcx # imm = 0xF4240
jne .LBB1_30
.LBB1_36:
testb $1, %r12b
je .LBB1_38
# %bb.37:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %eax, %eax
.LBB1_38:
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 416
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
jmp .LBB1_6
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
jmp .LBB1_6
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
jmp .LBB1_6
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
jmp .LBB1_6
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
.LBB1_6:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9schedulerPiS_S_iS_S_S_iS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9schedulerPiS_S_iS_S_S_iS_S_iiii,@object # @_Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.section .rodata,"a",@progbits
.globl _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.p2align 3, 0x0
_Z9schedulerPiS_S_iS_S_S_iS_S_iiii:
.quad _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.size _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n"
.size .L.str, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n"
.size .L.str.2, 62
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n"
.size .L.str.4, 59
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n"
.size .L.str.6, 71
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "nr %d Wynik 1 niepoprawny %d + %d != %d!!\n"
.size .L.str.7, 43
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "nr %d Wynik 2 niepoprawny %d + %d != %d!!\n"
.size .L.str.8, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9schedulerPiS_S_iS_S_S_iS_S_iiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Kopiowanie wektor\303\263w z hosta do urzadzenia..."
.size .Lstr, 46
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Kopiowanie tablic mapujacych do urzadzenia..."
.size .Lstr.1, 46
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Wynik poprawny!!"
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x1a8] ; /* 0x00006a0004027625 */
/* 0x001fcc00078e0009 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x1a0] ; /* 0x0000680004047625 */
/* 0x000fcc00078e0009 */
/*0070*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*0080*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ee20000002100 */
/*0090*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fe20003f05270 */
/*00a0*/ IMAD R6, R4, c[0x0][0x1b4], R7 ; /* 0x00006d0004067a24 */
/* 0x008fd800078e0207 */
/*00b0*/ @!P0 BRA 0x160 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x198], PT ; /* 0x0000660006007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.WIDE R4, R6, R9, c[0x0][0x188] ; /* 0x0000620006047625 */
/* 0x000fc800078e0209 */
/*00f0*/ IMAD.WIDE R2, R6.reuse, R9.reuse, c[0x0][0x180] ; /* 0x0000600006027625 */
/* 0x0c0fe400078e0209 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.WIDE R6, R6, R9, c[0x0][0x190] ; /* 0x0000640006067625 */
/* 0x000fe200078e0209 */
/*0130*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.WIDE R4, R6, R9, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0209 */
/*0190*/ IMAD.WIDE R2, R6.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0209 */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0209 */
/*01d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*01e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.globl _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.p2align 8
.type _Z9schedulerPiS_S_iS_S_S_iS_S_iiii,@function
_Z9schedulerPiS_S_iS_S_S_iS_S_iiii:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x40
s_load_b32 s8, s[0:1], 0x54
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b32 s2, s[2:3], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, s8, v[0:1]
s_cmp_lg_u32 s3, 0
s_cbranch_scc0 .LBB0_5
s_load_b32 s2, s[0:1], 0x38
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x20
s_load_b64 s[8:9], s[0:1], 0x30
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_5:
.LBB0_6:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 96
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, .Lfunc_end0-_Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 84
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: by_value
- .offset: 92
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 96
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9schedulerPiS_S_iS_S_S_iS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a5964_00000000-6_source.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10vectorAdd1PiS_S_iS_i
.type _Z10vectorAdd1PiS_S_iS_i, @function
_Z10vectorAdd1PiS_S_iS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10vectorAdd1PiS_S_iS_i, .-_Z10vectorAdd1PiS_S_iS_i
.globl _Z10vectorAdd2PiS_S_iS_i
.type _Z10vectorAdd2PiS_S_iS_i, @function
_Z10vectorAdd2PiS_S_iS_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z10vectorAdd2PiS_S_iS_i, .-_Z10vectorAdd2PiS_S_iS_i
.globl _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
.type _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii, @function
_Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii:
.LFB3696:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 52(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 288(%rsp), %rax
movq %rax, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 312(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 52(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 296(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 320(%rsp), %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 296
pushq 88(%rsp)
.cfi_def_cfa_offset 304
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z9schedulerPiS_S_iS_S_S_iS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii, .-_Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
.globl _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.type _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, @function
_Z9schedulerPiS_S_iS_S_S_iS_S_iiii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 72(%rsp)
.cfi_def_cfa_offset 56
pushq 72(%rsp)
.cfi_def_cfa_offset 64
movl 72(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 72
pushq 72(%rsp)
.cfi_def_cfa_offset 80
call _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
addq $72, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, .-_Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n"
.align 8
.LC1:
.string "Kopiowanie wektor\303\263w z hosta do urzadzenia...\n"
.align 8
.LC2:
.string "Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n"
.align 8
.LC3:
.string "Kopiowanie tablic mapujacych do urzadzenia...\n"
.align 8
.LC4:
.string "Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n"
.align 8
.LC5:
.string "Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n"
.align 8
.LC6:
.string "Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n"
.align 8
.LC7:
.string "nr %d Wynik 1 niepoprawny %d + %d != %d!!\n"
.align 8
.LC8:
.string "nr %d Wynik 2 niepoprawny %d + %d != %d!!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "Wynik poprawny!!\n"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $8000, %edi
call _Znam@PLT
movq %rax, %r15
movl $8000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %eax
movl $0, %edi
movl $0, %esi
jmp .L18
.L16:
movl %edi, %ecx
leal 1(%rdi), %edi
.L17:
movl %edx, (%r15,%rax,4)
movq 8(%rsp), %rbx
movl %ecx, (%rbx,%rax,4)
addq $1, %rax
cmpq $2000, %rax
je .L46
.L18:
movl %eax, %ecx
shrl $31, %ecx
leal (%rcx,%rax), %edx
andl $1, %edx
subl %ecx, %edx
testb $1, %al
jne .L16
movl %esi, %ecx
leal 1(%rsi), %esi
jmp .L17
.L46:
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
movl $4000000, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $4000000, %edi
call malloc@PLT
movq %rax, %r14
movl $4000000, %edi
call malloc@PLT
movq %rax, 24(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %ebx
.L19:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
movl %eax, (%r14,%rbx)
addq $4, %rbx
cmpq $4000000, %rbx
jne .L19
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movq $0, 72(%rsp)
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L47
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L48
leaq 48(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L49
leaq 56(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L50
leaq 64(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L51
leaq 72(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L52
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L53
movl $1, %ecx
movl $4000000, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L54
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L55
movl $1, %ecx
movl $4000000, %edx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L56
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L57
leaq 88(%rsp), %rdi
movl $8000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L58
movl $1, %ecx
movl $8000, %edx
movq %r15, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L59
movl $1, %ecx
movl $8000, %edx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L60
movl $1000, 108(%rsp)
movl $1, 112(%rsp)
movl $2000, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L34:
movl $2, %ecx
movl $4000000, %edx
movq 48(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L62
movl $2, %ecx
movl $4000000, %edx
movq 72(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
movl $0, %eax
.L36:
movl 0(%rbp,%rax,4), %esi
movl (%r12,%rax,4), %r8d
movl 0(%r13,%rax,4), %ecx
movl (%r14,%rax,4), %edx
leal (%rcx,%rdx), %r11d
movq 16(%rsp), %rbx
movl (%rbx,%rax,4), %r9d
leal (%rsi,%r8), %r10d
cmpl %r10d, %r9d
jne .L64
movq 24(%rsp), %rsi
movl (%rsi,%rax,4), %r9d
cmpl %r11d, %r9d
jne .L65
addq $1, %rax
cmpq $1000000, %rax
jne .L36
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L15
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
pushq $1000
.cfi_def_cfa_offset 200
pushq $2000
.cfi_def_cfa_offset 208
pushq $1000
.cfi_def_cfa_offset 216
pushq $2000
.cfi_def_cfa_offset 224
pushq 112(%rsp)
.cfi_def_cfa_offset 232
pushq 128(%rsp)
.cfi_def_cfa_offset 240
pushq $4000000
.cfi_def_cfa_offset 248
pushq 128(%rsp)
.cfi_def_cfa_offset 256
movq 128(%rsp), %r9
movq 120(%rsp), %r8
movl $4000000, %ecx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z48__device_stub__Z9schedulerPiS_S_iS_S_S_iS_S_iiiiPiS_S_iS_S_S_iS_S_iiii
addq $64, %rsp
.cfi_def_cfa_offset 192
jmp .L34
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %esi, %ecx
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L15:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L66
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl %edx, %r8d
movl %eax, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L15
.L66:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z9schedulerPiS_S_iS_S_S_iS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9schedulerPiS_S_iS_S_S_iS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "source.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii # -- Begin function _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.p2align 4, 0x90
.type _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii,@function
_Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii: # @_Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9schedulerPiS_S_iS_S_S_iS_S_iiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii, .Lfunc_end0-_Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 416
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r15
movl $8000, %edi # imm = 0x1F40
callq _Znam
xorl %r8d, %r8d
xorl %ecx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r8d, %esi
andl $1, %esi
movl %esi, (%r15,%r8,4)
movl %edx, %edi
cmovel %ecx, %edi
addl %esi, %edx
xorl $1, %esi
addl %esi, %ecx
movl %edi, (%rax,%r8,4)
incq %r8
cmpq $2000, %r8 # imm = 0x7D0
jne .LBB1_1
# %bb.2:
movq %rax, 120(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbp
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r13
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, 104(%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%rbp,%r12,4)
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%r13,%r12,4)
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1000000, %r12 # imm = 0xF4240
jne .LBB1_3
# %bb.4:
movq %rbp, 8(%rsp) # 8-byte Spill
movq $0, 72(%rsp)
movq $0, 64(%rsp)
movq $0, 56(%rsp)
movq $0, 48(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
leaq 72(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.7:
leaq 64(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.8:
movq %r13, %r12
leaq 56(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.9:
leaq 48(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.10:
leaq 40(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.11:
leaq 32(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.12:
movl $.Lstr, %edi
callq puts@PLT
movq 72(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq 8(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 64(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.15:
movq 48(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.16:
movq 40(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.17:
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movl $.Lstr.1, %edi
callq puts@PLT
leaq 24(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.18:
leaq 16(%rsp), %rdi
movl $8000, %esi # imm = 0x1F40
callq hipMalloc
testl %eax, %eax
jne .LBB1_5
# %bb.19:
movq 24(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_20
# %bb.21:
movq 16(%rsp), %rdi
movl $8000, %edx # imm = 0x1F40
movq 120(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_22
# %bb.23:
movabsq $4294968296, %rdx # imm = 0x1000003E8
leaq 1000(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_25
# %bb.24:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
movq 32(%rsp), %r8
movq 16(%rsp), %r9
movq 24(%rsp), %r10
movq %rax, 232(%rsp)
movq %rcx, 224(%rsp)
movq %rdx, 216(%rsp)
movl $4000000, 100(%rsp) # imm = 0x3D0900
movq %rsi, 208(%rsp)
movq %rdi, 200(%rsp)
movq %r8, 192(%rsp)
movl $4000000, 96(%rsp) # imm = 0x3D0900
movq %r9, 184(%rsp)
movq %r10, 176(%rsp)
movl $2000, 92(%rsp) # imm = 0x7D0
movl $1000, 88(%rsp) # imm = 0x3E8
movl $2000, 84(%rsp) # imm = 0x7D0
movl $1000, 80(%rsp) # imm = 0x3E8
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 224(%rsp), %rax
movq %rax, 248(%rsp)
leaq 216(%rsp), %rax
movq %rax, 256(%rsp)
leaq 100(%rsp), %rax
movq %rax, 264(%rsp)
leaq 208(%rsp), %rax
movq %rax, 272(%rsp)
leaq 200(%rsp), %rax
movq %rax, 280(%rsp)
leaq 192(%rsp), %rax
movq %rax, 288(%rsp)
leaq 96(%rsp), %rax
movq %rax, 296(%rsp)
leaq 184(%rsp), %rax
movq %rax, 304(%rsp)
leaq 176(%rsp), %rax
movq %rax, 312(%rsp)
leaq 92(%rsp), %rax
movq %rax, 320(%rsp)
leaq 88(%rsp), %rax
movq %rax, 328(%rsp)
leaq 84(%rsp), %rax
movq %rax, 336(%rsp)
leaq 80(%rsp), %rax
movq %rax, 344(%rsp)
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
leaq 240(%rsp), %r9
movl $_Z9schedulerPiS_S_iS_S_S_iS_S_iiii, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_25:
movq 56(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 112(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_26
# %bb.27:
movq 32(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 104(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_26
# %bb.28: # %.preheader.preheader
xorl %r15d, %r15d
xorl %r12d, %r12d
xorl %eax, %eax
movq 8(%rsp), %r9 # 8-byte Reload
.p2align 4, 0x90
.LBB1_30: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r9,%r15,4), %edx
movl (%r14,%r15,4), %ecx
leal (%rcx,%rdx), %esi
movq 112(%rsp), %rdi # 8-byte Reload
movl (%rdi,%r15,4), %r8d
cmpl %r8d, %esi
jne .LBB1_31
# %bb.32: # in Loop: Header=BB1_30 Depth=1
movl (%r13,%r15,4), %edx
movl (%rbx,%r15,4), %ecx
leal (%rcx,%rdx), %esi
movq 104(%rsp), %rdi # 8-byte Reload
movl (%rdi,%r15,4), %r8d
movb $1, %bpl
cmpl %r8d, %esi
je .LBB1_35
# %bb.33: # in Loop: Header=BB1_30 Depth=1
xorl %ebp, %ebp
movl $.L.str.8, %edi
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_31: # in Loop: Header=BB1_30 Depth=1
xorl %ebp, %ebp
movl $.L.str.7, %edi
.LBB1_34: # in Loop: Header=BB1_30 Depth=1
movl %r15d, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
movq 8(%rsp), %r9 # 8-byte Reload
movl $1, %eax
.LBB1_35: # in Loop: Header=BB1_30 Depth=1
testb %bpl, %bpl
je .LBB1_36
# %bb.29: # in Loop: Header=BB1_30 Depth=1
cmpq $999999, %r15 # imm = 0xF423F
leaq 1(%r15), %rcx
setae %r12b
movq %rcx, %r15
cmpq $1000000, %rcx # imm = 0xF4240
jne .LBB1_30
.LBB1_36:
testb $1, %r12b
je .LBB1_38
# %bb.37:
movl $.Lstr.2, %edi
callq puts@PLT
xorl %eax, %eax
.LBB1_38:
addq $360, %rsp # imm = 0x168
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 416
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
jmp .LBB1_6
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
jmp .LBB1_6
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
jmp .LBB1_6
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
jmp .LBB1_6
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
.LBB1_6:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9schedulerPiS_S_iS_S_S_iS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9schedulerPiS_S_iS_S_S_iS_S_iiii,@object # @_Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.section .rodata,"a",@progbits
.globl _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.p2align 3, 0x0
_Z9schedulerPiS_S_iS_S_S_iS_S_iiii:
.quad _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.size _Z9schedulerPiS_S_iS_S_S_iS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Nie udalo sie zaalokowac pamieci na urzadzeniu ( kod bledu %s)!\n"
.size .L.str, 65
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Nie udalo sie skopiowac danych do urzadzenia( kod bledu %s)!\n"
.size .L.str.2, 62
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Nie udalo sie skopiowac map do urzadzenia( kod bledu %s)!\n"
.size .L.str.4, 59
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Nie udalo sie skopiowac map do urzadzenia ( kod bledu %s)!\n"
.size .L.str.5, 60
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Nie udalo sie skopiowac danych z urzadzenia do hosta ( kod bledu %s)!\n"
.size .L.str.6, 71
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "nr %d Wynik 1 niepoprawny %d + %d != %d!!\n"
.size .L.str.7, 43
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "nr %d Wynik 2 niepoprawny %d + %d != %d!!\n"
.size .L.str.8, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9schedulerPiS_S_iS_S_S_iS_S_iiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Kopiowanie wektor\303\263w z hosta do urzadzenia..."
.size .Lstr, 46
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Kopiowanie tablic mapujacych do urzadzenia..."
.size .Lstr.1, 46
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Wynik poprawny!!"
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__schedulerPiS_S_iS_S_S_iS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9schedulerPiS_S_iS_S_S_iS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Now we make the matrix much bigger
g++ -pg seq_matrix_big_mul.c -o seq_matrix_big_mul
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#define N_THREADS 32
int num_rows_A = 2000; int num_rows_B = 2000; int num_rows_C = 2000;
int num_cols_A = 2000; int num_cols_B = 600; int num_cols_C = 600;
//int num_rows_A = 64; int num_rows_B = 64; int num_rows_C = 64;
//int num_cols_A = 64; int num_cols_B = 64; int num_cols_C = 64;
// I'm forcing a malloc because I want to add the malloc time on the game
float *A = (float*) malloc(sizeof(float) * num_rows_A * num_cols_A);
float *B = (float*) malloc(sizeof(float) * num_rows_B * num_cols_B);
float *C = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
float *C_ref = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Same code for all 2d kernel
int i = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if (i > num_rows_A || k > num_cols_B) return;
float sum = 0;
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
C[i*num_cols_B+k]=sum;
}
void matrix_2d_mul_float(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
float sum = 0;
int num_rows_C = num_rows_A;
int num_cols_C = num_cols_B;
// Iterate on each row of A
#pragma omp parallel for schedule(dynamic,1) collapse(2)
for(int i=0; i<num_rows_A; i++) {
// Iterate on each collumn of B
for (int k=0; k<num_cols_B; k++) {
sum = 0;
// Do the "multiply add between" row of A and collumn of B
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
// C[i][k] == C[i*num_cols_C+k]
C[i*num_cols_C+k]=sum;
}
}
}
void fillRand(float *vec, int minValue, int maxValue, int sizeVec) {
srand(time(NULL));
for (int idx = 0; idx < sizeVec; idx++) {
vec[idx] = rand() % maxValue + minValue;
}
}
int main() {
// Get size in bytes for our vectors
int numBytesA = sizeof(float) * num_rows_A * num_cols_A;
int numBytesB = sizeof(float) * num_rows_B * num_cols_B;
printf("Size in bytes A: %d\n",numBytesA);
printf("Size in bytes B: %d\n",numBytesB);
// Fill arrays
fillRand(A, 1, 100, num_rows_A * num_cols_A);
fillRand(B, 1, 100, num_rows_B * num_cols_B);
memset(C, 0, (num_rows_C*num_cols_C)*sizeof(float));
// Allocate memory on GPU
float *device_A_mat; float *device_B_mat; float *device_C_mat;
cudaMalloc((char**)&device_A_mat,numBytesA);
cudaMalloc((char**)&device_B_mat,numBytesB);
cudaMalloc((char**)&device_C_mat,numBytesB);
// Calculate kernel grid and blocks
dim3 dimBlock(N_THREADS, N_THREADS);
dim3 dimGrid((num_cols_B + dimBlock.x - 1) / dimBlock.x, (num_rows_A + dimBlock.y - 1) / dimBlock.y);
// Call sequential function
//ProfilerStart("nameOfProfile.log");
for (int idxLoop=0; idxLoop < 10; idxLoop++) {
// Copy matrices A and B to GPU
cudaMemcpy(device_A_mat,A,numBytesA,cudaMemcpyHostToDevice);
cudaMemcpy(device_B_mat,B,numBytesB,cudaMemcpyHostToDevice);
// Launch the kernel
//matrix_2d_mul_float(A,B,C,num_rows_A,num_cols_A,num_cols_B);
matrix_2d_mul_float_gpu<<<dimGrid, dimBlock>>>(device_A_mat,device_B_mat,device_C_mat,num_rows_A,num_cols_A,num_cols_B);
cudaError_t err = cudaThreadSynchronize();
//printf("Run kernel: %s\n", cudaGetErrorString(err));
// Get the result from the GPU to the CPU
cudaMemcpy(C,device_C_mat,numBytesB,cudaMemcpyDeviceToHost);
printf("Matrix multiplication done %d\n",idxLoop);
}
// Calculate one iteration with the reference function
/*printf("Calculating reference\n");
matrix_2d_mul_float(A,B,C_ref,num_rows_A,num_cols_A,num_cols_B);
printf("Comparing with reference\n");
float sumDiff = 0;
for (int i = 0; i < (num_rows_C*num_cols_C); i++) {
float diff = C_ref[i] - C[i];
if (diff > 0.01f) {
printf("Values = %f -- %f\n",C_ref[i], C[i]);
sumDiff += diff;
}
}
printf("Difference = %f\n",sumDiff);*/
// Free memory
free(A);free(B);free(C);
// Release memories from GPU
cudaFree(device_A_mat);
cudaFree(device_B_mat);
cudaFree(device_C_mat);
return 0;
} | code for sm_80
Function : _Z23matrix_2d_mul_float_gpuPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x180], R0 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Now we make the matrix much bigger
g++ -pg seq_matrix_big_mul.c -o seq_matrix_big_mul
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#define N_THREADS 32
int num_rows_A = 2000; int num_rows_B = 2000; int num_rows_C = 2000;
int num_cols_A = 2000; int num_cols_B = 600; int num_cols_C = 600;
//int num_rows_A = 64; int num_rows_B = 64; int num_rows_C = 64;
//int num_cols_A = 64; int num_cols_B = 64; int num_cols_C = 64;
// I'm forcing a malloc because I want to add the malloc time on the game
float *A = (float*) malloc(sizeof(float) * num_rows_A * num_cols_A);
float *B = (float*) malloc(sizeof(float) * num_rows_B * num_cols_B);
float *C = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
float *C_ref = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Same code for all 2d kernel
int i = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if (i > num_rows_A || k > num_cols_B) return;
float sum = 0;
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
C[i*num_cols_B+k]=sum;
}
void matrix_2d_mul_float(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
float sum = 0;
int num_rows_C = num_rows_A;
int num_cols_C = num_cols_B;
// Iterate on each row of A
#pragma omp parallel for schedule(dynamic,1) collapse(2)
for(int i=0; i<num_rows_A; i++) {
// Iterate on each collumn of B
for (int k=0; k<num_cols_B; k++) {
sum = 0;
// Do the "multiply add between" row of A and collumn of B
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
// C[i][k] == C[i*num_cols_C+k]
C[i*num_cols_C+k]=sum;
}
}
}
void fillRand(float *vec, int minValue, int maxValue, int sizeVec) {
srand(time(NULL));
for (int idx = 0; idx < sizeVec; idx++) {
vec[idx] = rand() % maxValue + minValue;
}
}
int main() {
// Get size in bytes for our vectors
int numBytesA = sizeof(float) * num_rows_A * num_cols_A;
int numBytesB = sizeof(float) * num_rows_B * num_cols_B;
printf("Size in bytes A: %d\n",numBytesA);
printf("Size in bytes B: %d\n",numBytesB);
// Fill arrays
fillRand(A, 1, 100, num_rows_A * num_cols_A);
fillRand(B, 1, 100, num_rows_B * num_cols_B);
memset(C, 0, (num_rows_C*num_cols_C)*sizeof(float));
// Allocate memory on GPU
float *device_A_mat; float *device_B_mat; float *device_C_mat;
cudaMalloc((char**)&device_A_mat,numBytesA);
cudaMalloc((char**)&device_B_mat,numBytesB);
cudaMalloc((char**)&device_C_mat,numBytesB);
// Calculate kernel grid and blocks
dim3 dimBlock(N_THREADS, N_THREADS);
dim3 dimGrid((num_cols_B + dimBlock.x - 1) / dimBlock.x, (num_rows_A + dimBlock.y - 1) / dimBlock.y);
// Call sequential function
//ProfilerStart("nameOfProfile.log");
for (int idxLoop=0; idxLoop < 10; idxLoop++) {
// Copy matrices A and B to GPU
cudaMemcpy(device_A_mat,A,numBytesA,cudaMemcpyHostToDevice);
cudaMemcpy(device_B_mat,B,numBytesB,cudaMemcpyHostToDevice);
// Launch the kernel
//matrix_2d_mul_float(A,B,C,num_rows_A,num_cols_A,num_cols_B);
matrix_2d_mul_float_gpu<<<dimGrid, dimBlock>>>(device_A_mat,device_B_mat,device_C_mat,num_rows_A,num_cols_A,num_cols_B);
cudaError_t err = cudaThreadSynchronize();
//printf("Run kernel: %s\n", cudaGetErrorString(err));
// Get the result from the GPU to the CPU
cudaMemcpy(C,device_C_mat,numBytesB,cudaMemcpyDeviceToHost);
printf("Matrix multiplication done %d\n",idxLoop);
}
// Calculate one iteration with the reference function
/*printf("Calculating reference\n");
matrix_2d_mul_float(A,B,C_ref,num_rows_A,num_cols_A,num_cols_B);
printf("Comparing with reference\n");
float sumDiff = 0;
for (int i = 0; i < (num_rows_C*num_cols_C); i++) {
float diff = C_ref[i] - C[i];
if (diff > 0.01f) {
printf("Values = %f -- %f\n",C_ref[i], C[i]);
sumDiff += diff;
}
}
printf("Difference = %f\n",sumDiff);*/
// Free memory
free(A);free(B);free(C);
// Release memories from GPU
cudaFree(device_A_mat);
cudaFree(device_B_mat);
cudaFree(device_C_mat);
return 0;
} | .file "tmpxft_001a4810_00000000-6_matrix_big_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19matrix_2d_mul_floatPfS_S_iii
.type _Z19matrix_2d_mul_floatPfS_S_iii, @function
_Z19matrix_2d_mul_floatPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %ecx, -20(%rsp)
testl %ecx, %ecx
jle .L3
movq %rdi, %rbx
movl %r8d, %r10d
movl %r9d, %r14d
movslq %r9d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %r8d, %r15
movq %r15, %rcx
jmp .L5
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L6
.L8:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L13
.L9:
movq %r9, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r10d, %r10d
jg .L6
jmp .L8
.L13:
movl -24(%rsp), %edx
.L7:
addl $1, %edx
addl %r14d, %r12d
addl %r10d, %r13d
cmpl %edx, -20(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jle .L7
movq -16(%rsp), %r9
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rcx, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -8(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z19matrix_2d_mul_floatPfS_S_iii, .-_Z19matrix_2d_mul_floatPfS_S_iii
.globl _Z8fillRandPfiii
.type _Z8fillRandPfiii, @function
_Z8fillRandPfiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movl %esi, %r12d
movl %edx, %ebp
movl %ecx, %r13d
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %r13d, %r13d
jle .L16
movq %r14, %rbx
movslq %r13d, %r13
leaq (%r14,%r13,4), %r13
.L18:
call rand@PLT
cltd
idivl %ebp
addl %r12d, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L18
.L16:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8fillRandPfiii, .-_Z8fillRandPfiii
.globl _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.type _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, @function
_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, .-_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii, @function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Size in bytes A: %d\n"
.LC2:
.string "Size in bytes B: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Matrix multiplication done %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl num_cols_A(%rip), %r12d
imull num_rows_A(%rip), %r12d
sall $2, %r12d
movl num_cols_B(%rip), %ebp
imull num_rows_B(%rip), %ebp
sall $2, %ebp
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl num_rows_A(%rip), %ecx
imull num_cols_A(%rip), %ecx
movl $100, %edx
movl $1, %esi
movq A(%rip), %rdi
call _Z8fillRandPfiii
movl num_rows_B(%rip), %ecx
imull num_cols_B(%rip), %ecx
movl $100, %edx
movl $1, %esi
movq B(%rip), %rdi
call _Z8fillRandPfiii
movl num_rows_C(%rip), %edx
imull num_cols_C(%rip), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %esi
movq C(%rip), %rdi
call memset@PLT
movslq %r12d, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq %ebp, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, 40(%rsp)
movl num_rows_A(%rip), %eax
addl $31, %eax
shrl $5, %eax
movl num_cols_B(%rip), %ebx
leal 31(%rbx), %edx
shrl $5, %edx
movl %edx, 44(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %ebx
leaq .LC3(%rip), %r13
jmp .L31
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq C(%rip), %rdi
call cudaMemcpy@PLT
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
je .L35
.L31:
movl $1, %ecx
movq %r12, %rdx
movq A(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq B(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L30
movl num_cols_B(%rip), %r9d
movl num_cols_A(%rip), %r8d
movl num_rows_A(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
jmp .L30
.L35:
movq A(%rip), %rdi
call free@PLT
movq B(%rip), %rdi
call free@PLT
movq C(%rip), %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_num_rows_A, @function
_GLOBAL__sub_I_num_rows_A:
.LFB2205:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq num_rows_A(%rip), %rdi
movslq num_cols_A(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, A(%rip)
movslq num_rows_B(%rip), %rdi
movslq num_cols_B(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, B(%rip)
movslq num_rows_C(%rip), %rbx
movslq num_cols_C(%rip), %rax
imulq %rax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, C(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, C_ref(%rip)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2205:
.size _GLOBAL__sub_I_num_rows_A, .-_GLOBAL__sub_I_num_rows_A
.section .init_array
.align 8
.quad _GLOBAL__sub_I_num_rows_A
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl C_ref
.bss
.align 8
.type C_ref, @object
.size C_ref, 8
C_ref:
.zero 8
.globl C
.align 8
.type C, @object
.size C, 8
C:
.zero 8
.globl B
.align 8
.type B, @object
.size B, 8
B:
.zero 8
.globl A
.align 8
.type A, @object
.size A, 8
A:
.zero 8
.globl num_cols_C
.data
.align 4
.type num_cols_C, @object
.size num_cols_C, 4
num_cols_C:
.long 600
.globl num_cols_B
.align 4
.type num_cols_B, @object
.size num_cols_B, 4
num_cols_B:
.long 600
.globl num_cols_A
.align 4
.type num_cols_A, @object
.size num_cols_A, 4
num_cols_A:
.long 2000
.globl num_rows_C
.align 4
.type num_rows_C, @object
.size num_rows_C, 4
num_rows_C:
.long 2000
.globl num_rows_B
.align 4
.type num_rows_B, @object
.size num_rows_B, 4
num_rows_B:
.long 2000
.globl num_rows_A
.align 4
.type num_rows_A, @object
.size num_rows_A, 4
num_rows_A:
.long 2000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Now we make the matrix much bigger
g++ -pg seq_matrix_big_mul.c -o seq_matrix_big_mul
*/
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#define N_THREADS 32
int num_rows_A = 2000; int num_rows_B = 2000; int num_rows_C = 2000;
int num_cols_A = 2000; int num_cols_B = 600; int num_cols_C = 600;
//int num_rows_A = 64; int num_rows_B = 64; int num_rows_C = 64;
//int num_cols_A = 64; int num_cols_B = 64; int num_cols_C = 64;
// I'm forcing a malloc because I want to add the malloc time on the game
float *A = (float*) malloc(sizeof(float) * num_rows_A * num_cols_A);
float *B = (float*) malloc(sizeof(float) * num_rows_B * num_cols_B);
float *C = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
float *C_ref = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Same code for all 2d kernel
int i = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if (i > num_rows_A || k > num_cols_B) return;
float sum = 0;
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
C[i*num_cols_B+k]=sum;
}
void matrix_2d_mul_float(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
float sum = 0;
int num_rows_C = num_rows_A;
int num_cols_C = num_cols_B;
// Iterate on each row of A
#pragma omp parallel for schedule(dynamic,1) collapse(2)
for(int i=0; i<num_rows_A; i++) {
// Iterate on each collumn of B
for (int k=0; k<num_cols_B; k++) {
sum = 0;
// Do the "multiply add between" row of A and collumn of B
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
// C[i][k] == C[i*num_cols_C+k]
C[i*num_cols_C+k]=sum;
}
}
}
void fillRand(float *vec, int minValue, int maxValue, int sizeVec) {
srand(time(NULL));
for (int idx = 0; idx < sizeVec; idx++) {
vec[idx] = rand() % maxValue + minValue;
}
}
int main() {
// Get size in bytes for our vectors
int numBytesA = sizeof(float) * num_rows_A * num_cols_A;
int numBytesB = sizeof(float) * num_rows_B * num_cols_B;
printf("Size in bytes A: %d\n",numBytesA);
printf("Size in bytes B: %d\n",numBytesB);
// Fill arrays
fillRand(A, 1, 100, num_rows_A * num_cols_A);
fillRand(B, 1, 100, num_rows_B * num_cols_B);
memset(C, 0, (num_rows_C*num_cols_C)*sizeof(float));
// Allocate memory on GPU
float *device_A_mat; float *device_B_mat; float *device_C_mat;
cudaMalloc((char**)&device_A_mat,numBytesA);
cudaMalloc((char**)&device_B_mat,numBytesB);
cudaMalloc((char**)&device_C_mat,numBytesB);
// Calculate kernel grid and blocks
dim3 dimBlock(N_THREADS, N_THREADS);
dim3 dimGrid((num_cols_B + dimBlock.x - 1) / dimBlock.x, (num_rows_A + dimBlock.y - 1) / dimBlock.y);
// Call sequential function
//ProfilerStart("nameOfProfile.log");
for (int idxLoop=0; idxLoop < 10; idxLoop++) {
// Copy matrices A and B to GPU
cudaMemcpy(device_A_mat,A,numBytesA,cudaMemcpyHostToDevice);
cudaMemcpy(device_B_mat,B,numBytesB,cudaMemcpyHostToDevice);
// Launch the kernel
//matrix_2d_mul_float(A,B,C,num_rows_A,num_cols_A,num_cols_B);
matrix_2d_mul_float_gpu<<<dimGrid, dimBlock>>>(device_A_mat,device_B_mat,device_C_mat,num_rows_A,num_cols_A,num_cols_B);
cudaError_t err = cudaThreadSynchronize();
//printf("Run kernel: %s\n", cudaGetErrorString(err));
// Get the result from the GPU to the CPU
cudaMemcpy(C,device_C_mat,numBytesB,cudaMemcpyDeviceToHost);
printf("Matrix multiplication done %d\n",idxLoop);
}
// Calculate one iteration with the reference function
/*printf("Calculating reference\n");
matrix_2d_mul_float(A,B,C_ref,num_rows_A,num_cols_A,num_cols_B);
printf("Comparing with reference\n");
float sumDiff = 0;
for (int i = 0; i < (num_rows_C*num_cols_C); i++) {
float diff = C_ref[i] - C[i];
if (diff > 0.01f) {
printf("Values = %f -- %f\n",C_ref[i], C[i]);
sumDiff += diff;
}
}
printf("Difference = %f\n",sumDiff);*/
// Free memory
free(A);free(B);free(C);
// Release memories from GPU
cudaFree(device_A_mat);
cudaFree(device_B_mat);
cudaFree(device_C_mat);
return 0;
} | /*
Now we make the matrix much bigger
g++ -pg seq_matrix_big_mul.c -o seq_matrix_big_mul
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#define N_THREADS 32
int num_rows_A = 2000; int num_rows_B = 2000; int num_rows_C = 2000;
int num_cols_A = 2000; int num_cols_B = 600; int num_cols_C = 600;
//int num_rows_A = 64; int num_rows_B = 64; int num_rows_C = 64;
//int num_cols_A = 64; int num_cols_B = 64; int num_cols_C = 64;
// I'm forcing a malloc because I want to add the malloc time on the game
float *A = (float*) malloc(sizeof(float) * num_rows_A * num_cols_A);
float *B = (float*) malloc(sizeof(float) * num_rows_B * num_cols_B);
float *C = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
float *C_ref = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Same code for all 2d kernel
int i = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if (i > num_rows_A || k > num_cols_B) return;
float sum = 0;
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
C[i*num_cols_B+k]=sum;
}
void matrix_2d_mul_float(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
float sum = 0;
int num_rows_C = num_rows_A;
int num_cols_C = num_cols_B;
// Iterate on each row of A
#pragma omp parallel for schedule(dynamic,1) collapse(2)
for(int i=0; i<num_rows_A; i++) {
// Iterate on each collumn of B
for (int k=0; k<num_cols_B; k++) {
sum = 0;
// Do the "multiply add between" row of A and collumn of B
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
// C[i][k] == C[i*num_cols_C+k]
C[i*num_cols_C+k]=sum;
}
}
}
void fillRand(float *vec, int minValue, int maxValue, int sizeVec) {
srand(time(NULL));
for (int idx = 0; idx < sizeVec; idx++) {
vec[idx] = rand() % maxValue + minValue;
}
}
int main() {
// Get size in bytes for our vectors
int numBytesA = sizeof(float) * num_rows_A * num_cols_A;
int numBytesB = sizeof(float) * num_rows_B * num_cols_B;
printf("Size in bytes A: %d\n",numBytesA);
printf("Size in bytes B: %d\n",numBytesB);
// Fill arrays
fillRand(A, 1, 100, num_rows_A * num_cols_A);
fillRand(B, 1, 100, num_rows_B * num_cols_B);
memset(C, 0, (num_rows_C*num_cols_C)*sizeof(float));
// Allocate memory on GPU
float *device_A_mat; float *device_B_mat; float *device_C_mat;
hipMalloc((char**)&device_A_mat,numBytesA);
hipMalloc((char**)&device_B_mat,numBytesB);
hipMalloc((char**)&device_C_mat,numBytesB);
// Calculate kernel grid and blocks
dim3 dimBlock(N_THREADS, N_THREADS);
dim3 dimGrid((num_cols_B + dimBlock.x - 1) / dimBlock.x, (num_rows_A + dimBlock.y - 1) / dimBlock.y);
// Call sequential function
//ProfilerStart("nameOfProfile.log");
for (int idxLoop=0; idxLoop < 10; idxLoop++) {
// Copy matrices A and B to GPU
hipMemcpy(device_A_mat,A,numBytesA,hipMemcpyHostToDevice);
hipMemcpy(device_B_mat,B,numBytesB,hipMemcpyHostToDevice);
// Launch the kernel
//matrix_2d_mul_float(A,B,C,num_rows_A,num_cols_A,num_cols_B);
matrix_2d_mul_float_gpu<<<dimGrid, dimBlock>>>(device_A_mat,device_B_mat,device_C_mat,num_rows_A,num_cols_A,num_cols_B);
hipError_t err = hipDeviceSynchronize();
//printf("Run kernel: %s\n", cudaGetErrorString(err));
// Get the result from the GPU to the CPU
hipMemcpy(C,device_C_mat,numBytesB,hipMemcpyDeviceToHost);
printf("Matrix multiplication done %d\n",idxLoop);
}
// Calculate one iteration with the reference function
/*printf("Calculating reference\n");
matrix_2d_mul_float(A,B,C_ref,num_rows_A,num_cols_A,num_cols_B);
printf("Comparing with reference\n");
float sumDiff = 0;
for (int i = 0; i < (num_rows_C*num_cols_C); i++) {
float diff = C_ref[i] - C[i];
if (diff > 0.01f) {
printf("Values = %f -- %f\n",C_ref[i], C[i]);
sumDiff += diff;
}
}
printf("Difference = %f\n",sumDiff);*/
// Free memory
free(A);free(B);free(C);
// Release memories from GPU
hipFree(device_A_mat);
hipFree(device_B_mat);
hipFree(device_C_mat);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Now we make the matrix much bigger
g++ -pg seq_matrix_big_mul.c -o seq_matrix_big_mul
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#define N_THREADS 32
int num_rows_A = 2000; int num_rows_B = 2000; int num_rows_C = 2000;
int num_cols_A = 2000; int num_cols_B = 600; int num_cols_C = 600;
//int num_rows_A = 64; int num_rows_B = 64; int num_rows_C = 64;
//int num_cols_A = 64; int num_cols_B = 64; int num_cols_C = 64;
// I'm forcing a malloc because I want to add the malloc time on the game
float *A = (float*) malloc(sizeof(float) * num_rows_A * num_cols_A);
float *B = (float*) malloc(sizeof(float) * num_rows_B * num_cols_B);
float *C = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
float *C_ref = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Same code for all 2d kernel
int i = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if (i > num_rows_A || k > num_cols_B) return;
float sum = 0;
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
C[i*num_cols_B+k]=sum;
}
void matrix_2d_mul_float(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
float sum = 0;
int num_rows_C = num_rows_A;
int num_cols_C = num_cols_B;
// Iterate on each row of A
#pragma omp parallel for schedule(dynamic,1) collapse(2)
for(int i=0; i<num_rows_A; i++) {
// Iterate on each collumn of B
for (int k=0; k<num_cols_B; k++) {
sum = 0;
// Do the "multiply add between" row of A and collumn of B
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
// C[i][k] == C[i*num_cols_C+k]
C[i*num_cols_C+k]=sum;
}
}
}
void fillRand(float *vec, int minValue, int maxValue, int sizeVec) {
srand(time(NULL));
for (int idx = 0; idx < sizeVec; idx++) {
vec[idx] = rand() % maxValue + minValue;
}
}
int main() {
// Get size in bytes for our vectors
int numBytesA = sizeof(float) * num_rows_A * num_cols_A;
int numBytesB = sizeof(float) * num_rows_B * num_cols_B;
printf("Size in bytes A: %d\n",numBytesA);
printf("Size in bytes B: %d\n",numBytesB);
// Fill arrays
fillRand(A, 1, 100, num_rows_A * num_cols_A);
fillRand(B, 1, 100, num_rows_B * num_cols_B);
memset(C, 0, (num_rows_C*num_cols_C)*sizeof(float));
// Allocate memory on GPU
float *device_A_mat; float *device_B_mat; float *device_C_mat;
hipMalloc((char**)&device_A_mat,numBytesA);
hipMalloc((char**)&device_B_mat,numBytesB);
hipMalloc((char**)&device_C_mat,numBytesB);
// Calculate kernel grid and blocks
dim3 dimBlock(N_THREADS, N_THREADS);
dim3 dimGrid((num_cols_B + dimBlock.x - 1) / dimBlock.x, (num_rows_A + dimBlock.y - 1) / dimBlock.y);
// Call sequential function
//ProfilerStart("nameOfProfile.log");
for (int idxLoop=0; idxLoop < 10; idxLoop++) {
// Copy matrices A and B to GPU
hipMemcpy(device_A_mat,A,numBytesA,hipMemcpyHostToDevice);
hipMemcpy(device_B_mat,B,numBytesB,hipMemcpyHostToDevice);
// Launch the kernel
//matrix_2d_mul_float(A,B,C,num_rows_A,num_cols_A,num_cols_B);
matrix_2d_mul_float_gpu<<<dimGrid, dimBlock>>>(device_A_mat,device_B_mat,device_C_mat,num_rows_A,num_cols_A,num_cols_B);
hipError_t err = hipDeviceSynchronize();
//printf("Run kernel: %s\n", cudaGetErrorString(err));
// Get the result from the GPU to the CPU
hipMemcpy(C,device_C_mat,numBytesB,hipMemcpyDeviceToHost);
printf("Matrix multiplication done %d\n",idxLoop);
}
// Calculate one iteration with the reference function
/*printf("Calculating reference\n");
matrix_2d_mul_float(A,B,C_ref,num_rows_A,num_cols_A,num_cols_B);
printf("Comparing with reference\n");
float sumDiff = 0;
for (int i = 0; i < (num_rows_C*num_cols_C); i++) {
float diff = C_ref[i] - C[i];
if (diff > 0.01f) {
printf("Values = %f -- %f\n",C_ref[i], C[i]);
sumDiff += diff;
}
}
printf("Difference = %f\n",sumDiff);*/
// Free memory
free(A);free(B);free(C);
// Release memories from GPU
hipFree(device_A_mat);
hipFree(device_B_mat);
hipFree(device_C_mat);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23matrix_2d_mul_float_gpuPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 8
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_ge_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23matrix_2d_mul_float_gpuPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23matrix_2d_mul_float_gpuPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23matrix_2d_mul_float_gpuPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Now we make the matrix much bigger
g++ -pg seq_matrix_big_mul.c -o seq_matrix_big_mul
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <time.h>
#define N_THREADS 32
int num_rows_A = 2000; int num_rows_B = 2000; int num_rows_C = 2000;
int num_cols_A = 2000; int num_cols_B = 600; int num_cols_C = 600;
//int num_rows_A = 64; int num_rows_B = 64; int num_rows_C = 64;
//int num_cols_A = 64; int num_cols_B = 64; int num_cols_C = 64;
// I'm forcing a malloc because I want to add the malloc time on the game
float *A = (float*) malloc(sizeof(float) * num_rows_A * num_cols_A);
float *B = (float*) malloc(sizeof(float) * num_rows_B * num_cols_B);
float *C = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
float *C_ref = (float*) malloc(sizeof(float) * num_rows_C * num_cols_C);
__global__ void matrix_2d_mul_float_gpu(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
// Same code for all 2d kernel
int i = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if (i > num_rows_A || k > num_cols_B) return;
float sum = 0;
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
C[i*num_cols_B+k]=sum;
}
void matrix_2d_mul_float(float *A, float *B, float *C, int num_rows_A, int num_cols_A, int num_cols_B) {
float sum = 0;
int num_rows_C = num_rows_A;
int num_cols_C = num_cols_B;
// Iterate on each row of A
#pragma omp parallel for schedule(dynamic,1) collapse(2)
for(int i=0; i<num_rows_A; i++) {
// Iterate on each collumn of B
for (int k=0; k<num_cols_B; k++) {
sum = 0;
// Do the "multiply add between" row of A and collumn of B
for (int j=0; j<num_cols_A; j++){
// A[i][j] == A[i*num_cols_A+j]
// B[j][k] == B[j*num_cols_B+k]
//sum += A[i][j]*B[j][k];
sum += A[i*num_cols_A+j]*B[j*num_cols_B+k];
}
// C[i][k] == C[i*num_cols_C+k]
C[i*num_cols_C+k]=sum;
}
}
}
void fillRand(float *vec, int minValue, int maxValue, int sizeVec) {
srand(time(NULL));
for (int idx = 0; idx < sizeVec; idx++) {
vec[idx] = rand() % maxValue + minValue;
}
}
int main() {
// Get size in bytes for our vectors
int numBytesA = sizeof(float) * num_rows_A * num_cols_A;
int numBytesB = sizeof(float) * num_rows_B * num_cols_B;
printf("Size in bytes A: %d\n",numBytesA);
printf("Size in bytes B: %d\n",numBytesB);
// Fill arrays
fillRand(A, 1, 100, num_rows_A * num_cols_A);
fillRand(B, 1, 100, num_rows_B * num_cols_B);
memset(C, 0, (num_rows_C*num_cols_C)*sizeof(float));
// Allocate memory on GPU
float *device_A_mat; float *device_B_mat; float *device_C_mat;
hipMalloc((char**)&device_A_mat,numBytesA);
hipMalloc((char**)&device_B_mat,numBytesB);
hipMalloc((char**)&device_C_mat,numBytesB);
// Calculate kernel grid and blocks
dim3 dimBlock(N_THREADS, N_THREADS);
dim3 dimGrid((num_cols_B + dimBlock.x - 1) / dimBlock.x, (num_rows_A + dimBlock.y - 1) / dimBlock.y);
// Call sequential function
//ProfilerStart("nameOfProfile.log");
for (int idxLoop=0; idxLoop < 10; idxLoop++) {
// Copy matrices A and B to GPU
hipMemcpy(device_A_mat,A,numBytesA,hipMemcpyHostToDevice);
hipMemcpy(device_B_mat,B,numBytesB,hipMemcpyHostToDevice);
// Launch the kernel
//matrix_2d_mul_float(A,B,C,num_rows_A,num_cols_A,num_cols_B);
matrix_2d_mul_float_gpu<<<dimGrid, dimBlock>>>(device_A_mat,device_B_mat,device_C_mat,num_rows_A,num_cols_A,num_cols_B);
hipError_t err = hipDeviceSynchronize();
//printf("Run kernel: %s\n", cudaGetErrorString(err));
// Get the result from the GPU to the CPU
hipMemcpy(C,device_C_mat,numBytesB,hipMemcpyDeviceToHost);
printf("Matrix multiplication done %d\n",idxLoop);
}
// Calculate one iteration with the reference function
/*printf("Calculating reference\n");
matrix_2d_mul_float(A,B,C_ref,num_rows_A,num_cols_A,num_cols_B);
printf("Comparing with reference\n");
float sumDiff = 0;
for (int i = 0; i < (num_rows_C*num_cols_C); i++) {
float diff = C_ref[i] - C[i];
if (diff > 0.01f) {
printf("Values = %f -- %f\n",C_ref[i], C[i]);
sumDiff += diff;
}
}
printf("Difference = %f\n",sumDiff);*/
// Free memory
free(A);free(B);free(C);
// Release memories from GPU
hipFree(device_A_mat);
hipFree(device_B_mat);
hipFree(device_C_mat);
return 0;
} | .text
.file "matrix_big_mul.hip"
.globl _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii # -- Begin function _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.p2align 4, 0x90
.type _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii: # @_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z19matrix_2d_mul_floatPfS_S_iii # -- Begin function _Z19matrix_2d_mul_floatPfS_S_iii
.p2align 4, 0x90
.type _Z19matrix_2d_mul_floatPfS_S_iii,@function
_Z19matrix_2d_mul_floatPfS_S_iii: # @_Z19matrix_2d_mul_floatPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB1_9
# %bb.1: # %.preheader29.lr.ph
movslq %r9d, %rdi
movl %ecx, %ecx
movl %edi, %r10d
movl %r8d, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge33
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %r8d, %r14d
cmpq %rcx, %r15
je .LBB1_9
.LBB1_2: # %.preheader29
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %r9d, %r9d
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movss %xmm0, (%r13,%rax,4)
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB1_8
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
xorps %xmm0, %xmm0
testl %r8d, %r8d
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
movq %rsi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %rdx
addq %rbx, %rbp
cmpq %rdx, %r11
jne .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge35
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19matrix_2d_mul_floatPfS_S_iii, .Lfunc_end1-_Z19matrix_2d_mul_floatPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z8fillRandPfiii # -- Begin function _Z8fillRandPfiii
.p2align 4, 0x90
.type _Z8fillRandPfiii,@function
_Z8fillRandPfiii: # @_Z8fillRandPfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
addl %ebp, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8fillRandPfiii, .Lfunc_end2-_Z8fillRandPfiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl num_rows_A(%rip), %ebx
imull num_cols_A(%rip), %ebx
shll $2, %ebx
movl num_rows_B(%rip), %ebp
imull num_cols_B(%rip), %ebp
shll $2, %ebp
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq A(%rip), %r14
movl num_cols_A(%rip), %r15d
imull num_rows_A(%rip), %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB3_2
.LBB3_3: # %_Z8fillRandPfiii.exit
movq B(%rip), %r14
movl num_cols_B(%rip), %r15d
imull num_rows_B(%rip), %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader.i17
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i19
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB3_5
.LBB3_6: # %_Z8fillRandPfiii.exit23
movq C(%rip), %rdi
movslq num_rows_C(%rip), %rax
movslq num_cols_C(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq %ebp, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movl num_cols_B(%rip), %eax
addl $31, %eax
shrl $5, %eax
movl num_rows_A(%rip), %r15d
addl $31, %r15d
shrl $5, %r15d
shlq $32, %r15
orq %rax, %r15
movabsq $137438953504, %r12 # imm = 0x2000000020
leaq 112(%rsp), %r13
xorl %ebp, %ebp
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
callq hipDeviceSynchronize
movq C(%rip), %rdi
movq (%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl $10, %ebp
je .LBB3_10
.LBB3_7: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
movq A(%rip), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq B(%rip), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movl num_rows_A(%rip), %esi
movl num_cols_A(%rip), %edi
movl num_cols_B(%rip), %r8d
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 36(%rsp)
movl %edi, 32(%rsp)
movl %r8d, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %edi
movq %r13, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_9
.LBB3_10:
movq A(%rip), %rdi
callq free
movq B(%rip), %rdi
callq free
movq C(%rip), %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_matrix_big_mul.hip
.type _GLOBAL__sub_I_matrix_big_mul.hip,@function
_GLOBAL__sub_I_matrix_big_mul.hip: # @_GLOBAL__sub_I_matrix_big_mul.hip
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq num_rows_A(%rip), %rax
movslq num_cols_A(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, A(%rip)
movslq num_rows_B(%rip), %rax
movslq num_cols_B(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, B(%rip)
movslq num_rows_C(%rip), %rax
movslq num_cols_C(%rip), %rbx
imulq %rax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, C(%rip)
movq %rbx, %rdi
callq malloc
movq %rax, C_ref(%rip)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _GLOBAL__sub_I_matrix_big_mul.hip, .Lfunc_end4-_GLOBAL__sub_I_matrix_big_mul.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type num_rows_A,@object # @num_rows_A
.data
.globl num_rows_A
.p2align 2, 0x0
num_rows_A:
.long 2000 # 0x7d0
.size num_rows_A, 4
.type num_rows_B,@object # @num_rows_B
.globl num_rows_B
.p2align 2, 0x0
num_rows_B:
.long 2000 # 0x7d0
.size num_rows_B, 4
.type num_rows_C,@object # @num_rows_C
.globl num_rows_C
.p2align 2, 0x0
num_rows_C:
.long 2000 # 0x7d0
.size num_rows_C, 4
.type num_cols_A,@object # @num_cols_A
.globl num_cols_A
.p2align 2, 0x0
num_cols_A:
.long 2000 # 0x7d0
.size num_cols_A, 4
.type num_cols_B,@object # @num_cols_B
.globl num_cols_B
.p2align 2, 0x0
num_cols_B:
.long 600 # 0x258
.size num_cols_B, 4
.type num_cols_C,@object # @num_cols_C
.globl num_cols_C
.p2align 2, 0x0
num_cols_C:
.long 600 # 0x258
.size num_cols_C, 4
.type A,@object # @A
.bss
.globl A
.p2align 3, 0x0
A:
.quad 0
.size A, 8
.type B,@object # @B
.globl B
.p2align 3, 0x0
B:
.quad 0
.size B, 8
.type C,@object # @C
.globl C
.p2align 3, 0x0
C:
.quad 0
.size C, 8
.type C_ref,@object # @C_ref
.globl C_ref
.p2align 3, 0x0
C_ref:
.quad 0
.size C_ref, 8
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@object # @_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 3, 0x0
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.quad _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Size in bytes A: %d\n"
.size .L.str, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Size in bytes B: %d\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Matrix multiplication done %d\n"
.size .L.str.5, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_matrix_big_mul.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym _GLOBAL__sub_I_matrix_big_mul.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23matrix_2d_mul_float_gpuPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x17c], RZ ; /* 0x00005f0004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x180] ; /* 0x0000600000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x180], R0 ; /* 0x0000600002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x168] ; /* 0x00005a0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x180] ; /* 0x00006000000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23matrix_2d_mul_float_gpuPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 8
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_ge_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23matrix_2d_mul_float_gpuPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23matrix_2d_mul_float_gpuPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23matrix_2d_mul_float_gpuPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a4810_00000000-6_matrix_big_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19matrix_2d_mul_floatPfS_S_iii
.type _Z19matrix_2d_mul_floatPfS_S_iii, @function
_Z19matrix_2d_mul_floatPfS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -16(%rsp)
movq %rdx, -8(%rsp)
movl %ecx, -20(%rsp)
testl %ecx, %ecx
jle .L3
movq %rdi, %rbx
movl %r8d, %r10d
movl %r9d, %r14d
movslq %r9d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %r8d, %r15
movq %r15, %rcx
jmp .L5
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L6
.L8:
movss %xmm1, (%r11,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L13
.L9:
movq %r9, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r10d, %r10d
jg .L6
jmp .L8
.L13:
movl -24(%rsp), %edx
.L7:
addl $1, %edx
addl %r14d, %r12d
addl %r10d, %r13d
cmpl %edx, -20(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jle .L7
movq -16(%rsp), %r9
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rcx, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -8(%rsp), %r11
leaq (%r11,%rax,4), %r11
movl $0, %r8d
movl %edx, -24(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z19matrix_2d_mul_floatPfS_S_iii, .-_Z19matrix_2d_mul_floatPfS_S_iii
.globl _Z8fillRandPfiii
.type _Z8fillRandPfiii, @function
_Z8fillRandPfiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movl %esi, %r12d
movl %edx, %ebp
movl %ecx, %r13d
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %r13d, %r13d
jle .L16
movq %r14, %rbx
movslq %r13d, %r13
leaq (%r14,%r13,4), %r13
.L18:
call rand@PLT
cltd
idivl %ebp
addl %r12d, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L18
.L16:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8fillRandPfiii, .-_Z8fillRandPfiii
.globl _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.type _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, @function
_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii, .-_Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii, @function
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, .-_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Size in bytes A: %d\n"
.LC2:
.string "Size in bytes B: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Matrix multiplication done %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl num_cols_A(%rip), %r12d
imull num_rows_A(%rip), %r12d
sall $2, %r12d
movl num_cols_B(%rip), %ebp
imull num_rows_B(%rip), %ebp
sall $2, %ebp
movl %r12d, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl num_rows_A(%rip), %ecx
imull num_cols_A(%rip), %ecx
movl $100, %edx
movl $1, %esi
movq A(%rip), %rdi
call _Z8fillRandPfiii
movl num_rows_B(%rip), %ecx
imull num_cols_B(%rip), %ecx
movl $100, %edx
movl $1, %esi
movq B(%rip), %rdi
call _Z8fillRandPfiii
movl num_rows_C(%rip), %edx
imull num_cols_C(%rip), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %esi
movq C(%rip), %rdi
call memset@PLT
movslq %r12d, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq %ebp, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, 40(%rsp)
movl num_rows_A(%rip), %eax
addl $31, %eax
shrl $5, %eax
movl num_cols_B(%rip), %ebx
leal 31(%rbx), %edx
shrl $5, %edx
movl %edx, 44(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %ebx
leaq .LC3(%rip), %r13
jmp .L31
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq C(%rip), %rdi
call cudaMemcpy@PLT
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
je .L35
.L31:
movl $1, %ecx
movq %r12, %rdx
movq A(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq B(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L30
movl num_cols_B(%rip), %r9d
movl num_cols_A(%rip), %r8d
movl num_rows_A(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z23matrix_2d_mul_float_gpuPfS_S_iiiPfS_S_iii
jmp .L30
.L35:
movq A(%rip), %rdi
call free@PLT
movq B(%rip), %rdi
call free@PLT
movq C(%rip), %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z23matrix_2d_mul_float_gpuPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_num_rows_A, @function
_GLOBAL__sub_I_num_rows_A:
.LFB2205:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movslq num_rows_A(%rip), %rdi
movslq num_cols_A(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, A(%rip)
movslq num_rows_B(%rip), %rdi
movslq num_cols_B(%rip), %rax
imulq %rax, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, B(%rip)
movslq num_rows_C(%rip), %rbx
movslq num_cols_C(%rip), %rax
imulq %rax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, C(%rip)
movq %rbx, %rdi
call malloc@PLT
movq %rax, C_ref(%rip)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2205:
.size _GLOBAL__sub_I_num_rows_A, .-_GLOBAL__sub_I_num_rows_A
.section .init_array
.align 8
.quad _GLOBAL__sub_I_num_rows_A
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl C_ref
.bss
.align 8
.type C_ref, @object
.size C_ref, 8
C_ref:
.zero 8
.globl C
.align 8
.type C, @object
.size C, 8
C:
.zero 8
.globl B
.align 8
.type B, @object
.size B, 8
B:
.zero 8
.globl A
.align 8
.type A, @object
.size A, 8
A:
.zero 8
.globl num_cols_C
.data
.align 4
.type num_cols_C, @object
.size num_cols_C, 4
num_cols_C:
.long 600
.globl num_cols_B
.align 4
.type num_cols_B, @object
.size num_cols_B, 4
num_cols_B:
.long 600
.globl num_cols_A
.align 4
.type num_cols_A, @object
.size num_cols_A, 4
num_cols_A:
.long 2000
.globl num_rows_C
.align 4
.type num_rows_C, @object
.size num_rows_C, 4
num_rows_C:
.long 2000
.globl num_rows_B
.align 4
.type num_rows_B, @object
.size num_rows_B, 4
num_rows_B:
.long 2000
.globl num_rows_A
.align 4
.type num_rows_A, @object
.size num_rows_A, 4
num_rows_A:
.long 2000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_big_mul.hip"
.globl _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii # -- Begin function _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.p2align 4, 0x90
.type _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii,@function
_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii: # @_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii, .Lfunc_end0-_Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z19matrix_2d_mul_floatPfS_S_iii # -- Begin function _Z19matrix_2d_mul_floatPfS_S_iii
.p2align 4, 0x90
.type _Z19matrix_2d_mul_floatPfS_S_iii,@function
_Z19matrix_2d_mul_floatPfS_S_iii: # @_Z19matrix_2d_mul_floatPfS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB1_9
# %bb.1: # %.preheader29.lr.ph
movslq %r9d, %rdi
movl %ecx, %ecx
movl %edi, %r10d
movl %r8d, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge33
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %r8d, %r14d
cmpq %rcx, %r15
je .LBB1_9
.LBB1_2: # %.preheader29
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %r9d, %r9d
jle .LBB1_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movss %xmm0, (%r13,%rax,4)
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB1_8
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
xorps %xmm0, %xmm0
testl %r8d, %r8d
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
movq %rsi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
incq %rdx
addq %rbx, %rbp
cmpq %rdx, %r11
jne .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge35
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19matrix_2d_mul_floatPfS_S_iii, .Lfunc_end1-_Z19matrix_2d_mul_floatPfS_S_iii
.cfi_endproc
# -- End function
.globl _Z8fillRandPfiii # -- Begin function _Z8fillRandPfiii
.p2align 4, 0x90
.type _Z8fillRandPfiii,@function
_Z8fillRandPfiii: # @_Z8fillRandPfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
addl %ebp, %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8fillRandPfiii, .Lfunc_end2-_Z8fillRandPfiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl num_rows_A(%rip), %ebx
imull num_cols_A(%rip), %ebx
shll $2, %ebx
movl num_rows_B(%rip), %ebp
imull num_cols_B(%rip), %ebp
shll $2, %ebp
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq A(%rip), %r14
movl num_cols_A(%rip), %r15d
imull num_rows_A(%rip), %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB3_2
.LBB3_3: # %_Z8fillRandPfiii.exit
movq B(%rip), %r14
movl num_cols_B(%rip), %r15d
imull num_rows_B(%rip), %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader.i17
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i19
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB3_5
.LBB3_6: # %_Z8fillRandPfiii.exit23
movq C(%rip), %rdi
movslq num_rows_C(%rip), %rax
movslq num_cols_C(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
xorl %esi, %esi
callq memset@PLT
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq %ebp, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movl num_cols_B(%rip), %eax
addl $31, %eax
shrl $5, %eax
movl num_rows_A(%rip), %r15d
addl $31, %r15d
shrl $5, %r15d
shlq $32, %r15
orq %rax, %r15
movabsq $137438953504, %r12 # imm = 0x2000000020
leaq 112(%rsp), %r13
xorl %ebp, %ebp
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
callq hipDeviceSynchronize
movq C(%rip), %rdi
movq (%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl $10, %ebp
je .LBB3_10
.LBB3_7: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rdi
movq A(%rip), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq B(%rip), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movl num_rows_A(%rip), %esi
movl num_cols_A(%rip), %edi
movl num_cols_B(%rip), %r8d
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 36(%rsp)
movl %edi, 32(%rsp)
movl %r8d, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %edi
movq %r13, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_9
.LBB3_10:
movq A(%rip), %rdi
callq free
movq B(%rip), %rdi
callq free
movq C(%rip), %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_matrix_big_mul.hip
.type _GLOBAL__sub_I_matrix_big_mul.hip,@function
_GLOBAL__sub_I_matrix_big_mul.hip: # @_GLOBAL__sub_I_matrix_big_mul.hip
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movslq num_rows_A(%rip), %rax
movslq num_cols_A(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, A(%rip)
movslq num_rows_B(%rip), %rax
movslq num_cols_B(%rip), %rdi
imulq %rax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, B(%rip)
movslq num_rows_C(%rip), %rax
movslq num_cols_C(%rip), %rbx
imulq %rax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, C(%rip)
movq %rbx, %rdi
callq malloc
movq %rax, C_ref(%rip)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _GLOBAL__sub_I_matrix_big_mul.hip, .Lfunc_end4-_GLOBAL__sub_I_matrix_big_mul.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23matrix_2d_mul_float_gpuPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type num_rows_A,@object # @num_rows_A
.data
.globl num_rows_A
.p2align 2, 0x0
num_rows_A:
.long 2000 # 0x7d0
.size num_rows_A, 4
.type num_rows_B,@object # @num_rows_B
.globl num_rows_B
.p2align 2, 0x0
num_rows_B:
.long 2000 # 0x7d0
.size num_rows_B, 4
.type num_rows_C,@object # @num_rows_C
.globl num_rows_C
.p2align 2, 0x0
num_rows_C:
.long 2000 # 0x7d0
.size num_rows_C, 4
.type num_cols_A,@object # @num_cols_A
.globl num_cols_A
.p2align 2, 0x0
num_cols_A:
.long 2000 # 0x7d0
.size num_cols_A, 4
.type num_cols_B,@object # @num_cols_B
.globl num_cols_B
.p2align 2, 0x0
num_cols_B:
.long 600 # 0x258
.size num_cols_B, 4
.type num_cols_C,@object # @num_cols_C
.globl num_cols_C
.p2align 2, 0x0
num_cols_C:
.long 600 # 0x258
.size num_cols_C, 4
.type A,@object # @A
.bss
.globl A
.p2align 3, 0x0
A:
.quad 0
.size A, 8
.type B,@object # @B
.globl B
.p2align 3, 0x0
B:
.quad 0
.size B, 8
.type C,@object # @C
.globl C
.p2align 3, 0x0
C:
.quad 0
.size C, 8
.type C_ref,@object # @C_ref
.globl C_ref
.p2align 3, 0x0
C_ref:
.quad 0
.size C_ref, 8
.type _Z23matrix_2d_mul_float_gpuPfS_S_iii,@object # @_Z23matrix_2d_mul_float_gpuPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z23matrix_2d_mul_float_gpuPfS_S_iii
.p2align 3, 0x0
_Z23matrix_2d_mul_float_gpuPfS_S_iii:
.quad _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.size _Z23matrix_2d_mul_float_gpuPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Size in bytes A: %d\n"
.size .L.str, 21
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Size in bytes B: %d\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Matrix multiplication done %d\n"
.size .L.str.5, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z23matrix_2d_mul_float_gpuPfS_S_iii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_matrix_big_mul.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym _GLOBAL__sub_I_matrix_big_mul.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23matrix_2d_mul_float_gpuPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void histogram_kernel( float *I, float *minI, float *maxI, float *mask, int nbins, int c, int h, int w, float *hist )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
int id = _id % size, dc = _id / size;
if (mask[id] < EPS)
return ;
float val = I[_id];
float _minI = minI[dc];
float _maxI = maxI[dc];
if (_minI == _maxI) {
_minI -= 1;
_maxI += 1;
}
if (_minI <= val && val <= _maxI) {
int idx = MIN((val - _minI) / (_maxI - _minI) * nbins, nbins-1);
int index = dc * nbins + idx;
atomicAdd(&hist[index], 1.0f);
}
}
return ;
} | code for sm_80
Function : _Z16histogram_kernelPfS_S_S_iiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0205 */
/*0060*/ IMAD R5, R3, c[0x0][0x184], RZ ; /* 0x0000610003057a24 */
/* 0x000fca00078e02ff */
/*0070*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IABS R7, R3.reuse ; /* 0x0000000300077213 */
/* 0x080fe20000000000 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*00b0*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x000fe20000000000 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e220000209400 */
/*00e0*/ IABS R10, R3 ; /* 0x00000003000a7213 */
/* 0x000fce0000000000 */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*0140*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe400078e02ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0160*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fc800078e0004 */
/*0170*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0a */
/*0180*/ IMAD.HI.U32 R0, R5, R6, RZ ; /* 0x0000000605007227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD R4, R0, R9, R6 ; /* 0x0000000900047224 */
/* 0x000fca00078e0206 */
/*01a0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f44070 */
/*01b0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a07 */
/*01c0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*01f0*/ LOP3.LUT R4, R2, R3, RZ, 0x3c, !PT ; /* 0x0000000302047212 */
/* 0x000fc800078e3cff */
/*0200*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f26270 */
/*0210*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fcc0007ffe0ff */
/*0220*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*0230*/ @!P2 LOP3.LUT R0, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff00a212 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV R4, RZ, RZ, -R0 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a00 */
/*0250*/ IMAD R4, R3, R4, R2 ; /* 0x0000000403047224 */
/* 0x000fc800078e0202 */
/*0260*/ IMAD.WIDE R4, R4, R11, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fcc00078e020b */
/*0270*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0280*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x004e240000201800 */
/*0290*/ DSETP.GEU.AND P0, PT, R6, c[0x2][0x0], PT ; /* 0x008000000600762a */
/* 0x001e1c0003f0e000 */
/*02a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x001fea0003800000 */
/*02b0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e020b */
/*02c0*/ IMAD.WIDE R6, R0, R11.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x080fe200078e020b */
/*02d0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020b */
/*0300*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ee2000c1e1900 */
/*0310*/ FSETP.NEU.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x004fda0003f0d000 */
/*0320*/ @!P0 FADD R8, R8, 1 ; /* 0x3f80000008088421 */
/* 0x000fe40000000000 */
/*0330*/ @!P0 FADD R9, R9, -1 ; /* 0xbf80000009098421 */
/* 0x000fc60000000000 */
/*0340*/ FSETP.GTU.AND P0, PT, R2, R8, PT ; /* 0x000000080200720b */
/* 0x008fc80003f0c000 */
/*0350*/ FSETP.GTU.OR P0, PT, R9, R2, P0 ; /* 0x000000020900720b */
/* 0x000fda000070c400 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ FADD R6, -R9.reuse, R8 ; /* 0x0000000809067221 */
/* 0x040fe20000000100 */
/*0380*/ BSSY B0, 0x460 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0390*/ FADD R5, -R9, R2 ; /* 0x0000000209057221 */
/* 0x000fe40000000100 */
/*03a0*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x000e300000001000 */
/*03b0*/ FCHK P0, R5, R6 ; /* 0x0000000605007302 */
/* 0x000e620000000000 */
/*03c0*/ FFMA R4, -R6, R3, 1 ; /* 0x3f80000006047423 */
/* 0x001fc80000000103 */
/*03d0*/ FFMA R4, R3, R4, R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000003 */
/*03e0*/ FFMA R3, R5, R4, RZ ; /* 0x0000000405037223 */
/* 0x000fc800000000ff */
/*03f0*/ FFMA R2, -R6, R3, R5 ; /* 0x0000000306027223 */
/* 0x000fc80000000105 */
/*0400*/ FFMA R2, R4, R2, R3 ; /* 0x0000000204027223 */
/* 0x000fe20000000003 */
/*0410*/ @!P0 BRA 0x450 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0420*/ MOV R2, 0x440 ; /* 0x0000044000027802 */
/* 0x000fe40000000f00 */
/*0430*/ CALL.REL.NOINC 0x540 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0440*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0470*/ I2F R3, c[0x0][0x180] ; /* 0x0000600000037b06 */
/* 0x000e220000201400 */
/*0480*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fd000078e00ff */
/*04a0*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x000e620008201400 */
/*04b0*/ FMUL R2, R3, R2 ; /* 0x0000000203027220 */
/* 0x001fe40000400000 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*04d0*/ FSETP.GEU.AND P0, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x002fc80003f0e000 */
/*04e0*/ FSEL R5, R2, R5, !P0 ; /* 0x0000000502057208 */
/* 0x000fcc0004000000 */
/*04f0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000020f100 */
/*0500*/ IMAD R2, R0, c[0x0][0x180], R5 ; /* 0x0000600000027a24 */
/* 0x001fc800078e0205 */
/*0510*/ IMAD.WIDE R2, R2, R3, c[0x0][0x190] ; /* 0x0000640002027625 */
/* 0x000fca00078e0203 */
/*0520*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e786 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ SHF.R.U32.HI R4, RZ, 0x17, R6 ; /* 0x00000017ff047819 */
/* 0x000fe20000011606 */
/*0550*/ BSSY B1, 0xba0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0560*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fe40000011605 */
/*0570*/ LOP3.LUT R11, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040b7812 */
/* 0x000fe400078ec0ff */
/*0580*/ LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03097812 */
/* 0x000fe400078ec0ff */
/*0590*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R8, R9, -0x1, RZ ; /* 0xffffffff09087810 */
/* 0x000fc40007ffe0ff */
/*05b0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*05c0*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*05d0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*05e0*/ @!P0 BRA 0x780 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe20003f1c200 */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*0610*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe20003f3c200 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0006 */
/*0630*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0640*/ @P0 BRA 0xb80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0650*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0660*/ @!P0 BRA 0xb60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0670*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0680*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0690*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*06a0*/ @!P1 BRA !P2, 0xb60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06b0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*06c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*06d0*/ @P1 BRA 0xb40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*06e0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*06f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0700*/ @P0 BRA 0xb10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0720*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0730*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0740*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0750*/ @!P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003058823 */
/* 0x000fe400000000ff */
/*0760*/ @!P1 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004069823 */
/* 0x000fe200000000ff */
/*0770*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0780*/ LEA R3, R11, 0xc0800000, 0x17 ; /* 0xc08000000b037811 */
/* 0x000fe200078eb8ff */
/*0790*/ BSSY B2, 0xb00 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07a0*/ IADD3 R4, R9, -0x7f, RZ ; /* 0xffffff8109047810 */
/* 0x000fc60007ffe0ff */
/*07b0*/ IMAD.IADD R6, R6, 0x1, -R3 ; /* 0x0000000106067824 */
/* 0x000fe400078e0a03 */
/*07c0*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fe400078e0205 */
/*07d0*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x0000620000001000 */
/*07e0*/ FADD.FTZ R8, -R6, -RZ ; /* 0x800000ff06087221 */
/* 0x000fe20000010100 */
/*07f0*/ IADD3 R6, R4, 0x7f, -R11 ; /* 0x0000007f04067810 */
/* 0x001fca0007ffe80b */
/*0800*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*0810*/ FFMA R10, R3, R8, 1 ; /* 0x3f800000030a7423 */
/* 0x002fc80000000008 */
/*0820*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0830*/ FFMA R3, R5, R12, RZ ; /* 0x0000000c05037223 */
/* 0x000fc800000000ff */
/*0840*/ FFMA R10, R8, R3, R5 ; /* 0x00000003080a7223 */
/* 0x000fc80000000005 */
/*0850*/ FFMA R9, R12, R10, R3 ; /* 0x0000000a0c097223 */
/* 0x000fc80000000003 */
/*0860*/ FFMA R5, R8, R9, R5 ; /* 0x0000000908057223 */
/* 0x000fc80000000005 */
/*0870*/ FFMA R3, R12, R5, R9 ; /* 0x000000050c037223 */
/* 0x000fca0000000009 */
/*0880*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0890*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*08a0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*08b0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*08c0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*08d0*/ @!P0 BRA 0xae0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*08f0*/ @P0 BRA 0xab0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0900*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0910*/ @P0 BRA 0xaf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0930*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0940*/ @!P0 BRA 0xaf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0950*/ FFMA.RZ R4, R12, R5.reuse, R9.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000c009 */
/*0960*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe40007ffe0ff */
/*0970*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0980*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0990*/ FFMA.RP R4, R12, R5.reuse, R9.reuse ; /* 0x000000050c047223 */
/* 0x180fe20000008009 */
/*09a0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*09b0*/ FFMA.RM R5, R12, R5, R9 ; /* 0x000000050c057223 */
/* 0x000fe20000004009 */
/*09c0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe200078efcff */
/*09d0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*09e0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*09f0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*0a00*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0a10*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0a20*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0a30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0a40*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fe40000011605 */
/*0a50*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a60*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0a70*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0a80*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0a90*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0aa0*/ BRA 0xaf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0ac0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xaf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0af0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b10*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4805 */
/*0b20*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b30*/ BRA 0xb90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4805 */
/*0b50*/ BRA 0xb90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b60*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0b70*/ BRA 0xb90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b80*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0b90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0bb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0bc0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff43002007950 */
/* 0x000fea0003c3ffff */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void histogram_kernel( float *I, float *minI, float *maxI, float *mask, int nbins, int c, int h, int w, float *hist )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
int id = _id % size, dc = _id / size;
if (mask[id] < EPS)
return ;
float val = I[_id];
float _minI = minI[dc];
float _maxI = maxI[dc];
if (_minI == _maxI) {
_minI -= 1;
_maxI += 1;
}
if (_minI <= val && val <= _maxI) {
int idx = MIN((val - _minI) / (_maxI - _minI) * nbins, nbins-1);
int index = dc * nbins + idx;
atomicAdd(&hist[index], 1.0f);
}
}
return ;
} | .file "tmpxft_00146f09_00000000-6_histogram_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_
.type _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_, @function
_Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16histogram_kernelPfS_S_S_iiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_, .-_Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_
.globl _Z16histogram_kernelPfS_S_S_iiiiS_
.type _Z16histogram_kernelPfS_S_S_iiiiS_, @function
_Z16histogram_kernelPfS_S_S_iiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16histogram_kernelPfS_S_S_iiiiS_, .-_Z16histogram_kernelPfS_S_S_iiiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16histogram_kernelPfS_S_S_iiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16histogram_kernelPfS_S_S_iiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void histogram_kernel( float *I, float *minI, float *maxI, float *mask, int nbins, int c, int h, int w, float *hist )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
int id = _id % size, dc = _id / size;
if (mask[id] < EPS)
return ;
float val = I[_id];
float _minI = minI[dc];
float _maxI = maxI[dc];
if (_minI == _maxI) {
_minI -= 1;
_maxI += 1;
}
if (_minI <= val && val <= _maxI) {
int idx = MIN((val - _minI) / (_maxI - _minI) * nbins, nbins-1);
int index = dc * nbins + idx;
atomicAdd(&hist[index], 1.0f);
}
}
return ;
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void histogram_kernel( float *I, float *minI, float *maxI, float *mask, int nbins, int c, int h, int w, float *hist )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
int id = _id % size, dc = _id / size;
if (mask[id] < EPS)
return ;
float val = I[_id];
float _minI = minI[dc];
float _maxI = maxI[dc];
if (_minI == _maxI) {
_minI -= 1;
_maxI += 1;
}
if (_minI <= val && val <= _maxI) {
int idx = MIN((val - _minI) / (_maxI - _minI) * nbins, nbins-1);
int index = dc * nbins + idx;
atomicAdd(&hist[index], 1.0f);
}
}
return ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void histogram_kernel( float *I, float *minI, float *maxI, float *mask, int nbins, int c, int h, int w, float *hist )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
int id = _id % size, dc = _id / size;
if (mask[id] < EPS)
return ;
float val = I[_id];
float _minI = minI[dc];
float _maxI = maxI[dc];
if (_minI == _maxI) {
_minI -= 1;
_maxI += 1;
}
if (_minI <= val && val <= _maxI) {
int idx = MIN((val - _minI) / (_maxI - _minI) * nbins, nbins-1);
int index = dc * nbins + idx;
atomicAdd(&hist[index], 1.0f);
}
}
return ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPfS_S_S_iiiiS_
.globl _Z16histogram_kernelPfS_S_S_iiiiS_
.p2align 8
.type _Z16histogram_kernelPfS_S_S_iiiiS_,@function
_Z16histogram_kernelPfS_S_S_iiiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s5
s_mul_i32 s3, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_5
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v2, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_add_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v1, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v4, v1
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s2
s_load_b64 s[2:3], s[0:1], 0x18
v_sub_nc_u32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, 0x3fb99999
s_mov_b32 s2, 0x9999999a
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[3:4], v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ngt_f64_e32 vcc_lo, s[2:3], v[3:4]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
global_load_b32 v3, v[6:7], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(1)
v_dual_add_f32 v5, -1.0, v3 :: v_dual_add_f32 v2, 1.0, v4
v_cmp_eq_f32_e32 vcc_lo, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v3, v5
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s2, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_f32_e32 vcc_lo, v3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
v_sub_f32_e32 v1, v1, v3
v_sub_f32_e32 v2, v2, v3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, v1
v_div_scale_f32 v6, vcc_lo, v1, v2, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_cvt_f32_i32_e32 v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v3, v2, v1
v_cvt_f32_i32_e32 v2, s3
v_mul_f32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v1, v2
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v3, v[0:1], off
.LBB0_4:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v3
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16histogram_kernelPfS_S_S_iiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16histogram_kernelPfS_S_S_iiiiS_, .Lfunc_end0-_Z16histogram_kernelPfS_S_S_iiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16histogram_kernelPfS_S_S_iiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16histogram_kernelPfS_S_S_iiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 256
#define EPS 0.1
#undef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#undef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
__global__ void histogram_kernel( float *I, float *minI, float *maxI, float *mask, int nbins, int c, int h, int w, float *hist )
{
int _id = blockIdx.x * blockDim.x + threadIdx.x;
int size = h * w;
if (_id < c * size) {
int id = _id % size, dc = _id / size;
if (mask[id] < EPS)
return ;
float val = I[_id];
float _minI = minI[dc];
float _maxI = maxI[dc];
if (_minI == _maxI) {
_minI -= 1;
_maxI += 1;
}
if (_minI <= val && val <= _maxI) {
int idx = MIN((val - _minI) / (_maxI - _minI) * nbins, nbins-1);
int index = dc * nbins + idx;
atomicAdd(&hist[index], 1.0f);
}
}
return ;
} | .text
.file "histogram_kernel.hip"
.globl _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_ # -- Begin function _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_,@function
_Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_: # @_Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16histogram_kernelPfS_S_S_iiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_, .Lfunc_end0-_Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16histogram_kernelPfS_S_S_iiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16histogram_kernelPfS_S_S_iiiiS_,@object # @_Z16histogram_kernelPfS_S_S_iiiiS_
.section .rodata,"a",@progbits
.globl _Z16histogram_kernelPfS_S_S_iiiiS_
.p2align 3, 0x0
_Z16histogram_kernelPfS_S_S_iiiiS_:
.quad _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.size _Z16histogram_kernelPfS_S_S_iiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16histogram_kernelPfS_S_S_iiiiS_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16histogram_kernelPfS_S_S_iiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16histogram_kernelPfS_S_S_iiiiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff037624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R3, R3, c[0x0][0x188], RZ ; /* 0x0000620003037a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0205 */
/*0060*/ IMAD R5, R3, c[0x0][0x184], RZ ; /* 0x0000610003057a24 */
/* 0x000fca00078e02ff */
/*0070*/ ISETP.GE.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IABS R7, R3.reuse ; /* 0x0000000300077213 */
/* 0x080fe20000000000 */
/*00a0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*00b0*/ IABS R8, R2 ; /* 0x0000000200087213 */
/* 0x000fe20000000000 */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e220000209400 */
/*00e0*/ IABS R10, R3 ; /* 0x00000003000a7213 */
/* 0x000fce0000000000 */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*0140*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe400078e02ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0160*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fc800078e0004 */
/*0170*/ IMAD.MOV R9, RZ, RZ, -R10 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0a */
/*0180*/ IMAD.HI.U32 R0, R5, R6, RZ ; /* 0x0000000605007227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD R4, R0, R9, R6 ; /* 0x0000000900047224 */
/* 0x000fca00078e0206 */
/*01a0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fda0003f44070 */
/*01b0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a07 */
/*01c0*/ @!P2 IADD3 R0, R0, 0x1, RZ ; /* 0x000000010000a810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.NE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f45270 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*01f0*/ LOP3.LUT R4, R2, R3, RZ, 0x3c, !PT ; /* 0x0000000302047212 */
/* 0x000fc800078e3cff */
/*0200*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f26270 */
/*0210*/ @P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100000810 */
/* 0x000fcc0007ffe0ff */
/*0220*/ @!P1 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff009224 */
/* 0x000fe200078e0a00 */
/*0230*/ @!P2 LOP3.LUT R0, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff00a212 */
/* 0x000fca00078e33ff */
/*0240*/ IMAD.MOV R4, RZ, RZ, -R0 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a00 */
/*0250*/ IMAD R4, R3, R4, R2 ; /* 0x0000000403047224 */
/* 0x000fc800078e0202 */
/*0260*/ IMAD.WIDE R4, R4, R11, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fcc00078e020b */
/*0270*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1900 */
/*0280*/ F2F.F64.F32 R6, R4 ; /* 0x0000000400067310 */
/* 0x004e240000201800 */
/*0290*/ DSETP.GEU.AND P0, PT, R6, c[0x2][0x0], PT ; /* 0x008000000600762a */
/* 0x001e1c0003f0e000 */
/*02a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x001fea0003800000 */
/*02b0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e020b */
/*02c0*/ IMAD.WIDE R6, R0, R11.reuse, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x080fe200078e020b */
/*02d0*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.WIDE R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e020b */
/*0300*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ee2000c1e1900 */
/*0310*/ FSETP.NEU.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x004fda0003f0d000 */
/*0320*/ @!P0 FADD R8, R8, 1 ; /* 0x3f80000008088421 */
/* 0x000fe40000000000 */
/*0330*/ @!P0 FADD R9, R9, -1 ; /* 0xbf80000009098421 */
/* 0x000fc60000000000 */
/*0340*/ FSETP.GTU.AND P0, PT, R2, R8, PT ; /* 0x000000080200720b */
/* 0x008fc80003f0c000 */
/*0350*/ FSETP.GTU.OR P0, PT, R9, R2, P0 ; /* 0x000000020900720b */
/* 0x000fda000070c400 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ FADD R6, -R9.reuse, R8 ; /* 0x0000000809067221 */
/* 0x040fe20000000100 */
/*0380*/ BSSY B0, 0x460 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0390*/ FADD R5, -R9, R2 ; /* 0x0000000209057221 */
/* 0x000fe40000000100 */
/*03a0*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x000e300000001000 */
/*03b0*/ FCHK P0, R5, R6 ; /* 0x0000000605007302 */
/* 0x000e620000000000 */
/*03c0*/ FFMA R4, -R6, R3, 1 ; /* 0x3f80000006047423 */
/* 0x001fc80000000103 */
/*03d0*/ FFMA R4, R3, R4, R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000003 */
/*03e0*/ FFMA R3, R5, R4, RZ ; /* 0x0000000405037223 */
/* 0x000fc800000000ff */
/*03f0*/ FFMA R2, -R6, R3, R5 ; /* 0x0000000306027223 */
/* 0x000fc80000000105 */
/*0400*/ FFMA R2, R4, R2, R3 ; /* 0x0000000204027223 */
/* 0x000fe20000000003 */
/*0410*/ @!P0 BRA 0x450 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0420*/ MOV R2, 0x440 ; /* 0x0000044000027802 */
/* 0x000fe40000000f00 */
/*0430*/ CALL.REL.NOINC 0x540 ; /* 0x0000010000007944 */
/* 0x000fea0003c00000 */
/*0440*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*0470*/ I2F R3, c[0x0][0x180] ; /* 0x0000600000037b06 */
/* 0x000e220000201400 */
/*0480*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fd000078e00ff */
/*04a0*/ I2F R5, UR4 ; /* 0x0000000400057d06 */
/* 0x000e620008201400 */
/*04b0*/ FMUL R2, R3, R2 ; /* 0x0000000203027220 */
/* 0x001fe40000400000 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*04d0*/ FSETP.GEU.AND P0, PT, R2, R5, PT ; /* 0x000000050200720b */
/* 0x002fc80003f0e000 */
/*04e0*/ FSEL R5, R2, R5, !P0 ; /* 0x0000000502057208 */
/* 0x000fcc0004000000 */
/*04f0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000020f100 */
/*0500*/ IMAD R2, R0, c[0x0][0x180], R5 ; /* 0x0000600000027a24 */
/* 0x001fc800078e0205 */
/*0510*/ IMAD.WIDE R2, R2, R3, c[0x0][0x190] ; /* 0x0000640002027625 */
/* 0x000fca00078e0203 */
/*0520*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x000fe2000c10e786 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ SHF.R.U32.HI R4, RZ, 0x17, R6 ; /* 0x00000017ff047819 */
/* 0x000fe20000011606 */
/*0550*/ BSSY B1, 0xba0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0560*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fe40000011605 */
/*0570*/ LOP3.LUT R11, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040b7812 */
/* 0x000fe400078ec0ff */
/*0580*/ LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03097812 */
/* 0x000fe400078ec0ff */
/*0590*/ IADD3 R10, R11, -0x1, RZ ; /* 0xffffffff0b0a7810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R8, R9, -0x1, RZ ; /* 0xffffffff09087810 */
/* 0x000fc40007ffe0ff */
/*05b0*/ ISETP.GT.U32.AND P0, PT, R10, 0xfd, PT ; /* 0x000000fd0a00780c */
/* 0x000fc80003f04070 */
/*05c0*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*05d0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*05e0*/ @!P0 BRA 0x780 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe20003f1c200 */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0005 */
/*0610*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe20003f3c200 */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fc600078e0006 */
/*0630*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0640*/ @P0 BRA 0xb80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0650*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0660*/ @!P0 BRA 0xb60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0670*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0680*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0690*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*06a0*/ @!P1 BRA !P2, 0xb60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06b0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*06c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*06d0*/ @P1 BRA 0xb40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*06e0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*06f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0700*/ @P0 BRA 0xb10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0720*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd60003f26270 */
/*0730*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0740*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0750*/ @!P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003058823 */
/* 0x000fe400000000ff */
/*0760*/ @!P1 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004069823 */
/* 0x000fe200000000ff */
/*0770*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0780*/ LEA R3, R11, 0xc0800000, 0x17 ; /* 0xc08000000b037811 */
/* 0x000fe200078eb8ff */
/*0790*/ BSSY B2, 0xb00 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07a0*/ IADD3 R4, R9, -0x7f, RZ ; /* 0xffffff8109047810 */
/* 0x000fc60007ffe0ff */
/*07b0*/ IMAD.IADD R6, R6, 0x1, -R3 ; /* 0x0000000106067824 */
/* 0x000fe400078e0a03 */
/*07c0*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fe400078e0205 */
/*07d0*/ MUFU.RCP R3, R6 ; /* 0x0000000600037308 */
/* 0x0000620000001000 */
/*07e0*/ FADD.FTZ R8, -R6, -RZ ; /* 0x800000ff06087221 */
/* 0x000fe20000010100 */
/*07f0*/ IADD3 R6, R4, 0x7f, -R11 ; /* 0x0000007f04067810 */
/* 0x001fca0007ffe80b */
/*0800*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*0810*/ FFMA R10, R3, R8, 1 ; /* 0x3f800000030a7423 */
/* 0x002fc80000000008 */
/*0820*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0830*/ FFMA R3, R5, R12, RZ ; /* 0x0000000c05037223 */
/* 0x000fc800000000ff */
/*0840*/ FFMA R10, R8, R3, R5 ; /* 0x00000003080a7223 */
/* 0x000fc80000000005 */
/*0850*/ FFMA R9, R12, R10, R3 ; /* 0x0000000a0c097223 */
/* 0x000fc80000000003 */
/*0860*/ FFMA R5, R8, R9, R5 ; /* 0x0000000908057223 */
/* 0x000fc80000000005 */
/*0870*/ FFMA R3, R12, R5, R9 ; /* 0x000000050c037223 */
/* 0x000fca0000000009 */
/*0880*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0890*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*08a0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*08b0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*08c0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*08d0*/ @!P0 BRA 0xae0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*08f0*/ @P0 BRA 0xab0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0900*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0910*/ @P0 BRA 0xaf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0920*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0930*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0940*/ @!P0 BRA 0xaf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0950*/ FFMA.RZ R4, R12, R5.reuse, R9.reuse ; /* 0x000000050c047223 */
/* 0x180fe2000000c009 */
/*0960*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe40007ffe0ff */
/*0970*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0980*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0990*/ FFMA.RP R4, R12, R5.reuse, R9.reuse ; /* 0x000000050c047223 */
/* 0x180fe20000008009 */
/*09a0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*09b0*/ FFMA.RM R5, R12, R5, R9 ; /* 0x000000050c057223 */
/* 0x000fe20000004009 */
/*09c0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe200078efcff */
/*09d0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0a08 */
/*09e0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*09f0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fe40003f1d000 */
/*0a00*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0a10*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0a20*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0a30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0a40*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fe40000011605 */
/*0a50*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a60*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0a70*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0a80*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0a90*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0aa0*/ BRA 0xaf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0ac0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xaf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0af0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b10*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fc800078e4805 */
/*0b20*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b30*/ BRA 0xb90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R3, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006037812 */
/* 0x000fe200078e4805 */
/*0b50*/ BRA 0xb90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b60*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0b70*/ BRA 0xb90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b80*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0b90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ba0*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0003 */
/*0bb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0bc0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff43002007950 */
/* 0x000fea0003c3ffff */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPfS_S_S_iiiiS_
.globl _Z16histogram_kernelPfS_S_S_iiiiS_
.p2align 8
.type _Z16histogram_kernelPfS_S_S_iiiiS_,@function
_Z16histogram_kernelPfS_S_S_iiiiS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s5
s_mul_i32 s3, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_5
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v2, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v1, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_add_nc_u32_e32 v0, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v1, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v4, v1
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v1
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cmp_le_u32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s2
s_load_b64 s[2:3], s[0:1], 0x18
v_sub_nc_u32_e32 v3, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s3, 0x3fb99999
s_mov_b32 s2, 0x9999999a
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[3:4], v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ngt_f64_e32 vcc_lo, s[2:3], v[3:4]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
global_load_b32 v3, v[6:7], off
global_load_b32 v4, v[4:5], off
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(1)
v_dual_add_f32 v5, -1.0, v3 :: v_dual_add_f32 v2, 1.0, v4
v_cmp_eq_f32_e32 vcc_lo, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v3, v5
s_waitcnt vmcnt(0)
v_cmp_le_f32_e64 s2, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_f32_e32 vcc_lo, v3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
v_sub_f32_e32 v1, v1, v3
v_sub_f32_e32 v2, v2, v3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x30
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, v1
v_div_scale_f32 v6, vcc_lo, v1, v2, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_cvt_f32_i32_e32 v4, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v3, v2, v1
v_cvt_f32_i32_e32 v2, s3
v_mul_f32_e32 v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v1, v2
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_cvt_i32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v3, v[0:1], off
.LBB0_4:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v3
global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
v_mov_b32_e32 v3, v2
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_4
.LBB0_5:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16histogram_kernelPfS_S_S_iiiiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16histogram_kernelPfS_S_S_iiiiS_, .Lfunc_end0-_Z16histogram_kernelPfS_S_S_iiiiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16histogram_kernelPfS_S_S_iiiiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16histogram_kernelPfS_S_S_iiiiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00146f09_00000000-6_histogram_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_
.type _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_, @function
_Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16histogram_kernelPfS_S_S_iiiiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_, .-_Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_
.globl _Z16histogram_kernelPfS_S_S_iiiiS_
.type _Z16histogram_kernelPfS_S_S_iiiiS_, @function
_Z16histogram_kernelPfS_S_S_iiiiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z48__device_stub__Z16histogram_kernelPfS_S_S_iiiiS_PfS_S_S_iiiiS_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16histogram_kernelPfS_S_S_iiiiS_, .-_Z16histogram_kernelPfS_S_S_iiiiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16histogram_kernelPfS_S_S_iiiiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16histogram_kernelPfS_S_S_iiiiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histogram_kernel.hip"
.globl _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_ # -- Begin function _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_,@function
_Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_: # @_Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16histogram_kernelPfS_S_S_iiiiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_, .Lfunc_end0-_Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16histogram_kernelPfS_S_S_iiiiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16histogram_kernelPfS_S_S_iiiiS_,@object # @_Z16histogram_kernelPfS_S_S_iiiiS_
.section .rodata,"a",@progbits
.globl _Z16histogram_kernelPfS_S_S_iiiiS_
.p2align 3, 0x0
_Z16histogram_kernelPfS_S_S_iiiiS_:
.quad _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.size _Z16histogram_kernelPfS_S_S_iiiiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16histogram_kernelPfS_S_S_iiiiS_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__histogram_kernelPfS_S_S_iiiiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16histogram_kernelPfS_S_S_iiiiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void saxpy_baseline ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
y[idx] = a * x[idx] + y[idx];
}
} | code for sm_80
Function : _Z14saxpy_baselinePfS_fPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, 0x300, R3 ; /* 0x0000030002027824 */
/* 0x001fe200078e0203 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 5.9604644775390625e-08, 32 ; /* 0x00015000ff037435 */
/* 0x000fc800000001ff */
/*0060*/ IADD3 R0, R2, 0x27600, RZ ; /* 0x0002760002007810 */
/* 0x000fe40007ffe0ff */
/*0070*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x002fca0000000f00 */
/*0080*/ IMAD.WIDE.U32 R6, R2, R5, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R8, R2.reuse, R5, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x040fe400078e0005 */
/*00a0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IADD3 R12, R2, 0x2a00, RZ ; /* 0x00002a00020c7810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ FFMA R17, R6, c[0x0][0x170], R11 ; /* 0x00005c0006117a23 */
/* 0x004fc8000000000b */
/*00e0*/ IMAD.WIDE.U32 R10, R12.reuse, R5.reuse, c[0x0][0x168] ; /* 0x00005a000c0a7625 */
/* 0x0c0fe200078e0005 */
/*00f0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0001e6000c101904 */
/*0100*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe400078e0005 */
/*0110*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R14, R2, 0x5400, RZ ; /* 0x00005400020e7810 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD.WIDE.U32 R6, R14, R5, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x000fc800078e0005 */
/*0150*/ FFMA R19, R10, c[0x0][0x170], R15 ; /* 0x00005c000a137a23 */
/* 0x004fe4000000000f */
/*0160*/ IMAD.WIDE.U32 R14, R14, R5, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc600078e0005 */
/*0170*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c101904 */
/*0180*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IADD3 R4, R2, 0x7e00, RZ ; /* 0x00007e0002047810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x001fc800078e0005 */
/*01c0*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x000fc800078e0005 */
/*01d0*/ FFMA R21, R6, c[0x0][0x170], R21 ; /* 0x00005c0006157a23 */
/* 0x004fca0000000015 */
/*01e0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IADD3 R4, R2, 0xa800, RZ ; /* 0x0000a80002047810 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*0230*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x002fc800078e0005 */
/*0240*/ FFMA R17, R8, c[0x0][0x170], R17 ; /* 0x00005c0008117a23 */
/* 0x004fca0000000011 */
/*0250*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0003e8000c101904 */
/*0260*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IADD3 R4, R2, 0xd200, RZ ; /* 0x0000d20002047810 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*02a0*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x001fc800078e0005 */
/*02b0*/ FFMA R19, R6, c[0x0][0x170], R19 ; /* 0x00005c0006137a23 */
/* 0x004fca0000000013 */
/*02c0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IADD3 R4, R2, 0xfc00, RZ ; /* 0x0000fc0002047810 */
/* 0x000fca0007ffe0ff */
/*0300*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*0310*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fc800078e0005 */
/*0320*/ FFMA R21, R8, c[0x0][0x170], R21 ; /* 0x00005c0008157a23 */
/* 0x004fca0000000015 */
/*0330*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0340*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IADD3 R4, R2, 0x12600, RZ ; /* 0x0001260002047810 */
/* 0x000fca0007ffe0ff */
/*0370*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0380*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fc800078e0005 */
/*0390*/ FFMA R17, R6, c[0x0][0x170], R17 ; /* 0x00005c0006117a23 */
/* 0x004fca0000000011 */
/*03a0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IADD3 R4, R2, 0x15000, RZ ; /* 0x0001500002047810 */
/* 0x000fca0007ffe0ff */
/*03e0*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*03f0*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x002fc800078e0005 */
/*0400*/ FFMA R19, R8, c[0x0][0x170], R19 ; /* 0x00005c0008137a23 */
/* 0x004fca0000000013 */
/*0410*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IADD3 R4, R0, -0xfc00, RZ ; /* 0xffff040000047810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0460*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x001fc800078e0005 */
/*0470*/ FFMA R21, R6, c[0x0][0x170], R21 ; /* 0x00005c0006157a23 */
/* 0x004fca0000000015 */
/*0480*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IADD3 R4, R0, -0xd200, RZ ; /* 0xffff2e0000047810 */
/* 0x000fca0007ffe0ff */
/*04c0*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*04d0*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x002fc800078e0005 */
/*04e0*/ FFMA R17, R8, c[0x0][0x170], R17 ; /* 0x00005c0008117a23 */
/* 0x004fca0000000011 */
/*04f0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0003e8000c101904 */
/*0500*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IADD3 R4, R0, -0xa800, RZ ; /* 0xffff580000047810 */
/* 0x000fca0007ffe0ff */
/*0530*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0540*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x001fc800078e0005 */
/*0550*/ FFMA R19, R6, c[0x0][0x170], R19 ; /* 0x00005c0006137a23 */
/* 0x004fca0000000013 */
/*0560*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R4, R0, -0x7e00, RZ ; /* 0xffff820000047810 */
/* 0x000fca0007ffe0ff */
/*05a0*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*05b0*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fc800078e0005 */
/*05c0*/ FFMA R21, R8, c[0x0][0x170], R21 ; /* 0x00005c0008157a23 */
/* 0x004fca0000000015 */
/*05d0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IADD3 R4, R0, -0x5400, RZ ; /* 0xffffac0000047810 */
/* 0x000fca0007ffe0ff */
/*0610*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0620*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fc800078e0005 */
/*0630*/ FFMA R17, R6, c[0x0][0x170], R17 ; /* 0x00005c0006117a23 */
/* 0x004fca0000000011 */
/*0640*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IADD3 R4, R0, -0x2a00, RZ ; /* 0xffffd60000047810 */
/* 0x000fca0007ffe0ff */
/*0680*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*0690*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x002fc800078e0005 */
/*06a0*/ FFMA R19, R8, c[0x0][0x170], R19 ; /* 0x00005c0008137a23 */
/* 0x004fca0000000013 */
/*06b0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c101904 */
/*06c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IMAD.WIDE.U32 R10, R0, R5, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x001fc800078e0005 */
/*06f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0005 */
/*0700*/ FFMA R21, R6, c[0x0][0x170], R21 ; /* 0x00005c0006157a23 */
/* 0x004fca0000000015 */
/*0710*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0720*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0740*/ IADD3 R3, R3, 0x2a000, RZ ; /* 0x0002a00003037810 */
/* 0x000fe40007ffe0ff */
/*0750*/ IADD3 R2, R2, 0x2a000, RZ ; /* 0x0002a00002027810 */
/* 0x000fc40007ffe0ff */
/*0760*/ ISETP.NE.AND P0, PT, R3, 0x1515000, PT ; /* 0x015150000300780c */
/* 0x000fe40003f05270 */
/*0770*/ IADD3 R0, R0, 0x2a000, RZ ; /* 0x0002a00000007810 */
/* 0x000fe20007ffe0ff */
/*0780*/ FFMA R9, R10, c[0x0][0x170], R9 ; /* 0x00005c000a097a23 */
/* 0x004fca0000000009 */
/*0790*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0003ea000c101904 */
/*07a0*/ @P0 BRA 0x70 ; /* 0xfffff8c000000947 */
/* 0x000fea000383ffff */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ BRA 0x7c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void saxpy_baseline ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
y[idx] = a * x[idx] + y[idx];
}
} | .file "tmpxft_00161d27_00000000-6_saxpy_baseline.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl
.type _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl, @function
_Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14saxpy_baselinePfS_fPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl, .-_Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl
.globl _Z14saxpy_baselinePfS_fPl
.type _Z14saxpy_baselinePfS_fPl, @function
_Z14saxpy_baselinePfS_fPl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14saxpy_baselinePfS_fPl, .-_Z14saxpy_baselinePfS_fPl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14saxpy_baselinePfS_fPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14saxpy_baselinePfS_fPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void saxpy_baseline ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
y[idx] = a * x[idx] + y[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_baseline ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
y[idx] = a * x[idx] + y[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_baseline ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
y[idx] = a * x[idx] + y[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14saxpy_baselinePfS_fPl
.globl _Z14saxpy_baselinePfS_fPl
.p2align 8
.type _Z14saxpy_baselinePfS_fPl,@function
_Z14saxpy_baselinePfS_fPl:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, s15, 0x300, v[0:1]
v_mov_b32_e32 v3, 0
s_mov_b32 s1, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s1, v1
s_addk_i32 s1, 0x2a00
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s1, 0x1500000
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v0, v[6:7], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s0, v0
global_store_b32 v[4:5], v2, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14saxpy_baselinePfS_fPl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14saxpy_baselinePfS_fPl, .Lfunc_end0-_Z14saxpy_baselinePfS_fPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14saxpy_baselinePfS_fPl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14saxpy_baselinePfS_fPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_baseline ( float* y, float* x, float a, clock_t * timer_vals)
{
for (int i=0; i < NUM_ITERS; i++) {
unsigned int idx = i * COMPUTE_THREADS_PER_CTA * CTA_COUNT + blockIdx.x * COMPUTE_THREADS_PER_CTA + threadIdx.x;
y[idx] = a * x[idx] + y[idx];
}
} | .text
.file "saxpy_baseline.hip"
.globl _Z29__device_stub__saxpy_baselinePfS_fPl # -- Begin function _Z29__device_stub__saxpy_baselinePfS_fPl
.p2align 4, 0x90
.type _Z29__device_stub__saxpy_baselinePfS_fPl,@function
_Z29__device_stub__saxpy_baselinePfS_fPl: # @_Z29__device_stub__saxpy_baselinePfS_fPl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14saxpy_baselinePfS_fPl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__saxpy_baselinePfS_fPl, .Lfunc_end0-_Z29__device_stub__saxpy_baselinePfS_fPl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14saxpy_baselinePfS_fPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14saxpy_baselinePfS_fPl,@object # @_Z14saxpy_baselinePfS_fPl
.section .rodata,"a",@progbits
.globl _Z14saxpy_baselinePfS_fPl
.p2align 3, 0x0
_Z14saxpy_baselinePfS_fPl:
.quad _Z29__device_stub__saxpy_baselinePfS_fPl
.size _Z14saxpy_baselinePfS_fPl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14saxpy_baselinePfS_fPl"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__saxpy_baselinePfS_fPl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14saxpy_baselinePfS_fPl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14saxpy_baselinePfS_fPl
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R2, R2, 0x300, R3 ; /* 0x0000030002027824 */
/* 0x001fe200078e0203 */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 5.9604644775390625e-08, 32 ; /* 0x00015000ff037435 */
/* 0x000fc800000001ff */
/*0060*/ IADD3 R0, R2, 0x27600, RZ ; /* 0x0002760002007810 */
/* 0x000fe40007ffe0ff */
/*0070*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x002fca0000000f00 */
/*0080*/ IMAD.WIDE.U32 R6, R2, R5, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R8, R2.reuse, R5, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x040fe400078e0005 */
/*00a0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IADD3 R12, R2, 0x2a00, RZ ; /* 0x00002a00020c7810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ FFMA R17, R6, c[0x0][0x170], R11 ; /* 0x00005c0006117a23 */
/* 0x004fc8000000000b */
/*00e0*/ IMAD.WIDE.U32 R10, R12.reuse, R5.reuse, c[0x0][0x168] ; /* 0x00005a000c0a7625 */
/* 0x0c0fe200078e0005 */
/*00f0*/ STG.E [R8.64], R17 ; /* 0x0000001108007986 */
/* 0x0001e6000c101904 */
/*0100*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe400078e0005 */
/*0110*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R14, R2, 0x5400, RZ ; /* 0x00005400020e7810 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD.WIDE.U32 R6, R14, R5, c[0x0][0x168] ; /* 0x00005a000e067625 */
/* 0x000fc800078e0005 */
/*0150*/ FFMA R19, R10, c[0x0][0x170], R15 ; /* 0x00005c000a137a23 */
/* 0x004fe4000000000f */
/*0160*/ IMAD.WIDE.U32 R14, R14, R5, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fc600078e0005 */
/*0170*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c101904 */
/*0180*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0190*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IADD3 R4, R2, 0x7e00, RZ ; /* 0x00007e0002047810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x001fc800078e0005 */
/*01c0*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x000fc800078e0005 */
/*01d0*/ FFMA R21, R6, c[0x0][0x170], R21 ; /* 0x00005c0006157a23 */
/* 0x004fca0000000015 */
/*01e0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IADD3 R4, R2, 0xa800, RZ ; /* 0x0000a80002047810 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*0230*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x002fc800078e0005 */
/*0240*/ FFMA R17, R8, c[0x0][0x170], R17 ; /* 0x00005c0008117a23 */
/* 0x004fca0000000011 */
/*0250*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0003e8000c101904 */
/*0260*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IADD3 R4, R2, 0xd200, RZ ; /* 0x0000d20002047810 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*02a0*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x001fc800078e0005 */
/*02b0*/ FFMA R19, R6, c[0x0][0x170], R19 ; /* 0x00005c0006137a23 */
/* 0x004fca0000000013 */
/*02c0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IADD3 R4, R2, 0xfc00, RZ ; /* 0x0000fc0002047810 */
/* 0x000fca0007ffe0ff */
/*0300*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*0310*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fc800078e0005 */
/*0320*/ FFMA R21, R8, c[0x0][0x170], R21 ; /* 0x00005c0008157a23 */
/* 0x004fca0000000015 */
/*0330*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0340*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IADD3 R4, R2, 0x12600, RZ ; /* 0x0001260002047810 */
/* 0x000fca0007ffe0ff */
/*0370*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0380*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fc800078e0005 */
/*0390*/ FFMA R17, R6, c[0x0][0x170], R17 ; /* 0x00005c0006117a23 */
/* 0x004fca0000000011 */
/*03a0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IADD3 R4, R2, 0x15000, RZ ; /* 0x0001500002047810 */
/* 0x000fca0007ffe0ff */
/*03e0*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*03f0*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x002fc800078e0005 */
/*0400*/ FFMA R19, R8, c[0x0][0x170], R19 ; /* 0x00005c0008137a23 */
/* 0x004fca0000000013 */
/*0410*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IADD3 R4, R0, -0xfc00, RZ ; /* 0xffff040000047810 */
/* 0x000fca0007ffe0ff */
/*0450*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0460*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x001fc800078e0005 */
/*0470*/ FFMA R21, R6, c[0x0][0x170], R21 ; /* 0x00005c0006157a23 */
/* 0x004fca0000000015 */
/*0480*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IADD3 R4, R0, -0xd200, RZ ; /* 0xffff2e0000047810 */
/* 0x000fca0007ffe0ff */
/*04c0*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*04d0*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x002fc800078e0005 */
/*04e0*/ FFMA R17, R8, c[0x0][0x170], R17 ; /* 0x00005c0008117a23 */
/* 0x004fca0000000011 */
/*04f0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0003e8000c101904 */
/*0500*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0520*/ IADD3 R4, R0, -0xa800, RZ ; /* 0xffff580000047810 */
/* 0x000fca0007ffe0ff */
/*0530*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0540*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x001fc800078e0005 */
/*0550*/ FFMA R19, R6, c[0x0][0x170], R19 ; /* 0x00005c0006137a23 */
/* 0x004fca0000000013 */
/*0560*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R4, R0, -0x7e00, RZ ; /* 0xffff820000047810 */
/* 0x000fca0007ffe0ff */
/*05a0*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*05b0*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fc800078e0005 */
/*05c0*/ FFMA R21, R8, c[0x0][0x170], R21 ; /* 0x00005c0008157a23 */
/* 0x004fca0000000015 */
/*05d0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IADD3 R4, R0, -0x5400, RZ ; /* 0xffffac0000047810 */
/* 0x000fca0007ffe0ff */
/*0610*/ IMAD.WIDE.U32 R8, R4, R5, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fc800078e0005 */
/*0620*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fc800078e0005 */
/*0630*/ FFMA R17, R6, c[0x0][0x170], R17 ; /* 0x00005c0006117a23 */
/* 0x004fca0000000011 */
/*0640*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IADD3 R4, R0, -0x2a00, RZ ; /* 0xffffd60000047810 */
/* 0x000fca0007ffe0ff */
/*0680*/ IMAD.WIDE.U32 R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fc800078e0005 */
/*0690*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x002fc800078e0005 */
/*06a0*/ FFMA R19, R8, c[0x0][0x170], R19 ; /* 0x00005c0008137a23 */
/* 0x004fca0000000013 */
/*06b0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0003e8000c101904 */
/*06c0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IMAD.WIDE.U32 R10, R0, R5, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x001fc800078e0005 */
/*06f0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0005 */
/*0700*/ FFMA R21, R6, c[0x0][0x170], R21 ; /* 0x00005c0006157a23 */
/* 0x004fca0000000015 */
/*0710*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0720*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0740*/ IADD3 R3, R3, 0x2a000, RZ ; /* 0x0002a00003037810 */
/* 0x000fe40007ffe0ff */
/*0750*/ IADD3 R2, R2, 0x2a000, RZ ; /* 0x0002a00002027810 */
/* 0x000fc40007ffe0ff */
/*0760*/ ISETP.NE.AND P0, PT, R3, 0x1515000, PT ; /* 0x015150000300780c */
/* 0x000fe40003f05270 */
/*0770*/ IADD3 R0, R0, 0x2a000, RZ ; /* 0x0002a00000007810 */
/* 0x000fe20007ffe0ff */
/*0780*/ FFMA R9, R10, c[0x0][0x170], R9 ; /* 0x00005c000a097a23 */
/* 0x004fca0000000009 */
/*0790*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0003ea000c101904 */
/*07a0*/ @P0 BRA 0x70 ; /* 0xfffff8c000000947 */
/* 0x000fea000383ffff */
/*07b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07c0*/ BRA 0x7c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14saxpy_baselinePfS_fPl
.globl _Z14saxpy_baselinePfS_fPl
.p2align 8
.type _Z14saxpy_baselinePfS_fPl,@function
_Z14saxpy_baselinePfS_fPl:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, s15, 0x300, v[0:1]
v_mov_b32_e32 v3, 0
s_mov_b32 s1, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s1, v1
s_addk_i32 s1, 0x2a00
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s1, 0x1500000
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v0, v[6:7], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s0, v0
global_store_b32 v[4:5], v2, off
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14saxpy_baselinePfS_fPl
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14saxpy_baselinePfS_fPl, .Lfunc_end0-_Z14saxpy_baselinePfS_fPl
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14saxpy_baselinePfS_fPl
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14saxpy_baselinePfS_fPl.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00161d27_00000000-6_saxpy_baseline.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl
.type _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl, @function
_Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14saxpy_baselinePfS_fPl(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl, .-_Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl
.globl _Z14saxpy_baselinePfS_fPl
.type _Z14saxpy_baselinePfS_fPl, @function
_Z14saxpy_baselinePfS_fPl:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14saxpy_baselinePfS_fPlPfS_fPl
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14saxpy_baselinePfS_fPl, .-_Z14saxpy_baselinePfS_fPl
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14saxpy_baselinePfS_fPl"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14saxpy_baselinePfS_fPl(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_baseline.hip"
.globl _Z29__device_stub__saxpy_baselinePfS_fPl # -- Begin function _Z29__device_stub__saxpy_baselinePfS_fPl
.p2align 4, 0x90
.type _Z29__device_stub__saxpy_baselinePfS_fPl,@function
_Z29__device_stub__saxpy_baselinePfS_fPl: # @_Z29__device_stub__saxpy_baselinePfS_fPl
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14saxpy_baselinePfS_fPl, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__saxpy_baselinePfS_fPl, .Lfunc_end0-_Z29__device_stub__saxpy_baselinePfS_fPl
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14saxpy_baselinePfS_fPl, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14saxpy_baselinePfS_fPl,@object # @_Z14saxpy_baselinePfS_fPl
.section .rodata,"a",@progbits
.globl _Z14saxpy_baselinePfS_fPl
.p2align 3, 0x0
_Z14saxpy_baselinePfS_fPl:
.quad _Z29__device_stub__saxpy_baselinePfS_fPl
.size _Z14saxpy_baselinePfS_fPl, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14saxpy_baselinePfS_fPl"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__saxpy_baselinePfS_fPl
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14saxpy_baselinePfS_fPl
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <limits>
using namespace std;
#define Nparticles 30
#define T_MAX 1000
#define NFC_MAX 1000000
#define W_0 0.9
#define W_T 0.4
#define MAX_V 2.0
#define c1 2.0
#define c2 2.0
#define Nvariables 30
#define Rand() ((double)rand()/RAND_MAX);
__global__ void evalPlane(int n, double *x, double *fit) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
fit[i] += x[i] * x[i];
}
class Particle {
public:
double *x;
double *v;
double fitness;
double pBest;
double *xBest;
};
class Swarm {
private:
int gBest; //index
double gBestValue;
public:
Particle *P;
Swarm();
void setGBestIndex(int index);
void setGBestValue(double gBestValue);
void setParticleXV(int i, int j, double x, double v);
void setParticleFitness(int i, double fit);
void setParticlePBest(int i, double value, double *x);
Particle getParticleValue(int i);
int getGbest();
double getGbestValue();
};
Swarm::Swarm() {
gBest = 0;
P = (Particle *)malloc(sizeof(Particle)*Nparticles);
if (P==NULL) {
fprintf(stderr, "Cannot allocate memory for %d Particles\n", Nparticles);
exit (1);
}
for(int i = 0; i < Nparticles; i++) {
P[i].x = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].x==NULL) {
fprintf(stderr, "Cannot allocate memory for %d x\n", Nvariables);
exit (1);
}
P[i].v = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].v==NULL) {
fprintf(stderr, "Cannot allocate memory for %d v\n", Nvariables);
exit (1);
}
P[i].xBest = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].xBest==NULL) {
fprintf(stderr, "Cannot allocate memory for %d xBest\n", Nvariables);
exit (1);
}
}
}
void Swarm::setGBestIndex(int index) {
this->gBest = index;
}
void Swarm::setGBestValue(double gBestValue) {
this->gBestValue = gBestValue;
}
void Swarm::setParticleXV(int i, int j, double x, double v) {
if (x != NULL) P[i].x[j] = x;
if (v != NULL) P[i].v[j] = v;
}
void Swarm::setParticleFitness(int i, double fit) {
P[i].fitness = fit;
}
void Swarm::setParticlePBest(int i, double value, double *x) {
P[i].pBest = value;
for(int j = 0; j < Nvariables; j++)
{
P[i].xBest[j] = P[i].x[j];
}
}
Particle Swarm::getParticleValue(int i) {
return P[i];
}
int Swarm::getGbest() {
return gBest;
}
double Swarm::getGbestValue() {
return gBestValue;
}
class PSO {
private:
int nfc;
double w;
double *maxV;
public:
Swarm swarm;
PSO();
void initialize();
void evolution();
void updateBest(int i);
void calculateVMax();
void particleMovement();
void evaluate(int i);
void evaluateSwarm();
};
PSO::PSO() {
maxV = (double *)malloc(sizeof(double)*Nvariables);
if (maxV==NULL) {
fprintf(stderr, "Cannot allocate memory for %d maxV\n", Nvariables);
exit (1);
}
}
void PSO::evolution() {
double dw = (W_0 - W_T) / (NFC_MAX / Nparticles);
w = W_0;
initialize();
nfc = 0;
while(nfc < NFC_MAX) {
calculateVMax();
particleMovement();
evaluateSwarm();
w -= dw;
}
}
void PSO::initialize() {
swarm.setGBestValue(numeric_limits<double>::max());
for(int i = 0; i < Nparticles; i++) {
for(int j = 0; j < Nvariables; j++) {
double x = -5.12 + 10.24 * Rand();
//double x = Rand();
double v = 0.0;
swarm.setParticleXV(i, j, x, v);
}
evaluate(i);
updateBest(i);
double fitness = swarm.getParticleValue(i).fitness;
double gbest = swarm.getGbestValue();
if (fitness < gbest) {
swarm.setGBestValue(fitness);
swarm.setGBestIndex(i);
}
}
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("0 : ");
for (int j = 0; j < Nvariables; j++)
printf("%g ", best.xBest[j]);
printf(" = %e\n", best.pBest);
}
void PSO::evaluate(int i) {
//int index = i;
int ThreadsInBlock = 8;
int BlocksInGrid = (int)(Nvariables + ThreadsInBlock - 1) / ThreadsInBlock;
double *fitness = (double *)malloc(sizeof(double));
cudaMallocManaged((void **)&fitness, sizeof(double));
cudaMallocManaged((void **)&swarm.P[i].x, sizeof(double)*Nvariables);
evalPlane<<<BlocksInGrid, ThreadsInBlock>>>(Nvariables, swarm.P[i].x, fitness);
cudaGetLastError();
//if (cudaSuccess != cudaMemcpy())
cudaDeviceSynchronize();
// double fitness = 0.0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// int x = swarm.getParticleValue(index).x[k];
// fitness += x * x;
// }
// double fitness = 0, temp = 0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// for(int l = 0; l < k; l++)
// {
// double x = swarm.getParticleValue(index).x[l];
// temp += x;
// }
// fitness += temp * temp;
// }
cudaFree(fitness);
cudaFree(swarm.P[i].x);
//swarm.setParticleFitness(index, fitness);
}
void PSO::evaluateSwarm() {
for(int i = 0; i < Nparticles; i++) {
evaluate(i);
nfc++;
if (nfc % 5000 == 0) {
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("%d : ", nfc);
// for (int j = 0; j < Nvariables; j++)
// printf("%g ", best.xBest[j]);
printf(" = %g\n", best.pBest);
//cout << "PSO SPHERE nfc" << nfc << " \tbestfit " << best.pBest << "\n";
}
}
for(int n = 0; n < Nparticles; n++) {
Particle par = swarm.getParticleValue(n);
if (par.fitness < par.pBest ) {
swarm.setParticlePBest(n, par.fitness, par.x);
if (par.fitness < swarm.getGbestValue() ) {
swarm.setGBestIndex(n);
swarm.setGBestValue(par.fitness);
}
}
}
}
void PSO::updateBest(int i) {
Particle par = swarm.getParticleValue(i);
swarm.setParticlePBest(i, par.fitness, par.x);
}
void PSO::calculateVMax() {
double xmin[Nparticles], xmax[Nparticles];
for (int d = 0; d < Nvariables; d++) {
xmin[d] = xmax[d] = swarm.getParticleValue(0).x[d];
for (int n = 1; n < Nparticles; n++) {
double pos = swarm.getParticleValue(n).x[d];
if (pos < xmin[d])
xmin[d] = pos;
if (pos > xmax[d])
xmax[d] = pos;
}
maxV[d] = xmax[d] - xmin[d];
}
}
void PSO::particleMovement() {
int n, d;
for (n = 0; n < Nparticles ; n++) {
Particle par = swarm.getParticleValue(n);
Particle bPar = swarm.getParticleValue(swarm.getGbest());
// update velocities
for(d = 0; d < Nvariables ; d++ ) {
double r1 = Rand();
double r2 = Rand();
double newV = w * par.v[d] + c1 * r1 * (par.xBest[d] - par.x[d]) + c2 * r2 * (bPar.x[d] - par.x[d]);
swarm.setParticleXV(n, d, NULL, newV);
// check v with its dimensional maxV
if ( swarm.getParticleValue(n).v[d] > maxV[d] ) swarm.setParticleXV(n, d, NULL, maxV[d]);
else if ( swarm.getParticleValue(n).v[d] < -maxV[d] ) swarm.setParticleXV(n, d, NULL, -maxV[d]);
}
// update positions
Particle newPar = swarm.getParticleValue(n);
for (d = 0; d < Nvariables ; d++) {
//newPar.x[d] = newPar.x[d] + newPar.v[d];
swarm.setParticleXV(n, d, newPar.x[d] + newPar.v[d], NULL);
}
}
}
int main(int argc, char **argv) {
//int threadCount = BlocksInGrid * ThreadsInBlock;
//long size = threadCount * sizeof(double);
PSO pso;
pso.evolution();
return 0;
} | code for sm_80
Function : _Z9evalPlaneiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a8000c1e1b00 */
/*0280*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*02d0*/ DFMA R10, R8, R8, R10 ; /* 0x00000008080a722b */
/* 0x004e0e000000000a */
/*02e0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0011e4000c101b04 */
/*02f0*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe400078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x002fc800078e00ff */
/*0340*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0208 */
/*0350*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fe200078e0208 */
/*0360*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0370*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1b00 */
/*0380*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fe200078e0208 */
/*0390*/ DFMA R10, R6, R6, R10 ; /* 0x00000006060a722b */
/* 0x004046000000000a */
/*03a0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x001fc800078e0204 */
/*03b0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0021e8000c101b04 */
/*03c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1b00 */
/*03d0*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IMAD.WIDE R18, R0, 0x8, R14 ; /* 0x0000000800127825 */
/* 0x000fe200078e020e */
/*03f0*/ DFMA R16, R12, R12, R16 ; /* 0x0000000c0c10722b */
/* 0x0042860000000010 */
/*0400*/ IMAD.WIDE R12, R0, 0x8, R6 ; /* 0x00000008000c7825 */
/* 0x002fc800078e0206 */
/*0410*/ STG.E.64 [R14.64], R16 ; /* 0x000000100e007986 */
/* 0x0043e8000c101b04 */
/*0420*/ LDG.E.64 R4, [R12.64] ; /* 0x000000040c047981 */
/* 0x000ea8000c1e1b00 */
/*0430*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R8, R0, 0x8, R18 ; /* 0x0000000800087825 */
/* 0x001fe200078e0212 */
/*0450*/ DFMA R20, R4, R4, R20 ; /* 0x000000040414722b */
/* 0x0040860000000014 */
/*0460*/ IMAD.WIDE R4, R0, 0x8, R12 ; /* 0x0000000800047825 */
/* 0x001fc800078e020c */
/*0470*/ STG.E.64 [R18.64], R20 ; /* 0x0000001412007986 */
/* 0x0043e8000c101b04 */
/*0480*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ DFMA R6, R4, R4, R6 ; /* 0x000000040406722b */
/* 0x004e0e0000000006 */
/*04e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0013ea000c101b04 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cstdlib>
#include <limits>
using namespace std;
#define Nparticles 30
#define T_MAX 1000
#define NFC_MAX 1000000
#define W_0 0.9
#define W_T 0.4
#define MAX_V 2.0
#define c1 2.0
#define c2 2.0
#define Nvariables 30
#define Rand() ((double)rand()/RAND_MAX);
__global__ void evalPlane(int n, double *x, double *fit) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
fit[i] += x[i] * x[i];
}
class Particle {
public:
double *x;
double *v;
double fitness;
double pBest;
double *xBest;
};
class Swarm {
private:
int gBest; //index
double gBestValue;
public:
Particle *P;
Swarm();
void setGBestIndex(int index);
void setGBestValue(double gBestValue);
void setParticleXV(int i, int j, double x, double v);
void setParticleFitness(int i, double fit);
void setParticlePBest(int i, double value, double *x);
Particle getParticleValue(int i);
int getGbest();
double getGbestValue();
};
Swarm::Swarm() {
gBest = 0;
P = (Particle *)malloc(sizeof(Particle)*Nparticles);
if (P==NULL) {
fprintf(stderr, "Cannot allocate memory for %d Particles\n", Nparticles);
exit (1);
}
for(int i = 0; i < Nparticles; i++) {
P[i].x = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].x==NULL) {
fprintf(stderr, "Cannot allocate memory for %d x\n", Nvariables);
exit (1);
}
P[i].v = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].v==NULL) {
fprintf(stderr, "Cannot allocate memory for %d v\n", Nvariables);
exit (1);
}
P[i].xBest = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].xBest==NULL) {
fprintf(stderr, "Cannot allocate memory for %d xBest\n", Nvariables);
exit (1);
}
}
}
void Swarm::setGBestIndex(int index) {
this->gBest = index;
}
void Swarm::setGBestValue(double gBestValue) {
this->gBestValue = gBestValue;
}
void Swarm::setParticleXV(int i, int j, double x, double v) {
if (x != NULL) P[i].x[j] = x;
if (v != NULL) P[i].v[j] = v;
}
void Swarm::setParticleFitness(int i, double fit) {
P[i].fitness = fit;
}
void Swarm::setParticlePBest(int i, double value, double *x) {
P[i].pBest = value;
for(int j = 0; j < Nvariables; j++)
{
P[i].xBest[j] = P[i].x[j];
}
}
Particle Swarm::getParticleValue(int i) {
return P[i];
}
int Swarm::getGbest() {
return gBest;
}
double Swarm::getGbestValue() {
return gBestValue;
}
class PSO {
private:
int nfc;
double w;
double *maxV;
public:
Swarm swarm;
PSO();
void initialize();
void evolution();
void updateBest(int i);
void calculateVMax();
void particleMovement();
void evaluate(int i);
void evaluateSwarm();
};
PSO::PSO() {
maxV = (double *)malloc(sizeof(double)*Nvariables);
if (maxV==NULL) {
fprintf(stderr, "Cannot allocate memory for %d maxV\n", Nvariables);
exit (1);
}
}
void PSO::evolution() {
double dw = (W_0 - W_T) / (NFC_MAX / Nparticles);
w = W_0;
initialize();
nfc = 0;
while(nfc < NFC_MAX) {
calculateVMax();
particleMovement();
evaluateSwarm();
w -= dw;
}
}
void PSO::initialize() {
swarm.setGBestValue(numeric_limits<double>::max());
for(int i = 0; i < Nparticles; i++) {
for(int j = 0; j < Nvariables; j++) {
double x = -5.12 + 10.24 * Rand();
//double x = Rand();
double v = 0.0;
swarm.setParticleXV(i, j, x, v);
}
evaluate(i);
updateBest(i);
double fitness = swarm.getParticleValue(i).fitness;
double gbest = swarm.getGbestValue();
if (fitness < gbest) {
swarm.setGBestValue(fitness);
swarm.setGBestIndex(i);
}
}
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("0 : ");
for (int j = 0; j < Nvariables; j++)
printf("%g ", best.xBest[j]);
printf(" = %e\n", best.pBest);
}
void PSO::evaluate(int i) {
//int index = i;
int ThreadsInBlock = 8;
int BlocksInGrid = (int)(Nvariables + ThreadsInBlock - 1) / ThreadsInBlock;
double *fitness = (double *)malloc(sizeof(double));
cudaMallocManaged((void **)&fitness, sizeof(double));
cudaMallocManaged((void **)&swarm.P[i].x, sizeof(double)*Nvariables);
evalPlane<<<BlocksInGrid, ThreadsInBlock>>>(Nvariables, swarm.P[i].x, fitness);
cudaGetLastError();
//if (cudaSuccess != cudaMemcpy())
cudaDeviceSynchronize();
// double fitness = 0.0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// int x = swarm.getParticleValue(index).x[k];
// fitness += x * x;
// }
// double fitness = 0, temp = 0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// for(int l = 0; l < k; l++)
// {
// double x = swarm.getParticleValue(index).x[l];
// temp += x;
// }
// fitness += temp * temp;
// }
cudaFree(fitness);
cudaFree(swarm.P[i].x);
//swarm.setParticleFitness(index, fitness);
}
void PSO::evaluateSwarm() {
for(int i = 0; i < Nparticles; i++) {
evaluate(i);
nfc++;
if (nfc % 5000 == 0) {
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("%d : ", nfc);
// for (int j = 0; j < Nvariables; j++)
// printf("%g ", best.xBest[j]);
printf(" = %g\n", best.pBest);
//cout << "PSO SPHERE nfc" << nfc << " \tbestfit " << best.pBest << "\n";
}
}
for(int n = 0; n < Nparticles; n++) {
Particle par = swarm.getParticleValue(n);
if (par.fitness < par.pBest ) {
swarm.setParticlePBest(n, par.fitness, par.x);
if (par.fitness < swarm.getGbestValue() ) {
swarm.setGBestIndex(n);
swarm.setGBestValue(par.fitness);
}
}
}
}
void PSO::updateBest(int i) {
Particle par = swarm.getParticleValue(i);
swarm.setParticlePBest(i, par.fitness, par.x);
}
void PSO::calculateVMax() {
double xmin[Nparticles], xmax[Nparticles];
for (int d = 0; d < Nvariables; d++) {
xmin[d] = xmax[d] = swarm.getParticleValue(0).x[d];
for (int n = 1; n < Nparticles; n++) {
double pos = swarm.getParticleValue(n).x[d];
if (pos < xmin[d])
xmin[d] = pos;
if (pos > xmax[d])
xmax[d] = pos;
}
maxV[d] = xmax[d] - xmin[d];
}
}
void PSO::particleMovement() {
int n, d;
for (n = 0; n < Nparticles ; n++) {
Particle par = swarm.getParticleValue(n);
Particle bPar = swarm.getParticleValue(swarm.getGbest());
// update velocities
for(d = 0; d < Nvariables ; d++ ) {
double r1 = Rand();
double r2 = Rand();
double newV = w * par.v[d] + c1 * r1 * (par.xBest[d] - par.x[d]) + c2 * r2 * (bPar.x[d] - par.x[d]);
swarm.setParticleXV(n, d, NULL, newV);
// check v with its dimensional maxV
if ( swarm.getParticleValue(n).v[d] > maxV[d] ) swarm.setParticleXV(n, d, NULL, maxV[d]);
else if ( swarm.getParticleValue(n).v[d] < -maxV[d] ) swarm.setParticleXV(n, d, NULL, -maxV[d]);
}
// update positions
Particle newPar = swarm.getParticleValue(n);
for (d = 0; d < Nvariables ; d++) {
//newPar.x[d] = newPar.x[d] + newPar.v[d];
swarm.setParticleXV(n, d, newPar.x[d] + newPar.v[d], NULL);
}
}
}
int main(int argc, char **argv) {
//int threadCount = BlocksInGrid * ThreadsInBlock;
//long size = threadCount * sizeof(double);
PSO pso;
pso.evolution();
return 0;
} | .file "tmpxft_00139421_00000000-6_CUDA_BPSO.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3693:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3693:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Cannot allocate memory for %d Particles\n"
.align 8
.LC1:
.string "Cannot allocate memory for %d x\n"
.align 8
.LC2:
.string "Cannot allocate memory for %d v\n"
.align 8
.LC3:
.string "Cannot allocate memory for %d xBest\n"
.text
.align 2
.globl _ZN5SwarmC2Ev
.type _ZN5SwarmC2Ev, @function
_ZN5SwarmC2Ev:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl $0, (%rdi)
movl $1200, %edi
call malloc@PLT
movq %rax, 16(%rbx)
testq %rax, %rax
je .L11
movq %rax, %rbx
leaq 1200(%rax), %rbp
.L8:
movl $240, %edi
call malloc@PLT
movq %rax, (%rbx)
testq %rax, %rax
je .L12
movl $240, %edi
call malloc@PLT
movq %rax, 8(%rbx)
testq %rax, %rax
je .L13
movl $240, %edi
call malloc@PLT
movq %rax, 32(%rbx)
testq %rax, %rax
je .L14
addq $40, %rbx
cmpq %rbp, %rbx
jne .L8
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
movl $30, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movl $30, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L13:
movl $30, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
movl $30, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _ZN5SwarmC2Ev, .-_ZN5SwarmC2Ev
.globl _ZN5SwarmC1Ev
.set _ZN5SwarmC1Ev,_ZN5SwarmC2Ev
.align 2
.globl _ZN5Swarm13setGBestIndexEi
.type _ZN5Swarm13setGBestIndexEi, @function
_ZN5Swarm13setGBestIndexEi:
.LFB3672:
.cfi_startproc
endbr64
movl %esi, (%rdi)
ret
.cfi_endproc
.LFE3672:
.size _ZN5Swarm13setGBestIndexEi, .-_ZN5Swarm13setGBestIndexEi
.align 2
.globl _ZN5Swarm13setGBestValueEd
.type _ZN5Swarm13setGBestValueEd, @function
_ZN5Swarm13setGBestValueEd:
.LFB3673:
.cfi_startproc
endbr64
movsd %xmm0, 8(%rdi)
ret
.cfi_endproc
.LFE3673:
.size _ZN5Swarm13setGBestValueEd, .-_ZN5Swarm13setGBestValueEd
.align 2
.globl _ZN5Swarm13setParticleXVEiidd
.type _ZN5Swarm13setParticleXVEiidd, @function
_ZN5Swarm13setParticleXVEiidd:
.LFB3674:
.cfi_startproc
endbr64
movq %rdi, %rcx
movl %esi, %eax
pxor %xmm2, %xmm2
ucomisd %xmm2, %xmm0
jp .L22
jne .L22
.L18:
pxor %xmm0, %xmm0
ucomisd %xmm0, %xmm1
jp .L23
jne .L23
.L17:
ret
.L22:
movslq %eax, %rsi
leaq (%rsi,%rsi,4), %rsi
salq $3, %rsi
addq 16(%rcx), %rsi
movslq %edx, %rdi
movq (%rsi), %r8
movsd %xmm0, (%r8,%rdi,8)
jmp .L18
.L23:
cltq
leaq (%rax,%rax,4), %rax
salq $3, %rax
addq 16(%rcx), %rax
movslq %edx, %rdx
movq 8(%rax), %rax
movsd %xmm1, (%rax,%rdx,8)
ret
.cfi_endproc
.LFE3674:
.size _ZN5Swarm13setParticleXVEiidd, .-_ZN5Swarm13setParticleXVEiidd
.align 2
.globl _ZN5Swarm18setParticleFitnessEid
.type _ZN5Swarm18setParticleFitnessEid, @function
_ZN5Swarm18setParticleFitnessEid:
.LFB3675:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rsi,%rsi,4), %rax
salq $3, %rax
addq 16(%rdi), %rax
movsd %xmm0, 16(%rax)
ret
.cfi_endproc
.LFE3675:
.size _ZN5Swarm18setParticleFitnessEid, .-_ZN5Swarm18setParticleFitnessEid
.align 2
.globl _ZN5Swarm16setParticlePBestEidPd
.type _ZN5Swarm16setParticlePBestEidPd, @function
_ZN5Swarm16setParticlePBestEidPd:
.LFB3676:
.cfi_startproc
endbr64
movslq %esi, %rsi
leaq (%rsi,%rsi,4), %rsi
salq $3, %rsi
movq 16(%rdi), %rax
movsd %xmm0, 24(%rax,%rsi)
movl $0, %eax
.L26:
movq %rsi, %rdx
addq 16(%rdi), %rdx
movq (%rdx), %rcx
movsd (%rcx,%rax), %xmm0
movq 32(%rdx), %rdx
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq $240, %rax
jne .L26
ret
.cfi_endproc
.LFE3676:
.size _ZN5Swarm16setParticlePBestEidPd, .-_ZN5Swarm16setParticlePBestEidPd
.align 2
.globl _ZN5Swarm16getParticleValueEi
.type _ZN5Swarm16getParticleValueEi, @function
_ZN5Swarm16getParticleValueEi:
.LFB3677:
.cfi_startproc
endbr64
movq %rdi, %rax
movslq %edx, %rdx
leaq (%rdx,%rdx,4), %rdx
salq $3, %rdx
addq 16(%rsi), %rdx
movdqu (%rdx), %xmm0
movups %xmm0, (%rdi)
movdqu 16(%rdx), %xmm1
movups %xmm1, 16(%rdi)
movq 32(%rdx), %rdx
movq %rdx, 32(%rdi)
ret
.cfi_endproc
.LFE3677:
.size _ZN5Swarm16getParticleValueEi, .-_ZN5Swarm16getParticleValueEi
.align 2
.globl _ZN5Swarm8getGbestEv
.type _ZN5Swarm8getGbestEv, @function
_ZN5Swarm8getGbestEv:
.LFB3678:
.cfi_startproc
endbr64
movl (%rdi), %eax
ret
.cfi_endproc
.LFE3678:
.size _ZN5Swarm8getGbestEv, .-_ZN5Swarm8getGbestEv
.align 2
.globl _ZN5Swarm13getGbestValueEv
.type _ZN5Swarm13getGbestValueEv, @function
_ZN5Swarm13getGbestValueEv:
.LFB3679:
.cfi_startproc
endbr64
movsd 8(%rdi), %xmm0
ret
.cfi_endproc
.LFE3679:
.size _ZN5Swarm13getGbestValueEv, .-_ZN5Swarm13getGbestValueEv
.section .rodata.str1.8
.align 8
.LC5:
.string "Cannot allocate memory for %d maxV\n"
.text
.align 2
.globl _ZN3PSOC2Ev
.type _ZN3PSOC2Ev, @function
_ZN3PSOC2Ev:
.LFB3681:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
leaq 24(%rdi), %rdi
call _ZN5SwarmC1Ev
movl $240, %edi
call malloc@PLT
movq %rax, 16(%rbx)
testq %rax, %rax
je .L34
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl $30, %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3681:
.size _ZN3PSOC2Ev, .-_ZN3PSOC2Ev
.globl _ZN3PSOC1Ev
.set _ZN3PSOC1Ev,_ZN3PSOC2Ev
.align 2
.globl _ZN3PSO10updateBestEi
.type _ZN3PSO10updateBestEi, @function
_ZN3PSO10updateBestEi:
.LFB3687:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rdi), %rbx
movq %rsp, %rdi
movl %esi, %edx
movq %rbx, %rsi
call _ZN5Swarm16getParticleValueEi
movq (%rsp), %rdx
movsd 16(%rsp), %xmm0
movl %ebp, %esi
movq %rbx, %rdi
call _ZN5Swarm16setParticlePBestEidPd
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3687:
.size _ZN3PSO10updateBestEi, .-_ZN3PSO10updateBestEi
.align 2
.globl _ZN3PSO13calculateVMaxEv
.type _ZN3PSO13calculateVMaxEv, @function
_ZN3PSO13calculateVMaxEv:
.LFB3688:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $600, %rsp
.cfi_def_cfa_offset 656
movq %rdi, 24(%rsp)
movq %fs:40, %rax
movq %rax, 584(%rsp)
xorl %eax, %eax
leaq 336(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 336(%rsp), %rcx
movq %rcx, 40(%rsp)
movq %rax, 8(%rsp)
leaq 48(%rsp), %r15
jmp .L43
.L41:
movsd %xmm0, (%r12)
addl $1, %ebx
cmpl $30, %ebx
je .L49
.L42:
movl %ebx, %edx
movq %r14, %rsi
movq %r15, %rdi
call _ZN5Swarm16getParticleValueEi
movq 48(%rsp), %rax
movsd (%rax,%r13), %xmm0
movsd 0(%rbp), %xmm2
movapd %xmm0, %xmm1
comisd %xmm0, %xmm2
ja .L40
movapd %xmm2, %xmm1
.L40:
movsd %xmm1, 0(%rbp)
comisd (%r12), %xmm0
ja .L41
movsd (%r12), %xmm0
jmp .L41
.L49:
movq 24(%rsp), %rax
movq 16(%rax), %rax
subsd 0(%rbp), %xmm0
movsd %xmm0, (%rax,%r13)
addq $8, 16(%rsp)
addq $8, 8(%rsp)
movq 8(%rsp), %rax
movq 40(%rsp), %rcx
cmpq %rcx, %rax
je .L50
.L43:
movq 24(%rsp), %rax
leaq 24(%rax), %r14
movl $0, %edx
movq %r14, %rsi
movq %r15, %rdi
call _ZN5Swarm16getParticleValueEi
movq 8(%rsp), %rcx
movq %rcx, %r13
movq 32(%rsp), %rax
subq %rax, %r13
movq 48(%rsp), %rax
movsd (%rax,%r13), %xmm0
movq 16(%rsp), %rax
movq %rax, %r12
movsd %xmm0, (%rax)
movq %rcx, %rbp
movsd %xmm0, (%rcx)
movl $1, %ebx
jmp .L42
.L50:
movq 584(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $600, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3688:
.size _ZN3PSO13calculateVMaxEv, .-_ZN3PSO13calculateVMaxEv
.align 2
.globl _ZN3PSO16particleMovementEv
.type _ZN3PSO16particleMovementEv, @function
_ZN3PSO16particleMovementEv:
.LFB3689:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rdi, %r14
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0, %r12d
leaq 24(%rdi), %r13
leaq 112(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L59
.L69:
movapd %xmm3, %xmm1
pxor %xmm0, %xmm0
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _ZN5Swarm13setParticleXVEiidd
.L55:
addq $1, %rbx
cmpq $30, %rbx
je .L68
.L57:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
movsd %xmm0, (%rsp)
call rand@PLT
movsd (%r15,%rbx,8), %xmm2
movq 48(%rsp), %rdx
movsd (%rdx,%rbx,8), %xmm0
subsd %xmm2, %xmm0
movsd (%rsp), %xmm1
addsd %xmm1, %xmm1
mulsd %xmm1, %xmm0
movq 24(%rsp), %rdx
movsd (%rdx,%rbx,8), %xmm1
mulsd 8(%r14), %xmm1
addsd %xmm1, %xmm0
movq 64(%rsp), %rdx
movsd (%rdx,%rbx,8), %xmm1
subsd %xmm2, %xmm1
pxor %xmm2, %xmm2
cvtsi2sdl %eax, %xmm2
divsd .LC6(%rip), %xmm2
addsd %xmm2, %xmm2
mulsd %xmm2, %xmm1
addsd %xmm0, %xmm1
pxor %xmm0, %xmm0
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _ZN5Swarm13setParticleXVEiidd
movl %r12d, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call _ZN5Swarm16getParticleValueEi
movq 120(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0
movq 16(%r14), %rax
movsd (%rax,%rbx,8), %xmm3
movsd %xmm3, (%rsp)
comisd %xmm3, %xmm0
ja .L69
movl %r12d, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call _ZN5Swarm16getParticleValueEi
movsd (%rsp), %xmm1
xorpd .LC7(%rip), %xmm1
movq 120(%rsp), %rax
comisd (%rax,%rbx,8), %xmm1
jbe .L55
pxor %xmm0, %xmm0
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _ZN5Swarm13setParticleXVEiidd
jmp .L55
.L68:
movl %r12d, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call _ZN5Swarm16getParticleValueEi
movl $0, %ebx
.L58:
movq 112(%rsp), %rax
movsd (%rax,%rbx,8), %xmm0
movq 120(%rsp), %rax
addsd (%rax,%rbx,8), %xmm0
pxor %xmm1, %xmm1
movl %ebx, %edx
movl %r12d, %esi
movq %r13, %rdi
call _ZN5Swarm13setParticleXVEiidd
addq $1, %rbx
cmpq $30, %rbx
jne .L58
addl $1, %r12d
cmpl $30, %r12d
je .L70
.L59:
leaq 16(%rsp), %rdi
movl %r12d, %edx
movq %r13, %rsi
call _ZN5Swarm16getParticleValueEi
movq 16(%rsp), %r15
leaq 64(%rsp), %rdi
movl 24(%r14), %edx
movq %r13, %rsi
call _ZN5Swarm16getParticleValueEi
movl $0, %ebx
jmp .L57
.L70:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L71
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3689:
.size _ZN3PSO16particleMovementEv, .-_ZN3PSO16particleMovementEv
.globl _Z31__device_stub__Z9evalPlaneiPdS_iPdS_
.type _Z31__device_stub__Z9evalPlaneiPdS_iPdS_, @function
_Z31__device_stub__Z9evalPlaneiPdS_iPdS_:
.LFB3715:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L76
.L72:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9evalPlaneiPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L72
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3715:
.size _Z31__device_stub__Z9evalPlaneiPdS_iPdS_, .-_Z31__device_stub__Z9evalPlaneiPdS_iPdS_
.globl _Z9evalPlaneiPdS_
.type _Z9evalPlaneiPdS_, @function
_Z9evalPlaneiPdS_:
.LFB3716:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9evalPlaneiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3716:
.size _Z9evalPlaneiPdS_, .-_Z9evalPlaneiPdS_
.align 2
.globl _ZN3PSO8evaluateEi
.type _ZN3PSO8evaluateEi, @function
_ZN3PSO8evaluateEi:
.LFB3685:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 8(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
movslq %ebx, %rsi
leaq (%rsi,%rsi,4), %rbx
salq $3, %rbx
movq %rbx, %rdi
addq 40(%rbp), %rdi
movl $1, %edx
movl $240, %esi
call cudaMallocManaged@PLT
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L81:
call cudaGetLastError@PLT
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rbp), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L85
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L84:
.cfi_restore_state
movq 40(%rbp), %rax
movq (%rax,%rbx), %rsi
movq 8(%rsp), %rdx
movl $30, %edi
call _Z31__device_stub__Z9evalPlaneiPdS_iPdS_
jmp .L81
.L85:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3685:
.size _ZN3PSO8evaluateEi, .-_ZN3PSO8evaluateEi
.section .rodata.str1.1,"aMS",@progbits,1
.LC11:
.string "0 : "
.LC12:
.string "%g "
.LC13:
.string " = %e\n"
.text
.align 2
.globl _ZN3PSO10initializeEv
.type _ZN3PSO10initializeEv, @function
_ZN3PSO10initializeEv:
.LFB3684:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 24(%rdi), %r12
movq .LC8(%rip), %rax
movq %rax, 32(%rdi)
movl $0, %ebp
movq %rsp, %r14
jmp .L87
.L89:
addl $1, %ebp
cmpl $30, %ebp
je .L91
.L87:
movl $0, %ebx
.L88:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
mulsd .LC9(%rip), %xmm0
subsd .LC10(%rip), %xmm0
pxor %xmm1, %xmm1
movl %ebx, %edx
movl %ebp, %esi
movq %r12, %rdi
call _ZN5Swarm13setParticleXVEiidd
addl $1, %ebx
cmpl $30, %ebx
jne .L88
movl %ebp, %esi
movq %r13, %rdi
call _ZN3PSO8evaluateEi
movl %ebp, %esi
movq %r13, %rdi
call _ZN3PSO10updateBestEi
movl %ebp, %edx
movq %r12, %rsi
movq %r14, %rdi
call _ZN5Swarm16getParticleValueEi
movsd 16(%rsp), %xmm0
movsd 32(%r13), %xmm1
comisd %xmm0, %xmm1
jbe .L89
movsd %xmm0, 32(%r13)
movl %ebp, 24(%r13)
jmp .L89
.L91:
movq %rsp, %rdi
movl 24(%r13), %edx
movq %r12, %rsi
call _ZN5Swarm16getParticleValueEi
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L92:
movq 32(%rsp), %rax
movsd (%rax,%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq $240, %rbx
jne .L92
movsd 24(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L98
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3684:
.size _ZN3PSO10initializeEv, .-_ZN3PSO10initializeEv
.section .rodata.str1.1
.LC14:
.string "%d : "
.LC15:
.string " = %g\n"
.text
.align 2
.globl _ZN3PSO13evaluateSwarmEv
.type _ZN3PSO13evaluateSwarmEv, @function
_ZN3PSO13evaluateSwarmEv:
.LFB3686:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %r12d
movq %rsp, %r15
leaq 24(%rdi), %r14
leaq .LC14(%rip), %r13
jmp .L101
.L100:
addl $1, %r12d
cmpl $30, %r12d
je .L112
.L101:
movl %r12d, %esi
movq %rbp, %rdi
call _ZN3PSO8evaluateEi
movl 0(%rbp), %eax
leal 1(%rax), %ebx
movl %ebx, 0(%rbp)
movslq %ebx, %rax
imulq $1759218605, %rax, %rax
sarq $43, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $5000, %eax, %eax
cmpl %eax, %ebx
jne .L100
movl 24(%rbp), %edx
movq %r14, %rsi
movq %r15, %rdi
call _ZN5Swarm16getParticleValueEi
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L100
.L112:
movl $0, %ebx
leaq 24(%rbp), %r13
jmp .L105
.L114:
movl %ebx, 24(%rbp)
movq %r12, 32(%rbp)
.L102:
addl $1, %ebx
cmpl $30, %ebx
je .L113
.L105:
movq %rsp, %rdi
movl %ebx, %edx
movq %r13, %rsi
call _ZN5Swarm16getParticleValueEi
movq 16(%rsp), %r12
movsd 24(%rsp), %xmm0
movq %r12, %xmm1
comisd %xmm1, %xmm0
jbe .L102
movq (%rsp), %rdx
movq %r12, %xmm0
movl %ebx, %esi
movq %r13, %rdi
call _ZN5Swarm16setParticlePBestEidPd
movsd 32(%rbp), %xmm0
movq %r12, %xmm2
comisd %xmm2, %xmm0
jbe .L102
jmp .L114
.L113:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L115
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L115:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3686:
.size _ZN3PSO13evaluateSwarmEv, .-_ZN3PSO13evaluateSwarmEv
.align 2
.globl _ZN3PSO9evolutionEv
.type _ZN3PSO9evolutionEv, @function
_ZN3PSO9evolutionEv:
.LFB3683:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq .LC16(%rip), %rax
movq %rax, 8(%rdi)
call _ZN3PSO10initializeEv
movl $0, (%rbx)
.L117:
movq %rbx, %rdi
call _ZN3PSO13calculateVMaxEv
movq %rbx, %rdi
call _ZN3PSO16particleMovementEv
movq %rbx, %rdi
call _ZN3PSO13evaluateSwarmEv
movsd 8(%rbx), %xmm0
subsd .LC17(%rip), %xmm0
movsd %xmm0, 8(%rbx)
cmpl $999999, (%rbx)
jle .L117
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3683:
.size _ZN3PSO9evolutionEv, .-_ZN3PSO9evolutionEv
.globl main
.type main, @function
main:
.LFB3690:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movq %rbx, %rdi
call _ZN3PSOC1Ev
movq %rbx, %rdi
call _ZN3PSO9evolutionEv
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L123
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L123:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3690:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z9evalPlaneiPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3718:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z9evalPlaneiPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3718:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -4194304
.long 1105199103
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC7:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC8:
.long -1
.long 2146435071
.align 8
.LC9:
.long 1202590843
.long 1076132577
.align 8
.LC10:
.long 1202590843
.long 1075084001
.align 8
.LC16:
.long -858993459
.long 1072483532
.align 8
.LC17:
.long -351632489
.long 1055880484
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <limits>
using namespace std;
#define Nparticles 30
#define T_MAX 1000
#define NFC_MAX 1000000
#define W_0 0.9
#define W_T 0.4
#define MAX_V 2.0
#define c1 2.0
#define c2 2.0
#define Nvariables 30
#define Rand() ((double)rand()/RAND_MAX);
__global__ void evalPlane(int n, double *x, double *fit) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
fit[i] += x[i] * x[i];
}
class Particle {
public:
double *x;
double *v;
double fitness;
double pBest;
double *xBest;
};
class Swarm {
private:
int gBest; //index
double gBestValue;
public:
Particle *P;
Swarm();
void setGBestIndex(int index);
void setGBestValue(double gBestValue);
void setParticleXV(int i, int j, double x, double v);
void setParticleFitness(int i, double fit);
void setParticlePBest(int i, double value, double *x);
Particle getParticleValue(int i);
int getGbest();
double getGbestValue();
};
Swarm::Swarm() {
gBest = 0;
P = (Particle *)malloc(sizeof(Particle)*Nparticles);
if (P==NULL) {
fprintf(stderr, "Cannot allocate memory for %d Particles\n", Nparticles);
exit (1);
}
for(int i = 0; i < Nparticles; i++) {
P[i].x = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].x==NULL) {
fprintf(stderr, "Cannot allocate memory for %d x\n", Nvariables);
exit (1);
}
P[i].v = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].v==NULL) {
fprintf(stderr, "Cannot allocate memory for %d v\n", Nvariables);
exit (1);
}
P[i].xBest = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].xBest==NULL) {
fprintf(stderr, "Cannot allocate memory for %d xBest\n", Nvariables);
exit (1);
}
}
}
void Swarm::setGBestIndex(int index) {
this->gBest = index;
}
void Swarm::setGBestValue(double gBestValue) {
this->gBestValue = gBestValue;
}
void Swarm::setParticleXV(int i, int j, double x, double v) {
if (x != NULL) P[i].x[j] = x;
if (v != NULL) P[i].v[j] = v;
}
void Swarm::setParticleFitness(int i, double fit) {
P[i].fitness = fit;
}
void Swarm::setParticlePBest(int i, double value, double *x) {
P[i].pBest = value;
for(int j = 0; j < Nvariables; j++)
{
P[i].xBest[j] = P[i].x[j];
}
}
Particle Swarm::getParticleValue(int i) {
return P[i];
}
int Swarm::getGbest() {
return gBest;
}
double Swarm::getGbestValue() {
return gBestValue;
}
class PSO {
private:
int nfc;
double w;
double *maxV;
public:
Swarm swarm;
PSO();
void initialize();
void evolution();
void updateBest(int i);
void calculateVMax();
void particleMovement();
void evaluate(int i);
void evaluateSwarm();
};
PSO::PSO() {
maxV = (double *)malloc(sizeof(double)*Nvariables);
if (maxV==NULL) {
fprintf(stderr, "Cannot allocate memory for %d maxV\n", Nvariables);
exit (1);
}
}
void PSO::evolution() {
double dw = (W_0 - W_T) / (NFC_MAX / Nparticles);
w = W_0;
initialize();
nfc = 0;
while(nfc < NFC_MAX) {
calculateVMax();
particleMovement();
evaluateSwarm();
w -= dw;
}
}
void PSO::initialize() {
swarm.setGBestValue(numeric_limits<double>::max());
for(int i = 0; i < Nparticles; i++) {
for(int j = 0; j < Nvariables; j++) {
double x = -5.12 + 10.24 * Rand();
//double x = Rand();
double v = 0.0;
swarm.setParticleXV(i, j, x, v);
}
evaluate(i);
updateBest(i);
double fitness = swarm.getParticleValue(i).fitness;
double gbest = swarm.getGbestValue();
if (fitness < gbest) {
swarm.setGBestValue(fitness);
swarm.setGBestIndex(i);
}
}
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("0 : ");
for (int j = 0; j < Nvariables; j++)
printf("%g ", best.xBest[j]);
printf(" = %e\n", best.pBest);
}
void PSO::evaluate(int i) {
//int index = i;
int ThreadsInBlock = 8;
int BlocksInGrid = (int)(Nvariables + ThreadsInBlock - 1) / ThreadsInBlock;
double *fitness = (double *)malloc(sizeof(double));
cudaMallocManaged((void **)&fitness, sizeof(double));
cudaMallocManaged((void **)&swarm.P[i].x, sizeof(double)*Nvariables);
evalPlane<<<BlocksInGrid, ThreadsInBlock>>>(Nvariables, swarm.P[i].x, fitness);
cudaGetLastError();
//if (cudaSuccess != cudaMemcpy())
cudaDeviceSynchronize();
// double fitness = 0.0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// int x = swarm.getParticleValue(index).x[k];
// fitness += x * x;
// }
// double fitness = 0, temp = 0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// for(int l = 0; l < k; l++)
// {
// double x = swarm.getParticleValue(index).x[l];
// temp += x;
// }
// fitness += temp * temp;
// }
cudaFree(fitness);
cudaFree(swarm.P[i].x);
//swarm.setParticleFitness(index, fitness);
}
void PSO::evaluateSwarm() {
for(int i = 0; i < Nparticles; i++) {
evaluate(i);
nfc++;
if (nfc % 5000 == 0) {
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("%d : ", nfc);
// for (int j = 0; j < Nvariables; j++)
// printf("%g ", best.xBest[j]);
printf(" = %g\n", best.pBest);
//cout << "PSO SPHERE nfc" << nfc << " \tbestfit " << best.pBest << "\n";
}
}
for(int n = 0; n < Nparticles; n++) {
Particle par = swarm.getParticleValue(n);
if (par.fitness < par.pBest ) {
swarm.setParticlePBest(n, par.fitness, par.x);
if (par.fitness < swarm.getGbestValue() ) {
swarm.setGBestIndex(n);
swarm.setGBestValue(par.fitness);
}
}
}
}
void PSO::updateBest(int i) {
Particle par = swarm.getParticleValue(i);
swarm.setParticlePBest(i, par.fitness, par.x);
}
void PSO::calculateVMax() {
double xmin[Nparticles], xmax[Nparticles];
for (int d = 0; d < Nvariables; d++) {
xmin[d] = xmax[d] = swarm.getParticleValue(0).x[d];
for (int n = 1; n < Nparticles; n++) {
double pos = swarm.getParticleValue(n).x[d];
if (pos < xmin[d])
xmin[d] = pos;
if (pos > xmax[d])
xmax[d] = pos;
}
maxV[d] = xmax[d] - xmin[d];
}
}
void PSO::particleMovement() {
int n, d;
for (n = 0; n < Nparticles ; n++) {
Particle par = swarm.getParticleValue(n);
Particle bPar = swarm.getParticleValue(swarm.getGbest());
// update velocities
for(d = 0; d < Nvariables ; d++ ) {
double r1 = Rand();
double r2 = Rand();
double newV = w * par.v[d] + c1 * r1 * (par.xBest[d] - par.x[d]) + c2 * r2 * (bPar.x[d] - par.x[d]);
swarm.setParticleXV(n, d, NULL, newV);
// check v with its dimensional maxV
if ( swarm.getParticleValue(n).v[d] > maxV[d] ) swarm.setParticleXV(n, d, NULL, maxV[d]);
else if ( swarm.getParticleValue(n).v[d] < -maxV[d] ) swarm.setParticleXV(n, d, NULL, -maxV[d]);
}
// update positions
Particle newPar = swarm.getParticleValue(n);
for (d = 0; d < Nvariables ; d++) {
//newPar.x[d] = newPar.x[d] + newPar.v[d];
swarm.setParticleXV(n, d, newPar.x[d] + newPar.v[d], NULL);
}
}
}
int main(int argc, char **argv) {
//int threadCount = BlocksInGrid * ThreadsInBlock;
//long size = threadCount * sizeof(double);
PSO pso;
pso.evolution();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <limits>
using namespace std;
#define Nparticles 30
#define T_MAX 1000
#define NFC_MAX 1000000
#define W_0 0.9
#define W_T 0.4
#define MAX_V 2.0
#define c1 2.0
#define c2 2.0
#define Nvariables 30
#define Rand() ((double)rand()/RAND_MAX);
__global__ void evalPlane(int n, double *x, double *fit) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
fit[i] += x[i] * x[i];
}
class Particle {
public:
double *x;
double *v;
double fitness;
double pBest;
double *xBest;
};
class Swarm {
private:
int gBest; //index
double gBestValue;
public:
Particle *P;
Swarm();
void setGBestIndex(int index);
void setGBestValue(double gBestValue);
void setParticleXV(int i, int j, double x, double v);
void setParticleFitness(int i, double fit);
void setParticlePBest(int i, double value, double *x);
Particle getParticleValue(int i);
int getGbest();
double getGbestValue();
};
Swarm::Swarm() {
gBest = 0;
P = (Particle *)malloc(sizeof(Particle)*Nparticles);
if (P==NULL) {
fprintf(stderr, "Cannot allocate memory for %d Particles\n", Nparticles);
exit (1);
}
for(int i = 0; i < Nparticles; i++) {
P[i].x = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].x==NULL) {
fprintf(stderr, "Cannot allocate memory for %d x\n", Nvariables);
exit (1);
}
P[i].v = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].v==NULL) {
fprintf(stderr, "Cannot allocate memory for %d v\n", Nvariables);
exit (1);
}
P[i].xBest = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].xBest==NULL) {
fprintf(stderr, "Cannot allocate memory for %d xBest\n", Nvariables);
exit (1);
}
}
}
void Swarm::setGBestIndex(int index) {
this->gBest = index;
}
void Swarm::setGBestValue(double gBestValue) {
this->gBestValue = gBestValue;
}
void Swarm::setParticleXV(int i, int j, double x, double v) {
if (x != NULL) P[i].x[j] = x;
if (v != NULL) P[i].v[j] = v;
}
void Swarm::setParticleFitness(int i, double fit) {
P[i].fitness = fit;
}
void Swarm::setParticlePBest(int i, double value, double *x) {
P[i].pBest = value;
for(int j = 0; j < Nvariables; j++)
{
P[i].xBest[j] = P[i].x[j];
}
}
Particle Swarm::getParticleValue(int i) {
return P[i];
}
int Swarm::getGbest() {
return gBest;
}
double Swarm::getGbestValue() {
return gBestValue;
}
class PSO {
private:
int nfc;
double w;
double *maxV;
public:
Swarm swarm;
PSO();
void initialize();
void evolution();
void updateBest(int i);
void calculateVMax();
void particleMovement();
void evaluate(int i);
void evaluateSwarm();
};
PSO::PSO() {
maxV = (double *)malloc(sizeof(double)*Nvariables);
if (maxV==NULL) {
fprintf(stderr, "Cannot allocate memory for %d maxV\n", Nvariables);
exit (1);
}
}
void PSO::evolution() {
double dw = (W_0 - W_T) / (NFC_MAX / Nparticles);
w = W_0;
initialize();
nfc = 0;
while(nfc < NFC_MAX) {
calculateVMax();
particleMovement();
evaluateSwarm();
w -= dw;
}
}
void PSO::initialize() {
swarm.setGBestValue(numeric_limits<double>::max());
for(int i = 0; i < Nparticles; i++) {
for(int j = 0; j < Nvariables; j++) {
double x = -5.12 + 10.24 * Rand();
//double x = Rand();
double v = 0.0;
swarm.setParticleXV(i, j, x, v);
}
evaluate(i);
updateBest(i);
double fitness = swarm.getParticleValue(i).fitness;
double gbest = swarm.getGbestValue();
if (fitness < gbest) {
swarm.setGBestValue(fitness);
swarm.setGBestIndex(i);
}
}
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("0 : ");
for (int j = 0; j < Nvariables; j++)
printf("%g ", best.xBest[j]);
printf(" = %e\n", best.pBest);
}
void PSO::evaluate(int i) {
//int index = i;
int ThreadsInBlock = 8;
int BlocksInGrid = (int)(Nvariables + ThreadsInBlock - 1) / ThreadsInBlock;
double *fitness = (double *)malloc(sizeof(double));
hipMallocManaged((void **)&fitness, sizeof(double));
hipMallocManaged((void **)&swarm.P[i].x, sizeof(double)*Nvariables);
evalPlane<<<BlocksInGrid, ThreadsInBlock>>>(Nvariables, swarm.P[i].x, fitness);
hipGetLastError();
//if (cudaSuccess != cudaMemcpy())
hipDeviceSynchronize();
// double fitness = 0.0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// int x = swarm.getParticleValue(index).x[k];
// fitness += x * x;
// }
// double fitness = 0, temp = 0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// for(int l = 0; l < k; l++)
// {
// double x = swarm.getParticleValue(index).x[l];
// temp += x;
// }
// fitness += temp * temp;
// }
hipFree(fitness);
hipFree(swarm.P[i].x);
//swarm.setParticleFitness(index, fitness);
}
void PSO::evaluateSwarm() {
for(int i = 0; i < Nparticles; i++) {
evaluate(i);
nfc++;
if (nfc % 5000 == 0) {
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("%d : ", nfc);
// for (int j = 0; j < Nvariables; j++)
// printf("%g ", best.xBest[j]);
printf(" = %g\n", best.pBest);
//cout << "PSO SPHERE nfc" << nfc << " \tbestfit " << best.pBest << "\n";
}
}
for(int n = 0; n < Nparticles; n++) {
Particle par = swarm.getParticleValue(n);
if (par.fitness < par.pBest ) {
swarm.setParticlePBest(n, par.fitness, par.x);
if (par.fitness < swarm.getGbestValue() ) {
swarm.setGBestIndex(n);
swarm.setGBestValue(par.fitness);
}
}
}
}
void PSO::updateBest(int i) {
Particle par = swarm.getParticleValue(i);
swarm.setParticlePBest(i, par.fitness, par.x);
}
void PSO::calculateVMax() {
double xmin[Nparticles], xmax[Nparticles];
for (int d = 0; d < Nvariables; d++) {
xmin[d] = xmax[d] = swarm.getParticleValue(0).x[d];
for (int n = 1; n < Nparticles; n++) {
double pos = swarm.getParticleValue(n).x[d];
if (pos < xmin[d])
xmin[d] = pos;
if (pos > xmax[d])
xmax[d] = pos;
}
maxV[d] = xmax[d] - xmin[d];
}
}
void PSO::particleMovement() {
int n, d;
for (n = 0; n < Nparticles ; n++) {
Particle par = swarm.getParticleValue(n);
Particle bPar = swarm.getParticleValue(swarm.getGbest());
// update velocities
for(d = 0; d < Nvariables ; d++ ) {
double r1 = Rand();
double r2 = Rand();
double newV = w * par.v[d] + c1 * r1 * (par.xBest[d] - par.x[d]) + c2 * r2 * (bPar.x[d] - par.x[d]);
swarm.setParticleXV(n, d, NULL, newV);
// check v with its dimensional maxV
if ( swarm.getParticleValue(n).v[d] > maxV[d] ) swarm.setParticleXV(n, d, NULL, maxV[d]);
else if ( swarm.getParticleValue(n).v[d] < -maxV[d] ) swarm.setParticleXV(n, d, NULL, -maxV[d]);
}
// update positions
Particle newPar = swarm.getParticleValue(n);
for (d = 0; d < Nvariables ; d++) {
//newPar.x[d] = newPar.x[d] + newPar.v[d];
swarm.setParticleXV(n, d, newPar.x[d] + newPar.v[d], NULL);
}
}
}
int main(int argc, char **argv) {
//int threadCount = BlocksInGrid * ThreadsInBlock;
//long size = threadCount * sizeof(double);
PSO pso;
pso.evolution();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <limits>
using namespace std;
#define Nparticles 30
#define T_MAX 1000
#define NFC_MAX 1000000
#define W_0 0.9
#define W_T 0.4
#define MAX_V 2.0
#define c1 2.0
#define c2 2.0
#define Nvariables 30
#define Rand() ((double)rand()/RAND_MAX);
__global__ void evalPlane(int n, double *x, double *fit) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
fit[i] += x[i] * x[i];
}
class Particle {
public:
double *x;
double *v;
double fitness;
double pBest;
double *xBest;
};
class Swarm {
private:
int gBest; //index
double gBestValue;
public:
Particle *P;
Swarm();
void setGBestIndex(int index);
void setGBestValue(double gBestValue);
void setParticleXV(int i, int j, double x, double v);
void setParticleFitness(int i, double fit);
void setParticlePBest(int i, double value, double *x);
Particle getParticleValue(int i);
int getGbest();
double getGbestValue();
};
Swarm::Swarm() {
gBest = 0;
P = (Particle *)malloc(sizeof(Particle)*Nparticles);
if (P==NULL) {
fprintf(stderr, "Cannot allocate memory for %d Particles\n", Nparticles);
exit (1);
}
for(int i = 0; i < Nparticles; i++) {
P[i].x = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].x==NULL) {
fprintf(stderr, "Cannot allocate memory for %d x\n", Nvariables);
exit (1);
}
P[i].v = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].v==NULL) {
fprintf(stderr, "Cannot allocate memory for %d v\n", Nvariables);
exit (1);
}
P[i].xBest = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].xBest==NULL) {
fprintf(stderr, "Cannot allocate memory for %d xBest\n", Nvariables);
exit (1);
}
}
}
void Swarm::setGBestIndex(int index) {
this->gBest = index;
}
void Swarm::setGBestValue(double gBestValue) {
this->gBestValue = gBestValue;
}
void Swarm::setParticleXV(int i, int j, double x, double v) {
if (x != NULL) P[i].x[j] = x;
if (v != NULL) P[i].v[j] = v;
}
void Swarm::setParticleFitness(int i, double fit) {
P[i].fitness = fit;
}
void Swarm::setParticlePBest(int i, double value, double *x) {
P[i].pBest = value;
for(int j = 0; j < Nvariables; j++)
{
P[i].xBest[j] = P[i].x[j];
}
}
Particle Swarm::getParticleValue(int i) {
return P[i];
}
int Swarm::getGbest() {
return gBest;
}
double Swarm::getGbestValue() {
return gBestValue;
}
class PSO {
private:
int nfc;
double w;
double *maxV;
public:
Swarm swarm;
PSO();
void initialize();
void evolution();
void updateBest(int i);
void calculateVMax();
void particleMovement();
void evaluate(int i);
void evaluateSwarm();
};
PSO::PSO() {
maxV = (double *)malloc(sizeof(double)*Nvariables);
if (maxV==NULL) {
fprintf(stderr, "Cannot allocate memory for %d maxV\n", Nvariables);
exit (1);
}
}
void PSO::evolution() {
double dw = (W_0 - W_T) / (NFC_MAX / Nparticles);
w = W_0;
initialize();
nfc = 0;
while(nfc < NFC_MAX) {
calculateVMax();
particleMovement();
evaluateSwarm();
w -= dw;
}
}
void PSO::initialize() {
swarm.setGBestValue(numeric_limits<double>::max());
for(int i = 0; i < Nparticles; i++) {
for(int j = 0; j < Nvariables; j++) {
double x = -5.12 + 10.24 * Rand();
//double x = Rand();
double v = 0.0;
swarm.setParticleXV(i, j, x, v);
}
evaluate(i);
updateBest(i);
double fitness = swarm.getParticleValue(i).fitness;
double gbest = swarm.getGbestValue();
if (fitness < gbest) {
swarm.setGBestValue(fitness);
swarm.setGBestIndex(i);
}
}
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("0 : ");
for (int j = 0; j < Nvariables; j++)
printf("%g ", best.xBest[j]);
printf(" = %e\n", best.pBest);
}
void PSO::evaluate(int i) {
//int index = i;
int ThreadsInBlock = 8;
int BlocksInGrid = (int)(Nvariables + ThreadsInBlock - 1) / ThreadsInBlock;
double *fitness = (double *)malloc(sizeof(double));
hipMallocManaged((void **)&fitness, sizeof(double));
hipMallocManaged((void **)&swarm.P[i].x, sizeof(double)*Nvariables);
evalPlane<<<BlocksInGrid, ThreadsInBlock>>>(Nvariables, swarm.P[i].x, fitness);
hipGetLastError();
//if (cudaSuccess != cudaMemcpy())
hipDeviceSynchronize();
// double fitness = 0.0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// int x = swarm.getParticleValue(index).x[k];
// fitness += x * x;
// }
// double fitness = 0, temp = 0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// for(int l = 0; l < k; l++)
// {
// double x = swarm.getParticleValue(index).x[l];
// temp += x;
// }
// fitness += temp * temp;
// }
hipFree(fitness);
hipFree(swarm.P[i].x);
//swarm.setParticleFitness(index, fitness);
}
void PSO::evaluateSwarm() {
for(int i = 0; i < Nparticles; i++) {
evaluate(i);
nfc++;
if (nfc % 5000 == 0) {
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("%d : ", nfc);
// for (int j = 0; j < Nvariables; j++)
// printf("%g ", best.xBest[j]);
printf(" = %g\n", best.pBest);
//cout << "PSO SPHERE nfc" << nfc << " \tbestfit " << best.pBest << "\n";
}
}
for(int n = 0; n < Nparticles; n++) {
Particle par = swarm.getParticleValue(n);
if (par.fitness < par.pBest ) {
swarm.setParticlePBest(n, par.fitness, par.x);
if (par.fitness < swarm.getGbestValue() ) {
swarm.setGBestIndex(n);
swarm.setGBestValue(par.fitness);
}
}
}
}
void PSO::updateBest(int i) {
Particle par = swarm.getParticleValue(i);
swarm.setParticlePBest(i, par.fitness, par.x);
}
void PSO::calculateVMax() {
double xmin[Nparticles], xmax[Nparticles];
for (int d = 0; d < Nvariables; d++) {
xmin[d] = xmax[d] = swarm.getParticleValue(0).x[d];
for (int n = 1; n < Nparticles; n++) {
double pos = swarm.getParticleValue(n).x[d];
if (pos < xmin[d])
xmin[d] = pos;
if (pos > xmax[d])
xmax[d] = pos;
}
maxV[d] = xmax[d] - xmin[d];
}
}
void PSO::particleMovement() {
int n, d;
for (n = 0; n < Nparticles ; n++) {
Particle par = swarm.getParticleValue(n);
Particle bPar = swarm.getParticleValue(swarm.getGbest());
// update velocities
for(d = 0; d < Nvariables ; d++ ) {
double r1 = Rand();
double r2 = Rand();
double newV = w * par.v[d] + c1 * r1 * (par.xBest[d] - par.x[d]) + c2 * r2 * (bPar.x[d] - par.x[d]);
swarm.setParticleXV(n, d, NULL, newV);
// check v with its dimensional maxV
if ( swarm.getParticleValue(n).v[d] > maxV[d] ) swarm.setParticleXV(n, d, NULL, maxV[d]);
else if ( swarm.getParticleValue(n).v[d] < -maxV[d] ) swarm.setParticleXV(n, d, NULL, -maxV[d]);
}
// update positions
Particle newPar = swarm.getParticleValue(n);
for (d = 0; d < Nvariables ; d++) {
//newPar.x[d] = newPar.x[d] + newPar.v[d];
swarm.setParticleXV(n, d, newPar.x[d] + newPar.v[d], NULL);
}
}
}
int main(int argc, char **argv) {
//int threadCount = BlocksInGrid * ThreadsInBlock;
//long size = threadCount * sizeof(double);
PSO pso;
pso.evolution();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9evalPlaneiPdS_
.globl _Z9evalPlaneiPdS_
.p2align 8
.type _Z9evalPlaneiPdS_,@function
_Z9evalPlaneiPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[6:7], off
v_add_co_u32 v2, s0, v2, s8
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[4:5], v[4:5], v[8:9]
global_store_b64 v[6:7], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9evalPlaneiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9evalPlaneiPdS_, .Lfunc_end0-_Z9evalPlaneiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9evalPlaneiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9evalPlaneiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <limits>
using namespace std;
#define Nparticles 30
#define T_MAX 1000
#define NFC_MAX 1000000
#define W_0 0.9
#define W_T 0.4
#define MAX_V 2.0
#define c1 2.0
#define c2 2.0
#define Nvariables 30
#define Rand() ((double)rand()/RAND_MAX);
__global__ void evalPlane(int n, double *x, double *fit) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
fit[i] += x[i] * x[i];
}
class Particle {
public:
double *x;
double *v;
double fitness;
double pBest;
double *xBest;
};
class Swarm {
private:
int gBest; //index
double gBestValue;
public:
Particle *P;
Swarm();
void setGBestIndex(int index);
void setGBestValue(double gBestValue);
void setParticleXV(int i, int j, double x, double v);
void setParticleFitness(int i, double fit);
void setParticlePBest(int i, double value, double *x);
Particle getParticleValue(int i);
int getGbest();
double getGbestValue();
};
Swarm::Swarm() {
gBest = 0;
P = (Particle *)malloc(sizeof(Particle)*Nparticles);
if (P==NULL) {
fprintf(stderr, "Cannot allocate memory for %d Particles\n", Nparticles);
exit (1);
}
for(int i = 0; i < Nparticles; i++) {
P[i].x = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].x==NULL) {
fprintf(stderr, "Cannot allocate memory for %d x\n", Nvariables);
exit (1);
}
P[i].v = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].v==NULL) {
fprintf(stderr, "Cannot allocate memory for %d v\n", Nvariables);
exit (1);
}
P[i].xBest = (double *)malloc(sizeof(double)*Nvariables);
if (P[i].xBest==NULL) {
fprintf(stderr, "Cannot allocate memory for %d xBest\n", Nvariables);
exit (1);
}
}
}
void Swarm::setGBestIndex(int index) {
this->gBest = index;
}
void Swarm::setGBestValue(double gBestValue) {
this->gBestValue = gBestValue;
}
void Swarm::setParticleXV(int i, int j, double x, double v) {
if (x != NULL) P[i].x[j] = x;
if (v != NULL) P[i].v[j] = v;
}
void Swarm::setParticleFitness(int i, double fit) {
P[i].fitness = fit;
}
void Swarm::setParticlePBest(int i, double value, double *x) {
P[i].pBest = value;
for(int j = 0; j < Nvariables; j++)
{
P[i].xBest[j] = P[i].x[j];
}
}
Particle Swarm::getParticleValue(int i) {
return P[i];
}
int Swarm::getGbest() {
return gBest;
}
double Swarm::getGbestValue() {
return gBestValue;
}
class PSO {
private:
int nfc;
double w;
double *maxV;
public:
Swarm swarm;
PSO();
void initialize();
void evolution();
void updateBest(int i);
void calculateVMax();
void particleMovement();
void evaluate(int i);
void evaluateSwarm();
};
PSO::PSO() {
maxV = (double *)malloc(sizeof(double)*Nvariables);
if (maxV==NULL) {
fprintf(stderr, "Cannot allocate memory for %d maxV\n", Nvariables);
exit (1);
}
}
void PSO::evolution() {
double dw = (W_0 - W_T) / (NFC_MAX / Nparticles);
w = W_0;
initialize();
nfc = 0;
while(nfc < NFC_MAX) {
calculateVMax();
particleMovement();
evaluateSwarm();
w -= dw;
}
}
void PSO::initialize() {
swarm.setGBestValue(numeric_limits<double>::max());
for(int i = 0; i < Nparticles; i++) {
for(int j = 0; j < Nvariables; j++) {
double x = -5.12 + 10.24 * Rand();
//double x = Rand();
double v = 0.0;
swarm.setParticleXV(i, j, x, v);
}
evaluate(i);
updateBest(i);
double fitness = swarm.getParticleValue(i).fitness;
double gbest = swarm.getGbestValue();
if (fitness < gbest) {
swarm.setGBestValue(fitness);
swarm.setGBestIndex(i);
}
}
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("0 : ");
for (int j = 0; j < Nvariables; j++)
printf("%g ", best.xBest[j]);
printf(" = %e\n", best.pBest);
}
void PSO::evaluate(int i) {
//int index = i;
int ThreadsInBlock = 8;
int BlocksInGrid = (int)(Nvariables + ThreadsInBlock - 1) / ThreadsInBlock;
double *fitness = (double *)malloc(sizeof(double));
hipMallocManaged((void **)&fitness, sizeof(double));
hipMallocManaged((void **)&swarm.P[i].x, sizeof(double)*Nvariables);
evalPlane<<<BlocksInGrid, ThreadsInBlock>>>(Nvariables, swarm.P[i].x, fitness);
hipGetLastError();
//if (cudaSuccess != cudaMemcpy())
hipDeviceSynchronize();
// double fitness = 0.0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// int x = swarm.getParticleValue(index).x[k];
// fitness += x * x;
// }
// double fitness = 0, temp = 0;
// for(int k = 0 ; k < Nvariables ; k++ ) {
// for(int l = 0; l < k; l++)
// {
// double x = swarm.getParticleValue(index).x[l];
// temp += x;
// }
// fitness += temp * temp;
// }
hipFree(fitness);
hipFree(swarm.P[i].x);
//swarm.setParticleFitness(index, fitness);
}
void PSO::evaluateSwarm() {
for(int i = 0; i < Nparticles; i++) {
evaluate(i);
nfc++;
if (nfc % 5000 == 0) {
Particle best = swarm.getParticleValue(swarm.getGbest());
printf("%d : ", nfc);
// for (int j = 0; j < Nvariables; j++)
// printf("%g ", best.xBest[j]);
printf(" = %g\n", best.pBest);
//cout << "PSO SPHERE nfc" << nfc << " \tbestfit " << best.pBest << "\n";
}
}
for(int n = 0; n < Nparticles; n++) {
Particle par = swarm.getParticleValue(n);
if (par.fitness < par.pBest ) {
swarm.setParticlePBest(n, par.fitness, par.x);
if (par.fitness < swarm.getGbestValue() ) {
swarm.setGBestIndex(n);
swarm.setGBestValue(par.fitness);
}
}
}
}
void PSO::updateBest(int i) {
Particle par = swarm.getParticleValue(i);
swarm.setParticlePBest(i, par.fitness, par.x);
}
void PSO::calculateVMax() {
double xmin[Nparticles], xmax[Nparticles];
for (int d = 0; d < Nvariables; d++) {
xmin[d] = xmax[d] = swarm.getParticleValue(0).x[d];
for (int n = 1; n < Nparticles; n++) {
double pos = swarm.getParticleValue(n).x[d];
if (pos < xmin[d])
xmin[d] = pos;
if (pos > xmax[d])
xmax[d] = pos;
}
maxV[d] = xmax[d] - xmin[d];
}
}
void PSO::particleMovement() {
int n, d;
for (n = 0; n < Nparticles ; n++) {
Particle par = swarm.getParticleValue(n);
Particle bPar = swarm.getParticleValue(swarm.getGbest());
// update velocities
for(d = 0; d < Nvariables ; d++ ) {
double r1 = Rand();
double r2 = Rand();
double newV = w * par.v[d] + c1 * r1 * (par.xBest[d] - par.x[d]) + c2 * r2 * (bPar.x[d] - par.x[d]);
swarm.setParticleXV(n, d, NULL, newV);
// check v with its dimensional maxV
if ( swarm.getParticleValue(n).v[d] > maxV[d] ) swarm.setParticleXV(n, d, NULL, maxV[d]);
else if ( swarm.getParticleValue(n).v[d] < -maxV[d] ) swarm.setParticleXV(n, d, NULL, -maxV[d]);
}
// update positions
Particle newPar = swarm.getParticleValue(n);
for (d = 0; d < Nvariables ; d++) {
//newPar.x[d] = newPar.x[d] + newPar.v[d];
swarm.setParticleXV(n, d, newPar.x[d] + newPar.v[d], NULL);
}
}
}
int main(int argc, char **argv) {
//int threadCount = BlocksInGrid * ThreadsInBlock;
//long size = threadCount * sizeof(double);
PSO pso;
pso.evolution();
return 0;
} | .text
.file "CUDA_BPSO.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__evalPlaneiPdS_ # -- Begin function _Z24__device_stub__evalPlaneiPdS_
.p2align 4, 0x90
.type _Z24__device_stub__evalPlaneiPdS_,@function
_Z24__device_stub__evalPlaneiPdS_: # @_Z24__device_stub__evalPlaneiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9evalPlaneiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__evalPlaneiPdS_, .Lfunc_end0-_Z24__device_stub__evalPlaneiPdS_
.cfi_endproc
# -- End function
.globl _ZN5SwarmC2Ev # -- Begin function _ZN5SwarmC2Ev
.p2align 4, 0x90
.type _ZN5SwarmC2Ev,@function
_ZN5SwarmC2Ev: # @_ZN5SwarmC2Ev
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %r14
movl $0, (%rdi)
movl $1200, %edi # imm = 0x4B0
callq malloc
movq %rax, 16(%r14)
testq %rax, %rax
je .LBB1_2
# %bb.1: # %.preheader.preheader
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $240, %edi
callq malloc
movq %rax, (%rbx,%r14)
testq %rax, %rax
je .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movl $240, %edi
callq malloc
movq %rax, 8(%rbx,%r14)
testq %rax, %rax
je .LBB1_8
# %bb.9: # in Loop: Header=BB1_5 Depth=1
movl $240, %edi
callq malloc
movq %rax, 32(%rbx,%r14)
testq %rax, %rax
je .LBB1_10
# %bb.4: # in Loop: Header=BB1_5 Depth=1
addq $40, %r14
cmpq $1200, %r14 # imm = 0x4B0
jne .LBB1_5
# %bb.11:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_10:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rdi
movl $.L.str.3, %esi
jmp .LBB1_3
.LBB1_6:
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
jmp .LBB1_3
.LBB1_8:
movq stderr(%rip), %rdi
movl $.L.str.2, %esi
.LBB1_3:
movl $30, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_2:
movq stderr(%rip), %rdi
movl $.L.str, %esi
jmp .LBB1_3
.Lfunc_end1:
.size _ZN5SwarmC2Ev, .Lfunc_end1-_ZN5SwarmC2Ev
.cfi_endproc
# -- End function
.globl _ZN5Swarm13setGBestIndexEi # -- Begin function _ZN5Swarm13setGBestIndexEi
.p2align 4, 0x90
.type _ZN5Swarm13setGBestIndexEi,@function
_ZN5Swarm13setGBestIndexEi: # @_ZN5Swarm13setGBestIndexEi
.cfi_startproc
# %bb.0:
movl %esi, (%rdi)
retq
.Lfunc_end2:
.size _ZN5Swarm13setGBestIndexEi, .Lfunc_end2-_ZN5Swarm13setGBestIndexEi
.cfi_endproc
# -- End function
.globl _ZN5Swarm13setGBestValueEd # -- Begin function _ZN5Swarm13setGBestValueEd
.p2align 4, 0x90
.type _ZN5Swarm13setGBestValueEd,@function
_ZN5Swarm13setGBestValueEd: # @_ZN5Swarm13setGBestValueEd
.cfi_startproc
# %bb.0:
movsd %xmm0, 8(%rdi)
retq
.Lfunc_end3:
.size _ZN5Swarm13setGBestValueEd, .Lfunc_end3-_ZN5Swarm13setGBestValueEd
.cfi_endproc
# -- End function
.globl _ZN5Swarm13setParticleXVEiidd # -- Begin function _ZN5Swarm13setParticleXVEiidd
.p2align 4, 0x90
.type _ZN5Swarm13setParticleXVEiidd,@function
_ZN5Swarm13setParticleXVEiidd: # @_ZN5Swarm13setParticleXVEiidd
.cfi_startproc
# %bb.0:
xorpd %xmm2, %xmm2
ucomisd %xmm2, %xmm0
movslq %esi, %rcx
movslq %edx, %rax
jne .LBB4_1
jnp .LBB4_2
.LBB4_1:
movq 16(%rdi), %rdx
leaq (%rcx,%rcx,4), %rsi
movq (%rdx,%rsi,8), %rdx
movsd %xmm0, (%rdx,%rax,8)
.LBB4_2:
ucomisd %xmm2, %xmm1
jne .LBB4_3
jnp .LBB4_4
.LBB4_3:
movq 16(%rdi), %rdx
leaq (%rcx,%rcx,4), %rcx
movq 8(%rdx,%rcx,8), %rcx
movsd %xmm1, (%rcx,%rax,8)
.LBB4_4:
retq
.Lfunc_end4:
.size _ZN5Swarm13setParticleXVEiidd, .Lfunc_end4-_ZN5Swarm13setParticleXVEiidd
.cfi_endproc
# -- End function
.globl _ZN5Swarm18setParticleFitnessEid # -- Begin function _ZN5Swarm18setParticleFitnessEid
.p2align 4, 0x90
.type _ZN5Swarm18setParticleFitnessEid,@function
_ZN5Swarm18setParticleFitnessEid: # @_ZN5Swarm18setParticleFitnessEid
.cfi_startproc
# %bb.0:
movq 16(%rdi), %rax
movslq %esi, %rcx
leaq (%rcx,%rcx,4), %rcx
movsd %xmm0, 16(%rax,%rcx,8)
retq
.Lfunc_end5:
.size _ZN5Swarm18setParticleFitnessEid, .Lfunc_end5-_ZN5Swarm18setParticleFitnessEid
.cfi_endproc
# -- End function
.globl _ZN5Swarm16setParticlePBestEidPd # -- Begin function _ZN5Swarm16setParticlePBestEidPd
.p2align 4, 0x90
.type _ZN5Swarm16setParticlePBestEidPd,@function
_ZN5Swarm16setParticlePBestEidPd: # @_ZN5Swarm16setParticlePBestEidPd
.cfi_startproc
# %bb.0:
movq 16(%rdi), %rcx
movslq %esi, %rax
leaq (%rax,%rax,4), %rdx
movsd %xmm0, 24(%rcx,%rdx,8)
movq (%rcx,%rdx,8), %rax
movq 32(%rcx,%rdx,8), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
movsd (%rax,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rcx,%rdx,8)
incq %rdx
cmpq $30, %rdx
jne .LBB6_1
# %bb.2:
retq
.Lfunc_end6:
.size _ZN5Swarm16setParticlePBestEidPd, .Lfunc_end6-_ZN5Swarm16setParticlePBestEidPd
.cfi_endproc
# -- End function
.globl _ZN5Swarm16getParticleValueEi # -- Begin function _ZN5Swarm16getParticleValueEi
.p2align 4, 0x90
.type _ZN5Swarm16getParticleValueEi,@function
_ZN5Swarm16getParticleValueEi: # @_ZN5Swarm16getParticleValueEi
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movq 16(%rsi), %rcx
movslq %edx, %rdx
leaq (%rdx,%rdx,4), %rdx
movq 32(%rcx,%rdx,8), %rsi
movq %rsi, 32(%rdi)
movups (%rcx,%rdx,8), %xmm0
movups 16(%rcx,%rdx,8), %xmm1
movups %xmm1, 16(%rdi)
movups %xmm0, (%rdi)
retq
.Lfunc_end7:
.size _ZN5Swarm16getParticleValueEi, .Lfunc_end7-_ZN5Swarm16getParticleValueEi
.cfi_endproc
# -- End function
.globl _ZN5Swarm8getGbestEv # -- Begin function _ZN5Swarm8getGbestEv
.p2align 4, 0x90
.type _ZN5Swarm8getGbestEv,@function
_ZN5Swarm8getGbestEv: # @_ZN5Swarm8getGbestEv
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
retq
.Lfunc_end8:
.size _ZN5Swarm8getGbestEv, .Lfunc_end8-_ZN5Swarm8getGbestEv
.cfi_endproc
# -- End function
.globl _ZN5Swarm13getGbestValueEv # -- Begin function _ZN5Swarm13getGbestValueEv
.p2align 4, 0x90
.type _ZN5Swarm13getGbestValueEv,@function
_ZN5Swarm13getGbestValueEv: # @_ZN5Swarm13getGbestValueEv
.cfi_startproc
# %bb.0:
movsd 8(%rdi), %xmm0 # xmm0 = mem[0],zero
retq
.Lfunc_end9:
.size _ZN5Swarm13getGbestValueEv, .Lfunc_end9-_ZN5Swarm13getGbestValueEv
.cfi_endproc
# -- End function
.globl _ZN3PSOC2Ev # -- Begin function _ZN3PSOC2Ev
.p2align 4, 0x90
.type _ZN3PSOC2Ev,@function
_ZN3PSOC2Ev: # @_ZN3PSOC2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
addq $24, %rdi
callq _ZN5SwarmC2Ev
movl $240, %edi
callq malloc
movq %rax, 16(%rbx)
testq %rax, %rax
je .LBB10_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_2:
.cfi_def_cfa_offset 16
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $30, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end10:
.size _ZN3PSOC2Ev, .Lfunc_end10-_ZN3PSOC2Ev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN3PSO9evolutionEv
.LCPI11_0:
.quad 0xbeef7524eb0a8397 # double -1.5000150001500015E-5
.text
.globl _ZN3PSO9evolutionEv
.p2align 4, 0x90
.type _ZN3PSO9evolutionEv,@function
_ZN3PSO9evolutionEv: # @_ZN3PSO9evolutionEv
.cfi_startproc
# %bb.0: # %.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4606281698874543309, %rax # imm = 0x3FECCCCCCCCCCCCD
movq %rax, 8(%rdi)
callq _ZN3PSO10initializeEv
movl $0, (%rbx)
.p2align 4, 0x90
.LBB11_1: # =>This Loop Header: Depth=1
# Child Loop BB11_2 Depth 2
# Child Loop BB11_3 Depth 3
movq 16(%rbx), %rax
movq 40(%rbx), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB11_2: # Parent Loop BB11_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB11_3 Depth 3
movq (%rcx), %rsi
movsd (%rsi,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movl $40, %esi
movapd %xmm0, %xmm1
.p2align 4, 0x90
.LBB11_3: # Parent Loop BB11_1 Depth=1
# Parent Loop BB11_2 Depth=2
# => This Inner Loop Header: Depth=3
movapd %xmm1, %xmm2
movapd %xmm0, %xmm3
movq (%rcx,%rsi), %rdi
movsd (%rdi,%rdx,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm0
minsd %xmm3, %xmm0
maxsd %xmm2, %xmm1
addq $40, %rsi
cmpq $1200, %rsi # imm = 0x4B0
jne .LBB11_3
# %bb.4: # in Loop: Header=BB11_2 Depth=2
subsd %xmm0, %xmm1
movsd %xmm1, (%rax,%rdx,8)
incq %rdx
cmpq $30, %rdx
jne .LBB11_2
# %bb.5: # %_ZN3PSO13calculateVMaxEv.exit
# in Loop: Header=BB11_1 Depth=1
movq %rbx, %rdi
callq _ZN3PSO16particleMovementEv
movq %rbx, %rdi
callq _ZN3PSO13evaluateSwarmEv
movsd 8(%rbx), %xmm0 # xmm0 = mem[0],zero
addsd .LCPI11_0(%rip), %xmm0
movsd %xmm0, 8(%rbx)
cmpl $1000000, (%rbx) # imm = 0xF4240
jl .LBB11_1
# %bb.6: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size _ZN3PSO9evolutionEv, .Lfunc_end11-_ZN3PSO9evolutionEv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN3PSO10initializeEv
.LCPI12_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI12_1:
.quad 0x40247ae147ae147b # double 10.24
.LCPI12_2:
.quad 0xc0147ae147ae147b # double -5.1200000000000001
.LCPI12_3:
.quad 0x0000000000000000 # double 0
.text
.globl _ZN3PSO10initializeEv
.p2align 4, 0x90
.type _ZN3PSO10initializeEv,@function
_ZN3PSO10initializeEv: # @_ZN3PSO10initializeEv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movabsq $9218868437227405311, %rax # imm = 0x7FEFFFFFFFFFFFFF
movq %rax, 32(%rdi)
xorl %r14d, %r14d
jmp .LBB12_1
.p2align 4, 0x90
.LBB12_9: # in Loop: Header=BB12_1 Depth=1
incq %r14
cmpq $30, %r14
je .LBB12_10
.LBB12_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB12_2 Depth 2
# Child Loop BB12_6 Depth 2
leaq (%r14,%r14,4), %r15
xorl %r12d, %r12d
jmp .LBB12_2
.p2align 4, 0x90
.LBB12_4: # %_ZN5Swarm13setParticleXVEiidd.exit
# in Loop: Header=BB12_2 Depth=2
incq %r12
cmpq $30, %r12
je .LBB12_5
.LBB12_2: # Parent Loop BB12_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI12_0(%rip), %xmm0
mulsd .LCPI12_1(%rip), %xmm0
addsd .LCPI12_2(%rip), %xmm0
ucomisd .LCPI12_3(%rip), %xmm0
jne .LBB12_3
jnp .LBB12_4
.LBB12_3: # in Loop: Header=BB12_2 Depth=2
movq 40(%rbx), %rax
movq (%rax,%r15,8), %rax
movsd %xmm0, (%rax,%r12,8)
jmp .LBB12_4
.p2align 4, 0x90
.LBB12_5: # in Loop: Header=BB12_1 Depth=1
movq %rbx, %rdi
movl %r14d, %esi
callq _ZN3PSO8evaluateEi
movq 40(%rbx), %rcx
movsd 16(%rcx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%rcx,%r15,8)
movq (%rcx,%r15,8), %rax
movq 32(%rcx,%r15,8), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB12_6: # Parent Loop BB12_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rcx,%rdx,8)
incq %rdx
cmpq $30, %rdx
jne .LBB12_6
# %bb.7: # %_ZN3PSO10updateBestEi.exit
# in Loop: Header=BB12_1 Depth=1
movq 40(%rbx), %rax
movsd 16(%rax,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd 32(%rbx), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jbe .LBB12_9
# %bb.8: # in Loop: Header=BB12_1 Depth=1
movsd %xmm0, 32(%rbx)
movl %r14d, 24(%rbx)
jmp .LBB12_9
.LBB12_10:
movslq 24(%rbx), %rax
movq 40(%rbx), %rcx
leaq (%rax,%rax,4), %rax
movsd 24(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsp) # 8-byte Spill
movq 32(%rcx,%rax,8), %rbx
xorl %r14d, %r14d
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB12_11: # =>This Inner Loop Header: Depth=1
movsd (%rbx,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r14
cmpq $30, %r14
jne .LBB12_11
# %bb.12:
movl $.L.str.7, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end12:
.size _ZN3PSO10initializeEv, .Lfunc_end12-_ZN3PSO10initializeEv
.cfi_endproc
# -- End function
.globl _ZN3PSO13calculateVMaxEv # -- Begin function _ZN3PSO13calculateVMaxEv
.p2align 4, 0x90
.type _ZN3PSO13calculateVMaxEv,@function
_ZN3PSO13calculateVMaxEv: # @_ZN3PSO13calculateVMaxEv
.cfi_startproc
# %bb.0:
movq 16(%rdi), %rax
movq 40(%rdi), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB13_1: # =>This Loop Header: Depth=1
# Child Loop BB13_2 Depth 2
movq (%rcx), %rsi
movsd (%rsi,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movl $40, %esi
movapd %xmm0, %xmm1
.p2align 4, 0x90
.LBB13_2: # Parent Loop BB13_1 Depth=1
# => This Inner Loop Header: Depth=2
movapd %xmm1, %xmm2
movapd %xmm0, %xmm3
movq (%rcx,%rsi), %rdi
movsd (%rdi,%rdx,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm0
minsd %xmm3, %xmm0
maxsd %xmm2, %xmm1
addq $40, %rsi
cmpq $1200, %rsi # imm = 0x4B0
jne .LBB13_2
# %bb.3: # in Loop: Header=BB13_1 Depth=1
subsd %xmm0, %xmm1
movsd %xmm1, (%rax,%rdx,8)
incq %rdx
cmpq $30, %rdx
jne .LBB13_1
# %bb.4:
retq
.Lfunc_end13:
.size _ZN3PSO13calculateVMaxEv, .Lfunc_end13-_ZN3PSO13calculateVMaxEv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _ZN3PSO16particleMovementEv
.LCPI14_0:
.quad 0x41dfffffffc00000 # double 2147483647
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI14_1:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.text
.globl _ZN3PSO16particleMovementEv
.p2align 4, 0x90
.type _ZN3PSO16particleMovementEv,@function
_ZN3PSO16particleMovementEv: # @_ZN3PSO16particleMovementEv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
xorl %ecx, %ecx
jmp .LBB14_1
.p2align 4, 0x90
.LBB14_15: # in Loop: Header=BB14_1 Depth=1
movq (%rsp), %rcx # 8-byte Reload
incq %rcx
cmpq $30, %rcx
je .LBB14_16
.LBB14_1: # =>This Loop Header: Depth=1
# Child Loop BB14_2 Depth 2
# Child Loop BB14_12 Depth 2
movq 40(%rbx), %rax
movq %rcx, (%rsp) # 8-byte Spill
leaq (%rcx,%rcx,4), %r15
movq (%rax,%r15,8), %rcx
movq %rcx, 8(%rsp) # 8-byte Spill
movq 8(%rax,%r15,8), %r13
movq 32(%rax,%r15,8), %rbp
movslq 24(%rbx), %rcx
leaq (%rcx,%rcx,4), %rcx
movq (%rax,%rcx,8), %r14
xorl %r12d, %r12d
jmp .LBB14_2
.p2align 4, 0x90
.LBB14_5: # in Loop: Header=BB14_2 Depth=2
ucomisd %xmm3, %xmm0
jne .LBB14_9
jnp .LBB14_10
.LBB14_9: # %_ZN5Swarm13setParticleXVEiidd.exit35.sink.split
# in Loop: Header=BB14_2 Depth=2
movq 8(%rax,%r15,8), %rax
movsd %xmm0, (%rax,%r12)
.LBB14_10: # %_ZN5Swarm13setParticleXVEiidd.exit35
# in Loop: Header=BB14_2 Depth=2
addq $8, %r12
cmpq $240, %r12
je .LBB14_11
.LBB14_2: # Parent Loop BB14_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI14_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
divsd .LCPI14_0(%rip), %xmm1
movsd 8(%rbx), %xmm0 # xmm0 = mem[0],zero
mulsd (%r13,%r12), %xmm0
movsd 16(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
addsd %xmm4, %xmm4
movsd (%rbp,%r12), %xmm2 # xmm2 = mem[0],zero
movq 8(%rsp), %rax # 8-byte Reload
movsd (%rax,%r12), %xmm3 # xmm3 = mem[0],zero
subsd %xmm3, %xmm2
mulsd %xmm4, %xmm2
addsd %xmm0, %xmm2
addsd %xmm1, %xmm1
movsd (%r14,%r12), %xmm0 # xmm0 = mem[0],zero
subsd %xmm3, %xmm0
xorpd %xmm3, %xmm3
mulsd %xmm1, %xmm0
addsd %xmm2, %xmm0
ucomisd %xmm3, %xmm0
jne .LBB14_3
jnp .LBB14_4
.LBB14_3: # in Loop: Header=BB14_2 Depth=2
movq 40(%rbx), %rax
movq 8(%rax,%r15,8), %rax
movsd %xmm0, (%rax,%r12)
.LBB14_4: # %_ZN5Swarm13setParticleXVEiidd.exit
# in Loop: Header=BB14_2 Depth=2
movq 16(%rbx), %rcx
movq 40(%rbx), %rax
movq 8(%rax,%r15,8), %rdx
movsd (%rdx,%r12), %xmm2 # xmm2 = mem[0],zero
movsd (%rcx,%r12), %xmm0 # xmm0 = mem[0],zero
ucomisd %xmm0, %xmm2
ja .LBB14_5
# %bb.6: # in Loop: Header=BB14_2 Depth=2
movapd %xmm0, %xmm1
xorpd .LCPI14_1(%rip), %xmm1
ucomisd %xmm2, %xmm1
jbe .LBB14_10
# %bb.7: # in Loop: Header=BB14_2 Depth=2
ucomisd %xmm3, %xmm0
jne .LBB14_8
jnp .LBB14_10
.LBB14_8: # in Loop: Header=BB14_2 Depth=2
movapd %xmm1, %xmm0
jmp .LBB14_9
.p2align 4, 0x90
.LBB14_11: # in Loop: Header=BB14_1 Depth=1
movq 40(%rbx), %rcx
movq (%rcx,%r15,8), %rax
movq 8(%rcx,%r15,8), %rcx
xorl %edx, %edx
jmp .LBB14_12
.p2align 4, 0x90
.LBB14_14: # %_ZN5Swarm13setParticleXVEiidd.exit37
# in Loop: Header=BB14_12 Depth=2
incq %rdx
cmpq $30, %rdx
je .LBB14_15
.LBB14_12: # Parent Loop BB14_1 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rax,%rdx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rcx,%rdx,8), %xmm0
ucomisd %xmm3, %xmm0
jne .LBB14_13
jnp .LBB14_14
.LBB14_13: # in Loop: Header=BB14_12 Depth=2
movsd %xmm0, (%rax,%rdx,8)
jmp .LBB14_14
.LBB14_16:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end14:
.size _ZN3PSO16particleMovementEv, .Lfunc_end14-_ZN3PSO16particleMovementEv
.cfi_endproc
# -- End function
.globl _ZN3PSO13evaluateSwarmEv # -- Begin function _ZN3PSO13evaluateSwarmEv
.p2align 4, 0x90
.type _ZN3PSO13evaluateSwarmEv,@function
_ZN3PSO13evaluateSwarmEv: # @_ZN3PSO13evaluateSwarmEv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
xorl %ebp, %ebp
jmp .LBB15_1
.p2align 4, 0x90
.LBB15_3: # in Loop: Header=BB15_1 Depth=1
incl %ebp
cmpl $30, %ebp
je .LBB15_4
.LBB15_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq _ZN3PSO8evaluateEi
movl (%rbx), %esi
incl %esi
movl %esi, (%rbx)
imull $989560465, %esi, %eax # imm = 0x3AFB7E91
addl $3435968, %eax # imm = 0x346DC0
rorl $3, %eax
cmpl $858992, %eax # imm = 0xD1B70
ja .LBB15_3
# %bb.2: # in Loop: Header=BB15_1 Depth=1
movslq 24(%rbx), %rax
movq 40(%rbx), %rcx
leaq (%rax,%rax,4), %rax
movsd 24(%rcx,%rax,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rsp) # 8-byte Spill
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.9, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
jmp .LBB15_3
.LBB15_4: # %.preheader
movq 40(%rbx), %rax
xorl %ecx, %ecx
jmp .LBB15_5
.p2align 4, 0x90
.LBB15_10: # in Loop: Header=BB15_5 Depth=1
incq %rcx
cmpq $30, %rcx
je .LBB15_11
.LBB15_5: # =>This Loop Header: Depth=1
# Child Loop BB15_7 Depth 2
leaq (%rcx,%rcx,4), %rsi
movsd 16(%rax,%rsi,8), %xmm0 # xmm0 = mem[0],zero
movsd 24(%rax,%rsi,8), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jbe .LBB15_10
# %bb.6: # in Loop: Header=BB15_5 Depth=1
leaq (%rax,%rsi,8), %rdx
movsd %xmm0, 24(%rax,%rsi,8)
movq (%rdx), %rdx
movq 32(%rax,%rsi,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB15_7: # Parent Loop BB15_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rdx,%rdi,8), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, (%rsi,%rdi,8)
incq %rdi
cmpq $30, %rdi
jne .LBB15_7
# %bb.8: # %_ZN5Swarm16setParticlePBestEidPd.exit
# in Loop: Header=BB15_5 Depth=1
movsd 32(%rbx), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jbe .LBB15_10
# %bb.9: # in Loop: Header=BB15_5 Depth=1
movl %ecx, 24(%rbx)
movsd %xmm0, 32(%rbx)
jmp .LBB15_10
.LBB15_11:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end15:
.size _ZN3PSO13evaluateSwarmEv, .Lfunc_end15-_ZN3PSO13evaluateSwarmEv
.cfi_endproc
# -- End function
.globl _ZN3PSO8evaluateEi # -- Begin function _ZN3PSO8evaluateEi
.p2align 4, 0x90
.type _ZN3PSO8evaluateEi,@function
_ZN3PSO8evaluateEi: # @_ZN3PSO8evaluateEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $8, %edi
callq malloc
movq %rax, (%rsp)
movq %rsp, %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
movslq %ebp, %rax
leaq (%rax,%rax,4), %r14
leaq (,%r14,8), %rdi
addq 40(%rbx), %rdi
movl $240, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB16_2
# %bb.1:
movq 40(%rbx), %rax
movq (%rax,%r14,8), %rax
movq (%rsp), %rcx
movl $30, 12(%rsp)
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9evalPlaneiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB16_2:
callq hipGetLastError
callq hipDeviceSynchronize
movq (%rsp), %rdi
callq hipFree
movq 40(%rbx), %rax
movq (%rax,%r14,8), %rdi
callq hipFree
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end16:
.size _ZN3PSO8evaluateEi, .Lfunc_end16-_ZN3PSO8evaluateEi
.cfi_endproc
# -- End function
.globl _ZN3PSO10updateBestEi # -- Begin function _ZN3PSO10updateBestEi
.p2align 4, 0x90
.type _ZN3PSO10updateBestEi,@function
_ZN3PSO10updateBestEi: # @_ZN3PSO10updateBestEi
.cfi_startproc
# %bb.0:
movq 40(%rdi), %rcx
movslq %esi, %rax
leaq (%rax,%rax,4), %rdx
movsd 16(%rcx,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 24(%rcx,%rdx,8)
movq (%rcx,%rdx,8), %rax
movq 32(%rcx,%rdx,8), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB17_1: # =>This Inner Loop Header: Depth=1
movsd (%rax,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%rcx,%rdx,8)
incq %rdx
cmpq $30, %rdx
jne .LBB17_1
# %bb.2: # %_ZN5Swarm16setParticlePBestEidPd.exit
retq
.Lfunc_end17:
.size _ZN3PSO10updateBestEi, .Lfunc_end17-_ZN3PSO10updateBestEi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI18_0:
.quad 0xbeef7524eb0a8397 # double -1.5000150001500015E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $48, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
callq _ZN5SwarmC2Ev
movl $240, %edi
callq malloc
movq %rax, 16(%rsp)
testq %rax, %rax
je .LBB18_8
# %bb.1: # %_ZN3PSOC2Ev.exit
movabsq $4606281698874543309, %rax # imm = 0x3FECCCCCCCCCCCCD
movq %rax, 8(%rsp)
movq %rsp, %rbx
movq %rbx, %rdi
callq _ZN3PSO10initializeEv
movl $0, (%rsp)
.p2align 4, 0x90
.LBB18_2: # =>This Loop Header: Depth=1
# Child Loop BB18_3 Depth 2
# Child Loop BB18_4 Depth 3
movq 16(%rsp), %rax
movq 40(%rsp), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB18_3: # Parent Loop BB18_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB18_4 Depth 3
movq (%rcx), %rsi
movsd (%rsi,%rdx,8), %xmm0 # xmm0 = mem[0],zero
movl $40, %esi
movapd %xmm0, %xmm1
.p2align 4, 0x90
.LBB18_4: # Parent Loop BB18_2 Depth=1
# Parent Loop BB18_3 Depth=2
# => This Inner Loop Header: Depth=3
movapd %xmm1, %xmm2
movapd %xmm0, %xmm3
movq (%rcx,%rsi), %rdi
movsd (%rdi,%rdx,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm0
minsd %xmm3, %xmm0
maxsd %xmm2, %xmm1
addq $40, %rsi
cmpq $1200, %rsi # imm = 0x4B0
jne .LBB18_4
# %bb.5: # in Loop: Header=BB18_3 Depth=2
subsd %xmm0, %xmm1
movsd %xmm1, (%rax,%rdx,8)
incq %rdx
cmpq $30, %rdx
jne .LBB18_3
# %bb.6: # %_ZN3PSO13calculateVMaxEv.exit.i
# in Loop: Header=BB18_2 Depth=1
movq %rbx, %rdi
callq _ZN3PSO16particleMovementEv
movq %rbx, %rdi
callq _ZN3PSO13evaluateSwarmEv
movsd 8(%rsp), %xmm0 # xmm0 = mem[0],zero
addsd .LCPI18_0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
cmpl $1000000, (%rsp) # imm = 0xF4240
jl .LBB18_2
# %bb.7: # %_ZN3PSO9evolutionEv.exit
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB18_8:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl $30, %edx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end18:
.size main, .Lfunc_end18-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB19_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB19_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9evalPlaneiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end19:
.size __hip_module_ctor, .Lfunc_end19-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB20_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB20_2:
retq
.Lfunc_end20:
.size __hip_module_dtor, .Lfunc_end20-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9evalPlaneiPdS_,@object # @_Z9evalPlaneiPdS_
.section .rodata,"a",@progbits
.globl _Z9evalPlaneiPdS_
.p2align 3, 0x0
_Z9evalPlaneiPdS_:
.quad _Z24__device_stub__evalPlaneiPdS_
.size _Z9evalPlaneiPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cannot allocate memory for %d Particles\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cannot allocate memory for %d x\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cannot allocate memory for %d v\n"
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cannot allocate memory for %d xBest\n"
.size .L.str.3, 37
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cannot allocate memory for %d maxV\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "0 : "
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%g "
.size .L.str.6, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " = %e\n"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d : "
.size .L.str.8, 6
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " = %g\n"
.size .L.str.9, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9evalPlaneiPdS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN5SwarmC1Ev
.type _ZN5SwarmC1Ev,@function
.set _ZN5SwarmC1Ev, _ZN5SwarmC2Ev
.globl _ZN3PSOC1Ev
.type _ZN3PSOC1Ev,@function
.set _ZN3PSOC1Ev, _ZN3PSOC2Ev
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__evalPlaneiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9evalPlaneiPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9evalPlaneiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a8000c1e1b00 */
/*0280*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*02d0*/ DFMA R10, R8, R8, R10 ; /* 0x00000008080a722b */
/* 0x004e0e000000000a */
/*02e0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0011e4000c101b04 */
/*02f0*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe400078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x002fc800078e00ff */
/*0340*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0208 */
/*0350*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fe200078e0208 */
/*0360*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0370*/ LDG.E.64 R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1b00 */
/*0380*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fe200078e0208 */
/*0390*/ DFMA R10, R6, R6, R10 ; /* 0x00000006060a722b */
/* 0x004046000000000a */
/*03a0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x001fc800078e0204 */
/*03b0*/ STG.E.64 [R8.64], R10 ; /* 0x0000000a08007986 */
/* 0x0021e8000c101b04 */
/*03c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1b00 */
/*03d0*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IMAD.WIDE R18, R0, 0x8, R14 ; /* 0x0000000800127825 */
/* 0x000fe200078e020e */
/*03f0*/ DFMA R16, R12, R12, R16 ; /* 0x0000000c0c10722b */
/* 0x0042860000000010 */
/*0400*/ IMAD.WIDE R12, R0, 0x8, R6 ; /* 0x00000008000c7825 */
/* 0x002fc800078e0206 */
/*0410*/ STG.E.64 [R14.64], R16 ; /* 0x000000100e007986 */
/* 0x0043e8000c101b04 */
/*0420*/ LDG.E.64 R4, [R12.64] ; /* 0x000000040c047981 */
/* 0x000ea8000c1e1b00 */
/*0430*/ LDG.E.64 R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R8, R0, 0x8, R18 ; /* 0x0000000800087825 */
/* 0x001fe200078e0212 */
/*0450*/ DFMA R20, R4, R4, R20 ; /* 0x000000040414722b */
/* 0x0040860000000014 */
/*0460*/ IMAD.WIDE R4, R0, 0x8, R12 ; /* 0x0000000800047825 */
/* 0x001fc800078e020c */
/*0470*/ STG.E.64 [R18.64], R20 ; /* 0x0000001412007986 */
/* 0x0043e8000c101b04 */
/*0480*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R8.64] ; /* 0x0000000408067981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ DFMA R6, R4, R4, R6 ; /* 0x000000040406722b */
/* 0x004e0e0000000006 */
/*04e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0013ea000c101b04 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9evalPlaneiPdS_
.globl _Z9evalPlaneiPdS_
.p2align 8
.type _Z9evalPlaneiPdS_,@function
_Z9evalPlaneiPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[6:7], off
v_add_co_u32 v2, s0, v2, s8
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[4:5], v[4:5], v[8:9]
global_store_b64 v[6:7], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9evalPlaneiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9evalPlaneiPdS_, .Lfunc_end0-_Z9evalPlaneiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9evalPlaneiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9evalPlaneiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void relabel2Kernel(int *components, int previousLabel, int newLabel, const int colsComponents, const int idx, const int frameRows) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
i = i * colsComponents + j;
i = i + (colsComponents * frameRows * idx);
if (components[i] == previousLabel) {
components[i] = newLabel;
}
} | code for sm_80
Function : _Z14relabel2KernelPiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R7, c[0x0][0x174], R0 ; /* 0x00005d0007007a24 */
/* 0x000fe400078e0200 */
/*0090*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*00b0*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fce00078e0203 */
/*00c0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x004fda0003f05270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fca0000000f00 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void relabel2Kernel(int *components, int previousLabel, int newLabel, const int colsComponents, const int idx, const int frameRows) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
i = i * colsComponents + j;
i = i + (colsComponents * frameRows * idx);
if (components[i] == previousLabel) {
components[i] = newLabel;
}
} | .file "tmpxft_00103878_00000000-6_relabel2Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii
.type _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii, @function
_Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14relabel2KernelPiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii, .-_Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii
.globl _Z14relabel2KernelPiiiiii
.type _Z14relabel2KernelPiiiiii, @function
_Z14relabel2KernelPiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14relabel2KernelPiiiiii, .-_Z14relabel2KernelPiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14relabel2KernelPiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14relabel2KernelPiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void relabel2Kernel(int *components, int previousLabel, int newLabel, const int colsComponents, const int idx, const int frameRows) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
i = i * colsComponents + j;
i = i + (colsComponents * frameRows * idx);
if (components[i] == previousLabel) {
components[i] = newLabel;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void relabel2Kernel(int *components, int previousLabel, int newLabel, const int colsComponents, const int idx, const int frameRows) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
i = i * colsComponents + j;
i = i + (colsComponents * frameRows * idx);
if (components[i] == previousLabel) {
components[i] = newLabel;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void relabel2Kernel(int *components, int previousLabel, int newLabel, const int colsComponents, const int idx, const int frameRows) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
i = i * colsComponents + j;
i = i + (colsComponents * frameRows * idx);
if (components[i] == previousLabel) {
components[i] = newLabel;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14relabel2KernelPiiiiii
.globl _Z14relabel2KernelPiiiiii
.p2align 8
.type _Z14relabel2KernelPiiiiii,@function
_Z14relabel2KernelPiiiiii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s6, 0xffff
s_mul_i32 s4, s4, s3
s_mul_i32 s14, s14, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v1, s14, s4, v1
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_lshr_b32 s2, s6, 16
v_mov_b32_e32 v1, 0
s_mul_i32 s15, s15, s2
s_load_b32 s2, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, v0, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14relabel2KernelPiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14relabel2KernelPiiiiii, .Lfunc_end0-_Z14relabel2KernelPiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14relabel2KernelPiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14relabel2KernelPiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void relabel2Kernel(int *components, int previousLabel, int newLabel, const int colsComponents, const int idx, const int frameRows) {
uint i = (blockIdx.x * blockDim.x) + threadIdx.x;
uint j = (blockIdx.y * blockDim.y) + threadIdx.y;
i = i * colsComponents + j;
i = i + (colsComponents * frameRows * idx);
if (components[i] == previousLabel) {
components[i] = newLabel;
}
} | .text
.file "relabel2Kernel.hip"
.globl _Z29__device_stub__relabel2KernelPiiiiii # -- Begin function _Z29__device_stub__relabel2KernelPiiiiii
.p2align 4, 0x90
.type _Z29__device_stub__relabel2KernelPiiiiii,@function
_Z29__device_stub__relabel2KernelPiiiiii: # @_Z29__device_stub__relabel2KernelPiiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14relabel2KernelPiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__relabel2KernelPiiiiii, .Lfunc_end0-_Z29__device_stub__relabel2KernelPiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14relabel2KernelPiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14relabel2KernelPiiiiii,@object # @_Z14relabel2KernelPiiiiii
.section .rodata,"a",@progbits
.globl _Z14relabel2KernelPiiiiii
.p2align 3, 0x0
_Z14relabel2KernelPiiiiii:
.quad _Z29__device_stub__relabel2KernelPiiiiii
.size _Z14relabel2KernelPiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14relabel2KernelPiiiiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__relabel2KernelPiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14relabel2KernelPiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14relabel2KernelPiiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD R0, R7, c[0x0][0x174], R0 ; /* 0x00005d0007007a24 */
/* 0x000fe400078e0200 */
/*0090*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fe200078e0205 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fc600000001ff */
/*00b0*/ IMAD R3, R0, c[0x0][0x170], R3 ; /* 0x00005c0000037a24 */
/* 0x000fce00078e0203 */
/*00c0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0002 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x004fda0003f05270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fca0000000f00 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14relabel2KernelPiiiiii
.globl _Z14relabel2KernelPiiiiii
.p2align 8
.type _Z14relabel2KernelPiiiiii,@function
_Z14relabel2KernelPiiiiii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s6, 0xffff
s_mul_i32 s4, s4, s3
s_mul_i32 s14, s14, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v1, s14, s4, v1
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_lshr_b32 s2, s6, 16
v_mov_b32_e32 v1, 0
s_mul_i32 s15, s15, s2
s_load_b32 s2, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, v0, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14relabel2KernelPiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14relabel2KernelPiiiiii, .Lfunc_end0-_Z14relabel2KernelPiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14relabel2KernelPiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14relabel2KernelPiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00103878_00000000-6_relabel2Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii
.type _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii, @function
_Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14relabel2KernelPiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii, .-_Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii
.globl _Z14relabel2KernelPiiiiii
.type _Z14relabel2KernelPiiiiii, @function
_Z14relabel2KernelPiiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14relabel2KernelPiiiiiiPiiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14relabel2KernelPiiiiii, .-_Z14relabel2KernelPiiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14relabel2KernelPiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14relabel2KernelPiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "relabel2Kernel.hip"
.globl _Z29__device_stub__relabel2KernelPiiiiii # -- Begin function _Z29__device_stub__relabel2KernelPiiiiii
.p2align 4, 0x90
.type _Z29__device_stub__relabel2KernelPiiiiii,@function
_Z29__device_stub__relabel2KernelPiiiiii: # @_Z29__device_stub__relabel2KernelPiiiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14relabel2KernelPiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__relabel2KernelPiiiiii, .Lfunc_end0-_Z29__device_stub__relabel2KernelPiiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14relabel2KernelPiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14relabel2KernelPiiiiii,@object # @_Z14relabel2KernelPiiiiii
.section .rodata,"a",@progbits
.globl _Z14relabel2KernelPiiiiii
.p2align 3, 0x0
_Z14relabel2KernelPiiiiii:
.quad _Z29__device_stub__relabel2KernelPiiiiii
.size _Z14relabel2KernelPiiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14relabel2KernelPiiiiii"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__relabel2KernelPiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14relabel2KernelPiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*************************************************************************************************
*
* Computer Engineering Group, Heidelberg University - GPU Computing Exercise 03
*
* Group : TBD
*
* File : main.cu
*
* Purpose : Memory Operations Benchmark
*
*************************************************************************************************/
//
// Kernels
//
__global__ void
globalMemCoalescedKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemCoalescedKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemCoalescedKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemStrideKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemStrideKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemStrideKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemOffsetKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemOffsetKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
} | code for sm_80
Function : _Z21globalMemOffsetKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21globalMemStrideKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24globalMemCoalescedKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*************************************************************************************************
*
* Computer Engineering Group, Heidelberg University - GPU Computing Exercise 03
*
* Group : TBD
*
* File : main.cu
*
* Purpose : Memory Operations Benchmark
*
*************************************************************************************************/
//
// Kernels
//
__global__ void
globalMemCoalescedKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemCoalescedKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemCoalescedKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemStrideKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemStrideKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemStrideKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemOffsetKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemOffsetKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
} | .file "tmpxft_0014ceb8_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z24globalMemCoalescedKernelvv
.type _Z43__device_stub__Z24globalMemCoalescedKernelvv, @function
_Z43__device_stub__Z24globalMemCoalescedKernelvv:
.LFB2054:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z24globalMemCoalescedKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z43__device_stub__Z24globalMemCoalescedKernelvv, .-_Z43__device_stub__Z24globalMemCoalescedKernelvv
.globl _Z24globalMemCoalescedKernelv
.type _Z24globalMemCoalescedKernelv, @function
_Z24globalMemCoalescedKernelv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z24globalMemCoalescedKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z24globalMemCoalescedKernelv, .-_Z24globalMemCoalescedKernelv
.globl _Z32globalMemCoalescedKernel_Wrapper4dim3S_
.type _Z32globalMemCoalescedKernel_Wrapper4dim3S_, @function
_Z32globalMemCoalescedKernel_Wrapper4dim3S_:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ecx
movl $0, %r9d
movl $0, %r8d
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z43__device_stub__Z24globalMemCoalescedKernelvv
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z32globalMemCoalescedKernel_Wrapper4dim3S_, .-_Z32globalMemCoalescedKernel_Wrapper4dim3S_
.globl _Z40__device_stub__Z21globalMemStrideKernelvv
.type _Z40__device_stub__Z21globalMemStrideKernelvv, @function
_Z40__device_stub__Z21globalMemStrideKernelvv:
.LFB2056:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z21globalMemStrideKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z40__device_stub__Z21globalMemStrideKernelvv, .-_Z40__device_stub__Z21globalMemStrideKernelvv
.globl _Z21globalMemStrideKernelv
.type _Z21globalMemStrideKernelv, @function
_Z21globalMemStrideKernelv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z21globalMemStrideKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z21globalMemStrideKernelv, .-_Z21globalMemStrideKernelv
.globl _Z29globalMemStrideKernel_Wrapper4dim3S_
.type _Z29globalMemStrideKernel_Wrapper4dim3S_, @function
_Z29globalMemStrideKernel_Wrapper4dim3S_:
.LFB2028:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ecx
movl $0, %r9d
movl $0, %r8d
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call _Z40__device_stub__Z21globalMemStrideKernelvv
jmp .L23
.cfi_endproc
.LFE2028:
.size _Z29globalMemStrideKernel_Wrapper4dim3S_, .-_Z29globalMemStrideKernel_Wrapper4dim3S_
.globl _Z40__device_stub__Z21globalMemOffsetKernelvv
.type _Z40__device_stub__Z21globalMemOffsetKernelvv, @function
_Z40__device_stub__Z21globalMemOffsetKernelvv:
.LFB2058:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z21globalMemOffsetKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z40__device_stub__Z21globalMemOffsetKernelvv, .-_Z40__device_stub__Z21globalMemOffsetKernelvv
.globl _Z21globalMemOffsetKernelv
.type _Z21globalMemOffsetKernelv, @function
_Z21globalMemOffsetKernelv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z21globalMemOffsetKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z21globalMemOffsetKernelv, .-_Z21globalMemOffsetKernelv
.globl _Z29globalMemOffsetKernel_Wrapper4dim3S_
.type _Z29globalMemOffsetKernel_Wrapper4dim3S_, @function
_Z29globalMemOffsetKernel_Wrapper4dim3S_:
.LFB2029:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ecx
movl $0, %r9d
movl $0, %r8d
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call _Z40__device_stub__Z21globalMemOffsetKernelvv
jmp .L35
.cfi_endproc
.LFE2029:
.size _Z29globalMemOffsetKernel_Wrapper4dim3S_, .-_Z29globalMemOffsetKernel_Wrapper4dim3S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21globalMemOffsetKernelv"
.LC1:
.string "_Z21globalMemStrideKernelv"
.LC2:
.string "_Z24globalMemCoalescedKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21globalMemOffsetKernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21globalMemStrideKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z24globalMemCoalescedKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*************************************************************************************************
*
* Computer Engineering Group, Heidelberg University - GPU Computing Exercise 03
*
* Group : TBD
*
* File : main.cu
*
* Purpose : Memory Operations Benchmark
*
*************************************************************************************************/
//
// Kernels
//
__global__ void
globalMemCoalescedKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemCoalescedKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemCoalescedKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemStrideKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemStrideKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemStrideKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemOffsetKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemOffsetKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
} | #include <hip/hip_runtime.h>
/*************************************************************************************************
*
* Computer Engineering Group, Heidelberg University - GPU Computing Exercise 03
*
* Group : TBD
*
* File : main.cu
*
* Purpose : Memory Operations Benchmark
*
*************************************************************************************************/
//
// Kernels
//
__global__ void
globalMemCoalescedKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemCoalescedKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemCoalescedKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemStrideKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemStrideKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemStrideKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemOffsetKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemOffsetKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*************************************************************************************************
*
* Computer Engineering Group, Heidelberg University - GPU Computing Exercise 03
*
* Group : TBD
*
* File : main.cu
*
* Purpose : Memory Operations Benchmark
*
*************************************************************************************************/
//
// Kernels
//
__global__ void
globalMemCoalescedKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemCoalescedKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemCoalescedKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemStrideKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemStrideKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemStrideKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemOffsetKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemOffsetKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24globalMemCoalescedKernelv
.globl _Z24globalMemCoalescedKernelv
.p2align 8
.type _Z24globalMemCoalescedKernelv,@function
_Z24globalMemCoalescedKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24globalMemCoalescedKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24globalMemCoalescedKernelv, .Lfunc_end0-_Z24globalMemCoalescedKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21globalMemStrideKernelv
.globl _Z21globalMemStrideKernelv
.p2align 8
.type _Z21globalMemStrideKernelv,@function
_Z21globalMemStrideKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21globalMemStrideKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z21globalMemStrideKernelv, .Lfunc_end1-_Z21globalMemStrideKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21globalMemOffsetKernelv
.globl _Z21globalMemOffsetKernelv
.p2align 8
.type _Z21globalMemOffsetKernelv,@function
_Z21globalMemOffsetKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21globalMemOffsetKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z21globalMemOffsetKernelv, .Lfunc_end2-_Z21globalMemOffsetKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24globalMemCoalescedKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z24globalMemCoalescedKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21globalMemStrideKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z21globalMemStrideKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21globalMemOffsetKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z21globalMemOffsetKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*************************************************************************************************
*
* Computer Engineering Group, Heidelberg University - GPU Computing Exercise 03
*
* Group : TBD
*
* File : main.cu
*
* Purpose : Memory Operations Benchmark
*
*************************************************************************************************/
//
// Kernels
//
__global__ void
globalMemCoalescedKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemCoalescedKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemCoalescedKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemStrideKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemStrideKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemStrideKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
}
__global__ void
globalMemOffsetKernel(/*TODO Parameters*/)
{
/*TODO Kernel Code*/
}
void
globalMemOffsetKernel_Wrapper(dim3 gridDim, dim3 blockDim /*TODO Parameters*/) {
globalMemOffsetKernel<<< gridDim, blockDim, 0 /*Shared Memory Size*/ >>>( /*TODO Parameters*/);
} | .text
.file "kernel.hip"
.globl _Z39__device_stub__globalMemCoalescedKernelv # -- Begin function _Z39__device_stub__globalMemCoalescedKernelv
.p2align 4, 0x90
.type _Z39__device_stub__globalMemCoalescedKernelv,@function
_Z39__device_stub__globalMemCoalescedKernelv: # @_Z39__device_stub__globalMemCoalescedKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24globalMemCoalescedKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z39__device_stub__globalMemCoalescedKernelv, .Lfunc_end0-_Z39__device_stub__globalMemCoalescedKernelv
.cfi_endproc
# -- End function
.globl _Z32globalMemCoalescedKernel_Wrapper4dim3S_ # -- Begin function _Z32globalMemCoalescedKernel_Wrapper4dim3S_
.p2align 4, 0x90
.type _Z32globalMemCoalescedKernel_Wrapper4dim3S_,@function
_Z32globalMemCoalescedKernel_Wrapper4dim3S_: # @_Z32globalMemCoalescedKernel_Wrapper4dim3S_
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24globalMemCoalescedKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z32globalMemCoalescedKernel_Wrapper4dim3S_, .Lfunc_end1-_Z32globalMemCoalescedKernel_Wrapper4dim3S_
.cfi_endproc
# -- End function
.globl _Z36__device_stub__globalMemStrideKernelv # -- Begin function _Z36__device_stub__globalMemStrideKernelv
.p2align 4, 0x90
.type _Z36__device_stub__globalMemStrideKernelv,@function
_Z36__device_stub__globalMemStrideKernelv: # @_Z36__device_stub__globalMemStrideKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemStrideKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z36__device_stub__globalMemStrideKernelv, .Lfunc_end2-_Z36__device_stub__globalMemStrideKernelv
.cfi_endproc
# -- End function
.globl _Z29globalMemStrideKernel_Wrapper4dim3S_ # -- Begin function _Z29globalMemStrideKernel_Wrapper4dim3S_
.p2align 4, 0x90
.type _Z29globalMemStrideKernel_Wrapper4dim3S_,@function
_Z29globalMemStrideKernel_Wrapper4dim3S_: # @_Z29globalMemStrideKernel_Wrapper4dim3S_
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemStrideKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z29globalMemStrideKernel_Wrapper4dim3S_, .Lfunc_end3-_Z29globalMemStrideKernel_Wrapper4dim3S_
.cfi_endproc
# -- End function
.globl _Z36__device_stub__globalMemOffsetKernelv # -- Begin function _Z36__device_stub__globalMemOffsetKernelv
.p2align 4, 0x90
.type _Z36__device_stub__globalMemOffsetKernelv,@function
_Z36__device_stub__globalMemOffsetKernelv: # @_Z36__device_stub__globalMemOffsetKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemOffsetKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end4:
.size _Z36__device_stub__globalMemOffsetKernelv, .Lfunc_end4-_Z36__device_stub__globalMemOffsetKernelv
.cfi_endproc
# -- End function
.globl _Z29globalMemOffsetKernel_Wrapper4dim3S_ # -- Begin function _Z29globalMemOffsetKernel_Wrapper4dim3S_
.p2align 4, 0x90
.type _Z29globalMemOffsetKernel_Wrapper4dim3S_,@function
_Z29globalMemOffsetKernel_Wrapper4dim3S_: # @_Z29globalMemOffsetKernel_Wrapper4dim3S_
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB5_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB5_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemOffsetKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z29globalMemOffsetKernel_Wrapper4dim3S_, .Lfunc_end5-_Z29globalMemOffsetKernel_Wrapper4dim3S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24globalMemCoalescedKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21globalMemStrideKernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21globalMemOffsetKernelv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24globalMemCoalescedKernelv,@object # @_Z24globalMemCoalescedKernelv
.section .rodata,"a",@progbits
.globl _Z24globalMemCoalescedKernelv
.p2align 3, 0x0
_Z24globalMemCoalescedKernelv:
.quad _Z39__device_stub__globalMemCoalescedKernelv
.size _Z24globalMemCoalescedKernelv, 8
.type _Z21globalMemStrideKernelv,@object # @_Z21globalMemStrideKernelv
.globl _Z21globalMemStrideKernelv
.p2align 3, 0x0
_Z21globalMemStrideKernelv:
.quad _Z36__device_stub__globalMemStrideKernelv
.size _Z21globalMemStrideKernelv, 8
.type _Z21globalMemOffsetKernelv,@object # @_Z21globalMemOffsetKernelv
.globl _Z21globalMemOffsetKernelv
.p2align 3, 0x0
_Z21globalMemOffsetKernelv:
.quad _Z36__device_stub__globalMemOffsetKernelv
.size _Z21globalMemOffsetKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24globalMemCoalescedKernelv"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21globalMemStrideKernelv"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21globalMemOffsetKernelv"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__globalMemCoalescedKernelv
.addrsig_sym _Z36__device_stub__globalMemStrideKernelv
.addrsig_sym _Z36__device_stub__globalMemOffsetKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24globalMemCoalescedKernelv
.addrsig_sym _Z21globalMemStrideKernelv
.addrsig_sym _Z21globalMemOffsetKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21globalMemOffsetKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z21globalMemStrideKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24globalMemCoalescedKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24globalMemCoalescedKernelv
.globl _Z24globalMemCoalescedKernelv
.p2align 8
.type _Z24globalMemCoalescedKernelv,@function
_Z24globalMemCoalescedKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24globalMemCoalescedKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24globalMemCoalescedKernelv, .Lfunc_end0-_Z24globalMemCoalescedKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21globalMemStrideKernelv
.globl _Z21globalMemStrideKernelv
.p2align 8
.type _Z21globalMemStrideKernelv,@function
_Z21globalMemStrideKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21globalMemStrideKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z21globalMemStrideKernelv, .Lfunc_end1-_Z21globalMemStrideKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z21globalMemOffsetKernelv
.globl _Z21globalMemOffsetKernelv
.p2align 8
.type _Z21globalMemOffsetKernelv,@function
_Z21globalMemOffsetKernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21globalMemOffsetKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z21globalMemOffsetKernelv, .Lfunc_end2-_Z21globalMemOffsetKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24globalMemCoalescedKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z24globalMemCoalescedKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21globalMemStrideKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z21globalMemStrideKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21globalMemOffsetKernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z21globalMemOffsetKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014ceb8_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z24globalMemCoalescedKernelvv
.type _Z43__device_stub__Z24globalMemCoalescedKernelvv, @function
_Z43__device_stub__Z24globalMemCoalescedKernelvv:
.LFB2054:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z24globalMemCoalescedKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z43__device_stub__Z24globalMemCoalescedKernelvv, .-_Z43__device_stub__Z24globalMemCoalescedKernelvv
.globl _Z24globalMemCoalescedKernelv
.type _Z24globalMemCoalescedKernelv, @function
_Z24globalMemCoalescedKernelv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z24globalMemCoalescedKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z24globalMemCoalescedKernelv, .-_Z24globalMemCoalescedKernelv
.globl _Z32globalMemCoalescedKernel_Wrapper4dim3S_
.type _Z32globalMemCoalescedKernel_Wrapper4dim3S_, @function
_Z32globalMemCoalescedKernel_Wrapper4dim3S_:
.LFB2027:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ecx
movl $0, %r9d
movl $0, %r8d
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z43__device_stub__Z24globalMemCoalescedKernelvv
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z32globalMemCoalescedKernel_Wrapper4dim3S_, .-_Z32globalMemCoalescedKernel_Wrapper4dim3S_
.globl _Z40__device_stub__Z21globalMemStrideKernelvv
.type _Z40__device_stub__Z21globalMemStrideKernelvv, @function
_Z40__device_stub__Z21globalMemStrideKernelvv:
.LFB2056:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z21globalMemStrideKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z40__device_stub__Z21globalMemStrideKernelvv, .-_Z40__device_stub__Z21globalMemStrideKernelvv
.globl _Z21globalMemStrideKernelv
.type _Z21globalMemStrideKernelv, @function
_Z21globalMemStrideKernelv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z21globalMemStrideKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z21globalMemStrideKernelv, .-_Z21globalMemStrideKernelv
.globl _Z29globalMemStrideKernel_Wrapper4dim3S_
.type _Z29globalMemStrideKernel_Wrapper4dim3S_, @function
_Z29globalMemStrideKernel_Wrapper4dim3S_:
.LFB2028:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ecx
movl $0, %r9d
movl $0, %r8d
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call _Z40__device_stub__Z21globalMemStrideKernelvv
jmp .L23
.cfi_endproc
.LFE2028:
.size _Z29globalMemStrideKernel_Wrapper4dim3S_, .-_Z29globalMemStrideKernel_Wrapper4dim3S_
.globl _Z40__device_stub__Z21globalMemOffsetKernelvv
.type _Z40__device_stub__Z21globalMemOffsetKernelvv, @function
_Z40__device_stub__Z21globalMemOffsetKernelvv:
.LFB2058:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z21globalMemOffsetKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z40__device_stub__Z21globalMemOffsetKernelvv, .-_Z40__device_stub__Z21globalMemOffsetKernelvv
.globl _Z21globalMemOffsetKernelv
.type _Z21globalMemOffsetKernelv, @function
_Z21globalMemOffsetKernelv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z21globalMemOffsetKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z21globalMemOffsetKernelv, .-_Z21globalMemOffsetKernelv
.globl _Z29globalMemOffsetKernel_Wrapper4dim3S_
.type _Z29globalMemOffsetKernel_Wrapper4dim3S_, @function
_Z29globalMemOffsetKernel_Wrapper4dim3S_:
.LFB2029:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ecx
movl $0, %r9d
movl $0, %r8d
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
call _Z40__device_stub__Z21globalMemOffsetKernelvv
jmp .L35
.cfi_endproc
.LFE2029:
.size _Z29globalMemOffsetKernel_Wrapper4dim3S_, .-_Z29globalMemOffsetKernel_Wrapper4dim3S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z21globalMemOffsetKernelv"
.LC1:
.string "_Z21globalMemStrideKernelv"
.LC2:
.string "_Z24globalMemCoalescedKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21globalMemOffsetKernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z21globalMemStrideKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z24globalMemCoalescedKernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z39__device_stub__globalMemCoalescedKernelv # -- Begin function _Z39__device_stub__globalMemCoalescedKernelv
.p2align 4, 0x90
.type _Z39__device_stub__globalMemCoalescedKernelv,@function
_Z39__device_stub__globalMemCoalescedKernelv: # @_Z39__device_stub__globalMemCoalescedKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24globalMemCoalescedKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z39__device_stub__globalMemCoalescedKernelv, .Lfunc_end0-_Z39__device_stub__globalMemCoalescedKernelv
.cfi_endproc
# -- End function
.globl _Z32globalMemCoalescedKernel_Wrapper4dim3S_ # -- Begin function _Z32globalMemCoalescedKernel_Wrapper4dim3S_
.p2align 4, 0x90
.type _Z32globalMemCoalescedKernel_Wrapper4dim3S_,@function
_Z32globalMemCoalescedKernel_Wrapper4dim3S_: # @_Z32globalMemCoalescedKernel_Wrapper4dim3S_
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB1_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24globalMemCoalescedKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z32globalMemCoalescedKernel_Wrapper4dim3S_, .Lfunc_end1-_Z32globalMemCoalescedKernel_Wrapper4dim3S_
.cfi_endproc
# -- End function
.globl _Z36__device_stub__globalMemStrideKernelv # -- Begin function _Z36__device_stub__globalMemStrideKernelv
.p2align 4, 0x90
.type _Z36__device_stub__globalMemStrideKernelv,@function
_Z36__device_stub__globalMemStrideKernelv: # @_Z36__device_stub__globalMemStrideKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemStrideKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z36__device_stub__globalMemStrideKernelv, .Lfunc_end2-_Z36__device_stub__globalMemStrideKernelv
.cfi_endproc
# -- End function
.globl _Z29globalMemStrideKernel_Wrapper4dim3S_ # -- Begin function _Z29globalMemStrideKernel_Wrapper4dim3S_
.p2align 4, 0x90
.type _Z29globalMemStrideKernel_Wrapper4dim3S_,@function
_Z29globalMemStrideKernel_Wrapper4dim3S_: # @_Z29globalMemStrideKernel_Wrapper4dim3S_
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemStrideKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z29globalMemStrideKernel_Wrapper4dim3S_, .Lfunc_end3-_Z29globalMemStrideKernel_Wrapper4dim3S_
.cfi_endproc
# -- End function
.globl _Z36__device_stub__globalMemOffsetKernelv # -- Begin function _Z36__device_stub__globalMemOffsetKernelv
.p2align 4, 0x90
.type _Z36__device_stub__globalMemOffsetKernelv,@function
_Z36__device_stub__globalMemOffsetKernelv: # @_Z36__device_stub__globalMemOffsetKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemOffsetKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end4:
.size _Z36__device_stub__globalMemOffsetKernelv, .Lfunc_end4-_Z36__device_stub__globalMemOffsetKernelv
.cfi_endproc
# -- End function
.globl _Z29globalMemOffsetKernel_Wrapper4dim3S_ # -- Begin function _Z29globalMemOffsetKernel_Wrapper4dim3S_
.p2align 4, 0x90
.type _Z29globalMemOffsetKernel_Wrapper4dim3S_,@function
_Z29globalMemOffsetKernel_Wrapper4dim3S_: # @_Z29globalMemOffsetKernel_Wrapper4dim3S_
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB5_1
# %bb.2:
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.LBB5_1:
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z21globalMemOffsetKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z29globalMemOffsetKernel_Wrapper4dim3S_, .Lfunc_end5-_Z29globalMemOffsetKernel_Wrapper4dim3S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24globalMemCoalescedKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21globalMemStrideKernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21globalMemOffsetKernelv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24globalMemCoalescedKernelv,@object # @_Z24globalMemCoalescedKernelv
.section .rodata,"a",@progbits
.globl _Z24globalMemCoalescedKernelv
.p2align 3, 0x0
_Z24globalMemCoalescedKernelv:
.quad _Z39__device_stub__globalMemCoalescedKernelv
.size _Z24globalMemCoalescedKernelv, 8
.type _Z21globalMemStrideKernelv,@object # @_Z21globalMemStrideKernelv
.globl _Z21globalMemStrideKernelv
.p2align 3, 0x0
_Z21globalMemStrideKernelv:
.quad _Z36__device_stub__globalMemStrideKernelv
.size _Z21globalMemStrideKernelv, 8
.type _Z21globalMemOffsetKernelv,@object # @_Z21globalMemOffsetKernelv
.globl _Z21globalMemOffsetKernelv
.p2align 3, 0x0
_Z21globalMemOffsetKernelv:
.quad _Z36__device_stub__globalMemOffsetKernelv
.size _Z21globalMemOffsetKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24globalMemCoalescedKernelv"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z21globalMemStrideKernelv"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z21globalMemOffsetKernelv"
.size .L__unnamed_3, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__globalMemCoalescedKernelv
.addrsig_sym _Z36__device_stub__globalMemStrideKernelv
.addrsig_sym _Z36__device_stub__globalMemOffsetKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24globalMemCoalescedKernelv
.addrsig_sym _Z21globalMemStrideKernelv
.addrsig_sym _Z21globalMemOffsetKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
//#include <stdlib.h>
#include <unistd.h>
#define BLOCK_SIZE 1024
#define GRID_SIZE 38400
extern "C" {
__global__ void mul_matrix(int *A, int *B, int *C, int size){
int i = threadIdx.x + blockDim.x * blockIdx.x;
int sum = 0;
if(i < size){
__syncthreads();
sum = A[i] + B[i];
C[i] = sum;
}
}
// CUDA code here
int cuda_matrixMul(int *a_h, int *b_h, int *c_h, int size, int device_id){
cudaError_t err;
int *a_d, *b_d, *c_d;
printf("C: device id >> %d\n", device_id);
cudaSetDevice(device_id);
//printf("C: Allocate GPU Memory1\n");
// allocate memory in the GPU device for a, b and c
err = cudaMalloc((void **) & a_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMalloc((void **) & b_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMalloc((void **) & c_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
// copy from host to GPU device
//printf("C: Memory Copy tost to device(Size %d)\n", size);
err = cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
int N = size / 4;
// do calculations on device
dim3 block(BLOCK_SIZE, 1, 1);
dim3 grid(N/BLOCK_SIZE, 1, 1);
// Launch GPU
printf("C: Launch(size = %d)\n", N);
mul_matrix<<<grid, block>>>(a_d, b_d, c_d, N);
cudaDeviceSynchronize();
//printf("C: Memory Copy device to host\n");
err = cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaDeviceSynchronize();
for(int i = 0; i < (size/4); i++) {
if(c_h[i] != i+i){
printf("C: Mismatch (c[%d] = %d)\n", i , c_h[i]);
exit(-1);
}
}
//printf("C: Memory Free\n");
cudaFree(a_d);
return 0;
}
} | code for sm_80
Function : mul_matrix
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fca00000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0090*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
//#include <stdlib.h>
#include <unistd.h>
#define BLOCK_SIZE 1024
#define GRID_SIZE 38400
extern "C" {
__global__ void mul_matrix(int *A, int *B, int *C, int size){
int i = threadIdx.x + blockDim.x * blockIdx.x;
int sum = 0;
if(i < size){
__syncthreads();
sum = A[i] + B[i];
C[i] = sum;
}
}
// CUDA code here
int cuda_matrixMul(int *a_h, int *b_h, int *c_h, int size, int device_id){
cudaError_t err;
int *a_d, *b_d, *c_d;
printf("C: device id >> %d\n", device_id);
cudaSetDevice(device_id);
//printf("C: Allocate GPU Memory1\n");
// allocate memory in the GPU device for a, b and c
err = cudaMalloc((void **) & a_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMalloc((void **) & b_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMalloc((void **) & c_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
// copy from host to GPU device
//printf("C: Memory Copy tost to device(Size %d)\n", size);
err = cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
int N = size / 4;
// do calculations on device
dim3 block(BLOCK_SIZE, 1, 1);
dim3 grid(N/BLOCK_SIZE, 1, 1);
// Launch GPU
printf("C: Launch(size = %d)\n", N);
mul_matrix<<<grid, block>>>(a_d, b_d, c_d, N);
cudaDeviceSynchronize();
//printf("C: Memory Copy device to host\n");
err = cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaDeviceSynchronize();
for(int i = 0; i < (size/4); i++) {
if(c_h[i] != i+i){
printf("C: Mismatch (c[%d] = %d)\n", i , c_h[i]);
exit(-1);
}
}
//printf("C: Memory Free\n");
cudaFree(a_d);
return 0;
}
} | .file "tmpxft_001bb57d_00000000-6_kernel_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mul_matrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
.globl mul_matrix
.type mul_matrix, @function
mul_matrix:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size mul_matrix, .-mul_matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "C: device id >> %d\n"
.LC1:
.string "CUDA error(1): %s\n"
.LC2:
.string "CUDA error(4): %s\n"
.LC3:
.string "C: Launch(size = %d)\n"
.LC4:
.string "C: Mismatch (c[%d] = %d)\n"
.text
.globl cuda_matrixMul
.type cuda_matrixMul, @function
cuda_matrixMul:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbp
movl %ecx, %r12d
movl %r8d, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %r8d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %ebx, %edi
call cudaSetDevice@PLT
movslq %r12d, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
leal 3(%r12), %ebx
testl %r12d, %r12d
cmovns %r12d, %ebx
sarl $2, %ebx
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
leal 4095(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $12, %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L17:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
call cudaDeviceSynchronize@PLT
cmpl $3, %r12d
jle .L19
movl $0, %eax
.L21:
movl 0(%rbp,%rax,4), %ecx
leal (%rax,%rax), %edx
cmpl %edx, %ecx
jne .L32
addq $1, %rax
cmpl %eax, %ebx
jg .L21
.L19:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
movl %ebx, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
jmp .L17
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size cuda_matrixMul, .-cuda_matrixMul
.section .rodata.str1.1
.LC5:
.string "mul_matrix"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq mul_matrix(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//#include <stdlib.h>
#include <unistd.h>
#define BLOCK_SIZE 1024
#define GRID_SIZE 38400
extern "C" {
__global__ void mul_matrix(int *A, int *B, int *C, int size){
int i = threadIdx.x + blockDim.x * blockIdx.x;
int sum = 0;
if(i < size){
__syncthreads();
sum = A[i] + B[i];
C[i] = sum;
}
}
// CUDA code here
int cuda_matrixMul(int *a_h, int *b_h, int *c_h, int size, int device_id){
cudaError_t err;
int *a_d, *b_d, *c_d;
printf("C: device id >> %d\n", device_id);
cudaSetDevice(device_id);
//printf("C: Allocate GPU Memory1\n");
// allocate memory in the GPU device for a, b and c
err = cudaMalloc((void **) & a_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMalloc((void **) & b_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMalloc((void **) & c_d, size);
if (err != cudaSuccess){
printf("CUDA error(1): %s\n", cudaGetErrorString(err));
exit(-1);
}
// copy from host to GPU device
//printf("C: Memory Copy tost to device(Size %d)\n", size);
err = cudaMemcpy(a_d, a_h, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
err = cudaMemcpy(b_d, b_h, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
int N = size / 4;
// do calculations on device
dim3 block(BLOCK_SIZE, 1, 1);
dim3 grid(N/BLOCK_SIZE, 1, 1);
// Launch GPU
printf("C: Launch(size = %d)\n", N);
mul_matrix<<<grid, block>>>(a_d, b_d, c_d, N);
cudaDeviceSynchronize();
//printf("C: Memory Copy device to host\n");
err = cudaMemcpy(c_h, c_d, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess){
printf("CUDA error(4): %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaDeviceSynchronize();
for(int i = 0; i < (size/4); i++) {
if(c_h[i] != i+i){
printf("C: Mismatch (c[%d] = %d)\n", i , c_h[i]);
exit(-1);
}
}
//printf("C: Memory Free\n");
cudaFree(a_d);
return 0;
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <stdlib.h>
#include <unistd.h>
#define BLOCK_SIZE 1024
#define GRID_SIZE 38400
extern "C" {
__global__ void mul_matrix(int *A, int *B, int *C, int size){
int i = threadIdx.x + blockDim.x * blockIdx.x;
int sum = 0;
if(i < size){
__syncthreads();
sum = A[i] + B[i];
C[i] = sum;
}
}
// CUDA code here
int cuda_matrixMul(int *a_h, int *b_h, int *c_h, int size, int device_id){
hipError_t err;
int *a_d, *b_d, *c_d;
printf("C: device id >> %d\n", device_id);
hipSetDevice(device_id);
//printf("C: Allocate GPU Memory1\n");
// allocate memory in the GPU device for a, b and c
err = hipMalloc((void **) & a_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMalloc((void **) & b_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMalloc((void **) & c_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
// copy from host to GPU device
//printf("C: Memory Copy tost to device(Size %d)\n", size);
err = hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
int N = size / 4;
// do calculations on device
dim3 block(BLOCK_SIZE, 1, 1);
dim3 grid(N/BLOCK_SIZE, 1, 1);
// Launch GPU
printf("C: Launch(size = %d)\n", N);
mul_matrix<<<grid, block>>>(a_d, b_d, c_d, N);
hipDeviceSynchronize();
//printf("C: Memory Copy device to host\n");
err = hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
hipDeviceSynchronize();
for(int i = 0; i < (size/4); i++) {
if(c_h[i] != i+i){
printf("C: Mismatch (c[%d] = %d)\n", i , c_h[i]);
exit(-1);
}
}
//printf("C: Memory Free\n");
hipFree(a_d);
return 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <stdlib.h>
#include <unistd.h>
#define BLOCK_SIZE 1024
#define GRID_SIZE 38400
extern "C" {
__global__ void mul_matrix(int *A, int *B, int *C, int size){
int i = threadIdx.x + blockDim.x * blockIdx.x;
int sum = 0;
if(i < size){
__syncthreads();
sum = A[i] + B[i];
C[i] = sum;
}
}
// CUDA code here
int cuda_matrixMul(int *a_h, int *b_h, int *c_h, int size, int device_id){
hipError_t err;
int *a_d, *b_d, *c_d;
printf("C: device id >> %d\n", device_id);
hipSetDevice(device_id);
//printf("C: Allocate GPU Memory1\n");
// allocate memory in the GPU device for a, b and c
err = hipMalloc((void **) & a_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMalloc((void **) & b_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMalloc((void **) & c_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
// copy from host to GPU device
//printf("C: Memory Copy tost to device(Size %d)\n", size);
err = hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
int N = size / 4;
// do calculations on device
dim3 block(BLOCK_SIZE, 1, 1);
dim3 grid(N/BLOCK_SIZE, 1, 1);
// Launch GPU
printf("C: Launch(size = %d)\n", N);
mul_matrix<<<grid, block>>>(a_d, b_d, c_d, N);
hipDeviceSynchronize();
//printf("C: Memory Copy device to host\n");
err = hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
hipDeviceSynchronize();
for(int i = 0; i < (size/4); i++) {
if(c_h[i] != i+i){
printf("C: Mismatch (c[%d] = %d)\n", i , c_h[i]);
exit(-1);
}
}
//printf("C: Memory Free\n");
hipFree(a_d);
return 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mul_matrix
.globl mul_matrix
.p2align 8
.type mul_matrix,@function
mul_matrix:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mul_matrix
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mul_matrix, .Lfunc_end0-mul_matrix
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mul_matrix
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mul_matrix.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//#include <stdlib.h>
#include <unistd.h>
#define BLOCK_SIZE 1024
#define GRID_SIZE 38400
extern "C" {
__global__ void mul_matrix(int *A, int *B, int *C, int size){
int i = threadIdx.x + blockDim.x * blockIdx.x;
int sum = 0;
if(i < size){
__syncthreads();
sum = A[i] + B[i];
C[i] = sum;
}
}
// CUDA code here
int cuda_matrixMul(int *a_h, int *b_h, int *c_h, int size, int device_id){
hipError_t err;
int *a_d, *b_d, *c_d;
printf("C: device id >> %d\n", device_id);
hipSetDevice(device_id);
//printf("C: Allocate GPU Memory1\n");
// allocate memory in the GPU device for a, b and c
err = hipMalloc((void **) & a_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMalloc((void **) & b_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMalloc((void **) & c_d, size);
if (err != hipSuccess){
printf("CUDA error(1): %s\n", hipGetErrorString(err));
exit(-1);
}
// copy from host to GPU device
//printf("C: Memory Copy tost to device(Size %d)\n", size);
err = hipMemcpy(a_d, a_h, size, hipMemcpyHostToDevice);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
err = hipMemcpy(b_d, b_h, size, hipMemcpyHostToDevice);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
int N = size / 4;
// do calculations on device
dim3 block(BLOCK_SIZE, 1, 1);
dim3 grid(N/BLOCK_SIZE, 1, 1);
// Launch GPU
printf("C: Launch(size = %d)\n", N);
mul_matrix<<<grid, block>>>(a_d, b_d, c_d, N);
hipDeviceSynchronize();
//printf("C: Memory Copy device to host\n");
err = hipMemcpy(c_h, c_d, size, hipMemcpyDeviceToHost);
if (err != hipSuccess){
printf("CUDA error(4): %s\n", hipGetErrorString(err));
exit(-1);
}
hipDeviceSynchronize();
for(int i = 0; i < (size/4); i++) {
if(c_h[i] != i+i){
printf("C: Mismatch (c[%d] = %d)\n", i , c_h[i]);
exit(-1);
}
}
//printf("C: Memory Free\n");
hipFree(a_d);
return 0;
}
} | .text
.file "kernel_code.hip"
.globl __device_stub__mul_matrix # -- Begin function __device_stub__mul_matrix
.p2align 4, 0x90
.type __device_stub__mul_matrix,@function
__device_stub__mul_matrix: # @__device_stub__mul_matrix
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mul_matrix, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__mul_matrix, .Lfunc_end0-__device_stub__mul_matrix
.cfi_endproc
# -- End function
.globl cuda_matrixMul # -- Begin function cuda_matrixMul
.p2align 4, 0x90
.type cuda_matrixMul,@function
cuda_matrixMul: # @cuda_matrixMul
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r14d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movl $.L.str, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipSetDevice
movslq %r14d, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.5:
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leal 3(%r14), %ebp
leal 4095(%r14), %r12d
testl %r14d, %r14d
cmovnsl %r14d, %ebp
cmovnsl %r14d, %r12d
sarl $2, %ebp
sarl $12, %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
orq $1024, %r13 # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $mul_matrix, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.11:
callq hipDeviceSynchronize
cmpl $4, %r14d
jl .LBB1_15
# %bb.12: # %.lr.ph.preheader
movl %ebp, %eax
addq %rax, %rax
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,2), %edx
cmpq %rdx, %rcx
jne .LBB1_16
# %bb.14: # in Loop: Header=BB1_13 Depth=1
incl %esi
addq $2, %rcx
cmpq %rcx, %rax
jne .LBB1_13
.LBB1_15: # %._crit_edge
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 208
movl $.L.str.4, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB1_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
jmp .LBB1_2
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
.LBB1_2:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size cuda_matrixMul, .Lfunc_end1-cuda_matrixMul
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mul_matrix, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type mul_matrix,@object # @mul_matrix
.section .rodata,"a",@progbits
.globl mul_matrix
.p2align 3, 0x0
mul_matrix:
.quad __device_stub__mul_matrix
.size mul_matrix, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "C: device id >> %d\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA error(1): %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA error(4): %s\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "C: Launch(size = %d)\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "C: Mismatch (c[%d] = %d)\n"
.size .L.str.4, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "mul_matrix"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mul_matrix
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mul_matrix
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : mul_matrix
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fca00000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0090*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00e0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mul_matrix
.globl mul_matrix
.p2align 8
.type mul_matrix,@function
mul_matrix:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mul_matrix
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mul_matrix, .Lfunc_end0-mul_matrix
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mul_matrix
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mul_matrix.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bb57d_00000000-6_kernel_code.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i:
.LFB2095:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mul_matrix(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
.globl mul_matrix
.type mul_matrix, @function
mul_matrix:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size mul_matrix, .-mul_matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "C: device id >> %d\n"
.LC1:
.string "CUDA error(1): %s\n"
.LC2:
.string "CUDA error(4): %s\n"
.LC3:
.string "C: Launch(size = %d)\n"
.LC4:
.string "C: Mismatch (c[%d] = %d)\n"
.text
.globl cuda_matrixMul
.type cuda_matrixMul, @function
cuda_matrixMul:
.LFB2070:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbp
movl %ecx, %r12d
movl %r8d, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %r8d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl %ebx, %edi
call cudaSetDevice@PLT
movslq %r12d, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L27
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
leal 3(%r12), %ebx
testl %r12d, %r12d
cmovns %r12d, %ebx
sarl $2, %ebx
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
leal 4095(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $12, %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L17:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L31
call cudaDeviceSynchronize@PLT
cmpl $3, %r12d
jle .L19
movl $0, %eax
.L21:
movl 0(%rbp,%rax,4), %ecx
leal (%rax,%rax), %edx
cmpl %edx, %ecx
jne .L32
addq $1, %rax
cmpl %eax, %ebx
jg .L21
.L19:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L30:
movl %ebx, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10mul_matrixPiS_S_iPiS_S_i
jmp .L17
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L32:
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size cuda_matrixMul, .-cuda_matrixMul
.section .rodata.str1.1
.LC5:
.string "mul_matrix"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq mul_matrix(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_code.hip"
.globl __device_stub__mul_matrix # -- Begin function __device_stub__mul_matrix
.p2align 4, 0x90
.type __device_stub__mul_matrix,@function
__device_stub__mul_matrix: # @__device_stub__mul_matrix
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mul_matrix, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__mul_matrix, .Lfunc_end0-__device_stub__mul_matrix
.cfi_endproc
# -- End function
.globl cuda_matrixMul # -- Begin function cuda_matrixMul
.p2align 4, 0x90
.type cuda_matrixMul,@function
cuda_matrixMul: # @cuda_matrixMul
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %r14d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movl $.L.str, %edi
movl %r8d, %esi
xorl %eax, %eax
callq printf
movl %ebp, %edi
callq hipSetDevice
movslq %r14d, %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.5:
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 32(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leal 3(%r14), %ebp
leal 4095(%r14), %r12d
testl %r14d, %r14d
cmovnsl %r14d, %ebp
cmovnsl %r14d, %r12d
sarl $2, %ebp
sarl $12, %r12d
movabsq $4294967296, %r13 # imm = 0x100000000
orq %r13, %r12
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
orq $1024, %r13 # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 20(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $mul_matrix, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.11:
callq hipDeviceSynchronize
cmpl $4, %r14d
jl .LBB1_15
# %bb.12: # %.lr.ph.preheader
movl %ebp, %eax
addq %rax, %rax
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_13: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,2), %edx
cmpq %rdx, %rcx
jne .LBB1_16
# %bb.14: # in Loop: Header=BB1_13 Depth=1
incl %esi
addq $2, %rcx
cmpq %rcx, %rax
jne .LBB1_13
.LBB1_15: # %._crit_edge
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 208
movl $.L.str.4, %edi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB1_1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
jmp .LBB1_2
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
.LBB1_2:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size cuda_matrixMul, .Lfunc_end1-cuda_matrixMul
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mul_matrix, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type mul_matrix,@object # @mul_matrix
.section .rodata,"a",@progbits
.globl mul_matrix
.p2align 3, 0x0
mul_matrix:
.quad __device_stub__mul_matrix
.size mul_matrix, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "C: device id >> %d\n"
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA error(1): %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA error(4): %s\n"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "C: Launch(size = %d)\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "C: Mismatch (c[%d] = %d)\n"
.size .L.str.4, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "mul_matrix"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mul_matrix
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mul_matrix
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "GalaxyCollision.cuh"
__device__ int doPrint = 0;
__device__
float3 bodiesInteraction2(float4 body1, float4 body2, float3 acceleration)
{
float EPS2 = 0.1f;
float3 r;
r.x = body2.x - body1.x;
r.y = body2.y - body1.y;
r.z = body2.z - body1.z;
// distSqr = dot(r_ij, r_ij) + EPS^2 [6 FLOPS]
float distSqr = sqrtf(r.x * r.x + r.y * r.y + r.z * r.z);
distSqr *= distSqr;
distSqr += EPS2;
// invDistCube =1/distSqr^(3/2) [4 FLOPS (2 mul, 1 sqrt, 1 inv)]
float distSixth = distSqr * distSqr * distSqr;
float invDistCube = 1.0f / sqrtf(distSixth);
// s = m_j * invDistCube [1 FLOP]
float s = body2.w * invDistCube;
acceleration.x += r.x * s;
acceleration.y += r.y * s;
acceleration.z += r.z * s;
return acceleration;
}
__device__
float3 bodiesInteraction(float4 body1, float4 body2, float3 acceleration)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
float EPS2 = 0.01f;
float ep = 1.0f;
float3 r;
r.x = body2.x - body1.x;
r.y = body2.y - body1.y;
r.z = body2.z - body1.z;
float distSqr = (r.x * r.x) + (r.y * r.y) + (r.z * r.z);
//distSqr *= distSqr;
distSqr += EPS2;
float dist = sqrtf(distSqr);
float distCube = dist * dist * dist;
float s = (body2.w) / distCube;
acceleration.x += r.x * s * ep;
acceleration.y += r.y * s * ep;
acceleration.z += r.z * s * ep;
/*
if(tid == 0 && r.y > 10.0)
{
doPrint = 99;
printf("\n");
printf("body1.w: %lf \n", body1.w);
printf("body2.w: %lf \n", body2.w);
printf("\n");
printf("r.x: %lf \n", r.x);
printf("r.y: %lf \n", r.y);
printf("r.z: %lf \n", r.z);
printf("\n");
printf("distSqr: %lf \n", distSqr);
printf("dist: %lf \n", dist);
printf("distCube: %lf \n", distCube);
printf("s: %lf \n", s);
printf("\n");
printf("acc.x: %lf \n", acceleration.x);
printf("acc.y: %lf \n", acceleration.y);
printf("acc.z: %lf \n", acceleration.z);
}
*/
return acceleration;
}
__device__
float3 tileAcceleration(float4 currPosition, float3 acceleration)
{
int i;
extern __shared__ float4 shPosition[];
for (i = 0; i < blockDim.x; i++) {
acceleration = bodiesInteraction(currPosition, shPosition[i], acceleration);
}
return acceleration;
}
__global__
void calculateForcesKernel(float4* bodyDescription, float3* acceleration, int size)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size)
{
extern __shared__ float4 shPosition[];
float4 currPosition;
float3 acc = { 0.0f, 0.0f, 0.0f };
int i, tile;
currPosition = bodyDescription[tid];
for (i = 0, tile = 0; i < size; i += blockDim.x, tile++)
{
int idx = tile * blockDim.x + threadIdx.x;
if (idx < size){
shPosition[threadIdx.x] = bodyDescription[idx];
__syncthreads();
acc = tileAcceleration(currPosition, acc);
__syncthreads();
}
}
// Save the result in global memory for the integration step.
acceleration[tid] = acc;
}
}
__host__
void galaxyCollisionLogic(float4* d_bodyDescription, float3* d_acceleration, int size)
{
double4 test;
dim3 DimGrid((size / MAX_BLOCK_THREAD_COUNT) + 1, 1, 1);
dim3 DimBlock(MAX_BLOCK_THREAD_COUNT, 1, 1);
//printf("DimGrid: x: %d, y: %d, z: %d \n", DimGrid.x, DimGrid.y, DimGrid.z);
//printf("DimBlock: x: %d, y: %d, z: %d \n\n", DimBlock.x, DimBlock.y, DimBlock.z);
calculateForcesKernel << <DimGrid, DimBlock, MAX_BLOCK_THREAD_COUNT * sizeof(float4)>> >
(d_bodyDescription, d_acceleration, size);
cudaDeviceSynchronize();
doPrint = 0;
}
__host__
void galaxyCollisionInit(float4* bodyDescription, float3* acceleration, int count)
{
float4* d_bodyDescription;
float3* d_acceleration;
int sizef3 = count * sizeof(float3);
int sizef4 = count * sizeof(float4);
cudaError_t err;
/*********** MEMORY ALLOCATION ***********/
if ((err = cudaMalloc((void**)&d_bodyDescription, sizef4)) != cudaSuccess) C_ERR(err);
if ((err = cudaMalloc((void**)&d_acceleration, sizef3)) != cudaSuccess) C_ERR(err);
/*********** COPY MEMORY TO DEVICE ***********/
if ((err = cudaMemcpy(d_bodyDescription, bodyDescription, sizef4, cudaMemcpyHostToDevice)) != cudaSuccess) C_ERR(err);
//if ((err = cudaMemcpy(d_acceleration, acceleration, sizef3, cudaMemcpyHostToDevice)) != cudaSuccess) ERR(err);
// Work
galaxyCollisionLogic(d_bodyDescription, d_acceleration, count);
/*********** COPY MEMORY BACK TO HOST ***********/
if ((err = cudaMemcpy(acceleration, d_acceleration, sizef3, cudaMemcpyDeviceToHost)) != cudaSuccess) C_ERR(err);
/*********** FREE MEMORY ***********/
if ((err = cudaFree(d_bodyDescription)) != cudaSuccess) C_ERR(err);
if ((err = cudaFree(d_acceleration)) != cudaSuccess) C_ERR(err);
// Update galaxies ...
/*
for (int i = 0; i < count; i+=100)
{
printf("Acc: %lf, %lf, %lf\n", acceleration[i].x, acceleration[i].y, acceleration[i].z);
}*/
// Init the body description - position and mass
} | .file "tmpxft_001b5927_00000000-6_GalaxyCollision.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18bodiesInteraction26float4S_6float3
.type _Z18bodiesInteraction26float4S_6float3, @function
_Z18bodiesInteraction26float4S_6float3:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm4, (%rsp)
movss %xmm5, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z18bodiesInteraction26float4S_6float3, .-_Z18bodiesInteraction26float4S_6float3
.globl _Z17bodiesInteraction6float4S_6float3
.type _Z17bodiesInteraction6float4S_6float3, @function
_Z17bodiesInteraction6float4S_6float3:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm4, (%rsp)
movss %xmm5, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z17bodiesInteraction6float4S_6float3, .-_Z17bodiesInteraction6float4S_6float3
.globl _Z16tileAcceleration6float46float3
.type _Z16tileAcceleration6float46float3, @function
_Z16tileAcceleration6float46float3:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z16tileAcceleration6float46float3, .-_Z16tileAcceleration6float46float3
.globl _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
.type _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i, @function
_Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21calculateForcesKernelP6float4P6float3i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i, .-_Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
.globl _Z21calculateForcesKernelP6float4P6float3i
.type _Z21calculateForcesKernelP6float4P6float3i, @function
_Z21calculateForcesKernelP6float4P6float3i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z21calculateForcesKernelP6float4P6float3i, .-_Z21calculateForcesKernelP6float4P6float3i
.globl _Z20galaxyCollisionLogicP6float4P6float3i
.type _Z20galaxyCollisionLogicP6float4P6float3i, @function
_Z20galaxyCollisionLogicP6float4P6float3i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L18:
call cudaDeviceSynchronize@PLT
movl $0, _ZL7doPrint(%rip)
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z20galaxyCollisionLogicP6float4P6float3i, .-_Z20galaxyCollisionLogicP6float4P6float3i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Jakub-Ciecierski/GalaxyCollisionCUDA/master/src/cuda/GalaxyCollision.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z19galaxyCollisionInitP6float4P6float3i
.type _Z19galaxyCollisionInitP6float4P6float3i, @function
_Z19galaxyCollisionInitP6float4P6float3i:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r14
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leal (%rdx,%rdx,2), %ebp
sall $2, %ebp
movl %edx, %r12d
sall $4, %r12d
movslq %r12d, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
movslq %ebp, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z20galaxyCollisionLogicP6float4P6float3i
movl $2, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L34
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L35
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $163, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $164, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $167, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $174, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $177, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $178, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z19galaxyCollisionInitP6float4P6float3i, .-_Z19galaxyCollisionInitP6float4P6float3i
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z21calculateForcesKernelP6float4P6float3i"
.section .rodata.str1.1
.LC3:
.string "doPrint"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21calculateForcesKernelP6float4P6float3i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7doPrint(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7doPrint
.comm _ZL7doPrint,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "GalaxyCollision.cuh"
__device__ int doPrint = 0;
__device__
float3 bodiesInteraction2(float4 body1, float4 body2, float3 acceleration)
{
float EPS2 = 0.1f;
float3 r;
r.x = body2.x - body1.x;
r.y = body2.y - body1.y;
r.z = body2.z - body1.z;
// distSqr = dot(r_ij, r_ij) + EPS^2 [6 FLOPS]
float distSqr = sqrtf(r.x * r.x + r.y * r.y + r.z * r.z);
distSqr *= distSqr;
distSqr += EPS2;
// invDistCube =1/distSqr^(3/2) [4 FLOPS (2 mul, 1 sqrt, 1 inv)]
float distSixth = distSqr * distSqr * distSqr;
float invDistCube = 1.0f / sqrtf(distSixth);
// s = m_j * invDistCube [1 FLOP]
float s = body2.w * invDistCube;
acceleration.x += r.x * s;
acceleration.y += r.y * s;
acceleration.z += r.z * s;
return acceleration;
}
__device__
float3 bodiesInteraction(float4 body1, float4 body2, float3 acceleration)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
float EPS2 = 0.01f;
float ep = 1.0f;
float3 r;
r.x = body2.x - body1.x;
r.y = body2.y - body1.y;
r.z = body2.z - body1.z;
float distSqr = (r.x * r.x) + (r.y * r.y) + (r.z * r.z);
//distSqr *= distSqr;
distSqr += EPS2;
float dist = sqrtf(distSqr);
float distCube = dist * dist * dist;
float s = (body2.w) / distCube;
acceleration.x += r.x * s * ep;
acceleration.y += r.y * s * ep;
acceleration.z += r.z * s * ep;
/*
if(tid == 0 && r.y > 10.0)
{
doPrint = 99;
printf("\n");
printf("body1.w: %lf \n", body1.w);
printf("body2.w: %lf \n", body2.w);
printf("\n");
printf("r.x: %lf \n", r.x);
printf("r.y: %lf \n", r.y);
printf("r.z: %lf \n", r.z);
printf("\n");
printf("distSqr: %lf \n", distSqr);
printf("dist: %lf \n", dist);
printf("distCube: %lf \n", distCube);
printf("s: %lf \n", s);
printf("\n");
printf("acc.x: %lf \n", acceleration.x);
printf("acc.y: %lf \n", acceleration.y);
printf("acc.z: %lf \n", acceleration.z);
}
*/
return acceleration;
}
__device__
float3 tileAcceleration(float4 currPosition, float3 acceleration)
{
int i;
extern __shared__ float4 shPosition[];
for (i = 0; i < blockDim.x; i++) {
acceleration = bodiesInteraction(currPosition, shPosition[i], acceleration);
}
return acceleration;
}
__global__
void calculateForcesKernel(float4* bodyDescription, float3* acceleration, int size)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size)
{
extern __shared__ float4 shPosition[];
float4 currPosition;
float3 acc = { 0.0f, 0.0f, 0.0f };
int i, tile;
currPosition = bodyDescription[tid];
for (i = 0, tile = 0; i < size; i += blockDim.x, tile++)
{
int idx = tile * blockDim.x + threadIdx.x;
if (idx < size){
shPosition[threadIdx.x] = bodyDescription[idx];
__syncthreads();
acc = tileAcceleration(currPosition, acc);
__syncthreads();
}
}
// Save the result in global memory for the integration step.
acceleration[tid] = acc;
}
}
__host__
void galaxyCollisionLogic(float4* d_bodyDescription, float3* d_acceleration, int size)
{
double4 test;
dim3 DimGrid((size / MAX_BLOCK_THREAD_COUNT) + 1, 1, 1);
dim3 DimBlock(MAX_BLOCK_THREAD_COUNT, 1, 1);
//printf("DimGrid: x: %d, y: %d, z: %d \n", DimGrid.x, DimGrid.y, DimGrid.z);
//printf("DimBlock: x: %d, y: %d, z: %d \n\n", DimBlock.x, DimBlock.y, DimBlock.z);
calculateForcesKernel << <DimGrid, DimBlock, MAX_BLOCK_THREAD_COUNT * sizeof(float4)>> >
(d_bodyDescription, d_acceleration, size);
cudaDeviceSynchronize();
doPrint = 0;
}
__host__
void galaxyCollisionInit(float4* bodyDescription, float3* acceleration, int count)
{
float4* d_bodyDescription;
float3* d_acceleration;
int sizef3 = count * sizeof(float3);
int sizef4 = count * sizeof(float4);
cudaError_t err;
/*********** MEMORY ALLOCATION ***********/
if ((err = cudaMalloc((void**)&d_bodyDescription, sizef4)) != cudaSuccess) C_ERR(err);
if ((err = cudaMalloc((void**)&d_acceleration, sizef3)) != cudaSuccess) C_ERR(err);
/*********** COPY MEMORY TO DEVICE ***********/
if ((err = cudaMemcpy(d_bodyDescription, bodyDescription, sizef4, cudaMemcpyHostToDevice)) != cudaSuccess) C_ERR(err);
//if ((err = cudaMemcpy(d_acceleration, acceleration, sizef3, cudaMemcpyHostToDevice)) != cudaSuccess) ERR(err);
// Work
galaxyCollisionLogic(d_bodyDescription, d_acceleration, count);
/*********** COPY MEMORY BACK TO HOST ***********/
if ((err = cudaMemcpy(acceleration, d_acceleration, sizef3, cudaMemcpyDeviceToHost)) != cudaSuccess) C_ERR(err);
/*********** FREE MEMORY ***********/
if ((err = cudaFree(d_bodyDescription)) != cudaSuccess) C_ERR(err);
if ((err = cudaFree(d_acceleration)) != cudaSuccess) C_ERR(err);
// Update galaxies ...
/*
for (int i = 0; i < count; i+=100)
{
printf("Acc: %lf, %lf, %lf\n", acceleration[i].x, acceleration[i].y, acceleration[i].z);
}*/
// Init the body description - position and mass
} | #ifndef _SHORTEST_CUDA_H_
#define _SHORTEST_CUDA_H_
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "hip/hip_runtime.h"
#define MAX_GRID_DIM_SIZE 65535
#define MAX_BLOCK_THREAD_COUNT 512
#define MAX_BLOCK_DIM_SIZE 32
#define C_ERR(err) (printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__),\
exit(EXIT_FAILURE))
__device__
float3 bodiesInteraction(float4 body1, float4 body2, float3 acceleration);
__device__
float3 tileAcceleration(float4 currPosition, float3 acceleration);
__global__
void calculateForcesKernel(float4* bodyDescription, float3* acceleration, int n);
__host__
void galaxyCollisionLogic(float4* d_bodyDescription, float3* d_acceleration, int n);
__host__
void galaxyCollisionInit(float4* bodyDescription, float3* acceleration, int count);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef _SHORTEST_CUDA_H_
#define _SHORTEST_CUDA_H_
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "hip/hip_runtime.h"
#define MAX_GRID_DIM_SIZE 65535
#define MAX_BLOCK_THREAD_COUNT 512
#define MAX_BLOCK_DIM_SIZE 32
#define C_ERR(err) (printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__),\
exit(EXIT_FAILURE))
__device__
float3 bodiesInteraction(float4 body1, float4 body2, float3 acceleration);
__device__
float3 tileAcceleration(float4 currPosition, float3 acceleration);
__global__
void calculateForcesKernel(float4* bodyDescription, float3* acceleration, int n);
__host__
void galaxyCollisionLogic(float4* d_bodyDescription, float3* d_acceleration, int n);
__host__
void galaxyCollisionInit(float4* bodyDescription, float3* acceleration, int count);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef _SHORTEST_CUDA_H_
#define _SHORTEST_CUDA_H_
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "hip/hip_runtime.h"
#define MAX_GRID_DIM_SIZE 65535
#define MAX_BLOCK_THREAD_COUNT 512
#define MAX_BLOCK_DIM_SIZE 32
#define C_ERR(err) (printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__),\
exit(EXIT_FAILURE))
__device__
float3 bodiesInteraction(float4 body1, float4 body2, float3 acceleration);
__device__
float3 tileAcceleration(float4 currPosition, float3 acceleration);
__global__
void calculateForcesKernel(float4* bodyDescription, float3* acceleration, int n);
__host__
void galaxyCollisionLogic(float4* d_bodyDescription, float3* d_acceleration, int n);
__host__
void galaxyCollisionInit(float4* bodyDescription, float3* acceleration, int count);
#endif | .text
.file "GalaxyCollision.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b5927_00000000-6_GalaxyCollision.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18bodiesInteraction26float4S_6float3
.type _Z18bodiesInteraction26float4S_6float3, @function
_Z18bodiesInteraction26float4S_6float3:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm4, (%rsp)
movss %xmm5, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z18bodiesInteraction26float4S_6float3, .-_Z18bodiesInteraction26float4S_6float3
.globl _Z17bodiesInteraction6float4S_6float3
.type _Z17bodiesInteraction6float4S_6float3, @function
_Z17bodiesInteraction6float4S_6float3:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm4, (%rsp)
movss %xmm5, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z17bodiesInteraction6float4S_6float3, .-_Z17bodiesInteraction6float4S_6float3
.globl _Z16tileAcceleration6float46float3
.type _Z16tileAcceleration6float46float3, @function
_Z16tileAcceleration6float46float3:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %xmm2, (%rsp)
movss %xmm3, 8(%rsp)
movl $1, 28(%rsp)
movl 28(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z16tileAcceleration6float46float3, .-_Z16tileAcceleration6float46float3
.globl _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
.type _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i, @function
_Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21calculateForcesKernelP6float4P6float3i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i, .-_Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
.globl _Z21calculateForcesKernelP6float4P6float3i
.type _Z21calculateForcesKernelP6float4P6float3i, @function
_Z21calculateForcesKernelP6float4P6float3i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z21calculateForcesKernelP6float4P6float3i, .-_Z21calculateForcesKernelP6float4P6float3i
.globl _Z20galaxyCollisionLogicP6float4P6float3i
.type _Z20galaxyCollisionLogicP6float4P6float3i, @function
_Z20galaxyCollisionLogicP6float4P6float3i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L18:
call cudaDeviceSynchronize@PLT
movl $0, _ZL7doPrint(%rip)
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z56__device_stub__Z21calculateForcesKernelP6float4P6float3iP6float4P6float3i
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z20galaxyCollisionLogicP6float4P6float3i, .-_Z20galaxyCollisionLogicP6float4P6float3i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Jakub-Ciecierski/GalaxyCollisionCUDA/master/src/cuda/GalaxyCollision.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z19galaxyCollisionInitP6float4P6float3i
.type _Z19galaxyCollisionInitP6float4P6float3i, @function
_Z19galaxyCollisionInitP6float4P6float3i:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r14
movl %edx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leal (%rdx,%rdx,2), %ebp
sall $2, %ebp
movl %edx, %r12d
sall $4, %r12d
movslq %r12d, %r12
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
movslq %ebp, %rbp
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L31
movl $1, %ecx
movq %r12, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movl %ebx, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z20galaxyCollisionLogicP6float4P6float3i
movl $2, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L33
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L34
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L35
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $163, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $164, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $167, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $174, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $177, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $178, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z19galaxyCollisionInitP6float4P6float3i, .-_Z19galaxyCollisionInitP6float4P6float3i
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z21calculateForcesKernelP6float4P6float3i"
.section .rodata.str1.1
.LC3:
.string "doPrint"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21calculateForcesKernelP6float4P6float3i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7doPrint(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7doPrint
.comm _ZL7doPrint,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GalaxyCollision.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // From CUDA for Engineering
// dist_v2/kernel.cu
#include <stdio.h>
#include <cuda_runtime.h>
#include <iostream>
#include <iomanip>
#define TPB 32
#define N 256000
#define M 5 // number of times to do cudaMemcpy
#define DEBUG 0
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= len) { return; }
const float x = d_in[i];
d_out[i] = distance(x, ref);
}
void distanceArray(float *out, float *in, float ref, int len)
{
// alloc cuda memory
float *d_in = 0;
float *d_out = 0;
cudaMalloc(&d_in, len * sizeof(float));
cudaMalloc(&d_out, len * sizeof(float));
// memcpy to device
struct timespec t0 = {0,0};
struct timespec t1 = {0,0};
clock_gettime(CLOCK_REALTIME, &t0);
for (int i = 0; i < M; i++) {
cudaMemcpy(d_in, in, len * sizeof(float), cudaMemcpyHostToDevice);
}
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Data transfer time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// call wrapper
clock_gettime(CLOCK_REALTIME, &t0);
distanceKernel<<<(len+TPB-1)/TPB, TPB>>>(d_out, d_in, ref, len);
cudaDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Kernel time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// memcpy from device
cudaMemcpy(out, d_out, len * sizeof(float), cudaMemcpyDeviceToHost);
// free cuda memory
cudaFree(d_in);
cudaFree(d_out);
}
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
int main()
{
std::cout << "dist_v2_cuda\n";
const float ref = 0.5f;
float *in = (float*)calloc(N, sizeof(float));
float *out = (float*)calloc(N, sizeof(float));
for (int i = 0; i < N; i++) {
in[i] = scale(i, N);
}
distanceArray(out, in, ref, N);
#if DEBUG
std::cout << std::fixed << std::setprecision(4);
for (int i = 0; i < N; i++) {
std::cout << "i = " << i << "\tin: " << in[i] << "\tout: " << out[i] << "\n";
}
#endif
free(in);
free(out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x190 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00b0*/ FADD R4, -R2, c[0x0][0x170] ; /* 0x00005c0002047621 */
/* 0x004fc80000000100 */
/*00c0*/ FMUL R4, R4, R4 ; /* 0x0000000404047220 */
/* 0x000fc80000400000 */
/*00d0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*00e0*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0100*/ @!P0 BRA 0x140 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0110*/ MOV R8, 0x130 ; /* 0x0000013000087802 */
/* 0x003fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x1d0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R3, R4, R5 ; /* 0x0000000504037220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R4, -R3, R3, R4 ; /* 0x0000000303047223 */
/* 0x000fc80000000104 */
/*0170*/ FFMA R5, R4, R5, R3 ; /* 0x0000000504057223 */
/* 0x000fe40000000003 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*01a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*01e0*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*01f0*/ @!P0 BRA 0x300 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*0210*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0220*/ @!P0 BRA 0x300 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0230*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0240*/ @P0 FADD.FTZ R2, R4, 1 ; /* 0x3f80000004020421 */
/* 0x000fe20000010000 */
/*0250*/ @P0 BRA 0x300 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*0270*/ @P0 FFMA R3, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004030823 */
/* 0x000fc800000000ff */
/*0280*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*0290*/ @P0 FMUL.FTZ R6, R3, R2 ; /* 0x0000000203060220 */
/* 0x001fe40000410000 */
/*02a0*/ @P0 FMUL.FTZ R7, R2, 0.5 ; /* 0x3f00000002070820 */
/* 0x000fe20000410000 */
/*02b0*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*02c0*/ @P0 FADD.FTZ R5, -R6, -RZ ; /* 0x800000ff06050221 */
/* 0x000fc80000010100 */
/*02d0*/ @P0 FFMA R5, R6, R5, R3 ; /* 0x0000000506050223 */
/* 0x000fc80000000003 */
/*02e0*/ @P0 FFMA R5, R5, R7, R6 ; /* 0x0000000705050223 */
/* 0x000fc80000000006 */
/*02f0*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0310*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe40000000f00 */
/*0320*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0330*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffcc002007950 */
/* 0x000fea0003c3ffff */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // From CUDA for Engineering
// dist_v2/kernel.cu
#include <stdio.h>
#include <cuda_runtime.h>
#include <iostream>
#include <iomanip>
#define TPB 32
#define N 256000
#define M 5 // number of times to do cudaMemcpy
#define DEBUG 0
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= len) { return; }
const float x = d_in[i];
d_out[i] = distance(x, ref);
}
void distanceArray(float *out, float *in, float ref, int len)
{
// alloc cuda memory
float *d_in = 0;
float *d_out = 0;
cudaMalloc(&d_in, len * sizeof(float));
cudaMalloc(&d_out, len * sizeof(float));
// memcpy to device
struct timespec t0 = {0,0};
struct timespec t1 = {0,0};
clock_gettime(CLOCK_REALTIME, &t0);
for (int i = 0; i < M; i++) {
cudaMemcpy(d_in, in, len * sizeof(float), cudaMemcpyHostToDevice);
}
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Data transfer time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// call wrapper
clock_gettime(CLOCK_REALTIME, &t0);
distanceKernel<<<(len+TPB-1)/TPB, TPB>>>(d_out, d_in, ref, len);
cudaDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Kernel time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// memcpy from device
cudaMemcpy(out, d_out, len * sizeof(float), cudaMemcpyDeviceToHost);
// free cuda memory
cudaFree(d_in);
cudaFree(d_out);
}
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
int main()
{
std::cout << "dist_v2_cuda\n";
const float ref = 0.5f;
float *in = (float*)calloc(N, sizeof(float));
float *out = (float*)calloc(N, sizeof(float));
for (int i = 0; i < N; i++) {
in[i] = scale(i, N);
}
distanceArray(out, in, ref, N);
#if DEBUG
std::cout << std::fixed << std::setprecision(4);
for (int i = 0; i < N; i++) {
std::cout << "i = " << i << "\tin: " << in[i] << "\tout: " << out[i] << "\n";
}
#endif
free(in);
free(out);
return 0;
} | .file "tmpxft_0001f403_00000000-6_dist_v2_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB3949:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3949:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB3951:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
subl $1, %esi
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
divss %xmm1, %xmm0
ret
.cfi_endproc
.LFE3951:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
.type _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi, @function
_Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi:
.LFB3977:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14distanceKernelPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi, .-_Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
.globl _Z14distanceKernelPfS_fi
.type _Z14distanceKernelPfS_fi, @function
_Z14distanceKernelPfS_fi:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z14distanceKernelPfS_fi, .-_Z14distanceKernelPfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Data transfer time (ms) = "
.LC3:
.string "\n"
.LC4:
.string "Kernel time (ms) = "
.text
.globl _Z13distanceArrayPfS_fi
.type _Z13distanceArrayPfS_fi, @function
_Z13distanceArrayPfS_fi:
.LFB3950:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r14
movq %rsi, %r12
movss %xmm0, 12(%rsp)
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movslq %edx, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $5, %ebx
.L15:
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %ebx
jne .L15
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $26, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC1(%rip), %xmm0
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $32, 52(%rsp)
movl $1, 56(%rsp)
leal 62(%r13), %eax
movl %r13d, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $19, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC1(%rip), %xmm0
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %r13d, %edx
movss 12(%rsp), %xmm0
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z13distanceArrayPfS_fi, .-_Z13distanceArrayPfS_fi
.section .rodata.str1.1
.LC5:
.string "dist_v2_cuda\n"
.text
.globl main
.type main, @function
main:
.LFB3952:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $4, %esi
movl $256000, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $256000, %edi
call calloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC6(%rip), %xmm1
.L23:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $256000, %rax
jne .L23
movl $256000, %edx
movss .LC7(%rip), %xmm0
movq %rbx, %rsi
movq %rbp, %rdi
call _Z13distanceArrayPfS_fi
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z14distanceKernelPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1083129856
.align 8
.LC2:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1215954880
.align 4
.LC7:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // From CUDA for Engineering
// dist_v2/kernel.cu
#include <stdio.h>
#include <cuda_runtime.h>
#include <iostream>
#include <iomanip>
#define TPB 32
#define N 256000
#define M 5 // number of times to do cudaMemcpy
#define DEBUG 0
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= len) { return; }
const float x = d_in[i];
d_out[i] = distance(x, ref);
}
void distanceArray(float *out, float *in, float ref, int len)
{
// alloc cuda memory
float *d_in = 0;
float *d_out = 0;
cudaMalloc(&d_in, len * sizeof(float));
cudaMalloc(&d_out, len * sizeof(float));
// memcpy to device
struct timespec t0 = {0,0};
struct timespec t1 = {0,0};
clock_gettime(CLOCK_REALTIME, &t0);
for (int i = 0; i < M; i++) {
cudaMemcpy(d_in, in, len * sizeof(float), cudaMemcpyHostToDevice);
}
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Data transfer time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// call wrapper
clock_gettime(CLOCK_REALTIME, &t0);
distanceKernel<<<(len+TPB-1)/TPB, TPB>>>(d_out, d_in, ref, len);
cudaDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Kernel time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// memcpy from device
cudaMemcpy(out, d_out, len * sizeof(float), cudaMemcpyDeviceToHost);
// free cuda memory
cudaFree(d_in);
cudaFree(d_out);
}
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
int main()
{
std::cout << "dist_v2_cuda\n";
const float ref = 0.5f;
float *in = (float*)calloc(N, sizeof(float));
float *out = (float*)calloc(N, sizeof(float));
for (int i = 0; i < N; i++) {
in[i] = scale(i, N);
}
distanceArray(out, in, ref, N);
#if DEBUG
std::cout << std::fixed << std::setprecision(4);
for (int i = 0; i < N; i++) {
std::cout << "i = " << i << "\tin: " << in[i] << "\tout: " << out[i] << "\n";
}
#endif
free(in);
free(out);
return 0;
} | // From CUDA for Engineering
// dist_v2/kernel.cu
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#define TPB 32
#define N 256000
#define M 5 // number of times to do cudaMemcpy
#define DEBUG 0
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= len) { return; }
const float x = d_in[i];
d_out[i] = distance(x, ref);
}
void distanceArray(float *out, float *in, float ref, int len)
{
// alloc cuda memory
float *d_in = 0;
float *d_out = 0;
hipMalloc(&d_in, len * sizeof(float));
hipMalloc(&d_out, len * sizeof(float));
// memcpy to device
struct timespec t0 = {0,0};
struct timespec t1 = {0,0};
clock_gettime(CLOCK_REALTIME, &t0);
for (int i = 0; i < M; i++) {
hipMemcpy(d_in, in, len * sizeof(float), hipMemcpyHostToDevice);
}
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Data transfer time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// call wrapper
clock_gettime(CLOCK_REALTIME, &t0);
distanceKernel<<<(len+TPB-1)/TPB, TPB>>>(d_out, d_in, ref, len);
hipDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Kernel time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// memcpy from device
hipMemcpy(out, d_out, len * sizeof(float), hipMemcpyDeviceToHost);
// free cuda memory
hipFree(d_in);
hipFree(d_out);
}
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
int main()
{
std::cout << "dist_v2_cuda\n";
const float ref = 0.5f;
float *in = (float*)calloc(N, sizeof(float));
float *out = (float*)calloc(N, sizeof(float));
for (int i = 0; i < N; i++) {
in[i] = scale(i, N);
}
distanceArray(out, in, ref, N);
#if DEBUG
std::cout << std::fixed << std::setprecision(4);
for (int i = 0; i < N; i++) {
std::cout << "i = " << i << "\tin: " << in[i] << "\tout: " << out[i] << "\n";
}
#endif
free(in);
free(out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // From CUDA for Engineering
// dist_v2/kernel.cu
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#define TPB 32
#define N 256000
#define M 5 // number of times to do cudaMemcpy
#define DEBUG 0
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= len) { return; }
const float x = d_in[i];
d_out[i] = distance(x, ref);
}
void distanceArray(float *out, float *in, float ref, int len)
{
// alloc cuda memory
float *d_in = 0;
float *d_out = 0;
hipMalloc(&d_in, len * sizeof(float));
hipMalloc(&d_out, len * sizeof(float));
// memcpy to device
struct timespec t0 = {0,0};
struct timespec t1 = {0,0};
clock_gettime(CLOCK_REALTIME, &t0);
for (int i = 0; i < M; i++) {
hipMemcpy(d_in, in, len * sizeof(float), hipMemcpyHostToDevice);
}
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Data transfer time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// call wrapper
clock_gettime(CLOCK_REALTIME, &t0);
distanceKernel<<<(len+TPB-1)/TPB, TPB>>>(d_out, d_in, ref, len);
hipDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Kernel time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// memcpy from device
hipMemcpy(out, d_out, len * sizeof(float), hipMemcpyDeviceToHost);
// free cuda memory
hipFree(d_in);
hipFree(d_out);
}
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
int main()
{
std::cout << "dist_v2_cuda\n";
const float ref = 0.5f;
float *in = (float*)calloc(N, sizeof(float));
float *out = (float*)calloc(N, sizeof(float));
for (int i = 0; i < N; i++) {
in[i] = scale(i, N);
}
distanceArray(out, in, ref, N);
#if DEBUG
std::cout << std::fixed << std::setprecision(4);
for (int i = 0; i < N; i++) {
std::cout << "i = " << i << "\tin: " << in[i] << "\tout: " << out[i] << "\n";
}
#endif
free(in);
free(out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfS_fi
.globl _Z14distanceKernelPfS_fi
.p2align 8
.type _Z14distanceKernelPfS_fi,@function
_Z14distanceKernelPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, s0, v2
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfS_fi, .Lfunc_end0-_Z14distanceKernelPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // From CUDA for Engineering
// dist_v2/kernel.cu
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#define TPB 32
#define N 256000
#define M 5 // number of times to do cudaMemcpy
#define DEBUG 0
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= len) { return; }
const float x = d_in[i];
d_out[i] = distance(x, ref);
}
void distanceArray(float *out, float *in, float ref, int len)
{
// alloc cuda memory
float *d_in = 0;
float *d_out = 0;
hipMalloc(&d_in, len * sizeof(float));
hipMalloc(&d_out, len * sizeof(float));
// memcpy to device
struct timespec t0 = {0,0};
struct timespec t1 = {0,0};
clock_gettime(CLOCK_REALTIME, &t0);
for (int i = 0; i < M; i++) {
hipMemcpy(d_in, in, len * sizeof(float), hipMemcpyHostToDevice);
}
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Data transfer time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// call wrapper
clock_gettime(CLOCK_REALTIME, &t0);
distanceKernel<<<(len+TPB-1)/TPB, TPB>>>(d_out, d_in, ref, len);
hipDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t1);
std::cout << "Kernel time (ms) = " << (t1.tv_sec-t0.tv_sec)*1e3 + (t1.tv_nsec-t0.tv_nsec)/1e6 << "\n";
// memcpy from device
hipMemcpy(out, d_out, len * sizeof(float), hipMemcpyDeviceToHost);
// free cuda memory
hipFree(d_in);
hipFree(d_out);
}
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
int main()
{
std::cout << "dist_v2_cuda\n";
const float ref = 0.5f;
float *in = (float*)calloc(N, sizeof(float));
float *out = (float*)calloc(N, sizeof(float));
for (int i = 0; i < N; i++) {
in[i] = scale(i, N);
}
distanceArray(out, in, ref, N);
#if DEBUG
std::cout << std::fixed << std::setprecision(4);
for (int i = 0; i < N; i++) {
std::cout << "i = " << i << "\tin: " << in[i] << "\tout: " << out[i] << "\n";
}
#endif
free(in);
free(out);
return 0;
} | .text
.file "dist_v2_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__distanceKernelPfS_fi # -- Begin function _Z29__device_stub__distanceKernelPfS_fi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfS_fi,@function
_Z29__device_stub__distanceKernelPfS_fi: # @_Z29__device_stub__distanceKernelPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPfS_fi, .Lfunc_end0-_Z29__device_stub__distanceKernelPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13distanceArrayPfS_fi
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z13distanceArrayPfS_fi
.p2align 4, 0x90
.type _Z13distanceArrayPfS_fi,@function
_Z13distanceArrayPfS_fi: # @_Z13distanceArrayPfS_fi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movss %xmm0, 20(%rsp) # 4-byte Spill
movq %rsi, %r12
movq %rdi, %rbx
movq $0, 8(%rsp)
movq $0, (%rsp)
movslq %edx, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
leaq 48(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $5, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
decl %ebp
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 48(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
subq 56(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 48(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leal 31(%r15), %eax
leal 62(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $5, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14distanceKernelPfS_fi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 48(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
subq 56(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13distanceArrayPfS_fi, .Lfunc_end1-_Z13distanceArrayPfS_fi
.cfi_endproc
# -- End function
.globl _Z5scaleii # -- Begin function _Z5scaleii
.p2align 4, 0x90
.type _Z5scaleii,@function
_Z5scaleii: # @_Z5scaleii
.cfi_startproc
# %bb.0:
cvtsi2ss %edi, %xmm0
decl %esi
cvtsi2ss %esi, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end2:
.size _Z5scaleii, .Lfunc_end2-_Z5scaleii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x4879ffc0 # float 255999
.LCPI3_1:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $256000, %edi # imm = 0x3E800
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $256000, %edi # imm = 0x3E800
movl $4, %esi
callq calloc
movq %rax, %r14
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $256000, %rax # imm = 0x3E800
jne .LBB3_1
# %bb.2:
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r14, %rdi
movq %rbx, %rsi
movl $256000, %edx # imm = 0x3E800
callq _Z13distanceArrayPfS_fi
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfS_fi,@object # @_Z14distanceKernelPfS_fi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfS_fi
.p2align 3, 0x0
_Z14distanceKernelPfS_fi:
.quad _Z29__device_stub__distanceKernelPfS_fi
.size _Z14distanceKernelPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Data transfer time (ms) = "
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel time (ms) = "
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "dist_v2_cuda\n"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14distanceKernelPfS_fi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfS_fi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14distanceKernelPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x190 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*00b0*/ FADD R4, -R2, c[0x0][0x170] ; /* 0x00005c0002047621 */
/* 0x004fc80000000100 */
/*00c0*/ FMUL R4, R4, R4 ; /* 0x0000000404047220 */
/* 0x000fc80000400000 */
/*00d0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*00e0*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0100*/ @!P0 BRA 0x140 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0110*/ MOV R8, 0x130 ; /* 0x0000013000087802 */
/* 0x003fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x1d0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R3, R4, R5 ; /* 0x0000000504037220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R4, -R3, R3, R4 ; /* 0x0000000303047223 */
/* 0x000fc80000000104 */
/*0170*/ FFMA R5, R4, R5, R3 ; /* 0x0000000504057223 */
/* 0x000fe40000000003 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*01a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*01e0*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*01f0*/ @!P0 BRA 0x300 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0200*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*0210*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0220*/ @!P0 BRA 0x300 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0230*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0240*/ @P0 FADD.FTZ R2, R4, 1 ; /* 0x3f80000004020421 */
/* 0x000fe20000010000 */
/*0250*/ @P0 BRA 0x300 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*0270*/ @P0 FFMA R3, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004030823 */
/* 0x000fc800000000ff */
/*0280*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*0290*/ @P0 FMUL.FTZ R6, R3, R2 ; /* 0x0000000203060220 */
/* 0x001fe40000410000 */
/*02a0*/ @P0 FMUL.FTZ R7, R2, 0.5 ; /* 0x3f00000002070820 */
/* 0x000fe20000410000 */
/*02b0*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*02c0*/ @P0 FADD.FTZ R5, -R6, -RZ ; /* 0x800000ff06050221 */
/* 0x000fc80000010100 */
/*02d0*/ @P0 FFMA R5, R6, R5, R3 ; /* 0x0000000506050223 */
/* 0x000fc80000000003 */
/*02e0*/ @P0 FFMA R5, R5, R7, R6 ; /* 0x0000000705050223 */
/* 0x000fc80000000006 */
/*02f0*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*0300*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0310*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe40000000f00 */
/*0320*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0330*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffcc002007950 */
/* 0x000fea0003c3ffff */
/*0340*/ BRA 0x340; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfS_fi
.globl _Z14distanceKernelPfS_fi
.p2align 8
.type _Z14distanceKernelPfS_fi,@function
_Z14distanceKernelPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, s0, v2
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfS_fi, .Lfunc_end0-_Z14distanceKernelPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001f403_00000000-6_dist_v2_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB3949:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3949:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB3951:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
subl $1, %esi
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
divss %xmm1, %xmm0
ret
.cfi_endproc
.LFE3951:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
.type _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi, @function
_Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi:
.LFB3977:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14distanceKernelPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3977:
.size _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi, .-_Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
.globl _Z14distanceKernelPfS_fi
.type _Z14distanceKernelPfS_fi, @function
_Z14distanceKernelPfS_fi:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _Z14distanceKernelPfS_fi, .-_Z14distanceKernelPfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Data transfer time (ms) = "
.LC3:
.string "\n"
.LC4:
.string "Kernel time (ms) = "
.text
.globl _Z13distanceArrayPfS_fi
.type _Z13distanceArrayPfS_fi, @function
_Z13distanceArrayPfS_fi:
.LFB3950:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $112, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r14
movq %rsi, %r12
movss %xmm0, 12(%rsp)
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movslq %edx, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 88(%rsp)
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $5, %ebx
.L15:
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
subl $1, %ebx
jne .L15
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $26, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC1(%rip), %xmm0
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 64(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $32, 52(%rsp)
movl $1, 56(%rsp)
leal 62(%r13), %eax
movl %r13d, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movl $19, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC1(%rip), %xmm0
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movl %r13d, %edx
movss 12(%rsp), %xmm0
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z38__device_stub__Z14distanceKernelPfS_fiPfS_fi
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z13distanceArrayPfS_fi, .-_Z13distanceArrayPfS_fi
.section .rodata.str1.1
.LC5:
.string "dist_v2_cuda\n"
.text
.globl main
.type main, @function
main:
.LFB3952:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $4, %esi
movl $256000, %edi
call calloc@PLT
movq %rax, %rbx
movl $4, %esi
movl $256000, %edi
call calloc@PLT
movq %rax, %rbp
movl $0, %eax
movss .LC6(%rip), %xmm1
.L23:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $256000, %rax
jne .L23
movl $256000, %edx
movss .LC7(%rip), %xmm0
movq %rbx, %rsi
movq %rbp, %rdi
call _Z13distanceArrayPfS_fi
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z14distanceKernelPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3980:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1083129856
.align 8
.LC2:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1215954880
.align 4
.LC7:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dist_v2_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__distanceKernelPfS_fi # -- Begin function _Z29__device_stub__distanceKernelPfS_fi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfS_fi,@function
_Z29__device_stub__distanceKernelPfS_fi: # @_Z29__device_stub__distanceKernelPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPfS_fi, .Lfunc_end0-_Z29__device_stub__distanceKernelPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13distanceArrayPfS_fi
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.LCPI1_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z13distanceArrayPfS_fi
.p2align 4, 0x90
.type _Z13distanceArrayPfS_fi,@function
_Z13distanceArrayPfS_fi: # @_Z13distanceArrayPfS_fi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movss %xmm0, 20(%rsp) # 4-byte Spill
movq %rsi, %r12
movq %rdi, %rbx
movq $0, 8(%rsp)
movq $0, (%rsp)
movslq %edx, %r14
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
leaq 48(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $5, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
decl %ebp
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 48(%rsp), %rax
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
subq 56(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 48(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
leal 31(%r15), %eax
leal 62(%r15), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $5, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14distanceKernelPfS_fi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
subq 48(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
subq 56(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
divsd .LCPI1_1(%rip), %xmm0
addsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13distanceArrayPfS_fi, .Lfunc_end1-_Z13distanceArrayPfS_fi
.cfi_endproc
# -- End function
.globl _Z5scaleii # -- Begin function _Z5scaleii
.p2align 4, 0x90
.type _Z5scaleii,@function
_Z5scaleii: # @_Z5scaleii
.cfi_startproc
# %bb.0:
cvtsi2ss %edi, %xmm0
decl %esi
cvtsi2ss %esi, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end2:
.size _Z5scaleii, .Lfunc_end2-_Z5scaleii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x4879ffc0 # float 255999
.LCPI3_1:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $256000, %edi # imm = 0x3E800
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $256000, %edi # imm = 0x3E800
movl $4, %esi
callq calloc
movq %rax, %r14
xorl %eax, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $256000, %rax # imm = 0x3E800
jne .LBB3_1
# %bb.2:
movss .LCPI3_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r14, %rdi
movq %rbx, %rsi
movl $256000, %edx # imm = 0x3E800
callq _Z13distanceArrayPfS_fi
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfS_fi,@object # @_Z14distanceKernelPfS_fi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfS_fi
.p2align 3, 0x0
_Z14distanceKernelPfS_fi:
.quad _Z29__device_stub__distanceKernelPfS_fi
.size _Z14distanceKernelPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Data transfer time (ms) = "
.size .L.str, 27
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Kernel time (ms) = "
.size .L.str.2, 20
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "dist_v2_cuda\n"
.size .L.str.3, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14distanceKernelPfS_fi"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfS_fi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sobel( int width_d, int height_d, int threshold_d, unsigned int *pic_d , int *final_res)
{
int row_1 = blockIdx.y * blockDim.y + threadIdx.y;
int col_1 = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.y;
int ty = threadIdx.x;
int width_Tile = TILE_SIZE;
int id, id1;
__shared__ int sharedTile[TILE_SIZE * TILE_SIZE];
int magnitude, sum1, sum2;
// Shared Tile Initialization
sharedTile[tx * width_Tile + ty] = 0;
__syncthreads();
// Copying Data from Global to Shared Memory
sharedTile[tx * width_Tile + ty] = pic_d[row_1 * (width_d) + col_1];
__syncthreads();
// Output
if ((row_1 < height_d) && (col_1 < width_d))
{
final_res[row_1 * width_d + col_1] = 0;
}
__syncthreads();
if (row_1 > 0 && col_1 > 0 && row_1 < height_d - 1 && col_1 < width_d - 1)
{
// Applying Sobel Filter on the Tile Stored in the Shared Memory
if ((tx > 0) && (tx < width_Tile - 1) && (ty > 0) && (ty < width_Tile - 1))
{
id = row_1 * width_d + col_1;
sum1 = sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx) + ty+1 ] - 2 * sharedTile[ width_Tile*(tx) + ty-1 ] + sharedTile[ width_Tile * (tx+1) + ty+1] - sharedTile[ width_Tile*(tx+1) + ty-1 ];
sum2 = sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx-1) + ty ] + sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[width_Tile * (tx+1) + ty-1 ] - 2 * sharedTile[ width_Tile * (tx+1) + ty ] - sharedTile[ width_Tile * (tx+1) + ty+1];
magnitude = sum1 * sum1 + sum2 * sum2;
if (magnitude > threshold_d)
{
final_res[id] = 255;
}
else
{
final_res[id] = 0;
}
}
__syncthreads();
// For the Pixels at the Boundaries of the Block using Global Memory
if ((row_1 == blockIdx.y * blockDim.y + blockDim.y - 1) || (col_1 == blockIdx.x * blockDim.x + blockDim.x - 1) || (row_1 == blockIdx.y * blockDim.y) || (col_1 == blockIdx.x * blockDim.x))
{
id1 = row_1 * width_d + col_1;
sum1 = pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1) + col_1+1 ] - 2 * pic_d[ width_d*(row_1) + col_1-1 ] + pic_d[ width_d * (row_1+1) + col_1+1] - pic_d[ width_d*(row_1+1) + col_1-1 ];
sum2 = pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1-1) + col_1 ] + pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[width_d * (row_1+1) + col_1-1 ] - 2 * pic_d[ width_d * (row_1+1) + col_1 ] - pic_d[ width_d * (row_1+1) + col_1+1];
magnitude = sum1*sum1 + sum2*sum2;
if (magnitude > threshold_d)
{
final_res[id1] = 255;
}
else
{
final_res[id1] = 0;
}
}
__syncthreads();
}
} | code for sm_80
Function : _Z5sobeliiiPjPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e280000002100 */
/*0050*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0060*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000ea20000002500 */
/*0070*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fc40000000000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ LEA R12, R7, R9, 0x5 ; /* 0x00000009070c7211 */
/* 0x001fe200078e28ff */
/*00a0*/ IMAD R10, R6, c[0x0][0x4], R7 ; /* 0x00000100060a7a24 */
/* 0x002fc800078e0207 */
/*00b0*/ STS [R12.X4], RZ ; /* 0x000000ff0c007388 */
/* 0x0001e20000004800 */
/*00c0*/ IMAD R11, R8, c[0x0][0x0], R9 ; /* 0x00000000080b7a24 */
/* 0x004fc800078e0209 */
/*00d0*/ IMAD R5, R10, c[0x0][0x160], R11 ; /* 0x000058000a057a24 */
/* 0x000fc800078e020b */
/*00e0*/ IMAD.WIDE R2, R5.reuse, R0.reuse, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x0c0fe200078e0200 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x000ea2000c1e1900 */
/*0110*/ ISETP.GE.AND P1, PT, R10.reuse, c[0x0][0x164], PT ; /* 0x000059000a007a0c */
/* 0x040fe20003f26270 */
/*0120*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fe200078e0200 */
/*0130*/ ISETP.GE.AND P0, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00780c */
/* 0x040fe20003f06270 */
/*0140*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*0150*/ ISETP.GE.OR P1, PT, R11, c[0x0][0x160], P1 ; /* 0x000058000b007a0c */
/* 0x000fe20000f26670 */
/*0160*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*0170*/ ISETP.LT.OR P0, PT, R10, 0x1, !P0 ; /* 0x000000010a00780c */
/* 0x000fc80004701670 */
/*0180*/ ISETP.GE.OR P0, PT, R10, UR4, P0 ; /* 0x000000040a007c0c */
/* 0x000fc80008706670 */
/*0190*/ ISETP.GE.OR P0, PT, R11, UR5, P0 ; /* 0x000000050b007c0c */
/* 0x000fe20008706670 */
/*01a0*/ STS [R12.X4], R13 ; /* 0x0000000d0c007388 */
/* 0x0041e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @!P1 STG.E [R4.64], RZ ; /* 0x000000ff04009986 */
/* 0x0001e8000c101908 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R13, R7, -0x1, RZ ; /* 0xffffffff070d7810 */
/* 0x001fe20007ffe0ff */
/*0200*/ BSSY B0, 0x3d0 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*0210*/ IADD3 R14, R9, -0x1, RZ ; /* 0xffffffff090e7810 */
/* 0x000fc40007ffe0ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R13, 0x1d, PT ; /* 0x0000001d0d00780c */
/* 0x000fe20003f04070 */
/*0230*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0d7624 */
/* 0x000fc600078e00ff */
/*0240*/ ISETP.GT.U32.OR P0, PT, R14, 0x1d, P0 ; /* 0x0000001d0e00780c */
/* 0x000fda0000704470 */
/*0250*/ @P0 BRA 0x3c0 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*0260*/ LDS R14, [R12.X4+-0x84] ; /* 0xffff7c000c0e7984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R15, [R12.X4+-0x7c] ; /* 0xffff84000c0f7984 */
/* 0x000e280000004800 */
/*0280*/ LDS R17, [R12.X4+0x4] ; /* 0x000004000c117984 */
/* 0x000e680000004800 */
/*0290*/ LDS R23, [R12.X4+-0x80] ; /* 0xffff80000c177984 */
/* 0x000ea80000004800 */
/*02a0*/ LDS R19, [R12.X4+-0x4] ; /* 0xfffffc000c137984 */
/* 0x000ee80000004800 */
/*02b0*/ LDS R18, [R12.X4+0x7c] ; /* 0x00007c000c127984 */
/* 0x000f280000004800 */
/*02c0*/ LDS R21, [R12.X4+0x84] ; /* 0x000084000c157984 */
/* 0x000f680000004800 */
/*02d0*/ LDS R20, [R12.X4+0x80] ; /* 0x000080000c147984 */
/* 0x000f620000004800 */
/*02e0*/ IMAD.IADD R16, R15, 0x1, -R14 ; /* 0x000000010f107824 */
/* 0x001fca00078e0a0e */
/*02f0*/ LEA R16, R17, R16, 0x1 ; /* 0x0000001011107211 */
/* 0x002fe200078e08ff */
/*0300*/ IMAD R23, R23, 0x2, R14 ; /* 0x0000000217177824 */
/* 0x004fc800078e020e */
/*0310*/ IMAD R16, R19, -0x2, R16 ; /* 0xfffffffe13107824 */
/* 0x008fe200078e0210 */
/*0320*/ IADD3 R23, -R18, R23, R15 ; /* 0x0000001712177210 */
/* 0x010fc80007ffe10f */
/*0330*/ IADD3 R16, -R18, R16, R21 ; /* 0x0000001012107210 */
/* 0x020fe20007ffe115 */
/*0340*/ IMAD R20, R20, -0x2, R23 ; /* 0xfffffffe14147824 */
/* 0x000fc800078e0217 */
/*0350*/ IMAD R15, R16, R16, RZ ; /* 0x00000010100f7224 */
/* 0x000fe400078e02ff */
/*0360*/ IMAD.IADD R20, R20, 0x1, -R21 ; /* 0x0000000114147824 */
/* 0x000fc800078e0a15 */
/*0370*/ IMAD R15, R20, R20, R15 ; /* 0x00000014140f7224 */
/* 0x000fca00078e020f */
/*0380*/ ISETP.GT.AND P0, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fda0003f04270 */
/*0390*/ @P0 MOV R15, 0xff ; /* 0x000000ff000f0802 */
/* 0x000fe20000000f00 */
/*03a0*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e8000c101908 */
/*03b0*/ @P0 STG.E [R4.64], R15 ; /* 0x0000000f04000986 */
/* 0x0001e4000c101908 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD R13, R6, R13, c[0x0][0x4] ; /* 0x00000100060d7624 */
/* 0x000fe200078e020d */
/*03e0*/ BSSY B0, 0x6a0 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0400*/ IADD3 R13, R13, -0x1, RZ ; /* 0xffffffff0d0d7810 */
/* 0x000fc60007ffe0ff */
/*0410*/ BSSY B1, 0x4d0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0420*/ ISETP.NE.AND P0, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fda0003f05270 */
/*0430*/ @!P0 BRA 0x4c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*0450*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f25270 */
/*0460*/ IMAD R8, R8, R13, c[0x0][0x0] ; /* 0x0000000008087624 */
/* 0x000fca00078e020d */
/*0470*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.NE.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x000fc80003f05270 */
/*0490*/ ISETP.NE.AND P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705270 */
/*04a0*/ @P0 BREAK P1, B1 ; /* 0x0000000000010942 */
/* 0x000fe20000800000 */
/*04b0*/ @P0 BRA P1, 0x690 ; /* 0x000001d000000947 */
/* 0x000fea0000800000 */
/*04c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04d0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000408020d7981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fc60000000f00 */
/*0500*/ IMAD R11, R10, c[0x0][0x160], R11 ; /* 0x000058000a0b7a24 */
/* 0x000fe200078e020b */
/*0510*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc08020f7981 */
/* 0x001ee6000c1e1900 */
/*0520*/ IMAD.WIDE R6, R11, R0, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fc800078e0200 */
/*0530*/ IMAD R9, R8, 0x2, R11 ; /* 0x0000000208097824 */
/* 0x000fe200078e020b */
/*0540*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc08060a7981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000408060b7981 */
/* 0x000f22000c1e1900 */
/*0560*/ IMAD.WIDE R8, R9, R0, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc600078e0200 */
/*0570*/ LDG.E R19, [R6.64] ; /* 0x0000000806137981 */
/* 0x000f68000c1e1900 */
/*0580*/ LDG.E R12, [R8.64+-0x4] ; /* 0xfffffc08080c7981 */
/* 0x000ee8000c1e1900 */
/*0590*/ LDG.E R17, [R8.64+0x4] ; /* 0x0000040808117981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R14, [R8.64] ; /* 0x00000008080e7981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IADD3 R0, -R10, R11, RZ ; /* 0x0000000b0a007210 */
/* 0x010fc80007ffe1ff */
/*05c0*/ LEA R0, R13, R0, 0x1 ; /* 0x000000000d007211 */
/* 0x004fe200078e08ff */
/*05d0*/ IMAD R19, R19, 0x2, R10 ; /* 0x0000000213137824 */
/* 0x020fc800078e020a */
/*05e0*/ IMAD R0, R15, -0x2, R0 ; /* 0xfffffffe0f007824 */
/* 0x008fe200078e0200 */
/*05f0*/ IADD3 R19, -R12, R19, R11 ; /* 0x000000130c137210 */
/* 0x000fc80007ffe10b */
/*0600*/ IADD3 R0, -R12, R0, R17 ; /* 0x000000000c007210 */
/* 0x000fe20007ffe111 */
/*0610*/ IMAD R14, R14, -0x2, R19 ; /* 0xfffffffe0e0e7824 */
/* 0x000fc800078e0213 */
/*0620*/ IMAD R3, R0, R0, RZ ; /* 0x0000000000037224 */
/* 0x000fe400078e02ff */
/*0630*/ IMAD.IADD R14, R14, 0x1, -R17 ; /* 0x000000010e0e7824 */
/* 0x000fc800078e0a11 */
/*0640*/ IMAD R3, R14, R14, R3 ; /* 0x0000000e0e037224 */
/* 0x000fca00078e0203 */
/*0650*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f04270 */
/*0660*/ @P0 MOV R3, 0xff ; /* 0x000000ff00030802 */
/* 0x000fe20000000f00 */
/*0670*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e8000c101908 */
/*0680*/ @P0 STG.E [R4.64], R3 ; /* 0x0000000304000986 */
/* 0x0001e4000c101908 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sobel( int width_d, int height_d, int threshold_d, unsigned int *pic_d , int *final_res)
{
int row_1 = blockIdx.y * blockDim.y + threadIdx.y;
int col_1 = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.y;
int ty = threadIdx.x;
int width_Tile = TILE_SIZE;
int id, id1;
__shared__ int sharedTile[TILE_SIZE * TILE_SIZE];
int magnitude, sum1, sum2;
// Shared Tile Initialization
sharedTile[tx * width_Tile + ty] = 0;
__syncthreads();
// Copying Data from Global to Shared Memory
sharedTile[tx * width_Tile + ty] = pic_d[row_1 * (width_d) + col_1];
__syncthreads();
// Output
if ((row_1 < height_d) && (col_1 < width_d))
{
final_res[row_1 * width_d + col_1] = 0;
}
__syncthreads();
if (row_1 > 0 && col_1 > 0 && row_1 < height_d - 1 && col_1 < width_d - 1)
{
// Applying Sobel Filter on the Tile Stored in the Shared Memory
if ((tx > 0) && (tx < width_Tile - 1) && (ty > 0) && (ty < width_Tile - 1))
{
id = row_1 * width_d + col_1;
sum1 = sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx) + ty+1 ] - 2 * sharedTile[ width_Tile*(tx) + ty-1 ] + sharedTile[ width_Tile * (tx+1) + ty+1] - sharedTile[ width_Tile*(tx+1) + ty-1 ];
sum2 = sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx-1) + ty ] + sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[width_Tile * (tx+1) + ty-1 ] - 2 * sharedTile[ width_Tile * (tx+1) + ty ] - sharedTile[ width_Tile * (tx+1) + ty+1];
magnitude = sum1 * sum1 + sum2 * sum2;
if (magnitude > threshold_d)
{
final_res[id] = 255;
}
else
{
final_res[id] = 0;
}
}
__syncthreads();
// For the Pixels at the Boundaries of the Block using Global Memory
if ((row_1 == blockIdx.y * blockDim.y + blockDim.y - 1) || (col_1 == blockIdx.x * blockDim.x + blockDim.x - 1) || (row_1 == blockIdx.y * blockDim.y) || (col_1 == blockIdx.x * blockDim.x))
{
id1 = row_1 * width_d + col_1;
sum1 = pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1) + col_1+1 ] - 2 * pic_d[ width_d*(row_1) + col_1-1 ] + pic_d[ width_d * (row_1+1) + col_1+1] - pic_d[ width_d*(row_1+1) + col_1-1 ];
sum2 = pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1-1) + col_1 ] + pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[width_d * (row_1+1) + col_1-1 ] - 2 * pic_d[ width_d * (row_1+1) + col_1 ] - pic_d[ width_d * (row_1+1) + col_1+1];
magnitude = sum1*sum1 + sum2*sum2;
if (magnitude > threshold_d)
{
final_res[id1] = 255;
}
else
{
final_res[id1] = 0;
}
}
__syncthreads();
}
} | .file "tmpxft_0012dc1a_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi
.type _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi, @function
_Z29__device_stub__Z5sobeliiiPjPiiiiPjPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sobeliiiPjPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi, .-_Z29__device_stub__Z5sobeliiiPjPiiiiPjPi
.globl _Z5sobeliiiPjPi
.type _Z5sobeliiiPjPi, @function
_Z5sobeliiiPjPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sobeliiiPjPi, .-_Z5sobeliiiPjPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5sobeliiiPjPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sobeliiiPjPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sobel( int width_d, int height_d, int threshold_d, unsigned int *pic_d , int *final_res)
{
int row_1 = blockIdx.y * blockDim.y + threadIdx.y;
int col_1 = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.y;
int ty = threadIdx.x;
int width_Tile = TILE_SIZE;
int id, id1;
__shared__ int sharedTile[TILE_SIZE * TILE_SIZE];
int magnitude, sum1, sum2;
// Shared Tile Initialization
sharedTile[tx * width_Tile + ty] = 0;
__syncthreads();
// Copying Data from Global to Shared Memory
sharedTile[tx * width_Tile + ty] = pic_d[row_1 * (width_d) + col_1];
__syncthreads();
// Output
if ((row_1 < height_d) && (col_1 < width_d))
{
final_res[row_1 * width_d + col_1] = 0;
}
__syncthreads();
if (row_1 > 0 && col_1 > 0 && row_1 < height_d - 1 && col_1 < width_d - 1)
{
// Applying Sobel Filter on the Tile Stored in the Shared Memory
if ((tx > 0) && (tx < width_Tile - 1) && (ty > 0) && (ty < width_Tile - 1))
{
id = row_1 * width_d + col_1;
sum1 = sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx) + ty+1 ] - 2 * sharedTile[ width_Tile*(tx) + ty-1 ] + sharedTile[ width_Tile * (tx+1) + ty+1] - sharedTile[ width_Tile*(tx+1) + ty-1 ];
sum2 = sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx-1) + ty ] + sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[width_Tile * (tx+1) + ty-1 ] - 2 * sharedTile[ width_Tile * (tx+1) + ty ] - sharedTile[ width_Tile * (tx+1) + ty+1];
magnitude = sum1 * sum1 + sum2 * sum2;
if (magnitude > threshold_d)
{
final_res[id] = 255;
}
else
{
final_res[id] = 0;
}
}
__syncthreads();
// For the Pixels at the Boundaries of the Block using Global Memory
if ((row_1 == blockIdx.y * blockDim.y + blockDim.y - 1) || (col_1 == blockIdx.x * blockDim.x + blockDim.x - 1) || (row_1 == blockIdx.y * blockDim.y) || (col_1 == blockIdx.x * blockDim.x))
{
id1 = row_1 * width_d + col_1;
sum1 = pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1) + col_1+1 ] - 2 * pic_d[ width_d*(row_1) + col_1-1 ] + pic_d[ width_d * (row_1+1) + col_1+1] - pic_d[ width_d*(row_1+1) + col_1-1 ];
sum2 = pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1-1) + col_1 ] + pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[width_d * (row_1+1) + col_1-1 ] - 2 * pic_d[ width_d * (row_1+1) + col_1 ] - pic_d[ width_d * (row_1+1) + col_1+1];
magnitude = sum1*sum1 + sum2*sum2;
if (magnitude > threshold_d)
{
final_res[id1] = 255;
}
else
{
final_res[id1] = 0;
}
}
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sobel( int width_d, int height_d, int threshold_d, unsigned int *pic_d , int *final_res)
{
int row_1 = blockIdx.y * blockDim.y + threadIdx.y;
int col_1 = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.y;
int ty = threadIdx.x;
int width_Tile = TILE_SIZE;
int id, id1;
__shared__ int sharedTile[TILE_SIZE * TILE_SIZE];
int magnitude, sum1, sum2;
// Shared Tile Initialization
sharedTile[tx * width_Tile + ty] = 0;
__syncthreads();
// Copying Data from Global to Shared Memory
sharedTile[tx * width_Tile + ty] = pic_d[row_1 * (width_d) + col_1];
__syncthreads();
// Output
if ((row_1 < height_d) && (col_1 < width_d))
{
final_res[row_1 * width_d + col_1] = 0;
}
__syncthreads();
if (row_1 > 0 && col_1 > 0 && row_1 < height_d - 1 && col_1 < width_d - 1)
{
// Applying Sobel Filter on the Tile Stored in the Shared Memory
if ((tx > 0) && (tx < width_Tile - 1) && (ty > 0) && (ty < width_Tile - 1))
{
id = row_1 * width_d + col_1;
sum1 = sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx) + ty+1 ] - 2 * sharedTile[ width_Tile*(tx) + ty-1 ] + sharedTile[ width_Tile * (tx+1) + ty+1] - sharedTile[ width_Tile*(tx+1) + ty-1 ];
sum2 = sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx-1) + ty ] + sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[width_Tile * (tx+1) + ty-1 ] - 2 * sharedTile[ width_Tile * (tx+1) + ty ] - sharedTile[ width_Tile * (tx+1) + ty+1];
magnitude = sum1 * sum1 + sum2 * sum2;
if (magnitude > threshold_d)
{
final_res[id] = 255;
}
else
{
final_res[id] = 0;
}
}
__syncthreads();
// For the Pixels at the Boundaries of the Block using Global Memory
if ((row_1 == blockIdx.y * blockDim.y + blockDim.y - 1) || (col_1 == blockIdx.x * blockDim.x + blockDim.x - 1) || (row_1 == blockIdx.y * blockDim.y) || (col_1 == blockIdx.x * blockDim.x))
{
id1 = row_1 * width_d + col_1;
sum1 = pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1) + col_1+1 ] - 2 * pic_d[ width_d*(row_1) + col_1-1 ] + pic_d[ width_d * (row_1+1) + col_1+1] - pic_d[ width_d*(row_1+1) + col_1-1 ];
sum2 = pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1-1) + col_1 ] + pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[width_d * (row_1+1) + col_1-1 ] - 2 * pic_d[ width_d * (row_1+1) + col_1 ] - pic_d[ width_d * (row_1+1) + col_1+1];
magnitude = sum1*sum1 + sum2*sum2;
if (magnitude > threshold_d)
{
final_res[id1] = 255;
}
else
{
final_res[id1] = 0;
}
}
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sobel( int width_d, int height_d, int threshold_d, unsigned int *pic_d , int *final_res)
{
int row_1 = blockIdx.y * blockDim.y + threadIdx.y;
int col_1 = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.y;
int ty = threadIdx.x;
int width_Tile = TILE_SIZE;
int id, id1;
__shared__ int sharedTile[TILE_SIZE * TILE_SIZE];
int magnitude, sum1, sum2;
// Shared Tile Initialization
sharedTile[tx * width_Tile + ty] = 0;
__syncthreads();
// Copying Data from Global to Shared Memory
sharedTile[tx * width_Tile + ty] = pic_d[row_1 * (width_d) + col_1];
__syncthreads();
// Output
if ((row_1 < height_d) && (col_1 < width_d))
{
final_res[row_1 * width_d + col_1] = 0;
}
__syncthreads();
if (row_1 > 0 && col_1 > 0 && row_1 < height_d - 1 && col_1 < width_d - 1)
{
// Applying Sobel Filter on the Tile Stored in the Shared Memory
if ((tx > 0) && (tx < width_Tile - 1) && (ty > 0) && (ty < width_Tile - 1))
{
id = row_1 * width_d + col_1;
sum1 = sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx) + ty+1 ] - 2 * sharedTile[ width_Tile*(tx) + ty-1 ] + sharedTile[ width_Tile * (tx+1) + ty+1] - sharedTile[ width_Tile*(tx+1) + ty-1 ];
sum2 = sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx-1) + ty ] + sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[width_Tile * (tx+1) + ty-1 ] - 2 * sharedTile[ width_Tile * (tx+1) + ty ] - sharedTile[ width_Tile * (tx+1) + ty+1];
magnitude = sum1 * sum1 + sum2 * sum2;
if (magnitude > threshold_d)
{
final_res[id] = 255;
}
else
{
final_res[id] = 0;
}
}
__syncthreads();
// For the Pixels at the Boundaries of the Block using Global Memory
if ((row_1 == blockIdx.y * blockDim.y + blockDim.y - 1) || (col_1 == blockIdx.x * blockDim.x + blockDim.x - 1) || (row_1 == blockIdx.y * blockDim.y) || (col_1 == blockIdx.x * blockDim.x))
{
id1 = row_1 * width_d + col_1;
sum1 = pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1) + col_1+1 ] - 2 * pic_d[ width_d*(row_1) + col_1-1 ] + pic_d[ width_d * (row_1+1) + col_1+1] - pic_d[ width_d*(row_1+1) + col_1-1 ];
sum2 = pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1-1) + col_1 ] + pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[width_d * (row_1+1) + col_1-1 ] - 2 * pic_d[ width_d * (row_1+1) + col_1 ] - pic_d[ width_d * (row_1+1) + col_1+1];
magnitude = sum1*sum1 + sum2*sum2;
if (magnitude > threshold_d)
{
final_res[id1] = 255;
}
else
{
final_res[id1] = 0;
}
}
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sobeliiiPjPi
.globl _Z5sobeliiiPjPi
.p2align 8
.type _Z5sobeliiiPjPi,@function
_Z5sobeliiiPjPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x0
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v12, 0 :: v_dual_and_b32 v7, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v11, 5, v6
v_add_nc_u32_e32 v10, v11, v7
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v13, 2, v10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s10, s2, 16
s_and_b32 s11, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s10, v[6:7]
v_mad_u64_u32 v[3:4], null, s14, s11, v[7:8]
ds_store_b32 v13, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mad_u64_u32 v[0:1], null, v2, s8, v[3:4]
v_cmp_gt_i32_e64 s2, s8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[8:9], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s9, v2
global_load_b32 v14, v[4:5], off
s_and_b32 s3, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b32 v13, v14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_store_b32 v[8:9], v12, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_min_i32_e32 v8, v2, v3
s_add_i32 s2, s9, -1
s_add_i32 s3, s8, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v3
v_cmp_lt_i32_e64 s3, 0, v8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s3, s[0:1], 0x8
s_mov_b32 s1, exec_lo
v_cmpx_ne_u32_e32 0, v6
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v8, -1, v7
v_cmp_gt_u32_e32 vcc_lo, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, 30, v8
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v11, v11, v7, 2
v_lshlrev_b32_e32 v12, 2, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, 0xffffff80, v11
v_add_nc_u32_e32 v13, 0xffffff7c, v11
v_add_nc_u32_e32 v14, -4, v12
ds_load_2addr_b32 v[8:9], v11 offset0:31 offset1:32
ds_load_b32 v15, v11 offset:132
ds_load_2addr_b32 v[10:11], v10 offset1:1
ds_load_b32 v13, v13
ds_load_b32 v12, v12 offset:4
ds_load_b32 v14, v14
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v16, v11, v15
v_add_nc_u32_e32 v17, v13, v8
v_add_nc_u32_e32 v8, v15, v8
v_sub_nc_u32_e32 v12, v12, v14
v_add_nc_u32_e32 v11, v13, v11
v_sub_nc_u32_e32 v9, v10, v9
v_sub_nc_u32_e32 v14, v16, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v11, v8
v_lshl_add_u32 v12, v12, 1, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v13, v9, 1, v10
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_mul_lo_u32 v8, v12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[11:12], null, v13, v13, v[8:9]
v_add_co_u32 v8, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_lt_i32_e32 vcc_lo, s3, v11
v_cndmask_b32_e64 v10, 0, 0xff, vcc_lo
global_store_b32 v[8:9], v10, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s11, s11, -1
v_cmp_eq_u32_e64 s0, 0, v6
v_cmp_eq_u32_e32 vcc_lo, s11, v7
s_add_i32 s10, s10, -1
v_cmp_eq_u32_e64 s1, 0, v7
v_cmp_eq_u32_e64 s2, s10, v6
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_or_b32 s0, s0, vcc_lo
s_barrier
s_or_b32 s0, s1, s0
buffer_gl0_inv
s_or_b32 s0, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v6, s8, v2
v_add_nc_u32_e32 v8, -1, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v2, v6, s8, v3
v_mad_u64_u32 v[6:7], null, v8, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_clause 0x5
global_load_b64 v[8:9], v[2:3], off
global_load_b32 v10, v[2:3], off offset:-4
global_load_b64 v[2:3], v[6:7], off
global_load_b32 v6, v[6:7], off offset:-4
global_load_b32 v7, v[4:5], off offset:4
global_load_b32 v4, v[4:5], off offset:-4
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(3)
v_add_nc_u32_e32 v5, v3, v9
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v11, v6, v10
v_add_nc_u32_e32 v3, v6, v3
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v7, v4
v_add_nc_u32_e32 v6, v9, v10
v_sub_nc_u32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v6
v_lshl_add_u32 v4, v4, 1, v5
v_sub_nc_u32_e32 v5, v2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v4, v4
v_lshl_add_u32 v5, v5, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, v5, v[2:3]
v_cmp_lt_i32_e32 vcc_lo, s3, v3
v_cndmask_b32_e64 v2, 0, 0xff, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_8:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_9:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sobeliiiPjPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sobeliiiPjPi, .Lfunc_end0-_Z5sobeliiiPjPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sobeliiiPjPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sobeliiiPjPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sobel( int width_d, int height_d, int threshold_d, unsigned int *pic_d , int *final_res)
{
int row_1 = blockIdx.y * blockDim.y + threadIdx.y;
int col_1 = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.y;
int ty = threadIdx.x;
int width_Tile = TILE_SIZE;
int id, id1;
__shared__ int sharedTile[TILE_SIZE * TILE_SIZE];
int magnitude, sum1, sum2;
// Shared Tile Initialization
sharedTile[tx * width_Tile + ty] = 0;
__syncthreads();
// Copying Data from Global to Shared Memory
sharedTile[tx * width_Tile + ty] = pic_d[row_1 * (width_d) + col_1];
__syncthreads();
// Output
if ((row_1 < height_d) && (col_1 < width_d))
{
final_res[row_1 * width_d + col_1] = 0;
}
__syncthreads();
if (row_1 > 0 && col_1 > 0 && row_1 < height_d - 1 && col_1 < width_d - 1)
{
// Applying Sobel Filter on the Tile Stored in the Shared Memory
if ((tx > 0) && (tx < width_Tile - 1) && (ty > 0) && (ty < width_Tile - 1))
{
id = row_1 * width_d + col_1;
sum1 = sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx) + ty+1 ] - 2 * sharedTile[ width_Tile*(tx) + ty-1 ] + sharedTile[ width_Tile * (tx+1) + ty+1] - sharedTile[ width_Tile*(tx+1) + ty-1 ];
sum2 = sharedTile[ width_Tile * (tx-1) + ty-1 ] + 2 * sharedTile[ width_Tile * (tx-1) + ty ] + sharedTile[ width_Tile * (tx-1) + ty+1] - sharedTile[width_Tile * (tx+1) + ty-1 ] - 2 * sharedTile[ width_Tile * (tx+1) + ty ] - sharedTile[ width_Tile * (tx+1) + ty+1];
magnitude = sum1 * sum1 + sum2 * sum2;
if (magnitude > threshold_d)
{
final_res[id] = 255;
}
else
{
final_res[id] = 0;
}
}
__syncthreads();
// For the Pixels at the Boundaries of the Block using Global Memory
if ((row_1 == blockIdx.y * blockDim.y + blockDim.y - 1) || (col_1 == blockIdx.x * blockDim.x + blockDim.x - 1) || (row_1 == blockIdx.y * blockDim.y) || (col_1 == blockIdx.x * blockDim.x))
{
id1 = row_1 * width_d + col_1;
sum1 = pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1) + col_1+1 ] - 2 * pic_d[ width_d*(row_1) + col_1-1 ] + pic_d[ width_d * (row_1+1) + col_1+1] - pic_d[ width_d*(row_1+1) + col_1-1 ];
sum2 = pic_d[ width_d * (row_1-1) + col_1-1 ] + 2 * pic_d[ width_d * (row_1-1) + col_1 ] + pic_d[ width_d * (row_1-1) + col_1+1] - pic_d[width_d * (row_1+1) + col_1-1 ] - 2 * pic_d[ width_d * (row_1+1) + col_1 ] - pic_d[ width_d * (row_1+1) + col_1+1];
magnitude = sum1*sum1 + sum2*sum2;
if (magnitude > threshold_d)
{
final_res[id1] = 255;
}
else
{
final_res[id1] = 0;
}
}
__syncthreads();
}
} | .text
.file "sobel.hip"
.globl _Z20__device_stub__sobeliiiPjPi # -- Begin function _Z20__device_stub__sobeliiiPjPi
.p2align 4, 0x90
.type _Z20__device_stub__sobeliiiPjPi,@function
_Z20__device_stub__sobeliiiPjPi: # @_Z20__device_stub__sobeliiiPjPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sobeliiiPjPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__sobeliiiPjPi, .Lfunc_end0-_Z20__device_stub__sobeliiiPjPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sobeliiiPjPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sobeliiiPjPi,@object # @_Z5sobeliiiPjPi
.section .rodata,"a",@progbits
.globl _Z5sobeliiiPjPi
.p2align 3, 0x0
_Z5sobeliiiPjPi:
.quad _Z20__device_stub__sobeliiiPjPi
.size _Z5sobeliiiPjPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sobeliiiPjPi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sobeliiiPjPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sobeliiiPjPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5sobeliiiPjPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e280000002100 */
/*0050*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0060*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000ea20000002500 */
/*0070*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fc40000000000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ LEA R12, R7, R9, 0x5 ; /* 0x00000009070c7211 */
/* 0x001fe200078e28ff */
/*00a0*/ IMAD R10, R6, c[0x0][0x4], R7 ; /* 0x00000100060a7a24 */
/* 0x002fc800078e0207 */
/*00b0*/ STS [R12.X4], RZ ; /* 0x000000ff0c007388 */
/* 0x0001e20000004800 */
/*00c0*/ IMAD R11, R8, c[0x0][0x0], R9 ; /* 0x00000000080b7a24 */
/* 0x004fc800078e0209 */
/*00d0*/ IMAD R5, R10, c[0x0][0x160], R11 ; /* 0x000058000a057a24 */
/* 0x000fc800078e020b */
/*00e0*/ IMAD.WIDE R2, R5.reuse, R0.reuse, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x0c0fe200078e0200 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x000ea2000c1e1900 */
/*0110*/ ISETP.GE.AND P1, PT, R10.reuse, c[0x0][0x164], PT ; /* 0x000059000a007a0c */
/* 0x040fe20003f26270 */
/*0120*/ IMAD.WIDE R4, R5, R0, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fe200078e0200 */
/*0130*/ ISETP.GE.AND P0, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00780c */
/* 0x040fe20003f06270 */
/*0140*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*0150*/ ISETP.GE.OR P1, PT, R11, c[0x0][0x160], P1 ; /* 0x000058000b007a0c */
/* 0x000fe20000f26670 */
/*0160*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*0170*/ ISETP.LT.OR P0, PT, R10, 0x1, !P0 ; /* 0x000000010a00780c */
/* 0x000fc80004701670 */
/*0180*/ ISETP.GE.OR P0, PT, R10, UR4, P0 ; /* 0x000000040a007c0c */
/* 0x000fc80008706670 */
/*0190*/ ISETP.GE.OR P0, PT, R11, UR5, P0 ; /* 0x000000050b007c0c */
/* 0x000fe20008706670 */
/*01a0*/ STS [R12.X4], R13 ; /* 0x0000000d0c007388 */
/* 0x0041e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ @!P1 STG.E [R4.64], RZ ; /* 0x000000ff04009986 */
/* 0x0001e8000c101908 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R13, R7, -0x1, RZ ; /* 0xffffffff070d7810 */
/* 0x001fe20007ffe0ff */
/*0200*/ BSSY B0, 0x3d0 ; /* 0x000001c000007945 */
/* 0x000fe20003800000 */
/*0210*/ IADD3 R14, R9, -0x1, RZ ; /* 0xffffffff090e7810 */
/* 0x000fc40007ffe0ff */
/*0220*/ ISETP.GT.U32.AND P0, PT, R13, 0x1d, PT ; /* 0x0000001d0d00780c */
/* 0x000fe20003f04070 */
/*0230*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x4] ; /* 0x00000100ff0d7624 */
/* 0x000fc600078e00ff */
/*0240*/ ISETP.GT.U32.OR P0, PT, R14, 0x1d, P0 ; /* 0x0000001d0e00780c */
/* 0x000fda0000704470 */
/*0250*/ @P0 BRA 0x3c0 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*0260*/ LDS R14, [R12.X4+-0x84] ; /* 0xffff7c000c0e7984 */
/* 0x000fe80000004800 */
/*0270*/ LDS R15, [R12.X4+-0x7c] ; /* 0xffff84000c0f7984 */
/* 0x000e280000004800 */
/*0280*/ LDS R17, [R12.X4+0x4] ; /* 0x000004000c117984 */
/* 0x000e680000004800 */
/*0290*/ LDS R23, [R12.X4+-0x80] ; /* 0xffff80000c177984 */
/* 0x000ea80000004800 */
/*02a0*/ LDS R19, [R12.X4+-0x4] ; /* 0xfffffc000c137984 */
/* 0x000ee80000004800 */
/*02b0*/ LDS R18, [R12.X4+0x7c] ; /* 0x00007c000c127984 */
/* 0x000f280000004800 */
/*02c0*/ LDS R21, [R12.X4+0x84] ; /* 0x000084000c157984 */
/* 0x000f680000004800 */
/*02d0*/ LDS R20, [R12.X4+0x80] ; /* 0x000080000c147984 */
/* 0x000f620000004800 */
/*02e0*/ IMAD.IADD R16, R15, 0x1, -R14 ; /* 0x000000010f107824 */
/* 0x001fca00078e0a0e */
/*02f0*/ LEA R16, R17, R16, 0x1 ; /* 0x0000001011107211 */
/* 0x002fe200078e08ff */
/*0300*/ IMAD R23, R23, 0x2, R14 ; /* 0x0000000217177824 */
/* 0x004fc800078e020e */
/*0310*/ IMAD R16, R19, -0x2, R16 ; /* 0xfffffffe13107824 */
/* 0x008fe200078e0210 */
/*0320*/ IADD3 R23, -R18, R23, R15 ; /* 0x0000001712177210 */
/* 0x010fc80007ffe10f */
/*0330*/ IADD3 R16, -R18, R16, R21 ; /* 0x0000001012107210 */
/* 0x020fe20007ffe115 */
/*0340*/ IMAD R20, R20, -0x2, R23 ; /* 0xfffffffe14147824 */
/* 0x000fc800078e0217 */
/*0350*/ IMAD R15, R16, R16, RZ ; /* 0x00000010100f7224 */
/* 0x000fe400078e02ff */
/*0360*/ IMAD.IADD R20, R20, 0x1, -R21 ; /* 0x0000000114147824 */
/* 0x000fc800078e0a15 */
/*0370*/ IMAD R15, R20, R20, R15 ; /* 0x00000014140f7224 */
/* 0x000fca00078e020f */
/*0380*/ ISETP.GT.AND P0, PT, R15, c[0x0][0x168], PT ; /* 0x00005a000f007a0c */
/* 0x000fda0003f04270 */
/*0390*/ @P0 MOV R15, 0xff ; /* 0x000000ff000f0802 */
/* 0x000fe20000000f00 */
/*03a0*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e8000c101908 */
/*03b0*/ @P0 STG.E [R4.64], R15 ; /* 0x0000000f04000986 */
/* 0x0001e4000c101908 */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ IMAD R13, R6, R13, c[0x0][0x4] ; /* 0x00000100060d7624 */
/* 0x000fe200078e020d */
/*03e0*/ BSSY B0, 0x6a0 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*03f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0400*/ IADD3 R13, R13, -0x1, RZ ; /* 0xffffffff0d0d7810 */
/* 0x000fc60007ffe0ff */
/*0410*/ BSSY B1, 0x4d0 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0420*/ ISETP.NE.AND P0, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fda0003f05270 */
/*0430*/ @!P0 BRA 0x4c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0d7624 */
/* 0x000fe200078e00ff */
/*0450*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f25270 */
/*0460*/ IMAD R8, R8, R13, c[0x0][0x0] ; /* 0x0000000008087624 */
/* 0x000fca00078e020d */
/*0470*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0480*/ ISETP.NE.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x000fc80003f05270 */
/*0490*/ ISETP.NE.AND P0, PT, R7, RZ, P0 ; /* 0x000000ff0700720c */
/* 0x000fda0000705270 */
/*04a0*/ @P0 BREAK P1, B1 ; /* 0x0000000000010942 */
/* 0x000fe20000800000 */
/*04b0*/ @P0 BRA P1, 0x690 ; /* 0x000001d000000947 */
/* 0x000fea0000800000 */
/*04c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04d0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000408020d7981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ MOV R8, c[0x0][0x160] ; /* 0x0000580000087a02 */
/* 0x000fc60000000f00 */
/*0500*/ IMAD R11, R10, c[0x0][0x160], R11 ; /* 0x000058000a0b7a24 */
/* 0x000fe200078e020b */
/*0510*/ LDG.E R15, [R2.64+-0x4] ; /* 0xfffffc08020f7981 */
/* 0x001ee6000c1e1900 */
/*0520*/ IMAD.WIDE R6, R11, R0, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fc800078e0200 */
/*0530*/ IMAD R9, R8, 0x2, R11 ; /* 0x0000000208097824 */
/* 0x000fe200078e020b */
/*0540*/ LDG.E R10, [R6.64+-0x4] ; /* 0xfffffc08060a7981 */
/* 0x000f28000c1e1900 */
/*0550*/ LDG.E R11, [R6.64+0x4] ; /* 0x00000408060b7981 */
/* 0x000f22000c1e1900 */
/*0560*/ IMAD.WIDE R8, R9, R0, c[0x0][0x170] ; /* 0x00005c0009087625 */
/* 0x000fc600078e0200 */
/*0570*/ LDG.E R19, [R6.64] ; /* 0x0000000806137981 */
/* 0x000f68000c1e1900 */
/*0580*/ LDG.E R12, [R8.64+-0x4] ; /* 0xfffffc08080c7981 */
/* 0x000ee8000c1e1900 */
/*0590*/ LDG.E R17, [R8.64+0x4] ; /* 0x0000040808117981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R14, [R8.64] ; /* 0x00000008080e7981 */
/* 0x000ee2000c1e1900 */
/*05b0*/ IADD3 R0, -R10, R11, RZ ; /* 0x0000000b0a007210 */
/* 0x010fc80007ffe1ff */
/*05c0*/ LEA R0, R13, R0, 0x1 ; /* 0x000000000d007211 */
/* 0x004fe200078e08ff */
/*05d0*/ IMAD R19, R19, 0x2, R10 ; /* 0x0000000213137824 */
/* 0x020fc800078e020a */
/*05e0*/ IMAD R0, R15, -0x2, R0 ; /* 0xfffffffe0f007824 */
/* 0x008fe200078e0200 */
/*05f0*/ IADD3 R19, -R12, R19, R11 ; /* 0x000000130c137210 */
/* 0x000fc80007ffe10b */
/*0600*/ IADD3 R0, -R12, R0, R17 ; /* 0x000000000c007210 */
/* 0x000fe20007ffe111 */
/*0610*/ IMAD R14, R14, -0x2, R19 ; /* 0xfffffffe0e0e7824 */
/* 0x000fc800078e0213 */
/*0620*/ IMAD R3, R0, R0, RZ ; /* 0x0000000000037224 */
/* 0x000fe400078e02ff */
/*0630*/ IMAD.IADD R14, R14, 0x1, -R17 ; /* 0x000000010e0e7824 */
/* 0x000fc800078e0a11 */
/*0640*/ IMAD R3, R14, R14, R3 ; /* 0x0000000e0e037224 */
/* 0x000fca00078e0203 */
/*0650*/ ISETP.GT.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fda0003f04270 */
/*0660*/ @P0 MOV R3, 0xff ; /* 0x000000ff00030802 */
/* 0x000fe20000000f00 */
/*0670*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e8000c101908 */
/*0680*/ @P0 STG.E [R4.64], R3 ; /* 0x0000000304000986 */
/* 0x0001e4000c101908 */
/*0690*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sobeliiiPjPi
.globl _Z5sobeliiiPjPi
.p2align 8
.type _Z5sobeliiiPjPi,@function
_Z5sobeliiiPjPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x0
v_bfe_u32 v6, v0, 10, 10
v_dual_mov_b32 v12, 0 :: v_dual_and_b32 v7, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v11, 5, v6
v_add_nc_u32_e32 v10, v11, v7
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v13, 2, v10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s10, s2, 16
s_and_b32 s11, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s10, v[6:7]
v_mad_u64_u32 v[3:4], null, s14, s11, v[7:8]
ds_store_b32 v13, v12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mad_u64_u32 v[0:1], null, v2, s8, v[3:4]
v_cmp_gt_i32_e64 s2, s8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[8:9], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v9, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, s9, v2
global_load_b32 v14, v[4:5], off
s_and_b32 s3, vcc_lo, s2
s_waitcnt vmcnt(0)
ds_store_b32 v13, v14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_2
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_store_b32 v[8:9], v12, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_min_i32_e32 v8, v2, v3
s_add_i32 s2, s9, -1
s_add_i32 s3, s8, -1
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_cmp_gt_i32_e64 s2, s3, v3
v_cmp_lt_i32_e64 s3, 0, v8
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s3, s[0:1], 0x8
s_mov_b32 s1, exec_lo
v_cmpx_ne_u32_e32 0, v6
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v8, -1, v7
v_cmp_gt_u32_e32 vcc_lo, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, 30, v8
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_6
v_add_lshl_u32 v11, v11, v7, 2
v_lshlrev_b32_e32 v12, 2, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v10, 0xffffff80, v11
v_add_nc_u32_e32 v13, 0xffffff7c, v11
v_add_nc_u32_e32 v14, -4, v12
ds_load_2addr_b32 v[8:9], v11 offset0:31 offset1:32
ds_load_b32 v15, v11 offset:132
ds_load_2addr_b32 v[10:11], v10 offset1:1
ds_load_b32 v13, v13
ds_load_b32 v12, v12 offset:4
ds_load_b32 v14, v14
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v16, v11, v15
v_add_nc_u32_e32 v17, v13, v8
v_add_nc_u32_e32 v8, v15, v8
v_sub_nc_u32_e32 v12, v12, v14
v_add_nc_u32_e32 v11, v13, v11
v_sub_nc_u32_e32 v9, v10, v9
v_sub_nc_u32_e32 v14, v16, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v11, v8
v_lshl_add_u32 v12, v12, 1, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v13, v9, 1, v10
v_lshlrev_b64 v[9:10], 2, v[0:1]
v_mul_lo_u32 v8, v12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[11:12], null, v13, v13, v[8:9]
v_add_co_u32 v8, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_lt_i32_e32 vcc_lo, s3, v11
v_cndmask_b32_e64 v10, 0, 0xff, vcc_lo
global_store_b32 v[8:9], v10, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s11, s11, -1
v_cmp_eq_u32_e64 s0, 0, v6
v_cmp_eq_u32_e32 vcc_lo, s11, v7
s_add_i32 s10, s10, -1
v_cmp_eq_u32_e64 s1, 0, v7
v_cmp_eq_u32_e64 s2, s10, v6
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_or_b32 s0, s0, vcc_lo
s_barrier
s_or_b32 s0, s1, s0
buffer_gl0_inv
s_or_b32 s0, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_8
v_mul_lo_u32 v6, s8, v2
v_add_nc_u32_e32 v8, -1, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v2, v6, s8, v3
v_mad_u64_u32 v[6:7], null, v8, s8, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_clause 0x5
global_load_b64 v[8:9], v[2:3], off
global_load_b32 v10, v[2:3], off offset:-4
global_load_b64 v[2:3], v[6:7], off
global_load_b32 v6, v[6:7], off offset:-4
global_load_b32 v7, v[4:5], off offset:4
global_load_b32 v4, v[4:5], off offset:-4
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(3)
v_add_nc_u32_e32 v5, v3, v9
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v11, v6, v10
v_add_nc_u32_e32 v3, v6, v3
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v7, v4
v_add_nc_u32_e32 v6, v9, v10
v_sub_nc_u32_e32 v5, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v6
v_lshl_add_u32 v4, v4, 1, v5
v_sub_nc_u32_e32 v5, v2, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v4, v4
v_lshl_add_u32 v5, v5, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, v5, v[2:3]
v_cmp_lt_i32_e32 vcc_lo, s3, v3
v_cndmask_b32_e64 v2, 0, 0xff, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_8:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_9:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sobeliiiPjPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sobeliiiPjPi, .Lfunc_end0-_Z5sobeliiiPjPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sobeliiiPjPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sobeliiiPjPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012dc1a_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi
.type _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi, @function
_Z29__device_stub__Z5sobeliiiPjPiiiiPjPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sobeliiiPjPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi, .-_Z29__device_stub__Z5sobeliiiPjPiiiiPjPi
.globl _Z5sobeliiiPjPi
.type _Z5sobeliiiPjPi, @function
_Z5sobeliiiPjPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5sobeliiiPjPiiiiPjPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sobeliiiPjPi, .-_Z5sobeliiiPjPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5sobeliiiPjPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sobeliiiPjPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sobel.hip"
.globl _Z20__device_stub__sobeliiiPjPi # -- Begin function _Z20__device_stub__sobeliiiPjPi
.p2align 4, 0x90
.type _Z20__device_stub__sobeliiiPjPi,@function
_Z20__device_stub__sobeliiiPjPi: # @_Z20__device_stub__sobeliiiPjPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sobeliiiPjPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__sobeliiiPjPi, .Lfunc_end0-_Z20__device_stub__sobeliiiPjPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sobeliiiPjPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sobeliiiPjPi,@object # @_Z5sobeliiiPjPi
.section .rodata,"a",@progbits
.globl _Z5sobeliiiPjPi
.p2align 3, 0x0
_Z5sobeliiiPjPi:
.quad _Z20__device_stub__sobeliiiPjPi
.size _Z5sobeliiiPjPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sobeliiiPjPi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sobeliiiPjPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sobeliiiPjPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define LOG_BANK_SIZE 5
#define BLOCK_SIZE 256
#define LOG_BLOCK_SIZE 8
#define BLOCK_NUM 8
#define IDX(n) (n + ((n) >> LOG_BANK_SIZE))
#define CSC(call) do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); \
exit(1); \
} \
} while (0)
int getNearPow2(int n) {
int m = BLOCK_SIZE;
while (m < n) {
m <<= 1;
}
return m;
}
__global__ void makeKey(uint* in, uint* key, int n, int shift) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
key[i] = (in[i] >> shift) & 1;
}
}
__global__ void scan(uint* in, uint* out, uint* s, int gn) {
volatile extern __shared__ uint temp[];
int tid = threadIdx.x;
int shift = BLOCK_SIZE * blockIdx.x;
int n = BLOCK_SIZE;
while (shift < gn) {
int offset = 1;
int ai = tid;
int bi = tid + (n / 2);
temp[IDX(ai)] = in[ai + shift];
temp[IDX(bi)] = in[bi + shift];
for (int d = n >> 1; d > 0; d >>= 1) {
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
temp[IDX(bi)] += temp[IDX(ai)];
}
offset *= 2;
}
if (tid == 0) {
s[shift / BLOCK_SIZE] = temp[IDX(n - 1)];
temp[IDX(n - 1)] = 0;
}
for (int d = 1; d < n; d <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
uint t = temp[IDX(ai)];
temp[IDX(ai)] = temp[IDX(bi)];
temp[IDX(bi)] += t;
}
}
__syncthreads();
out[ai + shift] = temp[IDX(ai)];
out[bi + shift] = temp[IDX(bi)];
shift += gridDim.x * BLOCK_SIZE;
}
}
__global__ void sum(uint* in, uint* s, int n) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
in[i] += s[i >> LOG_BLOCK_SIZE];
}
}
__global__ void swap(uint* in, uint* out, uint* s, int n, uint mask) {
int beg = n - (s[n - 1] + !!(in[n - 1] & mask));
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
if ((in[i] & mask) == 0) {
out[i - s[i]] = in[i];
}
else {
out[beg + s[i]] = in[i];
}
}
}
uint** scanArr;
void largeScan(uint* dev_in, uint* dev_s, int n, int k) {
int sz = getNearPow2(n >> LOG_BLOCK_SIZE);
scan<<<BLOCK_NUM, BLOCK_SIZE / 2, sizeof(uint) * BLOCK_NUM * (BLOCK_SIZE + (BLOCK_SIZE >> LOG_BANK_SIZE)) >>> (dev_in, dev_s, scanArr[k], n);
if (n > BLOCK_SIZE) {
largeScan(scanArr[k], scanArr[k + 1], sz, k + 2);
sum<<<32, 32>>>(dev_s, scanArr[k + 1], n);
}
}
void SortBit(uint* dev_in, uint* dev_out, uint* dev_s, int n, int i) {
makeKey<<<32, 32>>>(dev_in, dev_out, n, i);
largeScan(dev_out, dev_s, n, 0);
swap<<<32, 32>>>(dev_in, dev_out, dev_s, n, 1u << i);
}
int main() {
int n;
fread(&n, sizeof(int), 1, stdin);
if (n == 0) return 0;
int sz = getNearPow2(n);
uint* ar = (uint*)malloc(sz * sizeof(uint));
fread(ar, sizeof(uint), n, stdin);
for (int i = n; i < sz; ++i) {
ar[i] = 0u - 1;
}
int tmp;
int cnt = 0;
for (tmp = sz; tmp > BLOCK_SIZE;) {
cnt++;
tmp = getNearPow2(tmp / BLOCK_SIZE);
}
scanArr = (uint**)malloc((2 * cnt + 1) * sizeof(uint*));
tmp = sz;
for (int i = 0; tmp > BLOCK_SIZE; i += 2) {
tmp = getNearPow2(tmp / BLOCK_SIZE);
CSC(cudaMalloc(&(scanArr[i]), sizeof(uint) * tmp));
CSC(cudaMalloc(&(scanArr[i + 1]), sizeof(uint) * tmp));
}
CSC(cudaMalloc(&(scanArr[2 * cnt]), sizeof(uint) * BLOCK_SIZE));
uint* dev_in;
uint* dev_out;
uint* dev_s;
CSC(cudaMalloc(&dev_in, sizeof(uint) * sz));
CSC(cudaMalloc(&dev_out, sizeof(uint) * sz));
CSC(cudaMalloc(&dev_s, sizeof(uint) * sz));
CSC(cudaMemcpy(dev_in, ar, sizeof(uint) * sz, cudaMemcpyHostToDevice));
for (int i = 0; i < 32; i += 2) {
SortBit(dev_in, dev_out, dev_s, sz, i);
SortBit(dev_out, dev_in, dev_s, sz, i + 1);
}
CSC(cudaMemcpy(ar, dev_in, sizeof(uint) * n, cudaMemcpyDeviceToHost));
for (int i = 0; i <= 2 * cnt; ++i) {
CSC(cudaFree(scanArr[i]));
}
CSC(cudaFree(dev_in));
CSC(cudaFree(dev_out));
CSC(cudaFree(dev_s));
free(scanArr);
fwrite(ar, sizeof(uint), n, stdout);
free(ar);
} | .file "tmpxft_00055e68_00000000-6_lab5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11getNearPow2i
.type _Z11getNearPow2i, @function
_Z11getNearPow2i:
.LFB2057:
.cfi_startproc
endbr64
cmpl $256, %edi
jle .L6
movl $256, %eax
.L5:
addl %eax, %eax
cmpl %eax, %edi
jg .L5
ret
.L6:
movl $256, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z11getNearPow2i, .-_Z11getNearPow2i
.globl _Z30__device_stub__Z7makeKeyPjS_iiPjS_ii
.type _Z30__device_stub__Z7makeKeyPjS_iiPjS_ii, @function
_Z30__device_stub__Z7makeKeyPjS_iiPjS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7makeKeyPjS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z30__device_stub__Z7makeKeyPjS_iiPjS_ii, .-_Z30__device_stub__Z7makeKeyPjS_iiPjS_ii
.globl _Z7makeKeyPjS_ii
.type _Z7makeKeyPjS_ii, @function
_Z7makeKeyPjS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7makeKeyPjS_iiPjS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7makeKeyPjS_ii, .-_Z7makeKeyPjS_ii
.globl _Z28__device_stub__Z4scanPjS_S_iPjS_S_i
.type _Z28__device_stub__Z4scanPjS_S_iPjS_S_i, @function
_Z28__device_stub__Z4scanPjS_S_iPjS_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4scanPjS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z28__device_stub__Z4scanPjS_S_iPjS_S_i, .-_Z28__device_stub__Z4scanPjS_S_iPjS_S_i
.globl _Z4scanPjS_S_i
.type _Z4scanPjS_S_i, @function
_Z4scanPjS_S_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4scanPjS_S_iPjS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z4scanPjS_S_i, .-_Z4scanPjS_S_i
.globl _Z25__device_stub__Z3sumPjS_iPjS_i
.type _Z25__device_stub__Z3sumPjS_iPjS_i, @function
_Z25__device_stub__Z3sumPjS_iPjS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPjS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z25__device_stub__Z3sumPjS_iPjS_i, .-_Z25__device_stub__Z3sumPjS_iPjS_i
.globl _Z3sumPjS_i
.type _Z3sumPjS_i, @function
_Z3sumPjS_i:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3sumPjS_iPjS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z3sumPjS_i, .-_Z3sumPjS_i
.globl _Z9largeScanPjS_ii
.type _Z9largeScanPjS_ii, @function
_Z9largeScanPjS_ii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %r14d
movl %edx, %eax
sarl $8, %eax
cmpl $65791, %edx
jle .L33
movl $256, %ebx
.L34:
addl %ebx, %ebx
cmpl %ebx, %eax
jg .L34
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $8448, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L39
.L41:
movslq %r14d, %rax
movq scanArr(%rip), %rdx
movq (%rdx,%rax,8), %rdx
movl %ebp, %ecx
movq %r12, %rsi
movq %r13, %rdi
call _Z28__device_stub__Z4scanPjS_S_iPjS_S_i
.L36:
cmpl $256, %ebp
jg .L39
.L32:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $8448, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
movl $256, %ebx
jmp .L36
.L46:
movl $256, %ebx
jmp .L41
.L39:
movq scanArr(%rip), %rax
movslq %r14d, %r13
addq $1, %r13
leal 2(%r14), %ecx
movq (%rax,%r13,8), %rsi
movq -8(%rax,%r13,8), %rdi
movl %ebx, %edx
call _Z9largeScanPjS_ii
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq scanArr(%rip), %rax
movq (%rax,%r13,8), %rsi
movl %ebp, %edx
movq %r12, %rdi
call _Z25__device_stub__Z3sumPjS_iPjS_i
jmp .L32
.cfi_endproc
.LFE2058:
.size _Z9largeScanPjS_ii, .-_Z9largeScanPjS_ii
.globl _Z29__device_stub__Z4swapPjS_S_ijPjS_S_ij
.type _Z29__device_stub__Z4swapPjS_S_ijPjS_S_ij, @function
_Z29__device_stub__Z4swapPjS_S_ijPjS_S_ij:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4swapPjS_S_ij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z29__device_stub__Z4swapPjS_S_ijPjS_S_ij, .-_Z29__device_stub__Z4swapPjS_S_ijPjS_S_ij
.globl _Z4swapPjS_S_ij
.type _Z4swapPjS_S_ij, @function
_Z4swapPjS_S_ij:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z4swapPjS_S_ijPjS_S_ij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z4swapPjS_S_ij, .-_Z4swapPjS_S_ij
.globl _Z7SortBitPjS_S_ii
.type _Z7SortBitPjS_S_ii, @function
_Z7SortBitPjS_S_ii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %rbx
movq %rdx, %r12
movl %ecx, %ebp
movl %r8d, %r14d
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L56:
movl $0, %ecx
movl %ebp, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _Z9largeScanPjS_ii
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L60
.L55:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
movl %r14d, %ecx
movl %ebp, %edx
movq %rbx, %rsi
movq %r13, %rdi
call _Z30__device_stub__Z7makeKeyPjS_iiPjS_ii
jmp .L56
.L60:
movl $1, %r8d
movl %r14d, %ecx
sall %cl, %r8d
movl %ebp, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %r13, %rdi
call _Z29__device_stub__Z4swapPjS_S_ijPjS_S_ij
jmp .L55
.cfi_endproc
.LFE2059:
.size _Z7SortBitPjS_S_ii, .-_Z7SortBitPjS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ssor96/CUDA_labs/master/lab5.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CUDA Error in %s:%d: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rdi
movq stdin(%rip), %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 28(%rsp), %ebx
testl %ebx, %ebx
jne .L104
.L62:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L105
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L104:
.cfi_restore_state
cmpl $256, %ebx
jle .L91
movl $256, %r13d
.L64:
addl %r13d, %r13d
cmpl %r13d, %ebx
jg .L64
.L63:
movslq %r13d, %r15
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
movslq %ebx, %rcx
movq stdin(%rip), %r8
movl $4, %edx
movq %r15, %rsi
movq %rax, %rdi
call __fread_chk@PLT
movl 28(%rsp), %edx
cmpl %r13d, %edx
jge .L65
movslq %edx, %rsi
leaq (%r14,%rsi,4), %rax
movl %r13d, %ecx
subl %edx, %ecx
leaq (%rcx,%rsi), %rdx
leaq (%r14,%rdx,4), %rdx
.L66:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L66
.L65:
cmpl $256, %r13d
jle .L67
movl %r13d, %eax
movl $0, %ecx
.L70:
addl $1, %ecx
leal 255(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $8, %edx
cmpl $65791, %eax
jle .L68
movl $256, %eax
.L69:
addl %eax, %eax
cmpl %eax, %edx
jg .L69
jmp .L70
.L91:
movl $256, %r13d
jmp .L63
.L68:
leal (%rcx,%rcx), %eax
movl %eax, 12(%rsp)
leal 1(%rax), %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, scanArr(%rip)
movl %r13d, %ebx
movl $8, %r12d
jmp .L75
.L72:
addl %ebx, %ebx
cmpl %ebx, %eax
jg .L72
.L71:
movslq %ebx, %rbp
salq $2, %rbp
movq scanArr(%rip), %rax
leaq -8(%rax,%r12), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L106
movq %r12, %rdi
addq scanArr(%rip), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L107
addq $16, %r12
cmpl $256, %ebx
jle .L89
.L75:
leal 255(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $8, %eax
cmpl $65791, %ebx
jle .L92
movl $256, %ebx
jmp .L72
.L92:
movl $256, %ebx
jmp .L71
.L106:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $135, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L107:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $136, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L108:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $138, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L109:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $143, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L110:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $144, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L111:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $145, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L112:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $146, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $152, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L113:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $154, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L114:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $156, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L115:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $157, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L116:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $158, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L67:
movl $8, %edi
call malloc@PLT
movq %rax, scanArr(%rip)
movl $0, 12(%rsp)
.L89:
movslq 12(%rsp), %rax
movq scanArr(%rip), %rdx
leaq (%rdx,%rax,8), %rdi
movl $1024, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L108
leaq 32(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L109
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L110
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L111
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
testl %eax, %eax
jne .L112
.L80:
movl %ebx, %r8d
movl %r13d, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z7SortBitPjS_S_ii
leal 1(%rbx), %r8d
movl %r13d, %ecx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z7SortBitPjS_S_ii
addl $2, %ebx
cmpl $32, %ebx
jne .L80
movslq 28(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L81
cmpl $0, 12(%rsp)
js .L83
movl 12(%rsp), %eax
leal 1(%rax), %ebp
salq $3, %rbp
movl $0, %ebx
.L85:
movq scanArr(%rip), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L113
addq $8, %rbx
cmpq %rbp, %rbx
jne .L85
.L83:
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L114
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L115
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L116
movq scanArr(%rip), %rdi
call free@PLT
movslq 28(%rsp), %rdx
movq stdout(%rip), %rcx
movl $4, %esi
movq %r14, %rdi
call fwrite@PLT
movq %r14, %rdi
call free@PLT
jmp .L62
.L105:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z4swapPjS_S_ij"
.LC3:
.string "_Z3sumPjS_i"
.LC4:
.string "_Z4scanPjS_S_i"
.LC5:
.string "_Z7makeKeyPjS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4swapPjS_S_ij(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPjS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4scanPjS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7makeKeyPjS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl scanArr
.bss
.align 8
.type scanArr, @object
.size scanArr, 8
scanArr:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define LOG_BANK_SIZE 5
#define BLOCK_SIZE 256
#define LOG_BLOCK_SIZE 8
#define BLOCK_NUM 8
#define IDX(n) (n + ((n) >> LOG_BANK_SIZE))
#define CSC(call) do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, cudaGetErrorString(res)); \
exit(1); \
} \
} while (0)
int getNearPow2(int n) {
int m = BLOCK_SIZE;
while (m < n) {
m <<= 1;
}
return m;
}
__global__ void makeKey(uint* in, uint* key, int n, int shift) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
key[i] = (in[i] >> shift) & 1;
}
}
__global__ void scan(uint* in, uint* out, uint* s, int gn) {
volatile extern __shared__ uint temp[];
int tid = threadIdx.x;
int shift = BLOCK_SIZE * blockIdx.x;
int n = BLOCK_SIZE;
while (shift < gn) {
int offset = 1;
int ai = tid;
int bi = tid + (n / 2);
temp[IDX(ai)] = in[ai + shift];
temp[IDX(bi)] = in[bi + shift];
for (int d = n >> 1; d > 0; d >>= 1) {
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
temp[IDX(bi)] += temp[IDX(ai)];
}
offset *= 2;
}
if (tid == 0) {
s[shift / BLOCK_SIZE] = temp[IDX(n - 1)];
temp[IDX(n - 1)] = 0;
}
for (int d = 1; d < n; d <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
uint t = temp[IDX(ai)];
temp[IDX(ai)] = temp[IDX(bi)];
temp[IDX(bi)] += t;
}
}
__syncthreads();
out[ai + shift] = temp[IDX(ai)];
out[bi + shift] = temp[IDX(bi)];
shift += gridDim.x * BLOCK_SIZE;
}
}
__global__ void sum(uint* in, uint* s, int n) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
in[i] += s[i >> LOG_BLOCK_SIZE];
}
}
__global__ void swap(uint* in, uint* out, uint* s, int n, uint mask) {
int beg = n - (s[n - 1] + !!(in[n - 1] & mask));
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
if ((in[i] & mask) == 0) {
out[i - s[i]] = in[i];
}
else {
out[beg + s[i]] = in[i];
}
}
}
uint** scanArr;
void largeScan(uint* dev_in, uint* dev_s, int n, int k) {
int sz = getNearPow2(n >> LOG_BLOCK_SIZE);
scan<<<BLOCK_NUM, BLOCK_SIZE / 2, sizeof(uint) * BLOCK_NUM * (BLOCK_SIZE + (BLOCK_SIZE >> LOG_BANK_SIZE)) >>> (dev_in, dev_s, scanArr[k], n);
if (n > BLOCK_SIZE) {
largeScan(scanArr[k], scanArr[k + 1], sz, k + 2);
sum<<<32, 32>>>(dev_s, scanArr[k + 1], n);
}
}
void SortBit(uint* dev_in, uint* dev_out, uint* dev_s, int n, int i) {
makeKey<<<32, 32>>>(dev_in, dev_out, n, i);
largeScan(dev_out, dev_s, n, 0);
swap<<<32, 32>>>(dev_in, dev_out, dev_s, n, 1u << i);
}
int main() {
int n;
fread(&n, sizeof(int), 1, stdin);
if (n == 0) return 0;
int sz = getNearPow2(n);
uint* ar = (uint*)malloc(sz * sizeof(uint));
fread(ar, sizeof(uint), n, stdin);
for (int i = n; i < sz; ++i) {
ar[i] = 0u - 1;
}
int tmp;
int cnt = 0;
for (tmp = sz; tmp > BLOCK_SIZE;) {
cnt++;
tmp = getNearPow2(tmp / BLOCK_SIZE);
}
scanArr = (uint**)malloc((2 * cnt + 1) * sizeof(uint*));
tmp = sz;
for (int i = 0; tmp > BLOCK_SIZE; i += 2) {
tmp = getNearPow2(tmp / BLOCK_SIZE);
CSC(cudaMalloc(&(scanArr[i]), sizeof(uint) * tmp));
CSC(cudaMalloc(&(scanArr[i + 1]), sizeof(uint) * tmp));
}
CSC(cudaMalloc(&(scanArr[2 * cnt]), sizeof(uint) * BLOCK_SIZE));
uint* dev_in;
uint* dev_out;
uint* dev_s;
CSC(cudaMalloc(&dev_in, sizeof(uint) * sz));
CSC(cudaMalloc(&dev_out, sizeof(uint) * sz));
CSC(cudaMalloc(&dev_s, sizeof(uint) * sz));
CSC(cudaMemcpy(dev_in, ar, sizeof(uint) * sz, cudaMemcpyHostToDevice));
for (int i = 0; i < 32; i += 2) {
SortBit(dev_in, dev_out, dev_s, sz, i);
SortBit(dev_out, dev_in, dev_s, sz, i + 1);
}
CSC(cudaMemcpy(ar, dev_in, sizeof(uint) * n, cudaMemcpyDeviceToHost));
for (int i = 0; i <= 2 * cnt; ++i) {
CSC(cudaFree(scanArr[i]));
}
CSC(cudaFree(dev_in));
CSC(cudaFree(dev_out));
CSC(cudaFree(dev_s));
free(scanArr);
fwrite(ar, sizeof(uint), n, stdout);
free(ar);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define LOG_BANK_SIZE 5
#define BLOCK_SIZE 256
#define LOG_BLOCK_SIZE 8
#define BLOCK_NUM 8
#define IDX(n) (n + ((n) >> LOG_BANK_SIZE))
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(1); \
} \
} while (0)
int getNearPow2(int n) {
int m = BLOCK_SIZE;
while (m < n) {
m <<= 1;
}
return m;
}
__global__ void makeKey(uint* in, uint* key, int n, int shift) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
key[i] = (in[i] >> shift) & 1;
}
}
__global__ void scan(uint* in, uint* out, uint* s, int gn) {
volatile extern __shared__ uint temp[];
int tid = threadIdx.x;
int shift = BLOCK_SIZE * blockIdx.x;
int n = BLOCK_SIZE;
while (shift < gn) {
int offset = 1;
int ai = tid;
int bi = tid + (n / 2);
temp[IDX(ai)] = in[ai + shift];
temp[IDX(bi)] = in[bi + shift];
for (int d = n >> 1; d > 0; d >>= 1) {
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
temp[IDX(bi)] += temp[IDX(ai)];
}
offset *= 2;
}
if (tid == 0) {
s[shift / BLOCK_SIZE] = temp[IDX(n - 1)];
temp[IDX(n - 1)] = 0;
}
for (int d = 1; d < n; d <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
uint t = temp[IDX(ai)];
temp[IDX(ai)] = temp[IDX(bi)];
temp[IDX(bi)] += t;
}
}
__syncthreads();
out[ai + shift] = temp[IDX(ai)];
out[bi + shift] = temp[IDX(bi)];
shift += gridDim.x * BLOCK_SIZE;
}
}
__global__ void sum(uint* in, uint* s, int n) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
in[i] += s[i >> LOG_BLOCK_SIZE];
}
}
__global__ void swap(uint* in, uint* out, uint* s, int n, uint mask) {
int beg = n - (s[n - 1] + !!(in[n - 1] & mask));
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
if ((in[i] & mask) == 0) {
out[i - s[i]] = in[i];
}
else {
out[beg + s[i]] = in[i];
}
}
}
uint** scanArr;
void largeScan(uint* dev_in, uint* dev_s, int n, int k) {
int sz = getNearPow2(n >> LOG_BLOCK_SIZE);
scan<<<BLOCK_NUM, BLOCK_SIZE / 2, sizeof(uint) * BLOCK_NUM * (BLOCK_SIZE + (BLOCK_SIZE >> LOG_BANK_SIZE)) >>> (dev_in, dev_s, scanArr[k], n);
if (n > BLOCK_SIZE) {
largeScan(scanArr[k], scanArr[k + 1], sz, k + 2);
sum<<<32, 32>>>(dev_s, scanArr[k + 1], n);
}
}
void SortBit(uint* dev_in, uint* dev_out, uint* dev_s, int n, int i) {
makeKey<<<32, 32>>>(dev_in, dev_out, n, i);
largeScan(dev_out, dev_s, n, 0);
swap<<<32, 32>>>(dev_in, dev_out, dev_s, n, 1u << i);
}
int main() {
int n;
fread(&n, sizeof(int), 1, stdin);
if (n == 0) return 0;
int sz = getNearPow2(n);
uint* ar = (uint*)malloc(sz * sizeof(uint));
fread(ar, sizeof(uint), n, stdin);
for (int i = n; i < sz; ++i) {
ar[i] = 0u - 1;
}
int tmp;
int cnt = 0;
for (tmp = sz; tmp > BLOCK_SIZE;) {
cnt++;
tmp = getNearPow2(tmp / BLOCK_SIZE);
}
scanArr = (uint**)malloc((2 * cnt + 1) * sizeof(uint*));
tmp = sz;
for (int i = 0; tmp > BLOCK_SIZE; i += 2) {
tmp = getNearPow2(tmp / BLOCK_SIZE);
CSC(hipMalloc(&(scanArr[i]), sizeof(uint) * tmp));
CSC(hipMalloc(&(scanArr[i + 1]), sizeof(uint) * tmp));
}
CSC(hipMalloc(&(scanArr[2 * cnt]), sizeof(uint) * BLOCK_SIZE));
uint* dev_in;
uint* dev_out;
uint* dev_s;
CSC(hipMalloc(&dev_in, sizeof(uint) * sz));
CSC(hipMalloc(&dev_out, sizeof(uint) * sz));
CSC(hipMalloc(&dev_s, sizeof(uint) * sz));
CSC(hipMemcpy(dev_in, ar, sizeof(uint) * sz, hipMemcpyHostToDevice));
for (int i = 0; i < 32; i += 2) {
SortBit(dev_in, dev_out, dev_s, sz, i);
SortBit(dev_out, dev_in, dev_s, sz, i + 1);
}
CSC(hipMemcpy(ar, dev_in, sizeof(uint) * n, hipMemcpyDeviceToHost));
for (int i = 0; i <= 2 * cnt; ++i) {
CSC(hipFree(scanArr[i]));
}
CSC(hipFree(dev_in));
CSC(hipFree(dev_out));
CSC(hipFree(dev_s));
free(scanArr);
fwrite(ar, sizeof(uint), n, stdout);
free(ar);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define LOG_BANK_SIZE 5
#define BLOCK_SIZE 256
#define LOG_BLOCK_SIZE 8
#define BLOCK_NUM 8
#define IDX(n) (n + ((n) >> LOG_BANK_SIZE))
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(1); \
} \
} while (0)
int getNearPow2(int n) {
int m = BLOCK_SIZE;
while (m < n) {
m <<= 1;
}
return m;
}
__global__ void makeKey(uint* in, uint* key, int n, int shift) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
key[i] = (in[i] >> shift) & 1;
}
}
__global__ void scan(uint* in, uint* out, uint* s, int gn) {
volatile extern __shared__ uint temp[];
int tid = threadIdx.x;
int shift = BLOCK_SIZE * blockIdx.x;
int n = BLOCK_SIZE;
while (shift < gn) {
int offset = 1;
int ai = tid;
int bi = tid + (n / 2);
temp[IDX(ai)] = in[ai + shift];
temp[IDX(bi)] = in[bi + shift];
for (int d = n >> 1; d > 0; d >>= 1) {
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
temp[IDX(bi)] += temp[IDX(ai)];
}
offset *= 2;
}
if (tid == 0) {
s[shift / BLOCK_SIZE] = temp[IDX(n - 1)];
temp[IDX(n - 1)] = 0;
}
for (int d = 1; d < n; d <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
uint t = temp[IDX(ai)];
temp[IDX(ai)] = temp[IDX(bi)];
temp[IDX(bi)] += t;
}
}
__syncthreads();
out[ai + shift] = temp[IDX(ai)];
out[bi + shift] = temp[IDX(bi)];
shift += gridDim.x * BLOCK_SIZE;
}
}
__global__ void sum(uint* in, uint* s, int n) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
in[i] += s[i >> LOG_BLOCK_SIZE];
}
}
__global__ void swap(uint* in, uint* out, uint* s, int n, uint mask) {
int beg = n - (s[n - 1] + !!(in[n - 1] & mask));
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
if ((in[i] & mask) == 0) {
out[i - s[i]] = in[i];
}
else {
out[beg + s[i]] = in[i];
}
}
}
uint** scanArr;
void largeScan(uint* dev_in, uint* dev_s, int n, int k) {
int sz = getNearPow2(n >> LOG_BLOCK_SIZE);
scan<<<BLOCK_NUM, BLOCK_SIZE / 2, sizeof(uint) * BLOCK_NUM * (BLOCK_SIZE + (BLOCK_SIZE >> LOG_BANK_SIZE)) >>> (dev_in, dev_s, scanArr[k], n);
if (n > BLOCK_SIZE) {
largeScan(scanArr[k], scanArr[k + 1], sz, k + 2);
sum<<<32, 32>>>(dev_s, scanArr[k + 1], n);
}
}
void SortBit(uint* dev_in, uint* dev_out, uint* dev_s, int n, int i) {
makeKey<<<32, 32>>>(dev_in, dev_out, n, i);
largeScan(dev_out, dev_s, n, 0);
swap<<<32, 32>>>(dev_in, dev_out, dev_s, n, 1u << i);
}
int main() {
int n;
fread(&n, sizeof(int), 1, stdin);
if (n == 0) return 0;
int sz = getNearPow2(n);
uint* ar = (uint*)malloc(sz * sizeof(uint));
fread(ar, sizeof(uint), n, stdin);
for (int i = n; i < sz; ++i) {
ar[i] = 0u - 1;
}
int tmp;
int cnt = 0;
for (tmp = sz; tmp > BLOCK_SIZE;) {
cnt++;
tmp = getNearPow2(tmp / BLOCK_SIZE);
}
scanArr = (uint**)malloc((2 * cnt + 1) * sizeof(uint*));
tmp = sz;
for (int i = 0; tmp > BLOCK_SIZE; i += 2) {
tmp = getNearPow2(tmp / BLOCK_SIZE);
CSC(hipMalloc(&(scanArr[i]), sizeof(uint) * tmp));
CSC(hipMalloc(&(scanArr[i + 1]), sizeof(uint) * tmp));
}
CSC(hipMalloc(&(scanArr[2 * cnt]), sizeof(uint) * BLOCK_SIZE));
uint* dev_in;
uint* dev_out;
uint* dev_s;
CSC(hipMalloc(&dev_in, sizeof(uint) * sz));
CSC(hipMalloc(&dev_out, sizeof(uint) * sz));
CSC(hipMalloc(&dev_s, sizeof(uint) * sz));
CSC(hipMemcpy(dev_in, ar, sizeof(uint) * sz, hipMemcpyHostToDevice));
for (int i = 0; i < 32; i += 2) {
SortBit(dev_in, dev_out, dev_s, sz, i);
SortBit(dev_out, dev_in, dev_s, sz, i + 1);
}
CSC(hipMemcpy(ar, dev_in, sizeof(uint) * n, hipMemcpyDeviceToHost));
for (int i = 0; i <= 2 * cnt; ++i) {
CSC(hipFree(scanArr[i]));
}
CSC(hipFree(dev_in));
CSC(hipFree(dev_out));
CSC(hipFree(dev_s));
free(scanArr);
fwrite(ar, sizeof(uint), n, stdout);
free(ar);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7makeKeyPjS_ii
.globl _Z7makeKeyPjS_ii
.p2align 8
.type _Z7makeKeyPjS_ii,@function
_Z7makeKeyPjS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x14
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_mov_b32 s3, 0
.p2align 6
.LBB0_2:
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b32 v0, v[4:5], off
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
v_cmp_le_i32_e64 s0, s10, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s3, s0, s3
s_waitcnt vmcnt(0)
v_bfe_u32 v0, v0, s1, 1
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7makeKeyPjS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7makeKeyPjS_ii, .Lfunc_end0-_Z7makeKeyPjS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4scanPjS_S_i
.globl _Z4scanPjS_S_i
.p2align 8
.type _Z4scanPjS_S_i,@function
_Z4scanPjS_S_i:
s_load_b32 s12, s[0:1], 0x18
s_lshl_b32 s13, s15, 8
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s13, s12
s_cbranch_scc1 .LBB1_13
v_dual_mov_b32 v12, 0 :: v_dual_add_nc_u32 v9, 0x80, v0
v_lshrrev_b32_e32 v1, 5, v0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 1, v0
v_lshrrev_b32_e32 v2, 5, v9
s_mov_b64 s[10:11], src_shared_base
v_add_nc_u32_e32 v1, v1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_or_b32_e32 v10, 1, v3
v_add_nc_u32_e32 v2, v2, v9
v_add_nc_u32_e32 v11, 2, v3
v_lshl_add_u32 v1, v1, 2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, v2, 2, 0
v_cmp_ne_u32_e64 s2, -1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s3, -1, v4
v_cndmask_b32_e64 v1, 0, v1, s2
v_cndmask_b32_e64 v2, 0, s11, s2
s_add_u32 s2, s0, 32
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v3, 0, v4, s3
v_cndmask_b32_e64 v4, 0, s11, s3
s_addc_u32 s3, s1, 0
s_add_i32 s10, 0, 0x418
s_branch .LBB1_3
.LBB1_2:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
flat_load_b32 v13, v[1:2] glc dlc
s_waitcnt vmcnt(0)
v_add_co_u32 v5, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_waitcnt lgkmcnt(0)
global_store_b32 v[5:6], v13, off
flat_load_b32 v13, v[3:4] glc dlc
s_waitcnt vmcnt(0)
v_add_co_u32 v5, s0, s6, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v8, s0
s_waitcnt lgkmcnt(0)
global_store_b32 v[5:6], v13, off
s_load_b32 s0, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s0, s0, 8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s0, s13
s_cmp_ge_i32 s13, s12
s_cbranch_scc1 .LBB1_13
.LBB1_3:
v_add_nc_u32_e32 v5, s13, v0
s_mov_b32 s14, 1
s_movk_i32 s15, 0x80
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s0, s4, v5
v_add_co_ci_u32_e64 v8, s0, s5, v6, s0
global_load_b32 v15, v[7:8], off
v_add_nc_u32_e32 v7, s13, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v13, s0, s4, v7
v_add_co_ci_u32_e64 v14, s0, s5, v8, s0
s_waitcnt vmcnt(0)
flat_store_b32 v[1:2], v15 dlc
s_waitcnt_vscnt null, 0x0
global_load_b32 v13, v[13:14], off
s_waitcnt vmcnt(0)
flat_store_b32 v[3:4], v13 dlc
s_waitcnt_vscnt null, 0x0
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s16
s_lshr_b32 s0, s15, 1
s_lshl_b32 s14, s14, 1
s_cmp_lt_u32 s15, 2
s_mov_b32 s15, s0
s_cbranch_scc1 .LBB1_7
.LBB1_5:
s_mov_b32 s16, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s15, v0
s_cbranch_execz .LBB1_4
v_mad_u64_u32 v[13:14], null, s14, v10, -1
v_mad_u64_u32 v[14:15], null, s14, v11, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v15, 5, v13
v_ashrrev_i32_e32 v16, 5, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, v15, v13
v_add_nc_u32_e32 v14, v16, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v13, v13, 2, 0
v_lshl_add_u32 v14, v14, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, -1, v13
v_cmp_ne_u32_e64 s1, -1, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, 0, v13, s0
v_cndmask_b32_e64 v15, 0, v14, s1
v_cndmask_b32_e64 v14, 0, s11, s0
v_cndmask_b32_e64 v16, 0, s11, s1
flat_load_b32 v13, v[13:14] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v14, v[15:16] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v13, v14, v13
flat_store_b32 v[15:16], v13 dlc
s_waitcnt_vscnt null, 0x0
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB1_9
s_cmp_lg_u32 s10, -1
v_mov_b32_e32 v16, 0
s_cselect_b32 s14, s10, 0
s_cselect_b32 s15, s11, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v13, s14 :: v_dual_mov_b32 v14, s15
s_ashr_i32 s14, s13, 8
s_ashr_i32 s15, s14, 31
flat_load_b32 v15, v[13:14] glc dlc
s_waitcnt vmcnt(0)
s_lshl_b64 s[14:15], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s8, s14
s_addc_u32 s15, s9, s15
s_waitcnt lgkmcnt(0)
global_store_b32 v12, v15, s[14:15]
flat_store_b32 v[13:14], v16 dlc
s_waitcnt_vscnt null, 0x0
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s0
s_mov_b32 s14, 1
s_movk_i32 s15, 0x100
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_11
.p2align 6
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s16
s_lshl_b32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_gt_i32 s14, 0xff
s_cbranch_scc1 .LBB1_2
.LBB1_11:
s_lshr_b32 s15, s15, 1
s_mov_b32 s16, exec_lo
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s14, v0
s_cbranch_execz .LBB1_10
v_mad_u32_u24 v13, s15, v10, -1
v_mad_u32_u24 v14, s15, v11, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v15, 5, v13
v_ashrrev_i32_e32 v16, 5, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, v15, v13
v_add_nc_u32_e32 v14, v16, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v13, v13, 2, 0
v_lshl_add_u32 v14, v14, 2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, -1, v13
v_cmp_ne_u32_e64 s1, -1, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, 0, v13, s0
v_cndmask_b32_e64 v15, 0, v14, s1
v_cndmask_b32_e64 v14, 0, s11, s0
v_cndmask_b32_e64 v16, 0, s11, s1
flat_load_b32 v17, v[13:14] glc dlc
s_waitcnt vmcnt(0)
flat_load_b32 v18, v[15:16] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
flat_store_b32 v[13:14], v18 dlc
s_waitcnt_vscnt null, 0x0
flat_load_b32 v13, v[15:16] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v13, v13, v17
flat_store_b32 v[15:16], v13 dlc
s_waitcnt_vscnt null, 0x0
s_branch .LBB1_10
.LBB1_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4scanPjS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4scanPjS_S_i, .Lfunc_end1-_Z4scanPjS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3sumPjS_i
.globl _Z3sumPjS_i
.p2align 8
.type _Z3sumPjS_i,@function
_Z3sumPjS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB2_3
s_load_b32 s5, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s1, 0
s_lshl_b64 s[6:7], s[4:5], 2
.p2align 6
.LBB2_2:
v_ashrrev_i32_e32 v4, 8, v1
global_load_b32 v0, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b32 v4, v[4:5], off
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
v_add_co_u32 v2, s0, v2, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPjS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3sumPjS_i, .Lfunc_end2-_Z3sumPjS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4swapPjS_S_ij
.globl _Z4swapPjS_S_ij
.p2align 8
.type _Z4swapPjS_S_ij,@function
_Z4swapPjS_S_ij:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_add_u32 s10, s0, 32
s_addc_u32 s11, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s3, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB3_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v2, 31, v1
s_lshl_b64 s[14:15], s[2:3], 2
v_mov_b32_e32 v3, 0
s_add_u32 s13, s14, -4
s_addc_u32 s16, s15, -1
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_add_u32 s14, s4, s13
s_addc_u32 s15, s5, s16
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s0, s[14:15], 0x0
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_cselect_b32 s14, -1, 0
s_add_u32 s0, s8, s13
s_addc_u32 s1, s9, s16
s_load_b32 s10, s[10:11], 0x0
s_load_b32 s0, s[0:1], 0x0
s_cmp_lg_u32 s14, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s10, s12
s_subb_u32 s14, s2, s0
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[10:11], 2
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB3_2:
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, s12
global_load_b32 v0, v[6:7], off
global_load_b32 v2, v[8:9], off
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v6, s3, v0
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v7, v1, v2
v_add_nc_u32_e32 v2, s14, v2
v_add_nc_u32_e32 v1, s10, v1
v_cmp_eq_u32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v7, s0
v_cmp_le_i32_e64 s0, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_or_b32 s15, s0, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s1, s6, v6
v_add_co_ci_u32_e64 v7, s1, s7, v7, s1
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4swapPjS_S_ij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z4swapPjS_S_ij, .Lfunc_end3-_Z4swapPjS_S_ij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym temp
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7makeKeyPjS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7makeKeyPjS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4scanPjS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z4scanPjS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPjS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3sumPjS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4swapPjS_S_ij
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z4swapPjS_S_ij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define LOG_BANK_SIZE 5
#define BLOCK_SIZE 256
#define LOG_BLOCK_SIZE 8
#define BLOCK_NUM 8
#define IDX(n) (n + ((n) >> LOG_BANK_SIZE))
#define CSC(call) do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n", __FILE__, __LINE__, hipGetErrorString(res)); \
exit(1); \
} \
} while (0)
int getNearPow2(int n) {
int m = BLOCK_SIZE;
while (m < n) {
m <<= 1;
}
return m;
}
__global__ void makeKey(uint* in, uint* key, int n, int shift) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
key[i] = (in[i] >> shift) & 1;
}
}
__global__ void scan(uint* in, uint* out, uint* s, int gn) {
volatile extern __shared__ uint temp[];
int tid = threadIdx.x;
int shift = BLOCK_SIZE * blockIdx.x;
int n = BLOCK_SIZE;
while (shift < gn) {
int offset = 1;
int ai = tid;
int bi = tid + (n / 2);
temp[IDX(ai)] = in[ai + shift];
temp[IDX(bi)] = in[bi + shift];
for (int d = n >> 1; d > 0; d >>= 1) {
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
temp[IDX(bi)] += temp[IDX(ai)];
}
offset *= 2;
}
if (tid == 0) {
s[shift / BLOCK_SIZE] = temp[IDX(n - 1)];
temp[IDX(n - 1)] = 0;
}
for (int d = 1; d < n; d <<= 1) {
offset >>= 1;
__syncthreads();
if (tid < d) {
int ai = offset * (2 * tid + 1) - 1;
int bi = offset * (2 * tid + 2) - 1;
uint t = temp[IDX(ai)];
temp[IDX(ai)] = temp[IDX(bi)];
temp[IDX(bi)] += t;
}
}
__syncthreads();
out[ai + shift] = temp[IDX(ai)];
out[bi + shift] = temp[IDX(bi)];
shift += gridDim.x * BLOCK_SIZE;
}
}
__global__ void sum(uint* in, uint* s, int n) {
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
in[i] += s[i >> LOG_BLOCK_SIZE];
}
}
__global__ void swap(uint* in, uint* out, uint* s, int n, uint mask) {
int beg = n - (s[n - 1] + !!(in[n - 1] & mask));
int offset = gridDim.x * blockDim.x;
for (int i = blockDim.x * blockIdx.x + threadIdx.x; i < n; i += offset) {
if ((in[i] & mask) == 0) {
out[i - s[i]] = in[i];
}
else {
out[beg + s[i]] = in[i];
}
}
}
uint** scanArr;
void largeScan(uint* dev_in, uint* dev_s, int n, int k) {
int sz = getNearPow2(n >> LOG_BLOCK_SIZE);
scan<<<BLOCK_NUM, BLOCK_SIZE / 2, sizeof(uint) * BLOCK_NUM * (BLOCK_SIZE + (BLOCK_SIZE >> LOG_BANK_SIZE)) >>> (dev_in, dev_s, scanArr[k], n);
if (n > BLOCK_SIZE) {
largeScan(scanArr[k], scanArr[k + 1], sz, k + 2);
sum<<<32, 32>>>(dev_s, scanArr[k + 1], n);
}
}
void SortBit(uint* dev_in, uint* dev_out, uint* dev_s, int n, int i) {
makeKey<<<32, 32>>>(dev_in, dev_out, n, i);
largeScan(dev_out, dev_s, n, 0);
swap<<<32, 32>>>(dev_in, dev_out, dev_s, n, 1u << i);
}
int main() {
int n;
fread(&n, sizeof(int), 1, stdin);
if (n == 0) return 0;
int sz = getNearPow2(n);
uint* ar = (uint*)malloc(sz * sizeof(uint));
fread(ar, sizeof(uint), n, stdin);
for (int i = n; i < sz; ++i) {
ar[i] = 0u - 1;
}
int tmp;
int cnt = 0;
for (tmp = sz; tmp > BLOCK_SIZE;) {
cnt++;
tmp = getNearPow2(tmp / BLOCK_SIZE);
}
scanArr = (uint**)malloc((2 * cnt + 1) * sizeof(uint*));
tmp = sz;
for (int i = 0; tmp > BLOCK_SIZE; i += 2) {
tmp = getNearPow2(tmp / BLOCK_SIZE);
CSC(hipMalloc(&(scanArr[i]), sizeof(uint) * tmp));
CSC(hipMalloc(&(scanArr[i + 1]), sizeof(uint) * tmp));
}
CSC(hipMalloc(&(scanArr[2 * cnt]), sizeof(uint) * BLOCK_SIZE));
uint* dev_in;
uint* dev_out;
uint* dev_s;
CSC(hipMalloc(&dev_in, sizeof(uint) * sz));
CSC(hipMalloc(&dev_out, sizeof(uint) * sz));
CSC(hipMalloc(&dev_s, sizeof(uint) * sz));
CSC(hipMemcpy(dev_in, ar, sizeof(uint) * sz, hipMemcpyHostToDevice));
for (int i = 0; i < 32; i += 2) {
SortBit(dev_in, dev_out, dev_s, sz, i);
SortBit(dev_out, dev_in, dev_s, sz, i + 1);
}
CSC(hipMemcpy(ar, dev_in, sizeof(uint) * n, hipMemcpyDeviceToHost));
for (int i = 0; i <= 2 * cnt; ++i) {
CSC(hipFree(scanArr[i]));
}
CSC(hipFree(dev_in));
CSC(hipFree(dev_out));
CSC(hipFree(dev_s));
free(scanArr);
fwrite(ar, sizeof(uint), n, stdout);
free(ar);
} | .text
.file "lab5.hip"
.globl _Z11getNearPow2i # -- Begin function _Z11getNearPow2i
.p2align 4, 0x90
.type _Z11getNearPow2i,@function
_Z11getNearPow2i: # @_Z11getNearPow2i
.cfi_startproc
# %bb.0:
movl $256, %ecx # imm = 0x100
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ecx, %eax
leal (%rax,%rax), %ecx
cmpl %edi, %eax
jl .LBB0_1
# %bb.2:
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end0:
.size _Z11getNearPow2i, .Lfunc_end0-_Z11getNearPow2i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__makeKeyPjS_ii # -- Begin function _Z22__device_stub__makeKeyPjS_ii
.p2align 4, 0x90
.type _Z22__device_stub__makeKeyPjS_ii,@function
_Z22__device_stub__makeKeyPjS_ii: # @_Z22__device_stub__makeKeyPjS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7makeKeyPjS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__makeKeyPjS_ii, .Lfunc_end1-_Z22__device_stub__makeKeyPjS_ii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__scanPjS_S_i # -- Begin function _Z19__device_stub__scanPjS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__scanPjS_S_i,@function
_Z19__device_stub__scanPjS_S_i: # @_Z19__device_stub__scanPjS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPjS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z19__device_stub__scanPjS_S_i, .Lfunc_end2-_Z19__device_stub__scanPjS_S_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__sumPjS_i # -- Begin function _Z18__device_stub__sumPjS_i
.p2align 4, 0x90
.type _Z18__device_stub__sumPjS_i,@function
_Z18__device_stub__sumPjS_i: # @_Z18__device_stub__sumPjS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPjS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z18__device_stub__sumPjS_i, .Lfunc_end3-_Z18__device_stub__sumPjS_i
.cfi_endproc
# -- End function
.globl _Z19__device_stub__swapPjS_S_ij # -- Begin function _Z19__device_stub__swapPjS_S_ij
.p2align 4, 0x90
.type _Z19__device_stub__swapPjS_S_ij,@function
_Z19__device_stub__swapPjS_S_ij: # @_Z19__device_stub__swapPjS_S_ij
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4swapPjS_S_ij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z19__device_stub__swapPjS_S_ij, .Lfunc_end4-_Z19__device_stub__swapPjS_S_ij
.cfi_endproc
# -- End function
.globl _Z9largeScanPjS_ii # -- Begin function _Z9largeScanPjS_ii
.p2align 4, 0x90
.type _Z9largeScanPjS_ii,@function
_Z9largeScanPjS_ii: # @_Z9largeScanPjS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r13
movl %edx, %eax
sarl $8, %eax
movl $256, %ecx # imm = 0x100
.p2align 4, 0x90
.LBB5_1: # =>This Inner Loop Header: Depth=1
movl %ecx, %r12d
leal (%r12,%r12), %ecx
cmpl %eax, %r12d
jl .LBB5_1
# %bb.2: # %_Z11getNearPow2i.exit
movabsq $4294967328, %r15 # imm = 0x100000020
leaq -24(%r15), %rdi
leaq 96(%r15), %rdx
movl $8448, %r8d # imm = 0x2100
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB5_3
# %bb.4:
cmpl $257, %ebx # imm = 0x101
jge .LBB5_5
jmp .LBB5_7
.LBB5_3:
movq scanArr(%rip), %rax
movslq %ebp, %rcx
movq (%rax,%rcx,8), %rax
movq %r13, 64(%rsp)
movq %r14, 56(%rsp)
movq %rax, 16(%rsp)
movl %ebx, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4scanPjS_S_i, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $257, %ebx # imm = 0x101
jl .LBB5_7
.LBB5_5:
movq scanArr(%rip), %rax
movslq %ebp, %r13
movq (%rax,%r13,8), %rdi
movq 8(%rax,%r13,8), %rsi
addl $2, %ebp
movl %r12d, %edx
movl %ebp, %ecx
callq _Z9largeScanPjS_ii
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_7
# %bb.6:
incq %r13
movq scanArr(%rip), %rax
movq (%rax,%r13,8), %rax
movq %r14, 64(%rsp)
movq %rax, 56(%rsp)
movl %ebx, (%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPjS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_7:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z9largeScanPjS_ii, .Lfunc_end5-_Z9largeScanPjS_ii
.cfi_endproc
# -- End function
.globl _Z7SortBitPjS_S_ii # -- Begin function _Z7SortBitPjS_S_ii
.p2align 4, 0x90
.type _Z7SortBitPjS_S_ii,@function
_Z7SortBitPjS_S_ii: # @_Z7SortBitPjS_S_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r8d, %ebp
movl %ecx, %ebx
movq %rdx, 88(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %r14
movabsq $4294967328, %r13 # imm = 0x100000020
movq %r13, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movq %r14, 72(%rsp)
movq %r15, 64(%rsp)
movl %ebx, 8(%rsp)
movl %ebp, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7makeKeyPjS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movl %ebp, %r12d
movq %r15, %rdi
movq 88(%rsp), %rsi # 8-byte Reload
movl %ebx, %edx
xorl %ecx, %ecx
callq _Z9largeScanPjS_ii
movl $1, %ebp
movq %r13, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
movl %r12d, %ecx
shll %cl, %ebp
movq %r14, 72(%rsp)
movq %r15, 64(%rsp)
movq 88(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %ebx, 4(%rsp)
movl %ebp, 84(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 84(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4swapPjS_S_ij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7SortBitPjS_S_ii, .Lfunc_end6-_Z7SortBitPjS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq stdin(%rip), %rcx
leaq 28(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq fread
movslq 28(%rsp), %r15
testq %r15, %r15
je .LBB7_45
# %bb.1: # %.preheader100.preheader
movl $256, %eax # imm = 0x100
.p2align 4, 0x90
.LBB7_2: # %.preheader100
# =>This Inner Loop Header: Depth=1
movl %eax, %ebx
leal (%rbx,%rbx), %eax
cmpl %r15d, %ebx
jl .LBB7_2
# %bb.3: # %_Z11getNearPow2i.exit
movslq %ebx, %rdi
shlq $2, %rdi
movq %rdi, 48(%rsp) # 8-byte Spill
callq malloc
movq stdin(%rip), %rcx
movl $4, %esi
movq %rax, 32(%rsp) # 8-byte Spill
movq %rax, %rdi
movq %r15, %rdx
callq fread
cmpl %ebx, %r15d
jge .LBB7_5
# %bb.4: # %.lr.ph.preheader
movq 32(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15,4), %rdi
movl %r15d, %eax
notl %eax
addl %ebx, %eax
leaq 4(,%rax,4), %rdx
movl $255, %esi
callq memset@PLT
.LBB7_5: # %.preheader99
xorl %r14d, %r14d
cmpl $257, %ebx # imm = 0x101
jl .LBB7_11
# %bb.6: # %.lr.ph107.preheader
xorl %r14d, %r14d
movl %ebx, %eax
.p2align 4, 0x90
.LBB7_7: # %.lr.ph107
# =>This Loop Header: Depth=1
# Child Loop BB7_8 Depth 2
movl %eax, %ecx
shrl $8, %ecx
movl $256, %edx # imm = 0x100
.p2align 4, 0x90
.LBB7_8: # Parent Loop BB7_7 Depth=1
# => This Inner Loop Header: Depth=2
movl %edx, %eax
leal (%rax,%rax), %edx
cmpl %ecx, %eax
jl .LBB7_8
# %bb.9: # %_Z11getNearPow2i.exit95
# in Loop: Header=BB7_7 Depth=1
incl %r14d
cmpl $256, %eax # imm = 0x100
jg .LBB7_7
# %bb.10: # %._crit_edge.loopexit
addl %r14d, %r14d
.LBB7_11: # %._crit_edge
movq %r15, 40(%rsp) # 8-byte Spill
movl %r14d, %ebp
orl $1, %ebp
leaq (,%rbp,8), %rdi
callq malloc
movq %rax, scanArr(%rip)
cmpl $257, %ebx # imm = 0x101
jl .LBB7_19
# %bb.12: # %.lr.ph111.preheader
xorl %r12d, %r12d
movl %ebx, %r15d
.p2align 4, 0x90
.LBB7_13: # %.lr.ph111
# =>This Loop Header: Depth=1
# Child Loop BB7_14 Depth 2
movl %r15d, %eax
shrl $8, %eax
movl $256, %ecx # imm = 0x100
.p2align 4, 0x90
.LBB7_14: # Parent Loop BB7_13 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %r15d
leal (%r15,%r15), %ecx
cmpl %eax, %r15d
jl .LBB7_14
# %bb.15: # %_Z11getNearPow2i.exit97
# in Loop: Header=BB7_13 Depth=1
leaq (,%r12,8), %rdi
addq scanArr(%rip), %rdi
movslq %r15d, %r13
shlq $2, %r13
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_16
# %bb.21: # in Loop: Header=BB7_13 Depth=1
movq scanArr(%rip), %rax
leaq (%rax,%r12,8), %rdi
addq $8, %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_22
# %bb.18: # in Loop: Header=BB7_13 Depth=1
addq $2, %r12
cmpl $256, %r15d # imm = 0x100
jg .LBB7_13
.LBB7_19: # %._crit_edge112
movl %r14d, %edi
shlq $3, %rdi
addq scanArr(%rip), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB7_20
# %bb.23:
movq %rsp, %rdi
movq 48(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
movq 32(%rsp), %r15 # 8-byte Reload
jne .LBB7_24
# %bb.25:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_26
# %bb.27:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_28
# %bb.29:
movq (%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_46
# %bb.30: # %.preheader98.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_31: # %.preheader98
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movl %ebx, %ecx
movl %r12d, %r8d
callq _Z7SortBitPjS_S_ii
movq 16(%rsp), %rdi
movq (%rsp), %rsi
movq 8(%rsp), %rdx
leal 1(%r12), %r8d
movl %ebx, %ecx
callq _Z7SortBitPjS_S_ii
leal 2(%r12), %eax
cmpl $30, %r12d
movl %eax, %r12d
jb .LBB7_31
# %bb.32:
movq (%rsp), %rsi
movq 40(%rsp), %r14 # 8-byte Reload
leaq (,%r14,4), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_36
# %bb.33: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB7_34: # %.preheader
# =>This Inner Loop Header: Depth=1
movq scanArr(%rip), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_35
# %bb.37: # in Loop: Header=BB7_34 Depth=1
incq %rbx
cmpq %rbx, %rbp
jne .LBB7_34
# %bb.38:
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_39
# %bb.40:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_41
# %bb.42:
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB7_43
# %bb.44:
movq scanArr(%rip), %rdi
callq free
movq stdout(%rip), %rcx
movl $4, %esi
movq %r15, %rdi
movq %r14, %rdx
callq fwrite
movq %r15, %rdi
callq free
.LBB7_45:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_35:
.cfi_def_cfa_offset 112
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $156, %ecx
jmp .LBB7_17
.LBB7_22:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $138, %ecx
jmp .LBB7_17
.LBB7_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $137, %ecx
.LBB7_17:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB7_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $140, %ecx
jmp .LBB7_17
.LBB7_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $145, %ecx
jmp .LBB7_17
.LBB7_26:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $146, %ecx
jmp .LBB7_17
.LBB7_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $147, %ecx
jmp .LBB7_17
.LBB7_46:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $148, %ecx
jmp .LBB7_17
.LBB7_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $154, %ecx
jmp .LBB7_17
.LBB7_39:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $158, %ecx
jmp .LBB7_17
.LBB7_41:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $159, %ecx
jmp .LBB7_17
.LBB7_43:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movl $160, %ecx
jmp .LBB7_17
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7makeKeyPjS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4scanPjS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPjS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4swapPjS_S_ij, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7makeKeyPjS_ii,@object # @_Z7makeKeyPjS_ii
.section .rodata,"a",@progbits
.globl _Z7makeKeyPjS_ii
.p2align 3, 0x0
_Z7makeKeyPjS_ii:
.quad _Z22__device_stub__makeKeyPjS_ii
.size _Z7makeKeyPjS_ii, 8
.type _Z4scanPjS_S_i,@object # @_Z4scanPjS_S_i
.globl _Z4scanPjS_S_i
.p2align 3, 0x0
_Z4scanPjS_S_i:
.quad _Z19__device_stub__scanPjS_S_i
.size _Z4scanPjS_S_i, 8
.type _Z3sumPjS_i,@object # @_Z3sumPjS_i
.globl _Z3sumPjS_i
.p2align 3, 0x0
_Z3sumPjS_i:
.quad _Z18__device_stub__sumPjS_i
.size _Z3sumPjS_i, 8
.type _Z4swapPjS_S_ij,@object # @_Z4swapPjS_S_ij
.globl _Z4swapPjS_S_ij
.p2align 3, 0x0
_Z4swapPjS_S_ij:
.quad _Z19__device_stub__swapPjS_S_ij
.size _Z4swapPjS_S_ij, 8
.type scanArr,@object # @scanArr
.bss
.globl scanArr
.p2align 3, 0x0
scanArr:
.quad 0
.size scanArr, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA Error in %s:%d: %s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ssor96/CUDA_labs/master/lab5.hip"
.size .L.str.1, 90
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7makeKeyPjS_ii"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4scanPjS_S_i"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z3sumPjS_i"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z4swapPjS_S_ij"
.size .L__unnamed_4, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__makeKeyPjS_ii
.addrsig_sym _Z19__device_stub__scanPjS_S_i
.addrsig_sym _Z18__device_stub__sumPjS_i
.addrsig_sym _Z19__device_stub__swapPjS_S_ij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7makeKeyPjS_ii
.addrsig_sym _Z4scanPjS_S_i
.addrsig_sym _Z3sumPjS_i
.addrsig_sym _Z4swapPjS_S_ij
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=[32,1] --gridDim=[1,1]
#include <cuda.h>
#define NUM 32
__global__ void BitonicKernel(int * values)
{
__shared__ int shared[NUM];
unsigned int tid = threadIdx.x;
// Copy input to shared mem.
shared[tid] = values[tid];
#ifdef MUTATION
if (threadIdx.x == 0) {
#endif
__syncthreads();
#ifdef MUTATION
/* BUGINJECT: NON_UNIFORM_CONTROL_FLOW, UP */
}
#endif
// Parallel bitonic sort.
for (unsigned int k = 2;
k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2;
j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
else
{
if (shared[tid] < shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
}
__syncthreads();
}
}
// Write result.
values[tid] = shared[tid];
} | code for sm_80
Function : _Z13BitonicKernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ LOP3.LUT R7, R0.reuse, 0x1, RZ, 0x3c, !PT ; /* 0x0000000100077812 */
/* 0x040fe200078e3cff */
/*0070*/ BSSY B0, 0x1b0 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*0080*/ ISETP.GT.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f04070 */
/*0090*/ IMAD.SHL.U32 R7, R0, 0x4, RZ ; /* 0x0000000400077824 */
/* 0x000fca00078e00ff */
/*00a0*/ LOP3.LUT R4, R7, 0x4, RZ, 0x3c, !PT ; /* 0x0000000407047812 */
/* 0x000fe200078e3cff */
/*00b0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00d0*/ @!P0 BRA 0x1a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*00e0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x0010620000004800 */
/*00f0*/ LOP3.LUT P1, RZ, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200ff7812 */
/* 0x000fc6000782c0ff */
/*0100*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0000b40000000800 */
/*0110*/ @!P1 BRA 0x170 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GE.AND P1, PT, R5, R9, PT ; /* 0x000000090500720c */
/* 0x007fda0003f26270 */
/*0130*/ @P1 BRA 0x1a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0140*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0150*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*0160*/ BRA 0x1a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R5, R9, PT ; /* 0x000000090500720c */
/* 0x007fda0003f24270 */
/*0180*/ @P1 STS [R0.X4], R9 ; /* 0x0000000900001388 */
/* 0x0001e80000004800 */
/*0190*/ @P1 STS [R4], R9 ; /* 0x0000000904001388 */
/* 0x0001e40000000800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01b0*/ LOP3.LUT R5, R0.reuse, 0x2, RZ, 0x3c, !PT ; /* 0x0000000200057812 */
/* 0x040fe200078e3cff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ LOP3.LUT R8, R0, 0x4, RZ, 0xc0, !PT ; /* 0x0000000400087812 */
/* 0x000fe400078ec0ff */
/*01e0*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe40003f24070 */
/*01f0*/ LOP3.LUT R5, R7, 0x8, RZ, 0x3c, !PT ; /* 0x0000000807057812 */
/* 0x000fe200078e3cff */
/*0200*/ BSSY B0, 0x2f0 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0210*/ @!P1 BRA 0x2e0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0220*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x0000620000004800 */
/*0230*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f45270 */
/*0240*/ LDS R9, [R5] ; /* 0x0000000005097984 */
/* 0x0000b40000000800 */
/*0250*/ @!P2 BRA 0x2b0 ; /* 0x000000500000a947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GE.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f46270 */
/*0270*/ @P2 BRA 0x2e0 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*0280*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0290*/ STS [R5], R9 ; /* 0x0000000905007388 */
/* 0x0001e20000000800 */
/*02a0*/ BRA 0x2e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.GT.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f44270 */
/*02c0*/ @P2 STS [R0.X4], R9 ; /* 0x0000000900002388 */
/* 0x0001e80000004800 */
/*02d0*/ @P2 STS [R5], R9 ; /* 0x0000000905002388 */
/* 0x0001e40000000800 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ BSSY B0, 0x3f0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0310*/ @!P0 BRA 0x3e0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0320*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x0002a20000004800 */
/*0330*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f45270 */
/*0340*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0012340000000800 */
/*0350*/ @!P2 BRA 0x3b0 ; /* 0x000000500000a947 */
/* 0x000fea0003800000 */
/*0360*/ ISETP.GE.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f46270 */
/*0370*/ @P2 BRA 0x3e0 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*0380*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0390*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*03a0*/ BRA 0x3e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GT.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f44270 */
/*03c0*/ @P2 STS [R0.X4], R9 ; /* 0x0000000900002388 */
/* 0x0001e80000004800 */
/*03d0*/ @P2 STS [R4], R9 ; /* 0x0000000904002388 */
/* 0x0001e40000000800 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT R9, R0.reuse, 0x4, RZ, 0x3c, !PT ; /* 0x0000000400097812 */
/* 0x041fe200078e3cff */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0410*/ LOP3.LUT R10, R0, 0x8, RZ, 0xc0, !PT ; /* 0x00000008000a7812 */
/* 0x000fe400078ec0ff */
/*0420*/ ISETP.GT.U32.AND P2, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f44070 */
/*0430*/ LOP3.LUT R6, R7, 0x10, RZ, 0x3c, !PT ; /* 0x0000001007067812 */
/* 0x000fe200078e3cff */
/*0440*/ BSSY B0, 0x530 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0450*/ @!P2 BRA 0x520 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*0460*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0000620000004800 */
/*0470*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0480*/ LDS R9, [R6] ; /* 0x0000000006097984 */
/* 0x0000b40000000800 */
/*0490*/ @!P3 BRA 0x4f0 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*04a0*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*04b0*/ @P3 BRA 0x520 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*04c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*04d0*/ STS [R6], R9 ; /* 0x0000000906007388 */
/* 0x0001e20000000800 */
/*04e0*/ BRA 0x520 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0500*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0510*/ @P3 STS [R6], R9 ; /* 0x0000000906003388 */
/* 0x0001e40000000800 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0540*/ BSSY B0, 0x630 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0550*/ @!P1 BRA 0x620 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0560*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0570*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0580*/ LDS R9, [R5] ; /* 0x0000000005097984 */
/* 0x0012340000000800 */
/*0590*/ @!P3 BRA 0x5f0 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*05b0*/ @P3 BRA 0x620 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*05c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*05d0*/ STS [R5], R9 ; /* 0x0000000905007388 */
/* 0x0001e20000000800 */
/*05e0*/ BRA 0x620 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0600*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0610*/ @P3 STS [R5], R9 ; /* 0x0000000905003388 */
/* 0x0001e40000000800 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ BSSY B0, 0x730 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0650*/ @!P0 BRA 0x720 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0660*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0670*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0680*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0012340000000800 */
/*0690*/ @!P3 BRA 0x6f0 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*06b0*/ @P3 BRA 0x720 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*06c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*06d0*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*06e0*/ BRA 0x720 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0700*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0710*/ @P3 STS [R4], R9 ; /* 0x0000000904003388 */
/* 0x0001e40000000800 */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT R9, R0.reuse, 0x8, RZ, 0x3c, !PT ; /* 0x0000000800097812 */
/* 0x041fe200078e3cff */
/*0740*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0750*/ LOP3.LUT R7, R7, 0x20, RZ, 0x3c, !PT ; /* 0x0000002007077812 */
/* 0x000fe400078e3cff */
/*0760*/ ISETP.GT.U32.AND P3, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f64070 */
/*0770*/ LOP3.LUT R10, R0, 0x10, RZ, 0xc0, !PT ; /* 0x00000010000a7812 */
/* 0x000fe200078ec0ff */
/*0780*/ BSSY B0, 0x870 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0790*/ @!P3 BRA 0x860 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*07a0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0000620000004800 */
/*07b0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*07c0*/ LDS R9, [R7] ; /* 0x0000000007097984 */
/* 0x0000b40000000800 */
/*07d0*/ @!P4 BRA 0x830 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*07f0*/ @P4 BRA 0x860 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0800*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0810*/ STS [R7], R9 ; /* 0x0000000907007388 */
/* 0x0001e20000000800 */
/*0820*/ BRA 0x860 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0840*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0850*/ @P4 STS [R7], R9 ; /* 0x0000000907004388 */
/* 0x0001e40000000800 */
/*0860*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0870*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0880*/ BSSY B0, 0x970 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0890*/ @!P2 BRA 0x960 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*08a0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*08b0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*08c0*/ LDS R9, [R6] ; /* 0x0000000006097984 */
/* 0x0012340000000800 */
/*08d0*/ @!P4 BRA 0x930 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*08f0*/ @P4 BRA 0x960 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0900*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0910*/ STS [R6], R9 ; /* 0x0000000906007388 */
/* 0x0001e20000000800 */
/*0920*/ BRA 0x960 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0940*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0950*/ @P4 STS [R6], R9 ; /* 0x0000000906004388 */
/* 0x0001e40000000800 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0980*/ BSSY B0, 0xa70 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0990*/ @!P1 BRA 0xa60 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*09a0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*09b0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*09c0*/ LDS R9, [R5] ; /* 0x0000000005097984 */
/* 0x0012340000000800 */
/*09d0*/ @!P4 BRA 0xa30 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*09f0*/ @P4 BRA 0xa60 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0a00*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0a10*/ STS [R5], R9 ; /* 0x0000000905007388 */
/* 0x0001e20000000800 */
/*0a20*/ BRA 0xa60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0a40*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0a50*/ @P4 STS [R5], R9 ; /* 0x0000000905004388 */
/* 0x0001e40000000800 */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a80*/ BSSY B0, 0xb70 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0a90*/ @!P0 BRA 0xb60 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0ab0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*0ac0*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0012340000000800 */
/*0ad0*/ @!P4 BRA 0xb30 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*0ae0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*0af0*/ @P4 BRA 0xb60 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0b00*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0b10*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*0b20*/ BRA 0xb60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0b40*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0b50*/ @P4 STS [R4], R9 ; /* 0x0000000904004388 */
/* 0x0001e40000000800 */
/*0b60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R9, R0.reuse, 0x10, RZ, 0x3c, !PT ; /* 0x0000001000097812 */
/* 0x041fe200078e3cff */
/*0b80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b90*/ LOP3.LUT R10, R0, 0x20, RZ, 0xc0, !PT ; /* 0x00000020000a7812 */
/* 0x000fe400078ec0ff */
/*0ba0*/ ISETP.GT.U32.AND P4, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fc60003f84070 */
/*0bb0*/ BSSY B0, 0xca0 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0bc0*/ @!P4 BRA 0xc90 ; /* 0x000000c00000c947 */
/* 0x000fea0003800000 */
/*0bd0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0000620000004800 */
/*0be0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*0bf0*/ LDS R11, [R9.X4] ; /* 0x00000000090b7984 */
/* 0x0000b40000004800 */
/*0c00*/ @!P4 BRA 0xc60 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.GE.AND P4, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x007fda0003f86270 */
/*0c20*/ @P4 BRA 0xc90 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0c30*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e80000004800 */
/*0c40*/ STS [R9.X4], R11 ; /* 0x0000000b09007388 */
/* 0x0001e20000004800 */
/*0c50*/ BRA 0xc90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c60*/ ISETP.GT.AND P4, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x007fda0003f84270 */
/*0c70*/ @P4 STS [R0.X4], R11 ; /* 0x0000000b00004388 */
/* 0x0001e80000004800 */
/*0c80*/ @P4 STS [R9.X4], R11 ; /* 0x0000000b09004388 */
/* 0x0001e40000004800 */
/*0c90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ca0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0cb0*/ BSSY B0, 0xda0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0cc0*/ @!P3 BRA 0xd90 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*0cd0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0ce0*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0cf0*/ LDS R9, [R7] ; /* 0x0000000007097984 */
/* 0x0012340000000800 */
/*0d00*/ @!P3 BRA 0xd60 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*0d10*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*0d20*/ @P3 BRA 0xd90 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*0d30*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0d40*/ STS [R7], R9 ; /* 0x0000000907007388 */
/* 0x0001e20000000800 */
/*0d50*/ BRA 0xd90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0d60*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0d70*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0d80*/ @P3 STS [R7], R9 ; /* 0x0000000907003388 */
/* 0x0001e40000000800 */
/*0d90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0da0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0db0*/ BSSY B0, 0xea0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0dc0*/ @!P2 BRA 0xe90 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*0dd0*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x0010620000004800 */
/*0de0*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f45270 */
/*0df0*/ LDS R9, [R6] ; /* 0x0000000006097984 */
/* 0x0000b40000000800 */
/*0e00*/ @!P2 BRA 0xe60 ; /* 0x000000500000a947 */
/* 0x000fea0003800000 */
/*0e10*/ ISETP.GE.AND P2, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x007fda0003f46270 */
/*0e20*/ @P2 BRA 0xe90 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*0e30*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0e40*/ STS [R6], R9 ; /* 0x0000000906007388 */
/* 0x0001e20000000800 */
/*0e50*/ BRA 0xe90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e60*/ ISETP.GT.AND P2, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x007fda0003f44270 */
/*0e70*/ @P2 STS [R0.X4], R9 ; /* 0x0000000900002388 */
/* 0x0001e80000004800 */
/*0e80*/ @P2 STS [R6], R9 ; /* 0x0000000906002388 */
/* 0x0001e40000000800 */
/*0e90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ea0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0eb0*/ BSSY B0, 0xfa0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0ec0*/ @!P1 BRA 0xf90 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0ed0*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x0010620000004800 */
/*0ee0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f25270 */
/*0ef0*/ LDS R7, [R5] ; /* 0x0000000005077984 */
/* 0x0000b40000000800 */
/*0f00*/ @!P1 BRA 0xf60 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0f10*/ ISETP.GE.AND P1, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x007fda0003f26270 */
/*0f20*/ @P1 BRA 0xf90 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0f30*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0f40*/ STS [R5], R7 ; /* 0x0000000705007388 */
/* 0x0001e20000000800 */
/*0f50*/ BRA 0xf90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0f60*/ ISETP.GT.AND P1, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x007fda0003f24270 */
/*0f70*/ @P1 STS [R0.X4], R7 ; /* 0x0000000700001388 */
/* 0x0001e80000004800 */
/*0f80*/ @P1 STS [R5], R7 ; /* 0x0000000705001388 */
/* 0x0001e40000000800 */
/*0f90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0fa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0fb0*/ BSSY B0, 0x10a0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0fc0*/ @!P0 BRA 0x1090 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0fd0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x0010620000004800 */
/*0fe0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f05270 */
/*0ff0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x0000b40000000800 */
/*1000*/ @!P0 BRA 0x1060 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*1010*/ ISETP.GE.AND P0, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x007fda0003f06270 */
/*1020*/ @P0 BRA 0x1090 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*1030*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*1040*/ STS [R4], R7 ; /* 0x0000000704007388 */
/* 0x0001e20000000800 */
/*1050*/ BRA 0x1090 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1060*/ ISETP.GT.AND P0, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x007fda0003f04270 */
/*1070*/ @P0 STS [R0.X4], R7 ; /* 0x0000000700000388 */
/* 0x0001e80000004800 */
/*1080*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*1090*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*10a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*10b0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x001e280000004800 */
/*10c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*10d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10e0*/ BRA 0x10e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=[32,1] --gridDim=[1,1]
#include <cuda.h>
#define NUM 32
__global__ void BitonicKernel(int * values)
{
__shared__ int shared[NUM];
unsigned int tid = threadIdx.x;
// Copy input to shared mem.
shared[tid] = values[tid];
#ifdef MUTATION
if (threadIdx.x == 0) {
#endif
__syncthreads();
#ifdef MUTATION
/* BUGINJECT: NON_UNIFORM_CONTROL_FLOW, UP */
}
#endif
// Parallel bitonic sort.
for (unsigned int k = 2;
k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2;
j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
else
{
if (shared[tid] < shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
}
__syncthreads();
}
}
// Write result.
values[tid] = shared[tid];
} | .file "tmpxft_000e29f1_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z13BitonicKernelPiPi
.type _Z33__device_stub__Z13BitonicKernelPiPi, @function
_Z33__device_stub__Z13BitonicKernelPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13BitonicKernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z13BitonicKernelPiPi, .-_Z33__device_stub__Z13BitonicKernelPiPi
.globl _Z13BitonicKernelPi
.type _Z13BitonicKernelPi, @function
_Z13BitonicKernelPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13BitonicKernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13BitonicKernelPi, .-_Z13BitonicKernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13BitonicKernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13BitonicKernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=[32,1] --gridDim=[1,1]
#include <cuda.h>
#define NUM 32
__global__ void BitonicKernel(int * values)
{
__shared__ int shared[NUM];
unsigned int tid = threadIdx.x;
// Copy input to shared mem.
shared[tid] = values[tid];
#ifdef MUTATION
if (threadIdx.x == 0) {
#endif
__syncthreads();
#ifdef MUTATION
/* BUGINJECT: NON_UNIFORM_CONTROL_FLOW, UP */
}
#endif
// Parallel bitonic sort.
for (unsigned int k = 2;
k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2;
j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
else
{
if (shared[tid] < shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
}
__syncthreads();
}
}
// Write result.
values[tid] = shared[tid];
} | //pass
//--blockDim=[32,1] --gridDim=[1,1]
#include <hip/hip_runtime.h>
#define NUM 32
__global__ void BitonicKernel(int * values)
{
__shared__ int shared[NUM];
unsigned int tid = threadIdx.x;
// Copy input to shared mem.
shared[tid] = values[tid];
#ifdef MUTATION
if (threadIdx.x == 0) {
#endif
__syncthreads();
#ifdef MUTATION
/* BUGINJECT: NON_UNIFORM_CONTROL_FLOW, UP */
}
#endif
// Parallel bitonic sort.
for (unsigned int k = 2;
k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2;
j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
else
{
if (shared[tid] < shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
}
__syncthreads();
}
}
// Write result.
values[tid] = shared[tid];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=[32,1] --gridDim=[1,1]
#include <hip/hip_runtime.h>
#define NUM 32
__global__ void BitonicKernel(int * values)
{
__shared__ int shared[NUM];
unsigned int tid = threadIdx.x;
// Copy input to shared mem.
shared[tid] = values[tid];
#ifdef MUTATION
if (threadIdx.x == 0) {
#endif
__syncthreads();
#ifdef MUTATION
/* BUGINJECT: NON_UNIFORM_CONTROL_FLOW, UP */
}
#endif
// Parallel bitonic sort.
for (unsigned int k = 2;
k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2;
j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
else
{
if (shared[tid] < shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
}
__syncthreads();
}
}
// Write result.
values[tid] = shared[tid];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13BitonicKernelPi
.globl _Z13BitonicKernelPi
.p2align 8
.type _Z13BitonicKernelPi,@function
_Z13BitonicKernelPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s1, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 16
s_mov_b32 s1, s0
s_cbranch_scc1 .LBB0_11
.LBB0_2:
v_and_b32_e32 v4, s1, v0
s_mov_b32 s2, s1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
.LBB0_4:
s_mov_b32 s3, s2
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
v_xor_b32_e32 v4, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v4, v0
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v4, 2, v4
s_mov_b32 s5, 0
ds_load_b32 v6, v3
ds_load_b32 v5, v4
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s0, v6, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s5, s0, exec_lo
.LBB0_7:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_9
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, v6, v5
s_and_not1_b32 s5, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s5, s5, s0
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_3
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v5
ds_store_b32 v4, v5
s_branch .LBB0_3
.LBB0_11:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13BitonicKernelPi
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13BitonicKernelPi, .Lfunc_end0-_Z13BitonicKernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13BitonicKernelPi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z13BitonicKernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=[32,1] --gridDim=[1,1]
#include <hip/hip_runtime.h>
#define NUM 32
__global__ void BitonicKernel(int * values)
{
__shared__ int shared[NUM];
unsigned int tid = threadIdx.x;
// Copy input to shared mem.
shared[tid] = values[tid];
#ifdef MUTATION
if (threadIdx.x == 0) {
#endif
__syncthreads();
#ifdef MUTATION
/* BUGINJECT: NON_UNIFORM_CONTROL_FLOW, UP */
}
#endif
// Parallel bitonic sort.
for (unsigned int k = 2;
k <= NUM; k *= 2)
{
// Bitonic merge:
for (unsigned int j = k / 2;
j>0; j /= 2)
{
unsigned int ixj = tid ^ j;
if (ixj > tid)
{
if ((tid & k) == 0)
{
if (shared[tid] > shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
else
{
if (shared[tid] < shared[ixj])
{
unsigned int tmp = shared[tid];
shared[tid] = shared[ixj];
shared[ixj] = shared[tid];
}
}
}
__syncthreads();
}
}
// Write result.
values[tid] = shared[tid];
} | .text
.file "kernel.hip"
.globl _Z28__device_stub__BitonicKernelPi # -- Begin function _Z28__device_stub__BitonicKernelPi
.p2align 4, 0x90
.type _Z28__device_stub__BitonicKernelPi,@function
_Z28__device_stub__BitonicKernelPi: # @_Z28__device_stub__BitonicKernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13BitonicKernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__BitonicKernelPi, .Lfunc_end0-_Z28__device_stub__BitonicKernelPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13BitonicKernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13BitonicKernelPi,@object # @_Z13BitonicKernelPi
.section .rodata,"a",@progbits
.globl _Z13BitonicKernelPi
.p2align 3, 0x0
_Z13BitonicKernelPi:
.quad _Z28__device_stub__BitonicKernelPi
.size _Z13BitonicKernelPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13BitonicKernelPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__BitonicKernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13BitonicKernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13BitonicKernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ LOP3.LUT R7, R0.reuse, 0x1, RZ, 0x3c, !PT ; /* 0x0000000100077812 */
/* 0x040fe200078e3cff */
/*0070*/ BSSY B0, 0x1b0 ; /* 0x0000013000007945 */
/* 0x000fe60003800000 */
/*0080*/ ISETP.GT.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f04070 */
/*0090*/ IMAD.SHL.U32 R7, R0, 0x4, RZ ; /* 0x0000000400077824 */
/* 0x000fca00078e00ff */
/*00a0*/ LOP3.LUT R4, R7, 0x4, RZ, 0x3c, !PT ; /* 0x0000000407047812 */
/* 0x000fe200078e3cff */
/*00b0*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00d0*/ @!P0 BRA 0x1a0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*00e0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x0010620000004800 */
/*00f0*/ LOP3.LUT P1, RZ, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200ff7812 */
/* 0x000fc6000782c0ff */
/*0100*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0000b40000000800 */
/*0110*/ @!P1 BRA 0x170 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GE.AND P1, PT, R5, R9, PT ; /* 0x000000090500720c */
/* 0x007fda0003f26270 */
/*0130*/ @P1 BRA 0x1a0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0140*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0150*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*0160*/ BRA 0x1a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R5, R9, PT ; /* 0x000000090500720c */
/* 0x007fda0003f24270 */
/*0180*/ @P1 STS [R0.X4], R9 ; /* 0x0000000900001388 */
/* 0x0001e80000004800 */
/*0190*/ @P1 STS [R4], R9 ; /* 0x0000000904001388 */
/* 0x0001e40000000800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01b0*/ LOP3.LUT R5, R0.reuse, 0x2, RZ, 0x3c, !PT ; /* 0x0000000200057812 */
/* 0x040fe200078e3cff */
/*01c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01d0*/ LOP3.LUT R8, R0, 0x4, RZ, 0xc0, !PT ; /* 0x0000000400087812 */
/* 0x000fe400078ec0ff */
/*01e0*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe40003f24070 */
/*01f0*/ LOP3.LUT R5, R7, 0x8, RZ, 0x3c, !PT ; /* 0x0000000807057812 */
/* 0x000fe200078e3cff */
/*0200*/ BSSY B0, 0x2f0 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0210*/ @!P1 BRA 0x2e0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0220*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x0000620000004800 */
/*0230*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f45270 */
/*0240*/ LDS R9, [R5] ; /* 0x0000000005097984 */
/* 0x0000b40000000800 */
/*0250*/ @!P2 BRA 0x2b0 ; /* 0x000000500000a947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GE.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f46270 */
/*0270*/ @P2 BRA 0x2e0 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*0280*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0290*/ STS [R5], R9 ; /* 0x0000000905007388 */
/* 0x0001e20000000800 */
/*02a0*/ BRA 0x2e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*02b0*/ ISETP.GT.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f44270 */
/*02c0*/ @P2 STS [R0.X4], R9 ; /* 0x0000000900002388 */
/* 0x0001e80000004800 */
/*02d0*/ @P2 STS [R5], R9 ; /* 0x0000000905002388 */
/* 0x0001e40000000800 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ BSSY B0, 0x3f0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0310*/ @!P0 BRA 0x3e0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0320*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x0002a20000004800 */
/*0330*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f45270 */
/*0340*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0012340000000800 */
/*0350*/ @!P2 BRA 0x3b0 ; /* 0x000000500000a947 */
/* 0x000fea0003800000 */
/*0360*/ ISETP.GE.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f46270 */
/*0370*/ @P2 BRA 0x3e0 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*0380*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0390*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*03a0*/ BRA 0x3e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GT.AND P2, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x007fda0003f44270 */
/*03c0*/ @P2 STS [R0.X4], R9 ; /* 0x0000000900002388 */
/* 0x0001e80000004800 */
/*03d0*/ @P2 STS [R4], R9 ; /* 0x0000000904002388 */
/* 0x0001e40000000800 */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ LOP3.LUT R9, R0.reuse, 0x4, RZ, 0x3c, !PT ; /* 0x0000000400097812 */
/* 0x041fe200078e3cff */
/*0400*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0410*/ LOP3.LUT R10, R0, 0x8, RZ, 0xc0, !PT ; /* 0x00000008000a7812 */
/* 0x000fe400078ec0ff */
/*0420*/ ISETP.GT.U32.AND P2, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f44070 */
/*0430*/ LOP3.LUT R6, R7, 0x10, RZ, 0x3c, !PT ; /* 0x0000001007067812 */
/* 0x000fe200078e3cff */
/*0440*/ BSSY B0, 0x530 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0450*/ @!P2 BRA 0x520 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*0460*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0000620000004800 */
/*0470*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0480*/ LDS R9, [R6] ; /* 0x0000000006097984 */
/* 0x0000b40000000800 */
/*0490*/ @!P3 BRA 0x4f0 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*04a0*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*04b0*/ @P3 BRA 0x520 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*04c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*04d0*/ STS [R6], R9 ; /* 0x0000000906007388 */
/* 0x0001e20000000800 */
/*04e0*/ BRA 0x520 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0500*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0510*/ @P3 STS [R6], R9 ; /* 0x0000000906003388 */
/* 0x0001e40000000800 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0540*/ BSSY B0, 0x630 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0550*/ @!P1 BRA 0x620 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0560*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0570*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0580*/ LDS R9, [R5] ; /* 0x0000000005097984 */
/* 0x0012340000000800 */
/*0590*/ @!P3 BRA 0x5f0 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*05b0*/ @P3 BRA 0x620 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*05c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*05d0*/ STS [R5], R9 ; /* 0x0000000905007388 */
/* 0x0001e20000000800 */
/*05e0*/ BRA 0x620 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*05f0*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0600*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0610*/ @P3 STS [R5], R9 ; /* 0x0000000905003388 */
/* 0x0001e40000000800 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ BSSY B0, 0x730 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0650*/ @!P0 BRA 0x720 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0660*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0670*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0680*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0012340000000800 */
/*0690*/ @!P3 BRA 0x6f0 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*06a0*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*06b0*/ @P3 BRA 0x720 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*06c0*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*06d0*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*06e0*/ BRA 0x720 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*06f0*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0700*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0710*/ @P3 STS [R4], R9 ; /* 0x0000000904003388 */
/* 0x0001e40000000800 */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT R9, R0.reuse, 0x8, RZ, 0x3c, !PT ; /* 0x0000000800097812 */
/* 0x041fe200078e3cff */
/*0740*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0750*/ LOP3.LUT R7, R7, 0x20, RZ, 0x3c, !PT ; /* 0x0000002007077812 */
/* 0x000fe400078e3cff */
/*0760*/ ISETP.GT.U32.AND P3, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f64070 */
/*0770*/ LOP3.LUT R10, R0, 0x10, RZ, 0xc0, !PT ; /* 0x00000010000a7812 */
/* 0x000fe200078ec0ff */
/*0780*/ BSSY B0, 0x870 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0790*/ @!P3 BRA 0x860 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*07a0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0000620000004800 */
/*07b0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*07c0*/ LDS R9, [R7] ; /* 0x0000000007097984 */
/* 0x0000b40000000800 */
/*07d0*/ @!P4 BRA 0x830 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*07e0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*07f0*/ @P4 BRA 0x860 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0800*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0810*/ STS [R7], R9 ; /* 0x0000000907007388 */
/* 0x0001e20000000800 */
/*0820*/ BRA 0x860 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0840*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0850*/ @P4 STS [R7], R9 ; /* 0x0000000907004388 */
/* 0x0001e40000000800 */
/*0860*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0870*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0880*/ BSSY B0, 0x970 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0890*/ @!P2 BRA 0x960 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*08a0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*08b0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*08c0*/ LDS R9, [R6] ; /* 0x0000000006097984 */
/* 0x0012340000000800 */
/*08d0*/ @!P4 BRA 0x930 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*08f0*/ @P4 BRA 0x960 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0900*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0910*/ STS [R6], R9 ; /* 0x0000000906007388 */
/* 0x0001e20000000800 */
/*0920*/ BRA 0x960 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0940*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0950*/ @P4 STS [R6], R9 ; /* 0x0000000906004388 */
/* 0x0001e40000000800 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0980*/ BSSY B0, 0xa70 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0990*/ @!P1 BRA 0xa60 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*09a0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*09b0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*09c0*/ LDS R9, [R5] ; /* 0x0000000005097984 */
/* 0x0012340000000800 */
/*09d0*/ @!P4 BRA 0xa30 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*09e0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*09f0*/ @P4 BRA 0xa60 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0a00*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0a10*/ STS [R5], R9 ; /* 0x0000000905007388 */
/* 0x0001e20000000800 */
/*0a20*/ BRA 0xa60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a30*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0a40*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0a50*/ @P4 STS [R5], R9 ; /* 0x0000000905004388 */
/* 0x0001e40000000800 */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a80*/ BSSY B0, 0xb70 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0a90*/ @!P0 BRA 0xb60 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0ab0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*0ac0*/ LDS R9, [R4] ; /* 0x0000000004097984 */
/* 0x0012340000000800 */
/*0ad0*/ @!P4 BRA 0xb30 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*0ae0*/ ISETP.GE.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f86270 */
/*0af0*/ @P4 BRA 0xb60 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0b00*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0b10*/ STS [R4], R9 ; /* 0x0000000904007388 */
/* 0x0001e20000000800 */
/*0b20*/ BRA 0xb60 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.GT.AND P4, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f84270 */
/*0b40*/ @P4 STS [R0.X4], R9 ; /* 0x0000000900004388 */
/* 0x0001e80000004800 */
/*0b50*/ @P4 STS [R4], R9 ; /* 0x0000000904004388 */
/* 0x0001e40000000800 */
/*0b60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R9, R0.reuse, 0x10, RZ, 0x3c, !PT ; /* 0x0000001000097812 */
/* 0x041fe200078e3cff */
/*0b80*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b90*/ LOP3.LUT R10, R0, 0x20, RZ, 0xc0, !PT ; /* 0x00000020000a7812 */
/* 0x000fe400078ec0ff */
/*0ba0*/ ISETP.GT.U32.AND P4, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fc60003f84070 */
/*0bb0*/ BSSY B0, 0xca0 ; /* 0x000000e000007945 */
/* 0x000ff40003800000 */
/*0bc0*/ @!P4 BRA 0xc90 ; /* 0x000000c00000c947 */
/* 0x000fea0003800000 */
/*0bd0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0000620000004800 */
/*0be0*/ ISETP.NE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f85270 */
/*0bf0*/ LDS R11, [R9.X4] ; /* 0x00000000090b7984 */
/* 0x0000b40000004800 */
/*0c00*/ @!P4 BRA 0xc60 ; /* 0x000000500000c947 */
/* 0x000fea0003800000 */
/*0c10*/ ISETP.GE.AND P4, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x007fda0003f86270 */
/*0c20*/ @P4 BRA 0xc90 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0c30*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e80000004800 */
/*0c40*/ STS [R9.X4], R11 ; /* 0x0000000b09007388 */
/* 0x0001e20000004800 */
/*0c50*/ BRA 0xc90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0c60*/ ISETP.GT.AND P4, PT, R8, R11, PT ; /* 0x0000000b0800720c */
/* 0x007fda0003f84270 */
/*0c70*/ @P4 STS [R0.X4], R11 ; /* 0x0000000b00004388 */
/* 0x0001e80000004800 */
/*0c80*/ @P4 STS [R9.X4], R11 ; /* 0x0000000b09004388 */
/* 0x0001e40000004800 */
/*0c90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ca0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0cb0*/ BSSY B0, 0xda0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0cc0*/ @!P3 BRA 0xd90 ; /* 0x000000c00000b947 */
/* 0x000fea0003800000 */
/*0cd0*/ LDS R8, [R0.X4] ; /* 0x0000000000087984 */
/* 0x0002a20000004800 */
/*0ce0*/ ISETP.NE.AND P3, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f65270 */
/*0cf0*/ LDS R9, [R7] ; /* 0x0000000007097984 */
/* 0x0012340000000800 */
/*0d00*/ @!P3 BRA 0xd60 ; /* 0x000000500000b947 */
/* 0x000fea0003800000 */
/*0d10*/ ISETP.GE.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f66270 */
/*0d20*/ @P3 BRA 0xd90 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*0d30*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0d40*/ STS [R7], R9 ; /* 0x0000000907007388 */
/* 0x0001e20000000800 */
/*0d50*/ BRA 0xd90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0d60*/ ISETP.GT.AND P3, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x007fda0003f64270 */
/*0d70*/ @P3 STS [R0.X4], R9 ; /* 0x0000000900003388 */
/* 0x0001e80000004800 */
/*0d80*/ @P3 STS [R7], R9 ; /* 0x0000000907003388 */
/* 0x0001e40000000800 */
/*0d90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0da0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0db0*/ BSSY B0, 0xea0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0dc0*/ @!P2 BRA 0xe90 ; /* 0x000000c00000a947 */
/* 0x000fea0003800000 */
/*0dd0*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x0010620000004800 */
/*0de0*/ ISETP.NE.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f45270 */
/*0df0*/ LDS R9, [R6] ; /* 0x0000000006097984 */
/* 0x0000b40000000800 */
/*0e00*/ @!P2 BRA 0xe60 ; /* 0x000000500000a947 */
/* 0x000fea0003800000 */
/*0e10*/ ISETP.GE.AND P2, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x007fda0003f46270 */
/*0e20*/ @P2 BRA 0xe90 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*0e30*/ STS [R0.X4], R9 ; /* 0x0000000900007388 */
/* 0x0001e80000004800 */
/*0e40*/ STS [R6], R9 ; /* 0x0000000906007388 */
/* 0x0001e20000000800 */
/*0e50*/ BRA 0xe90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e60*/ ISETP.GT.AND P2, PT, R7, R9, PT ; /* 0x000000090700720c */
/* 0x007fda0003f44270 */
/*0e70*/ @P2 STS [R0.X4], R9 ; /* 0x0000000900002388 */
/* 0x0001e80000004800 */
/*0e80*/ @P2 STS [R6], R9 ; /* 0x0000000906002388 */
/* 0x0001e40000000800 */
/*0e90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ea0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0eb0*/ BSSY B0, 0xfa0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0ec0*/ @!P1 BRA 0xf90 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0ed0*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x0010620000004800 */
/*0ee0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f25270 */
/*0ef0*/ LDS R7, [R5] ; /* 0x0000000005077984 */
/* 0x0000b40000000800 */
/*0f00*/ @!P1 BRA 0xf60 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*0f10*/ ISETP.GE.AND P1, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x007fda0003f26270 */
/*0f20*/ @P1 BRA 0xf90 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0f30*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*0f40*/ STS [R5], R7 ; /* 0x0000000705007388 */
/* 0x0001e20000000800 */
/*0f50*/ BRA 0xf90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0f60*/ ISETP.GT.AND P1, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x007fda0003f24270 */
/*0f70*/ @P1 STS [R0.X4], R7 ; /* 0x0000000700001388 */
/* 0x0001e80000004800 */
/*0f80*/ @P1 STS [R5], R7 ; /* 0x0000000705001388 */
/* 0x0001e40000000800 */
/*0f90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0fa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0fb0*/ BSSY B0, 0x10a0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0fc0*/ @!P0 BRA 0x1090 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0fd0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x0010620000004800 */
/*0fe0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc60003f05270 */
/*0ff0*/ LDS R7, [R4] ; /* 0x0000000004077984 */
/* 0x0000b40000000800 */
/*1000*/ @!P0 BRA 0x1060 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*1010*/ ISETP.GE.AND P0, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x007fda0003f06270 */
/*1020*/ @P0 BRA 0x1090 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*1030*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0001e80000004800 */
/*1040*/ STS [R4], R7 ; /* 0x0000000704007388 */
/* 0x0001e20000000800 */
/*1050*/ BRA 0x1090 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1060*/ ISETP.GT.AND P0, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x007fda0003f04270 */
/*1070*/ @P0 STS [R0.X4], R7 ; /* 0x0000000700000388 */
/* 0x0001e80000004800 */
/*1080*/ @P0 STS [R4], R7 ; /* 0x0000000704000388 */
/* 0x0001e40000000800 */
/*1090*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*10a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*10b0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x001e280000004800 */
/*10c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*10d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*10e0*/ BRA 0x10e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13BitonicKernelPi
.globl _Z13BitonicKernelPi
.p2align 8
.type _Z13BitonicKernelPi,@function
_Z13BitonicKernelPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s1, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 16
s_mov_b32 s1, s0
s_cbranch_scc1 .LBB0_11
.LBB0_2:
v_and_b32_e32 v4, s1, v0
s_mov_b32 s2, s1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_1
.LBB0_4:
s_mov_b32 s3, s2
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
v_xor_b32_e32 v4, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 v4, v0
s_cbranch_execz .LBB0_3
v_lshlrev_b32_e32 v4, 2, v4
s_mov_b32 s5, 0
ds_load_b32 v6, v3
ds_load_b32 v5, v4
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s0
s_cbranch_execz .LBB0_7
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e64 s0, v6, v5
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s5, s0, exec_lo
.LBB0_7:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB0_9
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s0, v6, v5
s_and_not1_b32 s5, s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, exec_lo
s_or_b32 s5, s5, s0
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_3
s_waitcnt lgkmcnt(0)
ds_store_b32 v3, v5
ds_store_b32 v4, v5
s_branch .LBB0_3
.LBB0_11:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13BitonicKernelPi
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13BitonicKernelPi, .Lfunc_end0-_Z13BitonicKernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13BitonicKernelPi
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z13BitonicKernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e29f1_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z13BitonicKernelPiPi
.type _Z33__device_stub__Z13BitonicKernelPiPi, @function
_Z33__device_stub__Z13BitonicKernelPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13BitonicKernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z13BitonicKernelPiPi, .-_Z33__device_stub__Z13BitonicKernelPiPi
.globl _Z13BitonicKernelPi
.type _Z13BitonicKernelPi, @function
_Z13BitonicKernelPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13BitonicKernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13BitonicKernelPi, .-_Z13BitonicKernelPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13BitonicKernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13BitonicKernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z28__device_stub__BitonicKernelPi # -- Begin function _Z28__device_stub__BitonicKernelPi
.p2align 4, 0x90
.type _Z28__device_stub__BitonicKernelPi,@function
_Z28__device_stub__BitonicKernelPi: # @_Z28__device_stub__BitonicKernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13BitonicKernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__BitonicKernelPi, .Lfunc_end0-_Z28__device_stub__BitonicKernelPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13BitonicKernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13BitonicKernelPi,@object # @_Z13BitonicKernelPi
.section .rodata,"a",@progbits
.globl _Z13BitonicKernelPi
.p2align 3, 0x0
_Z13BitonicKernelPi:
.quad _Z28__device_stub__BitonicKernelPi
.size _Z13BitonicKernelPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13BitonicKernelPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__BitonicKernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13BitonicKernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* File: matmult-cuda-float.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
*
* Run: ./matmult-cuda-float.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <cuda_runtime.h>
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
float result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
float* h_A; // Matriz A en el equipo.
float* h_B; // Matriz B en el equipo.
float* h_C; // Matriz C (resultado) en el equipo.
float* d_A; // Matriz A en la memoria de la GPU.
float* d_B; // Matriz B en la memoria de la GPU.
float* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(float) * N;
//En la memoria del equipo
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_C = (float*)malloc(size);
//En la memoria de la GPU
cudaMalloc(&d_A, size);
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R5, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R10, R4 ; /* 0x00000004000a7213 */
/* 0x000fe20000000000 */
/*00b0*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*00c0*/ I2F.RP R5, R8 ; /* 0x0000000800057306 */
/* 0x000e220000209400 */
/*00d0*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f26270 */
/*00e0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0120*/ IADD3 R9, RZ, -R7, RZ ; /* 0x80000007ff097210 */
/* 0x002fca0007ffe0ff */
/*0130*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fe200078e0006 */
/*0150*/ MOV R9, R10 ; /* 0x0000000a00097202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.HI.U32 R7, R7, R9, RZ ; /* 0x0000000907077227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R5, R8, R7, R9 ; /* 0x0000000708057224 */
/* 0x000fca00078e0209 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IADD3 R5, R5, -R8, RZ ; /* 0x8000000805058210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IADD3 R5, R5, -R8, RZ ; /* 0x800000080505a210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f46270 */
/*01f0*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff058a12 */
/* 0x000fd200078e33ff */
/*0210*/ @!P2 BRA 0xd50 ; /* 0x00000b300000a947 */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R6, R2.reuse, -0x1, RZ ; /* 0xffffffff02067810 */
/* 0x040fe40007ffe0ff */
/*0230*/ LOP3.LUT R7, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302077812 */
/* 0x000fe400078ec0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0250*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*0260*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0270*/ @!P0 BRA 0xc30 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe20007ffe1ff */
/*0290*/ HFMA2.MMA R26, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1a7435 */
/* 0x000fe200000001ff */
/*02a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*02b0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*02c0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*02d0*/ IADD3 R9, R4, -R5, RZ ; /* 0x8000000504097210 */
/* 0x000fe40007ffe0ff */
/*02e0*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fc60000000f00 */
/*02f0*/ IMAD.WIDE R26, R5, R26, c[0x0][0x168] ; /* 0x00005a00051a7625 */
/* 0x000fcc00078e021a */
/*0300*/ @!P0 BRA 0xaa0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0330*/ @!P1 BRA 0x7e0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0350*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0360*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0000a2000c1e1900 */
/*0370*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0380*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x000fca00078e020c */
/*0390*/ LDG.E R28, [R12.64] ; /* 0x000000040c1c7981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R16, R2, 0x4, R26 ; /* 0x0000000402107825 */
/* 0x000fc600078e021a */
/*03b0*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ee6000c1e1900 */
/*03c0*/ IMAD.WIDE R10, R2.reuse, 0x4, R16 ; /* 0x00000004020a7825 */
/* 0x040fe200078e0210 */
/*03d0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e8000c1e1900 */
/*03e0*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000968000c1e1900 */
/*03f0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD.WIDE R10, R2, 0x4, R10 ; /* 0x00000004020a7825 */
/* 0x010fc600078e020a */
/*0420*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x001f28000c1e1900 */
/*0430*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000122000c1e1900 */
/*0440*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0450*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000122000c1e1900 */
/*0460*/ IMAD.WIDE R16, R2, 0x4, R20 ; /* 0x0000000402107825 */
/* 0x002fc600078e0214 */
/*0470*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x001f28000c1e1900 */
/*0480*/ LDG.E R21, [R12.64+0x1c] ; /* 0x00001c040c157981 */
/* 0x000f22000c1e1900 */
/*0490*/ FFMA R28, R19, R28, R18 ; /* 0x0000001c131c7223 */
/* 0x004fc60000000012 */
/*04a0*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0000a2000c1e1900 */
/*04c0*/ FFMA R28, R22, R23, R28 ; /* 0x00000017161c7223 */
/* 0x008fe4000000001c */
/*04d0*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x001fca00078e0210 */
/*04e0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ae2000c1e1900 */
/*04f0*/ IMAD.WIDE R22, R2, 0x4, R16 ; /* 0x0000000402167825 */
/* 0x000fca00078e0210 */
/*0500*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x0000e2000c1e1900 */
/*0510*/ FFMA R16, R25, R24, R28 ; /* 0x0000001819107223 */
/* 0x020fe4000000001c */
/*0520*/ IMAD.WIDE R24, R2.reuse, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x040fe200078e0216 */
/*0530*/ LDG.E R28, [R12.64+0x20] ; /* 0x000020040c1c7981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000362000c1e1900 */
/*0550*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x010fe40000000010 */
/*0560*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0570*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x001f26000c1e1900 */
/*0580*/ FFMA R26, R27, R26, R16 ; /* 0x0000001a1b1a7223 */
/* 0x000fc40000000010 */
/*0590*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe200078e020e */
/*05a0*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x000f28000c1e1900 */
/*05b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*05c0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000328000c1e1900 */
/*05d0*/ LDG.E R15, [R12.64+0x30] ; /* 0x000030040c0f7981 */
/* 0x001f22000c1e1900 */
/*05e0*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x004fc4000000001a */
/*05f0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc800078e0210 */
/*0600*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x008fe4000000001a */
/*0610*/ IMAD.WIDE R10, R2, 0x4, R18 ; /* 0x00000004020a7825 */
/* 0x000fe400078e0212 */
/*0620*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a4000c1e1900 */
/*0630*/ FFMA R24, R20, R21, R26 ; /* 0x0000001514187223 */
/* 0x002fe4000000001a */
/*0640*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fe200078e020a */
/*0650*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002e2000c1e1900 */
/*0670*/ FFMA R28, R29, R28, R24 ; /* 0x0000001c1d1c7223 */
/* 0x020fc60000000018 */
/*0680*/ LDG.E R19, [R12.64+0x38] ; /* 0x000038040c137981 */
/* 0x001f62000c1e1900 */
/*0690*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc600078e0214 */
/*06a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*06b0*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x002f62000c1e1900 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fc600078e0218 */
/*06d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000368000c1e1900 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x001f68000c1e1900 */
/*06f0*/ LDG.E R24, [R12.64+0x3c] ; /* 0x00003c040c187981 */
/* 0x002f62000c1e1900 */
/*0700*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x010fe2000000001c */
/*0710*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*0720*/ FFMA R27, R22, R27, R14 ; /* 0x0000001b161b7223 */
/* 0x000fe2000000000e */
/*0730*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0740*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0750*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0760*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0770*/ FFMA R18, R18, R26, R27 ; /* 0x0000001a12127223 */
/* 0x004fc8000000001b */
/*0780*/ FFMA R10, R10, R15, R18 ; /* 0x0000000f0a0a7223 */
/* 0x008fe40000000012 */
/*0790*/ IMAD.WIDE R26, R2, 0x4, R16 ; /* 0x00000004021a7825 */
/* 0x000fc800078e0210 */
/*07a0*/ FFMA R10, R20, R11, R10 ; /* 0x0000000b140a7223 */
/* 0x020fc8000000000a */
/*07b0*/ FFMA R10, R29, R19, R10 ; /* 0x000000131d0a7223 */
/* 0x000fc8000000000a */
/*07c0*/ FFMA R18, R21, R24, R10 ; /* 0x0000001815127223 */
/* 0x000fe2000000000a */
/*07d0*/ @P1 BRA 0x350 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*07e0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*07f0*/ @!P1 BRA 0xa80 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0800*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0810*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x000ea2000c1e1900 */
/*0820*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0830*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fca00078e020a */
/*0840*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IMAD.WIDE R22, R2, 0x4, R26 ; /* 0x0000000402167825 */
/* 0x000fc600078e021a */
/*0860*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0870*/ IMAD.WIDE R14, R2.reuse, 0x4, R22 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0216 */
/*0880*/ LDG.E R29, [R10.64+0x8] ; /* 0x000008040a1d7981 */
/* 0x000f28000c1e1900 */
/*0890*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e2000c1e1900 */
/*08a0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*08b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000326000c1e1900 */
/*08c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*08d0*/ LDG.E R28, [R10.64+0xc] ; /* 0x00000c040a1c7981 */
/* 0x000f68000c1e1900 */
/*08e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000362000c1e1900 */
/*08f0*/ IMAD.WIDE R20, R2, 0x4, R12 ; /* 0x0000000402147825 */
/* 0x000fc600078e020c */
/*0900*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000328000c1e1900 */
/*0910*/ LDG.E R23, [R10.64+0x14] ; /* 0x000014040a177981 */
/* 0x001f68000c1e1900 */
/*0920*/ LDG.E R16, [R10.64+0x18] ; /* 0x000018040a107981 */
/* 0x002f68000c1e1900 */
/*0930*/ LDG.E R13, [R10.64+0x10] ; /* 0x000010040a0d7981 */
/* 0x000f62000c1e1900 */
/*0940*/ FFMA R24, R19, R24, R18 ; /* 0x0000001813187223 */
/* 0x004fc40000000012 */
/*0950*/ IMAD.WIDE R18, R2.reuse, 0x4, R20 ; /* 0x0000000402127825 */
/* 0x040fe400078e0214 */
/*0960*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R26, R2, 0x4, R18 ; /* 0x00000004021a7825 */
/* 0x000fe200078e0212 */
/*0980*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0000a8000c1e1900 */
/*0990*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001ea8000c1e1900 */
/*09a0*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x0000a2000c1e1900 */
/*09b0*/ FFMA R22, R22, R25, R24 ; /* 0x0000001916167223 */
/* 0x008fc80000000018 */
/*09c0*/ FFMA R14, R14, R29, R22 ; /* 0x0000001d0e0e7223 */
/* 0x010fc80000000016 */
/*09d0*/ FFMA R14, R17, R28, R14 ; /* 0x0000001c110e7223 */
/* 0x020fc8000000000e */
/*09e0*/ FFMA R12, R12, R13, R14 ; /* 0x0000000d0c0c7223 */
/* 0x000fe2000000000e */
/*09f0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a10*/ IMAD.WIDE R26, R2, 0x4, R26 ; /* 0x00000004021a7825 */
/* 0x001fe200078e021a */
/*0a20*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a50*/ FFMA R12, R20, R23, R12 ; /* 0x00000017140c7223 */
/* 0x004fc8000000000c */
/*0a60*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x000fc8000000000c */
/*0a70*/ FFMA R18, R18, R19, R12 ; /* 0x0000001312127223 */
/* 0x000fe4000000000c */
/*0a80*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a90*/ @!P0 BRA 0xc30 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0ab0*/ IMAD.WIDE R12, R2, 0x4, R26 ; /* 0x00000004020c7825 */
/* 0x000fe200078e021a */
/*0ac0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0ad0*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea8000c1e1900 */
/*0ae0*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fc800078e020a */
/*0af0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0b00*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea8000c1e1900 */
/*0b10*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0b20*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*0b30*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0b40*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0b50*/ LDG.E R21, [R10.64+0x8] ; /* 0x000008040a157981 */
/* 0x000f28000c1e1900 */
/*0b60*/ LDG.E R23, [R10.64+0xc] ; /* 0x00000c040a177981 */
/* 0x000f68000c1e1900 */
/*0b70*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0b80*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0bb0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0bc0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bd0*/ FFMA R19, R27, R19, R18 ; /* 0x000000131b137223 */
/* 0x004fc80000000012 */
/*0be0*/ FFMA R19, R12, R20, R19 ; /* 0x000000140c137223 */
/* 0x008fe40000000013 */
/*0bf0*/ IMAD.WIDE R26, R2, 0x4, R16 ; /* 0x00000004021a7825 */
/* 0x000fc800078e0210 */
/*0c00*/ FFMA R19, R22, R21, R19 ; /* 0x0000001516137223 */
/* 0x010fc80000000013 */
/*0c10*/ FFMA R18, R24, R23, R19 ; /* 0x0000001718127223 */
/* 0x020fe20000000013 */
/*0c20*/ @P0 BRA 0xaa0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0c30*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0c40*/ @!P0 BRA 0xd50 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0c50*/ IADD3 R3, R3, R6, RZ ; /* 0x0000000603037210 */
/* 0x000fe20007ffe0ff */
/*0c60*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fc800000001ff */
/*0c70*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fca00078e0203 */
/*0c80*/ IADD3 R0, -R5, R0, RZ ; /* 0x0000000005007210 */
/* 0x000fe20007ffe1ff */
/*0c90*/ IMAD R5, R6, c[0x0][0x178], R5 ; /* 0x00005e0006057a24 */
/* 0x000fc800078e0205 */
/*0ca0*/ IMAD.WIDE R8, R0, R10, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e020a */
/*0cb0*/ IMAD.WIDE R10, R5, R10, c[0x0][0x168] ; /* 0x00005a00050a7625 */
/* 0x000fca00078e020a */
/*0cc0*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0000a8000c1e1900 */
/*0cd0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0002a2000c1e1900 */
/*0ce0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d00*/ IMAD.WIDE R10, R2, 0x4, R10 ; /* 0x00000004020a7825 */
/* 0x001fe200078e020a */
/*0d10*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x002fc80007f3e0ff */
/*0d20*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*0d30*/ FFMA R18, R3, R0, R18 ; /* 0x0000000003127223 */
/* 0x004fcc0000000012 */
/*0d40*/ @P0 BRA 0xcc0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0d50*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0d60*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0d70*/ STG.E [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x000fe2000c101904 */
/*0d80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d90*/ BRA 0xd90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* File: matmult-cuda-float.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
*
* Run: ./matmult-cuda-float.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <cuda_runtime.h>
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
float result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
float* h_A; // Matriz A en el equipo.
float* h_B; // Matriz B en el equipo.
float* h_C; // Matriz C (resultado) en el equipo.
float* d_A; // Matriz A en la memoria de la GPU.
float* d_B; // Matriz B en la memoria de la GPU.
float* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(float) * N;
//En la memoria del equipo
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_C = (float*)malloc(size);
//En la memoria de la GPU
cudaMalloc(&d_A, size);
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | .file "tmpxft_00032ad3_00000000-6_matmult-cuda-float.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $25000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
movl $25000000, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 16(%rsp)
movl $25000000, %edi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 40(%rsp), %rdi
movl $25000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $25000000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $25000000, %esi
call cudaMalloc@PLT
movl $0, %r15d
movl $11, %r14d
.L12:
movl %r14d, %ebp
movl $0, %ebx
.L13:
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $10000, %rbx
jne .L13
addl $11, %r14d
addl $2500, %r15d
addq $10000, %r13
addq $10000, %r12
cmpl $6250000, %r15d
jne .L12
movl $1, %ecx
movl $25000000, %edx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $25000000, %edx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $6104, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $25000000, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $2500, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 515396076
.long 1072819077
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* File: matmult-cuda-float.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
*
* Run: ./matmult-cuda-float.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <cuda_runtime.h>
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
float result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
float* h_A; // Matriz A en el equipo.
float* h_B; // Matriz B en el equipo.
float* h_C; // Matriz C (resultado) en el equipo.
float* d_A; // Matriz A en la memoria de la GPU.
float* d_B; // Matriz B en la memoria de la GPU.
float* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(float) * N;
//En la memoria del equipo
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_C = (float*)malloc(size);
//En la memoria de la GPU
cudaMalloc(&d_A, size);
cudaMalloc(&d_B, size);
cudaMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | /* File: matmult-cuda-float.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
*
* Run: ./matmult-cuda-float.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
float result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
float* h_A; // Matriz A en el equipo.
float* h_B; // Matriz B en el equipo.
float* h_C; // Matriz C (resultado) en el equipo.
float* d_A; // Matriz A en la memoria de la GPU.
float* d_B; // Matriz B en la memoria de la GPU.
float* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(float) * N;
//En la memoria del equipo
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_C = (float*)malloc(size);
//En la memoria de la GPU
hipMalloc(&d_A, size);
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* File: matmult-cuda-float.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
*
* Run: ./matmult-cuda-float.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
float result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
float* h_A; // Matriz A en el equipo.
float* h_B; // Matriz B en el equipo.
float* h_C; // Matriz C (resultado) en el equipo.
float* d_A; // Matriz A en la memoria de la GPU.
float* d_B; // Matriz B en la memoria de la GPU.
float* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(float) * N;
//En la memoria del equipo
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_C = (float*)malloc(size);
//En la memoria de la GPU
hipMalloc(&d_A, size);
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v0, v3
v_mul_lo_u32 v2, v5, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v2
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v6, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_mov_b32_e32 v3, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[1:2], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v7
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* File: matmult-cuda-float.cu
*
* Purpose:
*
* Input:
*
* Output:
*
* Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
*
* Run: ./matmult-cuda-float.o
*
* Algorithm:
*
* Note:
*
* */
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector
int ix; //ix indica el renglon
int iy; //iy toma valores solo entre 0 a N-1
float result; //Acumula la suma del renglon por la columna
int k; // Iterador
if(index < N * N)
{
ix = index / N;
iy = index % N;
result = 0.0;
for(k = 0; k < N; k++)
result += A[k + N * ix] * B[k * N + iy ];
C[iy + N * ix] = result;
}
}
// Host code
int main()
{
//Variables
int N; // Tamaño de la matriz cuadrada.
int i; // Indice del renglon.
int j; // Indice de la columna.
size_t size; // Tamaño total en memoria.
float* h_A; // Matriz A en el equipo.
float* h_B; // Matriz B en el equipo.
float* h_C; // Matriz C (resultado) en el equipo.
float* d_A; // Matriz A en la memoria de la GPU.
float* d_B; // Matriz B en la memoria de la GPU.
float* d_C; // Matriz C (resultado) en la memoria de la GPU.
int Tam; // Numero de datos que se manejan
int NumHilos; // Hilos por bloque
int numBlock; // Numero de bloques necesario para procesar los datos
//Asignacion de variables
N = 2500;
size = N * sizeof(float) * N;
//En la memoria del equipo
h_A = (float*)malloc(size);
h_B = (float*)malloc(size);
h_C = (float*)malloc(size);
//En la memoria de la GPU
hipMalloc(&d_A, size);
hipMalloc(&d_B, size);
hipMalloc(&d_C, size);
//
Tam = N * N;
NumHilos = 1024;
numBlock = Tam / NumHilos;
if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
numBlock++;
// LLena los arreglos A y B
for(i = 0;i < N;i++) //Renglon
for(j = 0;j < N;j++) // Columna
{
h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
}
//Copia los arreglos de memoria del CPU a memoria de la GPU
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
// Invoke kernel
VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);
//Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
/*
//Imprime la matriz A
printf("Matriz A\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_A[j + i * N]);
printf("\n");
}
//Imprime la matriz B
printf("Matriz B\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_B[j + i * N]);
printf("\n");
}
//Imprime la matriz C
printf("Matriz C\n");
for(i = 0;i < N;i++)
{
for(j = 0;j < N;j++)
printf("%.2f ", h_C[j + i * N]);
printf("\n");
}*/
//Libera la memoria utilizada.
// Free device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Free host memory
free(h_A);
free(h_B);
free(h_C);
} | .text
.file "matmult-cuda-float.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff1eb851eb851ec # double 1.1200000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $25000000, %edi # imm = 0x17D7840
callq malloc
movq %rax, %r13
movl $25000000, %edi # imm = 0x17D7840
callq malloc
movq %rax, %rbp
movl $25000000, %edi # imm = 0x17D7840
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
movl $25000000, %esi # imm = 0x17D7840
callq hipMalloc
leaq 16(%rsp), %rdi
movl $25000000, %esi # imm = 0x17D7840
callq hipMalloc
leaq 8(%rsp), %rdi
movl $25000000, %esi # imm = 0x17D7840
callq hipMalloc
xorl %r12d, %r12d
movq %r13, %r14
movq %rbp, 48(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leal (%r12,%r12,4), %eax
leal (%r12,%rax,2), %r15d
addl $11, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbx,4)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $2500, %rbx # imm = 0x9C4
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $10000, %rbp # imm = 0x2710
addq $10000, %r13 # imm = 0x2710
cmpq $2500, %r12 # imm = 0x9C4
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $25000000, %edx # imm = 0x17D7840
movq %r14, %rbx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $25000000, %edx # imm = 0x17D7840
movq 48(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 5080(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2500, 36(%rsp) # imm = 0x9C4
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $25000000, %edx # imm = 0x17D7840
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R5, R2, c[0x0][0x178], RZ ; /* 0x00005e0002057a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R10, R4 ; /* 0x00000004000a7213 */
/* 0x000fe20000000000 */
/*00b0*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*00c0*/ I2F.RP R5, R8 ; /* 0x0000000800057306 */
/* 0x000e220000209400 */
/*00d0*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f26270 */
/*00e0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x001fe200000001ff */
/*0120*/ IADD3 R9, RZ, -R7, RZ ; /* 0x80000007ff097210 */
/* 0x002fca0007ffe0ff */
/*0130*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R7, R7, R9, R6 ; /* 0x0000000907077227 */
/* 0x000fe200078e0006 */
/*0150*/ MOV R9, R10 ; /* 0x0000000a00097202 */
/* 0x000fca0000000f00 */
/*0160*/ IMAD.HI.U32 R7, R7, R9, RZ ; /* 0x0000000907077227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R5, R8, R7, R9 ; /* 0x0000000708057224 */
/* 0x000fca00078e0209 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IADD3 R5, R5, -R8, RZ ; /* 0x8000000805058210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IADD3 R5, R5, -R8, RZ ; /* 0x800000080505a210 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f46270 */
/*01f0*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff058a12 */
/* 0x000fd200078e33ff */
/*0210*/ @!P2 BRA 0xd50 ; /* 0x00000b300000a947 */
/* 0x000fea0003800000 */
/*0220*/ IADD3 R6, R2.reuse, -0x1, RZ ; /* 0xffffffff02067810 */
/* 0x040fe40007ffe0ff */
/*0230*/ LOP3.LUT R7, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302077812 */
/* 0x000fe400078ec0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0250*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*0260*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0270*/ @!P0 BRA 0xc30 ; /* 0x000009b000008947 */
/* 0x000fea0003800000 */
/*0280*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe20007ffe1ff */
/*0290*/ HFMA2.MMA R26, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1a7435 */
/* 0x000fe200000001ff */
/*02a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*02b0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*02c0*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*02d0*/ IADD3 R9, R4, -R5, RZ ; /* 0x8000000504097210 */
/* 0x000fe40007ffe0ff */
/*02e0*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fc60000000f00 */
/*02f0*/ IMAD.WIDE R26, R5, R26, c[0x0][0x168] ; /* 0x00005a00051a7625 */
/* 0x000fcc00078e021a */
/*0300*/ @!P0 BRA 0xaa0 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*0320*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0330*/ @!P1 BRA 0x7e0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0340*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0350*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0360*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0000a2000c1e1900 */
/*0370*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0380*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x000fca00078e020c */
/*0390*/ LDG.E R28, [R12.64] ; /* 0x000000040c1c7981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R16, R2, 0x4, R26 ; /* 0x0000000402107825 */
/* 0x000fc600078e021a */
/*03b0*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ee6000c1e1900 */
/*03c0*/ IMAD.WIDE R10, R2.reuse, 0x4, R16 ; /* 0x00000004020a7825 */
/* 0x040fe200078e0210 */
/*03d0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e8000c1e1900 */
/*03e0*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000968000c1e1900 */
/*03f0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD.WIDE R10, R2, 0x4, R10 ; /* 0x00000004020a7825 */
/* 0x010fc600078e020a */
/*0420*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x001f28000c1e1900 */
/*0430*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000122000c1e1900 */
/*0440*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0450*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000122000c1e1900 */
/*0460*/ IMAD.WIDE R16, R2, 0x4, R20 ; /* 0x0000000402107825 */
/* 0x002fc600078e0214 */
/*0470*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x001f28000c1e1900 */
/*0480*/ LDG.E R21, [R12.64+0x1c] ; /* 0x00001c040c157981 */
/* 0x000f22000c1e1900 */
/*0490*/ FFMA R28, R19, R28, R18 ; /* 0x0000001c131c7223 */
/* 0x004fc60000000012 */
/*04a0*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0000a2000c1e1900 */
/*04c0*/ FFMA R28, R22, R23, R28 ; /* 0x00000017161c7223 */
/* 0x008fe4000000001c */
/*04d0*/ IMAD.WIDE R16, R2, 0x4, R16 ; /* 0x0000000402107825 */
/* 0x001fca00078e0210 */
/*04e0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ae2000c1e1900 */
/*04f0*/ IMAD.WIDE R22, R2, 0x4, R16 ; /* 0x0000000402167825 */
/* 0x000fca00078e0210 */
/*0500*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x0000e2000c1e1900 */
/*0510*/ FFMA R16, R25, R24, R28 ; /* 0x0000001819107223 */
/* 0x020fe4000000001c */
/*0520*/ IMAD.WIDE R24, R2.reuse, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x040fe200078e0216 */
/*0530*/ LDG.E R28, [R12.64+0x20] ; /* 0x000020040c1c7981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000362000c1e1900 */
/*0550*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x010fe40000000010 */
/*0560*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0570*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x001f26000c1e1900 */
/*0580*/ FFMA R26, R27, R26, R16 ; /* 0x0000001a1b1a7223 */
/* 0x000fc40000000010 */
/*0590*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe200078e020e */
/*05a0*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x000f28000c1e1900 */
/*05b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*05c0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000328000c1e1900 */
/*05d0*/ LDG.E R15, [R12.64+0x30] ; /* 0x000030040c0f7981 */
/* 0x001f22000c1e1900 */
/*05e0*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x004fc4000000001a */
/*05f0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc800078e0210 */
/*0600*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x008fe4000000001a */
/*0610*/ IMAD.WIDE R10, R2, 0x4, R18 ; /* 0x00000004020a7825 */
/* 0x000fe400078e0212 */
/*0620*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a4000c1e1900 */
/*0630*/ FFMA R24, R20, R21, R26 ; /* 0x0000001514187223 */
/* 0x002fe4000000001a */
/*0640*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fe200078e020a */
/*0650*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002e2000c1e1900 */
/*0670*/ FFMA R28, R29, R28, R24 ; /* 0x0000001c1d1c7223 */
/* 0x020fc60000000018 */
/*0680*/ LDG.E R19, [R12.64+0x38] ; /* 0x000038040c137981 */
/* 0x001f62000c1e1900 */
/*0690*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc600078e0214 */
/*06a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*06b0*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x002f62000c1e1900 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fc600078e0218 */
/*06d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000368000c1e1900 */
/*06e0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x001f68000c1e1900 */
/*06f0*/ LDG.E R24, [R12.64+0x3c] ; /* 0x00003c040c187981 */
/* 0x002f62000c1e1900 */
/*0700*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x010fe2000000001c */
/*0710*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*0720*/ FFMA R27, R22, R27, R14 ; /* 0x0000001b161b7223 */
/* 0x000fe2000000000e */
/*0730*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0740*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0750*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0760*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0770*/ FFMA R18, R18, R26, R27 ; /* 0x0000001a12127223 */
/* 0x004fc8000000001b */
/*0780*/ FFMA R10, R10, R15, R18 ; /* 0x0000000f0a0a7223 */
/* 0x008fe40000000012 */
/*0790*/ IMAD.WIDE R26, R2, 0x4, R16 ; /* 0x00000004021a7825 */
/* 0x000fc800078e0210 */
/*07a0*/ FFMA R10, R20, R11, R10 ; /* 0x0000000b140a7223 */
/* 0x020fc8000000000a */
/*07b0*/ FFMA R10, R29, R19, R10 ; /* 0x000000131d0a7223 */
/* 0x000fc8000000000a */
/*07c0*/ FFMA R18, R21, R24, R10 ; /* 0x0000001815127223 */
/* 0x000fe2000000000a */
/*07d0*/ @P1 BRA 0x350 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*07e0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*07f0*/ @!P1 BRA 0xa80 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0800*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0810*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x000ea2000c1e1900 */
/*0820*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0830*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fca00078e020a */
/*0840*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IMAD.WIDE R22, R2, 0x4, R26 ; /* 0x0000000402167825 */
/* 0x000fc600078e021a */
/*0860*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0870*/ IMAD.WIDE R14, R2.reuse, 0x4, R22 ; /* 0x00000004020e7825 */
/* 0x040fe200078e0216 */
/*0880*/ LDG.E R29, [R10.64+0x8] ; /* 0x000008040a1d7981 */
/* 0x000f28000c1e1900 */
/*0890*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e2000c1e1900 */
/*08a0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*08b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000326000c1e1900 */
/*08c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*08d0*/ LDG.E R28, [R10.64+0xc] ; /* 0x00000c040a1c7981 */
/* 0x000f68000c1e1900 */
/*08e0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000362000c1e1900 */
/*08f0*/ IMAD.WIDE R20, R2, 0x4, R12 ; /* 0x0000000402147825 */
/* 0x000fc600078e020c */
/*0900*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000328000c1e1900 */
/*0910*/ LDG.E R23, [R10.64+0x14] ; /* 0x000014040a177981 */
/* 0x001f68000c1e1900 */
/*0920*/ LDG.E R16, [R10.64+0x18] ; /* 0x000018040a107981 */
/* 0x002f68000c1e1900 */
/*0930*/ LDG.E R13, [R10.64+0x10] ; /* 0x000010040a0d7981 */
/* 0x000f62000c1e1900 */
/*0940*/ FFMA R24, R19, R24, R18 ; /* 0x0000001813187223 */
/* 0x004fc40000000012 */
/*0950*/ IMAD.WIDE R18, R2.reuse, 0x4, R20 ; /* 0x0000000402127825 */
/* 0x040fe400078e0214 */
/*0960*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*0970*/ IMAD.WIDE R26, R2, 0x4, R18 ; /* 0x00000004021a7825 */
/* 0x000fe200078e0212 */
/*0980*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0000a8000c1e1900 */
/*0990*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001ea8000c1e1900 */
/*09a0*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x0000a2000c1e1900 */
/*09b0*/ FFMA R22, R22, R25, R24 ; /* 0x0000001916167223 */
/* 0x008fc80000000018 */
/*09c0*/ FFMA R14, R14, R29, R22 ; /* 0x0000001d0e0e7223 */
/* 0x010fc80000000016 */
/*09d0*/ FFMA R14, R17, R28, R14 ; /* 0x0000001c110e7223 */
/* 0x020fc8000000000e */
/*09e0*/ FFMA R12, R12, R13, R14 ; /* 0x0000000d0c0c7223 */
/* 0x000fe2000000000e */
/*09f0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a10*/ IMAD.WIDE R26, R2, 0x4, R26 ; /* 0x00000004021a7825 */
/* 0x001fe200078e021a */
/*0a20*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*0a30*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a50*/ FFMA R12, R20, R23, R12 ; /* 0x00000017140c7223 */
/* 0x004fc8000000000c */
/*0a60*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x000fc8000000000c */
/*0a70*/ FFMA R18, R18, R19, R12 ; /* 0x0000001312127223 */
/* 0x000fe4000000000c */
/*0a80*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a90*/ @!P0 BRA 0xc30 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0ab0*/ IMAD.WIDE R12, R2, 0x4, R26 ; /* 0x00000004020c7825 */
/* 0x000fe200078e021a */
/*0ac0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0ad0*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea8000c1e1900 */
/*0ae0*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fc800078e020a */
/*0af0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0b00*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea8000c1e1900 */
/*0b10*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0b20*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*0b30*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0b40*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0b50*/ LDG.E R21, [R10.64+0x8] ; /* 0x000008040a157981 */
/* 0x000f28000c1e1900 */
/*0b60*/ LDG.E R23, [R10.64+0xc] ; /* 0x00000c040a177981 */
/* 0x000f68000c1e1900 */
/*0b70*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0b80*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0bb0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0bc0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bd0*/ FFMA R19, R27, R19, R18 ; /* 0x000000131b137223 */
/* 0x004fc80000000012 */
/*0be0*/ FFMA R19, R12, R20, R19 ; /* 0x000000140c137223 */
/* 0x008fe40000000013 */
/*0bf0*/ IMAD.WIDE R26, R2, 0x4, R16 ; /* 0x00000004021a7825 */
/* 0x000fc800078e0210 */
/*0c00*/ FFMA R19, R22, R21, R19 ; /* 0x0000001516137223 */
/* 0x010fc80000000013 */
/*0c10*/ FFMA R18, R24, R23, R19 ; /* 0x0000001718127223 */
/* 0x020fe20000000013 */
/*0c20*/ @P0 BRA 0xaa0 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0c30*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0c40*/ @!P0 BRA 0xd50 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0c50*/ IADD3 R3, R3, R6, RZ ; /* 0x0000000603037210 */
/* 0x000fe20007ffe0ff */
/*0c60*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fc800000001ff */
/*0c70*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fca00078e0203 */
/*0c80*/ IADD3 R0, -R5, R0, RZ ; /* 0x0000000005007210 */
/* 0x000fe20007ffe1ff */
/*0c90*/ IMAD R5, R6, c[0x0][0x178], R5 ; /* 0x00005e0006057a24 */
/* 0x000fc800078e0205 */
/*0ca0*/ IMAD.WIDE R8, R0, R10, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e020a */
/*0cb0*/ IMAD.WIDE R10, R5, R10, c[0x0][0x168] ; /* 0x00005a00050a7625 */
/* 0x000fca00078e020a */
/*0cc0*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0000a8000c1e1900 */
/*0cd0*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0002a2000c1e1900 */
/*0ce0*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0d00*/ IMAD.WIDE R10, R2, 0x4, R10 ; /* 0x00000004020a7825 */
/* 0x001fe200078e020a */
/*0d10*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x002fc80007f3e0ff */
/*0d20*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*0d30*/ FFMA R18, R3, R0, R18 ; /* 0x0000000003127223 */
/* 0x004fcc0000000012 */
/*0d40*/ @P0 BRA 0xcc0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0d50*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*0d60*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0205 */
/*0d70*/ STG.E [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x000fe2000c101904 */
/*0d80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d90*/ BRA 0xd90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_i
.globl _Z6VecAddPfS_S_i
.p2align 8
.type _Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s4, s4, s3
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
s_cmp_lt_i32 s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v0, v3
v_mul_lo_u32 v2, v5, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v2
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v6, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[2:3]
v_mov_b32_e32 v3, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s3, s3, -1
s_cmp_lg_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_nc_u32_e32 v3, s2, v3
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v4, v[1:2], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v4, v7
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00032ad3_00000000-6_matmult-cuda-float.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.globl _Z6VecAddPfS_S_i
.type _Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $25000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 8(%rsp)
movl $25000000, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, 16(%rsp)
movl $25000000, %edi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 40(%rsp), %rdi
movl $25000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $25000000, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $25000000, %esi
call cudaMalloc@PLT
movl $0, %r15d
movl $11, %r14d
.L12:
movl %r14d, %ebp
movl $0, %ebx
.L13:
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rbx)
call rand@PLT
cltd
idivl %ebp
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
mulsd .LC0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $10000, %rbx
jne .L13
addl $11, %r14d
addl $2500, %r15d
addq $10000, %r13
addq $10000, %r12
cmpl $6250000, %r15d
jne .L12
movl $1, %ecx
movl $25000000, %edx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $25000000, %edx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $6104, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $2, %ecx
movl $25000000, %edx
movq 56(%rsp), %rsi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $2500, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z6VecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 515396076
.long 1072819077
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmult-cuda-float.hip"
.globl _Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i: # @_Z21__device_stub__VecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3ff1eb851eb851ec # double 1.1200000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $25000000, %edi # imm = 0x17D7840
callq malloc
movq %rax, %r13
movl $25000000, %edi # imm = 0x17D7840
callq malloc
movq %rax, %rbp
movl $25000000, %edi # imm = 0x17D7840
callq malloc
movq %rax, 40(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
movl $25000000, %esi # imm = 0x17D7840
callq hipMalloc
leaq 16(%rsp), %rdi
movl $25000000, %esi # imm = 0x17D7840
callq hipMalloc
leaq 8(%rsp), %rdi
movl $25000000, %esi # imm = 0x17D7840
callq hipMalloc
xorl %r12d, %r12d
movq %r13, %r14
movq %rbp, 48(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leal (%r12,%r12,4), %eax
leal (%r12,%rax,2), %r15d
addl $11, %r15d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r13,%rbx,4)
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
cltd
idivl %r15d
xorps %xmm0, %xmm0
cvtsi2sd %edx, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $2500, %rbx # imm = 0x9C4
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $10000, %rbp # imm = 0x2710
addq $10000, %r13 # imm = 0x2710
cmpq $2500, %r12 # imm = 0x9C4
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $25000000, %edx # imm = 0x17D7840
movq %r14, %rbx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $25000000, %edx # imm = 0x17D7840
movq 48(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 5080(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $2500, 36(%rsp) # imm = 0x9C4
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6VecAddPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $25000000, %edx # imm = 0x17D7840
movq 40(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_i,@object # @_Z6VecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_i
.p2align 3, 0x0
_Z6VecAddPfS_S_i:
.quad _Z21__device_stub__VecAddPfS_S_i
.size _Z6VecAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void BNAvg(const float lr, float *w, const float *dzdw,
const float ts, const float len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= len) return;
w[index] = (1-lr)*w[index]+lr*dzdw[index]/ts;
} | code for sm_80
Function : _Z5BNAvgfPfPKfff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0040*/ I2F R0, R2 ; /* 0x0000000200007306 */
/* 0x000e240000201400 */
/*0050*/ FSETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0b */
/* 0x001fda0003f06000 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fcc00078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0000a2000c1e1900 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000362000c1e1900 */
/*00d0*/ MUFU.RCP R7, c[0x0][0x178] ; /* 0x00005e0000077b08 */
/* 0x000ee20000001000 */
/*00e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x1e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff097624 */
/* 0x000fc800078e00ff */
/*0110*/ FADD R5, -R9, 1 ; /* 0x3f80000009057421 */
/* 0x001fe40000000100 */
/*0120*/ FFMA R8, R7, -R8, 1 ; /* 0x3f80000007087423 */
/* 0x008fc80000000808 */
/*0130*/ FFMA R7, R7, R8, R7 ; /* 0x0000000807077223 */
/* 0x000fe40000000007 */
/*0140*/ FMUL R6, R4, c[0x0][0x160] ; /* 0x0000580004067a20 */
/* 0x004fc80000400000 */
/*0150*/ FCHK P0, R6, c[0x0][0x178] ; /* 0x00005e0006007b02 */
/* 0x000e220000000000 */
/*0160*/ FFMA R8, R6, R7, RZ ; /* 0x0000000706087223 */
/* 0x000fc800000000ff */
/*0170*/ FFMA R4, R8, -c[0x0][0x178], R6 ; /* 0x80005e0008047a23 */
/* 0x000fc80000000006 */
/*0180*/ FFMA R4, R7, R4, R8 ; /* 0x0000000407047223 */
/* 0x000fe20000000008 */
/*0190*/ @!P0 BRA 0x1d0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*01a0*/ MOV R4, 0x1c0 ; /* 0x000001c000047802 */
/* 0x002fe40000000f00 */
/*01b0*/ CALL.REL.NOINC 0x210 ; /* 0x0000005000007944 */
/* 0x020fea0003c00000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*01e0*/ FFMA R5, R0, R5, R4 ; /* 0x0000000500057223 */
/* 0x020fca0000000004 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0e7624 */
/* 0x000fe200078e00ff */
/*0220*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011606 */
/*0230*/ BSSY B1, 0x880 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0250*/ SHF.R.U32.HI R8, RZ, 0x17, R14 ; /* 0x00000017ff087819 */
/* 0x000fe2000001160e */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0b7624 */
/* 0x000fc600078e00ff */
/*0270*/ LOP3.LUT R9, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08097812 */
/* 0x000fe400078ec0ff */
/*0280*/ LOP3.LUT R8, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07087812 */
/* 0x000fe400078ec0ff */
/*0290*/ IADD3 R13, R9, -0x1, RZ ; /* 0xffffffff090d7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R12, R8, -0x1, RZ ; /* 0xffffffff080c7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe40003f3c200 */
/*0300*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f1c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x860 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, R10, 0xc8, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c80a */
/*0340*/ @!P0 BRA 0x840 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x840 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x820 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R10, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f800000060a8823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R11, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0b9823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R6, R9, 0xc0800000, 0x17 ; /* 0xc080000009067811 */
/* 0x000fe200078eb8ff */
/*0470*/ BSSY B2, 0x7e0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0480*/ IADD3 R8, R8, -0x7f, RZ ; /* 0xffffff8108087810 */
/* 0x000fc60007ffe0ff */
/*0490*/ IMAD.IADD R11, R11, 0x1, -R6 ; /* 0x000000010b0b7824 */
/* 0x000fe400078e0a06 */
/*04a0*/ IMAD R10, R8, -0x800000, R10 ; /* 0xff800000080a7824 */
/* 0x000fe400078e020a */
/*04b0*/ MUFU.RCP R6, R11 ; /* 0x0000000b00067308 */
/* 0x000e220000001000 */
/*04c0*/ FADD.FTZ R13, -R11, -RZ ; /* 0x800000ff0b0d7221 */
/* 0x000fc80000010100 */
/*04d0*/ FFMA R15, R6, R13, 1 ; /* 0x3f800000060f7423 */
/* 0x001fc8000000000d */
/*04e0*/ FFMA R17, R6, R15, R6 ; /* 0x0000000f06117223 */
/* 0x000fc80000000006 */
/*04f0*/ FFMA R6, R10, R17, RZ ; /* 0x000000110a067223 */
/* 0x000fc800000000ff */
/*0500*/ FFMA R15, R13, R6, R10 ; /* 0x000000060d0f7223 */
/* 0x000fc8000000000a */
/*0510*/ FFMA R12, R17, R15, R6 ; /* 0x0000000f110c7223 */
/* 0x000fc80000000006 */
/*0520*/ FFMA R13, R13, R12, R10 ; /* 0x0000000c0d0d7223 */
/* 0x000fe2000000000a */
/*0530*/ IADD3 R10, R8, 0x7f, -R9 ; /* 0x0000007f080a7810 */
/* 0x000fc60007ffe809 */
/*0540*/ FFMA R6, R17, R13, R12 ; /* 0x0000000d11067223 */
/* 0x000fe4000000000c */
/*0550*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fc600078e0207 */
/*0560*/ SHF.R.U32.HI R8, RZ, 0x17, R6 ; /* 0x00000017ff087819 */
/* 0x000fc80000011606 */
/*0570*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fca00078ec0ff */
/*0580*/ IMAD.IADD R11, R8, 0x1, R7 ; /* 0x00000001080b7824 */
/* 0x000fca00078e0207 */
/*0590*/ IADD3 R8, R11, -0x1, RZ ; /* 0xffffffff0b087810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f06070 */
/*05b0*/ @!P0 BRA 0x7c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*05d0*/ @P0 BRA 0x790 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*05f0*/ @P0 BRA 0x7d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0610*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x7d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0630*/ FFMA.RZ R7, R17, R13.reuse, R12.reuse ; /* 0x0000000d11077223 */
/* 0x180fe2000000c00c */
/*0640*/ IADD3 R10, R11, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x000fe20007ffe0ff */
/*0650*/ FFMA.RM R8, R17, R13.reuse, R12.reuse ; /* 0x0000000d11087223 */
/* 0x180fe2000000400c */
/*0660*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0670*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0680*/ FFMA.RP R7, R17, R13, R12 ; /* 0x0000000d11077223 */
/* 0x000fe2000000800c */
/*0690*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*06a0*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*06b0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*06d0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*06e0*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0700*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0710*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0720*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0730*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0740*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0750*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0760*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fca00078e0207 */
/*0770*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*07a0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R6, R7, 0x800000, R6 ; /* 0x0080000007067824 */
/* 0x000fe400078e0206 */
/*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R6, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b067812 */
/* 0x000fc800078e480a */
/*0800*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R6, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b067812 */
/* 0x000fe200078e480a */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R6, R6, c[0x0][0x178] ; /* 0x00005e0006067621 */
/* 0x000fe40000010000 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*0890*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*08a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*08b0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff74006007950 */
/* 0x000fea0003c3ffff */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void BNAvg(const float lr, float *w, const float *dzdw,
const float ts, const float len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= len) return;
w[index] = (1-lr)*w[index]+lr*dzdw[index]/ts;
} | .file "tmpxft_0014f3f5_00000000-6_BNAvg.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff
.type _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff, @function
_Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5BNAvgfPfPKfff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff, .-_Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff
.globl _Z5BNAvgfPfPKfff
.type _Z5BNAvgfPfPKfff, @function
_Z5BNAvgfPfPKfff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5BNAvgfPfPKfff, .-_Z5BNAvgfPfPKfff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5BNAvgfPfPKfff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5BNAvgfPfPKfff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void BNAvg(const float lr, float *w, const float *dzdw,
const float ts, const float len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= len) return;
w[index] = (1-lr)*w[index]+lr*dzdw[index]/ts;
} | #include <hip/hip_runtime.h>
__global__ void BNAvg(const float lr, float *w, const float *dzdw,
const float ts, const float len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= len) return;
w[index] = (1-lr)*w[index]+lr*dzdw[index]/ts;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void BNAvg(const float lr, float *w, const float *dzdw,
const float ts, const float len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= len) return;
w[index] = (1-lr)*w[index]+lr*dzdw[index]/ts;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5BNAvgfPfPKfff
.globl _Z5BNAvgfPfPKfff
.p2align 8
.type _Z5BNAvgfPfPKfff,@function
_Z5BNAvgfPfPKfff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cvt_f32_i32_e32 v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nle_f32_e32 s3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, s2, s2, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, s2, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
v_sub_f32_e64 v5, 1.0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, s2, v2
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v5, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5BNAvgfPfPKfff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5BNAvgfPfPKfff, .Lfunc_end0-_Z5BNAvgfPfPKfff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5BNAvgfPfPKfff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5BNAvgfPfPKfff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void BNAvg(const float lr, float *w, const float *dzdw,
const float ts, const float len) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= len) return;
w[index] = (1-lr)*w[index]+lr*dzdw[index]/ts;
} | .text
.file "BNAvg.hip"
.globl _Z20__device_stub__BNAvgfPfPKfff # -- Begin function _Z20__device_stub__BNAvgfPfPKfff
.p2align 4, 0x90
.type _Z20__device_stub__BNAvgfPfPKfff,@function
_Z20__device_stub__BNAvgfPfPKfff: # @_Z20__device_stub__BNAvgfPfPKfff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5BNAvgfPfPKfff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__BNAvgfPfPKfff, .Lfunc_end0-_Z20__device_stub__BNAvgfPfPKfff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5BNAvgfPfPKfff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5BNAvgfPfPKfff,@object # @_Z5BNAvgfPfPKfff
.section .rodata,"a",@progbits
.globl _Z5BNAvgfPfPKfff
.p2align 3, 0x0
_Z5BNAvgfPfPKfff:
.quad _Z20__device_stub__BNAvgfPfPKfff
.size _Z5BNAvgfPfPKfff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5BNAvgfPfPKfff"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__BNAvgfPfPKfff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5BNAvgfPfPKfff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5BNAvgfPfPKfff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0040*/ I2F R0, R2 ; /* 0x0000000200007306 */
/* 0x000e240000201400 */
/*0050*/ FSETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0b */
/* 0x001fda0003f06000 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R4, R2, R3, c[0x0][0x170] ; /* 0x00005c0002047625 */
/* 0x000fcc00078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0000a2000c1e1900 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000362000c1e1900 */
/*00d0*/ MUFU.RCP R7, c[0x0][0x178] ; /* 0x00005e0000077b08 */
/* 0x000ee20000001000 */
/*00e0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x1e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff097624 */
/* 0x000fc800078e00ff */
/*0110*/ FADD R5, -R9, 1 ; /* 0x3f80000009057421 */
/* 0x001fe40000000100 */
/*0120*/ FFMA R8, R7, -R8, 1 ; /* 0x3f80000007087423 */
/* 0x008fc80000000808 */
/*0130*/ FFMA R7, R7, R8, R7 ; /* 0x0000000807077223 */
/* 0x000fe40000000007 */
/*0140*/ FMUL R6, R4, c[0x0][0x160] ; /* 0x0000580004067a20 */
/* 0x004fc80000400000 */
/*0150*/ FCHK P0, R6, c[0x0][0x178] ; /* 0x00005e0006007b02 */
/* 0x000e220000000000 */
/*0160*/ FFMA R8, R6, R7, RZ ; /* 0x0000000706087223 */
/* 0x000fc800000000ff */
/*0170*/ FFMA R4, R8, -c[0x0][0x178], R6 ; /* 0x80005e0008047a23 */
/* 0x000fc80000000006 */
/*0180*/ FFMA R4, R7, R4, R8 ; /* 0x0000000407047223 */
/* 0x000fe20000000008 */
/*0190*/ @!P0 BRA 0x1d0 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*01a0*/ MOV R4, 0x1c0 ; /* 0x000001c000047802 */
/* 0x002fe40000000f00 */
/*01b0*/ CALL.REL.NOINC 0x210 ; /* 0x0000005000007944 */
/* 0x020fea0003c00000 */
/*01c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0008 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*01e0*/ FFMA R5, R0, R5, R4 ; /* 0x0000000500057223 */
/* 0x020fca0000000004 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0e7624 */
/* 0x000fe200078e00ff */
/*0220*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011606 */
/*0230*/ BSSY B1, 0x880 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0006 */
/*0250*/ SHF.R.U32.HI R8, RZ, 0x17, R14 ; /* 0x00000017ff087819 */
/* 0x000fe2000001160e */
/*0260*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0b7624 */
/* 0x000fc600078e00ff */
/*0270*/ LOP3.LUT R9, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08097812 */
/* 0x000fe400078ec0ff */
/*0280*/ LOP3.LUT R8, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07087812 */
/* 0x000fe400078ec0ff */
/*0290*/ IADD3 R13, R9, -0x1, RZ ; /* 0xffffffff090d7810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R12, R8, -0x1, RZ ; /* 0xffffffff080c7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*02c0*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*02d0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P0 BRA 0x460 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.GTU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe40003f3c200 */
/*0300*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f1c200 */
/*0310*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0320*/ @P0 BRA 0x860 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0330*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, R10, 0xc8, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c80a */
/*0340*/ @!P0 BRA 0x840 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0350*/ FSETP.NEU.FTZ.AND P2, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f5d200 */
/*0360*/ FSETP.NEU.FTZ.AND P1, PT, |R14|, +INF , PT ; /* 0x7f8000000e00780b */
/* 0x000fe40003f3d200 */
/*0370*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0380*/ @!P1 BRA !P2, 0x840 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0390*/ LOP3.LUT P2, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fc8000784c0ff */
/*03a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03b0*/ @P1 BRA 0x820 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03c0*/ LOP3.LUT P1, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fc8000782c0ff */
/*03d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03e0*/ @P0 BRA 0x7f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0400*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0410*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0420*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0430*/ @!P0 FFMA R10, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f800000060a8823 */
/* 0x000fe400000000ff */
/*0440*/ @!P1 FFMA R11, R14, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000e0b9823 */
/* 0x000fe200000000ff */
/*0450*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0460*/ LEA R6, R9, 0xc0800000, 0x17 ; /* 0xc080000009067811 */
/* 0x000fe200078eb8ff */
/*0470*/ BSSY B2, 0x7e0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0480*/ IADD3 R8, R8, -0x7f, RZ ; /* 0xffffff8108087810 */
/* 0x000fc60007ffe0ff */
/*0490*/ IMAD.IADD R11, R11, 0x1, -R6 ; /* 0x000000010b0b7824 */
/* 0x000fe400078e0a06 */
/*04a0*/ IMAD R10, R8, -0x800000, R10 ; /* 0xff800000080a7824 */
/* 0x000fe400078e020a */
/*04b0*/ MUFU.RCP R6, R11 ; /* 0x0000000b00067308 */
/* 0x000e220000001000 */
/*04c0*/ FADD.FTZ R13, -R11, -RZ ; /* 0x800000ff0b0d7221 */
/* 0x000fc80000010100 */
/*04d0*/ FFMA R15, R6, R13, 1 ; /* 0x3f800000060f7423 */
/* 0x001fc8000000000d */
/*04e0*/ FFMA R17, R6, R15, R6 ; /* 0x0000000f06117223 */
/* 0x000fc80000000006 */
/*04f0*/ FFMA R6, R10, R17, RZ ; /* 0x000000110a067223 */
/* 0x000fc800000000ff */
/*0500*/ FFMA R15, R13, R6, R10 ; /* 0x000000060d0f7223 */
/* 0x000fc8000000000a */
/*0510*/ FFMA R12, R17, R15, R6 ; /* 0x0000000f110c7223 */
/* 0x000fc80000000006 */
/*0520*/ FFMA R13, R13, R12, R10 ; /* 0x0000000c0d0d7223 */
/* 0x000fe2000000000a */
/*0530*/ IADD3 R10, R8, 0x7f, -R9 ; /* 0x0000007f080a7810 */
/* 0x000fc60007ffe809 */
/*0540*/ FFMA R6, R17, R13, R12 ; /* 0x0000000d11067223 */
/* 0x000fe4000000000c */
/*0550*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fc600078e0207 */
/*0560*/ SHF.R.U32.HI R8, RZ, 0x17, R6 ; /* 0x00000017ff087819 */
/* 0x000fc80000011606 */
/*0570*/ LOP3.LUT R8, R8, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff08087812 */
/* 0x000fca00078ec0ff */
/*0580*/ IMAD.IADD R11, R8, 0x1, R7 ; /* 0x00000001080b7824 */
/* 0x000fca00078e0207 */
/*0590*/ IADD3 R8, R11, -0x1, RZ ; /* 0xffffffff0b087810 */
/* 0x000fc80007ffe0ff */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f06070 */
/*05b0*/ @!P0 BRA 0x7c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*05d0*/ @P0 BRA 0x790 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*05f0*/ @P0 BRA 0x7d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0610*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0620*/ @!P0 BRA 0x7d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0630*/ FFMA.RZ R7, R17, R13.reuse, R12.reuse ; /* 0x0000000d11077223 */
/* 0x180fe2000000c00c */
/*0640*/ IADD3 R10, R11, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x000fe20007ffe0ff */
/*0650*/ FFMA.RM R8, R17, R13.reuse, R12.reuse ; /* 0x0000000d11087223 */
/* 0x180fe2000000400c */
/*0660*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0670*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*0680*/ FFMA.RP R7, R17, R13, R12 ; /* 0x0000000d11077223 */
/* 0x000fe2000000800c */
/*0690*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*06a0*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*06b0*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*06d0*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*06e0*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*06f0*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0700*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0710*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0720*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0730*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0740*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*0750*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*0760*/ IMAD.IADD R7, R10, 0x1, R7 ; /* 0x000000010a077824 */
/* 0x000fca00078e0207 */
/*0770*/ LOP3.LUT R6, R7, R6, RZ, 0xfc, !PT ; /* 0x0000000607067212 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*07a0*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x7d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R6, R7, 0x800000, R6 ; /* 0x0080000007067824 */
/* 0x000fe400078e0206 */
/*07d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07e0*/ BRA 0x870 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07f0*/ LOP3.LUT R6, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b067812 */
/* 0x000fc800078e480a */
/*0800*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x870 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R6, R11, 0x80000000, R10, 0x48, !PT ; /* 0x800000000b067812 */
/* 0x000fe200078e480a */
/*0830*/ BRA 0x870 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0840*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*0850*/ BRA 0x870 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0860*/ FADD.FTZ R6, R6, c[0x0][0x178] ; /* 0x00005e0006067621 */
/* 0x000fe40000010000 */
/*0870*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0880*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*0890*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*08a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*08b0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff74006007950 */
/* 0x000fea0003c3ffff */
/*08c0*/ BRA 0x8c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5BNAvgfPfPKfff
.globl _Z5BNAvgfPfPKfff
.p2align 8
.type _Z5BNAvgfPfPKfff,@function
_Z5BNAvgfPfPKfff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cvt_f32_i32_e32 v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nle_f32_e32 s3, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, s0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, s2, s2, v2
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, s2, v2
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
v_sub_f32_e64 v5, 1.0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, s2, v2
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v5, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5BNAvgfPfPKfff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5BNAvgfPfPKfff, .Lfunc_end0-_Z5BNAvgfPfPKfff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5BNAvgfPfPKfff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5BNAvgfPfPKfff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014f3f5_00000000-6_BNAvg.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff
.type _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff, @function
_Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5BNAvgfPfPKfff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff, .-_Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff
.globl _Z5BNAvgfPfPKfff
.type _Z5BNAvgfPfPKfff, @function
_Z5BNAvgfPfPKfff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5BNAvgfPfPKffffPfPKfff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5BNAvgfPfPKfff, .-_Z5BNAvgfPfPKfff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5BNAvgfPfPKfff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5BNAvgfPfPKfff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BNAvg.hip"
.globl _Z20__device_stub__BNAvgfPfPKfff # -- Begin function _Z20__device_stub__BNAvgfPfPKfff
.p2align 4, 0x90
.type _Z20__device_stub__BNAvgfPfPKfff,@function
_Z20__device_stub__BNAvgfPfPKfff: # @_Z20__device_stub__BNAvgfPfPKfff
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5BNAvgfPfPKfff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__BNAvgfPfPKfff, .Lfunc_end0-_Z20__device_stub__BNAvgfPfPKfff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5BNAvgfPfPKfff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5BNAvgfPfPKfff,@object # @_Z5BNAvgfPfPKfff
.section .rodata,"a",@progbits
.globl _Z5BNAvgfPfPKfff
.p2align 3, 0x0
_Z5BNAvgfPfPKfff:
.quad _Z20__device_stub__BNAvgfPfPKfff
.size _Z5BNAvgfPfPKfff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5BNAvgfPfPKfff"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__BNAvgfPfPKfff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5BNAvgfPfPKfff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "point.cuh"
Point::Point() {}
Point::Point(double x_, double y_, bool border_x, bool border_y):
x(x_), y(y_), borderX(border_x), borderY(border_y) {}
double Point::getX() const {
return x;
}
double Point::getY() const {
return y;
}
bool Point::isBorderX() const {
return borderX;
}
bool Point::isBorderY() const {
return borderY;
}
double Point::distance(Point &other) {
double deltaX = x - other.x;
double deltaY = y - other.y;
return pow(deltaX * deltaX + deltaY * deltaY, 0.5);
}
void Point::move(double deltaX, double deltaY) {
x += deltaX;
y += deltaY;
}
__device__ bool Point::operator==(const Point& other) const {
return x == other.x && y == other.y;
}
__device__ bool Point::operator!=(const Point &other) const {
return !(*this == other);
}
ostream& operator<<(ostream& os, const Point &p) {
os << "(" << p.x << ", " << p.y << ")";
return os;
} | code for sm_80 |
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