system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fb9b3_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
.type _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_, @function
_Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9compute_rPiPdS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_, .-_Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
.globl _Z9compute_rPiPdS0_
.type _Z9compute_rPiPdS0_, @function
_Z9compute_rPiPdS0_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9compute_rPiPdS0_, .-_Z9compute_rPiPdS0_
.globl _Z30__device_stub__Z9reductionPiS_PiS_
.type _Z30__device_stub__Z9reductionPiS_PiS_, @function
_Z30__device_stub__Z9reductionPiS_PiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9reductionPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z30__device_stub__Z9reductionPiS_PiS_, .-_Z30__device_stub__Z9reductionPiS_PiS_
.globl _Z9reductionPiS_
.type _Z9reductionPiS_, @function
_Z9reductionPiS_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9reductionPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z9reductionPiS_, .-_Z9reductionPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Refine Pi using "
.LC1:
.string " iterations"
.LC3:
.string "Executing Kernel with "
.LC4:
.string " threads on "
.LC5:
.string " blocks"
.LC8:
.string "Pi is "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10000000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rsp, %rdi
movl $1, %edx
movl $40000000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $80000000, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $80000000, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
.L20:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
movq 16(%rsp), %rax
movsd %xmm0, (%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
movq 8(%rsp), %rax
movsd %xmm0, (%rax,%rbx)
addq $8, %rbx
cmpq $79999992, %rbx
jne .L20
leaq 24(%rsp), %rdi
movl $1, %edx
movl $312500, %esi
call cudaMallocManaged@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $128, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $78125, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $78125, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L21:
call cudaDeviceSynchronize@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $78125, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
movl $4, %eax
.L23:
movq 24(%rsp), %rdx
movl (%rdx,%rax), %ecx
addl %ecx, (%rdx)
addq $4, %rax
cmpq $312500, %rax
jne .L23
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdl (%rax), %xmm0
divsd .LC6(%rip), %xmm0
mulsd .LC7(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z9compute_rPiPdS0_PiPdS0_
jmp .L21
.L29:
movq 24(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9reductionPiS_PiS_
jmp .L22
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9reductionPiS_"
.LC10:
.string "_Z9compute_rPiPdS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9compute_rPiPdS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -4194304
.long 1105199103
.align 8
.LC6:
.long 0
.long 1097011920
.align 8
.LC7:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__compute_rPiPdS0_ # -- Begin function _Z24__device_stub__compute_rPiPdS0_
.p2align 4, 0x90
.type _Z24__device_stub__compute_rPiPdS0_,@function
_Z24__device_stub__compute_rPiPdS0_: # @_Z24__device_stub__compute_rPiPdS0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9compute_rPiPdS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__compute_rPiPdS0_, .Lfunc_end0-_Z24__device_stub__compute_rPiPdS0_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__reductionPiS_ # -- Begin function _Z24__device_stub__reductionPiS_
.p2align 4, 0x90
.type _Z24__device_stub__reductionPiS_,@function
_Z24__device_stub__reductionPiS_: # @_Z24__device_stub__reductionPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__reductionPiS_, .Lfunc_end1-_Z24__device_stub__reductionPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI2_1:
.quad 0x416312d000000000 # double 1.0E+7
.LCPI2_2:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $10000000, %esi # imm = 0x989680
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB2_4
.LBB2_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 24(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $80000000, %esi # imm = 0x4C4B400
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movq 8(%rsp), %rax
movsd %xmm0, (%rax,%rbx,8)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movq 16(%rsp), %rax
movsd %xmm0, (%rax,%rbx,8)
incq %rbx
cmpq $9999999, %rbx # imm = 0x98967F
jne .LBB2_5
# %bb.6:
movq %rsp, %rdi
movl $312500, %esi # imm = 0x4C4B4
movl $1, %edx
callq hipMallocManaged
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $128, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.3, %esi
movl $12, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $78125, %esi # imm = 0x1312D
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.4, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB2_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB2_10
.LBB2_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movabsq $4294967424, %rbx # imm = 0x100000080
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 77997(%rbx), %r14
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 40(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9compute_rPiPdS0_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 24(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9reductionPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipDeviceSynchronize
movq (%rsp), %rax
movl (%rax), %ecx
movl $1, %edx
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
addl (%rax,%rdx,4), %ecx
incq %rdx
cmpq $78125, %rdx # imm = 0x1312D
jne .LBB2_15
# %bb.16:
movl %ecx, (%rax)
movq (%rsp), %rax
cvtsi2sdl (%rax), %xmm0
divsd .LCPI2_1(%rip), %xmm0
mulsd .LCPI2_2(%rip), %xmm0
movsd %xmm0, 120(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB2_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB2_20
.LBB2_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_21:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9compute_rPiPdS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9compute_rPiPdS0_,@object # @_Z9compute_rPiPdS0_
.section .rodata,"a",@progbits
.globl _Z9compute_rPiPdS0_
.p2align 3, 0x0
_Z9compute_rPiPdS0_:
.quad _Z24__device_stub__compute_rPiPdS0_
.size _Z9compute_rPiPdS0_, 8
.type _Z9reductionPiS_,@object # @_Z9reductionPiS_
.globl _Z9reductionPiS_
.p2align 3, 0x0
_Z9reductionPiS_:
.quad _Z24__device_stub__reductionPiS_
.size _Z9reductionPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Refine Pi using "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " iterations"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Executing Kernel with "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " threads on "
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " blocks"
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Pi is "
.size .L.str.5, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9compute_rPiPdS0_"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9reductionPiS_"
.size .L__unnamed_2, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__compute_rPiPdS0_
.addrsig_sym _Z24__device_stub__reductionPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9compute_rPiPdS0_
.addrsig_sym _Z9reductionPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#define N 4
__global__ void outputFromGPU()
{
printf("[%d] : [%d]\n", blockIdx.x, threadIdx.x);
}
__global__ void multiplicationTableBlock(int *mutex, int *index)
{
int c = blockIdx.x;
while(atomicExch(mutex, 1) != 0);
for(int i = 1; i <= 12; i++)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i);
}
printf("\n");
if(*index == 10){*index = 2;}
*index += 4;
atomicExch(mutex, 0);
}
__global__ void multiplicationTableThread()
{
int c = threadIdx.x;
int i = c+1;
for(int index = 2; index <= 10; index+=4)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, index, i, index*i, index+1, i, (index+1)*i, index+2, i, (index+2)*i, index+3, i, (index+3)*i);
if(i == 12){printf("\n");}
}
}
__global__ void multiplicationTableBlockAndThread(int *mutex, int *index)
{
int c = blockIdx.x;
int i = threadIdx.x+1;
if(threadIdx.x == 0)
{
while(atomicExch(mutex, 1) != 0);
*index += 4;
atomicExch(mutex, 0);
}
printf("[%d] : [%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n%s",
c, threadIdx.x, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i, (i == 12)?"\n":"");
}
int main(void)
{
printf(":: Ex3 ::\n\n");
int *h_index, *d_index, *d_mutex;
h_index = (int*)malloc(sizeof(int));
cudaMalloc((void**)&d_index, sizeof(int));
cudaMalloc((void**)&d_mutex, sizeof(int));
printf("\n::: Block only :::\n");
outputFromGPU<<<N, 1>>>();
cudaDeviceSynchronize();
printf("\n::: Thread only :::\n");
outputFromGPU<<<1, N>>>();
cudaDeviceSynchronize();
printf("\n::: Block and Thread :::\n");
outputFromGPU<<<N, N>>>();
cudaDeviceSynchronize();
printf("\n::: Multiplication Table Block :::\n\n");
*h_index = 2;
cudaMemcpy(d_index, h_index, sizeof(int), cudaMemcpyHostToDevice);
multiplicationTableBlock<<<3, 1>>>(d_mutex, d_index);
cudaDeviceSynchronize();
printf("::: Multiplication Table Thread :::\n\n");
multiplicationTableThread<<<1, 12>>>();
cudaDeviceSynchronize();
printf("::: Multiplication Table Block and Thread :::\n\n");
*h_index = -2;
cudaMemcpy(d_index, h_index, sizeof(int), cudaMemcpyHostToDevice);
multiplicationTableBlockAndThread<<<3, 12>>>(d_mutex, d_index);
cudaDeviceSynchronize();
printf("::: Multiplication Table CPU :::\n\n");
for(int i = 2; i <= 10; i+=4)
{
for(int a = 1; a <= 12; a++)
{
printf("%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
i, a, i*a, i+1, a, (i+1)*a, i+2, a, (i+2)*a, i+3, a, (i+3)*a);
}
printf("\n");
}
cudaFree(d_index);
cudaFree(d_mutex);
free(h_index);
return 0;
} | .file "tmpxft_001a2dbb_00000000-6_Ex3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13outputFromGPUvv
.type _Z32__device_stub__Z13outputFromGPUvv, @function
_Z32__device_stub__Z13outputFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13outputFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z13outputFromGPUvv, .-_Z32__device_stub__Z13outputFromGPUvv
.globl _Z13outputFromGPUv
.type _Z13outputFromGPUv, @function
_Z13outputFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13outputFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13outputFromGPUv, .-_Z13outputFromGPUv
.globl _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
.type _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_, @function
_Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24multiplicationTableBlockPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_, .-_Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
.globl _Z24multiplicationTableBlockPiS_
.type _Z24multiplicationTableBlockPiS_, @function
_Z24multiplicationTableBlockPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z24multiplicationTableBlockPiS_, .-_Z24multiplicationTableBlockPiS_
.globl _Z44__device_stub__Z25multiplicationTableThreadvv
.type _Z44__device_stub__Z25multiplicationTableThreadvv, @function
_Z44__device_stub__Z25multiplicationTableThreadvv:
.LFB2086:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z25multiplicationTableThreadv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z25multiplicationTableThreadvv, .-_Z44__device_stub__Z25multiplicationTableThreadvv
.globl _Z25multiplicationTableThreadv
.type _Z25multiplicationTableThreadv, @function
_Z25multiplicationTableThreadv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z25multiplicationTableThreadvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z25multiplicationTableThreadv, .-_Z25multiplicationTableThreadv
.globl _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
.type _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_, @function
_Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z33multiplicationTableBlockAndThreadPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_, .-_Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
.globl _Z33multiplicationTableBlockAndThreadPiS_
.type _Z33multiplicationTableBlockAndThreadPiS_, @function
_Z33multiplicationTableBlockAndThreadPiS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z33multiplicationTableBlockAndThreadPiS_, .-_Z33multiplicationTableBlockAndThreadPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ":: Ex3 ::\n\n"
.LC1:
.string "\n::: Block only :::\n"
.LC2:
.string "\n::: Thread only :::\n"
.LC3:
.string "\n::: Block and Thread :::\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\n::: Multiplication Table Block :::\n\n"
.align 8
.LC5:
.string "::: Multiplication Table Thread :::\n\n"
.align 8
.LC6:
.string "::: Multiplication Table Block and Thread :::\n\n"
.align 8
.LC7:
.string "::: Multiplication Table CPU :::\n\n"
.align 8
.LC8:
.string "%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n"
.section .rodata.str1.1
.LC9:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L36:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L37:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 0(%rbp)
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $3, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L39:
call cudaDeviceSynchronize@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $12, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L40:
call cudaDeviceSynchronize@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-2, 0(%rbp)
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $12, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $3, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
call cudaDeviceSynchronize@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, 12(%rsp)
movl $4, %r15d
movl $3, 8(%rsp)
movl $2, 16(%rsp)
movq %rbp, 24(%rsp)
.L42:
movl 16(%rsp), %r13d
movl %r13d, 20(%rsp)
movl 12(%rsp), %r12d
movl %r15d, %ebp
movl 8(%rsp), %r14d
movl $1, %ebx
.L43:
pushq %r12
.cfi_def_cfa_offset 152
pushq %rbx
.cfi_def_cfa_offset 160
movl 28(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 168
pushq %rbp
.cfi_def_cfa_offset 176
pushq %rbx
.cfi_def_cfa_offset 184
pushq %r15
.cfi_def_cfa_offset 192
pushq %r14
.cfi_def_cfa_offset 200
pushq %rbx
.cfi_def_cfa_offset 208
movl 72(%rsp), %r9d
movl %r13d, %r8d
movl %ebx, %ecx
movl 80(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 84(%rsp), %ecx
addl %ecx, %r13d
movl 72(%rsp), %edx
addl %edx, %r14d
addl %r15d, %ebp
movl 76(%rsp), %eax
addl %eax, %r12d
addq $64, %rsp
.cfi_def_cfa_offset 144
cmpl $13, %ebx
jne .L43
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $4, 16(%rsp)
movl 16(%rsp), %eax
addl $4, 8(%rsp)
addl $4, %r15d
addl $4, 12(%rsp)
cmpl $14, %eax
jne .L42
movq 24(%rsp), %rbp
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call _Z32__device_stub__Z13outputFromGPUvv
jmp .L36
.L49:
call _Z32__device_stub__Z13outputFromGPUvv
jmp .L37
.L50:
call _Z32__device_stub__Z13outputFromGPUvv
jmp .L38
.L51:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
jmp .L39
.L52:
call _Z44__device_stub__Z25multiplicationTableThreadvv
jmp .L40
.L53:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
jmp .L41
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z33multiplicationTableBlockAndThreadPiS_"
.align 8
.LC11:
.string "_Z25multiplicationTableThreadv"
.align 8
.LC12:
.string "_Z24multiplicationTableBlockPiS_"
.section .rodata.str1.1
.LC13:
.string "_Z13outputFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z33multiplicationTableBlockAndThreadPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z25multiplicationTableThreadv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z24multiplicationTableBlockPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13outputFromGPUv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#define N 4
__global__ void outputFromGPU()
{
printf("[%d] : [%d]\n", blockIdx.x, threadIdx.x);
}
__global__ void multiplicationTableBlock(int *mutex, int *index)
{
int c = blockIdx.x;
while(atomicExch(mutex, 1) != 0);
for(int i = 1; i <= 12; i++)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i);
}
printf("\n");
if(*index == 10){*index = 2;}
*index += 4;
atomicExch(mutex, 0);
}
__global__ void multiplicationTableThread()
{
int c = threadIdx.x;
int i = c+1;
for(int index = 2; index <= 10; index+=4)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, index, i, index*i, index+1, i, (index+1)*i, index+2, i, (index+2)*i, index+3, i, (index+3)*i);
if(i == 12){printf("\n");}
}
}
__global__ void multiplicationTableBlockAndThread(int *mutex, int *index)
{
int c = blockIdx.x;
int i = threadIdx.x+1;
if(threadIdx.x == 0)
{
while(atomicExch(mutex, 1) != 0);
*index += 4;
atomicExch(mutex, 0);
}
printf("[%d] : [%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n%s",
c, threadIdx.x, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i, (i == 12)?"\n":"");
}
int main(void)
{
printf(":: Ex3 ::\n\n");
int *h_index, *d_index, *d_mutex;
h_index = (int*)malloc(sizeof(int));
cudaMalloc((void**)&d_index, sizeof(int));
cudaMalloc((void**)&d_mutex, sizeof(int));
printf("\n::: Block only :::\n");
outputFromGPU<<<N, 1>>>();
cudaDeviceSynchronize();
printf("\n::: Thread only :::\n");
outputFromGPU<<<1, N>>>();
cudaDeviceSynchronize();
printf("\n::: Block and Thread :::\n");
outputFromGPU<<<N, N>>>();
cudaDeviceSynchronize();
printf("\n::: Multiplication Table Block :::\n\n");
*h_index = 2;
cudaMemcpy(d_index, h_index, sizeof(int), cudaMemcpyHostToDevice);
multiplicationTableBlock<<<3, 1>>>(d_mutex, d_index);
cudaDeviceSynchronize();
printf("::: Multiplication Table Thread :::\n\n");
multiplicationTableThread<<<1, 12>>>();
cudaDeviceSynchronize();
printf("::: Multiplication Table Block and Thread :::\n\n");
*h_index = -2;
cudaMemcpy(d_index, h_index, sizeof(int), cudaMemcpyHostToDevice);
multiplicationTableBlockAndThread<<<3, 12>>>(d_mutex, d_index);
cudaDeviceSynchronize();
printf("::: Multiplication Table CPU :::\n\n");
for(int i = 2; i <= 10; i+=4)
{
for(int a = 1; a <= 12; a++)
{
printf("%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
i, a, i*a, i+1, a, (i+1)*a, i+2, a, (i+2)*a, i+3, a, (i+3)*a);
}
printf("\n");
}
cudaFree(d_index);
cudaFree(d_mutex);
free(h_index);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define N 4
__global__ void outputFromGPU()
{
printf("[%d] : [%d]\n", blockIdx.x, threadIdx.x);
}
__global__ void multiplicationTableBlock(int *mutex, int *index)
{
int c = blockIdx.x;
while(atomicExch(mutex, 1) != 0);
for(int i = 1; i <= 12; i++)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i);
}
printf("\n");
if(*index == 10){*index = 2;}
*index += 4;
atomicExch(mutex, 0);
}
__global__ void multiplicationTableThread()
{
int c = threadIdx.x;
int i = c+1;
for(int index = 2; index <= 10; index+=4)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, index, i, index*i, index+1, i, (index+1)*i, index+2, i, (index+2)*i, index+3, i, (index+3)*i);
if(i == 12){printf("\n");}
}
}
__global__ void multiplicationTableBlockAndThread(int *mutex, int *index)
{
int c = blockIdx.x;
int i = threadIdx.x+1;
if(threadIdx.x == 0)
{
while(atomicExch(mutex, 1) != 0);
*index += 4;
atomicExch(mutex, 0);
}
printf("[%d] : [%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n%s",
c, threadIdx.x, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i, (i == 12)?"\n":"");
}
int main(void)
{
printf(":: Ex3 ::\n\n");
int *h_index, *d_index, *d_mutex;
h_index = (int*)malloc(sizeof(int));
hipMalloc((void**)&d_index, sizeof(int));
hipMalloc((void**)&d_mutex, sizeof(int));
printf("\n::: Block only :::\n");
outputFromGPU<<<N, 1>>>();
hipDeviceSynchronize();
printf("\n::: Thread only :::\n");
outputFromGPU<<<1, N>>>();
hipDeviceSynchronize();
printf("\n::: Block and Thread :::\n");
outputFromGPU<<<N, N>>>();
hipDeviceSynchronize();
printf("\n::: Multiplication Table Block :::\n\n");
*h_index = 2;
hipMemcpy(d_index, h_index, sizeof(int), hipMemcpyHostToDevice);
multiplicationTableBlock<<<3, 1>>>(d_mutex, d_index);
hipDeviceSynchronize();
printf("::: Multiplication Table Thread :::\n\n");
multiplicationTableThread<<<1, 12>>>();
hipDeviceSynchronize();
printf("::: Multiplication Table Block and Thread :::\n\n");
*h_index = -2;
hipMemcpy(d_index, h_index, sizeof(int), hipMemcpyHostToDevice);
multiplicationTableBlockAndThread<<<3, 12>>>(d_mutex, d_index);
hipDeviceSynchronize();
printf("::: Multiplication Table CPU :::\n\n");
for(int i = 2; i <= 10; i+=4)
{
for(int a = 1; a <= 12; a++)
{
printf("%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
i, a, i*a, i+1, a, (i+1)*a, i+2, a, (i+2)*a, i+3, a, (i+3)*a);
}
printf("\n");
}
hipFree(d_index);
hipFree(d_mutex);
free(h_index);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define N 4
__global__ void outputFromGPU()
{
printf("[%d] : [%d]\n", blockIdx.x, threadIdx.x);
}
__global__ void multiplicationTableBlock(int *mutex, int *index)
{
int c = blockIdx.x;
while(atomicExch(mutex, 1) != 0);
for(int i = 1; i <= 12; i++)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i);
}
printf("\n");
if(*index == 10){*index = 2;}
*index += 4;
atomicExch(mutex, 0);
}
__global__ void multiplicationTableThread()
{
int c = threadIdx.x;
int i = c+1;
for(int index = 2; index <= 10; index+=4)
{
printf("[%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
c, index, i, index*i, index+1, i, (index+1)*i, index+2, i, (index+2)*i, index+3, i, (index+3)*i);
if(i == 12){printf("\n");}
}
}
__global__ void multiplicationTableBlockAndThread(int *mutex, int *index)
{
int c = blockIdx.x;
int i = threadIdx.x+1;
if(threadIdx.x == 0)
{
while(atomicExch(mutex, 1) != 0);
*index += 4;
atomicExch(mutex, 0);
}
printf("[%d] : [%d]\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n%s",
c, threadIdx.x, *index, i, *index*i, *index+1, i, (*index+1)*i, *index+2, i, (*index+2)*i, *index+3, i, (*index+3)*i, (i == 12)?"\n":"");
}
int main(void)
{
printf(":: Ex3 ::\n\n");
int *h_index, *d_index, *d_mutex;
h_index = (int*)malloc(sizeof(int));
hipMalloc((void**)&d_index, sizeof(int));
hipMalloc((void**)&d_mutex, sizeof(int));
printf("\n::: Block only :::\n");
outputFromGPU<<<N, 1>>>();
hipDeviceSynchronize();
printf("\n::: Thread only :::\n");
outputFromGPU<<<1, N>>>();
hipDeviceSynchronize();
printf("\n::: Block and Thread :::\n");
outputFromGPU<<<N, N>>>();
hipDeviceSynchronize();
printf("\n::: Multiplication Table Block :::\n\n");
*h_index = 2;
hipMemcpy(d_index, h_index, sizeof(int), hipMemcpyHostToDevice);
multiplicationTableBlock<<<3, 1>>>(d_mutex, d_index);
hipDeviceSynchronize();
printf("::: Multiplication Table Thread :::\n\n");
multiplicationTableThread<<<1, 12>>>();
hipDeviceSynchronize();
printf("::: Multiplication Table Block and Thread :::\n\n");
*h_index = -2;
hipMemcpy(d_index, h_index, sizeof(int), hipMemcpyHostToDevice);
multiplicationTableBlockAndThread<<<3, 12>>>(d_mutex, d_index);
hipDeviceSynchronize();
printf("::: Multiplication Table CPU :::\n\n");
for(int i = 2; i <= 10; i+=4)
{
for(int a = 1; a <= 12; a++)
{
printf("%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n",
i, a, i*a, i+1, a, (i+1)*a, i+2, a, (i+2)*a, i+3, a, (i+3)*a);
}
printf("\n");
}
hipFree(d_index);
hipFree(d_mutex);
free(h_index);
return 0;
} | .text
.file "Ex3.hip"
.globl _Z28__device_stub__outputFromGPUv # -- Begin function _Z28__device_stub__outputFromGPUv
.p2align 4, 0x90
.type _Z28__device_stub__outputFromGPUv,@function
_Z28__device_stub__outputFromGPUv: # @_Z28__device_stub__outputFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__outputFromGPUv, .Lfunc_end0-_Z28__device_stub__outputFromGPUv
.cfi_endproc
# -- End function
.globl _Z39__device_stub__multiplicationTableBlockPiS_ # -- Begin function _Z39__device_stub__multiplicationTableBlockPiS_
.p2align 4, 0x90
.type _Z39__device_stub__multiplicationTableBlockPiS_,@function
_Z39__device_stub__multiplicationTableBlockPiS_: # @_Z39__device_stub__multiplicationTableBlockPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24multiplicationTableBlockPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z39__device_stub__multiplicationTableBlockPiS_, .Lfunc_end1-_Z39__device_stub__multiplicationTableBlockPiS_
.cfi_endproc
# -- End function
.globl _Z40__device_stub__multiplicationTableThreadv # -- Begin function _Z40__device_stub__multiplicationTableThreadv
.p2align 4, 0x90
.type _Z40__device_stub__multiplicationTableThreadv,@function
_Z40__device_stub__multiplicationTableThreadv: # @_Z40__device_stub__multiplicationTableThreadv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z25multiplicationTableThreadv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z40__device_stub__multiplicationTableThreadv, .Lfunc_end2-_Z40__device_stub__multiplicationTableThreadv
.cfi_endproc
# -- End function
.globl _Z48__device_stub__multiplicationTableBlockAndThreadPiS_ # -- Begin function _Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.p2align 4, 0x90
.type _Z48__device_stub__multiplicationTableBlockAndThreadPiS_,@function
_Z48__device_stub__multiplicationTableBlockAndThreadPiS_: # @_Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z33multiplicationTableBlockAndThreadPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z48__device_stub__multiplicationTableBlockAndThreadPiS_, .Lfunc_end3-_Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $.Lstr, %edi
callq puts@PLT
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 96(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $.Lstr.1, %edi
callq puts@PLT
leaq 3(%r14), %r15
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
callq hipDeviceSynchronize
movl $.Lstr.2, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipDeviceSynchronize
movl $.Lstr.3, %edi
callq puts@PLT
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipDeviceSynchronize
movl $.Lstr.4, %edi
callq puts@PLT
movl $2, (%rbx)
movq 88(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 2(%r14), %r15
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24multiplicationTableBlockPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movl $.Lstr.5, %edi
callq puts@PLT
leaq 11(%r14), %r12
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25multiplicationTableThreadv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
movl $.Lstr.6, %edi
callq puts@PLT
movl $-2, (%rbx)
movq 88(%rsp), %rdi
movl $4, %edx
movq %rbx, 128(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z33multiplicationTableBlockAndThreadPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
callq hipDeviceSynchronize
movl $.Lstr.7, %edi
callq puts@PLT
movl $2, %r14d
movl $5, 84(%rsp) # 4-byte Folded Spill
movl $4, 80(%rsp) # 4-byte Folded Spill
movl $3, 76(%rsp) # 4-byte Folded Spill
.p2align 4, 0x90
.LBB4_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_14 Depth 2
movl %r14d, %eax
orl $1, %eax
movl %eax, 124(%rsp) # 4-byte Spill
leal 2(%r14), %eax
movq %rax, 144(%rsp) # 8-byte Spill
leal 3(%r14), %eax
movq %rax, 136(%rsp) # 8-byte Spill
movl $1, %r15d
movl %r14d, %r12d
movl 76(%rsp), %eax # 4-byte Reload
movl %eax, %ebx
movl 80(%rsp), %eax # 4-byte Reload
movl %eax, %r13d
movl 84(%rsp), %eax # 4-byte Reload
movl %eax, %ebp
.p2align 4, 0x90
.LBB4_14: # Parent Loop BB4_13 Depth=1
# => This Inner Loop Header: Depth=2
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.8, %edi
movl %r14d, %esi
movl %r15d, %edx
movl %r12d, %ecx
movl 132(%rsp), %r8d # 4-byte Reload
movl %r15d, %r9d
xorl %eax, %eax
pushq %rbp
.cfi_adjust_cfa_offset 8
pushq %r15
.cfi_adjust_cfa_offset 8
pushq 160(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq %r13
.cfi_adjust_cfa_offset 8
pushq %r15
.cfi_adjust_cfa_offset 8
pushq 192(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq %rbx
.cfi_adjust_cfa_offset 8
callq printf
addq $64, %rsp
.cfi_adjust_cfa_offset -64
incl %r15d
addl 84(%rsp), %ebp # 4-byte Folded Reload
addl 80(%rsp), %r13d # 4-byte Folded Reload
addl 76(%rsp), %ebx # 4-byte Folded Reload
addl %r14d, %r12d
cmpl $13, %r15d
jne .LBB4_14
# %bb.15: # in Loop: Header=BB4_13 Depth=1
movl $10, %edi
callq putchar@PLT
leal 4(%r14), %eax
addl $4, 84(%rsp) # 4-byte Folded Spill
addl $4, 80(%rsp) # 4-byte Folded Spill
addl $4, 76(%rsp) # 4-byte Folded Spill
cmpl $7, %r14d
movl %eax, %r14d
jb .LBB4_13
# %bb.16:
movq 88(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13outputFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24multiplicationTableBlockPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25multiplicationTableThreadv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33multiplicationTableBlockAndThreadPiS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13outputFromGPUv,@object # @_Z13outputFromGPUv
.section .rodata,"a",@progbits
.globl _Z13outputFromGPUv
.p2align 3, 0x0
_Z13outputFromGPUv:
.quad _Z28__device_stub__outputFromGPUv
.size _Z13outputFromGPUv, 8
.type _Z24multiplicationTableBlockPiS_,@object # @_Z24multiplicationTableBlockPiS_
.globl _Z24multiplicationTableBlockPiS_
.p2align 3, 0x0
_Z24multiplicationTableBlockPiS_:
.quad _Z39__device_stub__multiplicationTableBlockPiS_
.size _Z24multiplicationTableBlockPiS_, 8
.type _Z25multiplicationTableThreadv,@object # @_Z25multiplicationTableThreadv
.globl _Z25multiplicationTableThreadv
.p2align 3, 0x0
_Z25multiplicationTableThreadv:
.quad _Z40__device_stub__multiplicationTableThreadv
.size _Z25multiplicationTableThreadv, 8
.type _Z33multiplicationTableBlockAndThreadPiS_,@object # @_Z33multiplicationTableBlockAndThreadPiS_
.globl _Z33multiplicationTableBlockAndThreadPiS_
.p2align 3, 0x0
_Z33multiplicationTableBlockAndThreadPiS_:
.quad _Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.size _Z33multiplicationTableBlockAndThreadPiS_, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n"
.size .L.str.8, 59
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13outputFromGPUv"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24multiplicationTableBlockPiS_"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z25multiplicationTableThreadv"
.size .L__unnamed_3, 31
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z33multiplicationTableBlockAndThreadPiS_"
.size .L__unnamed_4, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz ":: Ex3 ::\n"
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n::: Block only :::"
.size .Lstr.1, 20
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n::: Thread only :::"
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n::: Block and Thread :::"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n::: Multiplication Table Block :::\n"
.size .Lstr.4, 37
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "::: Multiplication Table Thread :::\n"
.size .Lstr.5, 37
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "::: Multiplication Table Block and Thread :::\n"
.size .Lstr.6, 47
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "::: Multiplication Table CPU :::\n"
.size .Lstr.7, 34
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__outputFromGPUv
.addrsig_sym _Z39__device_stub__multiplicationTableBlockPiS_
.addrsig_sym _Z40__device_stub__multiplicationTableThreadv
.addrsig_sym _Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13outputFromGPUv
.addrsig_sym _Z24multiplicationTableBlockPiS_
.addrsig_sym _Z25multiplicationTableThreadv
.addrsig_sym _Z33multiplicationTableBlockAndThreadPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a2dbb_00000000-6_Ex3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13outputFromGPUvv
.type _Z32__device_stub__Z13outputFromGPUvv, @function
_Z32__device_stub__Z13outputFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13outputFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z13outputFromGPUvv, .-_Z32__device_stub__Z13outputFromGPUvv
.globl _Z13outputFromGPUv
.type _Z13outputFromGPUv, @function
_Z13outputFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13outputFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13outputFromGPUv, .-_Z13outputFromGPUv
.globl _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
.type _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_, @function
_Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24multiplicationTableBlockPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_, .-_Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
.globl _Z24multiplicationTableBlockPiS_
.type _Z24multiplicationTableBlockPiS_, @function
_Z24multiplicationTableBlockPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z24multiplicationTableBlockPiS_, .-_Z24multiplicationTableBlockPiS_
.globl _Z44__device_stub__Z25multiplicationTableThreadvv
.type _Z44__device_stub__Z25multiplicationTableThreadvv, @function
_Z44__device_stub__Z25multiplicationTableThreadvv:
.LFB2086:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z25multiplicationTableThreadv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z44__device_stub__Z25multiplicationTableThreadvv, .-_Z44__device_stub__Z25multiplicationTableThreadvv
.globl _Z25multiplicationTableThreadv
.type _Z25multiplicationTableThreadv, @function
_Z25multiplicationTableThreadv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z25multiplicationTableThreadvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z25multiplicationTableThreadv, .-_Z25multiplicationTableThreadv
.globl _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
.type _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_, @function
_Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z33multiplicationTableBlockAndThreadPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_, .-_Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
.globl _Z33multiplicationTableBlockAndThreadPiS_
.type _Z33multiplicationTableBlockAndThreadPiS_, @function
_Z33multiplicationTableBlockAndThreadPiS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z33multiplicationTableBlockAndThreadPiS_, .-_Z33multiplicationTableBlockAndThreadPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ":: Ex3 ::\n\n"
.LC1:
.string "\n::: Block only :::\n"
.LC2:
.string "\n::: Thread only :::\n"
.LC3:
.string "\n::: Block and Thread :::\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "\n::: Multiplication Table Block :::\n\n"
.align 8
.LC5:
.string "::: Multiplication Table Thread :::\n\n"
.align 8
.LC6:
.string "::: Multiplication Table Block and Thread :::\n\n"
.align 8
.LC7:
.string "::: Multiplication Table CPU :::\n\n"
.align 8
.LC8:
.string "%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n"
.section .rodata.str1.1
.LC9:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
leaq 32(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L36:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L37:
call cudaDeviceSynchronize@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
call cudaDeviceSynchronize@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 0(%rbp)
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $3, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L39:
call cudaDeviceSynchronize@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $12, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L40:
call cudaDeviceSynchronize@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-2, 0(%rbp)
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $12, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $3, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L41:
call cudaDeviceSynchronize@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, 12(%rsp)
movl $4, %r15d
movl $3, 8(%rsp)
movl $2, 16(%rsp)
movq %rbp, 24(%rsp)
.L42:
movl 16(%rsp), %r13d
movl %r13d, 20(%rsp)
movl 12(%rsp), %r12d
movl %r15d, %ebp
movl 8(%rsp), %r14d
movl $1, %ebx
.L43:
pushq %r12
.cfi_def_cfa_offset 152
pushq %rbx
.cfi_def_cfa_offset 160
movl 28(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 168
pushq %rbp
.cfi_def_cfa_offset 176
pushq %rbx
.cfi_def_cfa_offset 184
pushq %r15
.cfi_def_cfa_offset 192
pushq %r14
.cfi_def_cfa_offset 200
pushq %rbx
.cfi_def_cfa_offset 208
movl 72(%rsp), %r9d
movl %r13d, %r8d
movl %ebx, %ecx
movl 80(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 84(%rsp), %ecx
addl %ecx, %r13d
movl 72(%rsp), %edx
addl %edx, %r14d
addl %r15d, %ebp
movl 76(%rsp), %eax
addl %eax, %r12d
addq $64, %rsp
.cfi_def_cfa_offset 144
cmpl $13, %ebx
jne .L43
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $4, 16(%rsp)
movl 16(%rsp), %eax
addl $4, 8(%rsp)
addl $4, %r15d
addl $4, 12(%rsp)
cmpl $14, %eax
jne .L42
movq 24(%rsp), %rbp
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call _Z32__device_stub__Z13outputFromGPUvv
jmp .L36
.L49:
call _Z32__device_stub__Z13outputFromGPUvv
jmp .L37
.L50:
call _Z32__device_stub__Z13outputFromGPUvv
jmp .L38
.L51:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z46__device_stub__Z24multiplicationTableBlockPiS_PiS_
jmp .L39
.L52:
call _Z44__device_stub__Z25multiplicationTableThreadvv
jmp .L40
.L53:
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z55__device_stub__Z33multiplicationTableBlockAndThreadPiS_PiS_
jmp .L41
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z33multiplicationTableBlockAndThreadPiS_"
.align 8
.LC11:
.string "_Z25multiplicationTableThreadv"
.align 8
.LC12:
.string "_Z24multiplicationTableBlockPiS_"
.section .rodata.str1.1
.LC13:
.string "_Z13outputFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z33multiplicationTableBlockAndThreadPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z25multiplicationTableThreadv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z24multiplicationTableBlockPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z13outputFromGPUv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Ex3.hip"
.globl _Z28__device_stub__outputFromGPUv # -- Begin function _Z28__device_stub__outputFromGPUv
.p2align 4, 0x90
.type _Z28__device_stub__outputFromGPUv,@function
_Z28__device_stub__outputFromGPUv: # @_Z28__device_stub__outputFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__outputFromGPUv, .Lfunc_end0-_Z28__device_stub__outputFromGPUv
.cfi_endproc
# -- End function
.globl _Z39__device_stub__multiplicationTableBlockPiS_ # -- Begin function _Z39__device_stub__multiplicationTableBlockPiS_
.p2align 4, 0x90
.type _Z39__device_stub__multiplicationTableBlockPiS_,@function
_Z39__device_stub__multiplicationTableBlockPiS_: # @_Z39__device_stub__multiplicationTableBlockPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24multiplicationTableBlockPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z39__device_stub__multiplicationTableBlockPiS_, .Lfunc_end1-_Z39__device_stub__multiplicationTableBlockPiS_
.cfi_endproc
# -- End function
.globl _Z40__device_stub__multiplicationTableThreadv # -- Begin function _Z40__device_stub__multiplicationTableThreadv
.p2align 4, 0x90
.type _Z40__device_stub__multiplicationTableThreadv,@function
_Z40__device_stub__multiplicationTableThreadv: # @_Z40__device_stub__multiplicationTableThreadv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z25multiplicationTableThreadv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size _Z40__device_stub__multiplicationTableThreadv, .Lfunc_end2-_Z40__device_stub__multiplicationTableThreadv
.cfi_endproc
# -- End function
.globl _Z48__device_stub__multiplicationTableBlockAndThreadPiS_ # -- Begin function _Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.p2align 4, 0x90
.type _Z48__device_stub__multiplicationTableBlockAndThreadPiS_,@function
_Z48__device_stub__multiplicationTableBlockAndThreadPiS_: # @_Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z33multiplicationTableBlockAndThreadPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z48__device_stub__multiplicationTableBlockAndThreadPiS_, .Lfunc_end3-_Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $.Lstr, %edi
callq puts@PLT
movl $4, %edi
callq malloc
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 96(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $.Lstr.1, %edi
callq puts@PLT
leaq 3(%r14), %r15
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
callq hipDeviceSynchronize
movl $.Lstr.2, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
callq hipDeviceSynchronize
movl $.Lstr.3, %edi
callq puts@PLT
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13outputFromGPUv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq hipDeviceSynchronize
movl $.Lstr.4, %edi
callq puts@PLT
movl $2, (%rbx)
movq 88(%rsp), %rdi
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 2(%r14), %r15
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z24multiplicationTableBlockPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movl $.Lstr.5, %edi
callq puts@PLT
leaq 11(%r14), %r12
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
leaq 48(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z25multiplicationTableThreadv, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
movl $.Lstr.6, %edi
callq puts@PLT
movl $-2, (%rbx)
movq 88(%rsp), %rdi
movl $4, %edx
movq %rbx, 128(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_12
# %bb.11:
movq 96(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 24(%rsp)
movq %rcx, 64(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z33multiplicationTableBlockAndThreadPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_12:
callq hipDeviceSynchronize
movl $.Lstr.7, %edi
callq puts@PLT
movl $2, %r14d
movl $5, 84(%rsp) # 4-byte Folded Spill
movl $4, 80(%rsp) # 4-byte Folded Spill
movl $3, 76(%rsp) # 4-byte Folded Spill
.p2align 4, 0x90
.LBB4_13: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_14 Depth 2
movl %r14d, %eax
orl $1, %eax
movl %eax, 124(%rsp) # 4-byte Spill
leal 2(%r14), %eax
movq %rax, 144(%rsp) # 8-byte Spill
leal 3(%r14), %eax
movq %rax, 136(%rsp) # 8-byte Spill
movl $1, %r15d
movl %r14d, %r12d
movl 76(%rsp), %eax # 4-byte Reload
movl %eax, %ebx
movl 80(%rsp), %eax # 4-byte Reload
movl %eax, %r13d
movl 84(%rsp), %eax # 4-byte Reload
movl %eax, %ebp
.p2align 4, 0x90
.LBB4_14: # Parent Loop BB4_13 Depth=1
# => This Inner Loop Header: Depth=2
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.8, %edi
movl %r14d, %esi
movl %r15d, %edx
movl %r12d, %ecx
movl 132(%rsp), %r8d # 4-byte Reload
movl %r15d, %r9d
xorl %eax, %eax
pushq %rbp
.cfi_adjust_cfa_offset 8
pushq %r15
.cfi_adjust_cfa_offset 8
pushq 160(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq %r13
.cfi_adjust_cfa_offset 8
pushq %r15
.cfi_adjust_cfa_offset 8
pushq 192(%rsp) # 8-byte Folded Reload
.cfi_adjust_cfa_offset 8
pushq %rbx
.cfi_adjust_cfa_offset 8
callq printf
addq $64, %rsp
.cfi_adjust_cfa_offset -64
incl %r15d
addl 84(%rsp), %ebp # 4-byte Folded Reload
addl 80(%rsp), %r13d # 4-byte Folded Reload
addl 76(%rsp), %ebx # 4-byte Folded Reload
addl %r14d, %r12d
cmpl $13, %r15d
jne .LBB4_14
# %bb.15: # in Loop: Header=BB4_13 Depth=1
movl $10, %edi
callq putchar@PLT
leal 4(%r14), %eax
addl $4, 84(%rsp) # 4-byte Folded Spill
addl $4, 80(%rsp) # 4-byte Folded Spill
addl $4, 76(%rsp) # 4-byte Folded Spill
cmpl $7, %r14d
movl %eax, %r14d
jb .LBB4_13
# %bb.16:
movq 88(%rsp), %rdi
callq hipFree
movq 96(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13outputFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24multiplicationTableBlockPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25multiplicationTableThreadv, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33multiplicationTableBlockAndThreadPiS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13outputFromGPUv,@object # @_Z13outputFromGPUv
.section .rodata,"a",@progbits
.globl _Z13outputFromGPUv
.p2align 3, 0x0
_Z13outputFromGPUv:
.quad _Z28__device_stub__outputFromGPUv
.size _Z13outputFromGPUv, 8
.type _Z24multiplicationTableBlockPiS_,@object # @_Z24multiplicationTableBlockPiS_
.globl _Z24multiplicationTableBlockPiS_
.p2align 3, 0x0
_Z24multiplicationTableBlockPiS_:
.quad _Z39__device_stub__multiplicationTableBlockPiS_
.size _Z24multiplicationTableBlockPiS_, 8
.type _Z25multiplicationTableThreadv,@object # @_Z25multiplicationTableThreadv
.globl _Z25multiplicationTableThreadv
.p2align 3, 0x0
_Z25multiplicationTableThreadv:
.quad _Z40__device_stub__multiplicationTableThreadv
.size _Z25multiplicationTableThreadv, 8
.type _Z33multiplicationTableBlockAndThreadPiS_,@object # @_Z33multiplicationTableBlockAndThreadPiS_
.globl _Z33multiplicationTableBlockAndThreadPiS_
.p2align 3, 0x0
_Z33multiplicationTableBlockAndThreadPiS_:
.quad _Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.size _Z33multiplicationTableBlockAndThreadPiS_, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d \t\t%d x %d = %d\n"
.size .L.str.8, 59
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13outputFromGPUv"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z24multiplicationTableBlockPiS_"
.size .L__unnamed_2, 33
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z25multiplicationTableThreadv"
.size .L__unnamed_3, 31
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z33multiplicationTableBlockAndThreadPiS_"
.size .L__unnamed_4, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz ":: Ex3 ::\n"
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n::: Block only :::"
.size .Lstr.1, 20
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n::: Thread only :::"
.size .Lstr.2, 21
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\n::: Block and Thread :::"
.size .Lstr.3, 26
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n::: Multiplication Table Block :::\n"
.size .Lstr.4, 37
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "::: Multiplication Table Thread :::\n"
.size .Lstr.5, 37
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "::: Multiplication Table Block and Thread :::\n"
.size .Lstr.6, 47
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "::: Multiplication Table CPU :::\n"
.size .Lstr.7, 34
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__outputFromGPUv
.addrsig_sym _Z39__device_stub__multiplicationTableBlockPiS_
.addrsig_sym _Z40__device_stub__multiplicationTableThreadv
.addrsig_sym _Z48__device_stub__multiplicationTableBlockAndThreadPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13outputFromGPUv
.addrsig_sym _Z24multiplicationTableBlockPiS_
.addrsig_sym _Z25multiplicationTableThreadv
.addrsig_sym _Z33multiplicationTableBlockAndThreadPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include<cstdlib>
#include "cu_nbmath.cuh"
using namespace std;
__device__ void vecAdd(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]+B;
}
}
__device__ void vecMult(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]*B;
}
}
__device__ void vecDiv(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]/B;
}
}
__device__ void elementWiseAdd(double* result, double* A, double* B, int size){
for (int i = 0; i < size; i++){
result[i] = A[i]+B[i];
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include<cstdlib>
#include "cu_nbmath.cuh"
using namespace std;
__device__ void vecAdd(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]+B;
}
}
__device__ void vecMult(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]*B;
}
}
__device__ void vecDiv(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]/B;
}
}
__device__ void elementWiseAdd(double* result, double* A, double* B, int size){
for (int i = 0; i < size; i++){
result[i] = A[i]+B[i];
}
} | .file "tmpxft_000a40d8_00000000-6_cu_nbmath.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6vecAddPdS_di
.type _Z6vecAddPdS_di, @function
_Z6vecAddPdS_di:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z6vecAddPdS_di, .-_Z6vecAddPdS_di
.globl _Z7vecMultPdS_di
.type _Z7vecMultPdS_di, @function
_Z7vecMultPdS_di:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z7vecMultPdS_di, .-_Z7vecMultPdS_di
.globl _Z6vecDivPdS_di
.type _Z6vecDivPdS_di, @function
_Z6vecDivPdS_di:
.LFB3671:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _Z6vecDivPdS_di, .-_Z6vecDivPdS_di
.globl _Z14elementWiseAddPdS_S_i
.type _Z14elementWiseAddPdS_S_i, @function
_Z14elementWiseAddPdS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3672:
.size _Z14elementWiseAddPdS_S_i, .-_Z14elementWiseAddPdS_S_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include<cstdlib>
#include "cu_nbmath.cuh"
using namespace std;
__device__ void vecAdd(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]+B;
}
}
__device__ void vecMult(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]*B;
}
}
__device__ void vecDiv(double* result, double* A, double B, int sizeA){
for (int i = 0; i < sizeA; i++){
result[i] = A[i]/B;
}
}
__device__ void elementWiseAdd(double* result, double* A, double* B, int size){
for (int i = 0; i < size; i++){
result[i] = A[i]+B[i];
}
} | #ifndef NBMATH
#define NBMATH
/* Function -> vecAdd: Add a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A +. B [double *]
* A -> array to add B to by operation A +. B [double *]
* B -> scaler to add to array B by operation A +. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A +. B
*
*/
__device__ void vecAdd(double* result, double* A, double B, int sizeA);
/* Function -> vecMult: Multiply a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A *. B [double *]
* A -> array to add B to by operation A *. B [double *]
* B -> scaler to add to array B by operation A *. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A *. B
*
*/
__device__ void vecMult(double* result, double* A, double B, int sizeA);
/* Function -> vecDiv: Divide a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A /. B [double *]
* A -> array to add B to by operation A /. B [double *]
* B -> scaler to add to array B by operation A /. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A /. B
*
*/
__device__ void vecDiv(double* result, double* A, double B, int sizeA);
/* Function -> elementWiseAdd: Add a two vectors element by element
*
* Params:
* result -> array to store the resultant vector A + B [double *]
* A -> array to add B to by operation A + B [double *]
* B -> array to add to array B by operation A + B [double *]
* sizeA -> size of arrays A&B [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A + B
*
*/
__device__ void elementWiseAdd(double* result, double* A, double* B, int size);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef NBMATH
#define NBMATH
/* Function -> vecAdd: Add a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A +. B [double *]
* A -> array to add B to by operation A +. B [double *]
* B -> scaler to add to array B by operation A +. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A +. B
*
*/
__device__ void vecAdd(double* result, double* A, double B, int sizeA);
/* Function -> vecMult: Multiply a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A *. B [double *]
* A -> array to add B to by operation A *. B [double *]
* B -> scaler to add to array B by operation A *. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A *. B
*
*/
__device__ void vecMult(double* result, double* A, double B, int sizeA);
/* Function -> vecDiv: Divide a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A /. B [double *]
* A -> array to add B to by operation A /. B [double *]
* B -> scaler to add to array B by operation A /. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A /. B
*
*/
__device__ void vecDiv(double* result, double* A, double B, int sizeA);
/* Function -> elementWiseAdd: Add a two vectors element by element
*
* Params:
* result -> array to store the resultant vector A + B [double *]
* A -> array to add B to by operation A + B [double *]
* B -> array to add to array B by operation A + B [double *]
* sizeA -> size of arrays A&B [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A + B
*
*/
__device__ void elementWiseAdd(double* result, double* A, double* B, int size);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef NBMATH
#define NBMATH
/* Function -> vecAdd: Add a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A +. B [double *]
* A -> array to add B to by operation A +. B [double *]
* B -> scaler to add to array B by operation A +. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A +. B
*
*/
__device__ void vecAdd(double* result, double* A, double B, int sizeA);
/* Function -> vecMult: Multiply a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A *. B [double *]
* A -> array to add B to by operation A *. B [double *]
* B -> scaler to add to array B by operation A *. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A *. B
*
*/
__device__ void vecMult(double* result, double* A, double B, int sizeA);
/* Function -> vecDiv: Divide a scaler to a vector
*
* Params:
* result -> array to store the resultant vector A /. B [double *]
* A -> array to add B to by operation A /. B [double *]
* B -> scaler to add to array B by operation A /. B [double]
* sizeA -> size of array A [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A /. B
*
*/
__device__ void vecDiv(double* result, double* A, double B, int sizeA);
/* Function -> elementWiseAdd: Add a two vectors element by element
*
* Params:
* result -> array to store the resultant vector A + B [double *]
* A -> array to add B to by operation A + B [double *]
* B -> array to add to array B by operation A + B [double *]
* sizeA -> size of arrays A&B [int]
*
* Preconditions:
* - A allocated and given values
* - result allocated to be of sizeA doubles
*
* Postconditions:
* - results filled with results of operation A + B
*
*/
__device__ void elementWiseAdd(double* result, double* A, double* B, int size);
#endif | .text
.file "cu_nbmath.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a40d8_00000000-6_cu_nbmath.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6vecAddPdS_di
.type _Z6vecAddPdS_di, @function
_Z6vecAddPdS_di:
.LFB3669:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z6vecAddPdS_di, .-_Z6vecAddPdS_di
.globl _Z7vecMultPdS_di
.type _Z7vecMultPdS_di, @function
_Z7vecMultPdS_di:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z7vecMultPdS_di, .-_Z7vecMultPdS_di
.globl _Z6vecDivPdS_di
.type _Z6vecDivPdS_di, @function
_Z6vecDivPdS_di:
.LFB3671:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3671:
.size _Z6vecDivPdS_di, .-_Z6vecDivPdS_di
.globl _Z14elementWiseAddPdS_S_i
.type _Z14elementWiseAddPdS_S_i, @function
_Z14elementWiseAddPdS_S_i:
.LFB3672:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3672:
.size _Z14elementWiseAddPdS_S_i, .-_Z14elementWiseAddPdS_S_i
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cu_nbmath.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void calculateDelaysAndPhases(double * gpuDelays, double lo, double sampletime, int fftsamples, int fftchannels, int samplegranularity, float * rotationPhaseInfo, int *sampleShifts, float* fractionalSampleDelays)
{
size_t ifft = threadIdx.x + blockIdx.x * blockDim.x;
size_t iant = blockIdx.y;
int numffts = blockDim.x * gridDim.x;
double meandelay, deltadelay, netdelaysamples_f, startphase;
double d0, d1, d2, a, b;
double * interpolator = &(gpuDelays[iant*4]);
double filestartoffset = gpuDelays[iant*4+3];
float fractionaldelay;
int netdelaysamples;
// evaluate the delay for the given FFT of the given antenna
// calculate values at the beginning, middle, and end of this FFT
d0 = interpolator[0]*ifft*ifft + interpolator[1]*ifft + interpolator[2];
d1 = interpolator[0]*(ifft+0.5)*(ifft+0.5) + interpolator[1]*(ifft+0.5) + interpolator[2];
d2 = interpolator[0]*(ifft+1.0)*(ifft+1.0) + interpolator[1]*(ifft+1.0) + interpolator[2];
// use these to calculate a linear interpolator across the FFT, as well as a mean value
a = d2-d0; //this is the delay gradient across this FFT
b = d0 + (d1 - (a*0.5 + d0))/3.0; //this is the delay at the start of the FFT
meandelay = a*0.5 + b; //this is the delay in the middle of the FFT
deltadelay = a / fftsamples; // this is the change in delay per sample across this FFT window
netdelaysamples_f = (meandelay - filestartoffset) / sampletime;
netdelaysamples = __double2int_rn(netdelaysamples_f/samplegranularity) * samplegranularity;
// Save the integer number of sample shifts
sampleShifts[iant*numffts + ifft] = netdelaysamples;
// Save the fractional delay
fractionaldelay = (float)(-(netdelaysamples_f - netdelaysamples)*2*M_PI/fftsamples); // radians per FFT channel
fractionalSampleDelays[iant*numffts + ifft] = fractionaldelay;
// set the fringe rotation phase for the first sample of a given FFT of a given antenna
startphase = b*lo;
rotationPhaseInfo[iant*numffts*2 + ifft*2] = (float)(startphase - int(startphase))*2*M_PI;
rotationPhaseInfo[iant*numffts*2 + ifft*2 + 1] = (float)(deltadelay * lo)*2*M_PI;
} | code for sm_80
Function : _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R14, RZ, RZ, 0x20 ; /* 0x00000020ff0e7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R14, R3, R14, c[0x0][0x160] ; /* 0x00005800030e7625 */
/* 0x001fca00078e000e */
/*0050*/ LDG.E.64 R8, [R14.64] ; /* 0x000000060e087981 */
/* 0x0000a8000c1e1b00 */
/*0060*/ LDG.E.64 R12, [R14.64+0x8] ; /* 0x000008060e0c7981 */
/* 0x0000e8000c1e1b00 */
/*0070*/ LDG.E.64 R4, [R14.64+0x10] ; /* 0x000010060e047981 */
/* 0x000128000c1e1b00 */
/*0080*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e680000002100 */
/*0090*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*00a0*/ MUFU.RCP64H R17, 3 ; /* 0x4008000000117908 */
/* 0x000e220000001800 */
/*00b0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fc400078e00ff */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40080000 ; /* 0x40080000ff0b7424 */
/* 0x000fe200078e00ff */
/*00d0*/ LDG.E.64 R28, [R14.64+0x18] ; /* 0x000018060e1c7981 */
/* 0x000162000c1e1b00 */
/*00e0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*00f0*/ BSSY B0, 0x340 ; /* 0x0000024000007945 */
/* 0x000fea0003800000 */
/*0100*/ DFMA R18, R16, -R10, 1 ; /* 0x3ff000001012742b */
/* 0x001e0c000000080a */
/*0110*/ DFMA R24, R18, R18, R18 ; /* 0x000000121218722b */
/* 0x001e220000000012 */
/*0120*/ IMAD R6, R7, c[0x0][0x0], R6 ; /* 0x0000000007067a24 */
/* 0x002fc800078e0206 */
/*0130*/ I2F.F64.U32 R20, R6 ; /* 0x0000000600147312 */
/* 0x000e620000201800 */
/*0140*/ DFMA R16, R16, R24, R16 ; /* 0x000000181010722b */
/* 0x001e0c0000000010 */
/*0150*/ DFMA R10, R16, -R10, 1 ; /* 0x3ff00000100a742b */
/* 0x001e0c000000080a */
/*0160*/ DFMA R10, R16, R10, R16 ; /* 0x0000000a100a722b */
/* 0x001fc80000000010 */
/*0170*/ DADD R14, R20, 1 ; /* 0x3ff00000140e7429 */
/* 0x002e080000000000 */
/*0180*/ DMUL R18, R8, R20 ; /* 0x0000001408127228 */
/* 0x004fc80000000000 */
/*0190*/ DMUL R22, R20, R12 ; /* 0x0000000c14167228 */
/* 0x008e480000000000 */
/*01a0*/ DMUL R24, R12, R14 ; /* 0x0000000e0c187228 */
/* 0x001fc80000000000 */
/*01b0*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x002fc80000000016 */
/*01c0*/ DMUL R22, R8, R14 ; /* 0x0000000e08167228 */
/* 0x000e080000000000 */
/*01d0*/ DADD R20, R20, 0.5 ; /* 0x3fe0000014147429 */
/* 0x000e480000000000 */
/*01e0*/ DFMA R22, R14, R22, R24 ; /* 0x000000160e16722b */
/* 0x001e080000000018 */
/*01f0*/ DMUL R8, R8, R20 ; /* 0x0000001408087228 */
/* 0x002fc80000000000 */
/*0200*/ DMUL R12, R12, R20 ; /* 0x000000140c0c7228 */
/* 0x000e480000000000 */
/*0210*/ DADD R14, R18, R4 ; /* 0x00000000120e7229 */
/* 0x010fc80000000004 */
/*0220*/ DADD R22, R4, R22 ; /* 0x0000000004167229 */
/* 0x001e080000000016 */
/*0230*/ DFMA R12, R20, R8, R12 ; /* 0x00000008140c722b */
/* 0x002e48000000000c */
/*0240*/ DADD R8, -R14, R22 ; /* 0x000000000e087229 */
/* 0x001e080000000116 */
/*0250*/ DADD R12, R4, R12 ; /* 0x00000000040c7229 */
/* 0x002fc8000000000c */
/*0260*/ DFMA R4, R8, 0.5, R14 ; /* 0x3fe000000804782b */
/* 0x001e0c000000000e */
/*0270*/ DADD R18, R12, -R4 ; /* 0x000000000c127229 */
/* 0x001e0c0000000804 */
/*0280*/ DMUL R32, R18, R10 ; /* 0x0000000a12207228 */
/* 0x001e080000000000 */
/*0290*/ FSETP.GEU.AND P1, PT, |R19|, 6.5827683646048100446e-37, PT ; /* 0x036000001300780b */
/* 0x000fe40003f2e200 */
/*02a0*/ DFMA R4, R32, -3, R18 ; /* 0xc00800002004782b */
/* 0x001e0c0000000012 */
/*02b0*/ DFMA R32, R10, R4, R32 ; /* 0x000000040a20722b */
/* 0x001e140000000020 */
/*02c0*/ FFMA R0, RZ, 2.125, R33 ; /* 0x40080000ff007823 */
/* 0x001fca0000000021 */
/*02d0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*02e0*/ @P0 BRA P1, 0x330 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*02f0*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0300*/ MOV R4, 0x330 ; /* 0x0000033000047802 */
/* 0x000fe20000000f00 */
/*0310*/ IMAD.MOV.U32 R23, RZ, RZ, 0x40080000 ; /* 0x40080000ff177424 */
/* 0x000fe400078e00ff */
/*0320*/ CALL.REL.NOINC 0xbd0 ; /* 0x000008a000007944 */
/* 0x020fea0003c00000 */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ I2F.F64 R10, c[0x0][0x178] ; /* 0x00005e00000a7b12 */
/* 0x000e220000201c00 */
/*0350*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0360*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe20003f2e200 */
/*0370*/ DADD R14, R14, R32 ; /* 0x000000000e0e7229 */
/* 0x000fe20000000020 */
/*0380*/ BSSY B0, 0x4f0 ; /* 0x0000016000007945 */
/* 0x000fe80003800000 */
/*0390*/ MUFU.RCP64H R5, R11 ; /* 0x0000000b00057308 */
/* 0x001e240000001800 */
/*03a0*/ DFMA R12, -R10, R4, 1 ; /* 0x3ff000000a0c742b */
/* 0x001e0c0000000104 */
/*03b0*/ DFMA R12, R12, R12, R12 ; /* 0x0000000c0c0c722b */
/* 0x001e0c000000000c */
/*03c0*/ DFMA R12, R4, R12, R4 ; /* 0x0000000c040c722b */
/* 0x001e0c0000000004 */
/*03d0*/ DFMA R4, -R10, R12, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c000000010c */
/*03e0*/ DFMA R4, R12, R4, R12 ; /* 0x000000040c04722b */
/* 0x001e0c000000000c */
/*03f0*/ DMUL R12, R8, R4 ; /* 0x00000004080c7228 */
/* 0x001e0c0000000000 */
/*0400*/ DFMA R16, -R10, R12, R8 ; /* 0x0000000c0a10722b */
/* 0x001e0c0000000108 */
/*0410*/ DFMA R12, R4, R16, R12 ; /* 0x00000010040c722b */
/* 0x001e08000000000c */
/*0420*/ DFMA R16, R8, 0.5, R14 ; /* 0x3fe000000810782b */
/* 0x00028c000000000e */
/*0430*/ FFMA R0, RZ, R11, R13 ; /* 0x0000000bff007223 */
/* 0x001fca000000000d */
/*0440*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0450*/ @P0 BRA P1, 0x4e0 ; /* 0x0000008000000947 */
/* 0x000fea0000800000 */
/*0460*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x006fe200078e0008 */
/*0470*/ MOV R4, 0x4c0 ; /* 0x000004c000047802 */
/* 0x000fe20000000f00 */
/*0480*/ IMAD.MOV.U32 R19, RZ, RZ, R9 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0009 */
/*0490*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ; /* 0x000000ffff147224 */
/* 0x000fe400078e000a */
/*04a0*/ IMAD.MOV.U32 R23, RZ, RZ, R11 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000b */
/*04b0*/ CALL.REL.NOINC 0xbd0 ; /* 0x0000071000007944 */
/* 0x020fea0003c00000 */
/*04c0*/ IMAD.MOV.U32 R12, RZ, RZ, R32 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0020 */
/*04d0*/ IMAD.MOV.U32 R13, RZ, RZ, R33 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0021 */
/*04e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x006fea0003800000 */
/*04f0*/ MUFU.RCP64H R5, c[0x0][0x174] ; /* 0x00005d0000057b08 */
/* 0x000e220000001800 */
/*0500*/ IMAD.MOV.U32 R18, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff127624 */
/* 0x000fe200078e00ff */
/*0510*/ BSSY B0, 0x680 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff137624 */
/* 0x000fc400078e00ff */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fcc00078e00ff */
/*0540*/ DFMA R8, R4, -R18, 1 ; /* 0x3ff000000408742b */
/* 0x001e0c0000000812 */
/*0550*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0560*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x001e0c0000000004 */
/*0570*/ DFMA R4, R8, -R18, 1 ; /* 0x3ff000000804742b */
/* 0x001e080000000812 */
/*0580*/ DADD R18, -R28, R16 ; /* 0x000000001c127229 */
/* 0x020fc80000000110 */
/*0590*/ DFMA R4, R8, R4, R8 ; /* 0x000000040804722b */
/* 0x001e0c0000000008 */
/*05a0*/ DMUL R8, R18, R4 ; /* 0x0000000412087228 */
/* 0x001e220000000000 */
/*05b0*/ FSETP.GEU.AND P1, PT, |R19|, 6.5827683646048100446e-37, PT ; /* 0x036000001300780b */
/* 0x000fca0003f2e200 */
/*05c0*/ DFMA R16, R8, -c[0x0][0x170], R18 ; /* 0x80005c0008107a2b */
/* 0x001e0c0000000012 */
/*05d0*/ DFMA R8, R4, R16, R8 ; /* 0x000000100408722b */
/* 0x001e140000000008 */
/*05e0*/ FFMA R0, RZ, c[0x0][0x174], R9 ; /* 0x00005d00ff007a23 */
/* 0x001fca0000000009 */
/*05f0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0600*/ @P0 BRA P1, 0x670 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0610*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff147624 */
/* 0x000fe200078e00ff */
/*0620*/ MOV R4, 0x650 ; /* 0x0000065000047802 */
/* 0x000fe20000000f00 */
/*0630*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff177624 */
/* 0x000fe400078e00ff */
/*0640*/ CALL.REL.NOINC 0xbd0 ; /* 0x0000058000007944 */
/* 0x000fea0003c00000 */
/*0650*/ IMAD.MOV.U32 R8, RZ, RZ, R32 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0020 */
/*0660*/ IMAD.MOV.U32 R9, RZ, RZ, R33 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0021 */
/*0670*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0680*/ I2F.F64 R20, c[0x0][0x180] ; /* 0x0000600000147b12 */
/* 0x000e220000201c00 */
/*0690*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*06a0*/ FSETP.GEU.AND P1, PT, |R9|, 6.5827683646048100446e-37, PT ; /* 0x036000000900780b */
/* 0x000fe20003f2e200 */
/*06b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*06c0*/ BSSY B0, 0x810 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*06d0*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe40000000800 */
/*06e0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*06f0*/ MUFU.RCP64H R5, R21 ; /* 0x0000001500057308 */
/* 0x001e240000001800 */
/*0700*/ DFMA R16, -R20, R4, 1 ; /* 0x3ff000001410742b */
/* 0x001e0c0000000104 */
/*0710*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0720*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e0c0000000004 */
/*0730*/ DFMA R4, -R20, R16, 1 ; /* 0x3ff000001404742b */
/* 0x001e0c0000000110 */
/*0740*/ DFMA R4, R16, R4, R16 ; /* 0x000000041004722b */
/* 0x001e0c0000000010 */
/*0750*/ DMUL R16, R4, R8 ; /* 0x0000000804107228 */
/* 0x001e0c0000000000 */
/*0760*/ DFMA R18, -R20, R16, R8 ; /* 0x000000101412722b */
/* 0x001e0c0000000108 */
/*0770*/ DFMA R32, R4, R18, R16 ; /* 0x000000120420722b */
/* 0x001e140000000010 */
/*0780*/ FFMA R0, RZ, R21, R33 ; /* 0x00000015ff007223 */
/* 0x001fca0000000021 */
/*0790*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*07a0*/ @P0 BRA P1, 0x800 ; /* 0x0000005000000947 */
/* 0x000fea0000800000 */
/*07b0*/ IMAD.MOV.U32 R23, RZ, RZ, R21 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0015 */
/*07c0*/ MOV R4, 0x800 ; /* 0x0000080000047802 */
/* 0x000fe20000000f00 */
/*07d0*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe400078e0008 */
/*07e0*/ IMAD.MOV.U32 R19, RZ, RZ, R9 ; /* 0x000000ffff137224 */
/* 0x000fe400078e0009 */
/*07f0*/ CALL.REL.NOINC 0xbd0 ; /* 0x000003d000007944 */
/* 0x000fea0003c00000 */
/*0800*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0810*/ F2I.F64 R0, R32 ; /* 0x0000002000007311 */
/* 0x000e220000301100 */
/*0820*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0830*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe20008011404 */
/*0840*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0850*/ BSSY B0, 0xa50 ; /* 0x000001f000007945 */
/* 0x000fe60003800000 */
/*0860*/ IMAD.WIDE.U32 R6, R3.reuse, UR4, R6 ; /* 0x0000000403067c25 */
/* 0x040fe2000f8e0006 */
/*0870*/ MUFU.RCP64H R17, R11 ; /* 0x0000000b00117308 */
/* 0x000e660000001800 */
/*0880*/ IMAD R3, R3, UR5, RZ ; /* 0x0000000503037c24 */
/* 0x000fc8000f8e02ff */
/*0890*/ IMAD.IADD R3, R7, 0x1, R3 ; /* 0x0000000107037824 */
/* 0x000fe400078e0203 */
/*08a0*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x001fc800078e02ff */
/*08b0*/ I2F.F64 R4, R0 ; /* 0x0000000000047312 */
/* 0x000e220000201c00 */
/*08c0*/ DFMA R18, -R10, R16, 1 ; /* 0x3ff000000a12742b */
/* 0x002e4c0000000110 */
/*08d0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x002e4c0000000012 */
/*08e0*/ DFMA R16, R16, R18, R16 ; /* 0x000000121010722b */
/* 0x002e480000000010 */
/*08f0*/ DADD R4, -R4, R8 ; /* 0x0000000004047229 */
/* 0x001e080000000108 */
/*0900*/ DFMA R8, -R10, R16, 1 ; /* 0x3ff000000a08742b */
/* 0x002e480000000110 */
/*0910*/ DMUL R18, R4, -2 ; /* 0xc000000004127828 */
/* 0x001e080000000000 */
/*0920*/ DFMA R4, R16, R8, R16 ; /* 0x000000081004722b */
/* 0x0023e40000000010 */
/*0930*/ IMAD.SHL.U32 R8, R6.reuse, 0x4, RZ ; /* 0x0000000406087824 */
/* 0x042fe200078e00ff */
/*0940*/ SHF.L.U64.HI R9, R6, 0x2, R3 ; /* 0x0000000206097819 */
/* 0x000fe20000010203 */
/*0950*/ DMUL R18, R18, c[0x2][0x0] ; /* 0x0080000012127a28 */
/* 0x001e060000000000 */
/*0960*/ IADD3 R20, P0, R8, c[0x0][0x190], RZ ; /* 0x0000640008147a10 */
/* 0x000fc60007f1e0ff */
/*0970*/ DMUL R32, R4, R18 ; /* 0x0000001204207228 */
/* 0x001e220000000000 */
/*0980*/ IADD3.X R21, R9, c[0x0][0x194], RZ, P0, !PT ; /* 0x0000650009157a10 */
/* 0x000fc600007fe4ff */
/*0990*/ FSETP.GEU.AND P1, PT, |R19|, 6.5827683646048100446e-37, PT ; /* 0x036000001300780b */
/* 0x000fe40003f2e200 */
/*09a0*/ DFMA R16, -R10, R32, R18 ; /* 0x000000200a10722b */
/* 0x001e220000000112 */
/*09b0*/ STG.E [R20.64], R0 ; /* 0x0000000014007986 */
/* 0x0003ea000c101906 */
/*09c0*/ DFMA R32, R4, R16, R32 ; /* 0x000000100420722b */
/* 0x001e140000000020 */
/*09d0*/ FFMA R2, RZ, R11, R33 ; /* 0x0000000bff027223 */
/* 0x001fca0000000021 */
/*09e0*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fda0003f04200 */
/*09f0*/ @P0 BRA P1, 0xa40 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0a00*/ IMAD.MOV.U32 R20, RZ, RZ, R10 ; /* 0x000000ffff147224 */
/* 0x002fe200078e000a */
/*0a10*/ MOV R4, 0xa40 ; /* 0x00000a4000047802 */
/* 0x000fe20000000f00 */
/*0a20*/ IMAD.MOV.U32 R23, RZ, RZ, R11 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000b */
/*0a30*/ CALL.REL.NOINC 0xbd0 ; /* 0x0000019000007944 */
/* 0x000fea0003c00000 */
/*0a40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0a50*/ DMUL R14, R14, c[0x0][0x168] ; /* 0x00005a000e0e7a28 */
/* 0x000e220000000000 */
/*0a60*/ F2F.F32.F64 R33, R32 ; /* 0x0000002000217310 */
/* 0x000e620000301000 */
/*0a70*/ IADD3 R8, P0, R8, c[0x0][0x198], RZ ; /* 0x0000660008087a10 */
/* 0x000fe40007f1e0ff */
/*0a80*/ DMUL R12, R12, c[0x0][0x168] ; /* 0x00005a000c0c7a28 */
/* 0x000ea20000000000 */
/*0a90*/ LEA R2, P1, R6.reuse, c[0x0][0x188], 0x3 ; /* 0x0000620006027a11 */
/* 0x040fe400078218ff */
/*0aa0*/ IADD3.X R9, R9, c[0x0][0x19c], RZ, P0, !PT ; /* 0x0000670009097a10 */
/* 0x000fe400007fe4ff */
/*0ab0*/ F2I.F64.TRUNC R0, R14 ; /* 0x0000000e00007311 */
/* 0x001e22000030d100 */
/*0ac0*/ LEA.HI.X R3, R6, c[0x0][0x18c], R3, 0x3, P1 ; /* 0x0000630006037a11 */
/* 0x000fce00008f1c03 */
/*0ad0*/ F2F.F32.F64 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x004ea20000301000 */
/*0ae0*/ STG.E [R8.64], R33 ; /* 0x0000002108007986 */
/* 0x002fee000c101906 */
/*0af0*/ I2F.F64 R4, R0 ; /* 0x0000000000047312 */
/* 0x001e220000201c00 */
/*0b00*/ FADD R18, R12, R12 ; /* 0x0000000c0c127221 */
/* 0x004fce0000000000 */
/*0b10*/ F2F.F64.F32 R16, R18 ; /* 0x0000001200107310 */
/* 0x000e620000201800 */
/*0b20*/ DADD R4, R14, -R4 ; /* 0x000000000e047229 */
/* 0x001e140000000804 */
/*0b30*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x001e220000301000 */
/*0b40*/ DMUL R16, R16, c[0x2][0x0] ; /* 0x0080000010107a28 */
/* 0x002e540000000000 */
/*0b50*/ F2F.F32.F64 R17, R16 ; /* 0x0000001000117310 */
/* 0x002e620000301000 */
/*0b60*/ FADD R7, R4, R4 ; /* 0x0000000404077221 */
/* 0x001fce0000000000 */
/*0b70*/ F2F.F64.F32 R10, R7 ; /* 0x00000007000a7310 */
/* 0x000e220000201800 */
/*0b80*/ STG.E [R2.64+0x4], R17 ; /* 0x0000041102007986 */
/* 0x002fe2000c101906 */
/*0b90*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e140000000000 */
/*0ba0*/ F2F.F32.F64 R11, R10 ; /* 0x0000000a000b7310 */
/* 0x001e240000301000 */
/*0bb0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x001fe2000c101906 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ FSETP.GEU.AND P2, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x000fe20003f4e200 */
/*0be0*/ IMAD.MOV.U32 R22, RZ, RZ, R20 ; /* 0x000000ffff167224 */
/* 0x000fe200078e0014 */
/*0bf0*/ FSETP.GEU.AND P0, PT, |R23|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000001700780b */
/* 0x040fe20003f0e200 */
/*0c00*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff007424 */
/* 0x000fe200078e00ff */
/*0c10*/ LOP3.LUT R21, R23, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff17157812 */
/* 0x000fe200078ec0ff */
/*0c20*/ IMAD.MOV.U32 R30, RZ, RZ, R18 ; /* 0x000000ffff1e7224 */
/* 0x000fe200078e0012 */
/*0c30*/ LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000013027812 */
/* 0x000fe200078ec0ff */
/*0c40*/ IMAD.MOV.U32 R32, RZ, RZ, 0x1 ; /* 0x00000001ff207424 */
/* 0x000fe200078e00ff */
/*0c50*/ LOP3.LUT R21, R21, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000015157812 */
/* 0x000fe200078efcff */
/*0c60*/ BSSY B1, 0x1160 ; /* 0x000004f000017945 */
/* 0x000fe20003800000 */
/*0c70*/ LOP3.LUT R5, R23, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000017057812 */
/* 0x000fc600078ec0ff */
/*0c80*/ @!P2 LOP3.LUT R25, R23, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001719a812 */
/* 0x000fe200078ec0ff */
/*0c90*/ @!P2 IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff18a224 */
/* 0x000fe200078e00ff */
/*0ca0*/ @!P0 DMUL R20, R22, 8.98846567431157953865e+307 ; /* 0x7fe0000016148828 */
/* 0x000e220000000000 */
/*0cb0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, R5, PT ; /* 0x000000050200720c */
/* 0x040fe40003f26070 */
/*0cc0*/ @!P2 ISETP.GE.U32.AND P3, PT, R2, R25, PT ; /* 0x000000190200a20c */
/* 0x000fe40003f66070 */
/*0cd0*/ SEL R25, R0.reuse, 0x63400000, !P1 ; /* 0x6340000000197807 */
/* 0x040fe20004800000 */
/*0ce0*/ MUFU.RCP64H R33, R21 ; /* 0x0000001500217308 */
/* 0x001e220000001800 */
/*0cf0*/ @!P2 SEL R27, R0, 0x63400000, !P3 ; /* 0x63400000001ba807 */
/* 0x000fe40005800000 */
/*0d00*/ LOP3.LUT R31, R25, 0x800fffff, R19, 0xf8, !PT ; /* 0x800fffff191f7812 */
/* 0x000fc400078ef813 */
/*0d10*/ @!P2 LOP3.LUT R27, R27, 0x80000000, R19, 0xf8, !PT ; /* 0x800000001b1ba812 */
/* 0x000fe400078ef813 */
/*0d20*/ @!P0 LOP3.LUT R5, R21, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000015058812 */
/* 0x000fe400078ec0ff */
/*0d30*/ @!P2 LOP3.LUT R25, R27, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001b19a812 */
/* 0x000fcc00078efcff */
/*0d40*/ @!P2 DFMA R30, R30, 2, -R24 ; /* 0x400000001e1ea82b */
/* 0x000fc80000000818 */
/*0d50*/ DFMA R24, R32, -R20, 1 ; /* 0x3ff000002018742b */
/* 0x001e0c0000000814 */
/*0d60*/ DFMA R24, R24, R24, R24 ; /* 0x000000181818722b */
/* 0x001e0c0000000018 */
/*0d70*/ DFMA R24, R32, R24, R32 ; /* 0x000000182018722b */
/* 0x001e0c0000000020 */
/*0d80*/ DFMA R32, R24, -R20, 1 ; /* 0x3ff000001820742b */
/* 0x001e0c0000000814 */
/*0d90*/ DFMA R32, R24, R32, R24 ; /* 0x000000201820722b */
/* 0x001e0c0000000018 */
/*0da0*/ DMUL R24, R32, R30 ; /* 0x0000001e20187228 */
/* 0x001e0c0000000000 */
/*0db0*/ DFMA R26, R24, -R20, R30 ; /* 0x80000014181a722b */
/* 0x001e0c000000001e */
/*0dc0*/ DFMA R26, R32, R26, R24 ; /* 0x0000001a201a722b */
/* 0x0010640000000018 */
/*0dd0*/ IMAD.MOV.U32 R24, RZ, RZ, R2 ; /* 0x000000ffff187224 */
/* 0x001fe200078e0002 */
/*0de0*/ @!P2 LOP3.LUT R24, R31, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000001f18a812 */
/* 0x000fc800078ec0ff */
/*0df0*/ IADD3 R25, R24, -0x1, RZ ; /* 0xffffffff18197810 */
/* 0x000fc80007ffe0ff */
/*0e00*/ ISETP.GT.U32.AND P0, PT, R25, 0x7feffffe, PT ; /* 0x7feffffe1900780c */
/* 0x000fe40003f04070 */
/*0e10*/ IADD3 R25, R5, -0x1, RZ ; /* 0xffffffff05197810 */
/* 0x000fc80007ffe0ff */
/*0e20*/ ISETP.GT.U32.OR P0, PT, R25, 0x7feffffe, P0 ; /* 0x7feffffe1900780c */
/* 0x000fda0000704470 */
/*0e30*/ @P0 BRA 0x1000 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0e40*/ LOP3.LUT R5, R23, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000017057812 */
/* 0x002fc800078ec0ff */
/*0e50*/ ISETP.GE.U32.AND P0, PT, R2.reuse, R5, PT ; /* 0x000000050200720c */
/* 0x040fe20003f06070 */
/*0e60*/ IMAD.IADD R18, R2, 0x1, -R5 ; /* 0x0000000102127824 */
/* 0x000fc600078e0a05 */
/*0e70*/ SEL R0, R0, 0x63400000, !P0 ; /* 0x6340000000007807 */
/* 0x000fe40004000000 */
/*0e80*/ IMNMX R18, R18, -0x46a00000, !PT ; /* 0xb960000012127817 */
/* 0x000fc80007800200 */
/*0e90*/ IMNMX R5, R18, 0x46a00000, PT ; /* 0x46a0000012057817 */
/* 0x000fe20003800200 */
/*0ea0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc800078e00ff */
/*0eb0*/ IMAD.IADD R0, R5, 0x1, -R0 ; /* 0x0000000105007824 */
/* 0x000fca00078e0a00 */
/*0ec0*/ IADD3 R19, R0, 0x7fe00000, RZ ; /* 0x7fe0000000137810 */
/* 0x000fcc0007ffe0ff */
/*0ed0*/ DMUL R32, R26, R18 ; /* 0x000000121a207228 */
/* 0x000e140000000000 */
/*0ee0*/ FSETP.GTU.AND P0, PT, |R33|, 1.469367938527859385e-39, PT ; /* 0x001000002100780b */
/* 0x001fda0003f0c200 */
/*0ef0*/ @P0 BRA 0x1150 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0f00*/ DFMA R20, R26, -R20, R30 ; /* 0x800000141a14722b */
/* 0x000e0c000000001e */
/*0f10*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x001fc800078e00ff */
/*0f20*/ FSETP.NEU.AND P0, PT, R21.reuse, RZ, PT ; /* 0x000000ff1500720b */
/* 0x040fe40003f0d000 */
/*0f30*/ LOP3.LUT R22, R21, 0x80000000, R23, 0x48, !PT ; /* 0x8000000015167812 */
/* 0x000fc800078e4817 */
/*0f40*/ LOP3.LUT R21, R22, R19, RZ, 0xfc, !PT ; /* 0x0000001316157212 */
/* 0x000fce00078efcff */
/*0f50*/ @!P0 BRA 0x1150 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0f60*/ IMAD.MOV R19, RZ, RZ, -R0 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0a00 */
/*0f70*/ IADD3 R0, -R0, -0x43300000, RZ ; /* 0xbcd0000000007810 */
/* 0x000fe20007ffe1ff */
/*0f80*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fcc00078e00ff */
/*0f90*/ DFMA R18, R32, -R18, R26 ; /* 0x800000122012722b */
/* 0x000e08000000001a */
/*0fa0*/ DMUL.RP R26, R26, R20 ; /* 0x000000141a1a7228 */
/* 0x000e4c0000008000 */
/*0fb0*/ FSETP.NEU.AND P0, PT, |R19|, R0, PT ; /* 0x000000001300720b */
/* 0x001fc80003f0d200 */
/*0fc0*/ LOP3.LUT R5, R27, R22, RZ, 0x3c, !PT ; /* 0x000000161b057212 */
/* 0x002fe400078e3cff */
/*0fd0*/ FSEL R32, R26, R32, !P0 ; /* 0x000000201a207208 */
/* 0x000fe40004000000 */
/*0fe0*/ FSEL R33, R5, R33, !P0 ; /* 0x0000002105217208 */
/* 0x000fe20004000000 */
/*0ff0*/ BRA 0x1150 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*1000*/ DSETP.NAN.AND P0, PT, R18, R18, PT ; /* 0x000000121200722a */
/* 0x002e1c0003f08000 */
/*1010*/ @P0 BRA 0x1130 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*1020*/ DSETP.NAN.AND P0, PT, R22, R22, PT ; /* 0x000000161600722a */
/* 0x000e1c0003f08000 */
/*1030*/ @P0 BRA 0x1100 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*1040*/ ISETP.NE.AND P0, PT, R24, R5, PT ; /* 0x000000051800720c */
/* 0x000fe20003f05270 */
/*1050*/ IMAD.MOV.U32 R32, RZ, RZ, 0x0 ; /* 0x00000000ff207424 */
/* 0x000fe400078e00ff */
/*1060*/ IMAD.MOV.U32 R33, RZ, RZ, -0x80000 ; /* 0xfff80000ff217424 */
/* 0x000fd400078e00ff */
/*1070*/ @!P0 BRA 0x1150 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*1080*/ ISETP.NE.AND P0, PT, R24, 0x7ff00000, PT ; /* 0x7ff000001800780c */
/* 0x000fe40003f05270 */
/*1090*/ LOP3.LUT R33, R19, 0x80000000, R23, 0x48, !PT ; /* 0x8000000013217812 */
/* 0x000fe400078e4817 */
/*10a0*/ ISETP.EQ.OR P0, PT, R5, RZ, !P0 ; /* 0x000000ff0500720c */
/* 0x000fda0004702670 */
/*10b0*/ @P0 LOP3.LUT R0, R33, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000021000812 */
/* 0x000fe200078efcff */
/*10c0*/ @!P0 IMAD.MOV.U32 R32, RZ, RZ, RZ ; /* 0x000000ffff208224 */
/* 0x000fe400078e00ff */
/*10d0*/ @P0 IMAD.MOV.U32 R32, RZ, RZ, RZ ; /* 0x000000ffff200224 */
/* 0x000fe400078e00ff */
/*10e0*/ @P0 IMAD.MOV.U32 R33, RZ, RZ, R0 ; /* 0x000000ffff210224 */
/* 0x000fe200078e0000 */
/*10f0*/ BRA 0x1150 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1100*/ LOP3.LUT R33, R23, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000017217812 */
/* 0x000fe200078efcff */
/*1110*/ IMAD.MOV.U32 R32, RZ, RZ, R22 ; /* 0x000000ffff207224 */
/* 0x000fe200078e0016 */
/*1120*/ BRA 0x1150 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1130*/ LOP3.LUT R33, R19, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000013217812 */
/* 0x000fe200078efcff */
/*1140*/ IMAD.MOV.U32 R32, RZ, RZ, R18 ; /* 0x000000ffff207224 */
/* 0x000fe400078e0012 */
/*1150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*1170*/ RET.REL.NODEC R4 0x0 ; /* 0xffffee8004007950 */
/* 0x000fea0003c3ffff */
/*1180*/ BRA 0x1180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void calculateDelaysAndPhases(double * gpuDelays, double lo, double sampletime, int fftsamples, int fftchannels, int samplegranularity, float * rotationPhaseInfo, int *sampleShifts, float* fractionalSampleDelays)
{
size_t ifft = threadIdx.x + blockIdx.x * blockDim.x;
size_t iant = blockIdx.y;
int numffts = blockDim.x * gridDim.x;
double meandelay, deltadelay, netdelaysamples_f, startphase;
double d0, d1, d2, a, b;
double * interpolator = &(gpuDelays[iant*4]);
double filestartoffset = gpuDelays[iant*4+3];
float fractionaldelay;
int netdelaysamples;
// evaluate the delay for the given FFT of the given antenna
// calculate values at the beginning, middle, and end of this FFT
d0 = interpolator[0]*ifft*ifft + interpolator[1]*ifft + interpolator[2];
d1 = interpolator[0]*(ifft+0.5)*(ifft+0.5) + interpolator[1]*(ifft+0.5) + interpolator[2];
d2 = interpolator[0]*(ifft+1.0)*(ifft+1.0) + interpolator[1]*(ifft+1.0) + interpolator[2];
// use these to calculate a linear interpolator across the FFT, as well as a mean value
a = d2-d0; //this is the delay gradient across this FFT
b = d0 + (d1 - (a*0.5 + d0))/3.0; //this is the delay at the start of the FFT
meandelay = a*0.5 + b; //this is the delay in the middle of the FFT
deltadelay = a / fftsamples; // this is the change in delay per sample across this FFT window
netdelaysamples_f = (meandelay - filestartoffset) / sampletime;
netdelaysamples = __double2int_rn(netdelaysamples_f/samplegranularity) * samplegranularity;
// Save the integer number of sample shifts
sampleShifts[iant*numffts + ifft] = netdelaysamples;
// Save the fractional delay
fractionaldelay = (float)(-(netdelaysamples_f - netdelaysamples)*2*M_PI/fftsamples); // radians per FFT channel
fractionalSampleDelays[iant*numffts + ifft] = fractionaldelay;
// set the fringe rotation phase for the first sample of a given FFT of a given antenna
startphase = b*lo;
rotationPhaseInfo[iant*numffts*2 + ifft*2] = (float)(startphase - int(startphase))*2*M_PI;
rotationPhaseInfo[iant*numffts*2 + ifft*2 + 1] = (float)(deltadelay * lo)*2*M_PI;
} | .file "tmpxft_000e6760_00000000-6_calculateDelaysAndPhases.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_
.type _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_, @function
_Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_, .-_Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_
.globl _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.type _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, @function
_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, .-_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void calculateDelaysAndPhases(double * gpuDelays, double lo, double sampletime, int fftsamples, int fftchannels, int samplegranularity, float * rotationPhaseInfo, int *sampleShifts, float* fractionalSampleDelays)
{
size_t ifft = threadIdx.x + blockIdx.x * blockDim.x;
size_t iant = blockIdx.y;
int numffts = blockDim.x * gridDim.x;
double meandelay, deltadelay, netdelaysamples_f, startphase;
double d0, d1, d2, a, b;
double * interpolator = &(gpuDelays[iant*4]);
double filestartoffset = gpuDelays[iant*4+3];
float fractionaldelay;
int netdelaysamples;
// evaluate the delay for the given FFT of the given antenna
// calculate values at the beginning, middle, and end of this FFT
d0 = interpolator[0]*ifft*ifft + interpolator[1]*ifft + interpolator[2];
d1 = interpolator[0]*(ifft+0.5)*(ifft+0.5) + interpolator[1]*(ifft+0.5) + interpolator[2];
d2 = interpolator[0]*(ifft+1.0)*(ifft+1.0) + interpolator[1]*(ifft+1.0) + interpolator[2];
// use these to calculate a linear interpolator across the FFT, as well as a mean value
a = d2-d0; //this is the delay gradient across this FFT
b = d0 + (d1 - (a*0.5 + d0))/3.0; //this is the delay at the start of the FFT
meandelay = a*0.5 + b; //this is the delay in the middle of the FFT
deltadelay = a / fftsamples; // this is the change in delay per sample across this FFT window
netdelaysamples_f = (meandelay - filestartoffset) / sampletime;
netdelaysamples = __double2int_rn(netdelaysamples_f/samplegranularity) * samplegranularity;
// Save the integer number of sample shifts
sampleShifts[iant*numffts + ifft] = netdelaysamples;
// Save the fractional delay
fractionaldelay = (float)(-(netdelaysamples_f - netdelaysamples)*2*M_PI/fftsamples); // radians per FFT channel
fractionalSampleDelays[iant*numffts + ifft] = fractionaldelay;
// set the fringe rotation phase for the first sample of a given FFT of a given antenna
startphase = b*lo;
rotationPhaseInfo[iant*numffts*2 + ifft*2] = (float)(startphase - int(startphase))*2*M_PI;
rotationPhaseInfo[iant*numffts*2 + ifft*2 + 1] = (float)(deltadelay * lo)*2*M_PI;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calculateDelaysAndPhases(double * gpuDelays, double lo, double sampletime, int fftsamples, int fftchannels, int samplegranularity, float * rotationPhaseInfo, int *sampleShifts, float* fractionalSampleDelays)
{
size_t ifft = threadIdx.x + blockIdx.x * blockDim.x;
size_t iant = blockIdx.y;
int numffts = blockDim.x * gridDim.x;
double meandelay, deltadelay, netdelaysamples_f, startphase;
double d0, d1, d2, a, b;
double * interpolator = &(gpuDelays[iant*4]);
double filestartoffset = gpuDelays[iant*4+3];
float fractionaldelay;
int netdelaysamples;
// evaluate the delay for the given FFT of the given antenna
// calculate values at the beginning, middle, and end of this FFT
d0 = interpolator[0]*ifft*ifft + interpolator[1]*ifft + interpolator[2];
d1 = interpolator[0]*(ifft+0.5)*(ifft+0.5) + interpolator[1]*(ifft+0.5) + interpolator[2];
d2 = interpolator[0]*(ifft+1.0)*(ifft+1.0) + interpolator[1]*(ifft+1.0) + interpolator[2];
// use these to calculate a linear interpolator across the FFT, as well as a mean value
a = d2-d0; //this is the delay gradient across this FFT
b = d0 + (d1 - (a*0.5 + d0))/3.0; //this is the delay at the start of the FFT
meandelay = a*0.5 + b; //this is the delay in the middle of the FFT
deltadelay = a / fftsamples; // this is the change in delay per sample across this FFT window
netdelaysamples_f = (meandelay - filestartoffset) / sampletime;
netdelaysamples = __double2int_rn(netdelaysamples_f/samplegranularity) * samplegranularity;
// Save the integer number of sample shifts
sampleShifts[iant*numffts + ifft] = netdelaysamples;
// Save the fractional delay
fractionaldelay = (float)(-(netdelaysamples_f - netdelaysamples)*2*M_PI/fftsamples); // radians per FFT channel
fractionalSampleDelays[iant*numffts + ifft] = fractionaldelay;
// set the fringe rotation phase for the first sample of a given FFT of a given antenna
startphase = b*lo;
rotationPhaseInfo[iant*numffts*2 + ifft*2] = (float)(startphase - int(startphase))*2*M_PI;
rotationPhaseInfo[iant*numffts*2 + ifft*2 + 1] = (float)(deltadelay * lo)*2*M_PI;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calculateDelaysAndPhases(double * gpuDelays, double lo, double sampletime, int fftsamples, int fftchannels, int samplegranularity, float * rotationPhaseInfo, int *sampleShifts, float* fractionalSampleDelays)
{
size_t ifft = threadIdx.x + blockIdx.x * blockDim.x;
size_t iant = blockIdx.y;
int numffts = blockDim.x * gridDim.x;
double meandelay, deltadelay, netdelaysamples_f, startphase;
double d0, d1, d2, a, b;
double * interpolator = &(gpuDelays[iant*4]);
double filestartoffset = gpuDelays[iant*4+3];
float fractionaldelay;
int netdelaysamples;
// evaluate the delay for the given FFT of the given antenna
// calculate values at the beginning, middle, and end of this FFT
d0 = interpolator[0]*ifft*ifft + interpolator[1]*ifft + interpolator[2];
d1 = interpolator[0]*(ifft+0.5)*(ifft+0.5) + interpolator[1]*(ifft+0.5) + interpolator[2];
d2 = interpolator[0]*(ifft+1.0)*(ifft+1.0) + interpolator[1]*(ifft+1.0) + interpolator[2];
// use these to calculate a linear interpolator across the FFT, as well as a mean value
a = d2-d0; //this is the delay gradient across this FFT
b = d0 + (d1 - (a*0.5 + d0))/3.0; //this is the delay at the start of the FFT
meandelay = a*0.5 + b; //this is the delay in the middle of the FFT
deltadelay = a / fftsamples; // this is the change in delay per sample across this FFT window
netdelaysamples_f = (meandelay - filestartoffset) / sampletime;
netdelaysamples = __double2int_rn(netdelaysamples_f/samplegranularity) * samplegranularity;
// Save the integer number of sample shifts
sampleShifts[iant*numffts + ifft] = netdelaysamples;
// Save the fractional delay
fractionaldelay = (float)(-(netdelaysamples_f - netdelaysamples)*2*M_PI/fftsamples); // radians per FFT channel
fractionalSampleDelays[iant*numffts + ifft] = fractionaldelay;
// set the fringe rotation phase for the first sample of a given FFT of a given antenna
startphase = b*lo;
rotationPhaseInfo[iant*numffts*2 + ifft*2] = (float)(startphase - int(startphase))*2*M_PI;
rotationPhaseInfo[iant*numffts*2 + ifft*2 + 1] = (float)(deltadelay * lo)*2*M_PI;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.globl _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.p2align 8
.type _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_,@function
_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_:
s_load_b32 s2, s[0:1], 0x4c
s_mov_b32 s16, s15
s_mov_b32 s17, 0
s_load_b64 s[18:19], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s2, 0xffff
s_lshl_b64 s[2:3], s[16:17], 5
v_mad_u64_u32 v[1:2], null, s14, s20, v[0:1]
s_load_b128 s[12:15], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_f64_u32_e32 v[2:3], v1
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s12, s2
s_addc_u32 s3, s13, s3
s_load_b256 s[4:11], s[2:3], 0x0
v_add_f64 v[4:5], v[2:3], 1.0
s_waitcnt lgkmcnt(0)
v_mul_f64 v[6:7], s[4:5], v[2:3]
v_add_f64 v[10:11], v[2:3], 0.5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[8:9], s[4:5], v[4:5]
v_mul_f64 v[6:7], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[12:13], s[4:5], v[10:11]
v_mul_f64 v[8:9], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[2:3], s[6:7], v[2:3], v[6:7]
v_mul_f64 v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[4:5], s[6:7], v[4:5], v[8:9]
v_add_f64 v[2:3], s[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], s[6:7], v[10:11], v[6:7]
v_add_f64 v[4:5], s[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_2)
v_add_f64 v[6:7], s[8:9], v[6:7]
s_clause 0x4
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b64 s[8:9], s[0:1], 0x38
s_load_b32 s0, s[0:1], 0x40
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], -v[2:3]
v_fma_f64 v[8:9], v[4:5], 0.5, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[8:9]
v_div_scale_f64 v[8:9], null, 0x40080000, 0x40080000, v[6:7]
v_div_scale_f64 v[14:15], vcc_lo, v[6:7], 0x40080000, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_div_fixup_f64 v[6:7], v[8:9], 0x40080000, v[6:7]
v_cvt_f64_i32_e32 v[8:9], s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[2:3], v[6:7]
v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], v[4:5]
v_div_scale_f64 v[22:23], vcc_lo, v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[6:7], v[4:5], 0.5, v[2:3]
v_rcp_f64_e32 v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], -s[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_div_scale_f64 v[12:13], null, s[18:19], s[18:19], v[6:7]
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[16:17], v[12:13]
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[6:7], s[18:19], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
v_cvt_f64_i32_e32 v[14:15], s3
s_mov_b32 s2, 0x54442d18
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[4:5], v[10:11], v[8:9], v[4:5]
v_div_fixup_f64 v[6:7], v[12:13], s[18:19], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[4:5], s[14:15]
v_div_scale_f64 v[12:13], null, v[14:15], v[14:15], v[6:7]
v_div_scale_f64 v[20:21], vcc_lo, v[6:7], v[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], -v[12:13], v[16:17], 1.0
v_fma_f64 v[16:17], v[16:17], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[20:21], v[16:17]
v_fma_f64 v[12:13], -v[12:13], v[18:19], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[18:19]
v_mul_f64 v[18:19], v[2:3], s[14:15]
v_div_fixup_f64 v[12:13], v[12:13], v[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[12:13], v[12:13]
v_cvt_i32_f64_e32 v0, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v20, v0, s3
s_mov_b32 s3, 0x400921fb
v_cvt_i32_f64_e32 v0, v[18:19]
v_cvt_f64_i32_e32 v[12:13], v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[10:11], v0
v_cvt_f32_f64_e32 v0, v[4:5]
v_add_f64 v[6:7], v[6:7], -v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[2:3], v[2:3], s[14:15], -v[10:11]
v_add_f32_e32 v0, v0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[6:7], v[6:7], -2.0
v_cvt_f32_f64_e32 v4, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], s[2:3]
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[6:7]
v_div_scale_f64 v[18:19], vcc_lo, v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[14:15], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[18:19], v[14:15]
v_fma_f64 v[2:3], -v[12:13], v[10:11], v[18:19]
v_add_f32_e32 v12, v4, v4
v_cvt_f64_f32_e32 v[4:5], v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[2:3], v[2:3], v[14:15], v[10:11]
v_cvt_f64_f32_e32 v[10:11], v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[4:5], v[4:5], s[2:3]
v_div_fixup_f64 v[6:7], v[2:3], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[10:11], s[2:3]
v_mov_b32_e32 v2, 0
v_mad_u64_u32 v[10:11], null, s0, s16, v[1:2]
v_cvt_f32_f64_e32 v2, v[4:5]
s_ashr_i32 s0, s0, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v11
v_cvt_f32_f64_e32 v12, v[6:7]
v_cvt_f32_f64_e32 v1, v[8:9]
v_mad_u64_u32 v[3:4], null, s0, s16, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v11, v3
v_lshlrev_b64 v[3:4], 2, v[10:11]
v_lshlrev_b64 v[5:6], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_store_b32 v[7:8], v20, off
global_store_b32 v[3:4], v12, off
global_store_b64 v[5:6], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, .Lfunc_end0-_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void calculateDelaysAndPhases(double * gpuDelays, double lo, double sampletime, int fftsamples, int fftchannels, int samplegranularity, float * rotationPhaseInfo, int *sampleShifts, float* fractionalSampleDelays)
{
size_t ifft = threadIdx.x + blockIdx.x * blockDim.x;
size_t iant = blockIdx.y;
int numffts = blockDim.x * gridDim.x;
double meandelay, deltadelay, netdelaysamples_f, startphase;
double d0, d1, d2, a, b;
double * interpolator = &(gpuDelays[iant*4]);
double filestartoffset = gpuDelays[iant*4+3];
float fractionaldelay;
int netdelaysamples;
// evaluate the delay for the given FFT of the given antenna
// calculate values at the beginning, middle, and end of this FFT
d0 = interpolator[0]*ifft*ifft + interpolator[1]*ifft + interpolator[2];
d1 = interpolator[0]*(ifft+0.5)*(ifft+0.5) + interpolator[1]*(ifft+0.5) + interpolator[2];
d2 = interpolator[0]*(ifft+1.0)*(ifft+1.0) + interpolator[1]*(ifft+1.0) + interpolator[2];
// use these to calculate a linear interpolator across the FFT, as well as a mean value
a = d2-d0; //this is the delay gradient across this FFT
b = d0 + (d1 - (a*0.5 + d0))/3.0; //this is the delay at the start of the FFT
meandelay = a*0.5 + b; //this is the delay in the middle of the FFT
deltadelay = a / fftsamples; // this is the change in delay per sample across this FFT window
netdelaysamples_f = (meandelay - filestartoffset) / sampletime;
netdelaysamples = __double2int_rn(netdelaysamples_f/samplegranularity) * samplegranularity;
// Save the integer number of sample shifts
sampleShifts[iant*numffts + ifft] = netdelaysamples;
// Save the fractional delay
fractionaldelay = (float)(-(netdelaysamples_f - netdelaysamples)*2*M_PI/fftsamples); // radians per FFT channel
fractionalSampleDelays[iant*numffts + ifft] = fractionaldelay;
// set the fringe rotation phase for the first sample of a given FFT of a given antenna
startphase = b*lo;
rotationPhaseInfo[iant*numffts*2 + ifft*2] = (float)(startphase - int(startphase))*2*M_PI;
rotationPhaseInfo[iant*numffts*2 + ifft*2 + 1] = (float)(deltadelay * lo)*2*M_PI;
} | .text
.file "calculateDelaysAndPhases.hip"
.globl _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_ # -- Begin function _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.p2align 4, 0x90
.type _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_,@function
_Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_: # @_Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movsd %xmm0, 96(%rsp)
movsd %xmm1, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rax
movq %rax, 168(%rsp)
leaq 192(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_, .Lfunc_end0-_Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_,@object # @_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.section .rodata,"a",@progbits
.globl _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.p2align 3, 0x0
_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_:
.quad _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.size _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e6760_00000000-6_calculateDelaysAndPhases.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_
.type _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_, @function
_Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
movsd %xmm1, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_, .-_Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_
.globl _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.type _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, @function
_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z56__device_stub__Z24calculateDelaysAndPhasesPdddiiiPfPiS0_PdddiiiPfPiS0_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, .-_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "calculateDelaysAndPhases.hip"
.globl _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_ # -- Begin function _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.p2align 4, 0x90
.type _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_,@function
_Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_: # @_Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movsd %xmm0, 96(%rsp)
movsd %xmm1, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rax
movq %rax, 168(%rsp)
leaq 192(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_, .Lfunc_end0-_Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_,@object # @_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.section .rodata,"a",@progbits
.globl _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.p2align 3, 0x0
_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_:
.quad _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.size _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24calculateDelaysAndPhasesPdddiiiPfPiS0_"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__calculateDelaysAndPhasesPdddiiiPfPiS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24calculateDelaysAndPhasesPdddiiiPfPiS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <numeric>
#include <iostream>
#define MYDEVICE 0
#define NUM_BINS 4096
__global__ void computeHistogram(int *input, unsigned int *histogram, int dim)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if(index < dim){
int number = input[index];
atomicAdd(&histogram[number], 1);
if(histogram[number] > 127)
histogram[number] = 127;
}
}
int main(void){
// create array of input elements
const int num_elements = 1 << 19;
srand(time(NULL));
// generate random input on the host
std::vector<int> h_input;
for(int i = 0; i < num_elements; i++)
h_input.push_back(rand() % NUM_BINS);
int inputSize = num_elements * sizeof(int);
int *d_input = 0;
cudaMalloc(&d_input, inputSize);
cudaMemcpy(d_input, &h_input[0], inputSize, cudaMemcpyHostToDevice);
int histSize = NUM_BINS * sizeof(unsigned int);
unsigned int *h_hist = 0;
unsigned int *d_hist = 0;
cudaMallocHost(&h_hist, histSize);
cudaMalloc(&d_hist, histSize);
int block_size = 1024;
int num_blocks = (num_elements + block_size - 1)/block_size;
computeHistogram<<<num_blocks, block_size>>>(d_input, d_hist, num_elements);
cudaMemcpy(h_hist, d_hist, histSize, cudaMemcpyHostToDevice);
for (int i = 0; i < NUM_BINS; i++)
std::cout << "Bin: " << i << " Elements: " << h_hist[i] << '\n';
cudaFree(d_input);
cudaFree(h_hist);
cudaFree(d_hist);
return 0;
} | code for sm_80
Function : _Z16computeHistogramPiPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x004fcc00078e0205 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, 0x80, PT ; /* 0x000000800000780c */
/* 0x004fda0003f06070 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ MOV R3, 0x7f ; /* 0x0000007f00037802 */
/* 0x001fca0000000f00 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <numeric>
#include <iostream>
#define MYDEVICE 0
#define NUM_BINS 4096
__global__ void computeHistogram(int *input, unsigned int *histogram, int dim)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if(index < dim){
int number = input[index];
atomicAdd(&histogram[number], 1);
if(histogram[number] > 127)
histogram[number] = 127;
}
}
int main(void){
// create array of input elements
const int num_elements = 1 << 19;
srand(time(NULL));
// generate random input on the host
std::vector<int> h_input;
for(int i = 0; i < num_elements; i++)
h_input.push_back(rand() % NUM_BINS);
int inputSize = num_elements * sizeof(int);
int *d_input = 0;
cudaMalloc(&d_input, inputSize);
cudaMemcpy(d_input, &h_input[0], inputSize, cudaMemcpyHostToDevice);
int histSize = NUM_BINS * sizeof(unsigned int);
unsigned int *h_hist = 0;
unsigned int *d_hist = 0;
cudaMallocHost(&h_hist, histSize);
cudaMalloc(&d_hist, histSize);
int block_size = 1024;
int num_blocks = (num_elements + block_size - 1)/block_size;
computeHistogram<<<num_blocks, block_size>>>(d_input, d_hist, num_elements);
cudaMemcpy(h_hist, d_hist, histSize, cudaMemcpyHostToDevice);
for (int i = 0; i < NUM_BINS; i++)
std::cout << "Bin: " << i << " Elements: " << h_hist[i] << '\n';
cudaFree(d_input);
cudaFree(h_hist);
cudaFree(d_hist);
return 0;
} | .file "tmpxft_00039c54_00000000-6_histogram.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16computeHistogramPiPjiPiPji
.type _Z39__device_stub__Z16computeHistogramPiPjiPiPji, @function
_Z39__device_stub__Z16computeHistogramPiPjiPiPji:
.LFB4106:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16computeHistogramPiPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4106:
.size _Z39__device_stub__Z16computeHistogramPiPjiPiPji, .-_Z39__device_stub__Z16computeHistogramPiPjiPiPji
.globl _Z16computeHistogramPiPji
.type _Z16computeHistogramPiPji, @function
_Z16computeHistogramPiPji:
.LFB4107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16computeHistogramPiPjiPiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4107:
.size _Z16computeHistogramPiPji, .-_Z16computeHistogramPiPji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16computeHistogramPiPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16computeHistogramPiPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4419:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4419:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC1:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4681:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L36
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L22
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L23
jmp .L30
.L36:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L37:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L25
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L29
.L22:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L30:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L23:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L37
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L27
.L25:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L27:
addq %rbp, %r15
testq %r13, %r13
je .L28
movq 16(%rbx), %rsi
subq %r13, %rsi
.L29:
movq %r13, %rdi
call _ZdlPvm@PLT
.L28:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4681:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .rodata.str1.1
.LC2:
.string "Bin: "
.LC3:
.string " Elements: "
.text
.globl main
.type main, @function
main:
.LFB4071:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4071
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $524288, %ebx
leaq 36(%rsp), %rbp
jmp .L41
.L39:
leaq 48(%rsp), %rdi
movq %rbp, %rdx
.LEHB0:
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.L40:
subl $1, %ebx
je .L54
.L41:
call rand@PLT
cltd
shrl $20, %edx
addl %edx, %eax
andl $4095, %eax
subl %edx, %eax
movl %eax, 36(%rsp)
movq 56(%rsp), %rsi
cmpq 64(%rsp), %rsi
je .L39
movl %eax, (%rsi)
addq $4, %rsi
movq %rsi, 56(%rsp)
jmp .L40
.L54:
movq $0, (%rsp)
movq %rsp, %rdi
movl $2097152, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2097152, %edx
movq 48(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $0, %edx
movl $16384, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $512, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movl $524288, %edx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z16computeHistogramPiPjiPiPji
.L42:
movl $1, %ecx
movl $16384, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
leaq _ZSt4cout(%rip), %rbp
leaq .LC3(%rip), %r13
leaq 36(%rsp), %r14
jmp .L45
.L56:
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %r15
movl $11, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movb $10, 36(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L43
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L44
.L43:
movl $10, %esi
call _ZNSo3putEc@PLT
.L44:
addq $1, %rbx
cmpq $4096, %rbx
je .L55
.L45:
movl $5, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L56
.L55:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE0:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4071:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4071:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4071-.LLSDACSB4071
.LLSDACSB4071:
.uleb128 .LEHB0-.LFB4071
.uleb128 .LEHE0-.LEHB0
.uleb128 .L49-.LFB4071
.uleb128 0
.uleb128 .LEHB1-.LFB4071
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4071:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <numeric>
#include <iostream>
#define MYDEVICE 0
#define NUM_BINS 4096
__global__ void computeHistogram(int *input, unsigned int *histogram, int dim)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if(index < dim){
int number = input[index];
atomicAdd(&histogram[number], 1);
if(histogram[number] > 127)
histogram[number] = 127;
}
}
int main(void){
// create array of input elements
const int num_elements = 1 << 19;
srand(time(NULL));
// generate random input on the host
std::vector<int> h_input;
for(int i = 0; i < num_elements; i++)
h_input.push_back(rand() % NUM_BINS);
int inputSize = num_elements * sizeof(int);
int *d_input = 0;
cudaMalloc(&d_input, inputSize);
cudaMemcpy(d_input, &h_input[0], inputSize, cudaMemcpyHostToDevice);
int histSize = NUM_BINS * sizeof(unsigned int);
unsigned int *h_hist = 0;
unsigned int *d_hist = 0;
cudaMallocHost(&h_hist, histSize);
cudaMalloc(&d_hist, histSize);
int block_size = 1024;
int num_blocks = (num_elements + block_size - 1)/block_size;
computeHistogram<<<num_blocks, block_size>>>(d_input, d_hist, num_elements);
cudaMemcpy(h_hist, d_hist, histSize, cudaMemcpyHostToDevice);
for (int i = 0; i < NUM_BINS; i++)
std::cout << "Bin: " << i << " Elements: " << h_hist[i] << '\n';
cudaFree(d_input);
cudaFree(h_hist);
cudaFree(d_hist);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <numeric>
#include <iostream>
#define MYDEVICE 0
#define NUM_BINS 4096
__global__ void computeHistogram(int *input, unsigned int *histogram, int dim)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if(index < dim){
int number = input[index];
atomicAdd(&histogram[number], 1);
if(histogram[number] > 127)
histogram[number] = 127;
}
}
int main(void){
// create array of input elements
const int num_elements = 1 << 19;
srand(time(NULL));
// generate random input on the host
std::vector<int> h_input;
for(int i = 0; i < num_elements; i++)
h_input.push_back(rand() % NUM_BINS);
int inputSize = num_elements * sizeof(int);
int *d_input = 0;
hipMalloc(&d_input, inputSize);
hipMemcpy(d_input, &h_input[0], inputSize, hipMemcpyHostToDevice);
int histSize = NUM_BINS * sizeof(unsigned int);
unsigned int *h_hist = 0;
unsigned int *d_hist = 0;
hipHostMalloc(&h_hist, histSize, hipHostMallocDefault);
hipMalloc(&d_hist, histSize);
int block_size = 1024;
int num_blocks = (num_elements + block_size - 1)/block_size;
computeHistogram<<<num_blocks, block_size>>>(d_input, d_hist, num_elements);
hipMemcpy(h_hist, d_hist, histSize, hipMemcpyHostToDevice);
for (int i = 0; i < NUM_BINS; i++)
std::cout << "Bin: " << i << " Elements: " << h_hist[i] << '\n';
hipFree(d_input);
hipFree(h_hist);
hipFree(d_hist);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <numeric>
#include <iostream>
#define MYDEVICE 0
#define NUM_BINS 4096
__global__ void computeHistogram(int *input, unsigned int *histogram, int dim)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if(index < dim){
int number = input[index];
atomicAdd(&histogram[number], 1);
if(histogram[number] > 127)
histogram[number] = 127;
}
}
int main(void){
// create array of input elements
const int num_elements = 1 << 19;
srand(time(NULL));
// generate random input on the host
std::vector<int> h_input;
for(int i = 0; i < num_elements; i++)
h_input.push_back(rand() % NUM_BINS);
int inputSize = num_elements * sizeof(int);
int *d_input = 0;
hipMalloc(&d_input, inputSize);
hipMemcpy(d_input, &h_input[0], inputSize, hipMemcpyHostToDevice);
int histSize = NUM_BINS * sizeof(unsigned int);
unsigned int *h_hist = 0;
unsigned int *d_hist = 0;
hipHostMalloc(&h_hist, histSize, hipHostMallocDefault);
hipMalloc(&d_hist, histSize);
int block_size = 1024;
int num_blocks = (num_elements + block_size - 1)/block_size;
computeHistogram<<<num_blocks, block_size>>>(d_input, d_hist, num_elements);
hipMemcpy(h_hist, d_hist, histSize, hipMemcpyHostToDevice);
for (int i = 0; i < NUM_BINS; i++)
std::cout << "Bin: " << i << " Elements: " << h_hist[i] << '\n';
hipFree(d_input);
hipFree(h_hist);
hipFree(d_hist);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16computeHistogramPiPji
.globl _Z16computeHistogramPiPji
.p2align 8
.type _Z16computeHistogramPiPji,@function
_Z16computeHistogramPiPji:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, 0x7f, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0x7f
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16computeHistogramPiPji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16computeHistogramPiPji, .Lfunc_end0-_Z16computeHistogramPiPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16computeHistogramPiPji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16computeHistogramPiPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <vector>
#include <numeric>
#include <iostream>
#define MYDEVICE 0
#define NUM_BINS 4096
__global__ void computeHistogram(int *input, unsigned int *histogram, int dim)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
if(index < dim){
int number = input[index];
atomicAdd(&histogram[number], 1);
if(histogram[number] > 127)
histogram[number] = 127;
}
}
int main(void){
// create array of input elements
const int num_elements = 1 << 19;
srand(time(NULL));
// generate random input on the host
std::vector<int> h_input;
for(int i = 0; i < num_elements; i++)
h_input.push_back(rand() % NUM_BINS);
int inputSize = num_elements * sizeof(int);
int *d_input = 0;
hipMalloc(&d_input, inputSize);
hipMemcpy(d_input, &h_input[0], inputSize, hipMemcpyHostToDevice);
int histSize = NUM_BINS * sizeof(unsigned int);
unsigned int *h_hist = 0;
unsigned int *d_hist = 0;
hipHostMalloc(&h_hist, histSize, hipHostMallocDefault);
hipMalloc(&d_hist, histSize);
int block_size = 1024;
int num_blocks = (num_elements + block_size - 1)/block_size;
computeHistogram<<<num_blocks, block_size>>>(d_input, d_hist, num_elements);
hipMemcpy(h_hist, d_hist, histSize, hipMemcpyHostToDevice);
for (int i = 0; i < NUM_BINS; i++)
std::cout << "Bin: " << i << " Elements: " << h_hist[i] << '\n';
hipFree(d_input);
hipFree(h_hist);
hipFree(d_hist);
return 0;
} | .text
.file "histogram.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__computeHistogramPiPji # -- Begin function _Z31__device_stub__computeHistogramPiPji
.p2align 4, 0x90
.type _Z31__device_stub__computeHistogramPiPji,@function
_Z31__device_stub__computeHistogramPiPji: # @_Z31__device_stub__computeHistogramPiPji
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16computeHistogramPiPji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__computeHistogramPiPji, .Lfunc_end0-_Z31__device_stub__computeHistogramPiPji
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
xorl %ebx, %ebx
xorl %edi, %edi
callq time
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq srand
movl $524288, %ebp # imm = 0x80000
movabsq $2305843009213693951, %r12 # imm = 0x1FFFFFFFFFFFFFFF
xorl %r14d, %r14d
xorl %r13d, %r13d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_2: # in Loop: Header=BB1_1 Depth=1
movl %r15d, (%r14)
.LBB1_19: # %_ZNSt6vectorIiSaIiEE9push_backEOi.exit
# in Loop: Header=BB1_1 Depth=1
addq $4, %r14
decl %ebp
je .LBB1_20
.LBB1_1: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %r15d
leal 4095(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
andl $-4096, %eax # imm = 0xF000
subl %eax, %r15d
cmpq %r13, %r14
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movq %rbx, 32(%rsp) # 8-byte Spill
subq %rbx, %r14
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r14
je .LBB1_4
# %bb.6: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r14, %rbx
sarq $2, %rbx
cmpq $1, %rbx
movq %rbx, %rax
adcq $0, %rax
leaq (%rax,%rbx), %rcx
cmpq %r12, %rcx
jb .LBB1_8
# %bb.7: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r12, %rcx
.LBB1_8: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r12, %r13
addq %rbx, %rax
jb .LBB1_10
# %bb.9: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %rcx, %r13
.LBB1_10: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %r13, %r13
je .LBB1_11
# %bb.12: # in Loop: Header=BB1_1 Depth=1
leaq (,%r13,4), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movq %rax, %r12
jmp .LBB1_14
.LBB1_11: # in Loop: Header=BB1_1 Depth=1
xorl %r12d, %r12d
.LBB1_14: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movl %r15d, (%r12,%rbx,4)
testq %r14, %r14
movq 32(%rsp), %rbx # 8-byte Reload
jle .LBB1_16
# %bb.15: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB1_16: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %rbx, %rbx
je .LBB1_18
# %bb.17: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_18: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
addq %r12, %r14
leaq (%r12,%r13,4), %r13
movq %r12, %rbx
movabsq $2305843009213693951, %r12 # imm = 0x1FFFFFFFFFFFFFFF
jmp .LBB1_19
.LBB1_20:
movq $0, 24(%rsp)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
.Ltmp4:
# %bb.21: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 24(%rsp), %rdi
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $2097152, %edx # imm = 0x200000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp6:
# %bb.22:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
xorl %edx, %edx
callq hipHostMalloc
.Ltmp9:
# %bb.23: # %_ZL13hipHostMallocIjE10hipError_tPPT_mj.exit
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp11:
# %bb.24: # %_ZL9hipMallocIjE10hipError_tPPT_m.exit
.Ltmp13:
.cfi_escape 0x2e, 0x00
movabsq $4294967808, %rdi # imm = 0x100000200
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp14:
# %bb.25:
testl %eax, %eax
jne .LBB1_28
# %bb.26:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl $524288, 44(%rsp) # imm = 0x80000
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp16:
# %bb.27: # %.noexc33
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
.Ltmp17:
.cfi_escape 0x2e, 0x10
leaq 48(%rsp), %r9
movl $_Z16computeHistogramPiPji, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp18:
.LBB1_28:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
.Ltmp19:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movl $1, %ecx
callq hipMemcpy
.Ltmp20:
# %bb.29: # %.preheader.preheader
xorl %r14d, %r14d
leaq 48(%rsp), %r15
jmp .LBB1_30
.p2align 4, 0x90
.LBB1_41: # in Loop: Header=BB1_30 Depth=1
.Ltmp31:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp32:
.LBB1_42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_30 Depth=1
incq %r14
cmpq $4096, %r14 # imm = 0x1000
je .LBB1_43
.LBB1_30: # %.preheader
# =>This Inner Loop Header: Depth=1
.Ltmp21:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp22:
# %bb.31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_30 Depth=1
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp24:
# %bb.32: # in Loop: Header=BB1_30 Depth=1
.Ltmp25:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp26:
# %bb.33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit37
# in Loop: Header=BB1_30 Depth=1
movq 16(%rsp), %rax
movl (%rax,%r14,4), %esi
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp28:
# %bb.34: # %_ZNSolsEj.exit
# in Loop: Header=BB1_30 Depth=1
movb $10, 48(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_41
# %bb.35: # in Loop: Header=BB1_30 Depth=1
.Ltmp29:
.cfi_escape 0x2e, 0x00
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp30:
jmp .LBB1_42
.LBB1_43:
movq 24(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.44:
movq 16(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp37:
# %bb.45:
movq 8(%rsp), %rdi
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp39:
# %bb.46:
testq %rbx, %rbx
je .LBB1_48
# %bb.47:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_48: # %_ZNSt6vectorIiSaIiEED2Ev.exit
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 192
.Ltmp41:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp42:
# %bb.5: # %.noexc
.LBB1_49:
.Ltmp12:
jmp .LBB1_50
.LBB1_39:
.Ltmp7:
jmp .LBB1_50
.LBB1_40:
.Ltmp40:
jmp .LBB1_50
.LBB1_36: # %.loopexit
.Ltmp2:
jmp .LBB1_37
.LBB1_38: # %.loopexit.split-lp
.Ltmp43:
.LBB1_37:
movq %rax, %r14
movq 32(%rsp), %rbx # 8-byte Reload
jmp .LBB1_51
.LBB1_54:
.Ltmp33:
.LBB1_50:
movq %rax, %r14
.LBB1_51:
testq %rbx, %rbx
je .LBB1_53
# %bb.52:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_53: # %_ZNSt6vectorIiSaIiEED2Ev.exit42
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp8 # Call between .Ltmp8 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp20-.Ltmp13 # Call between .Ltmp13 and .Ltmp20
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp31 # Call between .Ltmp31 and .Ltmp30
.uleb128 .Ltmp33-.Lfunc_begin0 # jumps to .Ltmp33
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp39-.Ltmp34 # Call between .Ltmp34 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp42 # Call between .Ltmp42 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16computeHistogramPiPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16computeHistogramPiPji,@object # @_Z16computeHistogramPiPji
.section .rodata,"a",@progbits
.globl _Z16computeHistogramPiPji
.p2align 3, 0x0
_Z16computeHistogramPiPji:
.quad _Z31__device_stub__computeHistogramPiPji
.size _Z16computeHistogramPiPji, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Bin: "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Elements: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "vector::_M_realloc_insert"
.size .L.str.2, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16computeHistogramPiPji"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__computeHistogramPiPji
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z16computeHistogramPiPji
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16computeHistogramPiPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.WIDE R4, R2, R5, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x004fcc00078e0205 */
/*00c0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, 0x80, PT ; /* 0x000000800000780c */
/* 0x004fda0003f06070 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ MOV R3, 0x7f ; /* 0x0000007f00037802 */
/* 0x001fca0000000f00 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16computeHistogramPiPji
.globl _Z16computeHistogramPiPji
.p2align 8
.type _Z16computeHistogramPiPji,@function
_Z16computeHistogramPiPji:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_lt_u32_e32 vcc_lo, 0x7f, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0x7f
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16computeHistogramPiPji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16computeHistogramPiPji, .Lfunc_end0-_Z16computeHistogramPiPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16computeHistogramPiPji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16computeHistogramPiPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00039c54_00000000-6_histogram.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16computeHistogramPiPjiPiPji
.type _Z39__device_stub__Z16computeHistogramPiPjiPiPji, @function
_Z39__device_stub__Z16computeHistogramPiPjiPiPji:
.LFB4106:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16computeHistogramPiPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4106:
.size _Z39__device_stub__Z16computeHistogramPiPjiPiPji, .-_Z39__device_stub__Z16computeHistogramPiPjiPiPji
.globl _Z16computeHistogramPiPji
.type _Z16computeHistogramPiPji, @function
_Z16computeHistogramPiPji:
.LFB4107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16computeHistogramPiPjiPiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4107:
.size _Z16computeHistogramPiPji, .-_Z16computeHistogramPiPji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16computeHistogramPiPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16computeHistogramPiPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4419:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4419:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC1:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4681:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L36
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L22
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L23
jmp .L30
.L36:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L37:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L25
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L29
.L22:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L30:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L23:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L37
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L27
.L25:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L27:
addq %rbp, %r15
testq %r13, %r13
je .L28
movq 16(%rbx), %rsi
subq %r13, %rsi
.L29:
movq %r13, %rdi
call _ZdlPvm@PLT
.L28:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4681:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .rodata.str1.1
.LC2:
.string "Bin: "
.LC3:
.string " Elements: "
.text
.globl main
.type main, @function
main:
.LFB4071:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4071
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $524288, %ebx
leaq 36(%rsp), %rbp
jmp .L41
.L39:
leaq 48(%rsp), %rdi
movq %rbp, %rdx
.LEHB0:
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.L40:
subl $1, %ebx
je .L54
.L41:
call rand@PLT
cltd
shrl $20, %edx
addl %edx, %eax
andl $4095, %eax
subl %edx, %eax
movl %eax, 36(%rsp)
movq 56(%rsp), %rsi
cmpq 64(%rsp), %rsi
je .L39
movl %eax, (%rsi)
addq $4, %rsi
movq %rsi, 56(%rsp)
jmp .L40
.L54:
movq $0, (%rsp)
movq %rsp, %rdi
movl $2097152, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2097152, %edx
movq 48(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $0, %edx
movl $16384, %esi
call cudaHostAlloc@PLT
leaq 16(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $512, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L42
movl $524288, %edx
movq 16(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z16computeHistogramPiPjiPiPji
.L42:
movl $1, %ecx
movl $16384, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %r12
leaq _ZSt4cout(%rip), %rbp
leaq .LC3(%rip), %r13
leaq 36(%rsp), %r14
jmp .L45
.L56:
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %r15
movl $11, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movb $10, 36(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L43
movl $1, %edx
movq %r14, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L44
.L43:
movl $10, %esi
call _ZNSo3putEc@PLT
.L44:
addq $1, %rbx
cmpq $4096, %rbx
je .L55
.L45:
movl $5, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L56
.L55:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE0:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L47
call __stack_chk_fail@PLT
.L47:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4071:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4071:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4071-.LLSDACSB4071
.LLSDACSB4071:
.uleb128 .LEHB0-.LFB4071
.uleb128 .LEHE0-.LEHB0
.uleb128 .L49-.LFB4071
.uleb128 0
.uleb128 .LEHB1-.LFB4071
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4071:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histogram.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__computeHistogramPiPji # -- Begin function _Z31__device_stub__computeHistogramPiPji
.p2align 4, 0x90
.type _Z31__device_stub__computeHistogramPiPji,@function
_Z31__device_stub__computeHistogramPiPji: # @_Z31__device_stub__computeHistogramPiPji
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16computeHistogramPiPji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__computeHistogramPiPji, .Lfunc_end0-_Z31__device_stub__computeHistogramPiPji
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
xorl %ebx, %ebx
xorl %edi, %edi
callq time
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq srand
movl $524288, %ebp # imm = 0x80000
movabsq $2305843009213693951, %r12 # imm = 0x1FFFFFFFFFFFFFFF
xorl %r14d, %r14d
xorl %r13d, %r13d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_2: # in Loop: Header=BB1_1 Depth=1
movl %r15d, (%r14)
.LBB1_19: # %_ZNSt6vectorIiSaIiEE9push_backEOi.exit
# in Loop: Header=BB1_1 Depth=1
addq $4, %r14
decl %ebp
je .LBB1_20
.LBB1_1: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %r15d
leal 4095(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
andl $-4096, %eax # imm = 0xF000
subl %eax, %r15d
cmpq %r13, %r14
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movq %rbx, 32(%rsp) # 8-byte Spill
subq %rbx, %r14
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r14
je .LBB1_4
# %bb.6: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r14, %rbx
sarq $2, %rbx
cmpq $1, %rbx
movq %rbx, %rax
adcq $0, %rax
leaq (%rax,%rbx), %rcx
cmpq %r12, %rcx
jb .LBB1_8
# %bb.7: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r12, %rcx
.LBB1_8: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r12, %r13
addq %rbx, %rax
jb .LBB1_10
# %bb.9: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %rcx, %r13
.LBB1_10: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %r13, %r13
je .LBB1_11
# %bb.12: # in Loop: Header=BB1_1 Depth=1
leaq (,%r13,4), %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movq %rax, %r12
jmp .LBB1_14
.LBB1_11: # in Loop: Header=BB1_1 Depth=1
xorl %r12d, %r12d
.LBB1_14: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movl %r15d, (%r12,%rbx,4)
testq %r14, %r14
movq 32(%rsp), %rbx # 8-byte Reload
jle .LBB1_16
# %bb.15: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movq %rbx, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB1_16: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %rbx, %rbx
je .LBB1_18
# %bb.17: # in Loop: Header=BB1_1 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_18: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
addq %r12, %r14
leaq (%r12,%r13,4), %r13
movq %r12, %rbx
movabsq $2305843009213693951, %r12 # imm = 0x1FFFFFFFFFFFFFFF
jmp .LBB1_19
.LBB1_20:
movq $0, 24(%rsp)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
.Ltmp4:
# %bb.21: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 24(%rsp), %rdi
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $2097152, %edx # imm = 0x200000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp6:
# %bb.22:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
xorl %edx, %edx
callq hipHostMalloc
.Ltmp9:
# %bb.23: # %_ZL13hipHostMallocIjE10hipError_tPPT_mj.exit
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp11:
# %bb.24: # %_ZL9hipMallocIjE10hipError_tPPT_m.exit
.Ltmp13:
.cfi_escape 0x2e, 0x00
movabsq $4294967808, %rdi # imm = 0x100000200
movabsq $4294968320, %rdx # imm = 0x100000400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp14:
# %bb.25:
testl %eax, %eax
jne .LBB1_28
# %bb.26:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl $524288, 44(%rsp) # imm = 0x80000
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp16:
# %bb.27: # %.noexc33
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
.Ltmp17:
.cfi_escape 0x2e, 0x10
leaq 48(%rsp), %r9
movl $_Z16computeHistogramPiPji, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp18:
.LBB1_28:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
.Ltmp19:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movl $1, %ecx
callq hipMemcpy
.Ltmp20:
# %bb.29: # %.preheader.preheader
xorl %r14d, %r14d
leaq 48(%rsp), %r15
jmp .LBB1_30
.p2align 4, 0x90
.LBB1_41: # in Loop: Header=BB1_30 Depth=1
.Ltmp31:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp32:
.LBB1_42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB1_30 Depth=1
incq %r14
cmpq $4096, %r14 # imm = 0x1000
je .LBB1_43
.LBB1_30: # %.preheader
# =>This Inner Loop Header: Depth=1
.Ltmp21:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp22:
# %bb.31: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_30 Depth=1
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
.Ltmp24:
# %bb.32: # in Loop: Header=BB1_30 Depth=1
.Ltmp25:
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp26:
# %bb.33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit37
# in Loop: Header=BB1_30 Depth=1
movq 16(%rsp), %rax
movl (%rax,%r14,4), %esi
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp28:
# %bb.34: # %_ZNSolsEj.exit
# in Loop: Header=BB1_30 Depth=1
movb $10, 48(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_41
# %bb.35: # in Loop: Header=BB1_30 Depth=1
.Ltmp29:
.cfi_escape 0x2e, 0x00
movl $1, %edx
movq %rax, %rdi
movq %r15, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp30:
jmp .LBB1_42
.LBB1_43:
movq 24(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.44:
movq 16(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp37:
# %bb.45:
movq 8(%rsp), %rdi
.Ltmp38:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp39:
# %bb.46:
testq %rbx, %rbx
je .LBB1_48
# %bb.47:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_48: # %_ZNSt6vectorIiSaIiEED2Ev.exit
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 192
.Ltmp41:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp42:
# %bb.5: # %.noexc
.LBB1_49:
.Ltmp12:
jmp .LBB1_50
.LBB1_39:
.Ltmp7:
jmp .LBB1_50
.LBB1_40:
.Ltmp40:
jmp .LBB1_50
.LBB1_36: # %.loopexit
.Ltmp2:
jmp .LBB1_37
.LBB1_38: # %.loopexit.split-lp
.Ltmp43:
.LBB1_37:
movq %rax, %r14
movq 32(%rsp), %rbx # 8-byte Reload
jmp .LBB1_51
.LBB1_54:
.Ltmp33:
.LBB1_50:
movq %rax, %r14
.LBB1_51:
testq %rbx, %rbx
je .LBB1_53
# %bb.52:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_53: # %_ZNSt6vectorIiSaIiEED2Ev.exit42
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp3 # Call between .Ltmp3 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp8 # Call between .Ltmp8 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp20-.Ltmp13 # Call between .Ltmp13 and .Ltmp20
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp31 # Call between .Ltmp31 and .Ltmp30
.uleb128 .Ltmp33-.Lfunc_begin0 # jumps to .Ltmp33
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp39-.Ltmp34 # Call between .Ltmp34 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end1-.Ltmp42 # Call between .Ltmp42 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16computeHistogramPiPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16computeHistogramPiPji,@object # @_Z16computeHistogramPiPji
.section .rodata,"a",@progbits
.globl _Z16computeHistogramPiPji
.p2align 3, 0x0
_Z16computeHistogramPiPji:
.quad _Z31__device_stub__computeHistogramPiPji
.size _Z16computeHistogramPiPji, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Bin: "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Elements: "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "vector::_M_realloc_insert"
.size .L.str.2, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16computeHistogramPiPji"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__computeHistogramPiPji
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z16computeHistogramPiPji
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***************/
/* FFTSHIFT 2D */
/***************/
__global__ void fftshift_2D(float2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
}
__global__ void fftshift_2D(double2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
} | code for sm_80
Function : _Z11fftshift_2DP7double2ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R8, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000087a24 */
/* 0x000fc800078e0203 */
/*00d0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e0209 */
/*00e0*/ LDG.E.128 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1d00 */
/*00f0*/ IADD3 R0, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fc80007ffe0ff */
/*0100*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0110*/ LOP3.LUT R0, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200007812 */
/* 0x000fc800078ec0ff */
/*0120*/ IADD3 R0, -R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe1ff */
/*0130*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000ea40000201c00 */
/*0140*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x004fc80000000000 */
/*0150*/ DMUL R4, R2, R4 ; /* 0x0000000402047228 */
/* 0x000e0e0000000000 */
/*0160*/ STG.E.128 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe2000c101d04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11fftshift_2DP6float2ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00e0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IADD3 R0, R0, R5, RZ ; /* 0x0000000500007210 */
/* 0x000fc80007ffe0ff */
/*0100*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0110*/ LOP3.LUT R0, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200007812 */
/* 0x000fc800078ec0ff */
/*0120*/ IADD3 R0, -R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fcc0007ffe1ff */
/*0130*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000ea40000201400 */
/*0140*/ FMUL R7, R0.reuse, R7 ; /* 0x0000000700077220 */
/* 0x044fe40000400000 */
/*0150*/ FMUL R6, R0, R6 ; /* 0x0000000600067220 */
/* 0x000fca0000400000 */
/*0160*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************/
/* FFTSHIFT 2D */
/***************/
__global__ void fftshift_2D(float2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
}
__global__ void fftshift_2D(double2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
} | .file "tmpxft_0016b878_00000000-6_cuFFT_auxiliary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii
.type _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii, @function
_Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11fftshift_2DP6float2ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii, .-_Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii
.globl _Z11fftshift_2DP6float2ii
.type _Z11fftshift_2DP6float2ii, @function
_Z11fftshift_2DP6float2ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11fftshift_2DP6float2ii, .-_Z11fftshift_2DP6float2ii
.globl _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii
.type _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii, @function
_Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11fftshift_2DP7double2ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii, .-_Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii
.globl _Z11fftshift_2DP7double2ii
.type _Z11fftshift_2DP7double2ii, @function
_Z11fftshift_2DP7double2ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11fftshift_2DP7double2ii, .-_Z11fftshift_2DP7double2ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11fftshift_2DP7double2ii"
.LC1:
.string "_Z11fftshift_2DP6float2ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11fftshift_2DP7double2ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11fftshift_2DP6float2ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************/
/* FFTSHIFT 2D */
/***************/
__global__ void fftshift_2D(float2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
}
__global__ void fftshift_2D(double2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
} | #include <hip/hip_runtime.h>
/***************/
/* FFTSHIFT 2D */
/***************/
__global__ void fftshift_2D(float2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
}
__global__ void fftshift_2D(double2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/***************/
/* FFTSHIFT 2D */
/***************/
__global__ void fftshift_2D(float2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
}
__global__ void fftshift_2D(double2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.globl _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.p2align 8
.type _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii,@function
_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_add_lshl_u32 v0, v1, v0, 1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[4:5], v[2:3], off
v_and_b32_e32 v0, 2, v0
v_sub_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v4, v1
v_mul_f32_e32 v1, v5, v1
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, .Lfunc_end0-_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.globl _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.p2align 8
.type _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii,@function
_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_add_lshl_u32 v0, v1, v0, 1
v_and_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_sub_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 4, v[2:3]
v_cvt_f64_i32_e32 v[8:9], v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
global_load_b128 v[2:5], v[6:7], off
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[2:3], v[8:9]
v_mul_f64 v[2:3], v[4:5], v[8:9]
global_store_b128 v[6:7], v[0:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, .Lfunc_end1-_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/***************/
/* FFTSHIFT 2D */
/***************/
__global__ void fftshift_2D(float2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
}
__global__ void fftshift_2D(double2 * __restrict__ data, const int N1, const int N2)
{
int i = threadIdx.x + blockDim.x * blockIdx.x;
int j = threadIdx.y + blockDim.y * blockIdx.y;
if (i < N1 && j < N2) {
data[i*N2+j].x *= 1-2*((i+j)&1);
data[i*N2+j].y *= 1-2*((i+j)&1);
}
} | .text
.file "cuFFT_auxiliary.hip"
.globl _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii # -- Begin function _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.p2align 4, 0x90
.type _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii,@function
_Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii: # @_Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii, .Lfunc_end0-_Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii # -- Begin function _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.p2align 4, 0x90
.type _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii,@function
_Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii: # @_Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii, .Lfunc_end1-_Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii,@object # @_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.section .rodata,"a",@progbits
.globl _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.p2align 3, 0x0
_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii:
.quad _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.size _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, 8
.type _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii,@object # @_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.globl _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.p2align 3, 0x0
_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii:
.quad _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.size _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii"
.size .L__unnamed_1, 43
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii"
.size .L__unnamed_2, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.addrsig_sym _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.addrsig_sym _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11fftshift_2DP7double2ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R8, R0, c[0x0][0x16c], R3 ; /* 0x00005b0000087a24 */
/* 0x000fc800078e0203 */
/*00d0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e0209 */
/*00e0*/ LDG.E.128 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1d00 */
/*00f0*/ IADD3 R0, R0, R3, RZ ; /* 0x0000000300007210 */
/* 0x000fc80007ffe0ff */
/*0100*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0110*/ LOP3.LUT R0, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200007812 */
/* 0x000fc800078ec0ff */
/*0120*/ IADD3 R0, -R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe1ff */
/*0130*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000ea40000201c00 */
/*0140*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x004fc80000000000 */
/*0150*/ DMUL R4, R2, R4 ; /* 0x0000000402047228 */
/* 0x000e0e0000000000 */
/*0160*/ STG.E.128 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x001fe2000c101d04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11fftshift_2DP6float2ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000027a24 */
/* 0x000fe200078e0205 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00e0*/ LDG.E.64 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ IADD3 R0, R0, R5, RZ ; /* 0x0000000500007210 */
/* 0x000fc80007ffe0ff */
/*0100*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0110*/ LOP3.LUT R0, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200007812 */
/* 0x000fc800078ec0ff */
/*0120*/ IADD3 R0, -R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fcc0007ffe1ff */
/*0130*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000ea40000201400 */
/*0140*/ FMUL R7, R0.reuse, R7 ; /* 0x0000000700077220 */
/* 0x044fe40000400000 */
/*0150*/ FMUL R6, R0, R6 ; /* 0x0000000600067220 */
/* 0x000fca0000400000 */
/*0160*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.globl _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.p2align 8
.type _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii,@function
_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_add_lshl_u32 v0, v1, v0, 1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[4:5], v[2:3], off
v_and_b32_e32 v0, 2, v0
v_sub_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, v4, v1
v_mul_f32_e32 v1, v5, v1
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, .Lfunc_end0-_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.globl _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.p2align 8
.type _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii,@function
_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
v_add_lshl_u32 v0, v1, v0, 1
v_and_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_sub_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 4, v[2:3]
v_cvt_f64_i32_e32 v[8:9], v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
global_load_b128 v[2:5], v[6:7], off
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[2:3], v[8:9]
v_mul_f64 v[2:3], v[4:5], v[8:9]
global_store_b128 v[6:7], v[0:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, .Lfunc_end1-_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016b878_00000000-6_cuFFT_auxiliary.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii
.type _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii, @function
_Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11fftshift_2DP6float2ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii, .-_Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii
.globl _Z11fftshift_2DP6float2ii
.type _Z11fftshift_2DP6float2ii, @function
_Z11fftshift_2DP6float2ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11fftshift_2DP6float2iiP6float2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11fftshift_2DP6float2ii, .-_Z11fftshift_2DP6float2ii
.globl _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii
.type _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii, @function
_Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11fftshift_2DP7double2ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii, .-_Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii
.globl _Z11fftshift_2DP7double2ii
.type _Z11fftshift_2DP7double2ii, @function
_Z11fftshift_2DP7double2ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11fftshift_2DP7double2iiP7double2ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11fftshift_2DP7double2ii, .-_Z11fftshift_2DP7double2ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11fftshift_2DP7double2ii"
.LC1:
.string "_Z11fftshift_2DP6float2ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11fftshift_2DP7double2ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11fftshift_2DP6float2ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuFFT_auxiliary.hip"
.globl _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii # -- Begin function _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.p2align 4, 0x90
.type _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii,@function
_Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii: # @_Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii, .Lfunc_end0-_Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii # -- Begin function _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.p2align 4, 0x90
.type _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii,@function
_Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii: # @_Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii, .Lfunc_end1-_Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii,@object # @_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.section .rodata,"a",@progbits
.globl _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.p2align 3, 0x0
_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii:
.quad _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.size _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii, 8
.type _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii,@object # @_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.globl _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.p2align 3, 0x0
_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii:
.quad _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.size _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11fftshift_2DP15HIP_vector_typeIfLj2EEii"
.size .L__unnamed_1, 43
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11fftshift_2DP15HIP_vector_typeIdLj2EEii"
.size .L__unnamed_2, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__fftshift_2DP15HIP_vector_typeIfLj2EEii
.addrsig_sym _Z26__device_stub__fftshift_2DP15HIP_vector_typeIdLj2EEii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11fftshift_2DP15HIP_vector_typeIfLj2EEii
.addrsig_sym _Z11fftshift_2DP15HIP_vector_typeIdLj2EEii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <iostream>
#include <cstdlib>
#define checkCudaErrors(val) __check( (val), #val, __FILE__, __LINE__)
template<typename T>
void __check(T err, const char* const func, const char* const file, const int line) {
if (err != cudaSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << cudaGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
int main() {
int *data;
checkCudaErrors(cudaMalloc((void **)&data, 4));
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <iostream>
#include <cstdlib>
#define checkCudaErrors(val) __check( (val), #val, __FILE__, __LINE__)
template<typename T>
void __check(T err, const char* const func, const char* const file, const int line) {
if (err != cudaSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << cudaGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
int main() {
int *data;
checkCudaErrors(cudaMalloc((void **)&data, 4));
return 0;
} | .file "tmpxft_000f0296_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error at: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/timrobot/XRift/master/oculus/test.cu"
.section .rodata.str1.1
.LC2:
.string ":"
.LC3:
.string " "
.LC4:
.string "cudaMalloc((void **)&data, 4)"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L7
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $19, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <iostream>
#include <cstdlib>
#define checkCudaErrors(val) __check( (val), #val, __FILE__, __LINE__)
template<typename T>
void __check(T err, const char* const func, const char* const file, const int line) {
if (err != cudaSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << cudaGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
int main() {
int *data;
checkCudaErrors(cudaMalloc((void **)&data, 4));
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <cstdlib>
#define checkCudaErrors(val) __check( (val), #val, __FILE__, __LINE__)
template<typename T>
void __check(T err, const char* const func, const char* const file, const int line) {
if (err != hipSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << hipGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
int main() {
int *data;
checkCudaErrors(hipMalloc((void **)&data, 4));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <cstdlib>
#define checkCudaErrors(val) __check( (val), #val, __FILE__, __LINE__)
template<typename T>
void __check(T err, const char* const func, const char* const file, const int line) {
if (err != hipSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << hipGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
int main() {
int *data;
checkCudaErrors(hipMalloc((void **)&data, 4));
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
#include <cstdlib>
#define checkCudaErrors(val) __check( (val), #val, __FILE__, __LINE__)
template<typename T>
void __check(T err, const char* const func, const char* const file, const int line) {
if (err != hipSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << hipGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
int main() {
int *data;
checkCudaErrors(hipMalloc((void **)&data, 4));
return 0;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $.L.str, %esi
movl $.L.str.1, %edx
movl %eax, %edi
movl $19, %ecx
callq _Z7__checkI10hipError_tEvT_PKcS3_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z7__checkI10hipError_tEvT_PKcS3_i,"axG",@progbits,_Z7__checkI10hipError_tEvT_PKcS3_i,comdat
.weak _Z7__checkI10hipError_tEvT_PKcS3_i # -- Begin function _Z7__checkI10hipError_tEvT_PKcS3_i
.p2align 4, 0x90
.type _Z7__checkI10hipError_tEvT_PKcS3_i,@function
_Z7__checkI10hipError_tEvT_PKcS3_i: # @_Z7__checkI10hipError_tEvT_PKcS3_i
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movl $_ZSt4cerr, %edi
movq %rsi, %rbx
movl $.L.str.2, %esi
movl %ecx, %r14d
movq %rdx, %r15
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r15, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %rbx, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z7__checkI10hipError_tEvT_PKcS3_i, .Lfunc_end1-_Z7__checkI10hipError_tEvT_PKcS3_i
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc((void **)&data, 4)"
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/timrobot/XRift/master/oculus/test.hip"
.size .L.str.1, 95
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA error at: "
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ":"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f0296_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error at: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/timrobot/XRift/master/oculus/test.cu"
.section .rodata.str1.1
.LC2:
.string ":"
.LC3:
.string " "
.LC4:
.string "cudaMalloc((void **)&data, 4)"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L7
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $19, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $.L.str, %esi
movl $.L.str.1, %edx
movl %eax, %edi
movl $19, %ecx
callq _Z7__checkI10hipError_tEvT_PKcS3_i
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z7__checkI10hipError_tEvT_PKcS3_i,"axG",@progbits,_Z7__checkI10hipError_tEvT_PKcS3_i,comdat
.weak _Z7__checkI10hipError_tEvT_PKcS3_i # -- Begin function _Z7__checkI10hipError_tEvT_PKcS3_i
.p2align 4, 0x90
.type _Z7__checkI10hipError_tEvT_PKcS3_i,@function
_Z7__checkI10hipError_tEvT_PKcS3_i: # @_Z7__checkI10hipError_tEvT_PKcS3_i
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB1_2
# %bb.1:
retq
.LBB1_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movl $_ZSt4cerr, %edi
movq %rsi, %rbx
movl $.L.str.2, %esi
movl %ecx, %r14d
movq %rdx, %r15
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r15, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.4, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %rbx, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z7__checkI10hipError_tEvT_PKcS3_i, .Lfunc_end1-_Z7__checkI10hipError_tEvT_PKcS3_i
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc((void **)&data, 4)"
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/timrobot/XRift/master/oculus/test.hip"
.size .L.str.1, 95
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA error at: "
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ":"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " "
.size .L.str.4, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Name: H.G. Manesha Washani
// Student Id: 1432289
#include <stdio.h>
#include <stdlib.h>
#define N 6
/* The _global_ indicates a function that runs on the device and it called for host code. A kernel to add two integers */
__global__ void MatAdd(int A[][N], int B[][N], int C[][N]){
int g = threadIdx.x;
int h = threadIdx.y;
C[g][h] = A[g][h] + B[g][h];
}
/* My code i used variable is int g and int h, because of that reason i changed given code variables */
void randmatfunc(int newmat[N][N]){
int g, h, k;
for(g=0;g<N;g++){
for(h=0;h<N;h++){
k = rand() % 100 + 1;;
printf("%d ", k);
newmat[g][h] =k;
}
printf("\n");
}
printf("\n-----------------------------------\n");
}
int main(){
int A[N][N];
randmatfunc(A);
int B[N][N];
randmatfunc(B);
int C[N][N];
int (*d_A)[N], (*d_B)[N], (*d_C)[N];
/* device copies of A, B, C and Allocate space for device copies of A, B, C */
cudaMalloc((void**)&d_A, (N*N)*sizeof(int));
cudaMalloc((void**)&d_B, (N*N)*sizeof(int));
cudaMalloc((void**)&d_C, (N*N)*sizeof(int));
// copy input to device
cudaMemcpy(d_A, A, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
int numBlocks = 1;
dim3 threadsPerBlock(N,N);
MatAdd<<<numBlocks,threadsPerBlock>>>(d_A,d_B,d_C);
// Copy result back to the host
cudaMemcpy(C, d_C, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
int g, h; printf("C = \n");
for(g=0;g<N;g++){
for(h=0;h<N;h++){
printf("%d ", C[g][h]);
}
printf("\n");
}
// This is cleanup
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("\n");
return 0;
} | code for sm_80
Function : _Z6MatAddPA6_iS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e6e0000002200 */
/*0050*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x002fc800078e0202 */
/*0080*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*00c0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fe200078e0206 */
/*00d0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Name: H.G. Manesha Washani
// Student Id: 1432289
#include <stdio.h>
#include <stdlib.h>
#define N 6
/* The _global_ indicates a function that runs on the device and it called for host code. A kernel to add two integers */
__global__ void MatAdd(int A[][N], int B[][N], int C[][N]){
int g = threadIdx.x;
int h = threadIdx.y;
C[g][h] = A[g][h] + B[g][h];
}
/* My code i used variable is int g and int h, because of that reason i changed given code variables */
void randmatfunc(int newmat[N][N]){
int g, h, k;
for(g=0;g<N;g++){
for(h=0;h<N;h++){
k = rand() % 100 + 1;;
printf("%d ", k);
newmat[g][h] =k;
}
printf("\n");
}
printf("\n-----------------------------------\n");
}
int main(){
int A[N][N];
randmatfunc(A);
int B[N][N];
randmatfunc(B);
int C[N][N];
int (*d_A)[N], (*d_B)[N], (*d_C)[N];
/* device copies of A, B, C and Allocate space for device copies of A, B, C */
cudaMalloc((void**)&d_A, (N*N)*sizeof(int));
cudaMalloc((void**)&d_B, (N*N)*sizeof(int));
cudaMalloc((void**)&d_C, (N*N)*sizeof(int));
// copy input to device
cudaMemcpy(d_A, A, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
int numBlocks = 1;
dim3 threadsPerBlock(N,N);
MatAdd<<<numBlocks,threadsPerBlock>>>(d_A,d_B,d_C);
// Copy result back to the host
cudaMemcpy(C, d_C, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
int g, h; printf("C = \n");
for(g=0;g<N;g++){
for(h=0;h<N;h++){
printf("%d ", C[g][h]);
}
printf("\n");
}
// This is cleanup
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("\n");
return 0;
} | .file "tmpxft_000fce75_00000000-6_CUDA_task3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n-----------------------------------\n"
.text
.globl _Z11randmatfuncPA6_i
.type _Z11randmatfuncPA6_i, @function
_Z11randmatfuncPA6_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq 24(%rdi), %rbp
leaq 168(%rdi), %r13
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L4:
leaq -24(%rbp), %rbx
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
leal 1(%rax), %r15d
movl %r15d, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rbp
cmpq %r13, %rbp
jne .L4
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11randmatfuncPA6_i, .-_Z11randmatfuncPA6_i
.globl _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
.type _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_, @function
_Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatAddPA6_iS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_, .-_Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
.globl _Z6MatAddPA6_iS0_S0_
.type _Z6MatAddPA6_iS0_S0_, @function
_Z6MatAddPA6_iS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6MatAddPA6_iS0_S0_, .-_Z6MatAddPA6_iS0_S0_
.section .rodata.str1.1
.LC3:
.string "C = \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $496, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 488(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbp
movq %rbp, %rdi
call _Z11randmatfuncPA6_i
leaq 192(%rsp), %rbx
movq %rbx, %rdi
call _Z11randmatfuncPA6_i
movq %rsp, %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $144, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $144, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 336(%rsp), %rsi
movl $1, %ecx
movl $144, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 24(%rsp)
movl $6, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
leaq 336(%rsp), %rbp
movl $2, %ecx
movl $144, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 480(%rsp), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L19:
movl $0, %ebx
.L20:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $6, %rbx
jne .L20
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rbp
cmpq %r14, %rbp
jne .L19
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 488(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $496, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6MatAddPA6_iS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatAddPA6_iS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Name: H.G. Manesha Washani
// Student Id: 1432289
#include <stdio.h>
#include <stdlib.h>
#define N 6
/* The _global_ indicates a function that runs on the device and it called for host code. A kernel to add two integers */
__global__ void MatAdd(int A[][N], int B[][N], int C[][N]){
int g = threadIdx.x;
int h = threadIdx.y;
C[g][h] = A[g][h] + B[g][h];
}
/* My code i used variable is int g and int h, because of that reason i changed given code variables */
void randmatfunc(int newmat[N][N]){
int g, h, k;
for(g=0;g<N;g++){
for(h=0;h<N;h++){
k = rand() % 100 + 1;;
printf("%d ", k);
newmat[g][h] =k;
}
printf("\n");
}
printf("\n-----------------------------------\n");
}
int main(){
int A[N][N];
randmatfunc(A);
int B[N][N];
randmatfunc(B);
int C[N][N];
int (*d_A)[N], (*d_B)[N], (*d_C)[N];
/* device copies of A, B, C and Allocate space for device copies of A, B, C */
cudaMalloc((void**)&d_A, (N*N)*sizeof(int));
cudaMalloc((void**)&d_B, (N*N)*sizeof(int));
cudaMalloc((void**)&d_C, (N*N)*sizeof(int));
// copy input to device
cudaMemcpy(d_A, A, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_C, C, (N*N)*sizeof(int), cudaMemcpyHostToDevice);
// Launch add() kernel on GPU
int numBlocks = 1;
dim3 threadsPerBlock(N,N);
MatAdd<<<numBlocks,threadsPerBlock>>>(d_A,d_B,d_C);
// Copy result back to the host
cudaMemcpy(C, d_C, (N*N)*sizeof(int), cudaMemcpyDeviceToHost);
int g, h; printf("C = \n");
for(g=0;g<N;g++){
for(h=0;h<N;h++){
printf("%d ", C[g][h]);
}
printf("\n");
}
// This is cleanup
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
printf("\n");
return 0;
} | // Name: H.G. Manesha Washani
// Student Id: 1432289
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 6
/* The _global_ indicates a function that runs on the device and it called for host code. A kernel to add two integers */
__global__ void MatAdd(int A[][N], int B[][N], int C[][N]){
int g = threadIdx.x;
int h = threadIdx.y;
C[g][h] = A[g][h] + B[g][h];
}
/* My code i used variable is int g and int h, because of that reason i changed given code variables */
void randmatfunc(int newmat[N][N]){
int g, h, k;
for(g=0;g<N;g++){
for(h=0;h<N;h++){
k = rand() % 100 + 1;;
printf("%d ", k);
newmat[g][h] =k;
}
printf("\n");
}
printf("\n-----------------------------------\n");
}
int main(){
int A[N][N];
randmatfunc(A);
int B[N][N];
randmatfunc(B);
int C[N][N];
int (*d_A)[N], (*d_B)[N], (*d_C)[N];
/* device copies of A, B, C and Allocate space for device copies of A, B, C */
hipMalloc((void**)&d_A, (N*N)*sizeof(int));
hipMalloc((void**)&d_B, (N*N)*sizeof(int));
hipMalloc((void**)&d_C, (N*N)*sizeof(int));
// copy input to device
hipMemcpy(d_A, A, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, (N*N)*sizeof(int), hipMemcpyHostToDevice);
// Launch add() kernel on GPU
int numBlocks = 1;
dim3 threadsPerBlock(N,N);
MatAdd<<<numBlocks,threadsPerBlock>>>(d_A,d_B,d_C);
// Copy result back to the host
hipMemcpy(C, d_C, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
int g, h; printf("C = \n");
for(g=0;g<N;g++){
for(h=0;h<N;h++){
printf("%d ", C[g][h]);
}
printf("\n");
}
// This is cleanup
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Name: H.G. Manesha Washani
// Student Id: 1432289
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 6
/* The _global_ indicates a function that runs on the device and it called for host code. A kernel to add two integers */
__global__ void MatAdd(int A[][N], int B[][N], int C[][N]){
int g = threadIdx.x;
int h = threadIdx.y;
C[g][h] = A[g][h] + B[g][h];
}
/* My code i used variable is int g and int h, because of that reason i changed given code variables */
void randmatfunc(int newmat[N][N]){
int g, h, k;
for(g=0;g<N;g++){
for(h=0;h<N;h++){
k = rand() % 100 + 1;;
printf("%d ", k);
newmat[g][h] =k;
}
printf("\n");
}
printf("\n-----------------------------------\n");
}
int main(){
int A[N][N];
randmatfunc(A);
int B[N][N];
randmatfunc(B);
int C[N][N];
int (*d_A)[N], (*d_B)[N], (*d_C)[N];
/* device copies of A, B, C and Allocate space for device copies of A, B, C */
hipMalloc((void**)&d_A, (N*N)*sizeof(int));
hipMalloc((void**)&d_B, (N*N)*sizeof(int));
hipMalloc((void**)&d_C, (N*N)*sizeof(int));
// copy input to device
hipMemcpy(d_A, A, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, (N*N)*sizeof(int), hipMemcpyHostToDevice);
// Launch add() kernel on GPU
int numBlocks = 1;
dim3 threadsPerBlock(N,N);
MatAdd<<<numBlocks,threadsPerBlock>>>(d_A,d_B,d_C);
// Copy result back to the host
hipMemcpy(C, d_C, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
int g, h; printf("C = \n");
for(g=0;g<N;g++){
for(h=0;h<N;h++){
printf("%d ", C[g][h]);
}
printf("\n");
}
// This is cleanup
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatAddPA6_iS0_S0_
.globl _Z6MatAddPA6_iS0_S0_
.p2align 8
.type _Z6MatAddPA6_iS0_S0_,@function
_Z6MatAddPA6_iS0_S0_:
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_lshrrev_b32_e32 v0, 8, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v4, 24, v1
v_mul_hi_u32_u24_e32 v5, 24, v1
v_and_b32_e32 v6, 0xffc, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatAddPA6_iS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatAddPA6_iS0_S0_, .Lfunc_end0-_Z6MatAddPA6_iS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatAddPA6_iS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6MatAddPA6_iS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Name: H.G. Manesha Washani
// Student Id: 1432289
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 6
/* The _global_ indicates a function that runs on the device and it called for host code. A kernel to add two integers */
__global__ void MatAdd(int A[][N], int B[][N], int C[][N]){
int g = threadIdx.x;
int h = threadIdx.y;
C[g][h] = A[g][h] + B[g][h];
}
/* My code i used variable is int g and int h, because of that reason i changed given code variables */
void randmatfunc(int newmat[N][N]){
int g, h, k;
for(g=0;g<N;g++){
for(h=0;h<N;h++){
k = rand() % 100 + 1;;
printf("%d ", k);
newmat[g][h] =k;
}
printf("\n");
}
printf("\n-----------------------------------\n");
}
int main(){
int A[N][N];
randmatfunc(A);
int B[N][N];
randmatfunc(B);
int C[N][N];
int (*d_A)[N], (*d_B)[N], (*d_C)[N];
/* device copies of A, B, C and Allocate space for device copies of A, B, C */
hipMalloc((void**)&d_A, (N*N)*sizeof(int));
hipMalloc((void**)&d_B, (N*N)*sizeof(int));
hipMalloc((void**)&d_C, (N*N)*sizeof(int));
// copy input to device
hipMemcpy(d_A, A, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_B, B, (N*N)*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_C, C, (N*N)*sizeof(int), hipMemcpyHostToDevice);
// Launch add() kernel on GPU
int numBlocks = 1;
dim3 threadsPerBlock(N,N);
MatAdd<<<numBlocks,threadsPerBlock>>>(d_A,d_B,d_C);
// Copy result back to the host
hipMemcpy(C, d_C, (N*N)*sizeof(int), hipMemcpyDeviceToHost);
int g, h; printf("C = \n");
for(g=0;g<N;g++){
for(h=0;h<N;h++){
printf("%d ", C[g][h]);
}
printf("\n");
}
// This is cleanup
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
printf("\n");
return 0;
} | .text
.file "CUDA_task3.hip"
.globl _Z21__device_stub__MatAddPA6_iS0_S0_ # -- Begin function _Z21__device_stub__MatAddPA6_iS0_S0_
.p2align 4, 0x90
.type _Z21__device_stub__MatAddPA6_iS0_S0_,@function
_Z21__device_stub__MatAddPA6_iS0_S0_: # @_Z21__device_stub__MatAddPA6_iS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatAddPA6_iS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__MatAddPA6_iS0_S0_, .Lfunc_end0-_Z21__device_stub__MatAddPA6_iS0_S0_
.cfi_endproc
# -- End function
.globl _Z11randmatfuncPA6_i # -- Begin function _Z11randmatfuncPA6_i
.p2align 4, 0x90
.type _Z11randmatfuncPA6_i,@function
_Z11randmatfuncPA6_i: # @_Z11randmatfuncPA6_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
leal (%rax,%rcx), %ebp
incl %ebp
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl %ebp, (%rbx,%r15,4)
incq %r15
cmpq $6, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $24, %rbx
cmpq $6, %r14
jne .LBB1_1
# %bb.4:
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z11randmatfuncPA6_i, .Lfunc_end1-_Z11randmatfuncPA6_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $568, %rsp # imm = 0x238
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 272(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
leal (%rax,%rcx), %ebx
incl %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, (%r14,%r12,4)
incq %r12
cmpq $6, %r12
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $24, %r14
cmpq $6, %r15
jne .LBB2_1
# %bb.4: # %_Z11randmatfuncPA6_i.exit
movl $.Lstr, %edi
callq puts@PLT
leaq 128(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_5: # %.preheader.i13
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
leal (%rax,%rcx), %ebx
incl %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, (%r14,%r12,4)
incq %r12
cmpq $6, %r12
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $24, %r14
cmpq $6, %r15
jne .LBB2_5
# %bb.8: # %_Z11randmatfuncPA6_i.exit22
movl $.Lstr, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
movl $144, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $144, %esi
callq hipMalloc
movq %rsp, %rdi
movl $144, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 272(%rsp), %rsi
movl $144, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $144, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 416(%rsp), %rbx
movl $144, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $25769803782, %rdx # imm = 0x600000006
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatAddPA6_iS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq (%rsp), %rsi
movl $144, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_12: # Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $6, %r15
jne .LBB2_12
# %bb.13: # in Loop: Header=BB2_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $24, %rbx
cmpq $6, %r14
jne .LBB2_11
# %bb.14:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $568, %rsp # imm = 0x238
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatAddPA6_iS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatAddPA6_iS0_S0_,@object # @_Z6MatAddPA6_iS0_S0_
.section .rodata,"a",@progbits
.globl _Z6MatAddPA6_iS0_S0_
.p2align 3, 0x0
_Z6MatAddPA6_iS0_S0_:
.quad _Z21__device_stub__MatAddPA6_iS0_S0_
.size _Z6MatAddPA6_iS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatAddPA6_iS0_S0_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n-----------------------------------"
.size .Lstr, 37
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "C = "
.size .Lstr.1, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatAddPA6_iS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatAddPA6_iS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6MatAddPA6_iS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e6e0000002200 */
/*0050*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R9, 0x4, R2 ; /* 0x0000000409027825 */
/* 0x002fc800078e0202 */
/*0080*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fcc00078e0207 */
/*00c0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fe200078e0206 */
/*00d0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6MatAddPA6_iS0_S0_
.globl _Z6MatAddPA6_iS0_S0_
.p2align 8
.type _Z6MatAddPA6_iS0_S0_,@function
_Z6MatAddPA6_iS0_S0_:
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_lshrrev_b32_e32 v0, 8, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v4, 24, v1
v_mul_hi_u32_u24_e32 v5, 24, v1
v_and_b32_e32 v6, 0xffc, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, v0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v2, v6
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6MatAddPA6_iS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6MatAddPA6_iS0_S0_, .Lfunc_end0-_Z6MatAddPA6_iS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6MatAddPA6_iS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6MatAddPA6_iS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fce75_00000000-6_CUDA_task3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\n-----------------------------------\n"
.text
.globl _Z11randmatfuncPA6_i
.type _Z11randmatfuncPA6_i, @function
_Z11randmatfuncPA6_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq 24(%rdi), %rbp
leaq 168(%rdi), %r13
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L4:
leaq -24(%rbp), %rbx
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
leal 1(%rax), %r15d
movl %r15d, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rbp
cmpq %r13, %rbp
jne .L4
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11randmatfuncPA6_i, .-_Z11randmatfuncPA6_i
.globl _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
.type _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_, @function
_Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatAddPA6_iS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_, .-_Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
.globl _Z6MatAddPA6_iS0_S0_
.type _Z6MatAddPA6_iS0_S0_, @function
_Z6MatAddPA6_iS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6MatAddPA6_iS0_S0_, .-_Z6MatAddPA6_iS0_S0_
.section .rodata.str1.1
.LC3:
.string "C = \n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $496, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 488(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rbp
movq %rbp, %rdi
call _Z11randmatfuncPA6_i
leaq 192(%rsp), %rbx
movq %rbx, %rdi
call _Z11randmatfuncPA6_i
movq %rsp, %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $144, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $144, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 336(%rsp), %rsi
movl $1, %ecx
movl $144, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 24(%rsp)
movl $6, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L18:
leaq 336(%rsp), %rbp
movl $2, %ecx
movl $144, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 480(%rsp), %r14
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
.L19:
movl $0, %ebx
.L20:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $6, %rbx
jne .L20
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rbp
cmpq %r14, %rbp
jne .L19
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 488(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $496, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z6MatAddPA6_iS0_S0_PA6_iS0_S0_
jmp .L18
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6MatAddPA6_iS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatAddPA6_iS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA_task3.hip"
.globl _Z21__device_stub__MatAddPA6_iS0_S0_ # -- Begin function _Z21__device_stub__MatAddPA6_iS0_S0_
.p2align 4, 0x90
.type _Z21__device_stub__MatAddPA6_iS0_S0_,@function
_Z21__device_stub__MatAddPA6_iS0_S0_: # @_Z21__device_stub__MatAddPA6_iS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatAddPA6_iS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__MatAddPA6_iS0_S0_, .Lfunc_end0-_Z21__device_stub__MatAddPA6_iS0_S0_
.cfi_endproc
# -- End function
.globl _Z11randmatfuncPA6_i # -- Begin function _Z11randmatfuncPA6_i
.p2align 4, 0x90
.type _Z11randmatfuncPA6_i,@function
_Z11randmatfuncPA6_i: # @_Z11randmatfuncPA6_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
leal (%rax,%rcx), %ebp
incl %ebp
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl %ebp, (%rbx,%r15,4)
incq %r15
cmpq $6, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $24, %rbx
cmpq $6, %r14
jne .LBB1_1
# %bb.4:
movl $.Lstr, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z11randmatfuncPA6_i, .Lfunc_end1-_Z11randmatfuncPA6_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $568, %rsp # imm = 0x238
.cfi_def_cfa_offset 608
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 272(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
leal (%rax,%rcx), %ebx
incl %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, (%r14,%r12,4)
incq %r12
cmpq $6, %r12
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $24, %r14
cmpq $6, %r15
jne .LBB2_1
# %bb.4: # %_Z11randmatfuncPA6_i.exit
movl $.Lstr, %edi
callq puts@PLT
leaq 128(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_5: # %.preheader.i13
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
leal (%rax,%rcx), %ebx
incl %ebx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, (%r14,%r12,4)
incq %r12
cmpq $6, %r12
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $24, %r14
cmpq $6, %r15
jne .LBB2_5
# %bb.8: # %_Z11randmatfuncPA6_i.exit22
movl $.Lstr, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
movl $144, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $144, %esi
callq hipMalloc
movq %rsp, %rdi
movl $144, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 272(%rsp), %rsi
movl $144, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $144, %edx
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 416(%rsp), %rbx
movl $144, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $25769803782, %rdx # imm = 0x600000006
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatAddPA6_iS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq (%rsp), %rsi
movl $144, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_12: # Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $6, %r15
jne .LBB2_12
# %bb.13: # in Loop: Header=BB2_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $24, %rbx
cmpq $6, %r14
jne .LBB2_11
# %bb.14:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $568, %rsp # imm = 0x238
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatAddPA6_iS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatAddPA6_iS0_S0_,@object # @_Z6MatAddPA6_iS0_S0_
.section .rodata,"a",@progbits
.globl _Z6MatAddPA6_iS0_S0_
.p2align 3, 0x0
_Z6MatAddPA6_iS0_S0_:
.quad _Z21__device_stub__MatAddPA6_iS0_S0_
.size _Z6MatAddPA6_iS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatAddPA6_iS0_S0_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n-----------------------------------"
.size .Lstr, 37
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "C = "
.size .Lstr.1, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatAddPA6_iS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatAddPA6_iS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
#include <stdlib.h>
__global__ void abs_value(int n, double *a, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; //output x
if (i < n)
{
c[i] = abs(a[i]);
}
} | code for sm_80
Function : abs_value
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ DADD R6, -RZ, |R2| ; /* 0x00000000ff067229 */
/* 0x004e0e0000000502 */
/*00c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
#include <stdlib.h>
__global__ void abs_value(int n, double *a, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; //output x
if (i < n)
{
c[i] = abs(a[i]);
}
} | .file "tmpxft_0013fcc5_00000000-6_abs_value.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9abs_valueiPdS_iPdS_
.type _Z31__device_stub__Z9abs_valueiPdS_iPdS_, @function
_Z31__device_stub__Z9abs_valueiPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq abs_value(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9abs_valueiPdS_iPdS_, .-_Z31__device_stub__Z9abs_valueiPdS_iPdS_
.globl abs_value
.type abs_value, @function
abs_value:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9abs_valueiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size abs_value, .-abs_value
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "abs_value"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq abs_value(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
#include <stdlib.h>
__global__ void abs_value(int n, double *a, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; //output x
if (i < n)
{
c[i] = abs(a[i]);
}
} | extern "C"
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void abs_value(int n, double *a, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; //output x
if (i < n)
{
c[i] = abs(a[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | extern "C"
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void abs_value(int n, double *a, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; //output x
if (i < n)
{
c[i] = abs(a[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9abs_valueiPdS_
.globl _Z9abs_valueiPdS_
.p2align 8
.type _Z9abs_valueiPdS_,@function
_Z9abs_valueiPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9abs_valueiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9abs_valueiPdS_, .Lfunc_end0-_Z9abs_valueiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9abs_valueiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9abs_valueiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | extern "C"
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void abs_value(int n, double *a, double *c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x; //output x
if (i < n)
{
c[i] = abs(a[i]);
}
} | .text
.file "abs_value.hip"
.globl _Z24__device_stub__abs_valueiPdS_ # -- Begin function _Z24__device_stub__abs_valueiPdS_
.p2align 4, 0x90
.type _Z24__device_stub__abs_valueiPdS_,@function
_Z24__device_stub__abs_valueiPdS_: # @_Z24__device_stub__abs_valueiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9abs_valueiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__abs_valueiPdS_, .Lfunc_end0-_Z24__device_stub__abs_valueiPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9abs_valueiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9abs_valueiPdS_,@object # @_Z9abs_valueiPdS_
.section .rodata,"a",@progbits
.globl _Z9abs_valueiPdS_
.p2align 3, 0x0
_Z9abs_valueiPdS_:
.quad _Z24__device_stub__abs_valueiPdS_
.size _Z9abs_valueiPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9abs_valueiPdS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__abs_valueiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9abs_valueiPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : abs_value
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ DADD R6, -RZ, |R2| ; /* 0x00000000ff067229 */
/* 0x004e0e0000000502 */
/*00c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9abs_valueiPdS_
.globl _Z9abs_valueiPdS_
.p2align 8
.type _Z9abs_valueiPdS_,@function
_Z9abs_valueiPdS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v3
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9abs_valueiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9abs_valueiPdS_, .Lfunc_end0-_Z9abs_valueiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9abs_valueiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9abs_valueiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013fcc5_00000000-6_abs_value.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9abs_valueiPdS_iPdS_
.type _Z31__device_stub__Z9abs_valueiPdS_iPdS_, @function
_Z31__device_stub__Z9abs_valueiPdS_iPdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq abs_value(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9abs_valueiPdS_iPdS_, .-_Z31__device_stub__Z9abs_valueiPdS_iPdS_
.globl abs_value
.type abs_value, @function
abs_value:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9abs_valueiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size abs_value, .-abs_value
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "abs_value"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq abs_value(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "abs_value.hip"
.globl _Z24__device_stub__abs_valueiPdS_ # -- Begin function _Z24__device_stub__abs_valueiPdS_
.p2align 4, 0x90
.type _Z24__device_stub__abs_valueiPdS_,@function
_Z24__device_stub__abs_valueiPdS_: # @_Z24__device_stub__abs_valueiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9abs_valueiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__abs_valueiPdS_, .Lfunc_end0-_Z24__device_stub__abs_valueiPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9abs_valueiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9abs_valueiPdS_,@object # @_Z9abs_valueiPdS_
.section .rodata,"a",@progbits
.globl _Z9abs_valueiPdS_
.p2align 3, 0x0
_Z9abs_valueiPdS_:
.quad _Z24__device_stub__abs_valueiPdS_
.size _Z9abs_valueiPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9abs_valueiPdS_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__abs_valueiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9abs_valueiPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*Done with cpu version of convolution which can be scaled to any number of filters of
size 5x5. Maxpooling done with size 2x2. */
/*Implemented 2 layers of conv2d and maxpool using single 1D array */
/*implemented two dense layers*/
/*To do: measure time taken*/
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include<time.h>
int Maxpooling(int a, int b, int c, int d){
int temp,i;
temp = a;
if(b> c && b>d && b> temp){
temp = b;
// printf("temp is b\n");
}
if(c>b && c>d && c> temp){
temp = c;
//printf("temp is c\n");
}
if(d> c && d>b && d> temp){
temp = d;
// printf("temp is d\n");
}
// printf("temp is a\n");
return temp;
}
int main( int argc, char **argv )
{
int xsize, filterdim, numfilters, numfilters1, numweights, numweights1;
xsize = 28;
filterdim =5;
numfilters=32;
numfilters1=64;
numweights = 64;
numweights1 = 10;
/******num bytes required for the initial input********/
int numbytes = xsize * xsize * sizeof( int );
/*******num bytes required for input to conv1********/
int numbytes2 = (xsize-filterdim + 1) * (xsize - filterdim +1);
/*********num bytes required for the input to conv2****/
int numbytes3 = ((xsize-filterdim + 1)/2 -filterdim + 1) * ((xsize-filterdim + 1)/2 -filterdim + 1);
/************num of bytes required for first weight matrix**************/
int numbytes4 = numfilters1*numweights*numbytes3/4;
/************num of bytes required for second weight matrix************/
int numbytes5 = numweights*numweights1;
/*****Original input - pic*************/
unsigned int *pic = (unsigned int *)malloc(numbytes);
/*****filter of the first conv layer*****/
unsigned int filter[numfilters*filterdim*filterdim];
/*******filter for the second conv layer*******/
unsigned int filter2[numfilters1*numfilters*filterdim*filterdim];
/*********weight matrix for the first dense layer**********/
unsigned int weight1[numbytes4];
/*********weight matrix for the second dense layer**********/
unsigned int weight2[numbytes5];
int result[numfilters*numbytes2];
int result2[numfilters1*numbytes3];
int maxpool[numfilters*(((xsize-filterdim + 1)*(xsize-filterdim + 1))/4)];
int maxpool2[numfilters1*(numbytes3/4)];
int dense1[numweights];
int dense2[numweights1];
int i, j;
int count;
int sum1,k,l;
int dimx;
dimx = numfilters1*(numbytes3/4);
/*************Should read in input**********/
for (i=0; i<xsize; i++) {
for (j=0; j<xsize; j++) {
pic[i*xsize + j] = 1;
// printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
}
// printf("\n");
}
/******should read in filters*********/
for(int k=0;k<numfilters;k++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
// printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
}
}
}
for(int k=0;k<numfilters1;k++){
for(int m= 0; m<numfilters;m++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
// printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
}
}
}
// printf("\n");
}
/*********First weight matrix**************/
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
weight1[l*dimx+i] = 1;
// printf("element1 : %d\n", l*dimx+i);
}
}
/**********Second weight matrix**************/
for(l=0;l<numweights1;l++){
for(i=0;i<numweights;i++){
weight2[l*numweights+i] = 1;
// printf("element2 : %d\n", l*numweights+i);
}
}
clock_t start, end;
start = clock();
/*****Operations of first convolutional layer******/
for(l=0; l < numfilters; l++){
count = 0;
for (i = 0; i < xsize - filterdim +1; i++){
for (j = 0; j < xsize - filterdim+1; j++){
k =0;
sum1 = (filter[l*(filterdim*filterdim) + k])*pic[ xsize * (i) + j ] + (filter[l*(filterdim*filterdim) + k+1])*pic[ xsize*(i) + (j+1) ]
+ filter[l*(filterdim*filterdim)+ k+2]*pic[ xsize * (i)+(j+2)] + filter[l*(filterdim*filterdim) +k+3]*pic[xsize * (i)+(j+3)]
+ filter[l*(filterdim*filterdim) +k+4]*pic[ xsize * (i)+(j+4)]+ filter[l*(filterdim*filterdim) + k+5]*pic[ xsize*(i+1)+(j) ]
+ filter[l*(filterdim*filterdim) +k+6]*pic[ xsize * (i+1) + (j+1) ] + filter[l*(filterdim*filterdim) + k+7]*pic[ xsize*(i+1) + (j+2) ] +
filter[l*(filterdim*filterdim) +k+8]*pic[ xsize*(i+1) + (j+3) ] + filter[l*(filterdim*filterdim) +k+9]*pic[ xsize*(i+1) + (j+4) ] +
filter[l*(filterdim*filterdim) +k+10]*pic[ xsize*(i+2) + (j) ] + filter[l*(filterdim*filterdim) +k+11]*pic[ xsize * (i+2) + (j+1) ] +
filter[l*(filterdim*filterdim) +k+12]*pic[ xsize*(i+2) + (j+2)] + filter[l*(filterdim*filterdim) +k+13]*pic[ xsize*(i+2) + (j+3)]
+filter[l*(filterdim*filterdim) +k+14]*pic[ xsize*(i+2) + (j+4)] + filter[l*(filterdim*filterdim) +k+15]*pic[ xsize*(i+3) + (j)]
+ filter[l*(filterdim*filterdim) +k+16]*pic[ xsize*(i+3) + (j+1)] + filter[l*(filterdim*filterdim) +k+17]*pic[ xsize*(i+3) + (j+2)]
+ filter[l*(filterdim*filterdim) +k+18]*pic[ xsize*(i+3) + (j+3)] + filter[l*(filterdim*filterdim) +k+19]*pic[ xsize*(i+3) + (j+4)]
+ filter[l*(filterdim*filterdim) +k+20]*pic[ xsize*(i+4) + (j)] +filter[l*(filterdim*filterdim) +k+21]*pic[ xsize*(i+3) + (j+1)]
+ filter[l*(filterdim*filterdim) +k+22]*pic[ xsize*(i+4) + (j+2)] + filter[l*(filterdim*filterdim) +k+23]*pic[ xsize*(i+4) + (j+3)]
+ filter[l*(filterdim*filterdim) + k+24]*pic[ xsize*(i+4) + (j+4)];
result[l*numbytes2 +count] = sum1;
// printf("result[%d][%d]=%d\t",l,count,result[l*numbytes2 + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/***************Maxpool***************************/
for(l=0; l<numfilters; l++){
count =0;
for(j=0;j<(xsize-filterdim + 1);j+=2){
for(i=0;i<(xsize-filterdim + 1);i+=2){
maxpool[l*(numbytes2/4) + count] =
Maxpooling(result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+1],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)+1]);
printf("Maxpool[%d][%d] : %d \t",l,count ,maxpool[l*(numbytes2/4) + count]);
count+=1;
}
printf("\n");
}
printf("\n\n\n");
}
/******Operations of second convolutional layer*******/
int m;
int dim = (xsize-filterdim + 1)/2;
dimx = (xsize-filterdim + 1)/2 -filterdim + 1;
printf("dim: %d ; dimx: %d\n", dim,dimx);
for(l=0; l < numfilters1; l++){
for (i = 0; i < dimx; i++){
for (j = 0; j < dimx; j++){
k =0;
sum1 =0;
for(m=0;m<numfilters;m++){
sum1 += (filter2[l*(numfilters*filterdim*filterdim) + k])*maxpool[ (m*dim*dim)+ dim * (i) + j ] + (filter2[l*(numfilters*filterdim*filterdim) + k+1])*maxpool[(m*dim*dim)+ dim*(i) + (j+1) ]
+ filter2[l*(numfilters*filterdim*filterdim)+ k+2]*maxpool[(m*dim*dim)+ dim * (i)+(j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+3]*maxpool[(m*dim*dim)+dim * (i)+(j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+4]*maxpool[ (m*dim*dim)+dim * (i)+(j+4)]+ filter2[l*(numfilters*filterdim*filterdim) + k+5]*maxpool[(m*dim*dim)+ dim*(i+1)+(j) ]
+ filter2[l*(numfilters*filterdim*filterdim) +k+6]*maxpool[(m*dim*dim)+ dim * (i+1) + (j+1) ] + filter2[l*(numfilters*filterdim*filterdim) + k+7]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+2) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+8]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+3) ] + filter2[l*(numfilters*filterdim*filterdim) +k+9]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+4) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+10]*maxpool[(m*dim*dim)+ dim*(i+2) + (j) ] + filter2[l*(numfilters*filterdim*filterdim) +k+11]*maxpool[(m*dim*dim)+ dim * (i+2) + (j+1) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+12]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+13]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+3)]
+filter2[l*(numfilters*filterdim*filterdim) +k+14]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+4)] + filter2[l*(numfilters*filterdim*filterdim) +k+15]*maxpool[(m*dim*dim)+ dim*(i+3) + (j)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+16]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)] + filter2[l*(numfilters*filterdim*filterdim) +k+17]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+2)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+18]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+3)] + filter2[l*(numfilters*filterdim*filterdim) +k+19]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+4)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+20]*maxpool[(m*dim*dim)+ dim*(i+4) + (j)] +filter2[l*(numfilters*filterdim*filterdim) +k+21]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+22]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+23]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) + k+24]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+4)];
}
result2[l*numbytes3 +i*dimx+j] = sum1;
k+=1;
printf("result2[%d][%d]=%d\t",l,i*dimx+j,result2[l*numbytes3 + i*dimx + j]);
}
printf("\n");
}
printf("\n\n\n");
}
/******Second Maxpool Layer******/
dim =((xsize-filterdim + 1)/2 -filterdim + 1)/2;
printf("dim: %d ;dimx: %d; numbytes3: %d", dim, dimx, numbytes3);
for(l=0; l<numfilters1; l++){
count =0;
for(j=0;j<dimx;j+=2){
for(i=0;i<dimx;i+=2){
maxpool2[l*(numbytes3/4) + count] =
(Maxpooling(result2[l*numbytes3 + j*dimx+i],
result2[l*numbytes3 + j*dimx+i+1],
result2[l*numbytes3 + j*dimx+i+dimx],
result2[l*numbytes3 + j*dimx+i+dimx+1]))/625;
// printf("Maxpool2[%d][%d] : %d \t",l,count ,maxpool2[l*(numbytes3/4) + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/********************First Dense layer**********************/
dimx = numfilters1*(numbytes3/4);
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
dense1[l]+= weight1[l*dimx+i]*maxpool2[i];
}
// printf("dense1[%d]:%d\n",l,dense1[l]);
}
/*************Second Dense Layer***************/
dimx = numweights;
for(l=0;l<numweights1;l++){
for(i=0;i<dimx;i++){
dense2[l]+= weight2[l*dimx+i]*dense1[i];
}
// printf("dense2[%d]:%d\n",l,dense2[l]);
}
end = clock();
printf("time taken by cpu : %f seconds",((double) (end - start)) );
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*Done with cpu version of convolution which can be scaled to any number of filters of
size 5x5. Maxpooling done with size 2x2. */
/*Implemented 2 layers of conv2d and maxpool using single 1D array */
/*implemented two dense layers*/
/*To do: measure time taken*/
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include<time.h>
int Maxpooling(int a, int b, int c, int d){
int temp,i;
temp = a;
if(b> c && b>d && b> temp){
temp = b;
// printf("temp is b\n");
}
if(c>b && c>d && c> temp){
temp = c;
//printf("temp is c\n");
}
if(d> c && d>b && d> temp){
temp = d;
// printf("temp is d\n");
}
// printf("temp is a\n");
return temp;
}
int main( int argc, char **argv )
{
int xsize, filterdim, numfilters, numfilters1, numweights, numweights1;
xsize = 28;
filterdim =5;
numfilters=32;
numfilters1=64;
numweights = 64;
numweights1 = 10;
/******num bytes required for the initial input********/
int numbytes = xsize * xsize * sizeof( int );
/*******num bytes required for input to conv1********/
int numbytes2 = (xsize-filterdim + 1) * (xsize - filterdim +1);
/*********num bytes required for the input to conv2****/
int numbytes3 = ((xsize-filterdim + 1)/2 -filterdim + 1) * ((xsize-filterdim + 1)/2 -filterdim + 1);
/************num of bytes required for first weight matrix**************/
int numbytes4 = numfilters1*numweights*numbytes3/4;
/************num of bytes required for second weight matrix************/
int numbytes5 = numweights*numweights1;
/*****Original input - pic*************/
unsigned int *pic = (unsigned int *)malloc(numbytes);
/*****filter of the first conv layer*****/
unsigned int filter[numfilters*filterdim*filterdim];
/*******filter for the second conv layer*******/
unsigned int filter2[numfilters1*numfilters*filterdim*filterdim];
/*********weight matrix for the first dense layer**********/
unsigned int weight1[numbytes4];
/*********weight matrix for the second dense layer**********/
unsigned int weight2[numbytes5];
int result[numfilters*numbytes2];
int result2[numfilters1*numbytes3];
int maxpool[numfilters*(((xsize-filterdim + 1)*(xsize-filterdim + 1))/4)];
int maxpool2[numfilters1*(numbytes3/4)];
int dense1[numweights];
int dense2[numweights1];
int i, j;
int count;
int sum1,k,l;
int dimx;
dimx = numfilters1*(numbytes3/4);
/*************Should read in input**********/
for (i=0; i<xsize; i++) {
for (j=0; j<xsize; j++) {
pic[i*xsize + j] = 1;
// printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
}
// printf("\n");
}
/******should read in filters*********/
for(int k=0;k<numfilters;k++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
// printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
}
}
}
for(int k=0;k<numfilters1;k++){
for(int m= 0; m<numfilters;m++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
// printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
}
}
}
// printf("\n");
}
/*********First weight matrix**************/
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
weight1[l*dimx+i] = 1;
// printf("element1 : %d\n", l*dimx+i);
}
}
/**********Second weight matrix**************/
for(l=0;l<numweights1;l++){
for(i=0;i<numweights;i++){
weight2[l*numweights+i] = 1;
// printf("element2 : %d\n", l*numweights+i);
}
}
clock_t start, end;
start = clock();
/*****Operations of first convolutional layer******/
for(l=0; l < numfilters; l++){
count = 0;
for (i = 0; i < xsize - filterdim +1; i++){
for (j = 0; j < xsize - filterdim+1; j++){
k =0;
sum1 = (filter[l*(filterdim*filterdim) + k])*pic[ xsize * (i) + j ] + (filter[l*(filterdim*filterdim) + k+1])*pic[ xsize*(i) + (j+1) ]
+ filter[l*(filterdim*filterdim)+ k+2]*pic[ xsize * (i)+(j+2)] + filter[l*(filterdim*filterdim) +k+3]*pic[xsize * (i)+(j+3)]
+ filter[l*(filterdim*filterdim) +k+4]*pic[ xsize * (i)+(j+4)]+ filter[l*(filterdim*filterdim) + k+5]*pic[ xsize*(i+1)+(j) ]
+ filter[l*(filterdim*filterdim) +k+6]*pic[ xsize * (i+1) + (j+1) ] + filter[l*(filterdim*filterdim) + k+7]*pic[ xsize*(i+1) + (j+2) ] +
filter[l*(filterdim*filterdim) +k+8]*pic[ xsize*(i+1) + (j+3) ] + filter[l*(filterdim*filterdim) +k+9]*pic[ xsize*(i+1) + (j+4) ] +
filter[l*(filterdim*filterdim) +k+10]*pic[ xsize*(i+2) + (j) ] + filter[l*(filterdim*filterdim) +k+11]*pic[ xsize * (i+2) + (j+1) ] +
filter[l*(filterdim*filterdim) +k+12]*pic[ xsize*(i+2) + (j+2)] + filter[l*(filterdim*filterdim) +k+13]*pic[ xsize*(i+2) + (j+3)]
+filter[l*(filterdim*filterdim) +k+14]*pic[ xsize*(i+2) + (j+4)] + filter[l*(filterdim*filterdim) +k+15]*pic[ xsize*(i+3) + (j)]
+ filter[l*(filterdim*filterdim) +k+16]*pic[ xsize*(i+3) + (j+1)] + filter[l*(filterdim*filterdim) +k+17]*pic[ xsize*(i+3) + (j+2)]
+ filter[l*(filterdim*filterdim) +k+18]*pic[ xsize*(i+3) + (j+3)] + filter[l*(filterdim*filterdim) +k+19]*pic[ xsize*(i+3) + (j+4)]
+ filter[l*(filterdim*filterdim) +k+20]*pic[ xsize*(i+4) + (j)] +filter[l*(filterdim*filterdim) +k+21]*pic[ xsize*(i+3) + (j+1)]
+ filter[l*(filterdim*filterdim) +k+22]*pic[ xsize*(i+4) + (j+2)] + filter[l*(filterdim*filterdim) +k+23]*pic[ xsize*(i+4) + (j+3)]
+ filter[l*(filterdim*filterdim) + k+24]*pic[ xsize*(i+4) + (j+4)];
result[l*numbytes2 +count] = sum1;
// printf("result[%d][%d]=%d\t",l,count,result[l*numbytes2 + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/***************Maxpool***************************/
for(l=0; l<numfilters; l++){
count =0;
for(j=0;j<(xsize-filterdim + 1);j+=2){
for(i=0;i<(xsize-filterdim + 1);i+=2){
maxpool[l*(numbytes2/4) + count] =
Maxpooling(result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+1],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)+1]);
printf("Maxpool[%d][%d] : %d \t",l,count ,maxpool[l*(numbytes2/4) + count]);
count+=1;
}
printf("\n");
}
printf("\n\n\n");
}
/******Operations of second convolutional layer*******/
int m;
int dim = (xsize-filterdim + 1)/2;
dimx = (xsize-filterdim + 1)/2 -filterdim + 1;
printf("dim: %d ; dimx: %d\n", dim,dimx);
for(l=0; l < numfilters1; l++){
for (i = 0; i < dimx; i++){
for (j = 0; j < dimx; j++){
k =0;
sum1 =0;
for(m=0;m<numfilters;m++){
sum1 += (filter2[l*(numfilters*filterdim*filterdim) + k])*maxpool[ (m*dim*dim)+ dim * (i) + j ] + (filter2[l*(numfilters*filterdim*filterdim) + k+1])*maxpool[(m*dim*dim)+ dim*(i) + (j+1) ]
+ filter2[l*(numfilters*filterdim*filterdim)+ k+2]*maxpool[(m*dim*dim)+ dim * (i)+(j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+3]*maxpool[(m*dim*dim)+dim * (i)+(j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+4]*maxpool[ (m*dim*dim)+dim * (i)+(j+4)]+ filter2[l*(numfilters*filterdim*filterdim) + k+5]*maxpool[(m*dim*dim)+ dim*(i+1)+(j) ]
+ filter2[l*(numfilters*filterdim*filterdim) +k+6]*maxpool[(m*dim*dim)+ dim * (i+1) + (j+1) ] + filter2[l*(numfilters*filterdim*filterdim) + k+7]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+2) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+8]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+3) ] + filter2[l*(numfilters*filterdim*filterdim) +k+9]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+4) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+10]*maxpool[(m*dim*dim)+ dim*(i+2) + (j) ] + filter2[l*(numfilters*filterdim*filterdim) +k+11]*maxpool[(m*dim*dim)+ dim * (i+2) + (j+1) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+12]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+13]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+3)]
+filter2[l*(numfilters*filterdim*filterdim) +k+14]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+4)] + filter2[l*(numfilters*filterdim*filterdim) +k+15]*maxpool[(m*dim*dim)+ dim*(i+3) + (j)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+16]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)] + filter2[l*(numfilters*filterdim*filterdim) +k+17]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+2)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+18]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+3)] + filter2[l*(numfilters*filterdim*filterdim) +k+19]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+4)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+20]*maxpool[(m*dim*dim)+ dim*(i+4) + (j)] +filter2[l*(numfilters*filterdim*filterdim) +k+21]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+22]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+23]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) + k+24]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+4)];
}
result2[l*numbytes3 +i*dimx+j] = sum1;
k+=1;
printf("result2[%d][%d]=%d\t",l,i*dimx+j,result2[l*numbytes3 + i*dimx + j]);
}
printf("\n");
}
printf("\n\n\n");
}
/******Second Maxpool Layer******/
dim =((xsize-filterdim + 1)/2 -filterdim + 1)/2;
printf("dim: %d ;dimx: %d; numbytes3: %d", dim, dimx, numbytes3);
for(l=0; l<numfilters1; l++){
count =0;
for(j=0;j<dimx;j+=2){
for(i=0;i<dimx;i+=2){
maxpool2[l*(numbytes3/4) + count] =
(Maxpooling(result2[l*numbytes3 + j*dimx+i],
result2[l*numbytes3 + j*dimx+i+1],
result2[l*numbytes3 + j*dimx+i+dimx],
result2[l*numbytes3 + j*dimx+i+dimx+1]))/625;
// printf("Maxpool2[%d][%d] : %d \t",l,count ,maxpool2[l*(numbytes3/4) + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/********************First Dense layer**********************/
dimx = numfilters1*(numbytes3/4);
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
dense1[l]+= weight1[l*dimx+i]*maxpool2[i];
}
// printf("dense1[%d]:%d\n",l,dense1[l]);
}
/*************Second Dense Layer***************/
dimx = numweights;
for(l=0;l<numweights1;l++){
for(i=0;i<dimx;i++){
dense2[l]+= weight2[l*dimx+i]*dense1[i];
}
// printf("dense2[%d]:%d\n",l,dense2[l]);
}
end = clock();
printf("time taken by cpu : %f seconds",((double) (end - start)) );
} | .file "tmpxft_00060932_00000000-6_Cpuv9.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10Maxpoolingiiii
.type _Z10Maxpoolingiiii, @function
_Z10Maxpoolingiiii:
.LFB2061:
.cfi_startproc
endbr64
movl %edi, %eax
cmpl %ecx, %edx
movl %ecx, %r8d
cmovge %edx, %r8d
cmpl %esi, %edi
movl %esi, %edi
cmovge %eax, %edi
cmpl %esi, %r8d
cmovl %edi, %eax
cmpl %ecx, %esi
movl %ecx, %r8d
cmovge %esi, %r8d
cmpl %edx, %eax
movl %edx, %edi
cmovge %eax, %edi
cmpl %r8d, %edx
cmovg %edi, %eax
cmpl %edx, %esi
cmovl %edx, %esi
cmpl %ecx, %eax
movl %ecx, %edx
cmovge %eax, %edx
cmpl %esi, %ecx
cmovg %edx, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z10Maxpoolingiiii, .-_Z10Maxpoolingiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Maxpool[%d][%d] : %d \t"
.LC1:
.string "\n"
.LC2:
.string "\n\n\n"
.LC3:
.string "dim: %d ; dimx: %d\n"
.LC4:
.string "result2[%d][%d]=%d\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "dim: %d ;dimx: %d; numbytes3: %d"
.align 8
.LC6:
.string "time taken by cpu : %f seconds"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $3136, %edi
call malloc@PLT
movq %rax, -160(%rbp)
movq %rsp, %rax
.L8:
cmpq %rax, %rsp
je .L9
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L8
.L9:
subq $3200, %rsp
orq $0, 3192(%rsp)
movq %rsp, %rcx
leaq -204800(%rsp), %rax
.L11:
cmpq %rax, %rsp
je .L12
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L11
.L12:
movq %rsp, -208(%rbp)
leaq -262144(%rsp), %rax
.L14:
cmpq %rax, %rsp
je .L15
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L14
.L15:
movq %rsp, %rdi
movq %rsp, %rax
.L17:
cmpq %rax, %rsp
je .L18
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L17
.L18:
subq $2560, %rsp
orq $0, 2552(%rsp)
movq %rsp, %rsi
leaq -73728(%rsp), %rax
.L20:
cmpq %rax, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
movq %rsp, %rbx
leaq -16384(%rsp), %rax
.L23:
cmpq %rax, %rsp
je .L24
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L23
.L24:
movq %rsp, -256(%rbp)
leaq -16384(%rsp), %rax
.L26:
cmpq %rax, %rsp
je .L27
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L26
.L27:
subq $2048, %rsp
orq $0, 2040(%rsp)
movq %rsp, -264(%rbp)
leaq -4096(%rsp), %rax
.L29:
cmpq %rax, %rsp
je .L30
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L29
.L30:
movq %rsp, -280(%rbp)
movq -160(%rbp), %rax
leaq 112(%rax), %rdx
leaq 3248(%rax), %r8
.L32:
leaq -112(%rdx), %rax
.L33:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L33
addq $112, %rdx
cmpq %r8, %rdx
jne .L32
movq %rcx, %r14
leaq 100(%rcx), %rdx
addq $3300, %rcx
jmp .L36
.L91:
addq $100, %rdx
cmpq %rcx, %rdx
je .L90
.L36:
leaq -100(%rdx), %rax
.L35:
movl $1, (%rax)
movl $1, 4(%rax)
movl $1, 8(%rax)
movl $1, 12(%rax)
movl $1, 16(%rax)
addq $20, %rax
cmpq %rdx, %rax
jne .L35
jmp .L91
.L90:
movq -208(%rbp), %rax
leaq 3300(%rax), %rcx
leaq 208100(%rax), %r8
jmp .L37
.L92:
addq $100, %rdx
cmpq %rcx, %rdx
je .L39
.L41:
leaq -100(%rdx), %rax
.L38:
movl $1, (%rax)
movl $1, 4(%rax)
movl $1, 8(%rax)
movl $1, 12(%rax)
movl $1, 16(%rax)
addq $20, %rax
cmpq %rdx, %rax
jne .L38
jmp .L92
.L39:
addq $3200, %rcx
cmpq %r8, %rcx
je .L40
.L37:
leaq -3200(%rcx), %rdx
jmp .L41
.L40:
leaq 4096(%rdi), %rdx
addq $266240, %rdi
.L43:
leaq -4096(%rdx), %rax
.L42:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L42
addq $4096, %rdx
cmpq %rdi, %rdx
jne .L43
leaq 256(%rsi), %rdx
addq $2816, %rsi
.L44:
leaq -256(%rdx), %rax
.L45:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L45
addq $256, %rdx
cmpq %rsi, %rdx
jne .L44
call clock@PLT
movq %rax, -272(%rbp)
movl $0, %ecx
movq %r14, %rdx
movq %rbx, -168(%rbp)
movq %rbx, -176(%rbp)
jmp .L47
.L49:
movq -184(%rbp), %rdx
movl -192(%rbp), %ecx
addq $100, %rdx
addl $576, %ecx
addq $2304, -168(%rbp)
cmpl $18432, %ecx
je .L93
.L47:
movl (%rdx), %eax
movl %eax, -72(%rbp)
movl 4(%rdx), %eax
movl %eax, -80(%rbp)
movl 12(%rdx), %eax
movl %eax, -88(%rbp)
movl 8(%rdx), %eax
movl %eax, -92(%rbp)
movl 20(%rdx), %eax
movl %eax, -96(%rbp)
movl 16(%rdx), %eax
movl %eax, -100(%rbp)
movl 28(%rdx), %eax
movl %eax, -104(%rbp)
movl 24(%rdx), %eax
movl %eax, -108(%rbp)
movl 36(%rdx), %eax
movl %eax, -112(%rbp)
movl 32(%rdx), %r14d
movl 44(%rdx), %r13d
movl 40(%rdx), %r12d
movl 52(%rdx), %ebx
movl 48(%rdx), %r11d
movl 60(%rdx), %r10d
movl 56(%rdx), %eax
movl %eax, -116(%rbp)
movl 68(%rdx), %eax
movl %eax, -120(%rbp)
movl 76(%rdx), %eax
movl %eax, -124(%rbp)
movl 72(%rdx), %eax
movl %eax, -128(%rbp)
movl 84(%rdx), %eax
addl 64(%rdx), %eax
movl %eax, -136(%rbp)
movl 80(%rdx), %eax
movl %eax, -132(%rbp)
movl 92(%rdx), %r9d
movl 88(%rdx), %r8d
movl 96(%rdx), %edi
movq -160(%rbp), %rax
leaq 96(%rax), %rsi
movq -168(%rbp), %rax
movq %rax, -144(%rbp)
movl $0, %r15d
movq %rdx, -184(%rbp)
movl %ecx, -192(%rbp)
.L51:
leaq -96(%rsi), %rax
movq -144(%rbp), %rcx
movl %r15d, -148(%rbp)
.L48:
movl -72(%rbp), %edx
imull (%rax), %edx
movl -80(%rbp), %r15d
imull 4(%rax), %r15d
addl %edx, %r15d
movl -88(%rbp), %edx
imull 12(%rax), %edx
addl %r15d, %edx
movl -92(%rbp), %r15d
imull 8(%rax), %r15d
addl %edx, %r15d
movl -96(%rbp), %edx
imull 112(%rax), %edx
addl %r15d, %edx
movl -100(%rbp), %r15d
imull 16(%rax), %r15d
addl %edx, %r15d
movl -104(%rbp), %edx
imull 120(%rax), %edx
addl %r15d, %edx
movl -108(%rbp), %r15d
imull 116(%rax), %r15d
addl %edx, %r15d
movl -112(%rbp), %edx
imull 128(%rax), %edx
addl %r15d, %edx
movl %r14d, %r15d
imull 124(%rax), %r15d
addl %edx, %r15d
movl %r13d, %edx
imull 228(%rax), %edx
addl %r15d, %edx
movl %r12d, %r15d
imull 224(%rax), %r15d
addl %edx, %r15d
movl %ebx, %edx
imull 236(%rax), %edx
addl %r15d, %edx
movl %r11d, %r15d
imull 232(%rax), %r15d
addl %edx, %r15d
movl %r10d, %edx
imull 336(%rax), %edx
addl %r15d, %edx
movl -116(%rbp), %r15d
imull 240(%rax), %r15d
addl %edx, %r15d
movl -120(%rbp), %edx
imull 344(%rax), %edx
addl %r15d, %edx
movl -124(%rbp), %r15d
imull 352(%rax), %r15d
addl %edx, %r15d
movl -128(%rbp), %edx
imull 348(%rax), %edx
addl %r15d, %edx
movl -136(%rbp), %r15d
imull 340(%rax), %r15d
addl %edx, %r15d
movl -132(%rbp), %edx
imull 448(%rax), %edx
addl %r15d, %edx
movl %r9d, %r15d
imull 460(%rax), %r15d
addl %edx, %r15d
movl %r8d, %edx
imull 456(%rax), %edx
addl %r15d, %edx
movl %edi, %r15d
imull 464(%rax), %r15d
addl %r15d, %edx
movl %edx, (%rcx)
addq $4, %rax
addq $4, %rcx
cmpq %rsi, %rax
jne .L48
movl -148(%rbp), %r15d
addl $24, %r15d
addq $96, -144(%rbp)
addq $112, %rsi
cmpl $576, %r15d
jne .L51
jmp .L49
.L93:
movq -176(%rbp), %rbx
movq -264(%rbp), %r14
movl $0, %r12d
movl $0, %r15d
jmp .L50
.L53:
movq -80(%rbp), %r12
movq -88(%rbp), %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addq $576, %r14
addq $576, %r12
cmpl $32, %r15d
je .L54
.L50:
leaq (%rbx,%r12,4), %rax
movq %rax, -72(%rbp)
movl $12, %r13d
movq %r12, -80(%rbp)
movq %rbx, -88(%rbp)
.L55:
leaq -12(%r13), %r12
movq -72(%rbp), %rbx
.L52:
movl 100(%rbx), %ecx
movl 96(%rbx), %edx
movl 4(%rbx), %esi
movl (%rbx), %edi
call _Z10Maxpoolingiiii
movl %eax, %r8d
movl %eax, (%r14,%r12,4)
movl %r12d, %ecx
movl %r15d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
addq $8, %rbx
cmpq %r13, %r12
jne .L52
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $192, -72(%rbp)
addq $12, %r13
cmpq $156, %r13
jne .L55
jmp .L53
.L54:
movl $8, %ecx
movl $12, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L56
.L58:
movq -224(%rbp), %r12
movq -232(%rbp), %r13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
addq $48, %r13
cmpq $8, %r12
je .L59
.L62:
movq %r12, %rax
salq $5, %rax
movq -248(%rbp), %rbx
addq %rbx, %rax
movq %rax, -200(%rbp)
leal 0(,%r12,8), %eax
movl %eax, -152(%rbp)
movq $1, -176(%rbp)
movq %r13, %rbx
movq %r12, -224(%rbp)
movq %r13, -232(%rbp)
movq -240(%rbp), %r15
.L60:
movl -176(%rbp), %eax
movl %eax, -184(%rbp)
movq -208(%rbp), %rax
movl (%rax,%r15), %edi
movl %edi, -80(%rbp)
movl 4(%rax,%r15), %edi
movl %edi, -88(%rbp)
movl 12(%rax,%r15), %edi
movl %edi, -92(%rbp)
movl 8(%rax,%r15), %edi
movl %edi, -96(%rbp)
movl 20(%rax,%r15), %edi
movl %edi, -100(%rbp)
movl 16(%rax,%r15), %edi
movl %edi, -104(%rbp)
movl 28(%rax,%r15), %edi
movl %edi, -108(%rbp)
movl 24(%rax,%r15), %edi
movl %edi, -112(%rbp)
movl 36(%rax,%r15), %edi
movl %edi, -116(%rbp)
movl 32(%rax,%r15), %edi
movl %edi, -120(%rbp)
movl 44(%rax,%r15), %edi
movl %edi, -124(%rbp)
movl 40(%rax,%r15), %edi
movl %edi, -128(%rbp)
movl 52(%rax,%r15), %edi
movl %edi, -132(%rbp)
movl 48(%rax,%r15), %edi
movl %edi, -136(%rbp)
movl 60(%rax,%r15), %edi
movl %edi, -144(%rbp)
movl 56(%rax,%r15), %edi
movl %edi, -148(%rbp)
movl 68(%rax,%r15), %esi
movl %esi, -160(%rbp)
movl 76(%rax,%r15), %edi
movl %edi, -168(%rbp)
movl 72(%rax,%r15), %r14d
movl 84(%rax,%r15), %r10d
addl 64(%rax,%r15), %r10d
movl 80(%rax,%r15), %r13d
movl 92(%rax,%r15), %r12d
movl 88(%rax,%r15), %r9d
movl 96(%rax,%r15), %r11d
leaq -18432(%rbx), %rax
leaq -18384(%rbx), %rsi
leaq -18332(%rbx), %rcx
leaq -18288(%rbx), %rdx
leaq -18240(%rbx), %rdi
movl $0, -72(%rbp)
movq %r15, -192(%rbp)
.L57:
movl -80(%rbp), %r8d
imull (%rax), %r8d
movl -88(%rbp), %r15d
imull 4(%rax), %r15d
addl %r8d, %r15d
movl -92(%rbp), %r8d
imull 12(%rax), %r8d
addl %r15d, %r8d
movl -96(%rbp), %r15d
imull 8(%rax), %r15d
addl %r8d, %r15d
movl -100(%rbp), %r8d
imull (%rsi), %r8d
addl %r15d, %r8d
movl -104(%rbp), %r15d
imull 16(%rax), %r15d
addl %r8d, %r15d
movl -108(%rbp), %r8d
imull 8(%rsi), %r8d
addl %r15d, %r8d
movl -112(%rbp), %r15d
imull 4(%rsi), %r15d
addl %r8d, %r15d
movl -116(%rbp), %r8d
imull 16(%rsi), %r8d
addl %r15d, %r8d
movl -120(%rbp), %r15d
imull 12(%rsi), %r15d
addl %r8d, %r15d
movl -124(%rbp), %r8d
imull (%rcx), %r8d
addl %r15d, %r8d
movl -128(%rbp), %r15d
imull -4(%rcx), %r15d
addl %r8d, %r15d
movl -132(%rbp), %r8d
imull 8(%rcx), %r8d
addl %r15d, %r8d
movl -136(%rbp), %r15d
imull 4(%rcx), %r15d
addl %r8d, %r15d
movl -144(%rbp), %r8d
imull (%rdx), %r8d
addl %r15d, %r8d
movl -148(%rbp), %r15d
imull 12(%rcx), %r15d
addl %r8d, %r15d
movl -160(%rbp), %r8d
imull 8(%rdx), %r8d
addl %r15d, %r8d
movl -168(%rbp), %r15d
imull 16(%rdx), %r15d
addl %r8d, %r15d
movl %r14d, %r8d
imull 12(%rdx), %r8d
addl %r15d, %r8d
movl %r10d, %r15d
imull 4(%rdx), %r15d
addl %r8d, %r15d
movl %r13d, %r8d
imull (%rdi), %r8d
addl %r15d, %r8d
movl %r12d, %r15d
imull 12(%rdi), %r15d
addl %r8d, %r15d
movl %r9d, %r8d
imull 8(%rdi), %r8d
addl %r15d, %r8d
movl %r11d, %r15d
imull 16(%rdi), %r15d
addl %r15d, %r8d
movl -72(%rbp), %r15d
addl %r15d, %r8d
movl %r8d, -72(%rbp)
addq $576, %rax
addq $576, %rsi
addq $576, %rcx
addq $576, %rdx
addq $576, %rdi
cmpq %rbx, %rax
jne .L57
movq -192(%rbp), %r15
movq -200(%rbp), %rax
movq -176(%rbp), %r14
movl %r8d, -4(%rax,%r14,4)
movl -184(%rbp), %eax
movl -152(%rbp), %edi
leal -1(%rax,%rdi), %ecx
movl -212(%rbp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
movq %r14, -176(%rbp)
addq $4, %rbx
cmpq $9, %r14
jne .L60
jmp .L58
.L59:
movq -288(%rbp), %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $64, %rbx
je .L61
.L56:
movl %ebx, -212(%rbp)
movq -264(%rbp), %rax
leaq 18432(%rax), %r13
leaq (%rbx,%rbx,4), %rax
leaq (%rax,%rax,4), %rax
salq $7, %rax
movq %rax, -240(%rbp)
movq %rbx, %rax
salq $8, %rax
movq -256(%rbp), %rsi
leaq (%rsi,%rax), %r14
movl $0, %r12d
movq %r14, -248(%rbp)
movq %rbx, -288(%rbp)
jmp .L62
.L61:
movl $64, %r8d
movl $8, %ecx
movl $4, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -280(%rbp), %rax
movq %rax, -80(%rbp)
movq -256(%rbp), %r14
addq $32, %r14
movl $0, %r15d
jmp .L63
.L65:
addl $16, %r15d
addq $64, -80(%rbp)
addq $256, %r14
cmpl $1024, %r15d
je .L73
.L63:
movq %r14, %r13
movq -80(%rbp), %rax
movq %rax, -88(%rbp)
movl $0, -72(%rbp)
.L67:
leaq -32(%r13), %rbx
movq -88(%rbp), %r12
.L64:
movl 36(%rbx), %ecx
movl 32(%rbx), %edx
movl 4(%rbx), %esi
movl (%rbx), %edi
call _Z10Maxpoolingiiii
movl %eax, %edx
cltq
imulq $1759218605, %rax, %rax
sarq $40, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, (%r12)
addq $8, %rbx
addq $4, %r12
cmpq %rbx, %r13
jne .L64
addl $4, -72(%rbp)
movl -72(%rbp), %eax
addq $16, -88(%rbp)
addq $64, %r13
cmpl $16, %eax
jne .L67
jmp .L65
.L73:
movl $64, %edx
.L66:
movl %r15d, %eax
.L68:
subl $1, %eax
jne .L68
subl $1, %edx
jne .L66
movl $10, %edx
.L69:
movl $64, %eax
.L70:
subl $1, %eax
jne .L70
subl $1, %edx
jne .L69
call clock@PLT
movq -272(%rbp), %rbx
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L94
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L94:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*Done with cpu version of convolution which can be scaled to any number of filters of
size 5x5. Maxpooling done with size 2x2. */
/*Implemented 2 layers of conv2d and maxpool using single 1D array */
/*implemented two dense layers*/
/*To do: measure time taken*/
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include<time.h>
int Maxpooling(int a, int b, int c, int d){
int temp,i;
temp = a;
if(b> c && b>d && b> temp){
temp = b;
// printf("temp is b\n");
}
if(c>b && c>d && c> temp){
temp = c;
//printf("temp is c\n");
}
if(d> c && d>b && d> temp){
temp = d;
// printf("temp is d\n");
}
// printf("temp is a\n");
return temp;
}
int main( int argc, char **argv )
{
int xsize, filterdim, numfilters, numfilters1, numweights, numweights1;
xsize = 28;
filterdim =5;
numfilters=32;
numfilters1=64;
numweights = 64;
numweights1 = 10;
/******num bytes required for the initial input********/
int numbytes = xsize * xsize * sizeof( int );
/*******num bytes required for input to conv1********/
int numbytes2 = (xsize-filterdim + 1) * (xsize - filterdim +1);
/*********num bytes required for the input to conv2****/
int numbytes3 = ((xsize-filterdim + 1)/2 -filterdim + 1) * ((xsize-filterdim + 1)/2 -filterdim + 1);
/************num of bytes required for first weight matrix**************/
int numbytes4 = numfilters1*numweights*numbytes3/4;
/************num of bytes required for second weight matrix************/
int numbytes5 = numweights*numweights1;
/*****Original input - pic*************/
unsigned int *pic = (unsigned int *)malloc(numbytes);
/*****filter of the first conv layer*****/
unsigned int filter[numfilters*filterdim*filterdim];
/*******filter for the second conv layer*******/
unsigned int filter2[numfilters1*numfilters*filterdim*filterdim];
/*********weight matrix for the first dense layer**********/
unsigned int weight1[numbytes4];
/*********weight matrix for the second dense layer**********/
unsigned int weight2[numbytes5];
int result[numfilters*numbytes2];
int result2[numfilters1*numbytes3];
int maxpool[numfilters*(((xsize-filterdim + 1)*(xsize-filterdim + 1))/4)];
int maxpool2[numfilters1*(numbytes3/4)];
int dense1[numweights];
int dense2[numweights1];
int i, j;
int count;
int sum1,k,l;
int dimx;
dimx = numfilters1*(numbytes3/4);
/*************Should read in input**********/
for (i=0; i<xsize; i++) {
for (j=0; j<xsize; j++) {
pic[i*xsize + j] = 1;
// printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
}
// printf("\n");
}
/******should read in filters*********/
for(int k=0;k<numfilters;k++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
// printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
}
}
}
for(int k=0;k<numfilters1;k++){
for(int m= 0; m<numfilters;m++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
// printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
}
}
}
// printf("\n");
}
/*********First weight matrix**************/
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
weight1[l*dimx+i] = 1;
// printf("element1 : %d\n", l*dimx+i);
}
}
/**********Second weight matrix**************/
for(l=0;l<numweights1;l++){
for(i=0;i<numweights;i++){
weight2[l*numweights+i] = 1;
// printf("element2 : %d\n", l*numweights+i);
}
}
clock_t start, end;
start = clock();
/*****Operations of first convolutional layer******/
for(l=0; l < numfilters; l++){
count = 0;
for (i = 0; i < xsize - filterdim +1; i++){
for (j = 0; j < xsize - filterdim+1; j++){
k =0;
sum1 = (filter[l*(filterdim*filterdim) + k])*pic[ xsize * (i) + j ] + (filter[l*(filterdim*filterdim) + k+1])*pic[ xsize*(i) + (j+1) ]
+ filter[l*(filterdim*filterdim)+ k+2]*pic[ xsize * (i)+(j+2)] + filter[l*(filterdim*filterdim) +k+3]*pic[xsize * (i)+(j+3)]
+ filter[l*(filterdim*filterdim) +k+4]*pic[ xsize * (i)+(j+4)]+ filter[l*(filterdim*filterdim) + k+5]*pic[ xsize*(i+1)+(j) ]
+ filter[l*(filterdim*filterdim) +k+6]*pic[ xsize * (i+1) + (j+1) ] + filter[l*(filterdim*filterdim) + k+7]*pic[ xsize*(i+1) + (j+2) ] +
filter[l*(filterdim*filterdim) +k+8]*pic[ xsize*(i+1) + (j+3) ] + filter[l*(filterdim*filterdim) +k+9]*pic[ xsize*(i+1) + (j+4) ] +
filter[l*(filterdim*filterdim) +k+10]*pic[ xsize*(i+2) + (j) ] + filter[l*(filterdim*filterdim) +k+11]*pic[ xsize * (i+2) + (j+1) ] +
filter[l*(filterdim*filterdim) +k+12]*pic[ xsize*(i+2) + (j+2)] + filter[l*(filterdim*filterdim) +k+13]*pic[ xsize*(i+2) + (j+3)]
+filter[l*(filterdim*filterdim) +k+14]*pic[ xsize*(i+2) + (j+4)] + filter[l*(filterdim*filterdim) +k+15]*pic[ xsize*(i+3) + (j)]
+ filter[l*(filterdim*filterdim) +k+16]*pic[ xsize*(i+3) + (j+1)] + filter[l*(filterdim*filterdim) +k+17]*pic[ xsize*(i+3) + (j+2)]
+ filter[l*(filterdim*filterdim) +k+18]*pic[ xsize*(i+3) + (j+3)] + filter[l*(filterdim*filterdim) +k+19]*pic[ xsize*(i+3) + (j+4)]
+ filter[l*(filterdim*filterdim) +k+20]*pic[ xsize*(i+4) + (j)] +filter[l*(filterdim*filterdim) +k+21]*pic[ xsize*(i+3) + (j+1)]
+ filter[l*(filterdim*filterdim) +k+22]*pic[ xsize*(i+4) + (j+2)] + filter[l*(filterdim*filterdim) +k+23]*pic[ xsize*(i+4) + (j+3)]
+ filter[l*(filterdim*filterdim) + k+24]*pic[ xsize*(i+4) + (j+4)];
result[l*numbytes2 +count] = sum1;
// printf("result[%d][%d]=%d\t",l,count,result[l*numbytes2 + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/***************Maxpool***************************/
for(l=0; l<numfilters; l++){
count =0;
for(j=0;j<(xsize-filterdim + 1);j+=2){
for(i=0;i<(xsize-filterdim + 1);i+=2){
maxpool[l*(numbytes2/4) + count] =
Maxpooling(result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+1],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)+1]);
printf("Maxpool[%d][%d] : %d \t",l,count ,maxpool[l*(numbytes2/4) + count]);
count+=1;
}
printf("\n");
}
printf("\n\n\n");
}
/******Operations of second convolutional layer*******/
int m;
int dim = (xsize-filterdim + 1)/2;
dimx = (xsize-filterdim + 1)/2 -filterdim + 1;
printf("dim: %d ; dimx: %d\n", dim,dimx);
for(l=0; l < numfilters1; l++){
for (i = 0; i < dimx; i++){
for (j = 0; j < dimx; j++){
k =0;
sum1 =0;
for(m=0;m<numfilters;m++){
sum1 += (filter2[l*(numfilters*filterdim*filterdim) + k])*maxpool[ (m*dim*dim)+ dim * (i) + j ] + (filter2[l*(numfilters*filterdim*filterdim) + k+1])*maxpool[(m*dim*dim)+ dim*(i) + (j+1) ]
+ filter2[l*(numfilters*filterdim*filterdim)+ k+2]*maxpool[(m*dim*dim)+ dim * (i)+(j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+3]*maxpool[(m*dim*dim)+dim * (i)+(j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+4]*maxpool[ (m*dim*dim)+dim * (i)+(j+4)]+ filter2[l*(numfilters*filterdim*filterdim) + k+5]*maxpool[(m*dim*dim)+ dim*(i+1)+(j) ]
+ filter2[l*(numfilters*filterdim*filterdim) +k+6]*maxpool[(m*dim*dim)+ dim * (i+1) + (j+1) ] + filter2[l*(numfilters*filterdim*filterdim) + k+7]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+2) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+8]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+3) ] + filter2[l*(numfilters*filterdim*filterdim) +k+9]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+4) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+10]*maxpool[(m*dim*dim)+ dim*(i+2) + (j) ] + filter2[l*(numfilters*filterdim*filterdim) +k+11]*maxpool[(m*dim*dim)+ dim * (i+2) + (j+1) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+12]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+13]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+3)]
+filter2[l*(numfilters*filterdim*filterdim) +k+14]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+4)] + filter2[l*(numfilters*filterdim*filterdim) +k+15]*maxpool[(m*dim*dim)+ dim*(i+3) + (j)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+16]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)] + filter2[l*(numfilters*filterdim*filterdim) +k+17]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+2)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+18]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+3)] + filter2[l*(numfilters*filterdim*filterdim) +k+19]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+4)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+20]*maxpool[(m*dim*dim)+ dim*(i+4) + (j)] +filter2[l*(numfilters*filterdim*filterdim) +k+21]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+22]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+23]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) + k+24]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+4)];
}
result2[l*numbytes3 +i*dimx+j] = sum1;
k+=1;
printf("result2[%d][%d]=%d\t",l,i*dimx+j,result2[l*numbytes3 + i*dimx + j]);
}
printf("\n");
}
printf("\n\n\n");
}
/******Second Maxpool Layer******/
dim =((xsize-filterdim + 1)/2 -filterdim + 1)/2;
printf("dim: %d ;dimx: %d; numbytes3: %d", dim, dimx, numbytes3);
for(l=0; l<numfilters1; l++){
count =0;
for(j=0;j<dimx;j+=2){
for(i=0;i<dimx;i+=2){
maxpool2[l*(numbytes3/4) + count] =
(Maxpooling(result2[l*numbytes3 + j*dimx+i],
result2[l*numbytes3 + j*dimx+i+1],
result2[l*numbytes3 + j*dimx+i+dimx],
result2[l*numbytes3 + j*dimx+i+dimx+1]))/625;
// printf("Maxpool2[%d][%d] : %d \t",l,count ,maxpool2[l*(numbytes3/4) + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/********************First Dense layer**********************/
dimx = numfilters1*(numbytes3/4);
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
dense1[l]+= weight1[l*dimx+i]*maxpool2[i];
}
// printf("dense1[%d]:%d\n",l,dense1[l]);
}
/*************Second Dense Layer***************/
dimx = numweights;
for(l=0;l<numweights1;l++){
for(i=0;i<dimx;i++){
dense2[l]+= weight2[l*dimx+i]*dense1[i];
}
// printf("dense2[%d]:%d\n",l,dense2[l]);
}
end = clock();
printf("time taken by cpu : %f seconds",((double) (end - start)) );
} | /*Done with cpu version of convolution which can be scaled to any number of filters of
size 5x5. Maxpooling done with size 2x2. */
/*Implemented 2 layers of conv2d and maxpool using single 1D array */
/*implemented two dense layers*/
/*To do: measure time taken*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include<time.h>
int Maxpooling(int a, int b, int c, int d){
int temp,i;
temp = a;
if(b> c && b>d && b> temp){
temp = b;
// printf("temp is b\n");
}
if(c>b && c>d && c> temp){
temp = c;
//printf("temp is c\n");
}
if(d> c && d>b && d> temp){
temp = d;
// printf("temp is d\n");
}
// printf("temp is a\n");
return temp;
}
int main( int argc, char **argv )
{
int xsize, filterdim, numfilters, numfilters1, numweights, numweights1;
xsize = 28;
filterdim =5;
numfilters=32;
numfilters1=64;
numweights = 64;
numweights1 = 10;
/******num bytes required for the initial input********/
int numbytes = xsize * xsize * sizeof( int );
/*******num bytes required for input to conv1********/
int numbytes2 = (xsize-filterdim + 1) * (xsize - filterdim +1);
/*********num bytes required for the input to conv2****/
int numbytes3 = ((xsize-filterdim + 1)/2 -filterdim + 1) * ((xsize-filterdim + 1)/2 -filterdim + 1);
/************num of bytes required for first weight matrix**************/
int numbytes4 = numfilters1*numweights*numbytes3/4;
/************num of bytes required for second weight matrix************/
int numbytes5 = numweights*numweights1;
/*****Original input - pic*************/
unsigned int *pic = (unsigned int *)malloc(numbytes);
/*****filter of the first conv layer*****/
unsigned int filter[numfilters*filterdim*filterdim];
/*******filter for the second conv layer*******/
unsigned int filter2[numfilters1*numfilters*filterdim*filterdim];
/*********weight matrix for the first dense layer**********/
unsigned int weight1[numbytes4];
/*********weight matrix for the second dense layer**********/
unsigned int weight2[numbytes5];
int result[numfilters*numbytes2];
int result2[numfilters1*numbytes3];
int maxpool[numfilters*(((xsize-filterdim + 1)*(xsize-filterdim + 1))/4)];
int maxpool2[numfilters1*(numbytes3/4)];
int dense1[numweights];
int dense2[numweights1];
int i, j;
int count;
int sum1,k,l;
int dimx;
dimx = numfilters1*(numbytes3/4);
/*************Should read in input**********/
for (i=0; i<xsize; i++) {
for (j=0; j<xsize; j++) {
pic[i*xsize + j] = 1;
// printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
}
// printf("\n");
}
/******should read in filters*********/
for(int k=0;k<numfilters;k++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
// printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
}
}
}
for(int k=0;k<numfilters1;k++){
for(int m= 0; m<numfilters;m++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
// printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
}
}
}
// printf("\n");
}
/*********First weight matrix**************/
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
weight1[l*dimx+i] = 1;
// printf("element1 : %d\n", l*dimx+i);
}
}
/**********Second weight matrix**************/
for(l=0;l<numweights1;l++){
for(i=0;i<numweights;i++){
weight2[l*numweights+i] = 1;
// printf("element2 : %d\n", l*numweights+i);
}
}
clock_t start, end;
start = clock();
/*****Operations of first convolutional layer******/
for(l=0; l < numfilters; l++){
count = 0;
for (i = 0; i < xsize - filterdim +1; i++){
for (j = 0; j < xsize - filterdim+1; j++){
k =0;
sum1 = (filter[l*(filterdim*filterdim) + k])*pic[ xsize * (i) + j ] + (filter[l*(filterdim*filterdim) + k+1])*pic[ xsize*(i) + (j+1) ]
+ filter[l*(filterdim*filterdim)+ k+2]*pic[ xsize * (i)+(j+2)] + filter[l*(filterdim*filterdim) +k+3]*pic[xsize * (i)+(j+3)]
+ filter[l*(filterdim*filterdim) +k+4]*pic[ xsize * (i)+(j+4)]+ filter[l*(filterdim*filterdim) + k+5]*pic[ xsize*(i+1)+(j) ]
+ filter[l*(filterdim*filterdim) +k+6]*pic[ xsize * (i+1) + (j+1) ] + filter[l*(filterdim*filterdim) + k+7]*pic[ xsize*(i+1) + (j+2) ] +
filter[l*(filterdim*filterdim) +k+8]*pic[ xsize*(i+1) + (j+3) ] + filter[l*(filterdim*filterdim) +k+9]*pic[ xsize*(i+1) + (j+4) ] +
filter[l*(filterdim*filterdim) +k+10]*pic[ xsize*(i+2) + (j) ] + filter[l*(filterdim*filterdim) +k+11]*pic[ xsize * (i+2) + (j+1) ] +
filter[l*(filterdim*filterdim) +k+12]*pic[ xsize*(i+2) + (j+2)] + filter[l*(filterdim*filterdim) +k+13]*pic[ xsize*(i+2) + (j+3)]
+filter[l*(filterdim*filterdim) +k+14]*pic[ xsize*(i+2) + (j+4)] + filter[l*(filterdim*filterdim) +k+15]*pic[ xsize*(i+3) + (j)]
+ filter[l*(filterdim*filterdim) +k+16]*pic[ xsize*(i+3) + (j+1)] + filter[l*(filterdim*filterdim) +k+17]*pic[ xsize*(i+3) + (j+2)]
+ filter[l*(filterdim*filterdim) +k+18]*pic[ xsize*(i+3) + (j+3)] + filter[l*(filterdim*filterdim) +k+19]*pic[ xsize*(i+3) + (j+4)]
+ filter[l*(filterdim*filterdim) +k+20]*pic[ xsize*(i+4) + (j)] +filter[l*(filterdim*filterdim) +k+21]*pic[ xsize*(i+3) + (j+1)]
+ filter[l*(filterdim*filterdim) +k+22]*pic[ xsize*(i+4) + (j+2)] + filter[l*(filterdim*filterdim) +k+23]*pic[ xsize*(i+4) + (j+3)]
+ filter[l*(filterdim*filterdim) + k+24]*pic[ xsize*(i+4) + (j+4)];
result[l*numbytes2 +count] = sum1;
// printf("result[%d][%d]=%d\t",l,count,result[l*numbytes2 + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/***************Maxpool***************************/
for(l=0; l<numfilters; l++){
count =0;
for(j=0;j<(xsize-filterdim + 1);j+=2){
for(i=0;i<(xsize-filterdim + 1);i+=2){
maxpool[l*(numbytes2/4) + count] =
Maxpooling(result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+1],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)+1]);
printf("Maxpool[%d][%d] : %d \t",l,count ,maxpool[l*(numbytes2/4) + count]);
count+=1;
}
printf("\n");
}
printf("\n\n\n");
}
/******Operations of second convolutional layer*******/
int m;
int dim = (xsize-filterdim + 1)/2;
dimx = (xsize-filterdim + 1)/2 -filterdim + 1;
printf("dim: %d ; dimx: %d\n", dim,dimx);
for(l=0; l < numfilters1; l++){
for (i = 0; i < dimx; i++){
for (j = 0; j < dimx; j++){
k =0;
sum1 =0;
for(m=0;m<numfilters;m++){
sum1 += (filter2[l*(numfilters*filterdim*filterdim) + k])*maxpool[ (m*dim*dim)+ dim * (i) + j ] + (filter2[l*(numfilters*filterdim*filterdim) + k+1])*maxpool[(m*dim*dim)+ dim*(i) + (j+1) ]
+ filter2[l*(numfilters*filterdim*filterdim)+ k+2]*maxpool[(m*dim*dim)+ dim * (i)+(j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+3]*maxpool[(m*dim*dim)+dim * (i)+(j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+4]*maxpool[ (m*dim*dim)+dim * (i)+(j+4)]+ filter2[l*(numfilters*filterdim*filterdim) + k+5]*maxpool[(m*dim*dim)+ dim*(i+1)+(j) ]
+ filter2[l*(numfilters*filterdim*filterdim) +k+6]*maxpool[(m*dim*dim)+ dim * (i+1) + (j+1) ] + filter2[l*(numfilters*filterdim*filterdim) + k+7]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+2) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+8]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+3) ] + filter2[l*(numfilters*filterdim*filterdim) +k+9]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+4) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+10]*maxpool[(m*dim*dim)+ dim*(i+2) + (j) ] + filter2[l*(numfilters*filterdim*filterdim) +k+11]*maxpool[(m*dim*dim)+ dim * (i+2) + (j+1) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+12]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+13]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+3)]
+filter2[l*(numfilters*filterdim*filterdim) +k+14]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+4)] + filter2[l*(numfilters*filterdim*filterdim) +k+15]*maxpool[(m*dim*dim)+ dim*(i+3) + (j)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+16]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)] + filter2[l*(numfilters*filterdim*filterdim) +k+17]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+2)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+18]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+3)] + filter2[l*(numfilters*filterdim*filterdim) +k+19]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+4)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+20]*maxpool[(m*dim*dim)+ dim*(i+4) + (j)] +filter2[l*(numfilters*filterdim*filterdim) +k+21]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+22]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+23]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) + k+24]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+4)];
}
result2[l*numbytes3 +i*dimx+j] = sum1;
k+=1;
printf("result2[%d][%d]=%d\t",l,i*dimx+j,result2[l*numbytes3 + i*dimx + j]);
}
printf("\n");
}
printf("\n\n\n");
}
/******Second Maxpool Layer******/
dim =((xsize-filterdim + 1)/2 -filterdim + 1)/2;
printf("dim: %d ;dimx: %d; numbytes3: %d", dim, dimx, numbytes3);
for(l=0; l<numfilters1; l++){
count =0;
for(j=0;j<dimx;j+=2){
for(i=0;i<dimx;i+=2){
maxpool2[l*(numbytes3/4) + count] =
(Maxpooling(result2[l*numbytes3 + j*dimx+i],
result2[l*numbytes3 + j*dimx+i+1],
result2[l*numbytes3 + j*dimx+i+dimx],
result2[l*numbytes3 + j*dimx+i+dimx+1]))/625;
// printf("Maxpool2[%d][%d] : %d \t",l,count ,maxpool2[l*(numbytes3/4) + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/********************First Dense layer**********************/
dimx = numfilters1*(numbytes3/4);
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
dense1[l]+= weight1[l*dimx+i]*maxpool2[i];
}
// printf("dense1[%d]:%d\n",l,dense1[l]);
}
/*************Second Dense Layer***************/
dimx = numweights;
for(l=0;l<numweights1;l++){
for(i=0;i<dimx;i++){
dense2[l]+= weight2[l*dimx+i]*dense1[i];
}
// printf("dense2[%d]:%d\n",l,dense2[l]);
}
end = clock();
printf("time taken by cpu : %f seconds",((double) (end - start)) );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*Done with cpu version of convolution which can be scaled to any number of filters of
size 5x5. Maxpooling done with size 2x2. */
/*Implemented 2 layers of conv2d and maxpool using single 1D array */
/*implemented two dense layers*/
/*To do: measure time taken*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include<time.h>
int Maxpooling(int a, int b, int c, int d){
int temp,i;
temp = a;
if(b> c && b>d && b> temp){
temp = b;
// printf("temp is b\n");
}
if(c>b && c>d && c> temp){
temp = c;
//printf("temp is c\n");
}
if(d> c && d>b && d> temp){
temp = d;
// printf("temp is d\n");
}
// printf("temp is a\n");
return temp;
}
int main( int argc, char **argv )
{
int xsize, filterdim, numfilters, numfilters1, numweights, numweights1;
xsize = 28;
filterdim =5;
numfilters=32;
numfilters1=64;
numweights = 64;
numweights1 = 10;
/******num bytes required for the initial input********/
int numbytes = xsize * xsize * sizeof( int );
/*******num bytes required for input to conv1********/
int numbytes2 = (xsize-filterdim + 1) * (xsize - filterdim +1);
/*********num bytes required for the input to conv2****/
int numbytes3 = ((xsize-filterdim + 1)/2 -filterdim + 1) * ((xsize-filterdim + 1)/2 -filterdim + 1);
/************num of bytes required for first weight matrix**************/
int numbytes4 = numfilters1*numweights*numbytes3/4;
/************num of bytes required for second weight matrix************/
int numbytes5 = numweights*numweights1;
/*****Original input - pic*************/
unsigned int *pic = (unsigned int *)malloc(numbytes);
/*****filter of the first conv layer*****/
unsigned int filter[numfilters*filterdim*filterdim];
/*******filter for the second conv layer*******/
unsigned int filter2[numfilters1*numfilters*filterdim*filterdim];
/*********weight matrix for the first dense layer**********/
unsigned int weight1[numbytes4];
/*********weight matrix for the second dense layer**********/
unsigned int weight2[numbytes5];
int result[numfilters*numbytes2];
int result2[numfilters1*numbytes3];
int maxpool[numfilters*(((xsize-filterdim + 1)*(xsize-filterdim + 1))/4)];
int maxpool2[numfilters1*(numbytes3/4)];
int dense1[numweights];
int dense2[numweights1];
int i, j;
int count;
int sum1,k,l;
int dimx;
dimx = numfilters1*(numbytes3/4);
/*************Should read in input**********/
for (i=0; i<xsize; i++) {
for (j=0; j<xsize; j++) {
pic[i*xsize + j] = 1;
// printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
}
// printf("\n");
}
/******should read in filters*********/
for(int k=0;k<numfilters;k++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
// printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
}
}
}
for(int k=0;k<numfilters1;k++){
for(int m= 0; m<numfilters;m++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
// printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
}
}
}
// printf("\n");
}
/*********First weight matrix**************/
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
weight1[l*dimx+i] = 1;
// printf("element1 : %d\n", l*dimx+i);
}
}
/**********Second weight matrix**************/
for(l=0;l<numweights1;l++){
for(i=0;i<numweights;i++){
weight2[l*numweights+i] = 1;
// printf("element2 : %d\n", l*numweights+i);
}
}
clock_t start, end;
start = clock();
/*****Operations of first convolutional layer******/
for(l=0; l < numfilters; l++){
count = 0;
for (i = 0; i < xsize - filterdim +1; i++){
for (j = 0; j < xsize - filterdim+1; j++){
k =0;
sum1 = (filter[l*(filterdim*filterdim) + k])*pic[ xsize * (i) + j ] + (filter[l*(filterdim*filterdim) + k+1])*pic[ xsize*(i) + (j+1) ]
+ filter[l*(filterdim*filterdim)+ k+2]*pic[ xsize * (i)+(j+2)] + filter[l*(filterdim*filterdim) +k+3]*pic[xsize * (i)+(j+3)]
+ filter[l*(filterdim*filterdim) +k+4]*pic[ xsize * (i)+(j+4)]+ filter[l*(filterdim*filterdim) + k+5]*pic[ xsize*(i+1)+(j) ]
+ filter[l*(filterdim*filterdim) +k+6]*pic[ xsize * (i+1) + (j+1) ] + filter[l*(filterdim*filterdim) + k+7]*pic[ xsize*(i+1) + (j+2) ] +
filter[l*(filterdim*filterdim) +k+8]*pic[ xsize*(i+1) + (j+3) ] + filter[l*(filterdim*filterdim) +k+9]*pic[ xsize*(i+1) + (j+4) ] +
filter[l*(filterdim*filterdim) +k+10]*pic[ xsize*(i+2) + (j) ] + filter[l*(filterdim*filterdim) +k+11]*pic[ xsize * (i+2) + (j+1) ] +
filter[l*(filterdim*filterdim) +k+12]*pic[ xsize*(i+2) + (j+2)] + filter[l*(filterdim*filterdim) +k+13]*pic[ xsize*(i+2) + (j+3)]
+filter[l*(filterdim*filterdim) +k+14]*pic[ xsize*(i+2) + (j+4)] + filter[l*(filterdim*filterdim) +k+15]*pic[ xsize*(i+3) + (j)]
+ filter[l*(filterdim*filterdim) +k+16]*pic[ xsize*(i+3) + (j+1)] + filter[l*(filterdim*filterdim) +k+17]*pic[ xsize*(i+3) + (j+2)]
+ filter[l*(filterdim*filterdim) +k+18]*pic[ xsize*(i+3) + (j+3)] + filter[l*(filterdim*filterdim) +k+19]*pic[ xsize*(i+3) + (j+4)]
+ filter[l*(filterdim*filterdim) +k+20]*pic[ xsize*(i+4) + (j)] +filter[l*(filterdim*filterdim) +k+21]*pic[ xsize*(i+3) + (j+1)]
+ filter[l*(filterdim*filterdim) +k+22]*pic[ xsize*(i+4) + (j+2)] + filter[l*(filterdim*filterdim) +k+23]*pic[ xsize*(i+4) + (j+3)]
+ filter[l*(filterdim*filterdim) + k+24]*pic[ xsize*(i+4) + (j+4)];
result[l*numbytes2 +count] = sum1;
// printf("result[%d][%d]=%d\t",l,count,result[l*numbytes2 + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/***************Maxpool***************************/
for(l=0; l<numfilters; l++){
count =0;
for(j=0;j<(xsize-filterdim + 1);j+=2){
for(i=0;i<(xsize-filterdim + 1);i+=2){
maxpool[l*(numbytes2/4) + count] =
Maxpooling(result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+1],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)+1]);
printf("Maxpool[%d][%d] : %d \t",l,count ,maxpool[l*(numbytes2/4) + count]);
count+=1;
}
printf("\n");
}
printf("\n\n\n");
}
/******Operations of second convolutional layer*******/
int m;
int dim = (xsize-filterdim + 1)/2;
dimx = (xsize-filterdim + 1)/2 -filterdim + 1;
printf("dim: %d ; dimx: %d\n", dim,dimx);
for(l=0; l < numfilters1; l++){
for (i = 0; i < dimx; i++){
for (j = 0; j < dimx; j++){
k =0;
sum1 =0;
for(m=0;m<numfilters;m++){
sum1 += (filter2[l*(numfilters*filterdim*filterdim) + k])*maxpool[ (m*dim*dim)+ dim * (i) + j ] + (filter2[l*(numfilters*filterdim*filterdim) + k+1])*maxpool[(m*dim*dim)+ dim*(i) + (j+1) ]
+ filter2[l*(numfilters*filterdim*filterdim)+ k+2]*maxpool[(m*dim*dim)+ dim * (i)+(j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+3]*maxpool[(m*dim*dim)+dim * (i)+(j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+4]*maxpool[ (m*dim*dim)+dim * (i)+(j+4)]+ filter2[l*(numfilters*filterdim*filterdim) + k+5]*maxpool[(m*dim*dim)+ dim*(i+1)+(j) ]
+ filter2[l*(numfilters*filterdim*filterdim) +k+6]*maxpool[(m*dim*dim)+ dim * (i+1) + (j+1) ] + filter2[l*(numfilters*filterdim*filterdim) + k+7]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+2) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+8]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+3) ] + filter2[l*(numfilters*filterdim*filterdim) +k+9]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+4) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+10]*maxpool[(m*dim*dim)+ dim*(i+2) + (j) ] + filter2[l*(numfilters*filterdim*filterdim) +k+11]*maxpool[(m*dim*dim)+ dim * (i+2) + (j+1) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+12]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+13]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+3)]
+filter2[l*(numfilters*filterdim*filterdim) +k+14]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+4)] + filter2[l*(numfilters*filterdim*filterdim) +k+15]*maxpool[(m*dim*dim)+ dim*(i+3) + (j)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+16]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)] + filter2[l*(numfilters*filterdim*filterdim) +k+17]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+2)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+18]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+3)] + filter2[l*(numfilters*filterdim*filterdim) +k+19]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+4)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+20]*maxpool[(m*dim*dim)+ dim*(i+4) + (j)] +filter2[l*(numfilters*filterdim*filterdim) +k+21]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+22]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+23]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) + k+24]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+4)];
}
result2[l*numbytes3 +i*dimx+j] = sum1;
k+=1;
printf("result2[%d][%d]=%d\t",l,i*dimx+j,result2[l*numbytes3 + i*dimx + j]);
}
printf("\n");
}
printf("\n\n\n");
}
/******Second Maxpool Layer******/
dim =((xsize-filterdim + 1)/2 -filterdim + 1)/2;
printf("dim: %d ;dimx: %d; numbytes3: %d", dim, dimx, numbytes3);
for(l=0; l<numfilters1; l++){
count =0;
for(j=0;j<dimx;j+=2){
for(i=0;i<dimx;i+=2){
maxpool2[l*(numbytes3/4) + count] =
(Maxpooling(result2[l*numbytes3 + j*dimx+i],
result2[l*numbytes3 + j*dimx+i+1],
result2[l*numbytes3 + j*dimx+i+dimx],
result2[l*numbytes3 + j*dimx+i+dimx+1]))/625;
// printf("Maxpool2[%d][%d] : %d \t",l,count ,maxpool2[l*(numbytes3/4) + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/********************First Dense layer**********************/
dimx = numfilters1*(numbytes3/4);
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
dense1[l]+= weight1[l*dimx+i]*maxpool2[i];
}
// printf("dense1[%d]:%d\n",l,dense1[l]);
}
/*************Second Dense Layer***************/
dimx = numweights;
for(l=0;l<numweights1;l++){
for(i=0;i<dimx;i++){
dense2[l]+= weight2[l*dimx+i]*dense1[i];
}
// printf("dense2[%d]:%d\n",l,dense2[l]);
}
end = clock();
printf("time taken by cpu : %f seconds",((double) (end - start)) );
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*Done with cpu version of convolution which can be scaled to any number of filters of
size 5x5. Maxpooling done with size 2x2. */
/*Implemented 2 layers of conv2d and maxpool using single 1D array */
/*implemented two dense layers*/
/*To do: measure time taken*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include "string.h"
#include<time.h>
int Maxpooling(int a, int b, int c, int d){
int temp,i;
temp = a;
if(b> c && b>d && b> temp){
temp = b;
// printf("temp is b\n");
}
if(c>b && c>d && c> temp){
temp = c;
//printf("temp is c\n");
}
if(d> c && d>b && d> temp){
temp = d;
// printf("temp is d\n");
}
// printf("temp is a\n");
return temp;
}
int main( int argc, char **argv )
{
int xsize, filterdim, numfilters, numfilters1, numweights, numweights1;
xsize = 28;
filterdim =5;
numfilters=32;
numfilters1=64;
numweights = 64;
numweights1 = 10;
/******num bytes required for the initial input********/
int numbytes = xsize * xsize * sizeof( int );
/*******num bytes required for input to conv1********/
int numbytes2 = (xsize-filterdim + 1) * (xsize - filterdim +1);
/*********num bytes required for the input to conv2****/
int numbytes3 = ((xsize-filterdim + 1)/2 -filterdim + 1) * ((xsize-filterdim + 1)/2 -filterdim + 1);
/************num of bytes required for first weight matrix**************/
int numbytes4 = numfilters1*numweights*numbytes3/4;
/************num of bytes required for second weight matrix************/
int numbytes5 = numweights*numweights1;
/*****Original input - pic*************/
unsigned int *pic = (unsigned int *)malloc(numbytes);
/*****filter of the first conv layer*****/
unsigned int filter[numfilters*filterdim*filterdim];
/*******filter for the second conv layer*******/
unsigned int filter2[numfilters1*numfilters*filterdim*filterdim];
/*********weight matrix for the first dense layer**********/
unsigned int weight1[numbytes4];
/*********weight matrix for the second dense layer**********/
unsigned int weight2[numbytes5];
int result[numfilters*numbytes2];
int result2[numfilters1*numbytes3];
int maxpool[numfilters*(((xsize-filterdim + 1)*(xsize-filterdim + 1))/4)];
int maxpool2[numfilters1*(numbytes3/4)];
int dense1[numweights];
int dense2[numweights1];
int i, j;
int count;
int sum1,k,l;
int dimx;
dimx = numfilters1*(numbytes3/4);
/*************Should read in input**********/
for (i=0; i<xsize; i++) {
for (j=0; j<xsize; j++) {
pic[i*xsize + j] = 1;
// printf("pic[%d][%d] : %d\t",i,j,pic[i*xsize + j]);
}
// printf("\n");
}
/******should read in filters*********/
for(int k=0;k<numfilters;k++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter[k*(filterdim*filterdim) + i*filterdim + j] = 1;
// printf("filter[%d][%d]: %d\n",k, i*filterdim + j, filter[k*(filterdim*filterdim) + i*filterdim + j]);
}
}
}
for(int k=0;k<numfilters1;k++){
for(int m= 0; m<numfilters;m++){
for (int i=0; i<filterdim; i++) {
for (int j=0; j<filterdim; j++){
filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j] = 1;
// printf("filter2[%d][%d]: %d\t",k, m*filterdim*filterdim+i*filterdim + j, filter2[k*(numfilters*filterdim*filterdim)+ m*filterdim*filterdim + i*filterdim + j]);
}
}
}
// printf("\n");
}
/*********First weight matrix**************/
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
weight1[l*dimx+i] = 1;
// printf("element1 : %d\n", l*dimx+i);
}
}
/**********Second weight matrix**************/
for(l=0;l<numweights1;l++){
for(i=0;i<numweights;i++){
weight2[l*numweights+i] = 1;
// printf("element2 : %d\n", l*numweights+i);
}
}
clock_t start, end;
start = clock();
/*****Operations of first convolutional layer******/
for(l=0; l < numfilters; l++){
count = 0;
for (i = 0; i < xsize - filterdim +1; i++){
for (j = 0; j < xsize - filterdim+1; j++){
k =0;
sum1 = (filter[l*(filterdim*filterdim) + k])*pic[ xsize * (i) + j ] + (filter[l*(filterdim*filterdim) + k+1])*pic[ xsize*(i) + (j+1) ]
+ filter[l*(filterdim*filterdim)+ k+2]*pic[ xsize * (i)+(j+2)] + filter[l*(filterdim*filterdim) +k+3]*pic[xsize * (i)+(j+3)]
+ filter[l*(filterdim*filterdim) +k+4]*pic[ xsize * (i)+(j+4)]+ filter[l*(filterdim*filterdim) + k+5]*pic[ xsize*(i+1)+(j) ]
+ filter[l*(filterdim*filterdim) +k+6]*pic[ xsize * (i+1) + (j+1) ] + filter[l*(filterdim*filterdim) + k+7]*pic[ xsize*(i+1) + (j+2) ] +
filter[l*(filterdim*filterdim) +k+8]*pic[ xsize*(i+1) + (j+3) ] + filter[l*(filterdim*filterdim) +k+9]*pic[ xsize*(i+1) + (j+4) ] +
filter[l*(filterdim*filterdim) +k+10]*pic[ xsize*(i+2) + (j) ] + filter[l*(filterdim*filterdim) +k+11]*pic[ xsize * (i+2) + (j+1) ] +
filter[l*(filterdim*filterdim) +k+12]*pic[ xsize*(i+2) + (j+2)] + filter[l*(filterdim*filterdim) +k+13]*pic[ xsize*(i+2) + (j+3)]
+filter[l*(filterdim*filterdim) +k+14]*pic[ xsize*(i+2) + (j+4)] + filter[l*(filterdim*filterdim) +k+15]*pic[ xsize*(i+3) + (j)]
+ filter[l*(filterdim*filterdim) +k+16]*pic[ xsize*(i+3) + (j+1)] + filter[l*(filterdim*filterdim) +k+17]*pic[ xsize*(i+3) + (j+2)]
+ filter[l*(filterdim*filterdim) +k+18]*pic[ xsize*(i+3) + (j+3)] + filter[l*(filterdim*filterdim) +k+19]*pic[ xsize*(i+3) + (j+4)]
+ filter[l*(filterdim*filterdim) +k+20]*pic[ xsize*(i+4) + (j)] +filter[l*(filterdim*filterdim) +k+21]*pic[ xsize*(i+3) + (j+1)]
+ filter[l*(filterdim*filterdim) +k+22]*pic[ xsize*(i+4) + (j+2)] + filter[l*(filterdim*filterdim) +k+23]*pic[ xsize*(i+4) + (j+3)]
+ filter[l*(filterdim*filterdim) + k+24]*pic[ xsize*(i+4) + (j+4)];
result[l*numbytes2 +count] = sum1;
// printf("result[%d][%d]=%d\t",l,count,result[l*numbytes2 + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/***************Maxpool***************************/
for(l=0; l<numfilters; l++){
count =0;
for(j=0;j<(xsize-filterdim + 1);j+=2){
for(i=0;i<(xsize-filterdim + 1);i+=2){
maxpool[l*(numbytes2/4) + count] =
Maxpooling(result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+1],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)],
result[l*(xsize - filterdim +1)*(xsize - filterdim +1) + j*(xsize-filterdim+1)+i+(xsize-filterdim + 1)+1]);
printf("Maxpool[%d][%d] : %d \t",l,count ,maxpool[l*(numbytes2/4) + count]);
count+=1;
}
printf("\n");
}
printf("\n\n\n");
}
/******Operations of second convolutional layer*******/
int m;
int dim = (xsize-filterdim + 1)/2;
dimx = (xsize-filterdim + 1)/2 -filterdim + 1;
printf("dim: %d ; dimx: %d\n", dim,dimx);
for(l=0; l < numfilters1; l++){
for (i = 0; i < dimx; i++){
for (j = 0; j < dimx; j++){
k =0;
sum1 =0;
for(m=0;m<numfilters;m++){
sum1 += (filter2[l*(numfilters*filterdim*filterdim) + k])*maxpool[ (m*dim*dim)+ dim * (i) + j ] + (filter2[l*(numfilters*filterdim*filterdim) + k+1])*maxpool[(m*dim*dim)+ dim*(i) + (j+1) ]
+ filter2[l*(numfilters*filterdim*filterdim)+ k+2]*maxpool[(m*dim*dim)+ dim * (i)+(j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+3]*maxpool[(m*dim*dim)+dim * (i)+(j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+4]*maxpool[ (m*dim*dim)+dim * (i)+(j+4)]+ filter2[l*(numfilters*filterdim*filterdim) + k+5]*maxpool[(m*dim*dim)+ dim*(i+1)+(j) ]
+ filter2[l*(numfilters*filterdim*filterdim) +k+6]*maxpool[(m*dim*dim)+ dim * (i+1) + (j+1) ] + filter2[l*(numfilters*filterdim*filterdim) + k+7]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+2) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+8]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+3) ] + filter2[l*(numfilters*filterdim*filterdim) +k+9]*maxpool[(m*dim*dim)+ dim*(i+1) + (j+4) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+10]*maxpool[(m*dim*dim)+ dim*(i+2) + (j) ] + filter2[l*(numfilters*filterdim*filterdim) +k+11]*maxpool[(m*dim*dim)+ dim * (i+2) + (j+1) ] +
filter2[l*(numfilters*filterdim*filterdim) +k+12]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+13]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+3)]
+filter2[l*(numfilters*filterdim*filterdim) +k+14]*maxpool[(m*dim*dim)+ dim*(i+2) + (j+4)] + filter2[l*(numfilters*filterdim*filterdim) +k+15]*maxpool[(m*dim*dim)+ dim*(i+3) + (j)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+16]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)] + filter2[l*(numfilters*filterdim*filterdim) +k+17]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+2)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+18]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+3)] + filter2[l*(numfilters*filterdim*filterdim) +k+19]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+4)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+20]*maxpool[(m*dim*dim)+ dim*(i+4) + (j)] +filter2[l*(numfilters*filterdim*filterdim) +k+21]*maxpool[(m*dim*dim)+ dim*(i+3) + (j+1)]
+ filter2[l*(numfilters*filterdim*filterdim) +k+22]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+2)] + filter2[l*(numfilters*filterdim*filterdim) +k+23]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+3)]
+ filter2[l*(numfilters*filterdim*filterdim) + k+24]*maxpool[(m*dim*dim)+ dim*(i+4) + (j+4)];
}
result2[l*numbytes3 +i*dimx+j] = sum1;
k+=1;
printf("result2[%d][%d]=%d\t",l,i*dimx+j,result2[l*numbytes3 + i*dimx + j]);
}
printf("\n");
}
printf("\n\n\n");
}
/******Second Maxpool Layer******/
dim =((xsize-filterdim + 1)/2 -filterdim + 1)/2;
printf("dim: %d ;dimx: %d; numbytes3: %d", dim, dimx, numbytes3);
for(l=0; l<numfilters1; l++){
count =0;
for(j=0;j<dimx;j+=2){
for(i=0;i<dimx;i+=2){
maxpool2[l*(numbytes3/4) + count] =
(Maxpooling(result2[l*numbytes3 + j*dimx+i],
result2[l*numbytes3 + j*dimx+i+1],
result2[l*numbytes3 + j*dimx+i+dimx],
result2[l*numbytes3 + j*dimx+i+dimx+1]))/625;
// printf("Maxpool2[%d][%d] : %d \t",l,count ,maxpool2[l*(numbytes3/4) + count]);
count+=1;
}
// printf("\n");
}
// printf("\n\n\n");
}
/********************First Dense layer**********************/
dimx = numfilters1*(numbytes3/4);
for(l=0;l<numweights;l++){
for(i=0;i<dimx;i++){
dense1[l]+= weight1[l*dimx+i]*maxpool2[i];
}
// printf("dense1[%d]:%d\n",l,dense1[l]);
}
/*************Second Dense Layer***************/
dimx = numweights;
for(l=0;l<numweights1;l++){
for(i=0;i<dimx;i++){
dense2[l]+= weight2[l*dimx+i]*dense1[i];
}
// printf("dense2[%d]:%d\n",l,dense2[l]);
}
end = clock();
printf("time taken by cpu : %f seconds",((double) (end - start)) );
} | .text
.file "Cpuv9.hip"
.globl _Z10Maxpoolingiiii # -- Begin function _Z10Maxpoolingiiii
.p2align 4, 0x90
.type _Z10Maxpoolingiiii,@function
_Z10Maxpoolingiiii: # @_Z10Maxpoolingiiii
.cfi_startproc
# %bb.0:
cmpl %edi, %esi
movl %edi, %eax
cmovgl %esi, %eax
cmpl %ecx, %esi
cmovlel %edi, %eax
cmpl %edx, %esi
cmovlel %edi, %eax
cmpl %edx, %eax
movl %edx, %edi
cmovgl %eax, %edi
cmpl %ecx, %edx
cmovlel %eax, %edi
cmpl %esi, %edx
cmovlel %eax, %edi
cmpl %ecx, %edi
movl %ecx, %eax
cmovgl %edi, %eax
cmpl %esi, %ecx
cmovlel %edi, %eax
cmpl %edx, %ecx
cmovlel %edi, %eax
retq
.Lfunc_end0:
.size _Z10Maxpoolingiiii, .Lfunc_end0-_Z10Maxpoolingiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $585848, %rsp # imm = 0x8F078
.cfi_def_cfa_offset 585904
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $3136, %edi # imm = 0xC40
callq malloc
movq %rax, %rcx
xorl %eax, %eax
movq %rcx, 112(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_1: # %.preheader825
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rcx,%rdx,4)
incq %rdx
cmpq $28, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $112, %rcx
cmpq $28, %rax
jne .LBB1_1
# %bb.4: # %.preheader823.preheader
leaq 496(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader823
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_7 Depth 3
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_6: # %.preheader822
# Parent Loop BB1_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# Parent Loop BB1_6 Depth=2
# => This Inner Loop Header: Depth=3
movl $1, (%rdx,%rdi,4)
incq %rdi
cmpq $5, %rdi
jne .LBB1_7
# %bb.8: # in Loop: Header=BB1_6 Depth=2
incq %rsi
addq $20, %rdx
cmpq $5, %rsi
jne .LBB1_6
# %bb.9: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $100, %rax
cmpq $32, %rcx
jne .LBB1_5
# %bb.10: # %.preheader820.preheader
leaq 10352(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.preheader820
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_13 Depth 3
# Child Loop BB1_14 Depth 4
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_12: # %.preheader819
# Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_13 Depth 3
# Child Loop BB1_14 Depth 4
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_13: # %.preheader818
# Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_14 Depth 4
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_14: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# Parent Loop BB1_13 Depth=3
# => This Inner Loop Header: Depth=4
movl $1, (%rdi,%r9,4)
incq %r9
cmpq $5, %r9
jne .LBB1_14
# %bb.15: # in Loop: Header=BB1_13 Depth=3
incq %r8
addq $20, %rdi
cmpq $5, %r8
jne .LBB1_13
# %bb.16: # in Loop: Header=BB1_12 Depth=2
incq %rsi
addq $100, %rdx
cmpq $32, %rsi
jne .LBB1_12
# %bb.17: # in Loop: Header=BB1_11 Depth=1
incq %rcx
addq $3200, %rax # imm = 0xC80
cmpq $64, %rcx
jne .LBB1_11
# %bb.18: # %.preheader816.preheader
leaq 323696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_19: # %.preheader816
# =>This Loop Header: Depth=1
# Child Loop BB1_20 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_20: # Parent Loop BB1_19 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB1_20
# %bb.21: # in Loop: Header=BB1_19 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $64, %rcx
jne .LBB1_19
# %bb.22: # %.preheader814.preheader
leaq 3696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_23: # %.preheader814
# =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_24: # Parent Loop BB1_23 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq $64, %rdx
jne .LBB1_24
# %bb.25: # in Loop: Header=BB1_23 Depth=1
incq %rcx
addq $256, %rax # imm = 0x100
cmpq $10, %rcx
jne .LBB1_23
# %bb.26:
leaq 249968(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
xorl %ebx, %ebx
callq clock
movq %rax, 160(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_27: # %.preheader813
# =>This Loop Header: Depth=1
# Child Loop BB1_28 Depth 2
# Child Loop BB1_29 Depth 3
movq %rbx, 120(%rsp) # 8-byte Spill
imulq $100, %rbx, %r11
movl 496(%rsp,%r11), %ecx
movl 500(%rsp,%r11), %edx
movl 504(%rsp,%r11), %esi
movl 508(%rsp,%r11), %eax
movl %eax, 88(%rsp) # 4-byte Spill
movl 512(%rsp,%r11), %eax
movl %eax, 76(%rsp) # 4-byte Spill
movl 516(%rsp,%r11), %eax
movl %eax, 72(%rsp) # 4-byte Spill
movl 520(%rsp,%r11), %eax
movl %eax, 68(%rsp) # 4-byte Spill
movl 524(%rsp,%r11), %eax
movl %eax, 64(%rsp) # 4-byte Spill
movl 528(%rsp,%r11), %eax
movl %eax, 60(%rsp) # 4-byte Spill
movl 532(%rsp,%r11), %eax
movl %eax, 56(%rsp) # 4-byte Spill
movl 536(%rsp,%r11), %eax
movl %eax, 52(%rsp) # 4-byte Spill
movl 540(%rsp,%r11), %eax
movl %eax, 48(%rsp) # 4-byte Spill
movl 544(%rsp,%r11), %eax
movl %eax, 44(%rsp) # 4-byte Spill
movl 580(%rsp,%r11), %eax
addl 560(%rsp,%r11), %eax
movl %eax, 40(%rsp) # 4-byte Spill
movl 548(%rsp,%r11), %eax
movl %eax, 36(%rsp) # 4-byte Spill
movl 552(%rsp,%r11), %eax
movl %eax, 32(%rsp) # 4-byte Spill
movl 556(%rsp,%r11), %eax
movl %eax, 28(%rsp) # 4-byte Spill
movl 564(%rsp,%r11), %eax
movl %eax, 24(%rsp) # 4-byte Spill
movl 568(%rsp,%r11), %eax
movl %eax, 128(%rsp) # 4-byte Spill
movl 572(%rsp,%r11), %eax
movl %eax, 96(%rsp) # 4-byte Spill
movl 576(%rsp,%r11), %eax
movl %eax, 20(%rsp) # 4-byte Spill
movl 584(%rsp,%r11), %eax
movl %eax, 16(%rsp) # 4-byte Spill
movl 588(%rsp,%r11), %eax
movl %eax, 12(%rsp) # 4-byte Spill
movl 592(%rsp,%r11), %eax
movl %eax, 8(%rsp) # 4-byte Spill
movq 112(%rsp), %rbp # 8-byte Reload
xorl %eax, %eax
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_28: # %.preheader812
# Parent Loop BB1_27 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_29 Depth 3
movq %rax, 144(%rsp) # 8-byte Spill
movslq %edi, %rdi
movq 104(%rsp), %rax # 8-byte Reload
movq %rdi, 136(%rsp) # 8-byte Spill
leaq (%rax,%rdi,4), %rax
movq %rax, 80(%rsp) # 8-byte Spill
xorl %r13d, %r13d
movl 128(%rsp), %r10d # 4-byte Reload
movl 96(%rsp), %r11d # 4-byte Reload
movl 20(%rsp), %r12d # 4-byte Reload
movl 16(%rsp), %edi # 4-byte Reload
movl 12(%rsp), %r8d # 4-byte Reload
movl 8(%rsp), %r9d # 4-byte Reload
.p2align 4, 0x90
.LBB1_29: # Parent Loop BB1_27 Depth=1
# Parent Loop BB1_28 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbp,%r13,4), %r14d
imull %ecx, %r14d
movl 4(%rbp,%r13,4), %r15d
imull %edx, %r15d
addl %r14d, %r15d
movl 8(%rbp,%r13,4), %r14d
imull %esi, %r14d
movl 12(%rbp,%r13,4), %ebx
imull 88(%rsp), %ebx # 4-byte Folded Reload
addl %r14d, %ebx
addl %r15d, %ebx
movl 16(%rbp,%r13,4), %r14d
imull 76(%rsp), %r14d # 4-byte Folded Reload
movl 112(%rbp,%r13,4), %r15d
imull 72(%rsp), %r15d # 4-byte Folded Reload
addl %r14d, %r15d
movl 116(%rbp,%r13,4), %r14d
imull 68(%rsp), %r14d # 4-byte Folded Reload
addl %r15d, %r14d
addl %ebx, %r14d
movl 120(%rbp,%r13,4), %ebx
imull 64(%rsp), %ebx # 4-byte Folded Reload
movl 124(%rbp,%r13,4), %r15d
imull 60(%rsp), %r15d # 4-byte Folded Reload
addl %ebx, %r15d
movl 128(%rbp,%r13,4), %ebx
imull 56(%rsp), %ebx # 4-byte Folded Reload
addl %r15d, %ebx
movl 224(%rbp,%r13,4), %r15d
imull 52(%rsp), %r15d # 4-byte Folded Reload
addl %ebx, %r15d
addl %r14d, %r15d
movl 228(%rbp,%r13,4), %ebx
imull 48(%rsp), %ebx # 4-byte Folded Reload
movl 232(%rbp,%r13,4), %r14d
imull 44(%rsp), %r14d # 4-byte Folded Reload
addl %ebx, %r14d
movl 236(%rbp,%r13,4), %ebx
imull 36(%rsp), %ebx # 4-byte Folded Reload
addl %r14d, %ebx
movl 240(%rbp,%r13,4), %eax
imull 32(%rsp), %eax # 4-byte Folded Reload
addl %ebx, %eax
movl 336(%rbp,%r13,4), %r14d
imull 28(%rsp), %r14d # 4-byte Folded Reload
addl %eax, %r14d
addl %r15d, %r14d
movl 344(%rbp,%r13,4), %eax
imull 24(%rsp), %eax # 4-byte Folded Reload
movl 348(%rbp,%r13,4), %ebx
imull %r10d, %ebx
addl %eax, %ebx
movl 352(%rbp,%r13,4), %eax
imull %r11d, %eax
addl %ebx, %eax
movl 448(%rbp,%r13,4), %ebx
imull %r12d, %ebx
addl %eax, %ebx
movl 460(%rbp,%r13,4), %eax
imull %r8d, %eax
movl 464(%rbp,%r13,4), %r15d
imull %r9d, %r15d
addl %eax, %r15d
movl 340(%rbp,%r13,4), %eax
imull 40(%rsp), %eax # 4-byte Folded Reload
addl %ebx, %eax
movl 456(%rbp,%r13,4), %ebx
imull %edi, %ebx
addl %ebx, %eax
addl %r14d, %eax
addl %r15d, %eax
movq 80(%rsp), %rbx # 8-byte Reload
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq $24, %r13
jne .LBB1_29
# %bb.30: # in Loop: Header=BB1_28 Depth=2
movq 144(%rsp), %rax # 8-byte Reload
incq %rax
movq 136(%rsp), %rdi # 8-byte Reload
addq %r13, %rdi
addq $112, %rbp
cmpq $24, %rax
jne .LBB1_28
# %bb.31: # in Loop: Header=BB1_27 Depth=1
movq 120(%rsp), %rbx # 8-byte Reload
incq %rbx
addq $2304, 104(%rsp) # 8-byte Folded Spill
# imm = 0x900
cmpq $32, %rbx
jne .LBB1_27
# %bb.32: # %.preheader811
leaq 231536(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
leaq 250068(%rsp), %r12
xorl %r14d, %r14d
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_39: # in Loop: Header=BB1_33 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
incq %r14
addq $576, 80(%rsp) # 8-byte Folded Spill
# imm = 0x240
movq 88(%rsp), %r12 # 8-byte Reload
addq $2304, %r12 # imm = 0x900
cmpq $32, %r14
je .LBB1_40
.LBB1_33: # %.preheader810
# =>This Loop Header: Depth=1
# Child Loop BB1_34 Depth 2
# Child Loop BB1_35 Depth 3
movq %r12, 88(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_38: # in Loop: Header=BB1_34 Depth=2
addl %ebx, %ebp
movl $10, %edi
callq putchar@PLT
leaq 2(%r13), %rax
addq $192, %r12
cmpq $22, %r13
movq %rax, %r13
jae .LBB1_39
.LBB1_34: # %.preheader809
# Parent Loop BB1_33 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_35 Depth 3
movslq %ebp, %rax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
movl %eax, %ebp
xorl %ebx, %ebx
jmp .LBB1_35
.p2align 4, 0x90
.LBB1_37: # in Loop: Header=BB1_35 Depth=3
cmpl %eax, %edx
cmovlel %edi, %ecx
cmpl %esi, %edx
cmovlel %edi, %ecx
movl %ecx, (%r15,%rbx,4)
leal (%rbx,%rbp), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpl $12, %ebx
je .LBB1_38
.LBB1_35: # Parent Loop BB1_33 Depth=1
# Parent Loop BB1_34 Depth=2
# => This Inner Loop Header: Depth=3
movl -100(%r12,%rbx,8), %ecx
movl -96(%r12,%rbx,8), %eax
cmpl %ecx, %eax
movl %ecx, %r8d
cmovgl %eax, %r8d
movl (%r12,%rbx,8), %edx
cmpl %edx, %eax
cmovlel %ecx, %r8d
movl -4(%r12,%rbx,8), %esi
cmpl %esi, %eax
cmovlel %ecx, %r8d
cmpl %esi, %r8d
movl %esi, %edi
cmovgl %r8d, %edi
cmpl %edx, %esi
cmovlel %r8d, %edi
cmpl %eax, %esi
cmovlel %r8d, %edi
movl %edi, %ecx
cmpl %edx, %edi
jg .LBB1_37
# %bb.36: # in Loop: Header=BB1_35 Depth=3
movl %edx, %ecx
jmp .LBB1_37
.LBB1_40:
movl $.L.str.3, %edi
movl $12, %esi
movl $8, %edx
xorl %eax, %eax
callq printf
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_41: # %.preheader808
# =>This Loop Header: Depth=1
# Child Loop BB1_42 Depth 2
# Child Loop BB1_43 Depth 3
# Child Loop BB1_44 Depth 4
imulq $3200, %rcx, %rax # imm = 0xC80
movl 10352(%rsp,%rax), %edx
movl %edx, 80(%rsp) # 4-byte Spill
movl 10356(%rsp,%rax), %edx
movl %edx, 88(%rsp) # 4-byte Spill
movl 10360(%rsp,%rax), %edx
movl %edx, 76(%rsp) # 4-byte Spill
movl 10364(%rsp,%rax), %edx
movl %edx, 72(%rsp) # 4-byte Spill
movl 10368(%rsp,%rax), %edx
movl %edx, 68(%rsp) # 4-byte Spill
movl 10372(%rsp,%rax), %edx
movl %edx, 64(%rsp) # 4-byte Spill
movl 10376(%rsp,%rax), %edx
movl %edx, 60(%rsp) # 4-byte Spill
movl 10380(%rsp,%rax), %edx
movl %edx, 56(%rsp) # 4-byte Spill
movl 10384(%rsp,%rax), %edx
movl %edx, 52(%rsp) # 4-byte Spill
movl 10388(%rsp,%rax), %edx
movl %edx, 48(%rsp) # 4-byte Spill
movl 10392(%rsp,%rax), %edx
movl %edx, 44(%rsp) # 4-byte Spill
movl 10396(%rsp,%rax), %edx
movl %edx, 40(%rsp) # 4-byte Spill
movl 10436(%rsp,%rax), %edx
addl 10416(%rsp,%rax), %edx
movl %edx, 36(%rsp) # 4-byte Spill
movl 10400(%rsp,%rax), %edx
movl %edx, 32(%rsp) # 4-byte Spill
movl 10404(%rsp,%rax), %edx
movl %edx, 28(%rsp) # 4-byte Spill
movl 10408(%rsp,%rax), %edx
movl %edx, 24(%rsp) # 4-byte Spill
movl 10412(%rsp,%rax), %edx
movl %edx, 20(%rsp) # 4-byte Spill
movl 10420(%rsp,%rax), %edx
movl %edx, 16(%rsp) # 4-byte Spill
movl 10424(%rsp,%rax), %edx
movl %edx, 12(%rsp) # 4-byte Spill
movl 10428(%rsp,%rax), %edx
movl %edx, 8(%rsp) # 4-byte Spill
movl 10432(%rsp,%rax), %edx
movl %edx, 120(%rsp) # 4-byte Spill
movl 10440(%rsp,%rax), %edx
movl %edx, 112(%rsp) # 4-byte Spill
movl 10444(%rsp,%rax), %edx
movl %edx, 156(%rsp) # 4-byte Spill
movl 10448(%rsp,%rax), %eax
movl %eax, 152(%rsp) # 4-byte Spill
movq %rcx, 96(%rsp) # 8-byte Spill
movq %rcx, %rax
shlq $8, %rax
addq %rsp, %rax
addq $215152, %rax # imm = 0x34870
movq %rax, 168(%rsp) # 8-byte Spill
leaq 231536(%rsp), %rbp
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_42: # %.preheader807
# Parent Loop BB1_41 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_43 Depth 3
# Child Loop BB1_44 Depth 4
leaq (,%rax,8), %rcx
movq %rcx, 104(%rsp) # 8-byte Spill
movq %rax, 176(%rsp) # 8-byte Spill
shlq $5, %rax
addq 168(%rsp), %rax # 8-byte Folded Reload
movq %rax, 128(%rsp) # 8-byte Spill
movq %rbp, 184(%rsp) # 8-byte Spill
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_43: # %.preheader806
# Parent Loop BB1_41 Depth=1
# Parent Loop BB1_42 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_44 Depth 4
movq %rcx, 136(%rsp) # 8-byte Spill
leaq 1(%rcx), %rax
movq %rax, 144(%rsp) # 8-byte Spill
xorl %ecx, %ecx
movl $208, %eax
movl 20(%rsp), %edx # 4-byte Reload
movl 16(%rsp), %r11d # 4-byte Reload
movl 12(%rsp), %r12d # 4-byte Reload
movl 8(%rsp), %r13d # 4-byte Reload
movl 120(%rsp), %ebx # 4-byte Reload
movl 112(%rsp), %r15d # 4-byte Reload
movl 156(%rsp), %r14d # 4-byte Reload
movl 152(%rsp), %r10d # 4-byte Reload
.p2align 4, 0x90
.LBB1_44: # Parent Loop BB1_41 Depth=1
# Parent Loop BB1_42 Depth=2
# Parent Loop BB1_43 Depth=3
# => This Inner Loop Header: Depth=4
movl -208(%rbp,%rax), %esi
imull 80(%rsp), %esi # 4-byte Folded Reload
addl %ecx, %esi
movl -204(%rbp,%rax), %ecx
imull 88(%rsp), %ecx # 4-byte Folded Reload
movl -200(%rbp,%rax), %edi
imull 76(%rsp), %edi # 4-byte Folded Reload
addl %ecx, %edi
addl %esi, %edi
movl -196(%rbp,%rax), %ecx
imull 72(%rsp), %ecx # 4-byte Folded Reload
movl -192(%rbp,%rax), %esi
imull 68(%rsp), %esi # 4-byte Folded Reload
addl %ecx, %esi
movl -160(%rbp,%rax), %r8d
imull 64(%rsp), %r8d # 4-byte Folded Reload
addl %esi, %r8d
addl %edi, %r8d
movl -156(%rbp,%rax), %ecx
imull 60(%rsp), %ecx # 4-byte Folded Reload
movl -152(%rbp,%rax), %esi
imull 56(%rsp), %esi # 4-byte Folded Reload
addl %ecx, %esi
movl -148(%rbp,%rax), %edi
imull 52(%rsp), %edi # 4-byte Folded Reload
addl %esi, %edi
movl -144(%rbp,%rax), %ecx
imull 48(%rsp), %ecx # 4-byte Folded Reload
addl %edi, %ecx
addl %r8d, %ecx
movl -112(%rbp,%rax), %esi
imull 44(%rsp), %esi # 4-byte Folded Reload
movl -108(%rbp,%rax), %edi
imull 40(%rsp), %edi # 4-byte Folded Reload
addl %esi, %edi
movl -104(%rbp,%rax), %esi
imull 32(%rsp), %esi # 4-byte Folded Reload
addl %edi, %esi
movl -100(%rbp,%rax), %edi
imull 28(%rsp), %edi # 4-byte Folded Reload
addl %esi, %edi
movl -96(%rbp,%rax), %esi
imull 24(%rsp), %esi # 4-byte Folded Reload
addl %edi, %esi
addl %ecx, %esi
movl -64(%rbp,%rax), %ecx
imull %edx, %ecx
movl -56(%rbp,%rax), %edi
imull %r11d, %edi
addl %ecx, %edi
movl -52(%rbp,%rax), %ecx
imull %r12d, %ecx
addl %edi, %ecx
movl -48(%rbp,%rax), %edi
imull %r13d, %edi
addl %ecx, %edi
movl -16(%rbp,%rax), %r8d
imull %ebx, %r8d
addl %edi, %r8d
movl -8(%rbp,%rax), %ecx
imull %r15d, %ecx
movl -4(%rbp,%rax), %edi
imull %r14d, %edi
addl %ecx, %edi
movl (%rbp,%rax), %r9d
imull %r10d, %r9d
addl %edi, %r9d
movl -60(%rbp,%rax), %ecx
imull 36(%rsp), %ecx # 4-byte Folded Reload
addl %r8d, %ecx
addl %esi, %ecx
addl %r9d, %ecx
addq $576, %rax # imm = 0x240
cmpq $18640, %rax # imm = 0x48D0
jne .LBB1_44
# %bb.45: # in Loop: Header=BB1_43 Depth=3
movq 128(%rsp), %rax # 8-byte Reload
movq 136(%rsp), %rdx # 8-byte Reload
movl %ecx, (%rax,%rdx,4)
orl 104(%rsp), %edx # 4-byte Folded Reload
movl $.L.str.4, %edi
movq 96(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $4, %rbp
movq 144(%rsp), %rax # 8-byte Reload
movq %rax, %rcx
cmpq $8, %rax
jne .LBB1_43
# %bb.46: # in Loop: Header=BB1_42 Depth=2
movl $10, %edi
callq putchar@PLT
movq 176(%rsp), %rax # 8-byte Reload
incq %rax
movq 184(%rsp), %rbp # 8-byte Reload
addq $48, %rbp
cmpq $8, %rax
jne .LBB1_42
# %bb.47: # in Loop: Header=BB1_41 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 96(%rsp), %rcx # 8-byte Reload
incq %rcx
cmpq $64, %rcx
jne .LBB1_41
# %bb.48:
xorl %ebx, %ebx
movl $.L.str.5, %edi
movl $4, %esi
movl $8, %edx
movl $64, %ecx
xorl %eax, %eax
callq printf
leaq 6256(%rsp), %rax
leaq 215188(%rsp), %rcx
jmp .LBB1_49
.p2align 4, 0x90
.LBB1_55: # in Loop: Header=BB1_49 Depth=1
incq %rbx
addq $64, %rax
addq $256, %rcx # imm = 0x100
cmpq $64, %rbx
je .LBB1_56
.LBB1_49: # %.preheader805
# =>This Loop Header: Depth=1
# Child Loop BB1_50 Depth 2
# Child Loop BB1_51 Depth 3
movq %rcx, %rdx
xorl %edi, %edi
xorl %esi, %esi
jmp .LBB1_50
.p2align 4, 0x90
.LBB1_54: # in Loop: Header=BB1_50 Depth=2
addl %r8d, %esi
leaq 2(%rdi), %r8
addq $64, %rdx
cmpq $6, %rdi
movq %r8, %rdi
jae .LBB1_55
.LBB1_50: # %.preheader804
# Parent Loop BB1_49 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_51 Depth 3
movslq %esi, %r8
leaq (%rax,%r8,4), %r9
xorl %r8d, %r8d
jmp .LBB1_51
.p2align 4, 0x90
.LBB1_53: # in Loop: Header=BB1_51 Depth=3
cmpl %r10d, %r11d
cmovlel %r14d, %r15d
cmpl %ebp, %r11d
cmovlel %r14d, %r15d
movslq %r15d, %r10
imulq $1759218605, %r10, %r10 # imm = 0x68DB8BAD
movq %r10, %r11
shrq $63, %r11
sarq $40, %r10
addl %r11d, %r10d
movl %r10d, (%r9,%r8,4)
incq %r8
cmpl $4, %r8d
je .LBB1_54
.LBB1_51: # Parent Loop BB1_49 Depth=1
# Parent Loop BB1_50 Depth=2
# => This Inner Loop Header: Depth=3
movl -36(%rdx,%r8,8), %r14d
movl -32(%rdx,%r8,8), %r10d
cmpl %r14d, %r10d
movl %r14d, %r15d
cmovgl %r10d, %r15d
movl (%rdx,%r8,8), %r11d
cmpl %r11d, %r10d
cmovlel %r14d, %r15d
movl -4(%rdx,%r8,8), %ebp
cmpl %ebp, %r10d
cmovlel %r14d, %r15d
cmpl %ebp, %r15d
movl %ebp, %r14d
cmovgl %r15d, %r14d
cmpl %r11d, %ebp
cmovlel %r15d, %r14d
cmpl %r10d, %ebp
cmovlel %r15d, %r14d
movl %r14d, %r15d
cmpl %r11d, %r14d
jg .LBB1_53
# %bb.52: # in Loop: Header=BB1_51 Depth=3
movl %r11d, %r15d
jmp .LBB1_53
.LBB1_56: # %.preheader802.preheader
leaq 323696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_57: # %.preheader802
# =>This Loop Header: Depth=1
# Child Loop BB1_58 Depth 2
movl 240(%rsp,%rcx,4), %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_58: # Parent Loop BB1_57 Depth=1
# => This Inner Loop Header: Depth=2
movl 6256(%rsp,%rsi,4), %edi
imull (%rax,%rsi,4), %edi
addl %edi, %edx
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB1_58
# %bb.59: # in Loop: Header=BB1_57 Depth=1
movl %edx, 240(%rsp,%rcx,4)
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $64, %rcx
jne .LBB1_57
# %bb.60: # %.preheader.preheader
leaq 3696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_61: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_62 Depth 2
movl 192(%rsp,%rcx,4), %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_62: # Parent Loop BB1_61 Depth=1
# => This Inner Loop Header: Depth=2
movl 240(%rsp,%rsi,4), %edi
imull (%rax,%rsi,4), %edi
addl %edi, %edx
incq %rsi
cmpq $64, %rsi
jne .LBB1_62
# %bb.63: # in Loop: Header=BB1_61 Depth=1
movl %edx, 192(%rsp,%rcx,4)
incq %rcx
addq $256, %rax # imm = 0x100
cmpq $10, %rcx
jne .LBB1_61
# %bb.64:
callq clock
subq 160(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $585848, %rsp # imm = 0x8F078
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Maxpool[%d][%d] : %d \t"
.size .L.str, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "dim: %d
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "result2[%d][%d]=%d\t"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "dim: %d
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "time taken by cpu : %f seconds"
.size .L.str.6, 31
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n\n"
.size .Lstr.1, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00060932_00000000-6_Cpuv9.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10Maxpoolingiiii
.type _Z10Maxpoolingiiii, @function
_Z10Maxpoolingiiii:
.LFB2061:
.cfi_startproc
endbr64
movl %edi, %eax
cmpl %ecx, %edx
movl %ecx, %r8d
cmovge %edx, %r8d
cmpl %esi, %edi
movl %esi, %edi
cmovge %eax, %edi
cmpl %esi, %r8d
cmovl %edi, %eax
cmpl %ecx, %esi
movl %ecx, %r8d
cmovge %esi, %r8d
cmpl %edx, %eax
movl %edx, %edi
cmovge %eax, %edi
cmpl %r8d, %edx
cmovg %edi, %eax
cmpl %edx, %esi
cmovl %edx, %esi
cmpl %ecx, %eax
movl %ecx, %edx
cmovge %eax, %edx
cmpl %esi, %ecx
cmovg %edx, %eax
ret
.cfi_endproc
.LFE2061:
.size _Z10Maxpoolingiiii, .-_Z10Maxpoolingiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Maxpool[%d][%d] : %d \t"
.LC1:
.string "\n"
.LC2:
.string "\n\n\n"
.LC3:
.string "dim: %d ; dimx: %d\n"
.LC4:
.string "result2[%d][%d]=%d\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "dim: %d ;dimx: %d; numbytes3: %d"
.align 8
.LC6:
.string "time taken by cpu : %f seconds"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $3136, %edi
call malloc@PLT
movq %rax, -160(%rbp)
movq %rsp, %rax
.L8:
cmpq %rax, %rsp
je .L9
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L8
.L9:
subq $3200, %rsp
orq $0, 3192(%rsp)
movq %rsp, %rcx
leaq -204800(%rsp), %rax
.L11:
cmpq %rax, %rsp
je .L12
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L11
.L12:
movq %rsp, -208(%rbp)
leaq -262144(%rsp), %rax
.L14:
cmpq %rax, %rsp
je .L15
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L14
.L15:
movq %rsp, %rdi
movq %rsp, %rax
.L17:
cmpq %rax, %rsp
je .L18
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L17
.L18:
subq $2560, %rsp
orq $0, 2552(%rsp)
movq %rsp, %rsi
leaq -73728(%rsp), %rax
.L20:
cmpq %rax, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
movq %rsp, %rbx
leaq -16384(%rsp), %rax
.L23:
cmpq %rax, %rsp
je .L24
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L23
.L24:
movq %rsp, -256(%rbp)
leaq -16384(%rsp), %rax
.L26:
cmpq %rax, %rsp
je .L27
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L26
.L27:
subq $2048, %rsp
orq $0, 2040(%rsp)
movq %rsp, -264(%rbp)
leaq -4096(%rsp), %rax
.L29:
cmpq %rax, %rsp
je .L30
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L29
.L30:
movq %rsp, -280(%rbp)
movq -160(%rbp), %rax
leaq 112(%rax), %rdx
leaq 3248(%rax), %r8
.L32:
leaq -112(%rdx), %rax
.L33:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L33
addq $112, %rdx
cmpq %r8, %rdx
jne .L32
movq %rcx, %r14
leaq 100(%rcx), %rdx
addq $3300, %rcx
jmp .L36
.L91:
addq $100, %rdx
cmpq %rcx, %rdx
je .L90
.L36:
leaq -100(%rdx), %rax
.L35:
movl $1, (%rax)
movl $1, 4(%rax)
movl $1, 8(%rax)
movl $1, 12(%rax)
movl $1, 16(%rax)
addq $20, %rax
cmpq %rdx, %rax
jne .L35
jmp .L91
.L90:
movq -208(%rbp), %rax
leaq 3300(%rax), %rcx
leaq 208100(%rax), %r8
jmp .L37
.L92:
addq $100, %rdx
cmpq %rcx, %rdx
je .L39
.L41:
leaq -100(%rdx), %rax
.L38:
movl $1, (%rax)
movl $1, 4(%rax)
movl $1, 8(%rax)
movl $1, 12(%rax)
movl $1, 16(%rax)
addq $20, %rax
cmpq %rdx, %rax
jne .L38
jmp .L92
.L39:
addq $3200, %rcx
cmpq %r8, %rcx
je .L40
.L37:
leaq -3200(%rcx), %rdx
jmp .L41
.L40:
leaq 4096(%rdi), %rdx
addq $266240, %rdi
.L43:
leaq -4096(%rdx), %rax
.L42:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L42
addq $4096, %rdx
cmpq %rdi, %rdx
jne .L43
leaq 256(%rsi), %rdx
addq $2816, %rsi
.L44:
leaq -256(%rdx), %rax
.L45:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L45
addq $256, %rdx
cmpq %rsi, %rdx
jne .L44
call clock@PLT
movq %rax, -272(%rbp)
movl $0, %ecx
movq %r14, %rdx
movq %rbx, -168(%rbp)
movq %rbx, -176(%rbp)
jmp .L47
.L49:
movq -184(%rbp), %rdx
movl -192(%rbp), %ecx
addq $100, %rdx
addl $576, %ecx
addq $2304, -168(%rbp)
cmpl $18432, %ecx
je .L93
.L47:
movl (%rdx), %eax
movl %eax, -72(%rbp)
movl 4(%rdx), %eax
movl %eax, -80(%rbp)
movl 12(%rdx), %eax
movl %eax, -88(%rbp)
movl 8(%rdx), %eax
movl %eax, -92(%rbp)
movl 20(%rdx), %eax
movl %eax, -96(%rbp)
movl 16(%rdx), %eax
movl %eax, -100(%rbp)
movl 28(%rdx), %eax
movl %eax, -104(%rbp)
movl 24(%rdx), %eax
movl %eax, -108(%rbp)
movl 36(%rdx), %eax
movl %eax, -112(%rbp)
movl 32(%rdx), %r14d
movl 44(%rdx), %r13d
movl 40(%rdx), %r12d
movl 52(%rdx), %ebx
movl 48(%rdx), %r11d
movl 60(%rdx), %r10d
movl 56(%rdx), %eax
movl %eax, -116(%rbp)
movl 68(%rdx), %eax
movl %eax, -120(%rbp)
movl 76(%rdx), %eax
movl %eax, -124(%rbp)
movl 72(%rdx), %eax
movl %eax, -128(%rbp)
movl 84(%rdx), %eax
addl 64(%rdx), %eax
movl %eax, -136(%rbp)
movl 80(%rdx), %eax
movl %eax, -132(%rbp)
movl 92(%rdx), %r9d
movl 88(%rdx), %r8d
movl 96(%rdx), %edi
movq -160(%rbp), %rax
leaq 96(%rax), %rsi
movq -168(%rbp), %rax
movq %rax, -144(%rbp)
movl $0, %r15d
movq %rdx, -184(%rbp)
movl %ecx, -192(%rbp)
.L51:
leaq -96(%rsi), %rax
movq -144(%rbp), %rcx
movl %r15d, -148(%rbp)
.L48:
movl -72(%rbp), %edx
imull (%rax), %edx
movl -80(%rbp), %r15d
imull 4(%rax), %r15d
addl %edx, %r15d
movl -88(%rbp), %edx
imull 12(%rax), %edx
addl %r15d, %edx
movl -92(%rbp), %r15d
imull 8(%rax), %r15d
addl %edx, %r15d
movl -96(%rbp), %edx
imull 112(%rax), %edx
addl %r15d, %edx
movl -100(%rbp), %r15d
imull 16(%rax), %r15d
addl %edx, %r15d
movl -104(%rbp), %edx
imull 120(%rax), %edx
addl %r15d, %edx
movl -108(%rbp), %r15d
imull 116(%rax), %r15d
addl %edx, %r15d
movl -112(%rbp), %edx
imull 128(%rax), %edx
addl %r15d, %edx
movl %r14d, %r15d
imull 124(%rax), %r15d
addl %edx, %r15d
movl %r13d, %edx
imull 228(%rax), %edx
addl %r15d, %edx
movl %r12d, %r15d
imull 224(%rax), %r15d
addl %edx, %r15d
movl %ebx, %edx
imull 236(%rax), %edx
addl %r15d, %edx
movl %r11d, %r15d
imull 232(%rax), %r15d
addl %edx, %r15d
movl %r10d, %edx
imull 336(%rax), %edx
addl %r15d, %edx
movl -116(%rbp), %r15d
imull 240(%rax), %r15d
addl %edx, %r15d
movl -120(%rbp), %edx
imull 344(%rax), %edx
addl %r15d, %edx
movl -124(%rbp), %r15d
imull 352(%rax), %r15d
addl %edx, %r15d
movl -128(%rbp), %edx
imull 348(%rax), %edx
addl %r15d, %edx
movl -136(%rbp), %r15d
imull 340(%rax), %r15d
addl %edx, %r15d
movl -132(%rbp), %edx
imull 448(%rax), %edx
addl %r15d, %edx
movl %r9d, %r15d
imull 460(%rax), %r15d
addl %edx, %r15d
movl %r8d, %edx
imull 456(%rax), %edx
addl %r15d, %edx
movl %edi, %r15d
imull 464(%rax), %r15d
addl %r15d, %edx
movl %edx, (%rcx)
addq $4, %rax
addq $4, %rcx
cmpq %rsi, %rax
jne .L48
movl -148(%rbp), %r15d
addl $24, %r15d
addq $96, -144(%rbp)
addq $112, %rsi
cmpl $576, %r15d
jne .L51
jmp .L49
.L93:
movq -176(%rbp), %rbx
movq -264(%rbp), %r14
movl $0, %r12d
movl $0, %r15d
jmp .L50
.L53:
movq -80(%rbp), %r12
movq -88(%rbp), %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addq $576, %r14
addq $576, %r12
cmpl $32, %r15d
je .L54
.L50:
leaq (%rbx,%r12,4), %rax
movq %rax, -72(%rbp)
movl $12, %r13d
movq %r12, -80(%rbp)
movq %rbx, -88(%rbp)
.L55:
leaq -12(%r13), %r12
movq -72(%rbp), %rbx
.L52:
movl 100(%rbx), %ecx
movl 96(%rbx), %edx
movl 4(%rbx), %esi
movl (%rbx), %edi
call _Z10Maxpoolingiiii
movl %eax, %r8d
movl %eax, (%r14,%r12,4)
movl %r12d, %ecx
movl %r15d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
addq $8, %rbx
cmpq %r13, %r12
jne .L52
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $192, -72(%rbp)
addq $12, %r13
cmpq $156, %r13
jne .L55
jmp .L53
.L54:
movl $8, %ecx
movl $12, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L56
.L58:
movq -224(%rbp), %r12
movq -232(%rbp), %r13
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r12
addq $48, %r13
cmpq $8, %r12
je .L59
.L62:
movq %r12, %rax
salq $5, %rax
movq -248(%rbp), %rbx
addq %rbx, %rax
movq %rax, -200(%rbp)
leal 0(,%r12,8), %eax
movl %eax, -152(%rbp)
movq $1, -176(%rbp)
movq %r13, %rbx
movq %r12, -224(%rbp)
movq %r13, -232(%rbp)
movq -240(%rbp), %r15
.L60:
movl -176(%rbp), %eax
movl %eax, -184(%rbp)
movq -208(%rbp), %rax
movl (%rax,%r15), %edi
movl %edi, -80(%rbp)
movl 4(%rax,%r15), %edi
movl %edi, -88(%rbp)
movl 12(%rax,%r15), %edi
movl %edi, -92(%rbp)
movl 8(%rax,%r15), %edi
movl %edi, -96(%rbp)
movl 20(%rax,%r15), %edi
movl %edi, -100(%rbp)
movl 16(%rax,%r15), %edi
movl %edi, -104(%rbp)
movl 28(%rax,%r15), %edi
movl %edi, -108(%rbp)
movl 24(%rax,%r15), %edi
movl %edi, -112(%rbp)
movl 36(%rax,%r15), %edi
movl %edi, -116(%rbp)
movl 32(%rax,%r15), %edi
movl %edi, -120(%rbp)
movl 44(%rax,%r15), %edi
movl %edi, -124(%rbp)
movl 40(%rax,%r15), %edi
movl %edi, -128(%rbp)
movl 52(%rax,%r15), %edi
movl %edi, -132(%rbp)
movl 48(%rax,%r15), %edi
movl %edi, -136(%rbp)
movl 60(%rax,%r15), %edi
movl %edi, -144(%rbp)
movl 56(%rax,%r15), %edi
movl %edi, -148(%rbp)
movl 68(%rax,%r15), %esi
movl %esi, -160(%rbp)
movl 76(%rax,%r15), %edi
movl %edi, -168(%rbp)
movl 72(%rax,%r15), %r14d
movl 84(%rax,%r15), %r10d
addl 64(%rax,%r15), %r10d
movl 80(%rax,%r15), %r13d
movl 92(%rax,%r15), %r12d
movl 88(%rax,%r15), %r9d
movl 96(%rax,%r15), %r11d
leaq -18432(%rbx), %rax
leaq -18384(%rbx), %rsi
leaq -18332(%rbx), %rcx
leaq -18288(%rbx), %rdx
leaq -18240(%rbx), %rdi
movl $0, -72(%rbp)
movq %r15, -192(%rbp)
.L57:
movl -80(%rbp), %r8d
imull (%rax), %r8d
movl -88(%rbp), %r15d
imull 4(%rax), %r15d
addl %r8d, %r15d
movl -92(%rbp), %r8d
imull 12(%rax), %r8d
addl %r15d, %r8d
movl -96(%rbp), %r15d
imull 8(%rax), %r15d
addl %r8d, %r15d
movl -100(%rbp), %r8d
imull (%rsi), %r8d
addl %r15d, %r8d
movl -104(%rbp), %r15d
imull 16(%rax), %r15d
addl %r8d, %r15d
movl -108(%rbp), %r8d
imull 8(%rsi), %r8d
addl %r15d, %r8d
movl -112(%rbp), %r15d
imull 4(%rsi), %r15d
addl %r8d, %r15d
movl -116(%rbp), %r8d
imull 16(%rsi), %r8d
addl %r15d, %r8d
movl -120(%rbp), %r15d
imull 12(%rsi), %r15d
addl %r8d, %r15d
movl -124(%rbp), %r8d
imull (%rcx), %r8d
addl %r15d, %r8d
movl -128(%rbp), %r15d
imull -4(%rcx), %r15d
addl %r8d, %r15d
movl -132(%rbp), %r8d
imull 8(%rcx), %r8d
addl %r15d, %r8d
movl -136(%rbp), %r15d
imull 4(%rcx), %r15d
addl %r8d, %r15d
movl -144(%rbp), %r8d
imull (%rdx), %r8d
addl %r15d, %r8d
movl -148(%rbp), %r15d
imull 12(%rcx), %r15d
addl %r8d, %r15d
movl -160(%rbp), %r8d
imull 8(%rdx), %r8d
addl %r15d, %r8d
movl -168(%rbp), %r15d
imull 16(%rdx), %r15d
addl %r8d, %r15d
movl %r14d, %r8d
imull 12(%rdx), %r8d
addl %r15d, %r8d
movl %r10d, %r15d
imull 4(%rdx), %r15d
addl %r8d, %r15d
movl %r13d, %r8d
imull (%rdi), %r8d
addl %r15d, %r8d
movl %r12d, %r15d
imull 12(%rdi), %r15d
addl %r8d, %r15d
movl %r9d, %r8d
imull 8(%rdi), %r8d
addl %r15d, %r8d
movl %r11d, %r15d
imull 16(%rdi), %r15d
addl %r15d, %r8d
movl -72(%rbp), %r15d
addl %r15d, %r8d
movl %r8d, -72(%rbp)
addq $576, %rax
addq $576, %rsi
addq $576, %rcx
addq $576, %rdx
addq $576, %rdi
cmpq %rbx, %rax
jne .L57
movq -192(%rbp), %r15
movq -200(%rbp), %rax
movq -176(%rbp), %r14
movl %r8d, -4(%rax,%r14,4)
movl -184(%rbp), %eax
movl -152(%rbp), %edi
leal -1(%rax,%rdi), %ecx
movl -212(%rbp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
movq %r14, -176(%rbp)
addq $4, %rbx
cmpq $9, %r14
jne .L60
jmp .L58
.L59:
movq -288(%rbp), %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $64, %rbx
je .L61
.L56:
movl %ebx, -212(%rbp)
movq -264(%rbp), %rax
leaq 18432(%rax), %r13
leaq (%rbx,%rbx,4), %rax
leaq (%rax,%rax,4), %rax
salq $7, %rax
movq %rax, -240(%rbp)
movq %rbx, %rax
salq $8, %rax
movq -256(%rbp), %rsi
leaq (%rsi,%rax), %r14
movl $0, %r12d
movq %r14, -248(%rbp)
movq %rbx, -288(%rbp)
jmp .L62
.L61:
movl $64, %r8d
movl $8, %ecx
movl $4, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq -280(%rbp), %rax
movq %rax, -80(%rbp)
movq -256(%rbp), %r14
addq $32, %r14
movl $0, %r15d
jmp .L63
.L65:
addl $16, %r15d
addq $64, -80(%rbp)
addq $256, %r14
cmpl $1024, %r15d
je .L73
.L63:
movq %r14, %r13
movq -80(%rbp), %rax
movq %rax, -88(%rbp)
movl $0, -72(%rbp)
.L67:
leaq -32(%r13), %rbx
movq -88(%rbp), %r12
.L64:
movl 36(%rbx), %ecx
movl 32(%rbx), %edx
movl 4(%rbx), %esi
movl (%rbx), %edi
call _Z10Maxpoolingiiii
movl %eax, %edx
cltq
imulq $1759218605, %rax, %rax
sarq $40, %rax
sarl $31, %edx
subl %edx, %eax
movl %eax, (%r12)
addq $8, %rbx
addq $4, %r12
cmpq %rbx, %r13
jne .L64
addl $4, -72(%rbp)
movl -72(%rbp), %eax
addq $16, -88(%rbp)
addq $64, %r13
cmpl $16, %eax
jne .L67
jmp .L65
.L73:
movl $64, %edx
.L66:
movl %r15d, %eax
.L68:
subl $1, %eax
jne .L68
subl $1, %edx
jne .L66
movl $10, %edx
.L69:
movl $64, %eax
.L70:
subl $1, %eax
jne .L70
subl $1, %edx
jne .L69
call clock@PLT
movq -272(%rbp), %rbx
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L94
movl $0, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L94:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Cpuv9.hip"
.globl _Z10Maxpoolingiiii # -- Begin function _Z10Maxpoolingiiii
.p2align 4, 0x90
.type _Z10Maxpoolingiiii,@function
_Z10Maxpoolingiiii: # @_Z10Maxpoolingiiii
.cfi_startproc
# %bb.0:
cmpl %edi, %esi
movl %edi, %eax
cmovgl %esi, %eax
cmpl %ecx, %esi
cmovlel %edi, %eax
cmpl %edx, %esi
cmovlel %edi, %eax
cmpl %edx, %eax
movl %edx, %edi
cmovgl %eax, %edi
cmpl %ecx, %edx
cmovlel %eax, %edi
cmpl %esi, %edx
cmovlel %eax, %edi
cmpl %ecx, %edi
movl %ecx, %eax
cmovgl %edi, %eax
cmpl %esi, %ecx
cmovlel %edi, %eax
cmpl %edx, %ecx
cmovlel %edi, %eax
retq
.Lfunc_end0:
.size _Z10Maxpoolingiiii, .Lfunc_end0-_Z10Maxpoolingiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $585848, %rsp # imm = 0x8F078
.cfi_def_cfa_offset 585904
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $3136, %edi # imm = 0xC40
callq malloc
movq %rax, %rcx
xorl %eax, %eax
movq %rcx, 112(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_1: # %.preheader825
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rcx,%rdx,4)
incq %rdx
cmpq $28, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $112, %rcx
cmpq $28, %rax
jne .LBB1_1
# %bb.4: # %.preheader823.preheader
leaq 496(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader823
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
# Child Loop BB1_7 Depth 3
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_6: # %.preheader822
# Parent Loop BB1_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_7 Depth 3
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_7: # Parent Loop BB1_5 Depth=1
# Parent Loop BB1_6 Depth=2
# => This Inner Loop Header: Depth=3
movl $1, (%rdx,%rdi,4)
incq %rdi
cmpq $5, %rdi
jne .LBB1_7
# %bb.8: # in Loop: Header=BB1_6 Depth=2
incq %rsi
addq $20, %rdx
cmpq $5, %rsi
jne .LBB1_6
# %bb.9: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $100, %rax
cmpq $32, %rcx
jne .LBB1_5
# %bb.10: # %.preheader820.preheader
leaq 10352(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.preheader820
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
# Child Loop BB1_13 Depth 3
# Child Loop BB1_14 Depth 4
movq %rax, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_12: # %.preheader819
# Parent Loop BB1_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_13 Depth 3
# Child Loop BB1_14 Depth 4
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_13: # %.preheader818
# Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_14 Depth 4
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_14: # Parent Loop BB1_11 Depth=1
# Parent Loop BB1_12 Depth=2
# Parent Loop BB1_13 Depth=3
# => This Inner Loop Header: Depth=4
movl $1, (%rdi,%r9,4)
incq %r9
cmpq $5, %r9
jne .LBB1_14
# %bb.15: # in Loop: Header=BB1_13 Depth=3
incq %r8
addq $20, %rdi
cmpq $5, %r8
jne .LBB1_13
# %bb.16: # in Loop: Header=BB1_12 Depth=2
incq %rsi
addq $100, %rdx
cmpq $32, %rsi
jne .LBB1_12
# %bb.17: # in Loop: Header=BB1_11 Depth=1
incq %rcx
addq $3200, %rax # imm = 0xC80
cmpq $64, %rcx
jne .LBB1_11
# %bb.18: # %.preheader816.preheader
leaq 323696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_19: # %.preheader816
# =>This Loop Header: Depth=1
# Child Loop BB1_20 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_20: # Parent Loop BB1_19 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq $1024, %rdx # imm = 0x400
jne .LBB1_20
# %bb.21: # in Loop: Header=BB1_19 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $64, %rcx
jne .LBB1_19
# %bb.22: # %.preheader814.preheader
leaq 3696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_23: # %.preheader814
# =>This Loop Header: Depth=1
# Child Loop BB1_24 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_24: # Parent Loop BB1_23 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq $64, %rdx
jne .LBB1_24
# %bb.25: # in Loop: Header=BB1_23 Depth=1
incq %rcx
addq $256, %rax # imm = 0x100
cmpq $10, %rcx
jne .LBB1_23
# %bb.26:
leaq 249968(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
xorl %ebx, %ebx
callq clock
movq %rax, 160(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_27: # %.preheader813
# =>This Loop Header: Depth=1
# Child Loop BB1_28 Depth 2
# Child Loop BB1_29 Depth 3
movq %rbx, 120(%rsp) # 8-byte Spill
imulq $100, %rbx, %r11
movl 496(%rsp,%r11), %ecx
movl 500(%rsp,%r11), %edx
movl 504(%rsp,%r11), %esi
movl 508(%rsp,%r11), %eax
movl %eax, 88(%rsp) # 4-byte Spill
movl 512(%rsp,%r11), %eax
movl %eax, 76(%rsp) # 4-byte Spill
movl 516(%rsp,%r11), %eax
movl %eax, 72(%rsp) # 4-byte Spill
movl 520(%rsp,%r11), %eax
movl %eax, 68(%rsp) # 4-byte Spill
movl 524(%rsp,%r11), %eax
movl %eax, 64(%rsp) # 4-byte Spill
movl 528(%rsp,%r11), %eax
movl %eax, 60(%rsp) # 4-byte Spill
movl 532(%rsp,%r11), %eax
movl %eax, 56(%rsp) # 4-byte Spill
movl 536(%rsp,%r11), %eax
movl %eax, 52(%rsp) # 4-byte Spill
movl 540(%rsp,%r11), %eax
movl %eax, 48(%rsp) # 4-byte Spill
movl 544(%rsp,%r11), %eax
movl %eax, 44(%rsp) # 4-byte Spill
movl 580(%rsp,%r11), %eax
addl 560(%rsp,%r11), %eax
movl %eax, 40(%rsp) # 4-byte Spill
movl 548(%rsp,%r11), %eax
movl %eax, 36(%rsp) # 4-byte Spill
movl 552(%rsp,%r11), %eax
movl %eax, 32(%rsp) # 4-byte Spill
movl 556(%rsp,%r11), %eax
movl %eax, 28(%rsp) # 4-byte Spill
movl 564(%rsp,%r11), %eax
movl %eax, 24(%rsp) # 4-byte Spill
movl 568(%rsp,%r11), %eax
movl %eax, 128(%rsp) # 4-byte Spill
movl 572(%rsp,%r11), %eax
movl %eax, 96(%rsp) # 4-byte Spill
movl 576(%rsp,%r11), %eax
movl %eax, 20(%rsp) # 4-byte Spill
movl 584(%rsp,%r11), %eax
movl %eax, 16(%rsp) # 4-byte Spill
movl 588(%rsp,%r11), %eax
movl %eax, 12(%rsp) # 4-byte Spill
movl 592(%rsp,%r11), %eax
movl %eax, 8(%rsp) # 4-byte Spill
movq 112(%rsp), %rbp # 8-byte Reload
xorl %eax, %eax
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_28: # %.preheader812
# Parent Loop BB1_27 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_29 Depth 3
movq %rax, 144(%rsp) # 8-byte Spill
movslq %edi, %rdi
movq 104(%rsp), %rax # 8-byte Reload
movq %rdi, 136(%rsp) # 8-byte Spill
leaq (%rax,%rdi,4), %rax
movq %rax, 80(%rsp) # 8-byte Spill
xorl %r13d, %r13d
movl 128(%rsp), %r10d # 4-byte Reload
movl 96(%rsp), %r11d # 4-byte Reload
movl 20(%rsp), %r12d # 4-byte Reload
movl 16(%rsp), %edi # 4-byte Reload
movl 12(%rsp), %r8d # 4-byte Reload
movl 8(%rsp), %r9d # 4-byte Reload
.p2align 4, 0x90
.LBB1_29: # Parent Loop BB1_27 Depth=1
# Parent Loop BB1_28 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbp,%r13,4), %r14d
imull %ecx, %r14d
movl 4(%rbp,%r13,4), %r15d
imull %edx, %r15d
addl %r14d, %r15d
movl 8(%rbp,%r13,4), %r14d
imull %esi, %r14d
movl 12(%rbp,%r13,4), %ebx
imull 88(%rsp), %ebx # 4-byte Folded Reload
addl %r14d, %ebx
addl %r15d, %ebx
movl 16(%rbp,%r13,4), %r14d
imull 76(%rsp), %r14d # 4-byte Folded Reload
movl 112(%rbp,%r13,4), %r15d
imull 72(%rsp), %r15d # 4-byte Folded Reload
addl %r14d, %r15d
movl 116(%rbp,%r13,4), %r14d
imull 68(%rsp), %r14d # 4-byte Folded Reload
addl %r15d, %r14d
addl %ebx, %r14d
movl 120(%rbp,%r13,4), %ebx
imull 64(%rsp), %ebx # 4-byte Folded Reload
movl 124(%rbp,%r13,4), %r15d
imull 60(%rsp), %r15d # 4-byte Folded Reload
addl %ebx, %r15d
movl 128(%rbp,%r13,4), %ebx
imull 56(%rsp), %ebx # 4-byte Folded Reload
addl %r15d, %ebx
movl 224(%rbp,%r13,4), %r15d
imull 52(%rsp), %r15d # 4-byte Folded Reload
addl %ebx, %r15d
addl %r14d, %r15d
movl 228(%rbp,%r13,4), %ebx
imull 48(%rsp), %ebx # 4-byte Folded Reload
movl 232(%rbp,%r13,4), %r14d
imull 44(%rsp), %r14d # 4-byte Folded Reload
addl %ebx, %r14d
movl 236(%rbp,%r13,4), %ebx
imull 36(%rsp), %ebx # 4-byte Folded Reload
addl %r14d, %ebx
movl 240(%rbp,%r13,4), %eax
imull 32(%rsp), %eax # 4-byte Folded Reload
addl %ebx, %eax
movl 336(%rbp,%r13,4), %r14d
imull 28(%rsp), %r14d # 4-byte Folded Reload
addl %eax, %r14d
addl %r15d, %r14d
movl 344(%rbp,%r13,4), %eax
imull 24(%rsp), %eax # 4-byte Folded Reload
movl 348(%rbp,%r13,4), %ebx
imull %r10d, %ebx
addl %eax, %ebx
movl 352(%rbp,%r13,4), %eax
imull %r11d, %eax
addl %ebx, %eax
movl 448(%rbp,%r13,4), %ebx
imull %r12d, %ebx
addl %eax, %ebx
movl 460(%rbp,%r13,4), %eax
imull %r8d, %eax
movl 464(%rbp,%r13,4), %r15d
imull %r9d, %r15d
addl %eax, %r15d
movl 340(%rbp,%r13,4), %eax
imull 40(%rsp), %eax # 4-byte Folded Reload
addl %ebx, %eax
movl 456(%rbp,%r13,4), %ebx
imull %edi, %ebx
addl %ebx, %eax
addl %r14d, %eax
addl %r15d, %eax
movq 80(%rsp), %rbx # 8-byte Reload
movl %eax, (%rbx,%r13,4)
incq %r13
cmpq $24, %r13
jne .LBB1_29
# %bb.30: # in Loop: Header=BB1_28 Depth=2
movq 144(%rsp), %rax # 8-byte Reload
incq %rax
movq 136(%rsp), %rdi # 8-byte Reload
addq %r13, %rdi
addq $112, %rbp
cmpq $24, %rax
jne .LBB1_28
# %bb.31: # in Loop: Header=BB1_27 Depth=1
movq 120(%rsp), %rbx # 8-byte Reload
incq %rbx
addq $2304, 104(%rsp) # 8-byte Folded Spill
# imm = 0x900
cmpq $32, %rbx
jne .LBB1_27
# %bb.32: # %.preheader811
leaq 231536(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
leaq 250068(%rsp), %r12
xorl %r14d, %r14d
jmp .LBB1_33
.p2align 4, 0x90
.LBB1_39: # in Loop: Header=BB1_33 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
incq %r14
addq $576, 80(%rsp) # 8-byte Folded Spill
# imm = 0x240
movq 88(%rsp), %r12 # 8-byte Reload
addq $2304, %r12 # imm = 0x900
cmpq $32, %r14
je .LBB1_40
.LBB1_33: # %.preheader810
# =>This Loop Header: Depth=1
# Child Loop BB1_34 Depth 2
# Child Loop BB1_35 Depth 3
movq %r12, 88(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_34
.p2align 4, 0x90
.LBB1_38: # in Loop: Header=BB1_34 Depth=2
addl %ebx, %ebp
movl $10, %edi
callq putchar@PLT
leaq 2(%r13), %rax
addq $192, %r12
cmpq $22, %r13
movq %rax, %r13
jae .LBB1_39
.LBB1_34: # %.preheader809
# Parent Loop BB1_33 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_35 Depth 3
movslq %ebp, %rax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
movl %eax, %ebp
xorl %ebx, %ebx
jmp .LBB1_35
.p2align 4, 0x90
.LBB1_37: # in Loop: Header=BB1_35 Depth=3
cmpl %eax, %edx
cmovlel %edi, %ecx
cmpl %esi, %edx
cmovlel %edi, %ecx
movl %ecx, (%r15,%rbx,4)
leal (%rbx,%rbp), %edx
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpl $12, %ebx
je .LBB1_38
.LBB1_35: # Parent Loop BB1_33 Depth=1
# Parent Loop BB1_34 Depth=2
# => This Inner Loop Header: Depth=3
movl -100(%r12,%rbx,8), %ecx
movl -96(%r12,%rbx,8), %eax
cmpl %ecx, %eax
movl %ecx, %r8d
cmovgl %eax, %r8d
movl (%r12,%rbx,8), %edx
cmpl %edx, %eax
cmovlel %ecx, %r8d
movl -4(%r12,%rbx,8), %esi
cmpl %esi, %eax
cmovlel %ecx, %r8d
cmpl %esi, %r8d
movl %esi, %edi
cmovgl %r8d, %edi
cmpl %edx, %esi
cmovlel %r8d, %edi
cmpl %eax, %esi
cmovlel %r8d, %edi
movl %edi, %ecx
cmpl %edx, %edi
jg .LBB1_37
# %bb.36: # in Loop: Header=BB1_35 Depth=3
movl %edx, %ecx
jmp .LBB1_37
.LBB1_40:
movl $.L.str.3, %edi
movl $12, %esi
movl $8, %edx
xorl %eax, %eax
callq printf
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_41: # %.preheader808
# =>This Loop Header: Depth=1
# Child Loop BB1_42 Depth 2
# Child Loop BB1_43 Depth 3
# Child Loop BB1_44 Depth 4
imulq $3200, %rcx, %rax # imm = 0xC80
movl 10352(%rsp,%rax), %edx
movl %edx, 80(%rsp) # 4-byte Spill
movl 10356(%rsp,%rax), %edx
movl %edx, 88(%rsp) # 4-byte Spill
movl 10360(%rsp,%rax), %edx
movl %edx, 76(%rsp) # 4-byte Spill
movl 10364(%rsp,%rax), %edx
movl %edx, 72(%rsp) # 4-byte Spill
movl 10368(%rsp,%rax), %edx
movl %edx, 68(%rsp) # 4-byte Spill
movl 10372(%rsp,%rax), %edx
movl %edx, 64(%rsp) # 4-byte Spill
movl 10376(%rsp,%rax), %edx
movl %edx, 60(%rsp) # 4-byte Spill
movl 10380(%rsp,%rax), %edx
movl %edx, 56(%rsp) # 4-byte Spill
movl 10384(%rsp,%rax), %edx
movl %edx, 52(%rsp) # 4-byte Spill
movl 10388(%rsp,%rax), %edx
movl %edx, 48(%rsp) # 4-byte Spill
movl 10392(%rsp,%rax), %edx
movl %edx, 44(%rsp) # 4-byte Spill
movl 10396(%rsp,%rax), %edx
movl %edx, 40(%rsp) # 4-byte Spill
movl 10436(%rsp,%rax), %edx
addl 10416(%rsp,%rax), %edx
movl %edx, 36(%rsp) # 4-byte Spill
movl 10400(%rsp,%rax), %edx
movl %edx, 32(%rsp) # 4-byte Spill
movl 10404(%rsp,%rax), %edx
movl %edx, 28(%rsp) # 4-byte Spill
movl 10408(%rsp,%rax), %edx
movl %edx, 24(%rsp) # 4-byte Spill
movl 10412(%rsp,%rax), %edx
movl %edx, 20(%rsp) # 4-byte Spill
movl 10420(%rsp,%rax), %edx
movl %edx, 16(%rsp) # 4-byte Spill
movl 10424(%rsp,%rax), %edx
movl %edx, 12(%rsp) # 4-byte Spill
movl 10428(%rsp,%rax), %edx
movl %edx, 8(%rsp) # 4-byte Spill
movl 10432(%rsp,%rax), %edx
movl %edx, 120(%rsp) # 4-byte Spill
movl 10440(%rsp,%rax), %edx
movl %edx, 112(%rsp) # 4-byte Spill
movl 10444(%rsp,%rax), %edx
movl %edx, 156(%rsp) # 4-byte Spill
movl 10448(%rsp,%rax), %eax
movl %eax, 152(%rsp) # 4-byte Spill
movq %rcx, 96(%rsp) # 8-byte Spill
movq %rcx, %rax
shlq $8, %rax
addq %rsp, %rax
addq $215152, %rax # imm = 0x34870
movq %rax, 168(%rsp) # 8-byte Spill
leaq 231536(%rsp), %rbp
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_42: # %.preheader807
# Parent Loop BB1_41 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_43 Depth 3
# Child Loop BB1_44 Depth 4
leaq (,%rax,8), %rcx
movq %rcx, 104(%rsp) # 8-byte Spill
movq %rax, 176(%rsp) # 8-byte Spill
shlq $5, %rax
addq 168(%rsp), %rax # 8-byte Folded Reload
movq %rax, 128(%rsp) # 8-byte Spill
movq %rbp, 184(%rsp) # 8-byte Spill
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_43: # %.preheader806
# Parent Loop BB1_41 Depth=1
# Parent Loop BB1_42 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB1_44 Depth 4
movq %rcx, 136(%rsp) # 8-byte Spill
leaq 1(%rcx), %rax
movq %rax, 144(%rsp) # 8-byte Spill
xorl %ecx, %ecx
movl $208, %eax
movl 20(%rsp), %edx # 4-byte Reload
movl 16(%rsp), %r11d # 4-byte Reload
movl 12(%rsp), %r12d # 4-byte Reload
movl 8(%rsp), %r13d # 4-byte Reload
movl 120(%rsp), %ebx # 4-byte Reload
movl 112(%rsp), %r15d # 4-byte Reload
movl 156(%rsp), %r14d # 4-byte Reload
movl 152(%rsp), %r10d # 4-byte Reload
.p2align 4, 0x90
.LBB1_44: # Parent Loop BB1_41 Depth=1
# Parent Loop BB1_42 Depth=2
# Parent Loop BB1_43 Depth=3
# => This Inner Loop Header: Depth=4
movl -208(%rbp,%rax), %esi
imull 80(%rsp), %esi # 4-byte Folded Reload
addl %ecx, %esi
movl -204(%rbp,%rax), %ecx
imull 88(%rsp), %ecx # 4-byte Folded Reload
movl -200(%rbp,%rax), %edi
imull 76(%rsp), %edi # 4-byte Folded Reload
addl %ecx, %edi
addl %esi, %edi
movl -196(%rbp,%rax), %ecx
imull 72(%rsp), %ecx # 4-byte Folded Reload
movl -192(%rbp,%rax), %esi
imull 68(%rsp), %esi # 4-byte Folded Reload
addl %ecx, %esi
movl -160(%rbp,%rax), %r8d
imull 64(%rsp), %r8d # 4-byte Folded Reload
addl %esi, %r8d
addl %edi, %r8d
movl -156(%rbp,%rax), %ecx
imull 60(%rsp), %ecx # 4-byte Folded Reload
movl -152(%rbp,%rax), %esi
imull 56(%rsp), %esi # 4-byte Folded Reload
addl %ecx, %esi
movl -148(%rbp,%rax), %edi
imull 52(%rsp), %edi # 4-byte Folded Reload
addl %esi, %edi
movl -144(%rbp,%rax), %ecx
imull 48(%rsp), %ecx # 4-byte Folded Reload
addl %edi, %ecx
addl %r8d, %ecx
movl -112(%rbp,%rax), %esi
imull 44(%rsp), %esi # 4-byte Folded Reload
movl -108(%rbp,%rax), %edi
imull 40(%rsp), %edi # 4-byte Folded Reload
addl %esi, %edi
movl -104(%rbp,%rax), %esi
imull 32(%rsp), %esi # 4-byte Folded Reload
addl %edi, %esi
movl -100(%rbp,%rax), %edi
imull 28(%rsp), %edi # 4-byte Folded Reload
addl %esi, %edi
movl -96(%rbp,%rax), %esi
imull 24(%rsp), %esi # 4-byte Folded Reload
addl %edi, %esi
addl %ecx, %esi
movl -64(%rbp,%rax), %ecx
imull %edx, %ecx
movl -56(%rbp,%rax), %edi
imull %r11d, %edi
addl %ecx, %edi
movl -52(%rbp,%rax), %ecx
imull %r12d, %ecx
addl %edi, %ecx
movl -48(%rbp,%rax), %edi
imull %r13d, %edi
addl %ecx, %edi
movl -16(%rbp,%rax), %r8d
imull %ebx, %r8d
addl %edi, %r8d
movl -8(%rbp,%rax), %ecx
imull %r15d, %ecx
movl -4(%rbp,%rax), %edi
imull %r14d, %edi
addl %ecx, %edi
movl (%rbp,%rax), %r9d
imull %r10d, %r9d
addl %edi, %r9d
movl -60(%rbp,%rax), %ecx
imull 36(%rsp), %ecx # 4-byte Folded Reload
addl %r8d, %ecx
addl %esi, %ecx
addl %r9d, %ecx
addq $576, %rax # imm = 0x240
cmpq $18640, %rax # imm = 0x48D0
jne .LBB1_44
# %bb.45: # in Loop: Header=BB1_43 Depth=3
movq 128(%rsp), %rax # 8-byte Reload
movq 136(%rsp), %rdx # 8-byte Reload
movl %ecx, (%rax,%rdx,4)
orl 104(%rsp), %edx # 4-byte Folded Reload
movl $.L.str.4, %edi
movq 96(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
addq $4, %rbp
movq 144(%rsp), %rax # 8-byte Reload
movq %rax, %rcx
cmpq $8, %rax
jne .LBB1_43
# %bb.46: # in Loop: Header=BB1_42 Depth=2
movl $10, %edi
callq putchar@PLT
movq 176(%rsp), %rax # 8-byte Reload
incq %rax
movq 184(%rsp), %rbp # 8-byte Reload
addq $48, %rbp
cmpq $8, %rax
jne .LBB1_42
# %bb.47: # in Loop: Header=BB1_41 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 96(%rsp), %rcx # 8-byte Reload
incq %rcx
cmpq $64, %rcx
jne .LBB1_41
# %bb.48:
xorl %ebx, %ebx
movl $.L.str.5, %edi
movl $4, %esi
movl $8, %edx
movl $64, %ecx
xorl %eax, %eax
callq printf
leaq 6256(%rsp), %rax
leaq 215188(%rsp), %rcx
jmp .LBB1_49
.p2align 4, 0x90
.LBB1_55: # in Loop: Header=BB1_49 Depth=1
incq %rbx
addq $64, %rax
addq $256, %rcx # imm = 0x100
cmpq $64, %rbx
je .LBB1_56
.LBB1_49: # %.preheader805
# =>This Loop Header: Depth=1
# Child Loop BB1_50 Depth 2
# Child Loop BB1_51 Depth 3
movq %rcx, %rdx
xorl %edi, %edi
xorl %esi, %esi
jmp .LBB1_50
.p2align 4, 0x90
.LBB1_54: # in Loop: Header=BB1_50 Depth=2
addl %r8d, %esi
leaq 2(%rdi), %r8
addq $64, %rdx
cmpq $6, %rdi
movq %r8, %rdi
jae .LBB1_55
.LBB1_50: # %.preheader804
# Parent Loop BB1_49 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_51 Depth 3
movslq %esi, %r8
leaq (%rax,%r8,4), %r9
xorl %r8d, %r8d
jmp .LBB1_51
.p2align 4, 0x90
.LBB1_53: # in Loop: Header=BB1_51 Depth=3
cmpl %r10d, %r11d
cmovlel %r14d, %r15d
cmpl %ebp, %r11d
cmovlel %r14d, %r15d
movslq %r15d, %r10
imulq $1759218605, %r10, %r10 # imm = 0x68DB8BAD
movq %r10, %r11
shrq $63, %r11
sarq $40, %r10
addl %r11d, %r10d
movl %r10d, (%r9,%r8,4)
incq %r8
cmpl $4, %r8d
je .LBB1_54
.LBB1_51: # Parent Loop BB1_49 Depth=1
# Parent Loop BB1_50 Depth=2
# => This Inner Loop Header: Depth=3
movl -36(%rdx,%r8,8), %r14d
movl -32(%rdx,%r8,8), %r10d
cmpl %r14d, %r10d
movl %r14d, %r15d
cmovgl %r10d, %r15d
movl (%rdx,%r8,8), %r11d
cmpl %r11d, %r10d
cmovlel %r14d, %r15d
movl -4(%rdx,%r8,8), %ebp
cmpl %ebp, %r10d
cmovlel %r14d, %r15d
cmpl %ebp, %r15d
movl %ebp, %r14d
cmovgl %r15d, %r14d
cmpl %r11d, %ebp
cmovlel %r15d, %r14d
cmpl %r10d, %ebp
cmovlel %r15d, %r14d
movl %r14d, %r15d
cmpl %r11d, %r14d
jg .LBB1_53
# %bb.52: # in Loop: Header=BB1_51 Depth=3
movl %r11d, %r15d
jmp .LBB1_53
.LBB1_56: # %.preheader802.preheader
leaq 323696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_57: # %.preheader802
# =>This Loop Header: Depth=1
# Child Loop BB1_58 Depth 2
movl 240(%rsp,%rcx,4), %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_58: # Parent Loop BB1_57 Depth=1
# => This Inner Loop Header: Depth=2
movl 6256(%rsp,%rsi,4), %edi
imull (%rax,%rsi,4), %edi
addl %edi, %edx
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB1_58
# %bb.59: # in Loop: Header=BB1_57 Depth=1
movl %edx, 240(%rsp,%rcx,4)
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $64, %rcx
jne .LBB1_57
# %bb.60: # %.preheader.preheader
leaq 3696(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_61: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_62 Depth 2
movl 192(%rsp,%rcx,4), %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_62: # Parent Loop BB1_61 Depth=1
# => This Inner Loop Header: Depth=2
movl 240(%rsp,%rsi,4), %edi
imull (%rax,%rsi,4), %edi
addl %edi, %edx
incq %rsi
cmpq $64, %rsi
jne .LBB1_62
# %bb.63: # in Loop: Header=BB1_61 Depth=1
movl %edx, 192(%rsp,%rcx,4)
incq %rcx
addq $256, %rax # imm = 0x100
cmpq $10, %rcx
jne .LBB1_61
# %bb.64:
callq clock
subq 160(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $585848, %rsp # imm = 0x8F078
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Maxpool[%d][%d] : %d \t"
.size .L.str, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "dim: %d
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "result2[%d][%d]=%d\t"
.size .L.str.4, 20
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "dim: %d
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "time taken by cpu : %f seconds"
.size .L.str.6, 31
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "\n\n"
.size .Lstr.1, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include "cuda_runtime_api.h"
int main(int argc, char* argv[]) {
(void)argc;
(void)argv;
cudaSetDevice(0);
cudaEvent_t start;
cudaEvent_t end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
cudaEventRecord(end);
cudaEventSynchronize(end);
float elapsed_time;
cudaEventElapsedTime(&elapsed_time, start, end);
std::cout << "elapsed_time: " << elapsed_time << std::endl;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include "cuda_runtime_api.h"
int main(int argc, char* argv[]) {
(void)argc;
(void)argv;
cudaSetDevice(0);
cudaEvent_t start;
cudaEvent_t end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
cudaEventRecord(end);
cudaEventSynchronize(end);
float elapsed_time;
cudaEventElapsedTime(&elapsed_time, start, end);
std::cout << "elapsed_time: " << elapsed_time << std::endl;
} | .file "tmpxft_001b7b27_00000000-6_cuda_simple_func_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "elapsed_time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include "cuda_runtime_api.h"
int main(int argc, char* argv[]) {
(void)argc;
(void)argv;
cudaSetDevice(0);
cudaEvent_t start;
cudaEvent_t end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
cudaEventRecord(end);
cudaEventSynchronize(end);
float elapsed_time;
cudaEventElapsedTime(&elapsed_time, start, end);
std::cout << "elapsed_time: " << elapsed_time << std::endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include "hip/hip_runtime_api.h"
int main(int argc, char* argv[]) {
(void)argc;
(void)argv;
hipSetDevice(0);
hipEvent_t start;
hipEvent_t end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
hipEventRecord(end);
hipEventSynchronize(end);
float elapsed_time;
hipEventElapsedTime(&elapsed_time, start, end);
std::cout << "elapsed_time: " << elapsed_time << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include "hip/hip_runtime_api.h"
int main(int argc, char* argv[]) {
(void)argc;
(void)argv;
hipSetDevice(0);
hipEvent_t start;
hipEvent_t end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
hipEventRecord(end);
hipEventSynchronize(end);
float elapsed_time;
hipEventElapsedTime(&elapsed_time, start, end);
std::cout << "elapsed_time: " << elapsed_time << std::endl;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include "hip/hip_runtime_api.h"
int main(int argc, char* argv[]) {
(void)argc;
(void)argv;
hipSetDevice(0);
hipEvent_t start;
hipEvent_t end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
hipEventRecord(end);
hipEventSynchronize(end);
float elapsed_time;
hipEventElapsedTime(&elapsed_time, start, end);
std::cout << "elapsed_time: " << elapsed_time << std::endl;
} | .text
.file "cuda_simple_func_test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "elapsed_time: "
.size .L.str, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b7b27_00000000-6_cuda_simple_func_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "elapsed_time: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_simple_func_test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "elapsed_time: "
.size .L.str, 15
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <vector>
#include <iostream>
#include <stdio.h>
/*
To compile, use: nvcc -Xcompiler /wd4819 test1.cu
*/
void vecAddonHost(double *h_A,double *h_B,double *h_C,int n) {
for (int i=0; i<n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
// CUDA kernel
// each thread for each element
__global__
void vecAddKernel(double *A, double *B, double *C, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i<n) C[i] = A[i] + B[i];
}
void vecAddonDevice(double *h_A,double *h_B,double *h_C,int n) {
int size = n * sizeof(double);
double *d_A, *d_B, *d_C;
cudaError_t error;
error=cudaMalloc((void **) &d_A, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMalloc((void **) &d_B, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMalloc((void **) &d_C, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
vecAddKernel<<<ceil(n/256.0), 256>>>(d_A, d_B, d_C, n);
error=cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
// free memory
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
}
int main(int argc, char **argv) {
int N = 1000;
double *h_A = new double[N];
double *h_B = new double[N];
double *h_C = new double[N];
// initialize on host
for (int i=0; i<N; i++) {
h_A[i] = i;
h_B[i] = i*i;
}
for (int i=0; i<N; i++) h_C[i] = 0.0;
// perform C=A+B on host
vecAddonHost( h_A, h_B, h_C, N);
// output
std::cout << "host answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
// clean up C
std::cout << "cleaning up" << std::endl;
for (int i=0; i<N; i++) h_C[i] = 0.0;
// run cuda add
std::cout << "run cuda add" << std::endl;
vecAddonDevice( h_A, h_B, h_C, N);
// output
std::cout << "device answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
delete[] h_A;
delete[] h_B;
delete[] h_C;
return 0;
} | code for sm_80
Function : _Z12vecAddKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <vector>
#include <iostream>
#include <stdio.h>
/*
To compile, use: nvcc -Xcompiler /wd4819 test1.cu
*/
void vecAddonHost(double *h_A,double *h_B,double *h_C,int n) {
for (int i=0; i<n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
// CUDA kernel
// each thread for each element
__global__
void vecAddKernel(double *A, double *B, double *C, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i<n) C[i] = A[i] + B[i];
}
void vecAddonDevice(double *h_A,double *h_B,double *h_C,int n) {
int size = n * sizeof(double);
double *d_A, *d_B, *d_C;
cudaError_t error;
error=cudaMalloc((void **) &d_A, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMalloc((void **) &d_B, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMalloc((void **) &d_C, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
vecAddKernel<<<ceil(n/256.0), 256>>>(d_A, d_B, d_C, n);
error=cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
// free memory
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
}
int main(int argc, char **argv) {
int N = 1000;
double *h_A = new double[N];
double *h_B = new double[N];
double *h_C = new double[N];
// initialize on host
for (int i=0; i<N; i++) {
h_A[i] = i;
h_B[i] = i*i;
}
for (int i=0; i<N; i++) h_C[i] = 0.0;
// perform C=A+B on host
vecAddonHost( h_A, h_B, h_C, N);
// output
std::cout << "host answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
// clean up C
std::cout << "cleaning up" << std::endl;
for (int i=0; i<N; i++) h_C[i] = 0.0;
// run cuda add
std::cout << "run cuda add" << std::endl;
vecAddonDevice( h_A, h_B, h_C, N);
// output
std::cout << "device answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
delete[] h_A;
delete[] h_B;
delete[] h_C;
return 0;
} | .file "tmpxft_000e06bd_00000000-6_test1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12vecAddonHostPdS_S_i
.type _Z12vecAddonHostPdS_S_i, @function
_Z12vecAddonHostPdS_S_i:
.LFB4032:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L5:
movsd (%rdi,%rax), %xmm0
addsd (%rsi,%rax), %xmm0
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE4032:
.size _Z12vecAddonHostPdS_S_i, .-_Z12vecAddonHostPdS_S_i
.globl _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.type _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i:
.LFB4059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4059:
.size _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, .-_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.type _Z12vecAddKernelPdS_S_i, @function
_Z12vecAddKernelPdS_S_i:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _Z12vecAddKernelPdS_S_i, .-_Z12vecAddKernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/wingkitlee0/cuda-tests/master/test1/test1.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z14vecAddonDevicePdS_S_i
.type _Z14vecAddonDevicePdS_S_i, @function
_Z14vecAddonDevicePdS_S_i:
.LFB4033:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,8), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC6(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L21
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L21:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L22:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $31, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $37, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $43, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $49, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $55, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
jmp .L22
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $63, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4033:
.size _Z14vecAddonDevicePdS_S_i, .-_Z14vecAddonDevicePdS_S_i
.section .rodata.str1.1
.LC8:
.string "host answer (first 5 only):"
.LC9:
.string " "
.LC10:
.string "cleaning up"
.LC11:
.string "run cuda add"
.LC12:
.string "device answer (first 5 only):"
.text
.globl main
.type main, @function
main:
.LFB4034:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $8000, %edi
call _Znam@PLT
movq %rax, %r12
movl $8000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $8000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %eax
.L35:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r12,%rax,8)
movl %eax, %edx
imull %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L35
movq 8(%rsp), %rax
movq %rax, %r14
leaq 8000(%rax), %rbx
.L36:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rbx, %rax
jne .L36
movl $1000, %ecx
movq 8(%rsp), %r13
movq %r13, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12vecAddonHostPdS_S_i
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 40(%r13), %r15
.L37:
movsd 0(%r13), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC9(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %r13
cmpq %r15, %r13
jne .L37
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rax
.L38:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rbx, %rax
jne .L38
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1000, %ecx
movq 8(%rsp), %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14vecAddonDevicePdS_S_i
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %r13
.L39:
movsd (%r14), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %r14
cmpq %r15, %r14
jne .L39
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4034:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z12vecAddKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1064304640
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <vector>
#include <iostream>
#include <stdio.h>
/*
To compile, use: nvcc -Xcompiler /wd4819 test1.cu
*/
void vecAddonHost(double *h_A,double *h_B,double *h_C,int n) {
for (int i=0; i<n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
// CUDA kernel
// each thread for each element
__global__
void vecAddKernel(double *A, double *B, double *C, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i<n) C[i] = A[i] + B[i];
}
void vecAddonDevice(double *h_A,double *h_B,double *h_C,int n) {
int size = n * sizeof(double);
double *d_A, *d_B, *d_C;
cudaError_t error;
error=cudaMalloc((void **) &d_A, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMalloc((void **) &d_B, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=cudaMalloc((void **) &d_C, size);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
vecAddKernel<<<ceil(n/256.0), 256>>>(d_A, d_B, d_C, n);
error=cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (error != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
// free memory
cudaFree(d_A); cudaFree(d_B); cudaFree(d_C);
}
int main(int argc, char **argv) {
int N = 1000;
double *h_A = new double[N];
double *h_B = new double[N];
double *h_C = new double[N];
// initialize on host
for (int i=0; i<N; i++) {
h_A[i] = i;
h_B[i] = i*i;
}
for (int i=0; i<N; i++) h_C[i] = 0.0;
// perform C=A+B on host
vecAddonHost( h_A, h_B, h_C, N);
// output
std::cout << "host answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
// clean up C
std::cout << "cleaning up" << std::endl;
for (int i=0; i<N; i++) h_C[i] = 0.0;
// run cuda add
std::cout << "run cuda add" << std::endl;
vecAddonDevice( h_A, h_B, h_C, N);
// output
std::cout << "device answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
delete[] h_A;
delete[] h_B;
delete[] h_C;
return 0;
} | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <stdio.h>
/*
To compile, use: nvcc -Xcompiler /wd4819 test1.cu
*/
void vecAddonHost(double *h_A,double *h_B,double *h_C,int n) {
for (int i=0; i<n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
// CUDA kernel
// each thread for each element
__global__
void vecAddKernel(double *A, double *B, double *C, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i<n) C[i] = A[i] + B[i];
}
void vecAddonDevice(double *h_A,double *h_B,double *h_C,int n) {
int size = n * sizeof(double);
double *d_A, *d_B, *d_C;
hipError_t error;
error=hipMalloc((void **) &d_A, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMalloc((void **) &d_B, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMalloc((void **) &d_C, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
vecAddKernel<<<ceil(n/256.0), 256>>>(d_A, d_B, d_C, n);
error=hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
// free memory
hipFree(d_A); hipFree(d_B); hipFree(d_C);
}
int main(int argc, char **argv) {
int N = 1000;
double *h_A = new double[N];
double *h_B = new double[N];
double *h_C = new double[N];
// initialize on host
for (int i=0; i<N; i++) {
h_A[i] = i;
h_B[i] = i*i;
}
for (int i=0; i<N; i++) h_C[i] = 0.0;
// perform C=A+B on host
vecAddonHost( h_A, h_B, h_C, N);
// output
std::cout << "host answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
// clean up C
std::cout << "cleaning up" << std::endl;
for (int i=0; i<N; i++) h_C[i] = 0.0;
// run cuda add
std::cout << "run cuda add" << std::endl;
vecAddonDevice( h_A, h_B, h_C, N);
// output
std::cout << "device answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
delete[] h_A;
delete[] h_B;
delete[] h_C;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <stdio.h>
/*
To compile, use: nvcc -Xcompiler /wd4819 test1.cu
*/
void vecAddonHost(double *h_A,double *h_B,double *h_C,int n) {
for (int i=0; i<n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
// CUDA kernel
// each thread for each element
__global__
void vecAddKernel(double *A, double *B, double *C, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i<n) C[i] = A[i] + B[i];
}
void vecAddonDevice(double *h_A,double *h_B,double *h_C,int n) {
int size = n * sizeof(double);
double *d_A, *d_B, *d_C;
hipError_t error;
error=hipMalloc((void **) &d_A, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMalloc((void **) &d_B, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMalloc((void **) &d_C, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
vecAddKernel<<<ceil(n/256.0), 256>>>(d_A, d_B, d_C, n);
error=hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
// free memory
hipFree(d_A); hipFree(d_B); hipFree(d_C);
}
int main(int argc, char **argv) {
int N = 1000;
double *h_A = new double[N];
double *h_B = new double[N];
double *h_C = new double[N];
// initialize on host
for (int i=0; i<N; i++) {
h_A[i] = i;
h_B[i] = i*i;
}
for (int i=0; i<N; i++) h_C[i] = 0.0;
// perform C=A+B on host
vecAddonHost( h_A, h_B, h_C, N);
// output
std::cout << "host answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
// clean up C
std::cout << "cleaning up" << std::endl;
for (int i=0; i<N; i++) h_C[i] = 0.0;
// run cuda add
std::cout << "run cuda add" << std::endl;
vecAddonDevice( h_A, h_B, h_C, N);
// output
std::cout << "device answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
delete[] h_A;
delete[] h_B;
delete[] h_C;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.p2align 8
.type _Z12vecAddKernelPdS_S_i,@function
_Z12vecAddKernelPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPdS_S_i, .Lfunc_end0-_Z12vecAddKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#include <stdio.h>
/*
To compile, use: nvcc -Xcompiler /wd4819 test1.cu
*/
void vecAddonHost(double *h_A,double *h_B,double *h_C,int n) {
for (int i=0; i<n; i++) {
h_C[i] = h_A[i] + h_B[i];
}
}
// CUDA kernel
// each thread for each element
__global__
void vecAddKernel(double *A, double *B, double *C, int n) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i<n) C[i] = A[i] + B[i];
}
void vecAddonDevice(double *h_A,double *h_B,double *h_C,int n) {
int size = n * sizeof(double);
double *d_A, *d_B, *d_C;
hipError_t error;
error=hipMalloc((void **) &d_A, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMalloc((void **) &d_B, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
error=hipMalloc((void **) &d_C, size);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
vecAddKernel<<<ceil(n/256.0), 256>>>(d_A, d_B, d_C, n);
error=hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (error != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(error),__FILE__,__LINE__);
exit(EXIT_FAILURE);
}
// free memory
hipFree(d_A); hipFree(d_B); hipFree(d_C);
}
int main(int argc, char **argv) {
int N = 1000;
double *h_A = new double[N];
double *h_B = new double[N];
double *h_C = new double[N];
// initialize on host
for (int i=0; i<N; i++) {
h_A[i] = i;
h_B[i] = i*i;
}
for (int i=0; i<N; i++) h_C[i] = 0.0;
// perform C=A+B on host
vecAddonHost( h_A, h_B, h_C, N);
// output
std::cout << "host answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
// clean up C
std::cout << "cleaning up" << std::endl;
for (int i=0; i<N; i++) h_C[i] = 0.0;
// run cuda add
std::cout << "run cuda add" << std::endl;
vecAddonDevice( h_A, h_B, h_C, N);
// output
std::cout << "device answer (first 5 only):" << std::endl;
for (int i=0; i<5; i++) {
std::cout << h_C[i] << " ";
}
std::cout << std::endl;
delete[] h_A;
delete[] h_B;
delete[] h_C;
return 0;
} | .text
.file "test1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12vecAddonHostPdS_S_i # -- Begin function _Z12vecAddonHostPdS_S_i
.p2align 4, 0x90
.type _Z12vecAddonHostPdS_S_i,@function
_Z12vecAddonHostPdS_S_i: # @_Z12vecAddonHostPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rsi,%rcx,8), %xmm0
movsd %xmm0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z12vecAddonHostPdS_S_i, .Lfunc_end0-_Z12vecAddonHostPdS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPdS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPdS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPdS_S_i,@function
_Z27__device_stub__vecAddKernelPdS_S_i: # @_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__vecAddKernelPdS_S_i, .Lfunc_end1-_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14vecAddonDevicePdS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z14vecAddonDevicePdS_S_i
.p2align 4, 0x90
.type _Z14vecAddonDevicePdS_S_i,@function
_Z14vecAddonDevicePdS_S_i: # @_Z14vecAddonDevicePdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,8), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_8
# %bb.9:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_10
# %bb.11:
cvtsi2sd %r15d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $31, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $37, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $43, %ecx
jmp .LBB2_2
.LBB2_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
jmp .LBB2_2
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $55, %ecx
jmp .LBB2_2
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $63, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14vecAddonDevicePdS_S_i, .Lfunc_end2-_Z14vecAddonDevicePdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %rbx
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r14
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movl %eax, %ecx
imull %eax, %ecx
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movsd %xmm0, (%rbx,%rax,8)
movsd %xmm1, (%r14,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %r12d, %r12d
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%r12,8), %xmm0
movsd %xmm0, (%r15,%r12,8)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_3
# %bb.4: # %_Z12vecAddonHostPdS_S_i.exit
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB3_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB3_8
.LBB3_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $5, %r12
jne .LBB3_9
# %bb.10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r12)
je .LBB3_13
# %bb.12:
movzbl 67(%r12), %eax
jmp .LBB3_14
.LBB3_13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r12)
je .LBB3_17
# %bb.16:
movzbl 67(%r12), %eax
jmp .LBB3_18
.LBB3_17:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r12)
je .LBB3_21
# %bb.20:
movzbl 67(%r12), %eax
jmp .LBB3_22
.LBB3_21:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1000, %ecx # imm = 0x3E8
callq _Z14vecAddonDevicePdS_S_i
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB3_25
# %bb.24:
movzbl 67(%r12), %eax
jmp .LBB3_26
.LBB3_25:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_27: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $5, %r12
jne .LBB3_27
# %bb.28:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r12)
je .LBB3_31
# %bb.30:
movzbl 67(%r12), %eax
jmp .LBB3_32
.LBB3_31:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_33:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPdS_S_i,@object # @_Z12vecAddKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPdS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPdS_S_i:
.quad _Z27__device_stub__vecAddKernelPdS_S_i
.size _Z12vecAddKernelPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/wingkitlee0/cuda-tests/master/test1/test1.hip"
.size .L.str.1, 103
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "host answer (first 5 only):"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cleaning up"
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "run cuda add"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "device answer (first 5 only):"
.size .L.str.6, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPdS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPdS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vecAddKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vecAddKernelPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.p2align 8
.type _Z12vecAddKernelPdS_S_i,@function
_Z12vecAddKernelPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vecAddKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vecAddKernelPdS_S_i, .Lfunc_end0-_Z12vecAddKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vecAddKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vecAddKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e06bd_00000000-6_test1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4037:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12vecAddonHostPdS_S_i
.type _Z12vecAddonHostPdS_S_i, @function
_Z12vecAddonHostPdS_S_i:
.LFB4032:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
salq $3, %rcx
movl $0, %eax
.L5:
movsd (%rdi,%rax), %xmm0
addsd (%rsi,%rax), %xmm0
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE4032:
.size _Z12vecAddonHostPdS_S_i, .-_Z12vecAddonHostPdS_S_i
.globl _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.type _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, @function
_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i:
.LFB4059:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4059:
.size _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i, .-_Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
.globl _Z12vecAddKernelPdS_S_i
.type _Z12vecAddKernelPdS_S_i, @function
_Z12vecAddKernelPdS_S_i:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _Z12vecAddKernelPdS_S_i, .-_Z12vecAddKernelPdS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/wingkitlee0/cuda-tests/master/test1/test1.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z14vecAddonDevicePdS_S_i
.type _Z14vecAddonDevicePdS_S_i, @function
_Z14vecAddonDevicePdS_S_i:
.LFB4033:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,8), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L26
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L29
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L30
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC6(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L21
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L21:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L22:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L32
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $31, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L27:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $37, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L28:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $43, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $49, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $55, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L31:
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z12vecAddKernelPdS_S_iPdS_S_i
jmp .L22
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $63, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4033:
.size _Z14vecAddonDevicePdS_S_i, .-_Z14vecAddonDevicePdS_S_i
.section .rodata.str1.1
.LC8:
.string "host answer (first 5 only):"
.LC9:
.string " "
.LC10:
.string "cleaning up"
.LC11:
.string "run cuda add"
.LC12:
.string "device answer (first 5 only):"
.text
.globl main
.type main, @function
main:
.LFB4034:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $8000, %edi
call _Znam@PLT
movq %rax, %r12
movl $8000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $8000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %eax
.L35:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%r12,%rax,8)
movl %eax, %edx
imull %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
movsd %xmm0, 0(%rbp,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L35
movq 8(%rsp), %rax
movq %rax, %r14
leaq 8000(%rax), %rbx
.L36:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rbx, %rax
jne .L36
movl $1000, %ecx
movq 8(%rsp), %r13
movq %r13, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12vecAddonHostPdS_S_i
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 40(%r13), %r15
.L37:
movsd 0(%r13), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC9(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %r13
cmpq %r15, %r13
jne .L37
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rax
.L38:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rbx, %rax
jne .L38
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1000, %ecx
movq 8(%rsp), %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14vecAddonDevicePdS_S_i
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %r13
.L39:
movsd (%r14), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $8, %r14
cmpq %r15, %r14
jne .L39
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call _ZdaPv@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4034:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z12vecAddKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vecAddKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1064304640
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12vecAddonHostPdS_S_i # -- Begin function _Z12vecAddonHostPdS_S_i
.p2align 4, 0x90
.type _Z12vecAddonHostPdS_S_i,@function
_Z12vecAddonHostPdS_S_i: # @_Z12vecAddonHostPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%rsi,%rcx,8), %xmm0
movsd %xmm0, (%rdx,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z12vecAddonHostPdS_S_i, .Lfunc_end0-_Z12vecAddonHostPdS_S_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__vecAddKernelPdS_S_i # -- Begin function _Z27__device_stub__vecAddKernelPdS_S_i
.p2align 4, 0x90
.type _Z27__device_stub__vecAddKernelPdS_S_i,@function
_Z27__device_stub__vecAddKernelPdS_S_i: # @_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z27__device_stub__vecAddKernelPdS_S_i, .Lfunc_end1-_Z27__device_stub__vecAddKernelPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14vecAddonDevicePdS_S_i
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z14vecAddonDevicePdS_S_i
.p2align 4, 0x90
.type _Z14vecAddonDevicePdS_S_i,@function
_Z14vecAddonDevicePdS_S_i: # @_Z14vecAddonDevicePdS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,8), %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_8
# %bb.9:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_10
# %bb.11:
cvtsi2sd %r15d, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %r15d, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z12vecAddKernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_14
# %bb.15:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $31, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $37, %ecx
jmp .LBB2_2
.LBB2_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $43, %ecx
jmp .LBB2_2
.LBB2_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $49, %ecx
jmp .LBB2_2
.LBB2_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $55, %ecx
jmp .LBB2_2
.LBB2_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $63, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z14vecAddonDevicePdS_S_i, .Lfunc_end2-_Z14vecAddonDevicePdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %rbx
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r14
movl $8000, %edi # imm = 0x1F40
callq _Znam
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movl %eax, %ecx
imull %eax, %ecx
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movsd %xmm0, (%rbx,%rax,8)
movsd %xmm1, (%r14,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB3_1
# %bb.2: # %.preheader.preheader
xorl %r12d, %r12d
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%r12,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%r12,8), %xmm0
movsd %xmm0, (%r15,%r12,8)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB3_3
# %bb.4: # %_Z12vecAddonHostPdS_S_i.exit
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB3_7
# %bb.6:
movzbl 67(%r12), %eax
jmp .LBB3_8
.LBB3_7:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_9: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $5, %r12
jne .LBB3_9
# %bb.10:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r12)
je .LBB3_13
# %bb.12:
movzbl 67(%r12), %eax
jmp .LBB3_14
.LBB3_13:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r12)
je .LBB3_17
# %bb.16:
movzbl 67(%r12), %eax
jmp .LBB3_18
.LBB3_17:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $8000, %edx # imm = 0x1F40
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r12)
je .LBB3_21
# %bb.20:
movzbl 67(%r12), %eax
jmp .LBB3_22
.LBB3_21:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1000, %ecx # imm = 0x3E8
callq _Z14vecAddonDevicePdS_S_i
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB3_25
# %bb.24:
movzbl 67(%r12), %eax
jmp .LBB3_26
.LBB3_25:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_27: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq $5, %r12
jne .LBB3_27
# %bb.28:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_33
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%r12)
je .LBB3_31
# %bb.30:
movzbl 67(%r12), %eax
jmp .LBB3_32
.LBB3_31:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_33:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vecAddKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vecAddKernelPdS_S_i,@object # @_Z12vecAddKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z12vecAddKernelPdS_S_i
.p2align 3, 0x0
_Z12vecAddKernelPdS_S_i:
.quad _Z27__device_stub__vecAddKernelPdS_S_i
.size _Z12vecAddKernelPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/wingkitlee0/cuda-tests/master/test1/test1.hip"
.size .L.str.1, 103
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "host answer (first 5 only):"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cleaning up"
.size .L.str.4, 12
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "run cuda add"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "device answer (first 5 only):"
.size .L.str.6, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vecAddKernelPdS_S_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vecAddKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vecAddKernelPdS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <sys/time.h>
#define TILE_DIM 32
using namespace std;
/* cudaMallocPitch example:
* compares normal device memory allocation and allocation using cudaMallocPitch
* for different matrix sizes.
* When matrix width is not a multiple of 16 cudaMallocPitch should be preferred.
*/
// kernel for normal device memory allocation
__global__ void matmul(double *a, double* b, double *c, int aw, int bw, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*aw+i] * b[i*bw+col];
}
c[row*bw+col] = sum;
}
// kernel for allocation with cudaMallocPitch
__global__ void matmul_pitch(double *a, double* b, double *c, int aw, int bw, size_t pitch, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*pitch+i] * b[i*pitch+col];
}
c[row*pitch+col] = sum;
}
void run_matmul(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays
double *a_dev;
cudaMalloc((void**) &a_dev, ah1*aw1 * sizeof(double));
double *b_dev;
cudaMalloc((void**) &b_dev, bh1*bw1 * sizeof(double));
double *c_dev;
cudaMalloc((void**) &c_dev, ah1*bw1 * sizeof(double));
// copy to device
cudaMemcpy(a_dev, a, ah1*aw1 * sizeof(double) , cudaMemcpyHostToDevice);
cudaMemcpy(b_dev, b, bh1*bw1 * sizeof(double) , cudaMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
cudaThreadSynchronize();
gettimeofday( &tt1, NULL );
matmul <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1, enlarge);
cudaThreadSynchronize();
gettimeofday( &tt2, NULL );
// copy from device
cudaMemcpy(c, c_dev, ah1*bw1 * sizeof(double) , cudaMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "normal device memory alocation using cudaMalloc:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
}
void run_matmul_pitch(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays are allocated using cudaMallocPitch
size_t pitch;
double *a_dev;
cudaMallocPitch(&a_dev, &pitch, aw1 * sizeof(double), ah1);
double *b_dev;
cudaMallocPitch(&b_dev, &pitch, bw1 * sizeof(double), bh1);
double *c_dev;
cudaMallocPitch(&c_dev, &pitch, bw1 * sizeof(double), ah1);
// data is copied with cudaMemcpy2D
cudaMemcpy2D(a_dev, pitch, a, aw1 * sizeof(double), aw1, ah1, cudaMemcpyHostToDevice);
cudaMemcpy2D(b_dev, pitch, b, bw1 * sizeof(double), bw1, bh1, cudaMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
cudaThreadSynchronize();
gettimeofday( &tt1, NULL );
matmul_pitch <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1,
pitch/sizeof(double),enlarge);
cudaThreadSynchronize();
gettimeofday( &tt2, NULL );
// data is copied back with cudaMemcpy2D
cudaMemcpy2D(c, bw1 * sizeof(double), c_dev, pitch, bw1, ah1, cudaMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "device memory alocation using cudaMallocPitch:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
}
int main() {
int ah=2560;
int aw=2560;
int bw=2560;
// enlarges matrix dimensions given amount
// calculation is carried out over original matrix dimensions
// (*) give different values to see the effect on computation
// times of normal memory allocation and using cudaMallocPitch
int enlarge = 0;
run_matmul(ah, aw, bw, enlarge);
run_matmul_pitch(ah, aw, bw, enlarge);
} | .file "tmpxft_000315a9_00000000-6_pitchMemory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6matmulPdS_S_iiiPdS_S_iii
.type _Z32__device_stub__Z6matmulPdS_S_iiiPdS_S_iii, @function
_Z32__device_stub__Z6matmulPdS_S_iiiPdS_S_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6matmulPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z32__device_stub__Z6matmulPdS_S_iiiPdS_S_iii, .-_Z32__device_stub__Z6matmulPdS_S_iiiPdS_S_iii
.globl _Z6matmulPdS_S_iii
.type _Z6matmulPdS_S_iii, @function
_Z6matmulPdS_S_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6matmulPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z6matmulPdS_S_iii, .-_Z6matmulPdS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "-----------------------------------------------"
.align 8
.LC1:
.string "normal device memory alocation using cudaMalloc:"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Comp time = "
.LC5:
.string "GFlops = "
.LC6:
.string "value check = "
.text
.globl _Z10run_matmuliiii
.type _Z10run_matmuliiii, @function
_Z10run_matmuliiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movl %edi, %r14d
movl %edi, 28(%rsp)
movl %esi, %r13d
movl %esi, 40(%rsp)
movl %edx, %r15d
movl %ecx, %ebx
movl %ecx, 44(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %ebx, %eax
leal (%r14,%rbx), %ebp
leal 0(%r13,%rbx), %ebx
leal (%rax,%r15), %r12d
movl %ebp, %eax
imull %ebx, %eax
cltq
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r14
movl %ebx, %eax
imull %r12d, %eax
cltq
salq $3, %rax
movq %rax, 32(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebp, %eax
imull %r12d, %eax
cltq
salq $3, %rax
movq %rax, 16(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, (%rsp)
testl %ebp, %ebp
jle .L12
movl %ebx, %ecx
movl $0, %edi
movl $0, %esi
jmp .L13
.L15:
movl %esi, %eax
movslq %edi, %rdx
leaq (%r14,%rdx,8), %rdx
.L14:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdx)
addl $1, %eax
addq $8, %rdx
cmpl %eax, %ecx
jne .L14
.L16:
addl $1, %esi
addl %ebp, %edi
addl $1, %ecx
cmpl %esi, %ebp
je .L12
.L13:
testl %ebx, %ebx
jg .L15
jmp .L16
.L12:
testl %ebx, %ebx
jle .L17
movl %r12d, %ecx
negl %ecx
movl 40(%rsp), %edi
subl %r15d, %edi
movl $0, %esi
jmp .L18
.L20:
leal (%rcx,%r12), %eax
movslq %esi, %rdx
leaq 0(%r13,%rdx,8), %rdx
.L19:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdx)
subl $1, %eax
addq $8, %rdx
cmpl %ecx, %eax
jne .L19
.L21:
addl %ebx, %esi
addl $1, %ecx
cmpl %edi, %ecx
je .L17
.L18:
testl %r12d, %r12d
jg .L20
jmp .L21
.L17:
leaq 48(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq 32(%rsp), %rbp
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq 16(%rsp), %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq 8(%rsp), %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leal 31(%r15), %eax
testl %r15d, %r15d
cmovns %r15d, %eax
sarl $5, %eax
movl %eax, 72(%rsp)
movl 28(%rsp), %esi
leal 31(%rsi), %eax
testl %esi, %esi
cmovns %esi, %eax
sarl $5, %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $32, 84(%rsp)
movl $32, 88(%rsp)
movl $1, 92(%rsp)
call cudaThreadSynchronize@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L53
.L22:
call cudaThreadSynchronize@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq 16(%rsp), %rdx
movq 64(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $47, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L54
cmpb $0, 56(%rbx)
je .L25
movzbl 67(%rbx), %eax
.L26:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $48, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L55
cmpb $0, 56(%rbx)
je .L29
movzbl 67(%rbx), %eax
.L30:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 112(%rsp), %rax
subl 96(%rsp), %eax
imull $1000000, %eax, %eax
subl 104(%rsp), %eax
addl 120(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, 8(%rsp)
movl $12, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L56
cmpb $0, 56(%rbp)
je .L33
movzbl 67(%rbp), %eax
.L34:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 40(%rsp), %xmm0
addsd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 28(%rsp), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
mulsd %xmm1, %xmm0
mulsd .LC4(%rip), %xmm0
divsd 8(%rsp), %xmm0
movq %xmm0, %rbx
movl $9, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbx, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L57
cmpb $0, 56(%rbp)
je .L37
movzbl 67(%rbp), %eax
.L38:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rsp), %rax
movsd 1160(%rax), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L58
cmpb $0, 56(%rbp)
je .L41
movzbl 67(%rbp), %eax
.L42:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $47, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L59
cmpb $0, 56(%rbx)
je .L45
movzbl 67(%rbx), %eax
.L46:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movl 44(%rsp), %r9d
movl %r12d, %r8d
movl %ebx, %ecx
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z32__device_stub__Z6matmulPdS_S_iiiPdS_S_iii
jmp .L22
.L54:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L61
call _ZSt16__throw_bad_castv@PLT
.L61:
call __stack_chk_fail@PLT
.L25:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L26
.L55:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L62
call _ZSt16__throw_bad_castv@PLT
.L62:
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L30
.L56:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L63
call _ZSt16__throw_bad_castv@PLT
.L63:
call __stack_chk_fail@PLT
.L33:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L34
.L57:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
call _ZSt16__throw_bad_castv@PLT
.L64:
call __stack_chk_fail@PLT
.L37:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L38
.L58:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L65
call _ZSt16__throw_bad_castv@PLT
.L65:
call __stack_chk_fail@PLT
.L41:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L42
.L59:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L66:
call __stack_chk_fail@PLT
.L45:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L46
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z10run_matmuliiii, .-_Z10run_matmuliiii
.globl _Z40__device_stub__Z12matmul_pitchPdS_S_iimiPdS_S_iimi
.type _Z40__device_stub__Z12matmul_pitchPdS_S_iimiPdS_S_iimi, @function
_Z40__device_stub__Z12matmul_pitchPdS_S_iimiPdS_S_iimi:
.LFB3698:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12matmul_pitchPdS_S_iimi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z40__device_stub__Z12matmul_pitchPdS_S_iimiPdS_S_iimi, .-_Z40__device_stub__Z12matmul_pitchPdS_S_iimiPdS_S_iimi
.globl _Z12matmul_pitchPdS_S_iimi
.type _Z12matmul_pitchPdS_S_iimi, @function
_Z12matmul_pitchPdS_S_iimi:
.LFB3699:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z12matmul_pitchPdS_S_iimiPdS_S_iimi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z12matmul_pitchPdS_S_iimi, .-_Z12matmul_pitchPdS_S_iimi
.section .rodata.str1.8
.align 8
.LC7:
.string "device memory alocation using cudaMallocPitch:"
.text
.globl _Z16run_matmul_pitchiiii
.type _Z16run_matmul_pitchiiii, @function
_Z16run_matmul_pitchiiii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movl %edi, %r14d
movl %edi, 36(%rsp)
movl %esi, %ebp
movl %esi, 56(%rsp)
movl %edx, %r15d
movl %ecx, %ebx
movl %ecx, 60(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %ebx, %eax
addl %ebx, %r14d
leal 0(%rbp,%rbx), %ebx
leal (%rax,%r15), %ebp
movl %r14d, %edi
imull %ebx, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %edi
imull %ebp, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movl %r14d, %edi
imull %ebp, %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testl %r14d, %r14d
jle .L76
movl %ebx, %ecx
movl $0, %edi
movl $0, %esi
jmp .L77
.L79:
movl %esi, %eax
movslq %edi, %rdx
leaq 0(%r13,%rdx,8), %rdx
.L78:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdx)
addl $1, %eax
addq $8, %rdx
cmpl %eax, %ecx
jne .L78
.L80:
addl $1, %esi
addl %r14d, %edi
addl $1, %ecx
cmpl %esi, %r14d
je .L76
.L77:
testl %ebx, %ebx
jg .L79
jmp .L80
.L76:
testl %ebx, %ebx
jle .L81
movl %ebp, %ecx
negl %ecx
movl 56(%rsp), %edi
subl %r15d, %edi
movl $0, %esi
jmp .L82
.L84:
leal (%rcx,%rbp), %eax
movslq %esi, %rdx
leaq (%r12,%rdx,8), %rdx
.L83:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rdx)
subl $1, %eax
addq $8, %rdx
cmpl %ecx, %eax
jne .L83
.L85:
addl %ebx, %esi
addl $1, %ecx
cmpl %edi, %ecx
je .L81
.L82:
testl %ebp, %ebp
jg .L84
jmp .L85
.L81:
movslq %r14d, %rax
movslq %ebx, %r14
leaq 0(,%r14,8), %rdx
leaq 72(%rsp), %rsi
leaq 80(%rsp), %rdi
movq %rax, (%rsp)
movq %rax, %rcx
movq %rdx, 48(%rsp)
movq %rsi, 40(%rsp)
call cudaMallocPitch@PLT
movslq %ebp, %rdi
movq %rdi, 24(%rsp)
salq $3, %rdi
movq %rdi, %r10
leaq 88(%rsp), %rdi
movq %r14, %rcx
movq %r10, 8(%rsp)
movq %r10, %rdx
movq 40(%rsp), %rsi
call cudaMallocPitch@PLT
leaq 96(%rsp), %rdi
movq (%rsp), %rcx
movq 8(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaMallocPitch@PLT
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq $1
.cfi_def_cfa_offset 256
movq 16(%rsp), %r9
movq %r14, %r8
movq 64(%rsp), %rcx
movq %r13, %rdx
movq 88(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy2D@PLT
movl $1, (%rsp)
movq %r14, %r9
movq 40(%rsp), %r8
movq 24(%rsp), %rcx
movq %r12, %rdx
movq 88(%rsp), %rsi
movq 104(%rsp), %rdi
call cudaMemcpy2D@PLT
leal 31(%r15), %eax
addq $16, %rsp
.cfi_def_cfa_offset 240
testl %r15d, %r15d
cmovns %r15d, %eax
sarl $5, %eax
movl %eax, 104(%rsp)
movl 36(%rsp), %esi
leal 31(%rsi), %eax
testl %esi, %esi
cmovns %esi, %eax
sarl $5, %eax
movl %eax, 108(%rsp)
movl $1, 112(%rsp)
movl $32, 116(%rsp)
movl $32, 120(%rsp)
movl $1, 124(%rsp)
call cudaThreadSynchronize@PLT
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 124(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movq 104(%rsp), %rdi
movl 112(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L117
.L86:
call cudaThreadSynchronize@PLT
leaq 144(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
subq $8, %rsp
.cfi_def_cfa_offset 248
pushq $2
.cfi_def_cfa_offset 256
movq 16(%rsp), %r9
movq 40(%rsp), %r8
movq 88(%rsp), %rcx
movq 112(%rsp), %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy2D@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
movl $47, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L118
cmpb $0, 56(%rbx)
je .L89
movzbl 67(%rbx), %eax
.L90:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $46, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L119
cmpb $0, 56(%rbx)
je .L93
movzbl 67(%rbx), %eax
.L94:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 144(%rsp), %rax
subl 128(%rsp), %eax
imull $1000000, %eax, %eax
subl 136(%rsp), %eax
addl 152(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, (%rsp)
movl $12, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd (%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L120
cmpb $0, 56(%rbp)
je .L97
movzbl 67(%rbp), %eax
.L98:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 56(%rsp), %xmm0
addsd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 36(%rsp), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r15d, %xmm1
mulsd %xmm1, %xmm0
mulsd .LC4(%rip), %xmm0
divsd (%rsp), %xmm0
movq %xmm0, %rbx
movl $9, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbx, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L121
cmpb $0, 56(%rbp)
je .L101
movzbl 67(%rbp), %eax
.L102:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movsd 1160(%rax), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L122
cmpb $0, 56(%rbp)
je .L105
movzbl 67(%rbp), %eax
.L106:
movsbl %al, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $47, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L123
cmpb $0, 56(%rbx)
je .L109
movzbl 67(%rbx), %eax
.L110:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L124
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L117:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 248
movl 68(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 256
movq 88(%rsp), %r9
shrq $3, %r9
movl %ebp, %r8d
movl %ebx, %ecx
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z40__device_stub__Z12matmul_pitchPdS_S_iimiPdS_S_iimi
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L86
.L118:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L125
call _ZSt16__throw_bad_castv@PLT
.L125:
call __stack_chk_fail@PLT
.L89:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L90
.L119:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L126
call _ZSt16__throw_bad_castv@PLT
.L126:
call __stack_chk_fail@PLT
.L93:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L94
.L120:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L127
call _ZSt16__throw_bad_castv@PLT
.L127:
call __stack_chk_fail@PLT
.L97:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L98
.L121:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L128
call _ZSt16__throw_bad_castv@PLT
.L128:
call __stack_chk_fail@PLT
.L101:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L102
.L122:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L129
call _ZSt16__throw_bad_castv@PLT
.L129:
call __stack_chk_fail@PLT
.L105:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L106
.L123:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L130
call _ZSt16__throw_bad_castv@PLT
.L130:
call __stack_chk_fail@PLT
.L109:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L110
.L124:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z16run_matmul_pitchiiii, .-_Z16run_matmul_pitchiiii
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %ecx
movl $2560, %edx
movl $2560, %esi
movl $2560, %edi
call _Z10run_matmuliiii
movl $0, %ecx
movl $2560, %edx
movl $2560, %esi
movl $2560, %edi
call _Z16run_matmul_pitchiiii
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z12matmul_pitchPdS_S_iimi"
.LC9:
.string "_Z6matmulPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matmul_pitchPdS_S_iimi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPdS_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.align 8
.LC4:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <sys/time.h>
#define TILE_DIM 32
using namespace std;
/* cudaMallocPitch example:
* compares normal device memory allocation and allocation using cudaMallocPitch
* for different matrix sizes.
* When matrix width is not a multiple of 16 cudaMallocPitch should be preferred.
*/
// kernel for normal device memory allocation
__global__ void matmul(double *a, double* b, double *c, int aw, int bw, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*aw+i] * b[i*bw+col];
}
c[row*bw+col] = sum;
}
// kernel for allocation with cudaMallocPitch
__global__ void matmul_pitch(double *a, double* b, double *c, int aw, int bw, size_t pitch, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*pitch+i] * b[i*pitch+col];
}
c[row*pitch+col] = sum;
}
void run_matmul(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays
double *a_dev;
cudaMalloc((void**) &a_dev, ah1*aw1 * sizeof(double));
double *b_dev;
cudaMalloc((void**) &b_dev, bh1*bw1 * sizeof(double));
double *c_dev;
cudaMalloc((void**) &c_dev, ah1*bw1 * sizeof(double));
// copy to device
cudaMemcpy(a_dev, a, ah1*aw1 * sizeof(double) , cudaMemcpyHostToDevice);
cudaMemcpy(b_dev, b, bh1*bw1 * sizeof(double) , cudaMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
cudaThreadSynchronize();
gettimeofday( &tt1, NULL );
matmul <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1, enlarge);
cudaThreadSynchronize();
gettimeofday( &tt2, NULL );
// copy from device
cudaMemcpy(c, c_dev, ah1*bw1 * sizeof(double) , cudaMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "normal device memory alocation using cudaMalloc:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
}
void run_matmul_pitch(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays are allocated using cudaMallocPitch
size_t pitch;
double *a_dev;
cudaMallocPitch(&a_dev, &pitch, aw1 * sizeof(double), ah1);
double *b_dev;
cudaMallocPitch(&b_dev, &pitch, bw1 * sizeof(double), bh1);
double *c_dev;
cudaMallocPitch(&c_dev, &pitch, bw1 * sizeof(double), ah1);
// data is copied with cudaMemcpy2D
cudaMemcpy2D(a_dev, pitch, a, aw1 * sizeof(double), aw1, ah1, cudaMemcpyHostToDevice);
cudaMemcpy2D(b_dev, pitch, b, bw1 * sizeof(double), bw1, bh1, cudaMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
cudaThreadSynchronize();
gettimeofday( &tt1, NULL );
matmul_pitch <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1,
pitch/sizeof(double),enlarge);
cudaThreadSynchronize();
gettimeofday( &tt2, NULL );
// data is copied back with cudaMemcpy2D
cudaMemcpy2D(c, bw1 * sizeof(double), c_dev, pitch, bw1, ah1, cudaMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "device memory alocation using cudaMallocPitch:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
cudaFree(a_dev);
cudaFree(b_dev);
cudaFree(c_dev);
}
int main() {
int ah=2560;
int aw=2560;
int bw=2560;
// enlarges matrix dimensions given amount
// calculation is carried out over original matrix dimensions
// (*) give different values to see the effect on computation
// times of normal memory allocation and using cudaMallocPitch
int enlarge = 0;
run_matmul(ah, aw, bw, enlarge);
run_matmul_pitch(ah, aw, bw, enlarge);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define TILE_DIM 32
using namespace std;
/* cudaMallocPitch example:
* compares normal device memory allocation and allocation using cudaMallocPitch
* for different matrix sizes.
* When matrix width is not a multiple of 16 cudaMallocPitch should be preferred.
*/
// kernel for normal device memory allocation
__global__ void matmul(double *a, double* b, double *c, int aw, int bw, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*aw+i] * b[i*bw+col];
}
c[row*bw+col] = sum;
}
// kernel for allocation with cudaMallocPitch
__global__ void matmul_pitch(double *a, double* b, double *c, int aw, int bw, size_t pitch, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*pitch+i] * b[i*pitch+col];
}
c[row*pitch+col] = sum;
}
void run_matmul(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays
double *a_dev;
hipMalloc((void**) &a_dev, ah1*aw1 * sizeof(double));
double *b_dev;
hipMalloc((void**) &b_dev, bh1*bw1 * sizeof(double));
double *c_dev;
hipMalloc((void**) &c_dev, ah1*bw1 * sizeof(double));
// copy to device
hipMemcpy(a_dev, a, ah1*aw1 * sizeof(double) , hipMemcpyHostToDevice);
hipMemcpy(b_dev, b, bh1*bw1 * sizeof(double) , hipMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
matmul <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1, enlarge);
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
// copy from device
hipMemcpy(c, c_dev, ah1*bw1 * sizeof(double) , hipMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "normal device memory alocation using cudaMalloc:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
}
void run_matmul_pitch(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays are allocated using cudaMallocPitch
size_t pitch;
double *a_dev;
hipMallocPitch(&a_dev, &pitch, aw1 * sizeof(double), ah1);
double *b_dev;
hipMallocPitch(&b_dev, &pitch, bw1 * sizeof(double), bh1);
double *c_dev;
hipMallocPitch(&c_dev, &pitch, bw1 * sizeof(double), ah1);
// data is copied with cudaMemcpy2D
hipMemcpy2D(a_dev, pitch, a, aw1 * sizeof(double), aw1, ah1, hipMemcpyHostToDevice);
hipMemcpy2D(b_dev, pitch, b, bw1 * sizeof(double), bw1, bh1, hipMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
matmul_pitch <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1,
pitch/sizeof(double),enlarge);
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
// data is copied back with cudaMemcpy2D
hipMemcpy2D(c, bw1 * sizeof(double), c_dev, pitch, bw1, ah1, hipMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "device memory alocation using cudaMallocPitch:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
}
int main() {
int ah=2560;
int aw=2560;
int bw=2560;
// enlarges matrix dimensions given amount
// calculation is carried out over original matrix dimensions
// (*) give different values to see the effect on computation
// times of normal memory allocation and using cudaMallocPitch
int enlarge = 0;
run_matmul(ah, aw, bw, enlarge);
run_matmul_pitch(ah, aw, bw, enlarge);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define TILE_DIM 32
using namespace std;
/* cudaMallocPitch example:
* compares normal device memory allocation and allocation using cudaMallocPitch
* for different matrix sizes.
* When matrix width is not a multiple of 16 cudaMallocPitch should be preferred.
*/
// kernel for normal device memory allocation
__global__ void matmul(double *a, double* b, double *c, int aw, int bw, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*aw+i] * b[i*bw+col];
}
c[row*bw+col] = sum;
}
// kernel for allocation with cudaMallocPitch
__global__ void matmul_pitch(double *a, double* b, double *c, int aw, int bw, size_t pitch, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*pitch+i] * b[i*pitch+col];
}
c[row*pitch+col] = sum;
}
void run_matmul(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays
double *a_dev;
hipMalloc((void**) &a_dev, ah1*aw1 * sizeof(double));
double *b_dev;
hipMalloc((void**) &b_dev, bh1*bw1 * sizeof(double));
double *c_dev;
hipMalloc((void**) &c_dev, ah1*bw1 * sizeof(double));
// copy to device
hipMemcpy(a_dev, a, ah1*aw1 * sizeof(double) , hipMemcpyHostToDevice);
hipMemcpy(b_dev, b, bh1*bw1 * sizeof(double) , hipMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
matmul <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1, enlarge);
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
// copy from device
hipMemcpy(c, c_dev, ah1*bw1 * sizeof(double) , hipMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "normal device memory alocation using cudaMalloc:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
}
void run_matmul_pitch(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays are allocated using cudaMallocPitch
size_t pitch;
double *a_dev;
hipMallocPitch(&a_dev, &pitch, aw1 * sizeof(double), ah1);
double *b_dev;
hipMallocPitch(&b_dev, &pitch, bw1 * sizeof(double), bh1);
double *c_dev;
hipMallocPitch(&c_dev, &pitch, bw1 * sizeof(double), ah1);
// data is copied with cudaMemcpy2D
hipMemcpy2D(a_dev, pitch, a, aw1 * sizeof(double), aw1, ah1, hipMemcpyHostToDevice);
hipMemcpy2D(b_dev, pitch, b, bw1 * sizeof(double), bw1, bh1, hipMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
matmul_pitch <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1,
pitch/sizeof(double),enlarge);
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
// data is copied back with cudaMemcpy2D
hipMemcpy2D(c, bw1 * sizeof(double), c_dev, pitch, bw1, ah1, hipMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "device memory alocation using cudaMallocPitch:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
}
int main() {
int ah=2560;
int aw=2560;
int bw=2560;
// enlarges matrix dimensions given amount
// calculation is carried out over original matrix dimensions
// (*) give different values to see the effect on computation
// times of normal memory allocation and using cudaMallocPitch
int enlarge = 0;
run_matmul(ah, aw, bw, enlarge);
run_matmul_pitch(ah, aw, bw, enlarge);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPdS_S_iii
.globl _Z6matmulPdS_S_iii
.p2align 8
.type _Z6matmulPdS_S_iii,@function
_Z6matmulPdS_S_iii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s6, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
s_sub_i32 s8, s2, s5
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s2, 0
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_ge_i32 s2, s8
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s3, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPdS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPdS_S_iii, .Lfunc_end0-_Z6matmulPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12matmul_pitchPdS_S_iimi
.globl _Z12matmul_pitchPdS_S_iimi
.p2align 8
.type _Z12matmul_pitchPdS_S_iimi,@function
_Z12matmul_pitchPdS_S_iimi:
s_clause 0x3
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s5, s[0:1], 0x28
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s7, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s4, v[4:5]
s_sub_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lt_i32 s6, 1
v_ashrrev_i32_e32 v9, 31, v2
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_cbranch_scc1 .LBB1_3
s_load_b128 s[8:11], s[0:1], 0x0
v_mul_lo_u32 v5, v2, s3
v_mul_lo_u32 v6, v9, s2
v_mad_u64_u32 v[3:4], null, v2, s2, 0
v_lshlrev_b64 v[7:8], 3, v[0:1]
s_lshl_b64 s[4:5], s[2:3], 3
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v4, v5, v6
v_lshlrev_b64 v[5:6], 3, v[3:4]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
.LBB1_2:
global_load_b64 v[10:11], v[5:6], off
global_load_b64 v[12:13], v[7:8], off
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, s4
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s7, s6
s_waitcnt vmcnt(0)
v_fma_f64 v[3:4], v[10:11], v[12:13], v[3:4]
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB1_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v7, v2, s3
v_mul_lo_u32 v8, v9, s2
v_mad_u64_u32 v[5:6], null, v2, s2, 0
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v7, v8
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matmul_pitchPdS_S_iimi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12matmul_pitchPdS_S_iimi, .Lfunc_end1-_Z12matmul_pitchPdS_S_iimi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matmul_pitchPdS_S_iimi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matmul_pitchPdS_S_iimi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sys/time.h>
#define TILE_DIM 32
using namespace std;
/* cudaMallocPitch example:
* compares normal device memory allocation and allocation using cudaMallocPitch
* for different matrix sizes.
* When matrix width is not a multiple of 16 cudaMallocPitch should be preferred.
*/
// kernel for normal device memory allocation
__global__ void matmul(double *a, double* b, double *c, int aw, int bw, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*aw+i] * b[i*bw+col];
}
c[row*bw+col] = sum;
}
// kernel for allocation with cudaMallocPitch
__global__ void matmul_pitch(double *a, double* b, double *c, int aw, int bw, size_t pitch, int enlarge) {
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
double sum = 0.0;
for (int i = 0; i < aw-enlarge; i++) {
sum += a[row*pitch+i] * b[i*pitch+col];
}
c[row*pitch+col] = sum;
}
void run_matmul(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays
double *a_dev;
hipMalloc((void**) &a_dev, ah1*aw1 * sizeof(double));
double *b_dev;
hipMalloc((void**) &b_dev, bh1*bw1 * sizeof(double));
double *c_dev;
hipMalloc((void**) &c_dev, ah1*bw1 * sizeof(double));
// copy to device
hipMemcpy(a_dev, a, ah1*aw1 * sizeof(double) , hipMemcpyHostToDevice);
hipMemcpy(b_dev, b, bh1*bw1 * sizeof(double) , hipMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
matmul <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1, enlarge);
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
// copy from device
hipMemcpy(c, c_dev, ah1*bw1 * sizeof(double) , hipMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "normal device memory alocation using cudaMalloc:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
}
void run_matmul_pitch(int ah, int aw, int bw, int enlarge) {
time_t sTime = time(NULL);
timeval tt1, tt2;
int ms;
double fms;
int bh=aw;
int ah1 = ah + enlarge;
int aw1 = aw + enlarge;
int bh1 = bh + enlarge;
int bw1 = bw + enlarge;
// host arrays
double *a = (double*)malloc(ah1*aw1*sizeof(double));
double *b = (double*)malloc(bh1*bw1*sizeof(double));
double *c = (double*)malloc(ah1*bw1*sizeof(double));
for (int i=0;i<ah1;i++)
for (int j=0;j<aw1;j++)
a[i*ah1+j] = (double)(i+j);
for (int i=0;i<bh1;i++)
for (int j=0;j<bw1;j++)
b[i*bh1+j] = (double)(i-j);
// device arrays are allocated using cudaMallocPitch
size_t pitch;
double *a_dev;
hipMallocPitch(&a_dev, &pitch, aw1 * sizeof(double), ah1);
double *b_dev;
hipMallocPitch(&b_dev, &pitch, bw1 * sizeof(double), bh1);
double *c_dev;
hipMallocPitch(&c_dev, &pitch, bw1 * sizeof(double), ah1);
// data is copied with cudaMemcpy2D
hipMemcpy2D(a_dev, pitch, a, aw1 * sizeof(double), aw1, ah1, hipMemcpyHostToDevice);
hipMemcpy2D(b_dev, pitch, b, bw1 * sizeof(double), bw1, bh1, hipMemcpyHostToDevice);
// kernel run
dim3 nBlocks(bw/TILE_DIM, ah/TILE_DIM, 1);
dim3 nThreads(TILE_DIM, TILE_DIM, 1);
hipDeviceSynchronize();
gettimeofday( &tt1, NULL );
matmul_pitch <<< nBlocks, nThreads >>> (a_dev, b_dev, c_dev, aw1, bw1,
pitch/sizeof(double),enlarge);
hipDeviceSynchronize();
gettimeofday( &tt2, NULL );
// data is copied back with cudaMemcpy2D
hipMemcpy2D(c, bw1 * sizeof(double), c_dev, pitch, bw1, ah1, hipMemcpyDeviceToHost);
// timing
cout << "-----------------------------------------------" << endl;
cout << "device memory alocation using cudaMallocPitch:" << endl;
ms = (tt2.tv_sec - tt1.tv_sec);
ms = ms * 1000000 + (tt2.tv_usec - tt1.tv_usec);
fms = ((double)ms)/1000000.0;
cout << "Comp time = " << fms << endl;
double dNumOps = 2.0 * (double)(aw) * (double)(ah) * (double)(bw);
double gflops = 1.0e-9 * dNumOps/fms;
cout << "GFlops = " << gflops << endl;
cout << "value check = " << c[145] << endl;
cout << "-----------------------------------------------" << endl;
free(a);
free(b);
free(c);
hipFree(a_dev);
hipFree(b_dev);
hipFree(c_dev);
}
int main() {
int ah=2560;
int aw=2560;
int bw=2560;
// enlarges matrix dimensions given amount
// calculation is carried out over original matrix dimensions
// (*) give different values to see the effect on computation
// times of normal memory allocation and using cudaMallocPitch
int enlarge = 0;
run_matmul(ah, aw, bw, enlarge);
run_matmul_pitch(ah, aw, bw, enlarge);
} | .text
.file "pitchMemory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matmulPdS_S_iii # -- Begin function _Z21__device_stub__matmulPdS_S_iii
.p2align 4, 0x90
.type _Z21__device_stub__matmulPdS_S_iii,@function
_Z21__device_stub__matmulPdS_S_iii: # @_Z21__device_stub__matmulPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6matmulPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPdS_S_iii, .Lfunc_end0-_Z21__device_stub__matmulPdS_S_iii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__matmul_pitchPdS_S_iimi # -- Begin function _Z27__device_stub__matmul_pitchPdS_S_iimi
.p2align 4, 0x90
.type _Z27__device_stub__matmul_pitchPdS_S_iimi,@function
_Z27__device_stub__matmul_pitchPdS_S_iimi: # @_Z27__device_stub__matmul_pitchPdS_S_iimi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12matmul_pitchPdS_S_iimi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z27__device_stub__matmul_pitchPdS_S_iimi, .Lfunc_end1-_Z27__device_stub__matmul_pitchPdS_S_iimi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10run_matmuliiii
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_1:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl _Z10run_matmuliiii
.p2align 4, 0x90
.type _Z10run_matmuliiii,@function
_Z10run_matmuliiii: # @_Z10run_matmuliiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r13d
movl %edx, %r12d
movl %esi, %r15d
movl %edi, %r14d
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movq %r14, (%rsp) # 8-byte Spill
addl %r13d, %r14d
movq %r15, 72(%rsp) # 8-byte Spill
addl %r13d, %r15d
movq %r12, 80(%rsp) # 8-byte Spill
movq %r13, 64(%rsp) # 8-byte Spill
leal (%r12,%r13), %ebp
movl %r14d, %eax
imull %r15d, %eax
movslq %eax, %r12
shlq $3, %r12
movq %r12, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movl %r15d, %eax
imull %ebp, %eax
movslq %eax, %r13
shlq $3, %r13
movq %r13, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movl %r14d, %eax
imull %ebp, %eax
movslq %eax, %rdi
shlq $3, %rdi
movq %rdi, 8(%rsp) # 8-byte Spill
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movl %r15d, %eax
testl %r14d, %r14d
jle .LBB2_6
# %bb.1: # %.preheader110.lr.ph
movl %r14d, %ecx
xorl %edx, %edx
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addl %r14d, %ebx
cmpq %rcx, %rdx
je .LBB2_6
.LBB2_2: # %.preheader110
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %r15d, %r15d
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %ebx, %esi
movq 16(%rsp), %rdi # 8-byte Reload
leaq (%rdi,%rsi,8), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%rdi), %r8d
xorps %xmm0, %xmm0
cvtsi2sd %r8d, %xmm0
movsd %xmm0, (%rsi,%rdi,8)
incq %rdi
cmpq %rdi, %rax
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %.preheader109
testl %r15d, %r15d
movq 96(%rsp), %r14 # 8-byte Reload
jle .LBB2_12
# %bb.7: # %.preheader.lr.ph
movl %ebp, %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_11: # %._crit_edge115
# in Loop: Header=BB2_8 Depth=1
incq %rsi
addl %r15d, %edx
cmpq %rax, %rsi
je .LBB2_12
.LBB2_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_10 Depth 2
testl %ebp, %ebp
jle .LBB2_11
# %bb.9: # %.lr.ph114
# in Loop: Header=BB2_8 Depth=1
movl %edx, %edi
leaq (%r14,%rdi,8), %rdi
movl %esi, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB2_10: # Parent Loop BB2_8 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %r8d, %xmm0
movsd %xmm0, (%rdi,%r9,8)
incq %r9
decl %r8d
cmpq %r9, %rcx
jne .LBB2_10
jmp .LBB2_11
.LBB2_12: # %._crit_edge117
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq 8(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 80(%rsp), %r13 # 8-byte Reload
leal 31(%r13), %eax
testl %r13d, %r13d
cmovnsl %r13d, %eax
sarl $5, %eax
movq (%rsp), %rcx # 8-byte Reload
leal 31(%rcx), %r12d
testl %ecx, %ecx
cmovnsl %ecx, %r12d
sarl $5, %r12d
shlq $32, %r12
orq %rax, %r12
callq hipDeviceSynchronize
leaq 232(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r15d, 60(%rsp)
movl %ebp, 56(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 60(%rsp), %rax
movq %rax, 200(%rsp)
leaq 56(%rsp), %rax
movq %rax, 208(%rsp)
leaq 52(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z6matmulPdS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipDeviceSynchronize
leaq 176(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rsi
movq 88(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_39
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_17
# %bb.16:
movzbl 67(%r15), %eax
jmp .LBB2_18
.LBB2_17:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_39
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%r15)
je .LBB2_21
# %bb.20:
movzbl 67(%r15), %eax
jmp .LBB2_22
.LBB2_21:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 176(%rsp), %rax
subq 232(%rsp), %rax
movabsq $4294967296000000, %rcx # imm = 0xF424000000000
imulq %rax, %rcx
shrq $32, %rcx
movl 184(%rsp), %eax
subl 240(%rsp), %eax
addl %eax, %ecx
cvtsi2sd %ecx, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_39
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i88
cmpb $0, 56(%r15)
je .LBB2_25
# %bb.24:
movzbl 67(%r15), %ecx
jmp .LBB2_26
.LBB2_25:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit91
movq (%rsp), %rbx # 8-byte Reload
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
cvtsi2sdl 72(%rsp), %xmm0 # 4-byte Folded Reload
cvtsi2sd %ebx, %xmm1
addsd %xmm0, %xmm0
mulsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
mulsd %xmm1, %xmm0
mulsd .LCPI2_1(%rip), %xmm0
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_39
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i93
cmpb $0, 56(%r15)
je .LBB2_29
# %bb.28:
movzbl 67(%r15), %ecx
jmp .LBB2_30
.LBB2_29:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit96
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 1160(%r12), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_39
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i98
cmpb $0, 56(%r15)
je .LBB2_33
# %bb.32:
movzbl 67(%r15), %ecx
jmp .LBB2_34
.LBB2_33:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit101
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB2_39
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i103
cmpb $0, 56(%r15)
je .LBB2_37
# %bb.36:
movzbl 67(%r15), %eax
jmp .LBB2_38
.LBB2_37:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit106
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r12, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_39:
.cfi_def_cfa_offset 304
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z10run_matmuliiii, .Lfunc_end2-_Z10run_matmuliiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16run_matmul_pitchiiii
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_1:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl _Z16run_matmul_pitchiiii
.p2align 4, 0x90
.type _Z16run_matmul_pitchiiii,@function
_Z16run_matmul_pitchiiii: # @_Z16run_matmul_pitchiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r13d
movl %edx, %r15d
movl %esi, %r14d
movl %edi, %ebx
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movq %rbx, 40(%rsp) # 8-byte Spill
addl %r13d, %ebx
movq %r14, 112(%rsp) # 8-byte Spill
addl %r13d, %r14d
movq %r15, 128(%rsp) # 8-byte Spill
movq %r13, 104(%rsp) # 8-byte Spill
addl %r13d, %r15d
movl %ebx, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %r13
movl %r14d, %eax
imull %r15d, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, %rbp
movl %ebx, %eax
imull %r15d, %eax
movslq %eax, %rdi
shlq $3, %rdi
callq malloc
movq %rax, 136(%rsp) # 8-byte Spill
movl %r14d, %eax
testl %ebx, %ebx
jle .LBB3_6
# %bb.1: # %.preheader114.lr.ph
movl %ebx, %ecx
xorl %edx, %edx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rdx
addl %ebx, %r12d
cmpq %rcx, %rdx
je .LBB3_6
.LBB3_2: # %.preheader114
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %r14d, %r14d
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r12d, %esi
leaq (,%rsi,8), %rsi
addq %r13, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rdx,%rdi), %r8d
xorps %xmm0, %xmm0
cvtsi2sd %r8d, %xmm0
movsd %xmm0, (%rsi,%rdi,8)
incq %rdi
cmpq %rdi, %rax
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %.preheader113
movq %r13, 96(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB3_12
# %bb.7: # %.preheader.lr.ph
movl %r15d, %ecx
xorl %edx, %edx
xorl %esi, %esi
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_11: # %._crit_edge119
# in Loop: Header=BB3_8 Depth=1
incq %rsi
addl %r14d, %edx
cmpq %rax, %rsi
je .LBB3_12
.LBB3_8: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
testl %r15d, %r15d
jle .LBB3_11
# %bb.9: # %.lr.ph118
# in Loop: Header=BB3_8 Depth=1
movl %edx, %edi
leaq (,%rdi,8), %rdi
addq %rbp, %rdi
movl %esi, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_8 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2sd %r8d, %xmm0
movsd %xmm0, (%rdi,%r9,8)
incq %r9
decl %r8d
cmpq %r9, %rcx
jne .LBB3_10
jmp .LBB3_11
.LBB3_12: # %._crit_edge121
movq %rbp, 88(%rsp) # 8-byte Spill
movslq %r14d, %rbp
leaq (,%rbp,8), %rdx
movq %rdx, 24(%rsp) # 8-byte Spill
movslq %ebx, %r12
leaq 64(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r12, %rcx
callq hipMallocPitch
movslq %r15d, %rbx
leaq (,%rbx,8), %r13
leaq 56(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq hipMallocPitch
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %r13, %rdx
movq %r12, %rcx
callq hipMallocPitch
movq 64(%rsp), %rdi
movq 32(%rsp), %rsi
movl $1, (%rsp)
movq 96(%rsp), %rdx # 8-byte Reload
movq 24(%rsp), %rcx # 8-byte Reload
movq %rbp, %r8
movq %r12, 24(%rsp) # 8-byte Spill
movq %r12, %r9
movq %rbx, %r12
callq hipMemcpy2D
movq 56(%rsp), %rdi
movq 32(%rsp), %rsi
movl $1, (%rsp)
movq 88(%rsp), %rdx # 8-byte Reload
movq %r13, 120(%rsp) # 8-byte Spill
movq %r13, %rcx
movq %rbx, %r8
movq %rbp, %r9
callq hipMemcpy2D
movq 128(%rsp), %rbp # 8-byte Reload
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovnsl %ebp, %eax
sarl $5, %eax
movq 40(%rsp), %rcx # 8-byte Reload
leal 31(%rcx), %ebx
testl %ecx, %ecx
cmovnsl %ecx, %ebx
sarl $5, %ebx
shlq $32, %rbx
orq %rax, %rbx
callq hipDeviceSynchronize
leaq 280(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 64(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 32(%rsp), %rsi
shrq $3, %rsi
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movl %r14d, 84(%rsp)
movl %r15d, 80(%rsp)
movq %rsi, 192(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movl %eax, 76(%rsp)
leaq 216(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 84(%rsp), %rax
movq %rax, 248(%rsp)
leaq 80(%rsp), %rax
movq %rax, 256(%rsp)
leaq 192(%rsp), %rax
movq %rax, 264(%rsp)
leaq 76(%rsp), %rax
movq %rax, 272(%rsp)
leaq 176(%rsp), %rdi
leaq 160(%rsp), %rsi
leaq 152(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rax
movq 144(%rsp), %rdi
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
movq 160(%rsp), %rcx
movl 168(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 224(%rsp), %r9
movl $_Z12matmul_pitchPdS_S_iimi, %edi
callq hipLaunchKernel
.LBB3_14:
callq hipDeviceSynchronize
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rdx
movq 32(%rsp), %rcx
movl $2, (%rsp)
movq 136(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
movq 120(%rsp), %rsi # 8-byte Reload
movq %r12, %r8
movq 24(%rsp), %r9 # 8-byte Reload
callq hipMemcpy2D
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_39
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
movq 96(%rsp), %r13 # 8-byte Reload
movq 88(%rsp), %r12 # 8-byte Reload
je .LBB3_17
# %bb.16:
movzbl 67(%r15), %eax
jmp .LBB3_18
.LBB3_17:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $46, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_39
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
cmpb $0, 56(%r15)
je .LBB3_21
# %bb.20:
movzbl 67(%r15), %eax
jmp .LBB3_22
.LBB3_21:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit90
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 224(%rsp), %rax
subq 280(%rsp), %rax
movabsq $4294967296000000, %rcx # imm = 0xF424000000000
imulq %rax, %rcx
shrq $32, %rcx
movl 232(%rsp), %eax
subl 288(%rsp), %eax
addl %eax, %ecx
cvtsi2sd %ecx, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_39
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i92
cmpb $0, 56(%r15)
je .LBB3_25
# %bb.24:
movzbl 67(%r15), %ecx
jmp .LBB3_26
.LBB3_25:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit95
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorps %xmm0, %xmm0
cvtsi2sdl 112(%rsp), %xmm0 # 4-byte Folded Reload
cvtsi2sdl 40(%rsp), %xmm1 # 4-byte Folded Reload
addsd %xmm0, %xmm0
mulsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd %xmm1, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_39
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i97
cmpb $0, 56(%r15)
je .LBB3_29
# %bb.28:
movzbl 67(%r15), %ecx
jmp .LBB3_30
.LBB3_29:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit100
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 1160(%r14), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB3_39
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i102
cmpb $0, 56(%r15)
je .LBB3_33
# %bb.32:
movzbl 67(%r15), %ecx
jmp .LBB3_34
.LBB3_33:
movq %r15, %rdi
movq %rax, %rbx
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbx, %rax
.LBB3_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit105
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_39
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i107
cmpb $0, 56(%r15)
je .LBB3_37
# %bb.36:
movzbl 67(%r15), %eax
jmp .LBB3_38
.LBB3_37:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit110
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r13, %rdi
callq free
movq %r12, %rdi
callq free
movq %r14, %rdi
callq free
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_39:
.cfi_def_cfa_offset 352
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size _Z16run_matmul_pitchiiii, .Lfunc_end3-_Z16run_matmul_pitchiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $2560, %edi # imm = 0xA00
movl $2560, %esi # imm = 0xA00
movl $2560, %edx # imm = 0xA00
xorl %ecx, %ecx
callq _Z10run_matmuliiii
movl $2560, %edi # imm = 0xA00
movl $2560, %esi # imm = 0xA00
movl $2560, %edx # imm = 0xA00
xorl %ecx, %ecx
callq _Z16run_matmul_pitchiiii
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12matmul_pitchPdS_S_iimi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPdS_S_iii,@object # @_Z6matmulPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z6matmulPdS_S_iii
.p2align 3, 0x0
_Z6matmulPdS_S_iii:
.quad _Z21__device_stub__matmulPdS_S_iii
.size _Z6matmulPdS_S_iii, 8
.type _Z12matmul_pitchPdS_S_iimi,@object # @_Z12matmul_pitchPdS_S_iimi
.globl _Z12matmul_pitchPdS_S_iimi
.p2align 3, 0x0
_Z12matmul_pitchPdS_S_iimi:
.quad _Z27__device_stub__matmul_pitchPdS_S_iimi
.size _Z12matmul_pitchPdS_S_iimi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-----------------------------------------------"
.size .L.str, 48
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "normal device memory alocation using cudaMalloc:"
.size .L.str.1, 49
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Comp time = "
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GFlops = "
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "value check = "
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "device memory alocation using cudaMallocPitch:"
.size .L.str.5, 47
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmulPdS_S_iii"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12matmul_pitchPdS_S_iimi"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPdS_S_iii
.addrsig_sym _Z27__device_stub__matmul_pitchPdS_S_iimi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPdS_S_iii
.addrsig_sym _Z12matmul_pitchPdS_S_iimi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime_api.h>
#include <errno.h>
#include <unistd.h>
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o cuda_linear_regression CUDA_linear_regression.c -lm
*
* To run:
* ./cuda_linear_regression
*
* Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/
typedef struct point_t {
double x;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000; //device varialble
//date set
point_t data[] = {{84.00,158.34},{65.52,110.67},{85.91,134.11},{77.48,136.09},
{73.17,136.16},{67.40,109.20},{75.49,126.90},{77.85,114.67},
{79.25,148.06},{78.31,121.73},{68.11,123.17},{65.98,119.55},
{76.17,132.26},{ 2.64,38.33},{96.38,166.85},{86.14,132.68},
{61.54,96.82},{37.72,98.07},{37.70,80.81},{32.28,100.04},
{ 3.66,23.94},{ 7.46,52.84},{36.23,95.31},{22.34,69.48},
{71.96,115.66},{86.47,138.88},{92.92,145.82},{38.48,82.46},
{44.20,93.62},{21.05,49.35},{11.86,34.11},{46.37,98.83},
{91.10,151.02},{49.67,99.71},{93.18,154.70},{29.36,74.06},
{98.23,161.21},{11.48,37.38},{76.14,134.55},{12.82,42.87},
{41.65,73.14},{90.87,150.57},{20.07,60.27},{16.50,52.54},
{13.34,34.29},{84.40,135.44},{11.52,59.82},{29.37,47.39},
{98.77,186.38},{37.76,90.20},{70.76,120.68},{76.53,124.45},
{53.19,83.32},{43.38,84.37},{24.17,54.39},{34.73,75.47},
{48.74,88.61},{90.41,137.16},{71.67,116.42},{33.52,73.32},
{89.07,151.04},{99.62,157.57},{ 6.06,23.75},{ 9.88,41.48},
{37.40,88.12},{ 4.90,28.21},{59.65,93.58},{89.26,144.30},
{80.12,125.86},{55.68,109.87},{ 6.63,29.82},{42.01,82.57},
{28.50,58.62},{96.34,151.98},{58.48,86.73},{ 9.21,49.93},
{45.26,91.89},{61.45,129.42},{64.16,122.85},{50.16,110.61},
{69.15,117.41},{ 5.71,48.77},{94.65,155.24},{53.12,94.42},
{16.94,63.60},{14.17,54.90},{51.54,115.01},{39.22,79.28},
{39.61,78.46},{54.97,119.51},{11.59,36.63},{89.21,153.74},
{72.09,134.94},{65.94,108.67},{25.24,83.47},{46.42,97.83},
{92.01,150.73},{37.99,76.21},{89.04,142.25},{64.33,112.96},
{53.37,106.10},{95.53,165.26},{38.36,91.04},{93.05,143.28},
{28.64,68.65},{44.62,95.02},{45.09,77.05},{19.75,43.50},
{20.91,56.67},{54.75,98.18},{58.10,104.92},{76.92,112.29},
{95.54,134.70},{18.37,60.01},{34.41,64.02},{73.88,115.06},
{ 3.12,29.78},{87.83,139.28},{51.24,100.70},{59.09,93.30},
{17.73,37.79},{53.24,125.19},{55.98,95.18},{93.57,161.31},
{94.19,156.54},{17.23,61.67},{84.72,126.89},{94.21,173.37},
{14.36,50.76},{86.73,164.40},{11.46,50.63},{82.37,140.06},
{91.47,149.02},{78.43,139.81},{69.13,110.30},{55.18,98.69},
{77.04,133.84},{89.54,152.12},{41.97,92.78},{33.30,54.63},
{67.24,120.88},{99.28,167.60},{15.72,44.70},{ 1.99,30.69},
{22.75,63.59},{ 7.67,35.46},{33.63,78.13},{ 4.18,34.79},
{53.87,85.32},{50.78,116.87},{59.50,110.24},{86.30,128.04},
{ 1.58,32.38},{60.74,115.04},{41.74,80.26},{47.25,87.04},
{ 6.48,48.05},{ 5.38,40.66},{44.37,96.63},{52.09,106.49},
{ 2.53,20.15},{29.92,75.21},{64.13,113.18},{49.87,94.77},
{89.10,139.11},{64.31,122.49},{77.49,151.19},{47.76,92.00},
{35.10,84.27},{59.01,94.03},{30.72,66.91},{ 0.73,31.64},
{87.23,139.17},{93.71,143.40},{99.09,150.61},{49.24,86.30},
{70.06,123.48},{94.79,161.15},{65.53,110.62},{73.07,120.91},
{58.64,109.98},{93.06,153.11},{10.33,52.32},{53.66,99.87},
{79.93,131.72},{92.47,149.34},{81.26,134.04},{77.69,122.75},
{ 0.21,37.82},{ 5.74,33.36},{92.38,139.73},{11.65,57.39},
{75.26,145.81},{92.63,139.34},{73.34,147.14},{54.49,105.57},
{25.16,57.99},{15.96,57.13},{61.03,104.92},{49.06,91.20},
{46.50,78.47},{83.35,139.36},{75.69,107.74},{45.22,91.87},
{ 3.46,47.84},{90.17,155.25},{40.70,58.46},{42.82,97.35},
{49.34,98.41},{89.89,141.81},{42.76,84.78},{34.67,77.38},
{58.32,101.54},{14.00,39.47},{85.53,144.41},{ 0.20,38.28},
{86.50,126.17},{35.04,66.41},{48.45,101.50},{83.83,137.62},
{67.53,105.84},{ 8.18,36.42},{53.77,95.88},{73.79,129.29},
{53.20,93.60},{65.37,111.30},{97.78,167.73},{22.98,55.09},
{81.18,141.58},{37.60,92.48},{84.76,143.11},{22.76,73.08},
{82.74,116.98},{ 6.27,53.39},{34.87,71.66},{75.19,131.80},
{92.31,152.15},{86.41,132.70},{97.91,134.42},{23.91,64.29},
{39.02,83.92},{55.23,119.47},{22.70,69.44},{68.05,116.09},
{60.05,110.20},{43.42,94.91},{ 5.76,40.19},{ 0.85,27.11},
{25.87,54.31},{96.94,146.88},{26.27,72.95},{10.94,45.38},
{64.67,120.45},{11.09,66.59},{26.46,72.91},{18.58,52.41},
{80.97,134.00},{ 0.34,27.83},{33.13,69.96},{49.90,91.22},
{18.80,64.32},{35.91,80.24},{28.45,49.05},{64.01,119.04},
{ 4.57,17.02},{93.16,157.23},{78.53,132.43},{50.60,97.10},
{24.82,50.38},{ 4.84,48.13},{75.03,125.77},{75.72,138.80},
{52.51,114.45},{30.78,72.74},{18.85,45.55},{10.56,49.41},
{ 6.21,50.39},{ 8.24,48.12},{98.61,155.04},{65.17,127.86},
{73.79,127.93},{ 4.28,29.56},{96.11,151.45},{65.64,115.43},
{19.96,40.75},{54.15,107.88},{73.22,121.27},{31.92,62.21},
{92.49,137.93},{46.31,96.16},{24.55,67.97},{49.05,91.91},
{55.62,111.54},{81.51,151.15},{30.35,70.93},{88.44,146.56},
{48.89,97.29},{10.97,35.94},{14.82,56.32},{69.65,117.12},
{30.65,85.34},{92.16,146.37},{16.71,71.71},{66.67,131.21},
{37.11,74.31},{59.68,110.52},{77.14,127.68},{39.95,79.67},
{22.52,91.67},{10.03,45.65},{31.57,75.72},{65.36,128.53},
{83.86,140.56},{41.54,85.30},{ 6.38,30.93},{69.65,122.81},
{ 7.27,44.05},{94.53,149.93},{42.97,95.82},{31.21,65.74},
{56.21,100.24},{ 3.36,35.37},{38.60,82.21},{ 5.89,46.30},
{57.19,105.13},{24.70,62.79},{19.06,46.81},{ 0.03,40.45},
{53.27,98.31},{63.51,94.80},{60.00,117.85},{55.89,115.68},
{47.68,98.74},{ 6.75,49.35},{25.37,36.75},{ 6.02,27.97},
{32.83,70.94},{24.08,59.55},{ 1.50,41.37},{20.14,34.03},
{29.57,72.67},{67.45,129.74},{10.37,71.88},{ 4.00,28.25},
{70.58,121.73},{73.06,147.21},{ 3.18,31.23},{39.72,87.12},
{48.37,95.58},{87.89,148.28},{ 1.38,39.73},{74.67,123.62},
{23.09,85.06},{45.85,83.61},{70.08,120.59},{50.54,127.10},
{18.68,46.70},{25.34,75.71},{36.59,82.03},{74.06,136.39},
{77.69,119.75},{40.72,86.70},{ 2.10,39.85},{70.21,110.13},
{57.12,98.18},{95.81,168.67},{ 1.89,28.48},{80.47,151.77},
{58.85,110.02},{97.94,150.44},{94.39,148.61},{57.84,102.75},
{74.49,133.19},{54.75,103.82},{35.22,94.57},{75.75,136.10},
{50.83,93.11},{63.46,90.88},{43.93,98.46},{96.07,153.80},
{73.81,137.75},{42.06,85.80},{25.23,69.96},{88.47,133.44},
{36.88,84.25},{59.81,106.92},{17.34,65.65},{ 3.38,37.52},
{66.07,130.98},{83.69,133.52},{97.61,141.32},{ 5.25,37.57},
{ 3.65,26.65},{88.36,166.35},{92.12,134.00},{17.96,69.00},
{80.70,126.96},{99.18,157.12},{31.73,77.47},{43.01,99.71},
{40.38,88.63},{70.91,125.87},{80.45,153.99},{57.17,113.12},
{76.32,133.62},{73.71,134.36},{26.86,51.30},{39.58,83.32},
{74.78,129.83},{57.47,98.73},{41.74,87.85},{56.88,103.05},
{30.25,80.40},{10.57,55.26},{97.60,151.00},{93.22,149.95},
{ 0.46,23.10},{58.64,106.75},{99.59,158.87},{32.30,74.35},
{38.16,80.61},{42.23,96.81},{67.36,118.92},{47.78,90.29},
{53.16,112.75},{27.65,49.70},{30.00,56.75},{48.80,117.42},
{12.52,47.70},{29.98,63.12},{43.86,89.89},{99.69,171.58},
{40.14,79.46},{54.06,121.93},{91.20,147.36},{11.64,43.11},
{36.83,96.61},{15.05,42.61},{19.69,71.98},{31.61,75.89},
{25.20,90.34},{85.54,120.51},{52.87,88.38},{72.88,120.51},
{74.91,115.52},{25.60,48.79},{79.13,131.98},{16.82,58.28},
{17.84,48.08},{52.58,108.19},{50.31,94.38},{81.58,124.00},
{83.06,146.52},{70.99,129.95},{33.61,69.02},{52.77,113.22},
{22.94,60.25},{16.16,41.73},{32.61,74.22},{32.95,59.85},
{76.76,135.04},{79.95,136.48},{25.45,60.50},{81.66,142.89},
{45.57,98.11},{98.68,157.32},{33.40,92.64},{56.66,105.69},
{34.55,67.90},{65.58,116.61},{79.54,132.70},{13.55,49.96},
{49.60,92.00},{75.55,143.09},{94.16,145.02},{68.01,123.94},
{11.48,42.98},{ 7.76,56.04},{56.28,118.42},{ 6.09,57.31},
{98.90,179.15},{26.95,84.92},{ 8.52,25.64},{63.05,126.16},
{39.72,94.83},{94.54,159.75},{67.46,123.28},{68.85,138.76},
{46.96,83.67},{67.54,101.95},{23.17,61.79},{29.49,76.26},
{58.17,111.80},{53.25,97.62},{37.89,74.59},{ 7.60,29.16},
{60.72,103.03},{30.80,78.51},{14.13,34.68},{38.44,79.92},
{59.12,111.86},{17.24,56.59},{89.12,133.28},{19.85,60.88},
{90.45,151.93},{82.77,132.73},{34.02,76.70},{54.54,105.19},
{65.08,123.75},{69.80,115.13},{95.30,156.69},{17.66,70.39},
{25.18,82.85},{ 6.02,43.58},{12.61,40.23},{34.32,81.89},
{67.40,100.75},{ 7.81,34.52},{ 7.03,36.08},{22.67,59.09},
{93.01,150.36},{87.02,164.77},{32.20,74.13},{54.87,103.10},
{58.37,135.91},{62.51,96.38},{45.32,89.16},{39.40,80.36},
{12.45,68.04},{61.43,131.19},{59.25,103.13},{26.71,74.65},
{61.25,110.85},{53.78,97.09},{57.75,114.27},{29.38,59.90},
{18.36,71.14},{69.96,118.11},{14.56,39.27},{19.89,40.98},
{68.55,130.17},{ 7.50,47.37},{35.98,101.38},{17.22,43.45},
{76.31,127.73},{ 3.16,47.85},{93.16,152.57},{36.04,77.38},
{60.95,118.72},{ 2.53,27.86},{78.06,137.18},{34.06,71.82},
{83.47,149.39},{43.94,84.91},{82.45,154.13},{70.65,125.11},
{25.67,64.86},{ 3.34,31.20},{15.95,58.76},{82.08,133.76},
{94.85,157.96},{20.05,54.70},{ 3.44,40.93},{40.08,77.92},
{43.31,79.23},{66.15,117.30},{84.56,137.10},{27.33,78.17},
{16.18,46.85},{54.56,94.42},{32.63,78.15},{54.25,118.13},
{90.63,165.79},{57.19,98.26},{46.83,82.83},{ 4.02,24.60},
{66.12,115.96},{71.95,97.79},{52.13,103.65},{31.29,75.26},
{55.91,100.66},{73.56,127.91},{74.57,133.72},{14.54,55.51},
{35.91,76.04},{71.79,112.40},{ 3.52,32.63},{99.48,162.94},
{ 6.95,26.59},{75.82,121.54},{10.08,46.44},{45.52,91.13},
{ 1.68,30.79},{89.95,118.34},{34.84,77.63},{82.45,150.87},
{42.78,63.15},{94.05,152.35},{61.19,104.44},{54.42,104.51},
{ 9.39,44.61},{ 6.90,39.55},{75.00,125.36},{71.30,129.59},
{58.25,97.29},{90.61,147.99},{31.75,67.79},{85.80,137.70},
{79.15,139.56},{44.24,79.90},{81.04,137.23},{65.21,106.73},
{11.01,57.70},{33.41,84.03},{ 5.62,19.26},{77.21,143.88},
{99.40,162.13},{92.80,146.34},{77.65,128.09},{86.21,138.32},
{92.32,158.09},{79.31,150.60},{45.31,91.34},{13.30,45.91},
{91.10,145.10},{94.55,148.44},{90.81,162.01},{98.98,170.98},
{ 5.68,57.45},{10.28,46.14},{13.53,44.62},{52.10,93.46},
{98.73,164.39},{65.57,117.52},{63.85,112.29},{ 5.96,48.16},
{ 8.27,25.85},{14.11,51.72},{87.32,139.79},{ 7.19,36.04},
{36.11,87.96},{79.40,134.60},{79.73,146.13},{69.33,120.83},
{24.96,70.50},{12.89,34.58},{69.45,98.30},{86.02,147.84},
{12.77,47.45},{22.82,76.20},{88.41,150.31},{30.70,72.59},
{43.43,90.49},{25.14,51.00},{51.61,94.30},{61.68,132.43},
{19.55,53.26},{61.03,108.01},{24.35,65.91},{34.89,88.15},
{64.10,104.38},{67.04,133.73},{ 8.14,37.24},{11.35,43.91},
{11.79,46.13},{ 3.91,29.22},{37.60,97.66},{70.40,123.36},
{58.04,122.64},{49.69,93.67},{92.56,162.20},{96.15,157.63},
{23.97,73.66},{84.56,145.39},{61.80,94.78},{55.92,133.05},
{30.56,73.72},{ 4.70,31.81},{64.33,113.26},{50.51,95.26},
{47.10,94.95},{10.32,38.87},{67.75,120.60},{23.91,75.57},
{21.39,61.62},{96.89,147.19},{67.14,123.16},{16.08,61.14},
{93.28,139.31},{50.74,98.09},{37.71,86.95},{78.59,137.61},
{63.89,106.58},{31.69,82.45},{58.08,112.38},{43.16,94.01},
{11.39,25.42},{66.16,112.32},{96.03,152.01},{42.55,83.11},
{32.32,65.15},{23.02,47.10},{29.21,61.35},{16.54,58.56},
{48.28,100.58},{18.08,46.23},{25.86,59.73},{78.52,127.28},
{ 9.95,50.65},{28.39,64.12},{56.10,87.61},{43.22,93.14},
{42.76,89.45},{98.29,159.63},{97.34,177.78},{ 4.27,55.23},
{47.01,105.57},{59.86,114.37},{18.95,51.11},{41.52,84.33},
{62.96,108.18},{27.79,55.86},{16.39,65.66},{66.18,105.45},
{34.86,94.94},{28.47,69.45},{97.67,167.37},{75.86,104.33},
{25.01,74.40},{46.96,87.54},{92.52,129.85},{29.78,73.72},
{85.72,139.37},{83.89,126.76},{59.14,115.78},{46.85,97.38},
{ 6.19,34.32},{11.63,23.31},{11.63,44.46},{22.84,56.76},
{12.00,50.78},{62.84,100.45},{81.42,131.72},{90.47,143.37},
{29.93,88.90},{77.40,122.09},{93.82,145.35},{47.75,96.19},
{21.14,70.74},{97.46,148.02},{12.72,36.39},{49.97,83.79},
{97.95,162.70},{90.86,153.60},{63.85,117.19},{ 4.58,30.40},
{60.56,119.74},{53.52,110.35},{30.87,64.20},{ 6.80,49.32},
{73.95,124.06},{ 6.10,58.73},{22.38,69.13},{60.70,112.49},
{60.85,85.34},{88.28,163.12},{53.88,98.87},{11.25,27.58},
{61.39,111.48},{50.19,101.48},{47.54,105.73},{36.68,74.67},
{16.93,37.98},{63.31,104.97},{98.08,146.59},{20.30,65.51},
{66.90,115.71},{ 3.46,26.89},{75.90,129.36},{ 6.60,56.60},
{58.83,111.03},{69.25,129.30},{76.03,114.70},{62.91,118.23},
{96.98,154.55},{21.79,63.43},{82.03,146.15},{25.64,53.97},
{79.89,145.81},{39.61,84.38},{46.54,88.11},{63.57,98.17},
{78.91,134.57},{92.78,165.65},{88.14,156.37},{ 0.33,35.73},
{51.07,80.06},{37.70,69.07},{76.62,125.56},{74.47,121.16},
{47.03,88.43},{46.70,96.04},{25.41,63.87},{68.35,116.96},
{71.34,120.03},{16.20,49.28},{11.01,49.88},{95.77,162.43},
{28.71,77.99},{46.92,73.65},{62.38,104.31},{86.01,128.55},
{65.86,113.60},{57.63,121.48},{74.36,125.46},{ 1.08,39.77},
{ 8.21,41.65},{13.79,48.62},{83.45,141.43},{15.74,38.94},
{19.63,71.50},{99.25,151.24},{50.00,90.16},{81.22,122.70},
{24.58,46.44},{51.88,85.53},{55.71,84.04},{ 5.93,32.59},
{74.94,134.09},{92.76,149.10},{46.09,101.09},{36.43,94.08},
{ 8.41,38.29},{68.17,99.20},{34.42,85.90},{80.43,138.29},
{48.74,88.09},{56.61,116.21},{27.16,80.41},{96.04,143.67},
{41.60,88.71},{56.43,96.06},{99.67,159.49},{ 7.93,25.69},
{95.21,156.97},{42.55,69.14},{10.74,28.43},{51.32,97.30},
{44.89,83.67},{ 7.40,44.96},{ 1.16,42.00},{ 5.30,37.14},
{96.77,152.72},{ 5.98,40.00},{60.23,122.22},{37.87,84.62},
{42.33,78.24},{18.89,37.62},{26.30,51.55},{ 5.60,42.60},
{32.57,75.79},{94.80,149.64},{98.93,156.85},{ 8.20,41.74},
{38.60,87.55},{88.03,144.13},{28.03,53.93},{26.09,89.76},
{29.84,72.65},{85.36,132.48},{26.97,76.70},{35.26,76.30},
{25.85,70.80},{77.97,127.49},{71.01,138.54},{10.94,49.91},
{31.24,71.77},{ 7.53,44.95},{ 1.52,28.59},{19.27,43.30},
{14.91,45.06},{96.42,156.47},{66.39,126.02},{68.99,112.91},
{18.85,62.58},{32.55,100.92},{33.59,86.01},{58.03,97.94},
{35.86,75.80},{31.33,93.37},{93.26,153.90},{15.52,42.25},
{ 2.75,40.88},{14.25,56.34},{11.34,55.07},{ 1.06,29.82},
{19.47,46.71},{68.39,95.41},{39.15,67.12},{27.81,65.03},
{33.96,68.72},{29.79,83.58},{ 9.85,47.36},{49.47,115.24},
{ 1.24,29.63},{22.96,60.85},{37.50,66.51},{46.51,96.74},
{34.64,72.15},{82.11,143.60},{88.97,152.44},{91.71,145.13},
{13.42,62.70},{56.31,108.49},{26.71,74.17},{52.99,92.39},
{15.94,42.04},{ 1.25,24.40},{70.62,126.08},{88.17,143.68},
{ 7.38,48.95},{50.62,99.33},{43.91,86.82},{ 0.57,26.36},
{27.98,82.27},{38.45,69.65},{11.30,40.94},{45.25,84.73},
{23.87,68.58},{25.37,72.12},{60.34,119.79},{42.59,100.13},
{12.92,41.13},{22.43,55.83},{97.86,168.21},{15.57,53.63},
{26.44,66.90},{99.83,149.10},{83.71,118.45},{69.42,125.64},
{55.85,107.20},{58.00,110.89},{66.97,119.44},{47.25,93.49},
{49.27,106.34},{81.80,147.14},{84.71,137.74},{29.70,61.42},
{71.42,105.56},{68.87,128.05},{46.67,91.29},{65.32,132.59},
{48.76,85.75},{94.55,153.38},{21.41,42.63},{52.33,92.98},
{10.89,38.87},{21.31,52.97},{52.06,85.39},{17.92,50.67},
{73.13,126.80},{65.01,131.31},{37.48,85.60},{62.95,110.14},
{63.03,105.04},{10.10,51.57},{55.89,97.16},{16.20,67.89},
{14.11,38.98},{34.82,80.05},{43.53,87.53},{81.52,149.98},
{65.19,127.61},{13.80,43.24},{62.56,95.92},{32.09,68.79},
{24.35,52.32},{ 8.52,40.70},{83.94,140.84},{76.46,117.49},
{ 9.96,43.44},{90.95,133.38},{29.78,70.77},{15.32,39.57},
{80.51,130.61},{73.15,117.93},{10.85,52.82},{67.84,108.04},
{84.76,131.77},{37.11,74.72},{59.02,110.81},{83.26,138.42},
{44.73,104.58},{95.54,150.49},{60.96,85.42},{70.72,110.25},
{38.20,77.21},{80.19,123.35},{23.75,56.10},{36.83,91.49}
};
double residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
__device__ double d_residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
//error calc func
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].x, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
//global func
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
/*
Calculate the current index by using:
- The thread id
- The block id
- The number of threads per block
*/
int i = threadIdx.x + blockIdx.x * blockDim.x;
//sum error stored in array
error_sum_arr[i] = d_residual_error(d_data[i].x, d_data[i].y, *m, *c);
}
//time difffernce
int time_difference(struct timespec *start, struct timespec *finish,
long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
//main funcation
int main() {
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
//time start
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
cudaError_t error;
//variables for device func
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be = rms_error(bm, bc);
//allocating memory in device using CUDA malloc
error = cudaMalloc(&d_dm, (sizeof(double) * 8));
if(error){
fprintf(stderr, "cudaMalloc on d_dm returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//allocating memory in device using CUDA malloc
error = cudaMalloc(&d_dc, (sizeof(double) * 8));
if(error){
fprintf(stderr, "cudaMalloc on d_dc returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//allocating memory for d_error_sum_arr
error = cudaMalloc(&d_error_sum_arr, (sizeof(double) * 1000));
if(error){
fprintf(stderr, "cudaMalloc on d_error_sum_arr returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//allocating memory for d_data
error = cudaMalloc(&d_data, sizeof(data));
if(error){
fprintf(stderr, "cudaMalloc on d_data returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i] = bc + (oc[i] * step);
}
//copying memory host ti device
error = cudaMemcpy(d_dm, dm, (sizeof(double) * 8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_dm returned %d %s\n", error,
cudaGetErrorString(error));
}
//copying memory host to device
error = cudaMemcpy(d_dc, dc, (sizeof(double) * 8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_dc returned %d %s\n", error,
cudaGetErrorString(error));
}
//copying memory host to device
error = cudaMemcpy(d_data, data, sizeof(data), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_data returned %d %s\n", error,
cudaGetErrorString(error));
}
for(i=0;i<8;i++) {
//Host variable storing the array returned from the kernel function.
double h_error_sum_arr[1000];
//Stores the total sum of the values from the error sum array.
double error_sum_total;
//Stores the mean of the total sum of the error sums.
double error_sum_mean;
//Call the rms_error function using 100 blocks and 10 threads.
d_rms_error <<<100,10>>>(&d_dm[i], &d_dc[i], d_error_sum_arr, d_data);
cudaThreadSynchronize();
//Copy memory for d_error_sum_arr
error = cudaMemcpy(&h_error_sum_arr, d_error_sum_arr, (sizeof(double) * 1000),
cudaMemcpyDeviceToHost);
if(error){
fprintf(stderr, "cudaMemcpy to error_sum returned %d %s\n", error,
cudaGetErrorString(error));
}
//Loop through the error sum array returned from the kernel function
for(int j=0; j<n_data; j++) {
//Add each error sum to the error sum total.
error_sum_total += h_error_sum_arr[j];
}
//Calculate the mean for the error sum.
error_sum_mean = error_sum_total / n_data;
//Calculate the square root for the error sum mean.
e[i] = sqrt(error_sum_mean);
if(e[i] < best_error) {
best_error = e[i];
best_error_i = i;
}
//Reset the error sum total.
error_sum_total = 0;
}
//printf("best m,c is %lf,%lf with error %lf in direction %d\n",
//dm[best_error_i], dc[best_error_i], best_error, best_error_i);
if(best_error < be) {
be = best_error;
bm = dm[best_error_i];
bc = dc[best_error_i];
} else {
minimum_found = 1;
}
}
//clearing memory
error = cudaFree(d_dm);
if(error){
fprintf(stderr, "cudaFree on d_dm returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaFree(d_dc);
if(error){
fprintf(stderr, "cudaFree on d_dc returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaFree(d_data);
if(error){
fprintf(stderr, "cudaFree on d_data returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
error = cudaFree(d_error_sum_arr);
if(error){
fprintf(stderr, "cudaFree on d_error_sum_arr returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//freee memory complete
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
//geting time after printing m c with error
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime_api.h>
#include <errno.h>
#include <unistd.h>
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o cuda_linear_regression CUDA_linear_regression.c -lm
*
* To run:
* ./cuda_linear_regression
*
* Dr Kevan Buckley, University of Wolverhampton, 2018
*****************************************************************************/
typedef struct point_t {
double x;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000; //device varialble
//date set
point_t data[] = {{84.00,158.34},{65.52,110.67},{85.91,134.11},{77.48,136.09},
{73.17,136.16},{67.40,109.20},{75.49,126.90},{77.85,114.67},
{79.25,148.06},{78.31,121.73},{68.11,123.17},{65.98,119.55},
{76.17,132.26},{ 2.64,38.33},{96.38,166.85},{86.14,132.68},
{61.54,96.82},{37.72,98.07},{37.70,80.81},{32.28,100.04},
{ 3.66,23.94},{ 7.46,52.84},{36.23,95.31},{22.34,69.48},
{71.96,115.66},{86.47,138.88},{92.92,145.82},{38.48,82.46},
{44.20,93.62},{21.05,49.35},{11.86,34.11},{46.37,98.83},
{91.10,151.02},{49.67,99.71},{93.18,154.70},{29.36,74.06},
{98.23,161.21},{11.48,37.38},{76.14,134.55},{12.82,42.87},
{41.65,73.14},{90.87,150.57},{20.07,60.27},{16.50,52.54},
{13.34,34.29},{84.40,135.44},{11.52,59.82},{29.37,47.39},
{98.77,186.38},{37.76,90.20},{70.76,120.68},{76.53,124.45},
{53.19,83.32},{43.38,84.37},{24.17,54.39},{34.73,75.47},
{48.74,88.61},{90.41,137.16},{71.67,116.42},{33.52,73.32},
{89.07,151.04},{99.62,157.57},{ 6.06,23.75},{ 9.88,41.48},
{37.40,88.12},{ 4.90,28.21},{59.65,93.58},{89.26,144.30},
{80.12,125.86},{55.68,109.87},{ 6.63,29.82},{42.01,82.57},
{28.50,58.62},{96.34,151.98},{58.48,86.73},{ 9.21,49.93},
{45.26,91.89},{61.45,129.42},{64.16,122.85},{50.16,110.61},
{69.15,117.41},{ 5.71,48.77},{94.65,155.24},{53.12,94.42},
{16.94,63.60},{14.17,54.90},{51.54,115.01},{39.22,79.28},
{39.61,78.46},{54.97,119.51},{11.59,36.63},{89.21,153.74},
{72.09,134.94},{65.94,108.67},{25.24,83.47},{46.42,97.83},
{92.01,150.73},{37.99,76.21},{89.04,142.25},{64.33,112.96},
{53.37,106.10},{95.53,165.26},{38.36,91.04},{93.05,143.28},
{28.64,68.65},{44.62,95.02},{45.09,77.05},{19.75,43.50},
{20.91,56.67},{54.75,98.18},{58.10,104.92},{76.92,112.29},
{95.54,134.70},{18.37,60.01},{34.41,64.02},{73.88,115.06},
{ 3.12,29.78},{87.83,139.28},{51.24,100.70},{59.09,93.30},
{17.73,37.79},{53.24,125.19},{55.98,95.18},{93.57,161.31},
{94.19,156.54},{17.23,61.67},{84.72,126.89},{94.21,173.37},
{14.36,50.76},{86.73,164.40},{11.46,50.63},{82.37,140.06},
{91.47,149.02},{78.43,139.81},{69.13,110.30},{55.18,98.69},
{77.04,133.84},{89.54,152.12},{41.97,92.78},{33.30,54.63},
{67.24,120.88},{99.28,167.60},{15.72,44.70},{ 1.99,30.69},
{22.75,63.59},{ 7.67,35.46},{33.63,78.13},{ 4.18,34.79},
{53.87,85.32},{50.78,116.87},{59.50,110.24},{86.30,128.04},
{ 1.58,32.38},{60.74,115.04},{41.74,80.26},{47.25,87.04},
{ 6.48,48.05},{ 5.38,40.66},{44.37,96.63},{52.09,106.49},
{ 2.53,20.15},{29.92,75.21},{64.13,113.18},{49.87,94.77},
{89.10,139.11},{64.31,122.49},{77.49,151.19},{47.76,92.00},
{35.10,84.27},{59.01,94.03},{30.72,66.91},{ 0.73,31.64},
{87.23,139.17},{93.71,143.40},{99.09,150.61},{49.24,86.30},
{70.06,123.48},{94.79,161.15},{65.53,110.62},{73.07,120.91},
{58.64,109.98},{93.06,153.11},{10.33,52.32},{53.66,99.87},
{79.93,131.72},{92.47,149.34},{81.26,134.04},{77.69,122.75},
{ 0.21,37.82},{ 5.74,33.36},{92.38,139.73},{11.65,57.39},
{75.26,145.81},{92.63,139.34},{73.34,147.14},{54.49,105.57},
{25.16,57.99},{15.96,57.13},{61.03,104.92},{49.06,91.20},
{46.50,78.47},{83.35,139.36},{75.69,107.74},{45.22,91.87},
{ 3.46,47.84},{90.17,155.25},{40.70,58.46},{42.82,97.35},
{49.34,98.41},{89.89,141.81},{42.76,84.78},{34.67,77.38},
{58.32,101.54},{14.00,39.47},{85.53,144.41},{ 0.20,38.28},
{86.50,126.17},{35.04,66.41},{48.45,101.50},{83.83,137.62},
{67.53,105.84},{ 8.18,36.42},{53.77,95.88},{73.79,129.29},
{53.20,93.60},{65.37,111.30},{97.78,167.73},{22.98,55.09},
{81.18,141.58},{37.60,92.48},{84.76,143.11},{22.76,73.08},
{82.74,116.98},{ 6.27,53.39},{34.87,71.66},{75.19,131.80},
{92.31,152.15},{86.41,132.70},{97.91,134.42},{23.91,64.29},
{39.02,83.92},{55.23,119.47},{22.70,69.44},{68.05,116.09},
{60.05,110.20},{43.42,94.91},{ 5.76,40.19},{ 0.85,27.11},
{25.87,54.31},{96.94,146.88},{26.27,72.95},{10.94,45.38},
{64.67,120.45},{11.09,66.59},{26.46,72.91},{18.58,52.41},
{80.97,134.00},{ 0.34,27.83},{33.13,69.96},{49.90,91.22},
{18.80,64.32},{35.91,80.24},{28.45,49.05},{64.01,119.04},
{ 4.57,17.02},{93.16,157.23},{78.53,132.43},{50.60,97.10},
{24.82,50.38},{ 4.84,48.13},{75.03,125.77},{75.72,138.80},
{52.51,114.45},{30.78,72.74},{18.85,45.55},{10.56,49.41},
{ 6.21,50.39},{ 8.24,48.12},{98.61,155.04},{65.17,127.86},
{73.79,127.93},{ 4.28,29.56},{96.11,151.45},{65.64,115.43},
{19.96,40.75},{54.15,107.88},{73.22,121.27},{31.92,62.21},
{92.49,137.93},{46.31,96.16},{24.55,67.97},{49.05,91.91},
{55.62,111.54},{81.51,151.15},{30.35,70.93},{88.44,146.56},
{48.89,97.29},{10.97,35.94},{14.82,56.32},{69.65,117.12},
{30.65,85.34},{92.16,146.37},{16.71,71.71},{66.67,131.21},
{37.11,74.31},{59.68,110.52},{77.14,127.68},{39.95,79.67},
{22.52,91.67},{10.03,45.65},{31.57,75.72},{65.36,128.53},
{83.86,140.56},{41.54,85.30},{ 6.38,30.93},{69.65,122.81},
{ 7.27,44.05},{94.53,149.93},{42.97,95.82},{31.21,65.74},
{56.21,100.24},{ 3.36,35.37},{38.60,82.21},{ 5.89,46.30},
{57.19,105.13},{24.70,62.79},{19.06,46.81},{ 0.03,40.45},
{53.27,98.31},{63.51,94.80},{60.00,117.85},{55.89,115.68},
{47.68,98.74},{ 6.75,49.35},{25.37,36.75},{ 6.02,27.97},
{32.83,70.94},{24.08,59.55},{ 1.50,41.37},{20.14,34.03},
{29.57,72.67},{67.45,129.74},{10.37,71.88},{ 4.00,28.25},
{70.58,121.73},{73.06,147.21},{ 3.18,31.23},{39.72,87.12},
{48.37,95.58},{87.89,148.28},{ 1.38,39.73},{74.67,123.62},
{23.09,85.06},{45.85,83.61},{70.08,120.59},{50.54,127.10},
{18.68,46.70},{25.34,75.71},{36.59,82.03},{74.06,136.39},
{77.69,119.75},{40.72,86.70},{ 2.10,39.85},{70.21,110.13},
{57.12,98.18},{95.81,168.67},{ 1.89,28.48},{80.47,151.77},
{58.85,110.02},{97.94,150.44},{94.39,148.61},{57.84,102.75},
{74.49,133.19},{54.75,103.82},{35.22,94.57},{75.75,136.10},
{50.83,93.11},{63.46,90.88},{43.93,98.46},{96.07,153.80},
{73.81,137.75},{42.06,85.80},{25.23,69.96},{88.47,133.44},
{36.88,84.25},{59.81,106.92},{17.34,65.65},{ 3.38,37.52},
{66.07,130.98},{83.69,133.52},{97.61,141.32},{ 5.25,37.57},
{ 3.65,26.65},{88.36,166.35},{92.12,134.00},{17.96,69.00},
{80.70,126.96},{99.18,157.12},{31.73,77.47},{43.01,99.71},
{40.38,88.63},{70.91,125.87},{80.45,153.99},{57.17,113.12},
{76.32,133.62},{73.71,134.36},{26.86,51.30},{39.58,83.32},
{74.78,129.83},{57.47,98.73},{41.74,87.85},{56.88,103.05},
{30.25,80.40},{10.57,55.26},{97.60,151.00},{93.22,149.95},
{ 0.46,23.10},{58.64,106.75},{99.59,158.87},{32.30,74.35},
{38.16,80.61},{42.23,96.81},{67.36,118.92},{47.78,90.29},
{53.16,112.75},{27.65,49.70},{30.00,56.75},{48.80,117.42},
{12.52,47.70},{29.98,63.12},{43.86,89.89},{99.69,171.58},
{40.14,79.46},{54.06,121.93},{91.20,147.36},{11.64,43.11},
{36.83,96.61},{15.05,42.61},{19.69,71.98},{31.61,75.89},
{25.20,90.34},{85.54,120.51},{52.87,88.38},{72.88,120.51},
{74.91,115.52},{25.60,48.79},{79.13,131.98},{16.82,58.28},
{17.84,48.08},{52.58,108.19},{50.31,94.38},{81.58,124.00},
{83.06,146.52},{70.99,129.95},{33.61,69.02},{52.77,113.22},
{22.94,60.25},{16.16,41.73},{32.61,74.22},{32.95,59.85},
{76.76,135.04},{79.95,136.48},{25.45,60.50},{81.66,142.89},
{45.57,98.11},{98.68,157.32},{33.40,92.64},{56.66,105.69},
{34.55,67.90},{65.58,116.61},{79.54,132.70},{13.55,49.96},
{49.60,92.00},{75.55,143.09},{94.16,145.02},{68.01,123.94},
{11.48,42.98},{ 7.76,56.04},{56.28,118.42},{ 6.09,57.31},
{98.90,179.15},{26.95,84.92},{ 8.52,25.64},{63.05,126.16},
{39.72,94.83},{94.54,159.75},{67.46,123.28},{68.85,138.76},
{46.96,83.67},{67.54,101.95},{23.17,61.79},{29.49,76.26},
{58.17,111.80},{53.25,97.62},{37.89,74.59},{ 7.60,29.16},
{60.72,103.03},{30.80,78.51},{14.13,34.68},{38.44,79.92},
{59.12,111.86},{17.24,56.59},{89.12,133.28},{19.85,60.88},
{90.45,151.93},{82.77,132.73},{34.02,76.70},{54.54,105.19},
{65.08,123.75},{69.80,115.13},{95.30,156.69},{17.66,70.39},
{25.18,82.85},{ 6.02,43.58},{12.61,40.23},{34.32,81.89},
{67.40,100.75},{ 7.81,34.52},{ 7.03,36.08},{22.67,59.09},
{93.01,150.36},{87.02,164.77},{32.20,74.13},{54.87,103.10},
{58.37,135.91},{62.51,96.38},{45.32,89.16},{39.40,80.36},
{12.45,68.04},{61.43,131.19},{59.25,103.13},{26.71,74.65},
{61.25,110.85},{53.78,97.09},{57.75,114.27},{29.38,59.90},
{18.36,71.14},{69.96,118.11},{14.56,39.27},{19.89,40.98},
{68.55,130.17},{ 7.50,47.37},{35.98,101.38},{17.22,43.45},
{76.31,127.73},{ 3.16,47.85},{93.16,152.57},{36.04,77.38},
{60.95,118.72},{ 2.53,27.86},{78.06,137.18},{34.06,71.82},
{83.47,149.39},{43.94,84.91},{82.45,154.13},{70.65,125.11},
{25.67,64.86},{ 3.34,31.20},{15.95,58.76},{82.08,133.76},
{94.85,157.96},{20.05,54.70},{ 3.44,40.93},{40.08,77.92},
{43.31,79.23},{66.15,117.30},{84.56,137.10},{27.33,78.17},
{16.18,46.85},{54.56,94.42},{32.63,78.15},{54.25,118.13},
{90.63,165.79},{57.19,98.26},{46.83,82.83},{ 4.02,24.60},
{66.12,115.96},{71.95,97.79},{52.13,103.65},{31.29,75.26},
{55.91,100.66},{73.56,127.91},{74.57,133.72},{14.54,55.51},
{35.91,76.04},{71.79,112.40},{ 3.52,32.63},{99.48,162.94},
{ 6.95,26.59},{75.82,121.54},{10.08,46.44},{45.52,91.13},
{ 1.68,30.79},{89.95,118.34},{34.84,77.63},{82.45,150.87},
{42.78,63.15},{94.05,152.35},{61.19,104.44},{54.42,104.51},
{ 9.39,44.61},{ 6.90,39.55},{75.00,125.36},{71.30,129.59},
{58.25,97.29},{90.61,147.99},{31.75,67.79},{85.80,137.70},
{79.15,139.56},{44.24,79.90},{81.04,137.23},{65.21,106.73},
{11.01,57.70},{33.41,84.03},{ 5.62,19.26},{77.21,143.88},
{99.40,162.13},{92.80,146.34},{77.65,128.09},{86.21,138.32},
{92.32,158.09},{79.31,150.60},{45.31,91.34},{13.30,45.91},
{91.10,145.10},{94.55,148.44},{90.81,162.01},{98.98,170.98},
{ 5.68,57.45},{10.28,46.14},{13.53,44.62},{52.10,93.46},
{98.73,164.39},{65.57,117.52},{63.85,112.29},{ 5.96,48.16},
{ 8.27,25.85},{14.11,51.72},{87.32,139.79},{ 7.19,36.04},
{36.11,87.96},{79.40,134.60},{79.73,146.13},{69.33,120.83},
{24.96,70.50},{12.89,34.58},{69.45,98.30},{86.02,147.84},
{12.77,47.45},{22.82,76.20},{88.41,150.31},{30.70,72.59},
{43.43,90.49},{25.14,51.00},{51.61,94.30},{61.68,132.43},
{19.55,53.26},{61.03,108.01},{24.35,65.91},{34.89,88.15},
{64.10,104.38},{67.04,133.73},{ 8.14,37.24},{11.35,43.91},
{11.79,46.13},{ 3.91,29.22},{37.60,97.66},{70.40,123.36},
{58.04,122.64},{49.69,93.67},{92.56,162.20},{96.15,157.63},
{23.97,73.66},{84.56,145.39},{61.80,94.78},{55.92,133.05},
{30.56,73.72},{ 4.70,31.81},{64.33,113.26},{50.51,95.26},
{47.10,94.95},{10.32,38.87},{67.75,120.60},{23.91,75.57},
{21.39,61.62},{96.89,147.19},{67.14,123.16},{16.08,61.14},
{93.28,139.31},{50.74,98.09},{37.71,86.95},{78.59,137.61},
{63.89,106.58},{31.69,82.45},{58.08,112.38},{43.16,94.01},
{11.39,25.42},{66.16,112.32},{96.03,152.01},{42.55,83.11},
{32.32,65.15},{23.02,47.10},{29.21,61.35},{16.54,58.56},
{48.28,100.58},{18.08,46.23},{25.86,59.73},{78.52,127.28},
{ 9.95,50.65},{28.39,64.12},{56.10,87.61},{43.22,93.14},
{42.76,89.45},{98.29,159.63},{97.34,177.78},{ 4.27,55.23},
{47.01,105.57},{59.86,114.37},{18.95,51.11},{41.52,84.33},
{62.96,108.18},{27.79,55.86},{16.39,65.66},{66.18,105.45},
{34.86,94.94},{28.47,69.45},{97.67,167.37},{75.86,104.33},
{25.01,74.40},{46.96,87.54},{92.52,129.85},{29.78,73.72},
{85.72,139.37},{83.89,126.76},{59.14,115.78},{46.85,97.38},
{ 6.19,34.32},{11.63,23.31},{11.63,44.46},{22.84,56.76},
{12.00,50.78},{62.84,100.45},{81.42,131.72},{90.47,143.37},
{29.93,88.90},{77.40,122.09},{93.82,145.35},{47.75,96.19},
{21.14,70.74},{97.46,148.02},{12.72,36.39},{49.97,83.79},
{97.95,162.70},{90.86,153.60},{63.85,117.19},{ 4.58,30.40},
{60.56,119.74},{53.52,110.35},{30.87,64.20},{ 6.80,49.32},
{73.95,124.06},{ 6.10,58.73},{22.38,69.13},{60.70,112.49},
{60.85,85.34},{88.28,163.12},{53.88,98.87},{11.25,27.58},
{61.39,111.48},{50.19,101.48},{47.54,105.73},{36.68,74.67},
{16.93,37.98},{63.31,104.97},{98.08,146.59},{20.30,65.51},
{66.90,115.71},{ 3.46,26.89},{75.90,129.36},{ 6.60,56.60},
{58.83,111.03},{69.25,129.30},{76.03,114.70},{62.91,118.23},
{96.98,154.55},{21.79,63.43},{82.03,146.15},{25.64,53.97},
{79.89,145.81},{39.61,84.38},{46.54,88.11},{63.57,98.17},
{78.91,134.57},{92.78,165.65},{88.14,156.37},{ 0.33,35.73},
{51.07,80.06},{37.70,69.07},{76.62,125.56},{74.47,121.16},
{47.03,88.43},{46.70,96.04},{25.41,63.87},{68.35,116.96},
{71.34,120.03},{16.20,49.28},{11.01,49.88},{95.77,162.43},
{28.71,77.99},{46.92,73.65},{62.38,104.31},{86.01,128.55},
{65.86,113.60},{57.63,121.48},{74.36,125.46},{ 1.08,39.77},
{ 8.21,41.65},{13.79,48.62},{83.45,141.43},{15.74,38.94},
{19.63,71.50},{99.25,151.24},{50.00,90.16},{81.22,122.70},
{24.58,46.44},{51.88,85.53},{55.71,84.04},{ 5.93,32.59},
{74.94,134.09},{92.76,149.10},{46.09,101.09},{36.43,94.08},
{ 8.41,38.29},{68.17,99.20},{34.42,85.90},{80.43,138.29},
{48.74,88.09},{56.61,116.21},{27.16,80.41},{96.04,143.67},
{41.60,88.71},{56.43,96.06},{99.67,159.49},{ 7.93,25.69},
{95.21,156.97},{42.55,69.14},{10.74,28.43},{51.32,97.30},
{44.89,83.67},{ 7.40,44.96},{ 1.16,42.00},{ 5.30,37.14},
{96.77,152.72},{ 5.98,40.00},{60.23,122.22},{37.87,84.62},
{42.33,78.24},{18.89,37.62},{26.30,51.55},{ 5.60,42.60},
{32.57,75.79},{94.80,149.64},{98.93,156.85},{ 8.20,41.74},
{38.60,87.55},{88.03,144.13},{28.03,53.93},{26.09,89.76},
{29.84,72.65},{85.36,132.48},{26.97,76.70},{35.26,76.30},
{25.85,70.80},{77.97,127.49},{71.01,138.54},{10.94,49.91},
{31.24,71.77},{ 7.53,44.95},{ 1.52,28.59},{19.27,43.30},
{14.91,45.06},{96.42,156.47},{66.39,126.02},{68.99,112.91},
{18.85,62.58},{32.55,100.92},{33.59,86.01},{58.03,97.94},
{35.86,75.80},{31.33,93.37},{93.26,153.90},{15.52,42.25},
{ 2.75,40.88},{14.25,56.34},{11.34,55.07},{ 1.06,29.82},
{19.47,46.71},{68.39,95.41},{39.15,67.12},{27.81,65.03},
{33.96,68.72},{29.79,83.58},{ 9.85,47.36},{49.47,115.24},
{ 1.24,29.63},{22.96,60.85},{37.50,66.51},{46.51,96.74},
{34.64,72.15},{82.11,143.60},{88.97,152.44},{91.71,145.13},
{13.42,62.70},{56.31,108.49},{26.71,74.17},{52.99,92.39},
{15.94,42.04},{ 1.25,24.40},{70.62,126.08},{88.17,143.68},
{ 7.38,48.95},{50.62,99.33},{43.91,86.82},{ 0.57,26.36},
{27.98,82.27},{38.45,69.65},{11.30,40.94},{45.25,84.73},
{23.87,68.58},{25.37,72.12},{60.34,119.79},{42.59,100.13},
{12.92,41.13},{22.43,55.83},{97.86,168.21},{15.57,53.63},
{26.44,66.90},{99.83,149.10},{83.71,118.45},{69.42,125.64},
{55.85,107.20},{58.00,110.89},{66.97,119.44},{47.25,93.49},
{49.27,106.34},{81.80,147.14},{84.71,137.74},{29.70,61.42},
{71.42,105.56},{68.87,128.05},{46.67,91.29},{65.32,132.59},
{48.76,85.75},{94.55,153.38},{21.41,42.63},{52.33,92.98},
{10.89,38.87},{21.31,52.97},{52.06,85.39},{17.92,50.67},
{73.13,126.80},{65.01,131.31},{37.48,85.60},{62.95,110.14},
{63.03,105.04},{10.10,51.57},{55.89,97.16},{16.20,67.89},
{14.11,38.98},{34.82,80.05},{43.53,87.53},{81.52,149.98},
{65.19,127.61},{13.80,43.24},{62.56,95.92},{32.09,68.79},
{24.35,52.32},{ 8.52,40.70},{83.94,140.84},{76.46,117.49},
{ 9.96,43.44},{90.95,133.38},{29.78,70.77},{15.32,39.57},
{80.51,130.61},{73.15,117.93},{10.85,52.82},{67.84,108.04},
{84.76,131.77},{37.11,74.72},{59.02,110.81},{83.26,138.42},
{44.73,104.58},{95.54,150.49},{60.96,85.42},{70.72,110.25},
{38.20,77.21},{80.19,123.35},{23.75,56.10},{36.83,91.49}
};
double residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
__device__ double d_residual_error(double x, double y, double m, double c) {
double e = (m * x) + c - y;
return e * e;
}
//error calc func
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].x, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
//global func
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
/*
Calculate the current index by using:
- The thread id
- The block id
- The number of threads per block
*/
int i = threadIdx.x + blockIdx.x * blockDim.x;
//sum error stored in array
error_sum_arr[i] = d_residual_error(d_data[i].x, d_data[i].y, *m, *c);
}
//time difffernce
int time_difference(struct timespec *start, struct timespec *finish,
long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
//main funcation
int main() {
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
//time start
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
hipError_t error;
//variables for device func
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be = rms_error(bm, bc);
//allocating memory in device using CUDA malloc
error = hipMalloc(&d_dm, (sizeof(double) * 8));
if(error){
fprintf(stderr, "hipMalloc on d_dm returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//allocating memory in device using CUDA malloc
error = hipMalloc(&d_dc, (sizeof(double) * 8));
if(error){
fprintf(stderr, "hipMalloc on d_dc returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//allocating memory for d_error_sum_arr
error = hipMalloc(&d_error_sum_arr, (sizeof(double) * 1000));
if(error){
fprintf(stderr, "hipMalloc on d_error_sum_arr returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//allocating memory for d_data
error = hipMalloc(&d_data, sizeof(data));
if(error){
fprintf(stderr, "hipMalloc on d_data returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i] = bc + (oc[i] * step);
}
//copying memory host ti device
error = hipMemcpy(d_dm, dm, (sizeof(double) * 8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_dm returned %d %s\n", error,
hipGetErrorString(error));
}
//copying memory host to device
error = hipMemcpy(d_dc, dc, (sizeof(double) * 8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_dc returned %d %s\n", error,
hipGetErrorString(error));
}
//copying memory host to device
error = hipMemcpy(d_data, data, sizeof(data), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_data returned %d %s\n", error,
hipGetErrorString(error));
}
for(i=0;i<8;i++) {
//Host variable storing the array returned from the kernel function.
double h_error_sum_arr[1000];
//Stores the total sum of the values from the error sum array.
double error_sum_total;
//Stores the mean of the total sum of the error sums.
double error_sum_mean;
//Call the rms_error function using 100 blocks and 10 threads.
d_rms_error <<<100,10>>>(&d_dm[i], &d_dc[i], d_error_sum_arr, d_data);
hipDeviceSynchronize();
//Copy memory for d_error_sum_arr
error = hipMemcpy(&h_error_sum_arr, d_error_sum_arr, (sizeof(double) * 1000),
hipMemcpyDeviceToHost);
if(error){
fprintf(stderr, "hipMemcpy to error_sum returned %d %s\n", error,
hipGetErrorString(error));
}
//Loop through the error sum array returned from the kernel function
for(int j=0; j<n_data; j++) {
//Add each error sum to the error sum total.
error_sum_total += h_error_sum_arr[j];
}
//Calculate the mean for the error sum.
error_sum_mean = error_sum_total / n_data;
//Calculate the square root for the error sum mean.
e[i] = sqrt(error_sum_mean);
if(e[i] < best_error) {
best_error = e[i];
best_error_i = i;
}
//Reset the error sum total.
error_sum_total = 0;
}
//printf("best m,c is %lf,%lf with error %lf in direction %d\n",
//dm[best_error_i], dc[best_error_i], best_error, best_error_i);
if(best_error < be) {
be = best_error;
bm = dm[best_error_i];
bc = dc[best_error_i];
} else {
minimum_found = 1;
}
}
//clearing memory
error = hipFree(d_dm);
if(error){
fprintf(stderr, "hipFree on d_dm returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipFree(d_dc);
if(error){
fprintf(stderr, "hipFree on d_dc returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipFree(d_data);
if(error){
fprintf(stderr, "hipFree on d_data returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
error = hipFree(d_error_sum_arr);
if(error){
fprintf(stderr, "hipFree on d_error_sum_arr returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//freee memory complete
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
//geting time after printing m c with error
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
__global__ void updateCenters(float *centers, float *images, int *updates, int noClusters)
{
int gid = blockIdx.x * blockDim.x + threadIdx.x;
int imagesOffset;
int centersIndex=0;
float sum=0;
int index=0;
float weight;
float min;
int minCenterIndex=-1;
int imageSize=784;
float pImage[784];
imagesOffset = gid*imageSize;
for (index=0;index<imageSize;index++){
pImage[index]=images[imagesOffset+index];
}
min=100000000;
for(centersIndex=0;centersIndex<100;centersIndex++)
{
sum = 0;
for(index=0;index<784;index++)
{
weight = centers[centersIndex*imageSize+index]-pImage[index];
sum = sum+weight*weight;
}
if (sum<min)
{
min = sum;
minCenterIndex = centersIndex;
}
}
updates[gid]=minCenterIndex;
} | .file "tmpxft_001a77bb_00000000-6_updateCenters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii
.type _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii, @function
_Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq updateCenters(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii, .-_Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii
.globl updateCenters
.type updateCenters, @function
updateCenters:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size updateCenters, .-updateCenters
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "updateCenters"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq updateCenters(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
__global__ void updateCenters(float *centers, float *images, int *updates, int noClusters)
{
int gid = blockIdx.x * blockDim.x + threadIdx.x;
int imagesOffset;
int centersIndex=0;
float sum=0;
int index=0;
float weight;
float min;
int minCenterIndex=-1;
int imageSize=784;
float pImage[784];
imagesOffset = gid*imageSize;
for (index=0;index<imageSize;index++){
pImage[index]=images[imagesOffset+index];
}
min=100000000;
for(centersIndex=0;centersIndex<100;centersIndex++)
{
sum = 0;
for(index=0;index<784;index++)
{
weight = centers[centersIndex*imageSize+index]-pImage[index];
sum = sum+weight*weight;
}
if (sum<min)
{
min = sum;
minCenterIndex = centersIndex;
}
}
updates[gid]=minCenterIndex;
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void updateCenters(float *centers, float *images, int *updates, int noClusters)
{
int gid = blockIdx.x * blockDim.x + threadIdx.x;
int imagesOffset;
int centersIndex=0;
float sum=0;
int index=0;
float weight;
float min;
int minCenterIndex=-1;
int imageSize=784;
float pImage[784];
imagesOffset = gid*imageSize;
for (index=0;index<imageSize;index++){
pImage[index]=images[imagesOffset+index];
}
min=100000000;
for(centersIndex=0;centersIndex<100;centersIndex++)
{
sum = 0;
for(index=0;index<784;index++)
{
weight = centers[centersIndex*imageSize+index]-pImage[index];
sum = sum+weight*weight;
}
if (sum<min)
{
min = sum;
minCenterIndex = centersIndex;
}
}
updates[gid]=minCenterIndex;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void updateCenters(float *centers, float *images, int *updates, int noClusters)
{
int gid = blockIdx.x * blockDim.x + threadIdx.x;
int imagesOffset;
int centersIndex=0;
float sum=0;
int index=0;
float weight;
float min;
int minCenterIndex=-1;
int imageSize=784;
float pImage[784];
imagesOffset = gid*imageSize;
for (index=0;index<imageSize;index++){
pImage[index]=images[imagesOffset+index];
}
min=100000000;
for(centersIndex=0;centersIndex<100;centersIndex++)
{
sum = 0;
for(index=0;index<784;index++)
{
weight = centers[centersIndex*imageSize+index]-pImage[index];
sum = sum+weight*weight;
}
if (sum<min)
{
min = sum;
minCenterIndex = centersIndex;
}
}
updates[gid]=minCenterIndex;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected updateCenters
.globl updateCenters
.p2align 8
.type updateCenters,@function
updateCenters:
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x8
v_mul_lo_u32 v2, v1, 0x310
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
.LBB0_1:
global_load_b32 v0, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s3, s2, 16
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s2, 0xc40
s_waitcnt vmcnt(0)
scratch_store_b32 off, v0, s3
s_cbranch_scc1 .LBB0_1
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v0, -1
v_mov_b32_e32 v2, 0x4cbebc20
s_mov_b32 s6, 0
.p2align 6
.LBB0_3:
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[4:5], s[2:3]
s_mov_b32 s7, 0
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s8, s7, 16
s_add_i32 s7, s7, 4
scratch_load_b32 v4, off, s8
s_load_b32 s8, s[4:5], 0x0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmpk_lg_i32 s7, 0xc40
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v4, s8, v4
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v4
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v3, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cndmask_b32_e64 v0, v0, s6, vcc_lo
s_add_i32 s6, s6, 1
s_add_u32 s2, s2, 0xc40
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s6, 0x64
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel updateCenters
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 3152
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size updateCenters, .Lfunc_end0-updateCenters
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: updateCenters
.private_segment_fixed_size: 3152
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: updateCenters.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void updateCenters(float *centers, float *images, int *updates, int noClusters)
{
int gid = blockIdx.x * blockDim.x + threadIdx.x;
int imagesOffset;
int centersIndex=0;
float sum=0;
int index=0;
float weight;
float min;
int minCenterIndex=-1;
int imageSize=784;
float pImage[784];
imagesOffset = gid*imageSize;
for (index=0;index<imageSize;index++){
pImage[index]=images[imagesOffset+index];
}
min=100000000;
for(centersIndex=0;centersIndex<100;centersIndex++)
{
sum = 0;
for(index=0;index<784;index++)
{
weight = centers[centersIndex*imageSize+index]-pImage[index];
sum = sum+weight*weight;
}
if (sum<min)
{
min = sum;
minCenterIndex = centersIndex;
}
}
updates[gid]=minCenterIndex;
} | .text
.file "updateCenters.hip"
.globl __device_stub__updateCenters # -- Begin function __device_stub__updateCenters
.p2align 4, 0x90
.type __device_stub__updateCenters,@function
__device_stub__updateCenters: # @__device_stub__updateCenters
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $updateCenters, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__updateCenters, .Lfunc_end0-__device_stub__updateCenters
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $updateCenters, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type updateCenters,@object # @updateCenters
.section .rodata,"a",@progbits
.globl updateCenters
.p2align 3, 0x0
updateCenters:
.quad __device_stub__updateCenters
.size updateCenters, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "updateCenters"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__updateCenters
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym updateCenters
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a77bb_00000000-6_updateCenters.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii
.type _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii, @function
_Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq updateCenters(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii, .-_Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii
.globl updateCenters
.type updateCenters, @function
updateCenters:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13updateCentersPfS_PiiPfS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size updateCenters, .-updateCenters
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "updateCenters"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq updateCenters(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "updateCenters.hip"
.globl __device_stub__updateCenters # -- Begin function __device_stub__updateCenters
.p2align 4, 0x90
.type __device_stub__updateCenters,@function
__device_stub__updateCenters: # @__device_stub__updateCenters
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $updateCenters, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__updateCenters, .Lfunc_end0-__device_stub__updateCenters
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $updateCenters, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type updateCenters,@object # @updateCenters
.section .rodata,"a",@progbits
.globl updateCenters
.p2align 3, 0x0
updateCenters:
.quad __device_stub__updateCenters
.size updateCenters, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "updateCenters"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__updateCenters
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym updateCenters
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void square(int*a , int *t)
{
int n = threadIdx.x, m=blockIdx.x, size=blockDim.x, size1=gridDim.x;
int i= m*size+n;
t[i]=1;
//int final=0;
for(int j=0;j<(m+1);j++)
t[i]*=a[i];
}
int main(int argc, char const *argv[])
{
int *a,*t,m,n,i,j;
int *d_a, *d_t;
printf("enter the value of m \n");
scanf("%d",&m);
printf("enter the value of n\n");
scanf("%d",&n);
int size= sizeof(int)*m*n;
a=(int*)malloc(m*n*sizeof(int));
t=(int*)malloc(m*n*sizeof(int));
printf("enter the input matrix\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
square<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("the result vector is :\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
printf("%d\t",t[i*n+j] );
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | code for sm_80
Function : _Z6squarePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x041fe20003f06270 */
/*0070*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x002fca00078e0200 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*00a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x001fe40000011400 */
/*00d0*/ LEA R4, P1, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x040fe400078210ff */
/*00e0*/ IADD3 R6, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590000057a11 */
/* 0x000fc400008f1405 */
/*0100*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fe40000000f00 */
/*0110*/ LOP3.LUT R0, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306007812 */
/* 0x000fe200078ec0ff */
/*0120*/ @!P0 BRA 0x7d0 ; /* 0x000006a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R0, R9, RZ ; /* 0x0000000900067210 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fc600000001ff */
/*0150*/ ISETP.GT.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fda0003f04270 */
/*0160*/ @!P0 BRA 0x6e0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe40007ffe0ff */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01a0*/ @!P1 BRA 0x4f0 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x004ea4000c1e1900 */
/*01d0*/ IMAD R7, R8, R7, RZ ; /* 0x0000000708077224 */
/* 0x004fca00078e02ff */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0200*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x004fca00078e02ff */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0230*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*0240*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0250*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x008fca00078e02ff */
/*0270*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0280*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0290*/ IMAD R7, R13, R8, RZ ; /* 0x000000080d077224 */
/* 0x001fca00078e02ff */
/*02a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e64000c1e1900 */
/*02c0*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x002fca00078e02ff */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*0300*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0320*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x008fca00078e02ff */
/*0330*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0340*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0350*/ IMAD R7, R13, R8, RZ ; /* 0x000000080d077224 */
/* 0x001fca00078e02ff */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0370*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e64000c1e1900 */
/*0380*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x002fca00078e02ff */
/*0390*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*03c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*03e0*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x008fca00078e02ff */
/*03f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0410*/ IMAD R15, R13, R8, RZ ; /* 0x000000080d0f7224 */
/* 0x008fca00078e02ff */
/*0420*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0430*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0440*/ IMAD R9, R15, R8, RZ ; /* 0x000000080f097224 */
/* 0x001fca00078e02ff */
/*0450*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e8000c101904 */
/*0460*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e62000c1e1900 */
/*0470*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0480*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x002fca00078e02ff */
/*0490*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*04a0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ ISETP.GT.AND P1, PT, R6, 0xb, PT ; /* 0x0000000b0600780c */
/* 0x000fe20003f24270 */
/*04c0*/ IMAD R7, R11, R8, RZ ; /* 0x000000080b077224 */
/* 0x008fca00078e02ff */
/*04d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0005ee000c101904 */
/*04e0*/ @P1 BRA 0x1c0 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*04f0*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0510*/ @!P1 BRA 0x6c0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0530*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x00cfca00078e02ff */
/*0540*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0550*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0560*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x004fca00078e02ff */
/*0570*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0590*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*05a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*05b0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*05c0*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x004fca00078e02ff */
/*05d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*05e0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*05f0*/ IMAD R15, R13, R8, RZ ; /* 0x000000080d0f7224 */
/* 0x008fca00078e02ff */
/*0600*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0610*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0620*/ IMAD R9, R15, R8, RZ ; /* 0x000000080f097224 */
/* 0x001fca00078e02ff */
/*0630*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e8000c101904 */
/*0640*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e64000c1e1900 */
/*0650*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x002fca00078e02ff */
/*0660*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0670*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*0680*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0690*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ IMAD R7, R11, R8, RZ ; /* 0x000000080b077224 */
/* 0x008fca00078e02ff */
/*06b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0005e8000c101904 */
/*06c0*/ ISETP.NE.OR P0, PT, R6, -0x1, P0 ; /* 0xffffffff0600780c */
/* 0x000fda0000705670 */
/*06d0*/ @!P0 BRA 0x7d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*06e0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*06f0*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x00cfca00078e02ff */
/*0700*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0720*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*0730*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0740*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0760*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x004fca00078e02ff */
/*0770*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0780*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0790*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fe20003f05270 */
/*07a0*/ IMAD R7, R13, R8, RZ ; /* 0x000000080d077224 */
/* 0x004fca00078e02ff */
/*07b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*07c0*/ @P0 BRA 0x6e0 ; /* 0xffffff1000000947 */
/* 0x001fea000383ffff */
/*07d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*07e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1900 */
/*0800*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0810*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0820*/ IMAD R7, R6, R7, RZ ; /* 0x0000000706077224 */
/* 0x00dfca00078e02ff */
/*0830*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*0840*/ @P0 BRA 0x7f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0850*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void square(int*a , int *t)
{
int n = threadIdx.x, m=blockIdx.x, size=blockDim.x, size1=gridDim.x;
int i= m*size+n;
t[i]=1;
//int final=0;
for(int j=0;j<(m+1);j++)
t[i]*=a[i];
}
int main(int argc, char const *argv[])
{
int *a,*t,m,n,i,j;
int *d_a, *d_t;
printf("enter the value of m \n");
scanf("%d",&m);
printf("enter the value of n\n");
scanf("%d",&n);
int size= sizeof(int)*m*n;
a=(int*)malloc(m*n*sizeof(int));
t=(int*)malloc(m*n*sizeof(int));
printf("enter the input matrix\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
square<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("the result vector is :\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
printf("%d\t",t[i*n+j] );
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | .file "tmpxft_000e79ac_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePiS_PiS_
.type _Z27__device_stub__Z6squarePiS_PiS_, @function
_Z27__device_stub__Z6squarePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePiS_PiS_, .-_Z27__device_stub__Z6squarePiS_PiS_
.globl _Z6squarePiS_
.type _Z6squarePiS_, @function
_Z6squarePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePiS_, .-_Z6squarePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "enter the value of m \n"
.LC1:
.string "%d"
.LC2:
.string "enter the value of n\n"
.LC3:
.string "enter the input matrix\n"
.LC4:
.string "the result vector is :\n"
.LC5:
.string "%d\t"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 8(%rsp), %eax
movl 12(%rsp), %edx
movl %eax, %r14d
imull %edx, %r14d
sall $2, %r14d
imull %edx, %eax
movslq %eax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .L12
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L13:
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cmpl %ebx, %eax
jg .L13
.L12:
movslq %r14d, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L14:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r14
cmpl $0, 8(%rsp)
jg .L15
.L16:
movq stdin(%rip), %rdi
call getc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePiS_PiS_
jmp .L14
.L17:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 12(%rsp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jle .L16
.L15:
movl 12(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6squarePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void square(int*a , int *t)
{
int n = threadIdx.x, m=blockIdx.x, size=blockDim.x, size1=gridDim.x;
int i= m*size+n;
t[i]=1;
//int final=0;
for(int j=0;j<(m+1);j++)
t[i]*=a[i];
}
int main(int argc, char const *argv[])
{
int *a,*t,m,n,i,j;
int *d_a, *d_t;
printf("enter the value of m \n");
scanf("%d",&m);
printf("enter the value of n\n");
scanf("%d",&n);
int size= sizeof(int)*m*n;
a=(int*)malloc(m*n*sizeof(int));
t=(int*)malloc(m*n*sizeof(int));
printf("enter the input matrix\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
square<<<m,n>>>(d_a,d_t);
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("the result vector is :\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
printf("%d\t",t[i*n+j] );
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void square(int*a , int *t)
{
int n = threadIdx.x, m=blockIdx.x, size=blockDim.x, size1=gridDim.x;
int i= m*size+n;
t[i]=1;
//int final=0;
for(int j=0;j<(m+1);j++)
t[i]*=a[i];
}
int main(int argc, char const *argv[])
{
int *a,*t,m,n,i,j;
int *d_a, *d_t;
printf("enter the value of m \n");
scanf("%d",&m);
printf("enter the value of n\n");
scanf("%d",&n);
int size= sizeof(int)*m*n;
a=(int*)malloc(m*n*sizeof(int));
t=(int*)malloc(m*n*sizeof(int));
printf("enter the input matrix\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
square<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("the result vector is :\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
printf("%d\t",t[i*n+j] );
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void square(int*a , int *t)
{
int n = threadIdx.x, m=blockIdx.x, size=blockDim.x, size1=gridDim.x;
int i= m*size+n;
t[i]=1;
//int final=0;
for(int j=0;j<(m+1);j++)
t[i]*=a[i];
}
int main(int argc, char const *argv[])
{
int *a,*t,m,n,i,j;
int *d_a, *d_t;
printf("enter the value of m \n");
scanf("%d",&m);
printf("enter the value of n\n");
scanf("%d",&n);
int size= sizeof(int)*m*n;
a=(int*)malloc(m*n*sizeof(int));
t=(int*)malloc(m*n*sizeof(int));
printf("enter the input matrix\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
square<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("the result vector is :\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
printf("%d\t",t[i*n+j] );
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePiS_
.globl _Z6squarePiS_
.p2align 8
.type _Z6squarePiS_,@function
_Z6squarePiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_lt_i32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_add_i32 s0, s15, 1
.LBB0_2:
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v5, v4
global_store_b32 v[0:1], v4, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePiS_, .Lfunc_end0-_Z6squarePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6squarePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void square(int*a , int *t)
{
int n = threadIdx.x, m=blockIdx.x, size=blockDim.x, size1=gridDim.x;
int i= m*size+n;
t[i]=1;
//int final=0;
for(int j=0;j<(m+1);j++)
t[i]*=a[i];
}
int main(int argc, char const *argv[])
{
int *a,*t,m,n,i,j;
int *d_a, *d_t;
printf("enter the value of m \n");
scanf("%d",&m);
printf("enter the value of n\n");
scanf("%d",&n);
int size= sizeof(int)*m*n;
a=(int*)malloc(m*n*sizeof(int));
t=(int*)malloc(m*n*sizeof(int));
printf("enter the input matrix\n");
for(i=0;i<m*n;i++)
scanf("%d",&a[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
square<<<m,n>>>(d_a,d_t);
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("the result vector is :\n");
for(i=0;i<m;i++)
{
for(j=0;j<n;j++)
printf("%d\t",t[i*n+j] );
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.file "q1.hip"
.globl _Z21__device_stub__squarePiS_ # -- Begin function _Z21__device_stub__squarePiS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePiS_,@function
_Z21__device_stub__squarePiS_: # @_Z21__device_stub__squarePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePiS_, .Lfunc_end0-_Z21__device_stub__squarePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebp
imull 12(%rsp), %ebp
movslq %ebp, %rbx
shll $2, %ebp
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr.2, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %r12
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6squarePiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.6: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge29
# in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_11
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_10
# %bb.8: # %.lr.ph28.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph28
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_9
jmp .LBB1_10
.LBB1_11: # %._crit_edge31
movq stdin(%rip), %rdi
callq getc
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePiS_,@object # @_Z6squarePiS_
.section .rodata,"a",@progbits
.globl _Z6squarePiS_
.p2align 3, 0x0
_Z6squarePiS_:
.quad _Z21__device_stub__squarePiS_
.size _Z6squarePiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "enter the value of m "
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "enter the value of n"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "enter the input matrix"
.size .Lstr.2, 23
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "the result vector is :"
.size .Lstr.3, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x041fe20003f06270 */
/*0070*/ IMAD R0, R9, c[0x0][0x0], R0 ; /* 0x0000000009007a24 */
/* 0x002fca00078e0200 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*00a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R9.reuse, 0x3, PT ; /* 0x000000030900780c */
/* 0x040fe40003f06070 */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x001fe40000011400 */
/*00d0*/ LEA R4, P1, R0.reuse, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x040fe400078210ff */
/*00e0*/ IADD3 R6, R9, 0x1, RZ ; /* 0x0000000109067810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ LEA.HI.X R5, R0, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590000057a11 */
/* 0x000fc400008f1405 */
/*0100*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x000fe40000000f00 */
/*0110*/ LOP3.LUT R0, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306007812 */
/* 0x000fe200078ec0ff */
/*0120*/ @!P0 BRA 0x7d0 ; /* 0x000006a000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R0, R9, RZ ; /* 0x0000000900067210 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fc600000001ff */
/*0150*/ ISETP.GT.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fda0003f04270 */
/*0160*/ @!P0 BRA 0x6e0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fe40007ffe0ff */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01a0*/ @!P1 BRA 0x4f0 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x004ea4000c1e1900 */
/*01d0*/ IMAD R7, R8, R7, RZ ; /* 0x0000000708077224 */
/* 0x004fca00078e02ff */
/*01e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0200*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x004fca00078e02ff */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0220*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0230*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*0240*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0250*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0260*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x008fca00078e02ff */
/*0270*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0280*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0290*/ IMAD R7, R13, R8, RZ ; /* 0x000000080d077224 */
/* 0x001fca00078e02ff */
/*02a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e64000c1e1900 */
/*02c0*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x002fca00078e02ff */
/*02d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*0300*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0320*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x008fca00078e02ff */
/*0330*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0340*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0350*/ IMAD R7, R13, R8, RZ ; /* 0x000000080d077224 */
/* 0x001fca00078e02ff */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0370*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e64000c1e1900 */
/*0380*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x002fca00078e02ff */
/*0390*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*03c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*03e0*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x008fca00078e02ff */
/*03f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0410*/ IMAD R15, R13, R8, RZ ; /* 0x000000080d0f7224 */
/* 0x008fca00078e02ff */
/*0420*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0430*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0440*/ IMAD R9, R15, R8, RZ ; /* 0x000000080f097224 */
/* 0x001fca00078e02ff */
/*0450*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e8000c101904 */
/*0460*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e62000c1e1900 */
/*0470*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0480*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x002fca00078e02ff */
/*0490*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*04a0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ ISETP.GT.AND P1, PT, R6, 0xb, PT ; /* 0x0000000b0600780c */
/* 0x000fe20003f24270 */
/*04c0*/ IMAD R7, R11, R8, RZ ; /* 0x000000080b077224 */
/* 0x008fca00078e02ff */
/*04d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0005ee000c101904 */
/*04e0*/ @P1 BRA 0x1c0 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*04f0*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0510*/ @!P1 BRA 0x6c0 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0520*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*0530*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x00cfca00078e02ff */
/*0540*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0550*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0560*/ IMAD R9, R7, R8, RZ ; /* 0x0000000807097224 */
/* 0x004fca00078e02ff */
/*0570*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0590*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*05a0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*05b0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*05c0*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x004fca00078e02ff */
/*05d0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*05e0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*05f0*/ IMAD R15, R13, R8, RZ ; /* 0x000000080d0f7224 */
/* 0x008fca00078e02ff */
/*0600*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e8000c101904 */
/*0610*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e24000c1e1900 */
/*0620*/ IMAD R9, R15, R8, RZ ; /* 0x000000080f097224 */
/* 0x001fca00078e02ff */
/*0630*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0005e8000c101904 */
/*0640*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000e64000c1e1900 */
/*0650*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x002fca00078e02ff */
/*0660*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0670*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1900 */
/*0680*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0690*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ IMAD R7, R11, R8, RZ ; /* 0x000000080b077224 */
/* 0x008fca00078e02ff */
/*06b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0005e8000c101904 */
/*06c0*/ ISETP.NE.OR P0, PT, R6, -0x1, P0 ; /* 0xffffffff0600780c */
/* 0x000fda0000705670 */
/*06d0*/ @!P0 BRA 0x7d0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*06e0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee4000c1e1900 */
/*06f0*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x00cfca00078e02ff */
/*0700*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0720*/ IMAD R11, R9, R8, RZ ; /* 0x00000008090b7224 */
/* 0x004fca00078e02ff */
/*0730*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0740*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0760*/ IMAD R13, R11, R8, RZ ; /* 0x000000080b0d7224 */
/* 0x004fca00078e02ff */
/*0770*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0780*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*0790*/ ISETP.NE.AND P0, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x000fe20003f05270 */
/*07a0*/ IMAD R7, R13, R8, RZ ; /* 0x000000080d077224 */
/* 0x004fca00078e02ff */
/*07b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*07c0*/ @P0 BRA 0x6e0 ; /* 0xffffff1000000947 */
/* 0x001fea000383ffff */
/*07d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*07e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1900 */
/*0800*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0810*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0820*/ IMAD R7, R6, R7, RZ ; /* 0x0000000706077224 */
/* 0x00dfca00078e02ff */
/*0830*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ee000c101904 */
/*0840*/ @P0 BRA 0x7f0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0850*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePiS_
.globl _Z6squarePiS_
.p2align 8
.type _Z6squarePiS_,@function
_Z6squarePiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v4, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_cmp_lt_i32 s15, 0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
s_cbranch_scc1 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_add_i32 s0, s15, 1
.LBB0_2:
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v5, v4
global_store_b32 v[0:1], v4, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePiS_, .Lfunc_end0-_Z6squarePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6squarePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e79ac_00000000-6_q1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePiS_PiS_
.type _Z27__device_stub__Z6squarePiS_PiS_, @function
_Z27__device_stub__Z6squarePiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePiS_PiS_, .-_Z27__device_stub__Z6squarePiS_PiS_
.globl _Z6squarePiS_
.type _Z6squarePiS_, @function
_Z6squarePiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePiS_, .-_Z6squarePiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "enter the value of m \n"
.LC1:
.string "%d"
.LC2:
.string "enter the value of n\n"
.LC3:
.string "enter the input matrix\n"
.LC4:
.string "the result vector is :\n"
.LC5:
.string "%d\t"
.LC6:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 8(%rsp), %rsi
leaq .LC1(%rip), %rbx
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 8(%rsp), %eax
movl 12(%rsp), %edx
movl %eax, %r14d
imull %edx, %r14d
sall $2, %r14d
imull %edx, %eax
movslq %eax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .L12
movq %r15, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
.L13:
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
movl 8(%rsp), %eax
imull 12(%rsp), %eax
cmpl %ebx, %eax
jg .L13
.L12:
movslq %r14d, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl 8(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L14:
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC6(%rip), %r14
cmpl $0, 8(%rsp)
jg .L15
.L16:
movq stdin(%rip), %rdi
call getc@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePiS_PiS_
jmp .L14
.L17:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 12(%rsp), %eax
cmpl %ebx, %eax
jg .L17
.L18:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 8(%rsp)
jle .L16
.L15:
movl 12(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L17
jmp .L18
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z6squarePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q1.hip"
.globl _Z21__device_stub__squarePiS_ # -- Begin function _Z21__device_stub__squarePiS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePiS_,@function
_Z21__device_stub__squarePiS_: # @_Z21__device_stub__squarePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePiS_, .Lfunc_end0-_Z21__device_stub__squarePiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebp
imull 12(%rsp), %ebp
movslq %ebp, %rbx
shll $2, %ebp
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr.2, %edi
callq puts@PLT
movl 8(%rsp), %eax
imull 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r15, %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 12(%rsp), %rax
movslq 8(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r14
cmpq %rcx, %r12
jl .LBB1_2
.LBB1_3: # %._crit_edge
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movl 8(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6squarePiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 12(%rsp)
jle .LBB1_11
# %bb.6: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_10: # %._crit_edge29
# in Loop: Header=BB1_7 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB1_11
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_10
# %bb.8: # %.lr.ph28.preheader
# in Loop: Header=BB1_7 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_9: # %.lr.ph28
# Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_9
jmp .LBB1_10
.LBB1_11: # %._crit_edge31
movq stdin(%rip), %rdi
callq getc
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePiS_,@object # @_Z6squarePiS_
.section .rodata,"a",@progbits
.globl _Z6squarePiS_
.p2align 3, 0x0
_Z6squarePiS_:
.quad _Z21__device_stub__squarePiS_
.size _Z6squarePiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\t"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePiS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "enter the value of m "
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "enter the value of n"
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "enter the input matrix"
.size .Lstr.2, 23
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "the result vector is :"
.size .Lstr.3, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // allocate pitch memory and cudaArray
#include <stdio.h>
#include <memory.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define NX 1003
#define NY 1003
int main(){
size_t sizeByte = NX*NY*sizeof(float);
//host data declaration and initialization
float* hdata = (float* )malloc(sizeByte);
for(int i=0;i<NX*NY; i++){
hdata[i] = i;
}
//using pitch linear memory
float *ddata_pl;
float *ddata_pl_res;
size_t sizePL;
cudaMallocPitch((void**)&ddata_pl, &sizePL, NX*sizeof(float), NY);
printf("Pitch of ddata_pl is %d \n", sizePL);
printf("While Pitch of hdata is %d \n", NX*sizeof(float));
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // allocate pitch memory and cudaArray
#include <stdio.h>
#include <memory.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define NX 1003
#define NY 1003
int main(){
size_t sizeByte = NX*NY*sizeof(float);
//host data declaration and initialization
float* hdata = (float* )malloc(sizeByte);
for(int i=0;i<NX*NY; i++){
hdata[i] = i;
}
//using pitch linear memory
float *ddata_pl;
float *ddata_pl_res;
size_t sizePL;
cudaMallocPitch((void**)&ddata_pl, &sizePL, NX*sizeof(float), NY);
printf("Pitch of ddata_pl is %d \n", sizePL);
printf("While Pitch of hdata is %d \n", NX*sizeof(float));
return 0;
} | .file "tmpxft_0014432b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Pitch of ddata_pl is %d \n"
.LC1:
.string "While Pitch of hdata is %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4024036, %edi
call malloc@PLT
movl $0, %edx
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rax,%rdx,4)
addq $1, %rdx
cmpq $1006009, %rdx
jne .L4
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $1003, %ecx
movl $4012, %edx
call cudaMallocPitch@PLT
movq 16(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4012, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // allocate pitch memory and cudaArray
#include <stdio.h>
#include <memory.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define NX 1003
#define NY 1003
int main(){
size_t sizeByte = NX*NY*sizeof(float);
//host data declaration and initialization
float* hdata = (float* )malloc(sizeByte);
for(int i=0;i<NX*NY; i++){
hdata[i] = i;
}
//using pitch linear memory
float *ddata_pl;
float *ddata_pl_res;
size_t sizePL;
cudaMallocPitch((void**)&ddata_pl, &sizePL, NX*sizeof(float), NY);
printf("Pitch of ddata_pl is %d \n", sizePL);
printf("While Pitch of hdata is %d \n", NX*sizeof(float));
return 0;
} | // allocate pitch memory and cudaArray
#include <stdio.h>
#include <memory.h>
#include <hip/hip_runtime.h>
#define NX 1003
#define NY 1003
int main(){
size_t sizeByte = NX*NY*sizeof(float);
//host data declaration and initialization
float* hdata = (float* )malloc(sizeByte);
for(int i=0;i<NX*NY; i++){
hdata[i] = i;
}
//using pitch linear memory
float *ddata_pl;
float *ddata_pl_res;
size_t sizePL;
hipMallocPitch((void**)&ddata_pl, &sizePL, NX*sizeof(float), NY);
printf("Pitch of ddata_pl is %d \n", sizePL);
printf("While Pitch of hdata is %d \n", NX*sizeof(float));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // allocate pitch memory and cudaArray
#include <stdio.h>
#include <memory.h>
#include <hip/hip_runtime.h>
#define NX 1003
#define NY 1003
int main(){
size_t sizeByte = NX*NY*sizeof(float);
//host data declaration and initialization
float* hdata = (float* )malloc(sizeByte);
for(int i=0;i<NX*NY; i++){
hdata[i] = i;
}
//using pitch linear memory
float *ddata_pl;
float *ddata_pl_res;
size_t sizePL;
hipMallocPitch((void**)&ddata_pl, &sizePL, NX*sizeof(float), NY);
printf("Pitch of ddata_pl is %d \n", sizePL);
printf("While Pitch of hdata is %d \n", NX*sizeof(float));
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // allocate pitch memory and cudaArray
#include <stdio.h>
#include <memory.h>
#include <hip/hip_runtime.h>
#define NX 1003
#define NY 1003
int main(){
size_t sizeByte = NX*NY*sizeof(float);
//host data declaration and initialization
float* hdata = (float* )malloc(sizeByte);
for(int i=0;i<NX*NY; i++){
hdata[i] = i;
}
//using pitch linear memory
float *ddata_pl;
float *ddata_pl_res;
size_t sizePL;
hipMallocPitch((void**)&ddata_pl, &sizePL, NX*sizeof(float), NY);
printf("Pitch of ddata_pl is %d \n", sizePL);
printf("While Pitch of hdata is %d \n", NX*sizeof(float));
return 0;
} | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4012, %edx # imm = 0xFAC
movl $1003, %ecx # imm = 0x3EB
callq hipMallocPitch
movq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $4012, %esi # imm = 0xFAC
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Pitch of ddata_pl is %d \n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "While Pitch of hdata is %d \n"
.size .L.str.1, 29
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014432b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Pitch of ddata_pl is %d \n"
.LC1:
.string "While Pitch of hdata is %d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $4024036, %edi
call malloc@PLT
movl $0, %edx
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rax,%rdx,4)
addq $1, %rdx
cmpq $1006009, %rdx
jne .L4
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movl $1003, %ecx
movl $4012, %edx
call cudaMallocPitch@PLT
movq 16(%rsp), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4012, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $4012, %edx # imm = 0xFAC
movl $1003, %ecx # imm = 0x3EB
callq hipMallocPitch
movq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $4012, %esi # imm = 0xFAC
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Pitch of ddata_pl is %d \n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "While Pitch of hdata is %d \n"
.size .L.str.1, 29
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
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