system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void update_core(double *f, double *g, double *c, int nx, int ny) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int i = tid / ny;
int j = tid % ny;
if (i > 0 && j > 0 && i < nx-1 && j < ny-1) {
f[tid] = c[tid] * (g[tid-ny] + g[tid+ny] + g[tid-1] + g[tid+1]
- 4*g[tid]) + 2*g[tid] - f[tid];
}
}
__global__ void update_src(double *f, double val, int idx0) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
f[idx0] += val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11update_corePdS_S_ii
.globl _Z11update_corePdS_S_ii
.p2align 8
.type _Z11update_corePdS_S_ii,@function
_Z11update_corePdS_S_ii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s9, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s9, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_add_i32 s2, s8, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
s_add_i32 s3, s9, -1
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_mul_lo_u32 v2, v0, s9
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_min_i32_e32 v3, v0, v2
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, 0, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_subrev_nc_u32_e32 v2, s9, v1
v_add_nc_u32_e32 v4, s9, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s0, v8
s_clause 0x1
global_load_b64 v[10:11], v[0:1], off offset:-8
global_load_b128 v[0:3], v[0:1], off
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[12:13], v[12:13], off
global_load_b64 v[14:15], v[8:9], off
s_waitcnt vmcnt(4)
v_add_f64 v[4:5], v[6:7], v[4:5]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[10:11]
s_waitcnt vmcnt(2)
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[0:1], -4.0, v[2:3]
s_waitcnt vmcnt(1)
v_mul_f64 v[2:3], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], 2.0, v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], -v[14:15]
global_store_b64 v[8:9], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11update_corePdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11update_corePdS_S_ii, .Lfunc_end0-_Z11update_corePdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10update_srcPddi
.globl _Z10update_srcPddi
.p2align 8
.type _Z10update_srcPddi,@function
_Z10update_srcPddi:
s_load_b32 s2, s[0:1], 0x24
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 3
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], s[4:5], s[2:3]
global_store_b64 v2, v[0:1], s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10update_srcPddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10update_srcPddi, .Lfunc_end1-_Z10update_srcPddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11update_corePdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11update_corePdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10update_srcPddi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10update_srcPddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void update_core(double *f, double *g, double *c, int nx, int ny) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int i = tid / ny;
int j = tid % ny;
if (i > 0 && j > 0 && i < nx-1 && j < ny-1) {
f[tid] = c[tid] * (g[tid-ny] + g[tid+ny] + g[tid-1] + g[tid+1]
- 4*g[tid]) + 2*g[tid] - f[tid];
}
}
__global__ void update_src(double *f, double val, int idx0) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) {
f[idx0] += val;
}
} | .text
.file "pycuda_wave_fd.hip"
.globl _Z26__device_stub__update_corePdS_S_ii # -- Begin function _Z26__device_stub__update_corePdS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__update_corePdS_S_ii,@function
_Z26__device_stub__update_corePdS_S_ii: # @_Z26__device_stub__update_corePdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11update_corePdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__update_corePdS_S_ii, .Lfunc_end0-_Z26__device_stub__update_corePdS_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__update_srcPddi # -- Begin function _Z25__device_stub__update_srcPddi
.p2align 4, 0x90
.type _Z25__device_stub__update_srcPddi,@function
_Z25__device_stub__update_srcPddi: # @_Z25__device_stub__update_srcPddi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10update_srcPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__update_srcPddi, .Lfunc_end1-_Z25__device_stub__update_srcPddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11update_corePdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10update_srcPddi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11update_corePdS_S_ii,@object # @_Z11update_corePdS_S_ii
.section .rodata,"a",@progbits
.globl _Z11update_corePdS_S_ii
.p2align 3, 0x0
_Z11update_corePdS_S_ii:
.quad _Z26__device_stub__update_corePdS_S_ii
.size _Z11update_corePdS_S_ii, 8
.type _Z10update_srcPddi,@object # @_Z10update_srcPddi
.globl _Z10update_srcPddi
.p2align 3, 0x0
_Z10update_srcPddi:
.quad _Z25__device_stub__update_srcPddi
.size _Z10update_srcPddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11update_corePdS_S_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10update_srcPddi"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__update_corePdS_S_ii
.addrsig_sym _Z25__device_stub__update_srcPddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11update_corePdS_S_ii
.addrsig_sym _Z10update_srcPddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10update_srcPddi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x002fca00078e0a00 */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R2, c[0x0][0x170] ; /* 0x00005c0000027a02 */
/* 0x000fe20000000f00 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00b0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ DADD R4, R4, c[0x0][0x168] ; /* 0x00005a0004047629 */
/* 0x004e0e0000000000 */
/*00e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11update_corePdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x17c] ; /* 0x00005f0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0030*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0040*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x000fe40000000a00 */
/*0070*/ UIADD3 UR4, -UR5, UR6, URZ ; /* 0x0000000605047290 */
/* 0x000fe4000fffe13f */
/*0080*/ UIADD3 UR5, -UR5, UR7, URZ ; /* 0x0000000705057290 */
/* 0x000fc4000fffe13f */
/*0090*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*00a0*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*00b0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*00c0*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fe40000000000 */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0120*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0140*/ IMAD R0, R7, R5, R0 ; /* 0x0000000507007224 */
/* 0x000fca00078e0200 */
/*0150*/ ISETP.GT.U32.AND P2, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f44070 */
/*0160*/ @!P2 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x800000070000a210 */
/* 0x080fe40007ffe0ff */
/*0170*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06070 */
/*0190*/ LOP3.LUT R0, R4, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0004007a12 */
/* 0x000fe400078e3cff */
/*01a0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f45270 */
/*01b0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*01c0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*01d0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*01e0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff03aa12 */
/* 0x000fca00078e33ff */
/*01f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0200*/ IMAD R0, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005007a24 */
/* 0x000fca00078e0204 */
/*0210*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*0220*/ ISETP.LT.OR P0, PT, R3, 0x1, !P0 ; /* 0x000000010300780c */
/* 0x000fc80004701670 */
/*0230*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fc80008706670 */
/*0240*/ ISETP.GE.OR P0, PT, R0, UR5, P0 ; /* 0x0000000500007c0c */
/* 0x000fda0008706670 */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0260*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0270*/ IADD3 R10, R4.reuse, c[0x0][0x17c], RZ ; /* 0x00005f00040a7a10 */
/* 0x040fe20007ffe0ff */
/*0280*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0290*/ IADD3 R8, R4, -c[0x0][0x17c], RZ ; /* 0x80005f0004087a10 */
/* 0x000fce0007ffe0ff */
/*02a0*/ IMAD.WIDE R10, R10, R5, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e0205 */
/*02b0*/ IMAD.WIDE R8, R8, R5.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe400078e0205 */
/*02c0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ IMAD.WIDE R14, R4.reuse, R5.reuse, c[0x0][0x168] ; /* 0x00005a00040e7625 */
/* 0x0c0fe400078e0205 */
/*02e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*02f0*/ LDG.E.64 R16, [R14.64+-0x8] ; /* 0xfffff8040e107981 */
/* 0x000ee8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R14.64+0x8] ; /* 0x000008040e127981 */
/* 0x000f22000c1e1b00 */
/*0310*/ IMAD.WIDE R6, R4, R5, c[0x0][0x170] ; /* 0x00005c0004067625 */
/* 0x000fc600078e0205 */
/*0320*/ LDG.E.64 R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x000f68000c1e1b00 */
/*0330*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1b00 */
/*0340*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0350*/ LDG.E.64 R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000f62000c1e1b00 */
/*0360*/ DADD R12, R10, R8 ; /* 0x000000000a0c7229 */
/* 0x004ecc0000000008 */
/*0370*/ DADD R12, R12, R16 ; /* 0x000000000c0c7229 */
/* 0x008f0c0000000010 */
/*0380*/ DADD R12, R12, R18 ; /* 0x000000000c0c7229 */
/* 0x010f4c0000000012 */
/*0390*/ DFMA R12, R2, -4, R12 ; /* 0xc0100000020c782b */
/* 0x020e0c000000000c */
/*03a0*/ DMUL R12, R12, R6 ; /* 0x000000060c0c7228 */
/* 0x001e0c0000000000 */
/*03b0*/ DFMA R12, R2, 2, R12 ; /* 0x40000000020c782b */
/* 0x001e0c000000000c */
/*03c0*/ DADD R12, R12, -R20 ; /* 0x000000000c0c7229 */
/* 0x001e0e0000000814 */
/*03d0*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x001fe2000c101b04 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ BRA 0x3f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11update_corePdS_S_ii
.globl _Z11update_corePdS_S_ii
.p2align 8
.type _Z11update_corePdS_S_ii,@function
_Z11update_corePdS_S_ii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s9, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s4, s9, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
v_cvt_f32_u32_e32 v1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_add_i32 s2, s8, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
s_add_i32 s3, s9, -1
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v2
v_mul_lo_u32 v2, v0, s9
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v2
v_min_i32_e32 v3, v0, v2
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, 0, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_subrev_nc_u32_e32 v2, s9, v1
v_add_nc_u32_e32 v4, s9, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 3, v[1:2]
v_add_co_u32 v0, vcc_lo, s6, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s0, v8
s_clause 0x1
global_load_b64 v[10:11], v[0:1], off offset:-8
global_load_b128 v[0:3], v[0:1], off
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[12:13], v[12:13], off
global_load_b64 v[14:15], v[8:9], off
s_waitcnt vmcnt(4)
v_add_f64 v[4:5], v[6:7], v[4:5]
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[10:11]
s_waitcnt vmcnt(2)
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[0:1], -4.0, v[2:3]
s_waitcnt vmcnt(1)
v_mul_f64 v[2:3], v[12:13], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], 2.0, v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], -v[14:15]
global_store_b64 v[8:9], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11update_corePdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11update_corePdS_S_ii, .Lfunc_end0-_Z11update_corePdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10update_srcPddi
.globl _Z10update_srcPddi
.p2align 8
.type _Z10update_srcPddi,@function
_Z10update_srcPddi:
s_load_b32 s2, s[0:1], 0x24
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[4:5], 3
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], s[4:5], s[2:3]
global_store_b64 v2, v[0:1], s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10update_srcPddi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10update_srcPddi, .Lfunc_end1-_Z10update_srcPddi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11update_corePdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11update_corePdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10update_srcPddi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10update_srcPddi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011fb9f_00000000-6_pycuda_wave_fd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii
.type _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii, @function
_Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11update_corePdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii, .-_Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii
.globl _Z11update_corePdS_S_ii
.type _Z11update_corePdS_S_ii, @function
_Z11update_corePdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11update_corePdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11update_corePdS_S_ii, .-_Z11update_corePdS_S_ii
.globl _Z32__device_stub__Z10update_srcPddiPddi
.type _Z32__device_stub__Z10update_srcPddiPddi, @function
_Z32__device_stub__Z10update_srcPddiPddi:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10update_srcPddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z32__device_stub__Z10update_srcPddiPddi, .-_Z32__device_stub__Z10update_srcPddiPddi
.globl _Z10update_srcPddi
.type _Z10update_srcPddi, @function
_Z10update_srcPddi:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10update_srcPddiPddi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z10update_srcPddi, .-_Z10update_srcPddi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10update_srcPddi"
.LC1:
.string "_Z11update_corePdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10update_srcPddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11update_corePdS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pycuda_wave_fd.hip"
.globl _Z26__device_stub__update_corePdS_S_ii # -- Begin function _Z26__device_stub__update_corePdS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__update_corePdS_S_ii,@function
_Z26__device_stub__update_corePdS_S_ii: # @_Z26__device_stub__update_corePdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11update_corePdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__update_corePdS_S_ii, .Lfunc_end0-_Z26__device_stub__update_corePdS_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__update_srcPddi # -- Begin function _Z25__device_stub__update_srcPddi
.p2align 4, 0x90
.type _Z25__device_stub__update_srcPddi,@function
_Z25__device_stub__update_srcPddi: # @_Z25__device_stub__update_srcPddi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10update_srcPddi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__update_srcPddi, .Lfunc_end1-_Z25__device_stub__update_srcPddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11update_corePdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10update_srcPddi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11update_corePdS_S_ii,@object # @_Z11update_corePdS_S_ii
.section .rodata,"a",@progbits
.globl _Z11update_corePdS_S_ii
.p2align 3, 0x0
_Z11update_corePdS_S_ii:
.quad _Z26__device_stub__update_corePdS_S_ii
.size _Z11update_corePdS_S_ii, 8
.type _Z10update_srcPddi,@object # @_Z10update_srcPddi
.globl _Z10update_srcPddi
.p2align 3, 0x0
_Z10update_srcPddi:
.quad _Z25__device_stub__update_srcPddi
.size _Z10update_srcPddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11update_corePdS_S_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10update_srcPddi"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__update_corePdS_S_ii
.addrsig_sym _Z25__device_stub__update_srcPddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11update_corePdS_S_ii
.addrsig_sym _Z10update_srcPddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | # include <cuda.h>
# include <cuda_runtime.h>
# include <vector_types.h>
# include <device_launch_parameters.h>
# include <cstdio>
# ifdef WIN32
# include <time.h>
# else
# include <sys/time.h>
# endif
__global__ void iterMandel(int niterMax, int n, int* mandel )
{
int t_x, t_y, iter;
float step, zr;
float2 z0,c0;
iter = 0;
t_x = threadIdx.x+blockIdx.x*blockDim.x;
t_y = threadIdx.y+blockIdx.y*blockDim.y;
if ((t_x<n) && (t_y<n)) {
step = 2.5f/(n-1.f);
c0.x = -2.00 + step*t_x;
c0.y = -1.25 + step*t_y;
z0 = c0;
while ((z0.x*z0.x+z0.y*z0.y < 4.f)&&(iter<niterMax)) {
iter += 1;
zr = z0.x*z0.x-z0.y*z0.y+c0.x;
z0.y = 2.f*z0.x*z0.y+c0.y;
z0.x = zr;
}
mandel[t_x+t_y*n] = iter;
}
}
/* Petite routine renvoyant un instant
en seconde. En faisant la différence
entre deux instants, on peut mesure le temps
pris par une routine.
La précision est de l'ordre de la micro-seconde.
*/
float topChrono()
{
# ifdef WIN32
clock_t chrono;
chrono = clock();
return ((float)chrono)/CLOCKS_PER_SEC;
# else
struct timeval tv;
gettimeofday(&tv,NULL);
return tv.tv_sec+1.E-6*tv.tv_usec;
# endif
}
/* Calcul les coordonnees des sommets de la grille */
void compGrid(int n, float*& xh, float*& yh)
{
xh = new float[n];
yh = new float[n];
float step = 2.5/(n-1.);
for (int i = 0; i < n; i++) {
xh[i] = -2.+i*step;
yh[i] = -1.25+i*step;
}
}
/* Sauve l'ensemble de mandelbrot au format Gnuplot
*/
void saveMandel(int n, const float* xh, const float* yh,
const int* mandel)
{
FILE* fich = fopen("Mandel.dat", "w");
for (int j = 0; j < n; j++) {
for (int i = 0; i < n; i++) {
fprintf(fich,"%f\t%f\t%d\n",yh[i], xh[j], mandel[i*n+j]);
}
fprintf(fich, "\n");
}
fclose(fich);
}
int main(int nargc, char* argv[])
{
float t1,t2;
float *xh, *yh;
int n = 1280;
int maxIter = 1000;
int* gmandel, *cmandel;
cudaEvent_t start, stop;
float time;
if (nargc > 1) n = atoi(argv[1]);
if (nargc > 2) maxIter = atoi(argv[2]);
compGrid(n,xh,yh);
cudaMalloc((void**)&gmandel, n*n*sizeof(int));
cmandel = new int[n*n];
cudaEventCreate(&start); cudaEventCreate(&stop);
dim3 blockDim(16,16);
dim3 gridDim((n+15)/16, (n+15)/16);
cudaEventRecord( start, 0 );
iterMandel<<<gridDim,blockDim>>>(maxIter, n, gmandel);
cudaMemcpy(cmandel, gmandel, n*n*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); cudaEventSynchronize( stop );
cudaFree(gmandel);
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start ); cudaEventDestroy( stop );
printf("Temps de calcul du Bouddha : %f secondes\n",time/1000.);
saveMandel(n,xh,yh,cmandel);
delete [] cmandel;
delete [] xh;
delete [] yh;
return EXIT_SUCCESS;
}; | code for sm_80
Function : _Z10iterMandeliiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R2, c[0x0][0x164] ; /* 0x0000590000027b06 */
/* 0x000e220000201400 */
/*00b0*/ UMOV UR4, 0x40200000 ; /* 0x4020000000047882 */
/* 0x000fe40000000000 */
/*00c0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe4000f8e00ff */
/*00d0*/ FADD R4, R2, -1 ; /* 0xbf80000002047421 */
/* 0x001fc80000000000 */
/*00e0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e300000001000 */
/*00f0*/ FCHK P0, R7, R4 ; /* 0x0000000407007302 */
/* 0x000e620000000000 */
/*0100*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*0110*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc80000000005 */
/*0120*/ FFMA R5, R2, 2.5, RZ ; /* 0x4020000002057823 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R4, R5, 2.5 ; /* 0x4020000004067423 */
/* 0x000fc80000000105 */
/*0140*/ FFMA R2, R2, R6, R5 ; /* 0x0000000602027223 */
/* 0x000fe20000000005 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0160*/ MOV R2, 0x180 ; /* 0x0000018000027802 */
/* 0x000fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x3b0 ; /* 0x0000023000007944 */
/* 0x000fea0003c00000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0007 */
/*0190*/ I2F R5, R3 ; /* 0x0000000300057306 */
/* 0x0000620000201400 */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ BSSY B0, 0x390 ; /* 0x000001c000007945 */
/* 0x000fea0003800000 */
/*01d0*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x000ea20000201400 */
/*01e0*/ IMAD R3, R0, c[0x0][0x164], R3 ; /* 0x0000590000037a24 */
/* 0x001fc400078e0203 */
/*01f0*/ FFMA R9, R5, R2, -2 ; /* 0xc000000005097423 */
/* 0x002fc80000000002 */
/*0200*/ FMUL R4, R9, R9 ; /* 0x0000000909047220 */
/* 0x000fe40000400000 */
/*0210*/ FFMA R8, R7, R2, -1.25 ; /* 0xbfa0000007087423 */
/* 0x004fe40000000002 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0230*/ FMUL R5, R8, R8 ; /* 0x0000000808057220 */
/* 0x000fc80000400000 */
/*0240*/ FADD R2, R4, R5 ; /* 0x0000000504027221 */
/* 0x000fca0000000000 */
/*0250*/ FSETP.GEU.AND P0, PT, R2, 4, PT ; /* 0x408000000200780b */
/* 0x000fe20003f0e000 */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.LT.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fe20000701670 */
/*0280*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fd800078e0202 */
/*0290*/ @P0 BRA 0x380 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*02a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*02b0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0009 */
/*02d0*/ FADD R4, -R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe20000000100 */
/*02e0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ FADD R5, R6, R6 ; /* 0x0000000606057221 */
/* 0x000fe40000000000 */
/*0300*/ FADD R6, R9, R4 ; /* 0x0000000409067221 */
/* 0x000fe20000000000 */
/*0310*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x160], PT ; /* 0x0000580007007a0c */
/* 0x000fe20003f06270 */
/*0320*/ FFMA R0, R5, R0, R8 ; /* 0x0000000005007223 */
/* 0x000fe40000000008 */
/*0330*/ FMUL R4, R6, R6 ; /* 0x0000000606047220 */
/* 0x000fc40000400000 */
/*0340*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x000fc80000400000 */
/*0350*/ FADD R10, R4, R5 ; /* 0x00000005040a7221 */
/* 0x000fca0000000000 */
/*0360*/ FSETP.LT.AND P1, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f21000 */
/*0370*/ @!P0 BRA P1, 0x2d0 ; /* 0xffffff5000008947 */
/* 0x000fea000083ffff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*03c0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0004 */
/*03d0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*03e0*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ; /* 0x000000fd0800780c */
/* 0x000fda0003f04070 */
/*0400*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0410*/ @!P0 BRA 0x510 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0430*/ @P0 BRA 0x8e0 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*0440*/ MOV R6, 0x40200000 ; /* 0x4020000000067802 */
/* 0x000fc80000000f00 */
/*0450*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0460*/ @!P0 BRA 0x8c0 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1d200 */
/*0480*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0490*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04a0*/ @P0 BRA 0x8a0 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*04b0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*04c0*/ @!P0 BRA 0x870 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f06270 */
/*04e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd800078e00ff */
/*04f0*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe200000000ff */
/*0500*/ @!P0 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006068810 */
/* 0x000fe40007ffe0ff */
/*0510*/ LEA R4, R5, 0xc0800000, 0x17 ; /* 0xc080000005047811 */
/* 0x000fe200078eb8ff */
/*0520*/ UMOV UR4, 0x40200000 ; /* 0x4020000000047882 */
/* 0x000fe20000000000 */
/*0530*/ IADD3 R5, R6, 0x80, -R5 ; /* 0x0000008006057810 */
/* 0x000fe20007ffe805 */
/*0540*/ UIADD3 UR4, UR4, -0x800000, URZ ; /* 0xff80000004047890 */
/* 0x000fe4000fffe03f */
/*0550*/ IMAD.IADD R4, R7, 0x1, -R4 ; /* 0x0000000107047824 */
/* 0x000fc800078e0a04 */
/*0560*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000e220000001000 */
/*0570*/ FADD.FTZ R8, -R4, -RZ ; /* 0x800000ff04087221 */
/* 0x000fc80000010100 */
/*0580*/ FFMA R10, R7, R8, 1 ; /* 0x3f800000070a7423 */
/* 0x001fc80000000008 */
/*0590*/ FFMA R9, R7, R10, R7 ; /* 0x0000000a07097223 */
/* 0x000fc80000000007 */
/*05a0*/ FFMA R7, R9, UR4, RZ ; /* 0x0000000409077c23 */
/* 0x000fc800080000ff */
/*05b0*/ FFMA R10, R8, R7, UR4 ; /* 0x00000004080a7e23 */
/* 0x000fc80008000007 */
/*05c0*/ FFMA R10, R9, R10, R7 ; /* 0x0000000a090a7223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R8, R8, R10, UR4 ; /* 0x0000000408087e23 */
/* 0x000fc8000800000a */
/*05e0*/ FFMA R7, R9, R8, R10 ; /* 0x0000000809077223 */
/* 0x000fca000000000a */
/*05f0*/ SHF.R.U32.HI R4, RZ, 0x17, R7 ; /* 0x00000017ff047819 */
/* 0x000fc80000011607 */
/*0600*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0610*/ IMAD.IADD R11, R4, 0x1, R5 ; /* 0x00000001040b7824 */
/* 0x000fca00078e0205 */
/*0620*/ IADD3 R4, R11, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x000fc80007ffe0ff */
/*0630*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0640*/ @!P0 BRA 0x850 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0660*/ @P0 BRA 0x820 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0680*/ @P0 BRA 0x8f0 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*06a0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*06b0*/ @!P0 BRA 0x8f0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FFMA.RZ R4, R9, R8.reuse, R10.reuse ; /* 0x0000000809047223 */
/* 0x180fe2000000c00a */
/*06d0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f45270 */
/*06e0*/ FFMA.RM R5, R9, R8.reuse, R10.reuse ; /* 0x0000000809057223 */
/* 0x180fe2000000400a */
/*06f0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f25270 */
/*0700*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0710*/ FFMA.RP R4, R9, R8, R10 ; /* 0x0000000809047223 */
/* 0x000fe2000000800a */
/*0720*/ IADD3 R9, R11, 0x20, RZ ; /* 0x000000200b097810 */
/* 0x000fe20007ffe0ff */
/*0730*/ IMAD.MOV R8, RZ, RZ, -R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a0b */
/*0740*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0750*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0760*/ SHF.L.U32 R9, R6, R9, RZ ; /* 0x0000000906097219 */
/* 0x000fe400000006ff */
/*0770*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0780*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0790*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*07a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*07b0*/ SHF.R.U32.HI R9, RZ, 0x1, R5 ; /* 0x00000001ff097819 */
/* 0x000fc40000011605 */
/*07c0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*07d0*/ LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef809 */
/*07e0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fc800078ec0ff */
/*07f0*/ IADD3 R4, R9, R4, RZ ; /* 0x0000000409047210 */
/* 0x000fc80007ffe0ff */
/*0800*/ LOP3.LUT R7, R4, R7, RZ, 0xfc, !PT ; /* 0x0000000704077212 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x8f0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0830*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x8f0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0850*/ IMAD R7, R5, 0x800000, R7 ; /* 0x0080000005077824 */
/* 0x000fe200078e0207 */
/*0860*/ BRA 0x8f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078e4806 */
/*0880*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0890*/ BRA 0x8f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08a0*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fe200078e4806 */
/*08b0*/ BRA 0x8f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*08c0*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*08d0*/ BRA 0x8f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08e0*/ FADD.FTZ R7, R4, 2.5 ; /* 0x4020000004077421 */
/* 0x000fe40000010000 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0900*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0910*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6e004007950 */
/* 0x000fea0003c3ffff */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | # include <cuda.h>
# include <cuda_runtime.h>
# include <vector_types.h>
# include <device_launch_parameters.h>
# include <cstdio>
# ifdef WIN32
# include <time.h>
# else
# include <sys/time.h>
# endif
__global__ void iterMandel(int niterMax, int n, int* mandel )
{
int t_x, t_y, iter;
float step, zr;
float2 z0,c0;
iter = 0;
t_x = threadIdx.x+blockIdx.x*blockDim.x;
t_y = threadIdx.y+blockIdx.y*blockDim.y;
if ((t_x<n) && (t_y<n)) {
step = 2.5f/(n-1.f);
c0.x = -2.00 + step*t_x;
c0.y = -1.25 + step*t_y;
z0 = c0;
while ((z0.x*z0.x+z0.y*z0.y < 4.f)&&(iter<niterMax)) {
iter += 1;
zr = z0.x*z0.x-z0.y*z0.y+c0.x;
z0.y = 2.f*z0.x*z0.y+c0.y;
z0.x = zr;
}
mandel[t_x+t_y*n] = iter;
}
}
/* Petite routine renvoyant un instant
en seconde. En faisant la différence
entre deux instants, on peut mesure le temps
pris par une routine.
La précision est de l'ordre de la micro-seconde.
*/
float topChrono()
{
# ifdef WIN32
clock_t chrono;
chrono = clock();
return ((float)chrono)/CLOCKS_PER_SEC;
# else
struct timeval tv;
gettimeofday(&tv,NULL);
return tv.tv_sec+1.E-6*tv.tv_usec;
# endif
}
/* Calcul les coordonnees des sommets de la grille */
void compGrid(int n, float*& xh, float*& yh)
{
xh = new float[n];
yh = new float[n];
float step = 2.5/(n-1.);
for (int i = 0; i < n; i++) {
xh[i] = -2.+i*step;
yh[i] = -1.25+i*step;
}
}
/* Sauve l'ensemble de mandelbrot au format Gnuplot
*/
void saveMandel(int n, const float* xh, const float* yh,
const int* mandel)
{
FILE* fich = fopen("Mandel.dat", "w");
for (int j = 0; j < n; j++) {
for (int i = 0; i < n; i++) {
fprintf(fich,"%f\t%f\t%d\n",yh[i], xh[j], mandel[i*n+j]);
}
fprintf(fich, "\n");
}
fclose(fich);
}
int main(int nargc, char* argv[])
{
float t1,t2;
float *xh, *yh;
int n = 1280;
int maxIter = 1000;
int* gmandel, *cmandel;
cudaEvent_t start, stop;
float time;
if (nargc > 1) n = atoi(argv[1]);
if (nargc > 2) maxIter = atoi(argv[2]);
compGrid(n,xh,yh);
cudaMalloc((void**)&gmandel, n*n*sizeof(int));
cmandel = new int[n*n];
cudaEventCreate(&start); cudaEventCreate(&stop);
dim3 blockDim(16,16);
dim3 gridDim((n+15)/16, (n+15)/16);
cudaEventRecord( start, 0 );
iterMandel<<<gridDim,blockDim>>>(maxIter, n, gmandel);
cudaMemcpy(cmandel, gmandel, n*n*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); cudaEventSynchronize( stop );
cudaFree(gmandel);
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start ); cudaEventDestroy( stop );
printf("Temps de calcul du Bouddha : %f secondes\n",time/1000.);
saveMandel(n,xh,yh,cmandel);
delete [] cmandel;
delete [] xh;
delete [] yh;
return EXIT_SUCCESS;
}; | .file "tmpxft_000e54c5_00000000-6_MandelGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9topChronov
.type _Z9topChronov, @function
_Z9topChronov:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
cvtsd2ss %xmm0, %xmm0
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9topChronov, .-_Z9topChronov
.globl _Z8compGridiRPfS0_
.type _Z8compGridiRPfS0_, @function
_Z8compGridiRPfS0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movslq %edi, %r12
movabsq $2305843009213693950, %rax
cmpq %r12, %rax
jb .L8
movl %edi, %r13d
movq %rsi, %rbp
movq %rdx, %rbx
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, 0(%rbp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, (%rbx)
pxor %xmm0, %xmm0
cvtsi2sdl %r13d, %xmm0
subsd .LC1(%rip), %xmm0
movsd .LC2(%rip), %xmm2
divsd %xmm0, %xmm2
cvtsd2ss %xmm2, %xmm2
movl $0, %eax
movss .LC3(%rip), %xmm4
movss .LC4(%rip), %xmm3
testl %r13d, %r13d
jle .L7
.L9:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm2, %xmm0
movq 0(%rbp), %rdx
movaps %xmm0, %xmm1
subss %xmm4, %xmm1
movss %xmm1, (%rdx,%rax,4)
movq (%rbx), %rdx
subss %xmm3, %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq %rax, %r12
jne .L9
.L7:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE2058:
.size _Z8compGridiRPfS0_, .-_Z8compGridiRPfS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "w"
.LC6:
.string "Mandel.dat"
.LC7:
.string "%f\t%f\t%d\n"
.LC8:
.string "\n"
.text
.globl _Z10saveMandeliPKfS0_PKi
.type _Z10saveMandeliPKfS0_PKi, @function
_Z10saveMandeliPKfS0_PKi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movq %rsi, %r12
movq %rdx, %r15
movq %rdx, 8(%rsp)
movq %rcx, 16(%rsp)
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L16
movslq %ebx, %rax
leaq 0(,%rax,4), %r14
addq %r14, %r15
movq $0, (%rsp)
movq %rax, 24(%rsp)
.L17:
movq 16(%rsp), %rax
movq (%rsp), %rsi
leaq (%rax,%rsi,4), %rbp
movq 8(%rsp), %rbx
.L18:
movl 0(%rbp), %ecx
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12), %xmm1
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $2, %eax
call __fprintf_chk@PLT
addq %r14, %rbp
addq $4, %rbx
cmpq %r15, %rbx
jne .L18
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, (%rsp)
movq (%rsp), %rax
addq $4, %r12
movq 24(%rsp), %rdx
cmpq %rdx, %rax
jne .L17
.L16:
movq %r13, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10saveMandeliPKfS0_PKi, .-_Z10saveMandeliPKfS0_PKi
.globl _Z32__device_stub__Z10iterMandeliiPiiiPi
.type _Z32__device_stub__Z10iterMandeliiPiiiPi, @function
_Z32__device_stub__Z10iterMandeliiPiiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10iterMandeliiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z10iterMandeliiPiiiPi, .-_Z32__device_stub__Z10iterMandeliiPiiiPi
.globl _Z10iterMandeliiPi
.type _Z10iterMandeliiPi, @function
_Z10iterMandeliiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10iterMandeliiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10iterMandeliiPi, .-_Z10iterMandeliiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "Temps de calcul du Bouddha : %f secondes\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1280, %ebx
movl $1000, %r13d
cmpl $1, %edi
jg .L39
.L31:
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rsi
movl %ebx, %edi
call _Z8compGridiRPfS0_
movl %ebx, %ebp
imull %ebx, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %r12
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $1, 56(%rsp)
leal 30(%rbx), %eax
movl %ebx, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 60(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L32:
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rbp
movq 8(%rsp), %r13
movq %r12, %rcx
movq %rbp, %rdx
movq %r13, %rsi
movl %ebx, %edi
call _Z10saveMandeliPKfS0_PKi
movq %r12, %rdi
call _ZdaPv@PLT
testq %r13, %r13
je .L33
movq %r13, %rdi
call _ZdaPv@PLT
.L33:
testq %rbp, %rbp
je .L34
movq %rbp, %rdi
call _ZdaPv@PLT
.L34:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %edi, %ebp
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
cmpl $2, %ebp
jle .L31
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L31
.L40:
movq 24(%rsp), %rdx
movl %ebx, %esi
movl %r13d, %edi
call _Z32__device_stub__Z10iterMandeliiPiiiPi
jmp .L32
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z10iterMandeliiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10iterMandeliiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1074003968
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1067450368
.section .rodata.cst8
.align 8
.LC9:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | # include <cuda.h>
# include <cuda_runtime.h>
# include <vector_types.h>
# include <device_launch_parameters.h>
# include <cstdio>
# ifdef WIN32
# include <time.h>
# else
# include <sys/time.h>
# endif
__global__ void iterMandel(int niterMax, int n, int* mandel )
{
int t_x, t_y, iter;
float step, zr;
float2 z0,c0;
iter = 0;
t_x = threadIdx.x+blockIdx.x*blockDim.x;
t_y = threadIdx.y+blockIdx.y*blockDim.y;
if ((t_x<n) && (t_y<n)) {
step = 2.5f/(n-1.f);
c0.x = -2.00 + step*t_x;
c0.y = -1.25 + step*t_y;
z0 = c0;
while ((z0.x*z0.x+z0.y*z0.y < 4.f)&&(iter<niterMax)) {
iter += 1;
zr = z0.x*z0.x-z0.y*z0.y+c0.x;
z0.y = 2.f*z0.x*z0.y+c0.y;
z0.x = zr;
}
mandel[t_x+t_y*n] = iter;
}
}
/* Petite routine renvoyant un instant
en seconde. En faisant la différence
entre deux instants, on peut mesure le temps
pris par une routine.
La précision est de l'ordre de la micro-seconde.
*/
float topChrono()
{
# ifdef WIN32
clock_t chrono;
chrono = clock();
return ((float)chrono)/CLOCKS_PER_SEC;
# else
struct timeval tv;
gettimeofday(&tv,NULL);
return tv.tv_sec+1.E-6*tv.tv_usec;
# endif
}
/* Calcul les coordonnees des sommets de la grille */
void compGrid(int n, float*& xh, float*& yh)
{
xh = new float[n];
yh = new float[n];
float step = 2.5/(n-1.);
for (int i = 0; i < n; i++) {
xh[i] = -2.+i*step;
yh[i] = -1.25+i*step;
}
}
/* Sauve l'ensemble de mandelbrot au format Gnuplot
*/
void saveMandel(int n, const float* xh, const float* yh,
const int* mandel)
{
FILE* fich = fopen("Mandel.dat", "w");
for (int j = 0; j < n; j++) {
for (int i = 0; i < n; i++) {
fprintf(fich,"%f\t%f\t%d\n",yh[i], xh[j], mandel[i*n+j]);
}
fprintf(fich, "\n");
}
fclose(fich);
}
int main(int nargc, char* argv[])
{
float t1,t2;
float *xh, *yh;
int n = 1280;
int maxIter = 1000;
int* gmandel, *cmandel;
cudaEvent_t start, stop;
float time;
if (nargc > 1) n = atoi(argv[1]);
if (nargc > 2) maxIter = atoi(argv[2]);
compGrid(n,xh,yh);
cudaMalloc((void**)&gmandel, n*n*sizeof(int));
cmandel = new int[n*n];
cudaEventCreate(&start); cudaEventCreate(&stop);
dim3 blockDim(16,16);
dim3 gridDim((n+15)/16, (n+15)/16);
cudaEventRecord( start, 0 );
iterMandel<<<gridDim,blockDim>>>(maxIter, n, gmandel);
cudaMemcpy(cmandel, gmandel, n*n*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord( stop, 0 ); cudaEventSynchronize( stop );
cudaFree(gmandel);
cudaEventElapsedTime( &time, start, stop );
cudaEventDestroy( start ); cudaEventDestroy( stop );
printf("Temps de calcul du Bouddha : %f secondes\n",time/1000.);
saveMandel(n,xh,yh,cmandel);
delete [] cmandel;
delete [] xh;
delete [] yh;
return EXIT_SUCCESS;
}; | # include <hip/hip_runtime.h>
# include <hip/hip_vector_types.h>
# include <cstdio>
# ifdef WIN32
# include <time.h>
# else
# include <sys/time.h>
# endif
__global__ void iterMandel(int niterMax, int n, int* mandel )
{
int t_x, t_y, iter;
float step, zr;
float2 z0,c0;
iter = 0;
t_x = threadIdx.x+blockIdx.x*blockDim.x;
t_y = threadIdx.y+blockIdx.y*blockDim.y;
if ((t_x<n) && (t_y<n)) {
step = 2.5f/(n-1.f);
c0.x = -2.00 + step*t_x;
c0.y = -1.25 + step*t_y;
z0 = c0;
while ((z0.x*z0.x+z0.y*z0.y < 4.f)&&(iter<niterMax)) {
iter += 1;
zr = z0.x*z0.x-z0.y*z0.y+c0.x;
z0.y = 2.f*z0.x*z0.y+c0.y;
z0.x = zr;
}
mandel[t_x+t_y*n] = iter;
}
}
/* Petite routine renvoyant un instant
en seconde. En faisant la différence
entre deux instants, on peut mesure le temps
pris par une routine.
La précision est de l'ordre de la micro-seconde.
*/
float topChrono()
{
# ifdef WIN32
clock_t chrono;
chrono = clock();
return ((float)chrono)/CLOCKS_PER_SEC;
# else
struct timeval tv;
gettimeofday(&tv,NULL);
return tv.tv_sec+1.E-6*tv.tv_usec;
# endif
}
/* Calcul les coordonnees des sommets de la grille */
void compGrid(int n, float*& xh, float*& yh)
{
xh = new float[n];
yh = new float[n];
float step = 2.5/(n-1.);
for (int i = 0; i < n; i++) {
xh[i] = -2.+i*step;
yh[i] = -1.25+i*step;
}
}
/* Sauve l'ensemble de mandelbrot au format Gnuplot
*/
void saveMandel(int n, const float* xh, const float* yh,
const int* mandel)
{
FILE* fich = fopen("Mandel.dat", "w");
for (int j = 0; j < n; j++) {
for (int i = 0; i < n; i++) {
fprintf(fich,"%f\t%f\t%d\n",yh[i], xh[j], mandel[i*n+j]);
}
fprintf(fich, "\n");
}
fclose(fich);
}
int main(int nargc, char* argv[])
{
float t1,t2;
float *xh, *yh;
int n = 1280;
int maxIter = 1000;
int* gmandel, *cmandel;
hipEvent_t start, stop;
float time;
if (nargc > 1) n = atoi(argv[1]);
if (nargc > 2) maxIter = atoi(argv[2]);
compGrid(n,xh,yh);
hipMalloc((void**)&gmandel, n*n*sizeof(int));
cmandel = new int[n*n];
hipEventCreate(&start); hipEventCreate(&stop);
dim3 blockDim(16,16);
dim3 gridDim((n+15)/16, (n+15)/16);
hipEventRecord( start, 0 );
iterMandel<<<gridDim,blockDim>>>(maxIter, n, gmandel);
hipMemcpy(cmandel, gmandel, n*n*sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); hipEventSynchronize( stop );
hipFree(gmandel);
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start ); hipEventDestroy( stop );
printf("Temps de calcul du Bouddha : %f secondes\n",time/1000.);
saveMandel(n,xh,yh,cmandel);
delete [] cmandel;
delete [] xh;
delete [] yh;
return EXIT_SUCCESS;
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | # include <hip/hip_runtime.h>
# include <hip/hip_vector_types.h>
# include <cstdio>
# ifdef WIN32
# include <time.h>
# else
# include <sys/time.h>
# endif
__global__ void iterMandel(int niterMax, int n, int* mandel )
{
int t_x, t_y, iter;
float step, zr;
float2 z0,c0;
iter = 0;
t_x = threadIdx.x+blockIdx.x*blockDim.x;
t_y = threadIdx.y+blockIdx.y*blockDim.y;
if ((t_x<n) && (t_y<n)) {
step = 2.5f/(n-1.f);
c0.x = -2.00 + step*t_x;
c0.y = -1.25 + step*t_y;
z0 = c0;
while ((z0.x*z0.x+z0.y*z0.y < 4.f)&&(iter<niterMax)) {
iter += 1;
zr = z0.x*z0.x-z0.y*z0.y+c0.x;
z0.y = 2.f*z0.x*z0.y+c0.y;
z0.x = zr;
}
mandel[t_x+t_y*n] = iter;
}
}
/* Petite routine renvoyant un instant
en seconde. En faisant la différence
entre deux instants, on peut mesure le temps
pris par une routine.
La précision est de l'ordre de la micro-seconde.
*/
float topChrono()
{
# ifdef WIN32
clock_t chrono;
chrono = clock();
return ((float)chrono)/CLOCKS_PER_SEC;
# else
struct timeval tv;
gettimeofday(&tv,NULL);
return tv.tv_sec+1.E-6*tv.tv_usec;
# endif
}
/* Calcul les coordonnees des sommets de la grille */
void compGrid(int n, float*& xh, float*& yh)
{
xh = new float[n];
yh = new float[n];
float step = 2.5/(n-1.);
for (int i = 0; i < n; i++) {
xh[i] = -2.+i*step;
yh[i] = -1.25+i*step;
}
}
/* Sauve l'ensemble de mandelbrot au format Gnuplot
*/
void saveMandel(int n, const float* xh, const float* yh,
const int* mandel)
{
FILE* fich = fopen("Mandel.dat", "w");
for (int j = 0; j < n; j++) {
for (int i = 0; i < n; i++) {
fprintf(fich,"%f\t%f\t%d\n",yh[i], xh[j], mandel[i*n+j]);
}
fprintf(fich, "\n");
}
fclose(fich);
}
int main(int nargc, char* argv[])
{
float t1,t2;
float *xh, *yh;
int n = 1280;
int maxIter = 1000;
int* gmandel, *cmandel;
hipEvent_t start, stop;
float time;
if (nargc > 1) n = atoi(argv[1]);
if (nargc > 2) maxIter = atoi(argv[2]);
compGrid(n,xh,yh);
hipMalloc((void**)&gmandel, n*n*sizeof(int));
cmandel = new int[n*n];
hipEventCreate(&start); hipEventCreate(&stop);
dim3 blockDim(16,16);
dim3 gridDim((n+15)/16, (n+15)/16);
hipEventRecord( start, 0 );
iterMandel<<<gridDim,blockDim>>>(maxIter, n, gmandel);
hipMemcpy(cmandel, gmandel, n*n*sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); hipEventSynchronize( stop );
hipFree(gmandel);
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start ); hipEventDestroy( stop );
printf("Temps de calcul du Bouddha : %f secondes\n",time/1000.);
saveMandel(n,xh,yh,cmandel);
delete [] cmandel;
delete [] xh;
delete [] yh;
return EXIT_SUCCESS;
}; | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10iterMandeliiPi
.globl _Z10iterMandeliiPi
.p2align 8
.type _Z10iterMandeliiPi,@function
_Z10iterMandeliiPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x4
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
v_cvt_f32_i32_e32 v2, s2
s_load_b32 s3, s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, -1.0, v2
v_div_scale_f32 v3, null, v2, v2, 0x40200000
v_div_scale_f32 v6, vcc_lo, 0x40200000, v2, 0x40200000
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v4, v3
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s3, 0
s_cselect_b32 s4, -1, 0
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_cvt_f32_i32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v3, v2, 0x40200000
v_cvt_f32_i32_e32 v2, v1
v_fmaak_f32 v2, v3, v2, 0xbfa00000
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v3, v4, -2.0
v_mul_f32_e32 v4, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v3, v3, v4
v_cmp_gt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, 0
s_and_b32 s6, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_5
v_dual_mul_f32 v7, v3, v3 :: v_dual_mov_b32 v6, v2
v_mov_b32_e32 v8, v3
s_mov_b32 s6, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v8, v8
s_add_i32 s6, s6, 1
v_sub_f32_e32 v4, v7, v4
s_cmp_ge_i32 s6, s3
s_cselect_b32 s7, -1, 0
v_fma_f32 v6, v5, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v3, v4
v_dual_mul_f32 v4, v6, v6 :: v_dual_mul_f32 v7, v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v8, v8, v4
v_cmp_ngt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s6
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s7
s_or_b32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10iterMandeliiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10iterMandeliiPi, .Lfunc_end0-_Z10iterMandeliiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10iterMandeliiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10iterMandeliiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | # include <hip/hip_runtime.h>
# include <hip/hip_vector_types.h>
# include <cstdio>
# ifdef WIN32
# include <time.h>
# else
# include <sys/time.h>
# endif
__global__ void iterMandel(int niterMax, int n, int* mandel )
{
int t_x, t_y, iter;
float step, zr;
float2 z0,c0;
iter = 0;
t_x = threadIdx.x+blockIdx.x*blockDim.x;
t_y = threadIdx.y+blockIdx.y*blockDim.y;
if ((t_x<n) && (t_y<n)) {
step = 2.5f/(n-1.f);
c0.x = -2.00 + step*t_x;
c0.y = -1.25 + step*t_y;
z0 = c0;
while ((z0.x*z0.x+z0.y*z0.y < 4.f)&&(iter<niterMax)) {
iter += 1;
zr = z0.x*z0.x-z0.y*z0.y+c0.x;
z0.y = 2.f*z0.x*z0.y+c0.y;
z0.x = zr;
}
mandel[t_x+t_y*n] = iter;
}
}
/* Petite routine renvoyant un instant
en seconde. En faisant la différence
entre deux instants, on peut mesure le temps
pris par une routine.
La précision est de l'ordre de la micro-seconde.
*/
float topChrono()
{
# ifdef WIN32
clock_t chrono;
chrono = clock();
return ((float)chrono)/CLOCKS_PER_SEC;
# else
struct timeval tv;
gettimeofday(&tv,NULL);
return tv.tv_sec+1.E-6*tv.tv_usec;
# endif
}
/* Calcul les coordonnees des sommets de la grille */
void compGrid(int n, float*& xh, float*& yh)
{
xh = new float[n];
yh = new float[n];
float step = 2.5/(n-1.);
for (int i = 0; i < n; i++) {
xh[i] = -2.+i*step;
yh[i] = -1.25+i*step;
}
}
/* Sauve l'ensemble de mandelbrot au format Gnuplot
*/
void saveMandel(int n, const float* xh, const float* yh,
const int* mandel)
{
FILE* fich = fopen("Mandel.dat", "w");
for (int j = 0; j < n; j++) {
for (int i = 0; i < n; i++) {
fprintf(fich,"%f\t%f\t%d\n",yh[i], xh[j], mandel[i*n+j]);
}
fprintf(fich, "\n");
}
fclose(fich);
}
int main(int nargc, char* argv[])
{
float t1,t2;
float *xh, *yh;
int n = 1280;
int maxIter = 1000;
int* gmandel, *cmandel;
hipEvent_t start, stop;
float time;
if (nargc > 1) n = atoi(argv[1]);
if (nargc > 2) maxIter = atoi(argv[2]);
compGrid(n,xh,yh);
hipMalloc((void**)&gmandel, n*n*sizeof(int));
cmandel = new int[n*n];
hipEventCreate(&start); hipEventCreate(&stop);
dim3 blockDim(16,16);
dim3 gridDim((n+15)/16, (n+15)/16);
hipEventRecord( start, 0 );
iterMandel<<<gridDim,blockDim>>>(maxIter, n, gmandel);
hipMemcpy(cmandel, gmandel, n*n*sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord( stop, 0 ); hipEventSynchronize( stop );
hipFree(gmandel);
hipEventElapsedTime( &time, start, stop );
hipEventDestroy( start ); hipEventDestroy( stop );
printf("Temps de calcul du Bouddha : %f secondes\n",time/1000.);
saveMandel(n,xh,yh,cmandel);
delete [] cmandel;
delete [] xh;
delete [] yh;
return EXIT_SUCCESS;
}; | .text
.file "MandelGPU.hip"
.globl _Z25__device_stub__iterMandeliiPi # -- Begin function _Z25__device_stub__iterMandeliiPi
.p2align 4, 0x90
.type _Z25__device_stub__iterMandeliiPi,@function
_Z25__device_stub__iterMandeliiPi: # @_Z25__device_stub__iterMandeliiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10iterMandeliiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__iterMandeliiPi, .Lfunc_end0-_Z25__device_stub__iterMandeliiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9topChronov
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9topChronov
.p2align 4, 0x90
.type _Z9topChronov,@function
_Z9topChronov: # @_Z9topChronov
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9topChronov, .Lfunc_end1-_Z9topChronov
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8compGridiRPfS0_
.LCPI2_0:
.quad 0xbff0000000000000 # double -1
.LCPI2_1:
.quad 0x4004000000000000 # double 2.5
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0xc0000000 # float -2
.LCPI2_3:
.long 0xbfa00000 # float -1.25
.text
.globl _Z8compGridiRPfS0_
.p2align 4, 0x90
.type _Z8compGridiRPfS0_,@function
_Z8compGridiRPfS0_: # @_Z8compGridiRPfS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r14
movl %edi, %ebx
movslq %edi, %r13
leaq (,%r13,4), %rax
testl %r13d, %r13d
movq $-1, %r12
cmovnsq %rax, %r12
movq %r12, %rdi
callq _Znam
movq %rax, (%r14)
movq %r12, %rdi
callq _Znam
movq %rax, (%r15)
testl %r13d, %r13d
jle .LBB2_3
# %bb.1: # %.lr.ph
cvtsi2sd %ebx, %xmm0
addsd .LCPI2_0(%rip), %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq (%r14), %rcx
movl %ebx, %edx
xorl %esi, %esi
movss .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %esi, %xmm3
mulss %xmm0, %xmm3
movaps %xmm3, %xmm4
addss %xmm1, %xmm4
movss %xmm4, (%rcx,%rsi,4)
addss %xmm2, %xmm3
movss %xmm3, (%rax,%rsi,4)
incq %rsi
cmpq %rsi, %rdx
jne .LBB2_2
.LBB2_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8compGridiRPfS0_, .Lfunc_end2-_Z8compGridiRPfS0_
.cfi_endproc
# -- End function
.globl _Z10saveMandeliPKfS0_PKi # -- Begin function _Z10saveMandeliPKfS0_PKi
.p2align 4, 0x90
.type _Z10saveMandeliPKfS0_PKi,@function
_Z10saveMandeliPKfS0_PKi: # @_Z10saveMandeliPKfS0_PKi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r14
movq %rdx, 40(%rsp) # 8-byte Spill
movq %rsi, 32(%rsp) # 8-byte Spill
movl %edi, %ebp
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %ebp, %edx
leaq (,%rdx,4), %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
xorl %ecx, %ecx
movq %rdx, 8(%rsp) # 8-byte Spill
movq 40(%rsp), %r12 # 8-byte Reload
movq 32(%rsp), %rbp # 8-byte Reload
movq 24(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movq %rcx, 16(%rsp) # 8-byte Spill
movq %r14, 48(%rsp) # 8-byte Spill
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq 16(%rsp), %rax # 8-byte Reload
movss (%rbp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl (%r14), %edx
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $2, %al
callq fprintf
incq %r15
addq %r13, %r14
cmpq %r15, 8(%rsp) # 8-byte Folded Reload
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
movq 16(%rsp), %rsi # 8-byte Reload
incq %rsi
movq 48(%rsp), %r14 # 8-byte Reload
addq $4, %r14
movq 8(%rsp), %rcx # 8-byte Reload
cmpq %rcx, %rsi
movq %rsi, %rcx
jne .LBB3_2
.LBB3_5: # %._crit_edge20
movq %rbx, %rdi
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z10saveMandeliPKfS0_PKi, .Lfunc_end3-_Z10saveMandeliPKfS0_PKi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0xbff0000000000000 # double -1
.LCPI4_1:
.quad 0x4004000000000000 # double 2.5
.LCPI4_4:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_2:
.long 0xc0000000 # float -2
.LCPI4_3:
.long 0xbfa00000 # float -1.25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $1280, %r15d # imm = 0x500
cmpl $2, %edi
jl .LBB4_2
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB4_2:
movl $1000, %eax # imm = 0x3E8
cmpl $3, %ebp
jl .LBB4_4
# %bb.3:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB4_4:
movq %rax, (%rsp) # 8-byte Spill
movslq %r15d, %rbx
leaq (,%rbx,4), %rax
testl %ebx, %ebx
movq $-1, %r14
cmovnsq %rax, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %r12
movq %r14, %rdi
callq _Znam
movl %r15d, %r14d
testl %ebx, %ebx
jle .LBB4_7
# %bb.5: # %.lr.ph.i
cvtsi2sd %r15d, %xmm0
addsd .LCPI4_0(%rip), %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
xorl %ecx, %ecx
movss .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI4_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB4_6: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %ecx, %xmm3
mulss %xmm0, %xmm3
movaps %xmm3, %xmm4
addss %xmm1, %xmm4
movss %xmm4, (%r12,%rcx,4)
addss %xmm2, %xmm3
movss %xmm3, (%rax,%rcx,4)
incq %rcx
cmpq %rcx, %r14
jne .LBB4_6
.LBB4_7: # %_Z8compGridiRPfS0_.exit
movq %rax, 48(%rsp) # 8-byte Spill
movq %r12, 56(%rsp) # 8-byte Spill
movl %r15d, %ebp
imull %ebp, %ebp
shlq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %rbp, %rdi
callq _Znam
movq %rax, %rbx
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leal 15(%r15), %eax
leal 30(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
movq %rcx, %r13
shlq $32, %r13
orq %rcx, %r13
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8:
movq 24(%rsp), %rax
movq (%rsp), %rcx # 8-byte Reload
movl %ecx, 36(%rsp)
movl %r15d, 32(%rsp)
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 160(%rsp), %rax
movq %rax, 80(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10iterMandeliiPi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9:
movq 24(%rsp), %rsi
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_4(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbp
testl %r15d, %r15d
jle .LBB4_14
# %bb.10: # %.preheader.lr.ph.i
leaq (,%r14,4), %r15
xorl %ecx, %ecx
movq 40(%rsp), %r12 # 8-byte Reload
movq %r14, 96(%rsp) # 8-byte Spill
movq 48(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB4_11: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
movq %rcx, (%rsp) # 8-byte Spill
movq %r12, 104(%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq 56(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq (%rsp), %rax # 8-byte Reload
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl (%r12), %edx
movl $.L.str.2, %esi
movq %rbp, %rdi
movb $2, %al
callq fprintf
addq $4, %rbx
addq %r15, %r12
cmpq %rbx, %r15
jne .LBB4_12
# %bb.13: # %._crit_edge.i
# in Loop: Header=BB4_11 Depth=1
movl $10, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%rsp), %rcx # 8-byte Reload
incq %rcx
movq 104(%rsp), %r12 # 8-byte Reload
addq $4, %r12
movq 96(%rsp), %r14 # 8-byte Reload
cmpq %r14, %rcx
jne .LBB4_11
.LBB4_14: # %_Z10saveMandeliPKfS0_PKi.exit
movq %rbp, %rdi
callq fclose
movq 40(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq 56(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq 48(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10iterMandeliiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10iterMandeliiPi,@object # @_Z10iterMandeliiPi
.section .rodata,"a",@progbits
.globl _Z10iterMandeliiPi
.p2align 3, 0x0
_Z10iterMandeliiPi:
.quad _Z25__device_stub__iterMandeliiPi
.size _Z10iterMandeliiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mandel.dat"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f\t%f\t%d\n"
.size .L.str.2, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Temps de calcul du Bouddha : %f secondes\n"
.size .L.str.4, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10iterMandeliiPi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__iterMandeliiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10iterMandeliiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10iterMandeliiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ I2F R2, c[0x0][0x164] ; /* 0x0000590000027b06 */
/* 0x000e220000201400 */
/*00b0*/ UMOV UR4, 0x40200000 ; /* 0x4020000000047882 */
/* 0x000fe40000000000 */
/*00c0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe4000f8e00ff */
/*00d0*/ FADD R4, R2, -1 ; /* 0xbf80000002047421 */
/* 0x001fc80000000000 */
/*00e0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e300000001000 */
/*00f0*/ FCHK P0, R7, R4 ; /* 0x0000000407007302 */
/* 0x000e620000000000 */
/*0100*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*0110*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc80000000005 */
/*0120*/ FFMA R5, R2, 2.5, RZ ; /* 0x4020000002057823 */
/* 0x000fc800000000ff */
/*0130*/ FFMA R6, -R4, R5, 2.5 ; /* 0x4020000004067423 */
/* 0x000fc80000000105 */
/*0140*/ FFMA R2, R2, R6, R5 ; /* 0x0000000602027223 */
/* 0x000fe20000000005 */
/*0150*/ @!P0 BRA 0x190 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0160*/ MOV R2, 0x180 ; /* 0x0000018000027802 */
/* 0x000fe40000000f00 */
/*0170*/ CALL.REL.NOINC 0x3b0 ; /* 0x0000023000007944 */
/* 0x000fea0003c00000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0007 */
/*0190*/ I2F R5, R3 ; /* 0x0000000300057306 */
/* 0x0000620000201400 */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff067624 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ BSSY B0, 0x390 ; /* 0x000001c000007945 */
/* 0x000fea0003800000 */
/*01d0*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x000ea20000201400 */
/*01e0*/ IMAD R3, R0, c[0x0][0x164], R3 ; /* 0x0000590000037a24 */
/* 0x001fc400078e0203 */
/*01f0*/ FFMA R9, R5, R2, -2 ; /* 0xc000000005097423 */
/* 0x002fc80000000002 */
/*0200*/ FMUL R4, R9, R9 ; /* 0x0000000909047220 */
/* 0x000fe40000400000 */
/*0210*/ FFMA R8, R7, R2, -1.25 ; /* 0xbfa0000007087423 */
/* 0x004fe40000000002 */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0230*/ FMUL R5, R8, R8 ; /* 0x0000000808057220 */
/* 0x000fc80000400000 */
/*0240*/ FADD R2, R4, R5 ; /* 0x0000000504027221 */
/* 0x000fca0000000000 */
/*0250*/ FSETP.GEU.AND P0, PT, R2, 4, PT ; /* 0x408000000200780b */
/* 0x000fe20003f0e000 */
/*0260*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc600078e00ff */
/*0270*/ ISETP.LT.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fe20000701670 */
/*0280*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fd800078e0202 */
/*0290*/ @P0 BRA 0x380 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*02a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*02b0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*02c0*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0009 */
/*02d0*/ FADD R4, -R5, R4 ; /* 0x0000000405047221 */
/* 0x000fe20000000100 */
/*02e0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ FADD R5, R6, R6 ; /* 0x0000000606057221 */
/* 0x000fe40000000000 */
/*0300*/ FADD R6, R9, R4 ; /* 0x0000000409067221 */
/* 0x000fe20000000000 */
/*0310*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x160], PT ; /* 0x0000580007007a0c */
/* 0x000fe20003f06270 */
/*0320*/ FFMA R0, R5, R0, R8 ; /* 0x0000000005007223 */
/* 0x000fe40000000008 */
/*0330*/ FMUL R4, R6, R6 ; /* 0x0000000606047220 */
/* 0x000fc40000400000 */
/*0340*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x000fc80000400000 */
/*0350*/ FADD R10, R4, R5 ; /* 0x00000005040a7221 */
/* 0x000fca0000000000 */
/*0360*/ FSETP.LT.AND P1, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f21000 */
/*0370*/ @!P0 BRA P1, 0x2d0 ; /* 0xffffff5000008947 */
/* 0x000fea000083ffff */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*03c0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0004 */
/*03d0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fc800078ec0ff */
/*03e0*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fc80007ffe0ff */
/*03f0*/ ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ; /* 0x000000fd0800780c */
/* 0x000fda0003f04070 */
/*0400*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0410*/ @!P0 BRA 0x510 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0430*/ @P0 BRA 0x8e0 ; /* 0x000004a000000947 */
/* 0x000fea0003800000 */
/*0440*/ MOV R6, 0x40200000 ; /* 0x4020000000067802 */
/* 0x000fc80000000f00 */
/*0450*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R6, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c806 */
/*0460*/ @!P0 BRA 0x8c0 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1d200 */
/*0480*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0490*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04a0*/ @P0 BRA 0x8a0 ; /* 0x000003f000000947 */
/* 0x000fea0003800000 */
/*04b0*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c0ff */
/*04c0*/ @!P0 BRA 0x870 ; /* 0x000003a000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f06270 */
/*04e0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd800078e00ff */
/*04f0*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe200000000ff */
/*0500*/ @!P0 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006068810 */
/* 0x000fe40007ffe0ff */
/*0510*/ LEA R4, R5, 0xc0800000, 0x17 ; /* 0xc080000005047811 */
/* 0x000fe200078eb8ff */
/*0520*/ UMOV UR4, 0x40200000 ; /* 0x4020000000047882 */
/* 0x000fe20000000000 */
/*0530*/ IADD3 R5, R6, 0x80, -R5 ; /* 0x0000008006057810 */
/* 0x000fe20007ffe805 */
/*0540*/ UIADD3 UR4, UR4, -0x800000, URZ ; /* 0xff80000004047890 */
/* 0x000fe4000fffe03f */
/*0550*/ IMAD.IADD R4, R7, 0x1, -R4 ; /* 0x0000000107047824 */
/* 0x000fc800078e0a04 */
/*0560*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000e220000001000 */
/*0570*/ FADD.FTZ R8, -R4, -RZ ; /* 0x800000ff04087221 */
/* 0x000fc80000010100 */
/*0580*/ FFMA R10, R7, R8, 1 ; /* 0x3f800000070a7423 */
/* 0x001fc80000000008 */
/*0590*/ FFMA R9, R7, R10, R7 ; /* 0x0000000a07097223 */
/* 0x000fc80000000007 */
/*05a0*/ FFMA R7, R9, UR4, RZ ; /* 0x0000000409077c23 */
/* 0x000fc800080000ff */
/*05b0*/ FFMA R10, R8, R7, UR4 ; /* 0x00000004080a7e23 */
/* 0x000fc80008000007 */
/*05c0*/ FFMA R10, R9, R10, R7 ; /* 0x0000000a090a7223 */
/* 0x000fc80000000007 */
/*05d0*/ FFMA R8, R8, R10, UR4 ; /* 0x0000000408087e23 */
/* 0x000fc8000800000a */
/*05e0*/ FFMA R7, R9, R8, R10 ; /* 0x0000000809077223 */
/* 0x000fca000000000a */
/*05f0*/ SHF.R.U32.HI R4, RZ, 0x17, R7 ; /* 0x00000017ff047819 */
/* 0x000fc80000011607 */
/*0600*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0610*/ IMAD.IADD R11, R4, 0x1, R5 ; /* 0x00000001040b7824 */
/* 0x000fca00078e0205 */
/*0620*/ IADD3 R4, R11, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x000fc80007ffe0ff */
/*0630*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0640*/ @!P0 BRA 0x850 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0650*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0660*/ @P0 BRA 0x820 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0670*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0680*/ @P0 BRA 0x8f0 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0690*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*06a0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*06b0*/ @!P0 BRA 0x8f0 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*06c0*/ FFMA.RZ R4, R9, R8.reuse, R10.reuse ; /* 0x0000000809047223 */
/* 0x180fe2000000c00a */
/*06d0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f45270 */
/*06e0*/ FFMA.RM R5, R9, R8.reuse, R10.reuse ; /* 0x0000000809057223 */
/* 0x180fe2000000400a */
/*06f0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f25270 */
/*0700*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0710*/ FFMA.RP R4, R9, R8, R10 ; /* 0x0000000809047223 */
/* 0x000fe2000000800a */
/*0720*/ IADD3 R9, R11, 0x20, RZ ; /* 0x000000200b097810 */
/* 0x000fe20007ffe0ff */
/*0730*/ IMAD.MOV R8, RZ, RZ, -R11 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a0b */
/*0740*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0750*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0760*/ SHF.L.U32 R9, R6, R9, RZ ; /* 0x0000000906097219 */
/* 0x000fe400000006ff */
/*0770*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0780*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0790*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*07a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*07b0*/ SHF.R.U32.HI R9, RZ, 0x1, R5 ; /* 0x00000001ff097819 */
/* 0x000fc40000011605 */
/*07c0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*07d0*/ LOP3.LUT R4, R4, 0x1, R9, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef809 */
/*07e0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fc800078ec0ff */
/*07f0*/ IADD3 R4, R9, R4, RZ ; /* 0x0000000409047210 */
/* 0x000fc80007ffe0ff */
/*0800*/ LOP3.LUT R7, R4, R7, RZ, 0xfc, !PT ; /* 0x0000000704077212 */
/* 0x000fe200078efcff */
/*0810*/ BRA 0x8f0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0820*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*0830*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0840*/ BRA 0x8f0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0850*/ IMAD R7, R5, 0x800000, R7 ; /* 0x0080000005077824 */
/* 0x000fe200078e0207 */
/*0860*/ BRA 0x8f0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078e4806 */
/*0880*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0890*/ BRA 0x8f0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*08a0*/ LOP3.LUT R7, R7, 0x80000000, R6, 0x48, !PT ; /* 0x8000000007077812 */
/* 0x000fe200078e4806 */
/*08b0*/ BRA 0x8f0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*08c0*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*08d0*/ BRA 0x8f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08e0*/ FADD.FTZ R7, R4, 2.5 ; /* 0x4020000004077421 */
/* 0x000fe40000010000 */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, R2 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0002 */
/*0900*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0910*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff6e004007950 */
/* 0x000fea0003c3ffff */
/*0920*/ BRA 0x920; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10iterMandeliiPi
.globl _Z10iterMandeliiPi
.p2align 8
.type _Z10iterMandeliiPi,@function
_Z10iterMandeliiPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x4
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
v_cvt_f32_i32_e32 v2, s2
s_load_b32 s3, s[0:1], 0x0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, -1.0, v2
v_div_scale_f32 v3, null, v2, v2, 0x40200000
v_div_scale_f32 v6, vcc_lo, 0x40200000, v2, 0x40200000
s_delay_alu instid0(VALU_DEP_2)
v_rcp_f32_e32 v4, v3
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s3, 0
s_cselect_b32 s4, -1, 0
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_cvt_f32_i32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v3, v3, v2, 0x40200000
v_cvt_f32_i32_e32 v2, v1
v_fmaak_f32 v2, v3, v2, 0xbfa00000
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v3, v4, -2.0
v_mul_f32_e32 v4, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v3, v3, v4
v_cmp_gt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, 0
s_and_b32 s6, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_5
v_dual_mul_f32 v7, v3, v3 :: v_dual_mov_b32 v6, v2
v_mov_b32_e32 v8, v3
s_mov_b32 s6, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v8, v8
s_add_i32 s6, s6, 1
v_sub_f32_e32 v4, v7, v4
s_cmp_ge_i32 s6, s3
s_cselect_b32 s7, -1, 0
v_fma_f32 v6, v5, v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v3, v4
v_dual_mul_f32 v4, v6, v6 :: v_dual_mul_f32 v7, v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v8, v8, v4
v_cmp_ngt_f32_e32 vcc_lo, 4.0, v5
v_mov_b32_e32 v5, s6
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s7
s_or_b32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10iterMandeliiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10iterMandeliiPi, .Lfunc_end0-_Z10iterMandeliiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10iterMandeliiPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10iterMandeliiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e54c5_00000000-6_MandelGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9topChronov
.type _Z9topChronov, @function
_Z9topChronov:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
cvtsd2ss %xmm0, %xmm0
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9topChronov, .-_Z9topChronov
.globl _Z8compGridiRPfS0_
.type _Z8compGridiRPfS0_, @function
_Z8compGridiRPfS0_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movslq %edi, %r12
movabsq $2305843009213693950, %rax
cmpq %r12, %rax
jb .L8
movl %edi, %r13d
movq %rsi, %rbp
movq %rdx, %rbx
leaq 0(,%r12,4), %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, 0(%rbp)
movq %r14, %rdi
call _Znam@PLT
movq %rax, (%rbx)
pxor %xmm0, %xmm0
cvtsi2sdl %r13d, %xmm0
subsd .LC1(%rip), %xmm0
movsd .LC2(%rip), %xmm2
divsd %xmm0, %xmm2
cvtsd2ss %xmm2, %xmm2
movl $0, %eax
movss .LC3(%rip), %xmm4
movss .LC4(%rip), %xmm3
testl %r13d, %r13d
jle .L7
.L9:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm2, %xmm0
movq 0(%rbp), %rdx
movaps %xmm0, %xmm1
subss %xmm4, %xmm1
movss %xmm1, (%rdx,%rax,4)
movq (%rbx), %rdx
subss %xmm3, %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq %rax, %r12
jne .L9
.L7:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE2058:
.size _Z8compGridiRPfS0_, .-_Z8compGridiRPfS0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "w"
.LC6:
.string "Mandel.dat"
.LC7:
.string "%f\t%f\t%d\n"
.LC8:
.string "\n"
.text
.globl _Z10saveMandeliPKfS0_PKi
.type _Z10saveMandeliPKfS0_PKi, @function
_Z10saveMandeliPKfS0_PKi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movq %rsi, %r12
movq %rdx, %r15
movq %rdx, 8(%rsp)
movq %rcx, 16(%rsp)
leaq .LC5(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L16
movslq %ebx, %rax
leaq 0(,%rax,4), %r14
addq %r14, %r15
movq $0, (%rsp)
movq %rax, 24(%rsp)
.L17:
movq 16(%rsp), %rax
movq (%rsp), %rsi
leaq (%rax,%rsi,4), %rbp
movq 8(%rsp), %rbx
.L18:
movl 0(%rbp), %ecx
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12), %xmm1
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $2, %eax
call __fprintf_chk@PLT
addq %r14, %rbp
addq $4, %rbx
cmpq %r15, %rbx
jne .L18
leaq .LC8(%rip), %rdx
movl $2, %esi
movq %r13, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, (%rsp)
movq (%rsp), %rax
addq $4, %r12
movq 24(%rsp), %rdx
cmpq %rdx, %rax
jne .L17
.L16:
movq %r13, %rdi
call fclose@PLT
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z10saveMandeliPKfS0_PKi, .-_Z10saveMandeliPKfS0_PKi
.globl _Z32__device_stub__Z10iterMandeliiPiiiPi
.type _Z32__device_stub__Z10iterMandeliiPiiiPi, @function
_Z32__device_stub__Z10iterMandeliiPiiiPi:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10iterMandeliiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z10iterMandeliiPiiiPi, .-_Z32__device_stub__Z10iterMandeliiPiiiPi
.globl _Z10iterMandeliiPi
.type _Z10iterMandeliiPi, @function
_Z10iterMandeliiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10iterMandeliiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10iterMandeliiPi, .-_Z10iterMandeliiPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "Temps de calcul du Bouddha : %f secondes\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1280, %ebx
movl $1000, %r13d
cmpl $1, %edi
jg .L39
.L31:
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rsi
movl %ebx, %edi
call _Z8compGridiRPfS0_
movl %ebx, %ebp
imull %ebx, %ebp
movslq %ebp, %rbp
salq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %r12
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl $1, 56(%rsp)
leal 30(%rbx), %eax
movl %ebx, %edx
addl $15, %edx
cmovns %edx, %eax
sarl $4, %eax
movl %eax, 60(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L32:
movl $2, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
divsd .LC9(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rbp
movq 8(%rsp), %r13
movq %r12, %rcx
movq %rbp, %rdx
movq %r13, %rsi
movl %ebx, %edi
call _Z10saveMandeliPKfS0_PKi
movq %r12, %rdi
call _ZdaPv@PLT
testq %r13, %r13
je .L33
movq %r13, %rdi
call _ZdaPv@PLT
.L33:
testq %rbp, %rbp
je .L34
movq %rbp, %rdi
call _ZdaPv@PLT
.L34:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %edi, %ebp
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
cmpl $2, %ebp
jle .L31
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r13d
jmp .L31
.L40:
movq 24(%rsp), %rdx
movl %ebx, %esi
movl %r13d, %edi
call _Z32__device_stub__Z10iterMandeliiPiiiPi
jmp .L32
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z10iterMandeliiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10iterMandeliiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1074003968
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1067450368
.section .rodata.cst8
.align 8
.LC9:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MandelGPU.hip"
.globl _Z25__device_stub__iterMandeliiPi # -- Begin function _Z25__device_stub__iterMandeliiPi
.p2align 4, 0x90
.type _Z25__device_stub__iterMandeliiPi,@function
_Z25__device_stub__iterMandeliiPi: # @_Z25__device_stub__iterMandeliiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10iterMandeliiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__iterMandeliiPi, .Lfunc_end0-_Z25__device_stub__iterMandeliiPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9topChronov
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9topChronov
.p2align 4, 0x90
.type _Z9topChronov,@function
_Z9topChronov: # @_Z9topChronov
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9topChronov, .Lfunc_end1-_Z9topChronov
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8compGridiRPfS0_
.LCPI2_0:
.quad 0xbff0000000000000 # double -1
.LCPI2_1:
.quad 0x4004000000000000 # double 2.5
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_2:
.long 0xc0000000 # float -2
.LCPI2_3:
.long 0xbfa00000 # float -1.25
.text
.globl _Z8compGridiRPfS0_
.p2align 4, 0x90
.type _Z8compGridiRPfS0_,@function
_Z8compGridiRPfS0_: # @_Z8compGridiRPfS0_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r15
movq %rsi, %r14
movl %edi, %ebx
movslq %edi, %r13
leaq (,%r13,4), %rax
testl %r13d, %r13d
movq $-1, %r12
cmovnsq %rax, %r12
movq %r12, %rdi
callq _Znam
movq %rax, (%r14)
movq %r12, %rdi
callq _Znam
movq %rax, (%r15)
testl %r13d, %r13d
jle .LBB2_3
# %bb.1: # %.lr.ph
cvtsi2sd %ebx, %xmm0
addsd .LCPI2_0(%rip), %xmm0
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movq (%r14), %rcx
movl %ebx, %edx
xorl %esi, %esi
movss .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %esi, %xmm3
mulss %xmm0, %xmm3
movaps %xmm3, %xmm4
addss %xmm1, %xmm4
movss %xmm4, (%rcx,%rsi,4)
addss %xmm2, %xmm3
movss %xmm3, (%rax,%rsi,4)
incq %rsi
cmpq %rsi, %rdx
jne .LBB2_2
.LBB2_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8compGridiRPfS0_, .Lfunc_end2-_Z8compGridiRPfS0_
.cfi_endproc
# -- End function
.globl _Z10saveMandeliPKfS0_PKi # -- Begin function _Z10saveMandeliPKfS0_PKi
.p2align 4, 0x90
.type _Z10saveMandeliPKfS0_PKi,@function
_Z10saveMandeliPKfS0_PKi: # @_Z10saveMandeliPKfS0_PKi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %r14
movq %rdx, 40(%rsp) # 8-byte Spill
movq %rsi, 32(%rsp) # 8-byte Spill
movl %edi, %ebp
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbx
testl %ebp, %ebp
jle .LBB3_5
# %bb.1: # %.preheader.lr.ph
movl %ebp, %edx
leaq (,%rdx,4), %rcx
movq %rcx, 24(%rsp) # 8-byte Spill
xorl %ecx, %ecx
movq %rdx, 8(%rsp) # 8-byte Spill
movq 40(%rsp), %r12 # 8-byte Reload
movq 32(%rsp), %rbp # 8-byte Reload
movq 24(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movq %rcx, 16(%rsp) # 8-byte Spill
movq %r14, 48(%rsp) # 8-byte Spill
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq 16(%rsp), %rax # 8-byte Reload
movss (%rbp,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl (%r14), %edx
movl $.L.str.2, %esi
movq %rbx, %rdi
movb $2, %al
callq fprintf
incq %r15
addq %r13, %r14
cmpq %r15, 8(%rsp) # 8-byte Folded Reload
jne .LBB3_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
movq 16(%rsp), %rsi # 8-byte Reload
incq %rsi
movq 48(%rsp), %r14 # 8-byte Reload
addq $4, %r14
movq 8(%rsp), %rcx # 8-byte Reload
cmpq %rcx, %rsi
movq %rsi, %rcx
jne .LBB3_2
.LBB3_5: # %._crit_edge20
movq %rbx, %rdi
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z10saveMandeliPKfS0_PKi, .Lfunc_end3-_Z10saveMandeliPKfS0_PKi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0xbff0000000000000 # double -1
.LCPI4_1:
.quad 0x4004000000000000 # double 2.5
.LCPI4_4:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_2:
.long 0xc0000000 # float -2
.LCPI4_3:
.long 0xbfa00000 # float -1.25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $1280, %r15d # imm = 0x500
cmpl $2, %edi
jl .LBB4_2
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
.LBB4_2:
movl $1000, %eax # imm = 0x3E8
cmpl $3, %ebp
jl .LBB4_4
# %bb.3:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB4_4:
movq %rax, (%rsp) # 8-byte Spill
movslq %r15d, %rbx
leaq (,%rbx,4), %rax
testl %ebx, %ebx
movq $-1, %r14
cmovnsq %rax, %r14
movq %r14, %rdi
callq _Znam
movq %rax, %r12
movq %r14, %rdi
callq _Znam
movl %r15d, %r14d
testl %ebx, %ebx
jle .LBB4_7
# %bb.5: # %.lr.ph.i
cvtsi2sd %r15d, %xmm0
addsd .LCPI4_0(%rip), %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
xorl %ecx, %ecx
movss .LCPI4_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI4_3(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB4_6: # =>This Inner Loop Header: Depth=1
xorps %xmm3, %xmm3
cvtsi2ss %ecx, %xmm3
mulss %xmm0, %xmm3
movaps %xmm3, %xmm4
addss %xmm1, %xmm4
movss %xmm4, (%r12,%rcx,4)
addss %xmm2, %xmm3
movss %xmm3, (%rax,%rcx,4)
incq %rcx
cmpq %rcx, %r14
jne .LBB4_6
.LBB4_7: # %_Z8compGridiRPfS0_.exit
movq %rax, 48(%rsp) # 8-byte Spill
movq %r12, 56(%rsp) # 8-byte Spill
movl %r15d, %ebp
imull %ebp, %ebp
shlq $2, %rbp
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq %rbp, %rdi
callq _Znam
movq %rax, %rbx
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leal 15(%r15), %eax
leal 30(%r15), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $4, %ecx
movq %rcx, %r13
shlq $32, %r13
orq %rcx, %r13
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8:
movq 24(%rsp), %rax
movq (%rsp), %rcx # 8-byte Reload
movl %ecx, 36(%rsp)
movl %r15d, 32(%rsp)
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rax
movq %rax, 72(%rsp)
leaq 160(%rsp), %rax
movq %rax, 80(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10iterMandeliiPi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9:
movq 24(%rsp), %rsi
movq %rbx, 40(%rsp) # 8-byte Spill
movq %rbx, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI4_4(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbp
testl %r15d, %r15d
jle .LBB4_14
# %bb.10: # %.preheader.lr.ph.i
leaq (,%r14,4), %r15
xorl %ecx, %ecx
movq 40(%rsp), %r12 # 8-byte Reload
movq %r14, 96(%rsp) # 8-byte Spill
movq 48(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB4_11: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_12 Depth 2
movq %rcx, (%rsp) # 8-byte Spill
movq %r12, 104(%rsp) # 8-byte Spill
xorl %ebx, %ebx
movq 56(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB4_12: # Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r13,%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq (%rsp), %rax # 8-byte Reload
movss (%r14,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl (%r12), %edx
movl $.L.str.2, %esi
movq %rbp, %rdi
movb $2, %al
callq fprintf
addq $4, %rbx
addq %r15, %r12
cmpq %rbx, %r15
jne .LBB4_12
# %bb.13: # %._crit_edge.i
# in Loop: Header=BB4_11 Depth=1
movl $10, %edi
movq %rbp, %rsi
callq fputc@PLT
movq (%rsp), %rcx # 8-byte Reload
incq %rcx
movq 104(%rsp), %r12 # 8-byte Reload
addq $4, %r12
movq 96(%rsp), %r14 # 8-byte Reload
cmpq %r14, %rcx
jne .LBB4_11
.LBB4_14: # %_Z10saveMandeliPKfS0_PKi.exit
movq %rbp, %rdi
callq fclose
movq 40(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq 56(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq 48(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10iterMandeliiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10iterMandeliiPi,@object # @_Z10iterMandeliiPi
.section .rodata,"a",@progbits
.globl _Z10iterMandeliiPi
.p2align 3, 0x0
_Z10iterMandeliiPi:
.quad _Z25__device_stub__iterMandeliiPi
.size _Z10iterMandeliiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Mandel.dat"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%f\t%f\t%d\n"
.size .L.str.2, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Temps de calcul du Bouddha : %f secondes\n"
.size .L.str.4, 42
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10iterMandeliiPi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__iterMandeliiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10iterMandeliiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 2016 Henry Lee
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
extern "C" __device__ int hash_quinary(unsigned char q[], int len, int k, int *dp)
{
int sum = 0;
int i;
for (i=0; i<len; i++)
{
sum += dp[q[i]*14*10 + (len-i-1)*10 + k];
k -= q[i];
if (k <= 0)
{
break;
}
}
return sum;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 2016 Henry Lee
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
extern "C" __device__ int hash_quinary(unsigned char q[], int len, int k, int *dp)
{
int sum = 0;
int i;
for (i=0; i<len; i++)
{
sum += dp[q[i]*14*10 + (len-i-1)*10 + k];
k -= q[i];
if (k <= 0)
{
break;
}
}
return sum;
} | .file "tmpxft_0019d5cf_00000000-6_hash.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl hash_quinary
.type hash_quinary, @function
hash_quinary:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size hash_quinary, .-hash_quinary
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 2016 Henry Lee
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
extern "C" __device__ int hash_quinary(unsigned char q[], int len, int k, int *dp)
{
int sum = 0;
int i;
for (i=0; i<len; i++)
{
sum += dp[q[i]*14*10 + (len-i-1)*10 + k];
k -= q[i];
if (k <= 0)
{
break;
}
}
return sum;
} | /*
* Copyright 2016 Henry Lee
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" __device__ int hash_quinary(unsigned char q[], int len, int k, int *dp)
{
int sum = 0;
int i;
for (i=0; i<len; i++)
{
sum += dp[q[i]*14*10 + (len-i-1)*10 + k];
k -= q[i];
if (k <= 0)
{
break;
}
}
return sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 2016 Henry Lee
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" __device__ int hash_quinary(unsigned char q[], int len, int k, int *dp)
{
int sum = 0;
int i;
for (i=0; i<len; i++)
{
sum += dp[q[i]*14*10 + (len-i-1)*10 + k];
k -= q[i];
if (k <= 0)
{
break;
}
}
return sum;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 2016 Henry Lee
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
extern "C" __device__ int hash_quinary(unsigned char q[], int len, int k, int *dp)
{
int sum = 0;
int i;
for (i=0; i<len; i++)
{
sum += dp[q[i]*14*10 + (len-i-1)*10 + k];
k -= q[i];
if (k <= 0)
{
break;
}
}
return sum;
} | .text
.file "hash.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d5cf_00000000-6_hash.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl hash_quinary
.type hash_quinary, @function
hash_quinary:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size hash_quinary, .-hash_quinary
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hash.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reductionKernel(float* vec, int width, double* sumUp){
//shared memory instantiation
extern __shared__ float partialSum[];
//index for global memory
int g_idx = blockDim.x * blockIdx.x + threadIdx.x;
//index for shared memory
int b_idx = threadIdx.x;
//load shared memory from global memory
partialSum[b_idx] = g_idx < width ? vec[g_idx] : 0;
//reduction inside blocks
for(int stride = blockDim.x/2; stride >= 1 ; stride = stride/2){
__syncthreads();
if(b_idx < stride ){
partialSum[b_idx] = partialSum[b_idx] + partialSum[b_idx + stride];
}
}
//reduction for grid using just thread 0 of each block
if(b_idx == 0){
//coppy value back to global memory
vec[g_idx] = partialSum[b_idx];
//reduction
for(int stride = (gridDim.x * blockDim.x)/2; stride>=blockDim.x; stride = stride/2){
__syncthreads();
if(g_idx < stride){
vec[g_idx] = vec[g_idx] + vec[g_idx + stride];
}
}
}
//save result in output variable
if(g_idx == 0)
(*sumUp) = vec[g_idx];
} | code for sm_80
Function : _Z15reductionKernelPfiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0209 */
/*0070*/ IMAD.WIDE R2, R0.reuse, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe200078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @!P0 LDG.E R4, [R2.64] ; /* 0x0000000602048981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041d80000004800 */
/*00f0*/ @!P1 BRA 0x1c0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0100*/ SHF.L.U32 R4, R9, 0x2, RZ ; /* 0x0000000209047819 */
/* 0x001fe200000006ff */
/*0110*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fc8000f8e00ff */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0130*/ ISETP.GE.AND P1, PT, R9, R5, PT ; /* 0x000000050900720c */
/* 0x000fda0003f26270 */
/*0140*/ @!P1 IMAD R7, R5, 0x4, R4 ; /* 0x0000000405079824 */
/* 0x000fe200078e0204 */
/*0150*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fe20000011605 */
/*0160*/ @!P1 LDS R6, [R9.X4] ; /* 0x0000000009069984 */
/* 0x000fe80000004800 */
/*0170*/ @!P1 LDS R7, [R7] ; /* 0x0000000007079984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 FADD R6, R6, R7 ; /* 0x0000000706069221 */
/* 0x001fca0000000000 */
/*0190*/ @!P1 STS [R9.X4], R6 ; /* 0x0000000609009388 */
/* 0x0001e20000004800 */
/*01a0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*01b0*/ @P1 BRA 0x120 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01c0*/ BSSY B0, 0x350 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*01d0*/ @P0 BRA 0x340 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01f0*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x001fca0000000f00 */
/*0200*/ IMAD R4, R4, c[0x0][0xc], RZ ; /* 0x0000030004047a24 */
/* 0x000fca00078e02ff */
/*0210*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011604 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fe20003f06070 */
/*0230*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0021d8000c101906 */
/*0240*/ @!P0 BRA 0x340 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.GE.AND P0, PT, R0, R4.reuse, PT ; /* 0x000000040000720c */
/* 0x080fe20003f06270 */
/*0260*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0280*/ LEA.HI R8, R4, R4, RZ, 0x1 ; /* 0x0000000404087211 */
/* 0x000fca00078f08ff */
/*0290*/ BSSY B1, 0x310 ; /* 0x0000007000017945 */
/* 0x000fea0003800000 */
/*02a0*/ @P0 BRA 0x300 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*02b0*/ IMAD.WIDE R4, R4, 0x4, R2 ; /* 0x0000000404047825 */
/* 0x001fe200078e0202 */
/*02c0*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000eaa000c1e1900 */
/*02d0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fca0000000000 */
/*02f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*0300*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0310*/ SHF.R.S32.HI R4, RZ, 0x1, R8 ; /* 0x00000001ff047819 */
/* 0x000fc80000011408 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0330*/ @P0 BRA 0x250 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe400078e00ff */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0390*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*03c0*/ F2F.F64.F32 R4, R2 ; /* 0x0000000200047310 */
/* 0x004e280000201800 */
/*03d0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b06 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ BRA 0x3f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reductionKernel(float* vec, int width, double* sumUp){
//shared memory instantiation
extern __shared__ float partialSum[];
//index for global memory
int g_idx = blockDim.x * blockIdx.x + threadIdx.x;
//index for shared memory
int b_idx = threadIdx.x;
//load shared memory from global memory
partialSum[b_idx] = g_idx < width ? vec[g_idx] : 0;
//reduction inside blocks
for(int stride = blockDim.x/2; stride >= 1 ; stride = stride/2){
__syncthreads();
if(b_idx < stride ){
partialSum[b_idx] = partialSum[b_idx] + partialSum[b_idx + stride];
}
}
//reduction for grid using just thread 0 of each block
if(b_idx == 0){
//coppy value back to global memory
vec[g_idx] = partialSum[b_idx];
//reduction
for(int stride = (gridDim.x * blockDim.x)/2; stride>=blockDim.x; stride = stride/2){
__syncthreads();
if(g_idx < stride){
vec[g_idx] = vec[g_idx] + vec[g_idx + stride];
}
}
}
//save result in output variable
if(g_idx == 0)
(*sumUp) = vec[g_idx];
} | .file "tmpxft_00150965_00000000-6_reductionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15reductionKernelPfiPdPfiPd
.type _Z38__device_stub__Z15reductionKernelPfiPdPfiPd, @function
_Z38__device_stub__Z15reductionKernelPfiPdPfiPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15reductionKernelPfiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15reductionKernelPfiPdPfiPd, .-_Z38__device_stub__Z15reductionKernelPfiPdPfiPd
.globl _Z15reductionKernelPfiPd
.type _Z15reductionKernelPfiPd, @function
_Z15reductionKernelPfiPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15reductionKernelPfiPdPfiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15reductionKernelPfiPd, .-_Z15reductionKernelPfiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15reductionKernelPfiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15reductionKernelPfiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reductionKernel(float* vec, int width, double* sumUp){
//shared memory instantiation
extern __shared__ float partialSum[];
//index for global memory
int g_idx = blockDim.x * blockIdx.x + threadIdx.x;
//index for shared memory
int b_idx = threadIdx.x;
//load shared memory from global memory
partialSum[b_idx] = g_idx < width ? vec[g_idx] : 0;
//reduction inside blocks
for(int stride = blockDim.x/2; stride >= 1 ; stride = stride/2){
__syncthreads();
if(b_idx < stride ){
partialSum[b_idx] = partialSum[b_idx] + partialSum[b_idx + stride];
}
}
//reduction for grid using just thread 0 of each block
if(b_idx == 0){
//coppy value back to global memory
vec[g_idx] = partialSum[b_idx];
//reduction
for(int stride = (gridDim.x * blockDim.x)/2; stride>=blockDim.x; stride = stride/2){
__syncthreads();
if(g_idx < stride){
vec[g_idx] = vec[g_idx] + vec[g_idx + stride];
}
}
}
//save result in output variable
if(g_idx == 0)
(*sumUp) = vec[g_idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reductionKernel(float* vec, int width, double* sumUp){
//shared memory instantiation
extern __shared__ float partialSum[];
//index for global memory
int g_idx = blockDim.x * blockIdx.x + threadIdx.x;
//index for shared memory
int b_idx = threadIdx.x;
//load shared memory from global memory
partialSum[b_idx] = g_idx < width ? vec[g_idx] : 0;
//reduction inside blocks
for(int stride = blockDim.x/2; stride >= 1 ; stride = stride/2){
__syncthreads();
if(b_idx < stride ){
partialSum[b_idx] = partialSum[b_idx] + partialSum[b_idx + stride];
}
}
//reduction for grid using just thread 0 of each block
if(b_idx == 0){
//coppy value back to global memory
vec[g_idx] = partialSum[b_idx];
//reduction
for(int stride = (gridDim.x * blockDim.x)/2; stride>=blockDim.x; stride = stride/2){
__syncthreads();
if(g_idx < stride){
vec[g_idx] = vec[g_idx] + vec[g_idx + stride];
}
}
}
//save result in output variable
if(g_idx == 0)
(*sumUp) = vec[g_idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reductionKernel(float* vec, int width, double* sumUp){
//shared memory instantiation
extern __shared__ float partialSum[];
//index for global memory
int g_idx = blockDim.x * blockIdx.x + threadIdx.x;
//index for shared memory
int b_idx = threadIdx.x;
//load shared memory from global memory
partialSum[b_idx] = g_idx < width ? vec[g_idx] : 0;
//reduction inside blocks
for(int stride = blockDim.x/2; stride >= 1 ; stride = stride/2){
__syncthreads();
if(b_idx < stride ){
partialSum[b_idx] = partialSum[b_idx] + partialSum[b_idx + stride];
}
}
//reduction for grid using just thread 0 of each block
if(b_idx == 0){
//coppy value back to global memory
vec[g_idx] = partialSum[b_idx];
//reduction
for(int stride = (gridDim.x * blockDim.x)/2; stride>=blockDim.x; stride = stride/2){
__syncthreads();
if(g_idx < stride){
vec[g_idx] = vec[g_idx] + vec[g_idx + stride];
}
}
}
//save result in output variable
if(g_idx == 0)
(*sumUp) = vec[g_idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15reductionKernelPfiPd
.globl _Z15reductionKernelPfiPd
.p2align 8
.type _Z15reductionKernelPfiPd,@function
_Z15reductionKernelPfiPd:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s5, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v4, v[3:4], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_load_b32 s6, s[0:1], 0x18
v_lshl_add_u32 v3, v0, 2, 0
s_cmp_lt_u32 s4, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, s4
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s7
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshr_b32 s7, s5, 1
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s7, v0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v4, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v4
ds_store_b32 v3, v4
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
ds_load_b32 v0, v3
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s6, s6, 1
s_cmp_lt_u32 s6, s4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v0, off
s_cbranch_scc0 .LBB0_13
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
global_load_b32 v0, v2, s[2:3]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[0:1], v0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s7
s_lshr_b32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s4
s_cbranch_scc0 .LBB0_9
.LBB0_13:
s_mov_b32 s7, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v4, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_branch .LBB0_12
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reductionKernelPfiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15reductionKernelPfiPd, .Lfunc_end0-_Z15reductionKernelPfiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reductionKernelPfiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15reductionKernelPfiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reductionKernel(float* vec, int width, double* sumUp){
//shared memory instantiation
extern __shared__ float partialSum[];
//index for global memory
int g_idx = blockDim.x * blockIdx.x + threadIdx.x;
//index for shared memory
int b_idx = threadIdx.x;
//load shared memory from global memory
partialSum[b_idx] = g_idx < width ? vec[g_idx] : 0;
//reduction inside blocks
for(int stride = blockDim.x/2; stride >= 1 ; stride = stride/2){
__syncthreads();
if(b_idx < stride ){
partialSum[b_idx] = partialSum[b_idx] + partialSum[b_idx + stride];
}
}
//reduction for grid using just thread 0 of each block
if(b_idx == 0){
//coppy value back to global memory
vec[g_idx] = partialSum[b_idx];
//reduction
for(int stride = (gridDim.x * blockDim.x)/2; stride>=blockDim.x; stride = stride/2){
__syncthreads();
if(g_idx < stride){
vec[g_idx] = vec[g_idx] + vec[g_idx + stride];
}
}
}
//save result in output variable
if(g_idx == 0)
(*sumUp) = vec[g_idx];
} | .text
.file "reductionKernel.hip"
.globl _Z30__device_stub__reductionKernelPfiPd # -- Begin function _Z30__device_stub__reductionKernelPfiPd
.p2align 4, 0x90
.type _Z30__device_stub__reductionKernelPfiPd,@function
_Z30__device_stub__reductionKernelPfiPd: # @_Z30__device_stub__reductionKernelPfiPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15reductionKernelPfiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__reductionKernelPfiPd, .Lfunc_end0-_Z30__device_stub__reductionKernelPfiPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15reductionKernelPfiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15reductionKernelPfiPd,@object # @_Z15reductionKernelPfiPd
.section .rodata,"a",@progbits
.globl _Z15reductionKernelPfiPd
.p2align 3, 0x0
_Z15reductionKernelPfiPd:
.quad _Z30__device_stub__reductionKernelPfiPd
.size _Z15reductionKernelPfiPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15reductionKernelPfiPd"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__reductionKernelPfiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15reductionKernelPfiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15reductionKernelPfiPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0209 */
/*0070*/ IMAD.WIDE R2, R0.reuse, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe200078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @!P0 LDG.E R4, [R2.64] ; /* 0x0000000602048981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R9.X4], R4 ; /* 0x0000000409007388 */
/* 0x0041d80000004800 */
/*00f0*/ @!P1 BRA 0x1c0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0100*/ SHF.L.U32 R4, R9, 0x2, RZ ; /* 0x0000000209047819 */
/* 0x001fe200000006ff */
/*0110*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fc8000f8e00ff */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0130*/ ISETP.GE.AND P1, PT, R9, R5, PT ; /* 0x000000050900720c */
/* 0x000fda0003f26270 */
/*0140*/ @!P1 IMAD R7, R5, 0x4, R4 ; /* 0x0000000405079824 */
/* 0x000fe200078e0204 */
/*0150*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fe20000011605 */
/*0160*/ @!P1 LDS R6, [R9.X4] ; /* 0x0000000009069984 */
/* 0x000fe80000004800 */
/*0170*/ @!P1 LDS R7, [R7] ; /* 0x0000000007079984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 FADD R6, R6, R7 ; /* 0x0000000706069221 */
/* 0x001fca0000000000 */
/*0190*/ @!P1 STS [R9.X4], R6 ; /* 0x0000000609009388 */
/* 0x0001e20000004800 */
/*01a0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*01b0*/ @P1 BRA 0x120 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01c0*/ BSSY B0, 0x350 ; /* 0x0000018000007945 */
/* 0x000fe20003800000 */
/*01d0*/ @P0 BRA 0x340 ; /* 0x0000016000000947 */
/* 0x000fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01f0*/ MOV R4, c[0x0][0x0] ; /* 0x0000000000047a02 */
/* 0x001fca0000000f00 */
/*0200*/ IMAD R4, R4, c[0x0][0xc], RZ ; /* 0x0000030004047a24 */
/* 0x000fca00078e02ff */
/*0210*/ SHF.R.U32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011604 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fe20003f06070 */
/*0230*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0021d8000c101906 */
/*0240*/ @!P0 BRA 0x340 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.GE.AND P0, PT, R0, R4.reuse, PT ; /* 0x000000040000720c */
/* 0x080fe20003f06270 */
/*0260*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0270*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0280*/ LEA.HI R8, R4, R4, RZ, 0x1 ; /* 0x0000000404087211 */
/* 0x000fca00078f08ff */
/*0290*/ BSSY B1, 0x310 ; /* 0x0000007000017945 */
/* 0x000fea0003800000 */
/*02a0*/ @P0 BRA 0x300 ; /* 0x0000005000000947 */
/* 0x001fea0003800000 */
/*02b0*/ IMAD.WIDE R4, R4, 0x4, R2 ; /* 0x0000000404047825 */
/* 0x001fe200078e0202 */
/*02c0*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000eaa000c1e1900 */
/*02d0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fca0000000000 */
/*02f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*0300*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0310*/ SHF.R.S32.HI R4, RZ, 0x1, R8 ; /* 0x00000001ff047819 */
/* 0x000fc80000011408 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x0], PT ; /* 0x0000000004007a0c */
/* 0x000fda0003f06070 */
/*0330*/ @P0 BRA 0x250 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0360*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x001fe400078e00ff */
/*0380*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0390*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*03b0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*03c0*/ F2F.F64.F32 R4, R2 ; /* 0x0000000200047310 */
/* 0x004e280000201800 */
/*03d0*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b06 */
/*03e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03f0*/ BRA 0x3f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15reductionKernelPfiPd
.globl _Z15reductionKernelPfiPd
.p2align 8
.type _Z15reductionKernelPfiPd,@function
_Z15reductionKernelPfiPd:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s5, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v4, v[3:4], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_load_b32 s6, s[0:1], 0x18
v_lshl_add_u32 v3, v0, 2, 0
s_cmp_lt_u32 s4, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_cbranch_scc1 .LBB0_7
s_mov_b32 s5, s4
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s8
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s7
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshr_b32 s7, s5, 1
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s7, v0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v4, s7, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v4, 2, 0
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v4
ds_store_b32 v3, v4
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
ds_load_b32 v0, v3
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s6, s6, 1
s_cmp_lt_u32 s6, s4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v0, off
s_cbranch_scc0 .LBB0_13
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
global_load_b32 v0, v2, s[2:3]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[0:1], v0
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s7
s_lshr_b32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s4
s_cbranch_scc0 .LBB0_9
.LBB0_13:
s_mov_b32 s7, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v4, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[2:3], off
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
s_branch .LBB0_12
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reductionKernelPfiPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15reductionKernelPfiPd, .Lfunc_end0-_Z15reductionKernelPfiPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reductionKernelPfiPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15reductionKernelPfiPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00150965_00000000-6_reductionKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z15reductionKernelPfiPdPfiPd
.type _Z38__device_stub__Z15reductionKernelPfiPdPfiPd, @function
_Z38__device_stub__Z15reductionKernelPfiPdPfiPd:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15reductionKernelPfiPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z15reductionKernelPfiPdPfiPd, .-_Z38__device_stub__Z15reductionKernelPfiPdPfiPd
.globl _Z15reductionKernelPfiPd
.type _Z15reductionKernelPfiPd, @function
_Z15reductionKernelPfiPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15reductionKernelPfiPdPfiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15reductionKernelPfiPd, .-_Z15reductionKernelPfiPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15reductionKernelPfiPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15reductionKernelPfiPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reductionKernel.hip"
.globl _Z30__device_stub__reductionKernelPfiPd # -- Begin function _Z30__device_stub__reductionKernelPfiPd
.p2align 4, 0x90
.type _Z30__device_stub__reductionKernelPfiPd,@function
_Z30__device_stub__reductionKernelPfiPd: # @_Z30__device_stub__reductionKernelPfiPd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15reductionKernelPfiPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__reductionKernelPfiPd, .Lfunc_end0-_Z30__device_stub__reductionKernelPfiPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15reductionKernelPfiPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15reductionKernelPfiPd,@object # @_Z15reductionKernelPfiPd
.section .rodata,"a",@progbits
.globl _Z15reductionKernelPfiPd
.p2align 3, 0x0
_Z15reductionKernelPfiPd:
.quad _Z30__device_stub__reductionKernelPfiPd
.size _Z15reductionKernelPfiPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15reductionKernelPfiPd"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__reductionKernelPfiPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15reductionKernelPfiPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdlib>
#include <cstdio>
#include <cmath>
#include <cassert>
#define SIZE 32
void print_err_msg(cudaError_t err) {
if(err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void matrix_add3(float* d_A, float* d_B, float* d_C, size_t size, size_t h) {
/*
The Matrix kernel, each thread operates on 1 Matrix column
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(i; i < size; i=i+h) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add2(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix row
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + gridDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(size_t j=i; j < i+gridDim.x && j < size; ++j) {
d_C[j] = d_A[j] + d_B[j];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix element
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
if(i < size) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
int main() {
float* h_A;
float* h_B;
float* h_C;
float* d_A;
float* d_B;
float* d_C;
size_t size = SIZE*SIZE;
size_t bytes = size*sizeof(float);
h_A = (float *)malloc(bytes);
h_B = (float *)malloc(bytes);
h_C = (float *)malloc(bytes);
cudaError_t err;
err = cudaMalloc((void **) &d_A, bytes);
print_err_msg(err);
err = cudaMalloc((void **) &d_B, bytes);
print_err_msg(err);
err = cudaMalloc((void **) &d_C, bytes);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
h_A[i] = 1.0f;
h_B[i] = 2.0f;
h_C[i] = 5.0f;
}
err = cudaMemcpy(d_A, h_A, bytes, cudaMemcpyHostToDevice);
print_err_msg(err);
err = cudaMemcpy(d_B, h_B, bytes, cudaMemcpyHostToDevice);
print_err_msg(err);
/* int threads = SIZE; */
/* int blocks = ceil(size/threads); */
/* matrix_add<<<blocks, threads>>>(d_A, d_B, d_C, size); */
/* int threads = 1; */
/* int blocks = ceil(size/(SIZE*threads)); */
/* matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size); */
int threads = 32;
int blocks = ceil(size/(SIZE*threads));
matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size);
err = cudaMemcpy(h_C, d_C, bytes, cudaMemcpyDeviceToHost);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
assert(h_C[i] == 3.0f);
/* printf("%f ", h_C[i]); */
/* if(i % SIZE == 0) printf("\n"); */
}
free(h_A);
free(h_B);
free(h_C);
err = cudaFree(d_A);
print_err_msg(err);
err = cudaFree(d_B);
print_err_msg(err);
err = cudaFree(d_C);
print_err_msg(err);
return 0;
} | code for sm_80
Function : _Z10matrix_addPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R2, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc80000ffe4ff */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe200007fe4ff */
/*0120*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11matrix_add2PfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R11, R11, c[0x0][0xc], R0 ; /* 0x000003000b0b7a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fc80003f06100 */
/*0060*/ ISETP.EQ.OR P0, PT, RZ, c[0x0][0xc], P0 ; /* 0x00000300ff007a0c */
/* 0x000fda0000702670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R8, P0, R11.reuse, c[0x0][0xc], RZ ; /* 0x000003000b087a10 */
/* 0x040fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*00a0*/ IADD3 R3, P1, R11, 0x1, RZ ; /* 0x000000010b037810 */
/* 0x000fe20007f3e0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x430 ; /* 0x0000036000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.X R9, RZ, RZ, RZ, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e06ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe20003f04070 */
/*00f0*/ IMAD.X R6, RZ, RZ, R0, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0600 */
/*0100*/ IADD3 R2, P1, R11, -c[0x0][0x178], RZ ; /* 0x80005e000b027a10 */
/* 0x000fc80007f3e0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, R9, PT, P0 ; /* 0x000000090600720c */
/* 0x000fc80003f04100 */
/*0120*/ SEL R4, R3, R8, P0 ; /* 0x0000000803047207 */
/* 0x000fe40000000000 */
/*0130*/ SEL R7, R6, R9, P0 ; /* 0x0000000906077207 */
/* 0x000fe40000000000 */
/*0140*/ IADD3 R5, P0, -R4, R11, RZ ; /* 0x0000000b04057210 */
/* 0x000fe40007f1e1ff */
/*0150*/ IADD3.X R3, R0, ~c[0x0][0x17c], RZ, P1, !PT ; /* 0x80005f0000037a10 */
/* 0x000fc60000ffe4ff */
/*0160*/ IMAD.X R4, R0, 0x1, ~R7, P0 ; /* 0x0000000100047824 */
/* 0x000fe200000e0e07 */
/*0170*/ ISETP.GT.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fc80003f04070 */
/*0180*/ ISETP.GT.U32.AND.EX P0, PT, R4, R3, PT, P0 ; /* 0x000000030400720c */
/* 0x000fc80003f04100 */
/*0190*/ SEL R5, R5, R2, P0 ; /* 0x0000000205057207 */
/* 0x000fe40000000000 */
/*01a0*/ SEL R3, R4, R3, P0 ; /* 0x0000000304037207 */
/* 0x000fe40000000000 */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R5, -0x4, PT ; /* 0xfffffffc0500780c */
/* 0x000fe20003f04070 */
/*01c0*/ IMAD.MOV R2, RZ, RZ, -R5 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a05 */
/*01d0*/ ISETP.GT.U32.AND.EX P0, PT, R3, -0x1, PT, P0 ; /* 0xffffffff0300780c */
/* 0x000fe40003f04100 */
/*01e0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fc800078ec0ff */
/*01f0*/ ISETP.NE.U32.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f25070 */
/*0200*/ ISETP.NE.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fda0003f25310 */
/*0210*/ @!P1 BRA 0x420 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0230*/ IADD3 R6, P4, RZ, -R2, RZ ; /* 0x80000002ff067210 */
/* 0x000fe40007f9e0ff */
/*0240*/ SHF.L.U64.HI R13, R11, 0x2, R0 ; /* 0x000000020b0d7819 */
/* 0x000fe40000010200 */
/*0250*/ IADD3 R15, P1, R12.reuse, c[0x0][0x170], RZ ; /* 0x00005c000c0f7a10 */
/* 0x040fe20007f3e0ff */
/*0260*/ IMAD.X R10, RZ, RZ, -0x1, P4 ; /* 0xffffffffff0a7424 */
/* 0x000fe200020e06ff */
/*0270*/ IADD3 R14, P2, R12.reuse, c[0x0][0x168], RZ ; /* 0x00005a000c0e7a10 */
/* 0x040fe40007f5e0ff */
/*0280*/ IADD3 R12, P3, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fe40007f7e0ff */
/*0290*/ IADD3.X R16, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d107a10 */
/* 0x000fc40000ffe4ff */
/*02a0*/ IADD3.X R5, R13.reuse, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b000d057a10 */
/* 0x040fe400017fe4ff */
/*02b0*/ IADD3.X R13, R13, c[0x0][0x164], RZ, P3, !PT ; /* 0x000059000d0d7a10 */
/* 0x000fc60001ffe4ff */
/*02c0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x001fe400078e000d */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*02f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0000a8000c1e1900 */
/*0300*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0002a2000c1e1900 */
/*0310*/ IADD3 R6, P1, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc40007f3e0ff */
/*0320*/ IADD3 R11, P2, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007f5e0ff */
/*0330*/ IADD3 R14, P4, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007f9e0ff */
/*0340*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0350*/ ISETP.NE.U32.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25070 */
/*0360*/ IMAD.X R0, RZ, RZ, R0, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0600 */
/*0370*/ IADD3 R12, P5, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007fbe0ff */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R15 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000f */
/*0390*/ ISETP.NE.AND.EX P1, PT, R10, RZ, PT, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25310 */
/*03a0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x001fe200020e0605 */
/*03b0*/ IADD3 R15, P3, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe20007f7e0ff */
/*03c0*/ IMAD.X R13, RZ, RZ, R13, P5 ; /* 0x000000ffff0d7224 */
/* 0x000fc400028e060d */
/*03d0*/ FADD R7, R4, R3 ; /* 0x0000000304077221 */
/* 0x004fe40000000000 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, R16.reuse ; /* 0x000000ffff037224 */
/* 0x100fe400078e0010 */
/*03f0*/ IMAD.X R16, RZ, RZ, R16, P3 ; /* 0x000000ffff107224 */
/* 0x000fc600018e0610 */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0410*/ @P1 BRA 0x2c0 ; /* 0xfffffea000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.SHL.U32 R2, R11.reuse, 0x4, RZ ; /* 0x000000040b027824 */
/* 0x041fe200078e00ff */
/*0450*/ SHF.L.U64.HI R3, R11, 0x2, R0 ; /* 0x000000020b037819 */
/* 0x000fc80000010200 */
/*0460*/ IADD3 R6, P0, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x040fe40007f1e0ff */
/*0470*/ IADD3 R4, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fe40007f3e0ff */
/*0480*/ IADD3.X R7, R3.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x040fe400007fe4ff */
/*0490*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003057a10 */
/* 0x000fc60000ffe4ff */
/*04a0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IADD3 R2, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fc80007f1e0ff */
/*04d0*/ IADD3.X R3, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003037a10 */
/* 0x000fe200007fe4ff */
/*04e0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*04f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0500*/ LDG.E R10, [R6.64+0x4] ; /* 0x00000404060a7981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x000ea4000c1e1900 */
/*0520*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*0530*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0001e8000c101904 */
/*0540*/ LDG.E R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080404117981 */
/* 0x000ea4000c1e1900 */
/*0560*/ FADD R17, R10, R17 ; /* 0x000000110a117221 */
/* 0x004fca0000000000 */
/*0570*/ STG.E [R2.64+0x8], R17 ; /* 0x0000081102007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R10, [R6.64+0xc] ; /* 0x00000c04060a7981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R19, [R4.64+0xc] ; /* 0x00000c0404137981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R11, P0, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc80007f1e0ff */
/*05b0*/ ISETP.GE.U32.AND P1, PT, R11.reuse, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x040fe20003f26070 */
/*05c0*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x000fc80003f06070 */
/*05e0*/ ISETP.GE.U32.AND.EX P0, PT, R0.reuse, R9, PT, P0 ; /* 0x000000090000720c */
/* 0x040fe40003f06100 */
/*05f0*/ ISETP.GE.U32.AND.EX P1, PT, R0, c[0x0][0x17c], PT, P1 ; /* 0x00005f0000007a0c */
/* 0x000fe20003f26110 */
/*0600*/ FADD R19, R10, R19 ; /* 0x000000130a137221 */
/* 0x004fca0000000000 */
/*0610*/ STG.E [R2.64+0xc], R19 ; /* 0x00000c1302007986 */
/* 0x0001ee000c101904 */
/*0620*/ @!P0 BRA !P1, 0x440 ; /* 0xfffffe1000008947 */
/* 0x000fea000483ffff */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ BRA 0x640; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11matrix_add3PfS_S_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x041fe200078e00ff */
/*0090*/ SHF.L.U64.HI R7, R0, 0x2, R11 ; /* 0x0000000200077819 */
/* 0x000fe2000001020b */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f3e0ff */
/*00c0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f1e0ff */
/*00d0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */
/* 0x040fe40000ffe4ff */
/*00e0*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */
/* 0x000fc800007fe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe400007fe4ff */
/*0130*/ IADD3 R0, P0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fc80007f1e0ff */
/*0140*/ IADD3.X R11, R11, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000b0b7a10 */
/* 0x000fe400007fe4ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0160*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */
/* 0x000fe20003f06100 */
/*0170*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0180*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0190*/ @!P0 BRA 0x80 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdlib>
#include <cstdio>
#include <cmath>
#include <cassert>
#define SIZE 32
void print_err_msg(cudaError_t err) {
if(err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void matrix_add3(float* d_A, float* d_B, float* d_C, size_t size, size_t h) {
/*
The Matrix kernel, each thread operates on 1 Matrix column
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(i; i < size; i=i+h) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add2(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix row
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + gridDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(size_t j=i; j < i+gridDim.x && j < size; ++j) {
d_C[j] = d_A[j] + d_B[j];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix element
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
if(i < size) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
int main() {
float* h_A;
float* h_B;
float* h_C;
float* d_A;
float* d_B;
float* d_C;
size_t size = SIZE*SIZE;
size_t bytes = size*sizeof(float);
h_A = (float *)malloc(bytes);
h_B = (float *)malloc(bytes);
h_C = (float *)malloc(bytes);
cudaError_t err;
err = cudaMalloc((void **) &d_A, bytes);
print_err_msg(err);
err = cudaMalloc((void **) &d_B, bytes);
print_err_msg(err);
err = cudaMalloc((void **) &d_C, bytes);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
h_A[i] = 1.0f;
h_B[i] = 2.0f;
h_C[i] = 5.0f;
}
err = cudaMemcpy(d_A, h_A, bytes, cudaMemcpyHostToDevice);
print_err_msg(err);
err = cudaMemcpy(d_B, h_B, bytes, cudaMemcpyHostToDevice);
print_err_msg(err);
/* int threads = SIZE; */
/* int blocks = ceil(size/threads); */
/* matrix_add<<<blocks, threads>>>(d_A, d_B, d_C, size); */
/* int threads = 1; */
/* int blocks = ceil(size/(SIZE*threads)); */
/* matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size); */
int threads = 32;
int blocks = ceil(size/(SIZE*threads));
matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size);
err = cudaMemcpy(h_C, d_C, bytes, cudaMemcpyDeviceToHost);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
assert(h_C[i] == 3.0f);
/* printf("%f ", h_C[i]); */
/* if(i % SIZE == 0) printf("\n"); */
}
free(h_A);
free(h_B);
free(h_C);
err = cudaFree(d_A);
print_err_msg(err);
err = cudaFree(d_B);
print_err_msg(err);
err = cudaFree(d_C);
print_err_msg(err);
return 0;
} | .file "tmpxft_000e1b22_00000000-6_matrix_add2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/palPrabhakar/tutorials/master/cuda/kirk_hwu/ch3/matrix_add2.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z13print_err_msg9cudaError
.type _Z13print_err_msg9cudaError, @function
_Z13print_err_msg9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $10, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13print_err_msg9cudaError, .-_Z13print_err_msg9cudaError
.globl _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm
.type _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm, @function
_Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11matrix_add3PfS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm, .-_Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm
.globl _Z11matrix_add3PfS_S_mm
.type _Z11matrix_add3PfS_S_mm, @function
_Z11matrix_add3PfS_S_mm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11matrix_add3PfS_S_mm, .-_Z11matrix_add3PfS_S_mm
.globl _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
.type _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m, @function
_Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11matrix_add2PfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m, .-_Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
.globl _Z11matrix_add2PfS_S_m
.type _Z11matrix_add2PfS_S_m, @function
_Z11matrix_add2PfS_S_m:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11matrix_add2PfS_S_m, .-_Z11matrix_add2PfS_S_m
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movl $0, %ebx
movss .LC2(%rip), %xmm2
movss .LC3(%rip), %xmm1
movss .LC4(%rip), %xmm0
.L26:
movss %xmm2, 0(%r13,%rbx,4)
movss %xmm1, (%r12,%rbx,4)
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $1024, %rbx
jne .L26
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
.L28:
subq $1, %rbx
jne .L28
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.globl _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m
.type _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m, @function
_Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_addPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m, .-_Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m
.globl _Z10matrix_addPfS_S_m
.type _Z10matrix_addPfS_S_m, @function
_Z10matrix_addPfS_S_m:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z10matrix_addPfS_S_m, .-_Z10matrix_addPfS_S_m
.section .rodata.str1.1
.LC5:
.string "_Z10matrix_addPfS_S_m"
.LC6:
.string "_Z11matrix_add2PfS_S_m"
.LC7:
.string "_Z11matrix_add3PfS_S_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_addPfS_S_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_add2PfS_S_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_add3PfS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdlib>
#include <cstdio>
#include <cmath>
#include <cassert>
#define SIZE 32
void print_err_msg(cudaError_t err) {
if(err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void matrix_add3(float* d_A, float* d_B, float* d_C, size_t size, size_t h) {
/*
The Matrix kernel, each thread operates on 1 Matrix column
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(i; i < size; i=i+h) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add2(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix row
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + gridDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(size_t j=i; j < i+gridDim.x && j < size; ++j) {
d_C[j] = d_A[j] + d_B[j];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix element
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
if(i < size) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
int main() {
float* h_A;
float* h_B;
float* h_C;
float* d_A;
float* d_B;
float* d_C;
size_t size = SIZE*SIZE;
size_t bytes = size*sizeof(float);
h_A = (float *)malloc(bytes);
h_B = (float *)malloc(bytes);
h_C = (float *)malloc(bytes);
cudaError_t err;
err = cudaMalloc((void **) &d_A, bytes);
print_err_msg(err);
err = cudaMalloc((void **) &d_B, bytes);
print_err_msg(err);
err = cudaMalloc((void **) &d_C, bytes);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
h_A[i] = 1.0f;
h_B[i] = 2.0f;
h_C[i] = 5.0f;
}
err = cudaMemcpy(d_A, h_A, bytes, cudaMemcpyHostToDevice);
print_err_msg(err);
err = cudaMemcpy(d_B, h_B, bytes, cudaMemcpyHostToDevice);
print_err_msg(err);
/* int threads = SIZE; */
/* int blocks = ceil(size/threads); */
/* matrix_add<<<blocks, threads>>>(d_A, d_B, d_C, size); */
/* int threads = 1; */
/* int blocks = ceil(size/(SIZE*threads)); */
/* matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size); */
int threads = 32;
int blocks = ceil(size/(SIZE*threads));
matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size);
err = cudaMemcpy(h_C, d_C, bytes, cudaMemcpyDeviceToHost);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
assert(h_C[i] == 3.0f);
/* printf("%f ", h_C[i]); */
/* if(i % SIZE == 0) printf("\n"); */
}
free(h_A);
free(h_B);
free(h_C);
err = cudaFree(d_A);
print_err_msg(err);
err = cudaFree(d_B);
print_err_msg(err);
err = cudaFree(d_C);
print_err_msg(err);
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include <cassert>
#define SIZE 32
void print_err_msg(hipError_t err) {
if(err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void matrix_add3(float* d_A, float* d_B, float* d_C, size_t size, size_t h) {
/*
The Matrix kernel, each thread operates on 1 Matrix column
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(i; i < size; i=i+h) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add2(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix row
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + gridDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(size_t j=i; j < i+gridDim.x && j < size; ++j) {
d_C[j] = d_A[j] + d_B[j];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix element
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
if(i < size) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
int main() {
float* h_A;
float* h_B;
float* h_C;
float* d_A;
float* d_B;
float* d_C;
size_t size = SIZE*SIZE;
size_t bytes = size*sizeof(float);
h_A = (float *)malloc(bytes);
h_B = (float *)malloc(bytes);
h_C = (float *)malloc(bytes);
hipError_t err;
err = hipMalloc((void **) &d_A, bytes);
print_err_msg(err);
err = hipMalloc((void **) &d_B, bytes);
print_err_msg(err);
err = hipMalloc((void **) &d_C, bytes);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
h_A[i] = 1.0f;
h_B[i] = 2.0f;
h_C[i] = 5.0f;
}
err = hipMemcpy(d_A, h_A, bytes, hipMemcpyHostToDevice);
print_err_msg(err);
err = hipMemcpy(d_B, h_B, bytes, hipMemcpyHostToDevice);
print_err_msg(err);
/* int threads = SIZE; */
/* int blocks = ceil(size/threads); */
/* matrix_add<<<blocks, threads>>>(d_A, d_B, d_C, size); */
/* int threads = 1; */
/* int blocks = ceil(size/(SIZE*threads)); */
/* matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size); */
int threads = 32;
int blocks = ceil(size/(SIZE*threads));
matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size);
err = hipMemcpy(h_C, d_C, bytes, hipMemcpyDeviceToHost);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
assert(h_C[i] == 3.0f);
/* printf("%f ", h_C[i]); */
/* if(i % SIZE == 0) printf("\n"); */
}
free(h_A);
free(h_B);
free(h_C);
err = hipFree(d_A);
print_err_msg(err);
err = hipFree(d_B);
print_err_msg(err);
err = hipFree(d_C);
print_err_msg(err);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include <cassert>
#define SIZE 32
void print_err_msg(hipError_t err) {
if(err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void matrix_add3(float* d_A, float* d_B, float* d_C, size_t size, size_t h) {
/*
The Matrix kernel, each thread operates on 1 Matrix column
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(i; i < size; i=i+h) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add2(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix row
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + gridDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(size_t j=i; j < i+gridDim.x && j < size; ++j) {
d_C[j] = d_A[j] + d_B[j];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix element
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
if(i < size) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
int main() {
float* h_A;
float* h_B;
float* h_C;
float* d_A;
float* d_B;
float* d_C;
size_t size = SIZE*SIZE;
size_t bytes = size*sizeof(float);
h_A = (float *)malloc(bytes);
h_B = (float *)malloc(bytes);
h_C = (float *)malloc(bytes);
hipError_t err;
err = hipMalloc((void **) &d_A, bytes);
print_err_msg(err);
err = hipMalloc((void **) &d_B, bytes);
print_err_msg(err);
err = hipMalloc((void **) &d_C, bytes);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
h_A[i] = 1.0f;
h_B[i] = 2.0f;
h_C[i] = 5.0f;
}
err = hipMemcpy(d_A, h_A, bytes, hipMemcpyHostToDevice);
print_err_msg(err);
err = hipMemcpy(d_B, h_B, bytes, hipMemcpyHostToDevice);
print_err_msg(err);
/* int threads = SIZE; */
/* int blocks = ceil(size/threads); */
/* matrix_add<<<blocks, threads>>>(d_A, d_B, d_C, size); */
/* int threads = 1; */
/* int blocks = ceil(size/(SIZE*threads)); */
/* matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size); */
int threads = 32;
int blocks = ceil(size/(SIZE*threads));
matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size);
err = hipMemcpy(h_C, d_C, bytes, hipMemcpyDeviceToHost);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
assert(h_C[i] == 3.0f);
/* printf("%f ", h_C[i]); */
/* if(i % SIZE == 0) printf("\n"); */
}
free(h_A);
free(h_B);
free(h_C);
err = hipFree(d_A);
print_err_msg(err);
err = hipFree(d_B);
print_err_msg(err);
err = hipFree(d_C);
print_err_msg(err);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_add3PfS_S_mm
.globl _Z11matrix_add3PfS_S_mm
.p2align 8
.type _Z11matrix_add3PfS_S_mm,@function
_Z11matrix_add3PfS_S_mm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[12:13], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v0, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_add3PfS_S_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_add3PfS_S_mm, .Lfunc_end0-_Z11matrix_add3PfS_S_mm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11matrix_add2PfS_S_m
.globl _Z11matrix_add2PfS_S_m
.p2align 8
.type _Z11matrix_add2PfS_S_m,@function
_Z11matrix_add2PfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, s15, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s4, v1, s4
v_add_co_ci_u32_e64 v4, null, 0, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[3:4]
v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, s2, v3
v_cndmask_b32_e32 v4, s3, v4, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
v_cmpx_gt_u64_e64 v[3:4], v[1:2]
s_cbranch_execz .LBB1_3
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[9:10], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v10, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
.p2align 6
.LBB1_2:
global_load_b32 v0, v[9:10], off
global_load_b32 v11, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_cmp_ge_u64_e32 vcc_lo, v[1:2], v[3:4]
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v11
global_store_b32 v[5:6], v0, off
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_add2PfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11matrix_add2PfS_S_m, .Lfunc_end1-_Z11matrix_add2PfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10matrix_addPfS_S_m
.globl _Z10matrix_addPfS_S_m
.p2align 8
.type _Z10matrix_addPfS_S_m,@function
_Z10matrix_addPfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_addPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10matrix_addPfS_S_m, .Lfunc_end2-_Z10matrix_addPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_add3PfS_S_mm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_add3PfS_S_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_add2PfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_add2PfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_addPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_addPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdlib>
#include <cstdio>
#include <cmath>
#include <cassert>
#define SIZE 32
void print_err_msg(hipError_t err) {
if(err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
}
__global__ void matrix_add3(float* d_A, float* d_B, float* d_C, size_t size, size_t h) {
/*
The Matrix kernel, each thread operates on 1 Matrix column
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(i; i < size; i=i+h) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add2(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix row
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + gridDim.x*blockIdx.x;
/* printf("gridDim.x: %d\n", gridDim.x); */
for(size_t j=i; j < i+gridDim.x && j < size; ++j) {
d_C[j] = d_A[j] + d_B[j];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
__global__ void matrix_add(float* d_A, float* d_B, float* d_C, size_t size) {
/*
The Matrix kernel, each thread operates on 1 Matrix element
2D Array is represented as flat 1D array
2D Array is processed as flat 1D array
*/
size_t i = threadIdx.x + blockDim.x*blockIdx.x;
if(i < size) {
d_C[i] = d_A[i] + d_B[i];
/* printf("i: %d, d_C[i] %f\n", i, d_C[i]); */
}
}
int main() {
float* h_A;
float* h_B;
float* h_C;
float* d_A;
float* d_B;
float* d_C;
size_t size = SIZE*SIZE;
size_t bytes = size*sizeof(float);
h_A = (float *)malloc(bytes);
h_B = (float *)malloc(bytes);
h_C = (float *)malloc(bytes);
hipError_t err;
err = hipMalloc((void **) &d_A, bytes);
print_err_msg(err);
err = hipMalloc((void **) &d_B, bytes);
print_err_msg(err);
err = hipMalloc((void **) &d_C, bytes);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
h_A[i] = 1.0f;
h_B[i] = 2.0f;
h_C[i] = 5.0f;
}
err = hipMemcpy(d_A, h_A, bytes, hipMemcpyHostToDevice);
print_err_msg(err);
err = hipMemcpy(d_B, h_B, bytes, hipMemcpyHostToDevice);
print_err_msg(err);
/* int threads = SIZE; */
/* int blocks = ceil(size/threads); */
/* matrix_add<<<blocks, threads>>>(d_A, d_B, d_C, size); */
/* int threads = 1; */
/* int blocks = ceil(size/(SIZE*threads)); */
/* matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size); */
int threads = 32;
int blocks = ceil(size/(SIZE*threads));
matrix_add2<<<blocks, threads>>>(d_A, d_B, d_C, size);
err = hipMemcpy(h_C, d_C, bytes, hipMemcpyDeviceToHost);
print_err_msg(err);
for(size_t i = 0; i < size; ++i) {
assert(h_C[i] == 3.0f);
/* printf("%f ", h_C[i]); */
/* if(i % SIZE == 0) printf("\n"); */
}
free(h_A);
free(h_B);
free(h_C);
err = hipFree(d_A);
print_err_msg(err);
err = hipFree(d_B);
print_err_msg(err);
err = hipFree(d_C);
print_err_msg(err);
return 0;
} | .text
.file "matrix_add2.hip"
.globl _Z13print_err_msg10hipError_t # -- Begin function _Z13print_err_msg10hipError_t
.p2align 4, 0x90
.type _Z13print_err_msg10hipError_t,@function
_Z13print_err_msg10hipError_t: # @_Z13print_err_msg10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $12, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13print_err_msg10hipError_t, .Lfunc_end0-_Z13print_err_msg10hipError_t
.cfi_endproc
# -- End function
.globl _Z26__device_stub__matrix_add3PfS_S_mm # -- Begin function _Z26__device_stub__matrix_add3PfS_S_mm
.p2align 4, 0x90
.type _Z26__device_stub__matrix_add3PfS_S_mm,@function
_Z26__device_stub__matrix_add3PfS_S_mm: # @_Z26__device_stub__matrix_add3PfS_S_mm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11matrix_add3PfS_S_mm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z26__device_stub__matrix_add3PfS_S_mm, .Lfunc_end1-_Z26__device_stub__matrix_add3PfS_S_mm
.cfi_endproc
# -- End function
.globl _Z26__device_stub__matrix_add2PfS_S_m # -- Begin function _Z26__device_stub__matrix_add2PfS_S_m
.p2align 4, 0x90
.type _Z26__device_stub__matrix_add2PfS_S_m,@function
_Z26__device_stub__matrix_add2PfS_S_m: # @_Z26__device_stub__matrix_add2PfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_add2PfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__matrix_add2PfS_S_m, .Lfunc_end2-_Z26__device_stub__matrix_add2PfS_S_m
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrix_addPfS_S_m # -- Begin function _Z25__device_stub__matrix_addPfS_S_m
.p2align 4, 0x90
.type _Z25__device_stub__matrix_addPfS_S_m,@function
_Z25__device_stub__matrix_addPfS_S_m: # @_Z25__device_stub__matrix_addPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_addPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__matrix_addPfS_S_m, .Lfunc_end3-_Z25__device_stub__matrix_addPfS_S_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB4_14
# %bb.1: # %_Z13print_err_msg10hipError_t.exit
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB4_14
# %bb.2: # %_Z13print_err_msg10hipError_t.exit45
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB4_14
# %bb.3: # %_Z13print_err_msg10hipError_t.exit47.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_4: # %_Z13print_err_msg10hipError_t.exit47
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
movl $1084227584, (%r15,%rax,4) # imm = 0x40A00000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB4_4
# %bb.5:
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.6: # %_Z13print_err_msg10hipError_t.exit49
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.7: # %_Z13print_err_msg10hipError_t.exit51
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq $1024, 80(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11matrix_add2PfS_S_m, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.10: # %_Z13print_err_msg10hipError_t.exit53.preheader
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_14
# %bb.11: # %_Z13print_err_msg10hipError_t.exit55
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_14
# %bb.12: # %_Z13print_err_msg10hipError_t.exit57
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_14
# %bb.13: # %_Z13print_err_msg10hipError_t.exit59
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_14:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $12, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_add3PfS_S_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_add2PfS_S_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_addPfS_S_m, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/palPrabhakar/tutorials/master/cuda/kirk_hwu/ch3/matrix_add2.hip"
.size .L.str.1, 121
.type _Z11matrix_add3PfS_S_mm,@object # @_Z11matrix_add3PfS_S_mm
.section .rodata,"a",@progbits
.globl _Z11matrix_add3PfS_S_mm
.p2align 3, 0x0
_Z11matrix_add3PfS_S_mm:
.quad _Z26__device_stub__matrix_add3PfS_S_mm
.size _Z11matrix_add3PfS_S_mm, 8
.type _Z11matrix_add2PfS_S_m,@object # @_Z11matrix_add2PfS_S_m
.globl _Z11matrix_add2PfS_S_m
.p2align 3, 0x0
_Z11matrix_add2PfS_S_m:
.quad _Z26__device_stub__matrix_add2PfS_S_m
.size _Z11matrix_add2PfS_S_m, 8
.type _Z10matrix_addPfS_S_m,@object # @_Z10matrix_addPfS_S_m
.globl _Z10matrix_addPfS_S_m
.p2align 3, 0x0
_Z10matrix_addPfS_S_m:
.quad _Z25__device_stub__matrix_addPfS_S_m
.size _Z10matrix_addPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11matrix_add3PfS_S_mm"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11matrix_add2PfS_S_m"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10matrix_addPfS_S_m"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_add3PfS_S_mm
.addrsig_sym _Z26__device_stub__matrix_add2PfS_S_m
.addrsig_sym _Z25__device_stub__matrix_addPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_add3PfS_S_mm
.addrsig_sym _Z11matrix_add2PfS_S_m
.addrsig_sym _Z10matrix_addPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10matrix_addPfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*0080*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f1e0ff */
/*00b0*/ IADD3 R2, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f3e0ff */
/*00c0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00d0*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc80000ffe4ff */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe200007fe4ff */
/*0120*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11matrix_add2PfS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R11, R11, c[0x0][0xc], R0 ; /* 0x000003000b0b7a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fc80003f06100 */
/*0060*/ ISETP.EQ.OR P0, PT, RZ, c[0x0][0xc], P0 ; /* 0x00000300ff007a0c */
/* 0x000fda0000702670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R8, P0, R11.reuse, c[0x0][0xc], RZ ; /* 0x000003000b087a10 */
/* 0x040fe20007f1e0ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*00a0*/ IADD3 R3, P1, R11, 0x1, RZ ; /* 0x000000010b037810 */
/* 0x000fe20007f3e0ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ BSSY B0, 0x430 ; /* 0x0000036000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.X R9, RZ, RZ, RZ, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e06ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe20003f04070 */
/*00f0*/ IMAD.X R6, RZ, RZ, R0, P1 ; /* 0x000000ffff067224 */
/* 0x000fe200008e0600 */
/*0100*/ IADD3 R2, P1, R11, -c[0x0][0x178], RZ ; /* 0x80005e000b027a10 */
/* 0x000fc80007f3e0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, R9, PT, P0 ; /* 0x000000090600720c */
/* 0x000fc80003f04100 */
/*0120*/ SEL R4, R3, R8, P0 ; /* 0x0000000803047207 */
/* 0x000fe40000000000 */
/*0130*/ SEL R7, R6, R9, P0 ; /* 0x0000000906077207 */
/* 0x000fe40000000000 */
/*0140*/ IADD3 R5, P0, -R4, R11, RZ ; /* 0x0000000b04057210 */
/* 0x000fe40007f1e1ff */
/*0150*/ IADD3.X R3, R0, ~c[0x0][0x17c], RZ, P1, !PT ; /* 0x80005f0000037a10 */
/* 0x000fc60000ffe4ff */
/*0160*/ IMAD.X R4, R0, 0x1, ~R7, P0 ; /* 0x0000000100047824 */
/* 0x000fe200000e0e07 */
/*0170*/ ISETP.GT.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fc80003f04070 */
/*0180*/ ISETP.GT.U32.AND.EX P0, PT, R4, R3, PT, P0 ; /* 0x000000030400720c */
/* 0x000fc80003f04100 */
/*0190*/ SEL R5, R5, R2, P0 ; /* 0x0000000205057207 */
/* 0x000fe40000000000 */
/*01a0*/ SEL R3, R4, R3, P0 ; /* 0x0000000304037207 */
/* 0x000fe40000000000 */
/*01b0*/ ISETP.GT.U32.AND P0, PT, R5, -0x4, PT ; /* 0xfffffffc0500780c */
/* 0x000fe20003f04070 */
/*01c0*/ IMAD.MOV R2, RZ, RZ, -R5 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0a05 */
/*01d0*/ ISETP.GT.U32.AND.EX P0, PT, R3, -0x1, PT, P0 ; /* 0xffffffff0300780c */
/* 0x000fe40003f04100 */
/*01e0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fc800078ec0ff */
/*01f0*/ ISETP.NE.U32.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f25070 */
/*0200*/ ISETP.NE.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fda0003f25310 */
/*0210*/ @!P1 BRA 0x420 ; /* 0x0000020000009947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.SHL.U32 R12, R11.reuse, 0x4, RZ ; /* 0x000000040b0c7824 */
/* 0x040fe200078e00ff */
/*0230*/ IADD3 R6, P4, RZ, -R2, RZ ; /* 0x80000002ff067210 */
/* 0x000fe40007f9e0ff */
/*0240*/ SHF.L.U64.HI R13, R11, 0x2, R0 ; /* 0x000000020b0d7819 */
/* 0x000fe40000010200 */
/*0250*/ IADD3 R15, P1, R12.reuse, c[0x0][0x170], RZ ; /* 0x00005c000c0f7a10 */
/* 0x040fe20007f3e0ff */
/*0260*/ IMAD.X R10, RZ, RZ, -0x1, P4 ; /* 0xffffffffff0a7424 */
/* 0x000fe200020e06ff */
/*0270*/ IADD3 R14, P2, R12.reuse, c[0x0][0x168], RZ ; /* 0x00005a000c0e7a10 */
/* 0x040fe40007f5e0ff */
/*0280*/ IADD3 R12, P3, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fe40007f7e0ff */
/*0290*/ IADD3.X R16, R13, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d000d107a10 */
/* 0x000fc40000ffe4ff */
/*02a0*/ IADD3.X R5, R13.reuse, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b000d057a10 */
/* 0x040fe400017fe4ff */
/*02b0*/ IADD3.X R13, R13, c[0x0][0x164], RZ, P3, !PT ; /* 0x000059000d0d7a10 */
/* 0x000fc60001ffe4ff */
/*02c0*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x001fe400078e000d */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*02f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0000a8000c1e1900 */
/*0300*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0002a2000c1e1900 */
/*0310*/ IADD3 R6, P1, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fc40007f3e0ff */
/*0320*/ IADD3 R11, P2, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007f5e0ff */
/*0330*/ IADD3 R14, P4, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007f9e0ff */
/*0340*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*0350*/ ISETP.NE.U32.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25070 */
/*0360*/ IMAD.X R0, RZ, RZ, R0, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0600 */
/*0370*/ IADD3 R12, P5, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007fbe0ff */
/*0380*/ IMAD.MOV.U32 R2, RZ, RZ, R15 ; /* 0x000000ffff027224 */
/* 0x002fe200078e000f */
/*0390*/ ISETP.NE.AND.EX P1, PT, R10, RZ, PT, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe20003f25310 */
/*03a0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x001fe200020e0605 */
/*03b0*/ IADD3 R15, P3, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe20007f7e0ff */
/*03c0*/ IMAD.X R13, RZ, RZ, R13, P5 ; /* 0x000000ffff0d7224 */
/* 0x000fc400028e060d */
/*03d0*/ FADD R7, R4, R3 ; /* 0x0000000304077221 */
/* 0x004fe40000000000 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, R16.reuse ; /* 0x000000ffff037224 */
/* 0x100fe400078e0010 */
/*03f0*/ IMAD.X R16, RZ, RZ, R16, P3 ; /* 0x000000ffff107224 */
/* 0x000fc600018e0610 */
/*0400*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0410*/ @P1 BRA 0x2c0 ; /* 0xfffffea000001947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0440*/ IMAD.SHL.U32 R2, R11.reuse, 0x4, RZ ; /* 0x000000040b027824 */
/* 0x041fe200078e00ff */
/*0450*/ SHF.L.U64.HI R3, R11, 0x2, R0 ; /* 0x000000020b037819 */
/* 0x000fc80000010200 */
/*0460*/ IADD3 R6, P0, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002067a10 */
/* 0x040fe40007f1e0ff */
/*0470*/ IADD3 R4, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fe40007f3e0ff */
/*0480*/ IADD3.X R7, R3.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003077a10 */
/* 0x040fe400007fe4ff */
/*0490*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003057a10 */
/* 0x000fc60000ffe4ff */
/*04a0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IADD3 R2, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fc80007f1e0ff */
/*04d0*/ IADD3.X R3, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003037a10 */
/* 0x000fe200007fe4ff */
/*04e0*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x004fca0000000000 */
/*04f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0500*/ LDG.E R10, [R6.64+0x4] ; /* 0x00000404060a7981 */
/* 0x000ea8000c1e1900 */
/*0510*/ LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f7981 */
/* 0x000ea4000c1e1900 */
/*0520*/ FADD R15, R10, R15 ; /* 0x0000000f0a0f7221 */
/* 0x004fca0000000000 */
/*0530*/ STG.E [R2.64+0x4], R15 ; /* 0x0000040f02007986 */
/* 0x0001e8000c101904 */
/*0540*/ LDG.E R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080404117981 */
/* 0x000ea4000c1e1900 */
/*0560*/ FADD R17, R10, R17 ; /* 0x000000110a117221 */
/* 0x004fca0000000000 */
/*0570*/ STG.E [R2.64+0x8], R17 ; /* 0x0000081102007986 */
/* 0x0001e8000c101904 */
/*0580*/ LDG.E R10, [R6.64+0xc] ; /* 0x00000c04060a7981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R19, [R4.64+0xc] ; /* 0x00000c0404137981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R11, P0, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc80007f1e0ff */
/*05b0*/ ISETP.GE.U32.AND P1, PT, R11.reuse, c[0x0][0x178], PT ; /* 0x00005e000b007a0c */
/* 0x040fe20003f26070 */
/*05c0*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R11, R8, PT ; /* 0x000000080b00720c */
/* 0x000fc80003f06070 */
/*05e0*/ ISETP.GE.U32.AND.EX P0, PT, R0.reuse, R9, PT, P0 ; /* 0x000000090000720c */
/* 0x040fe40003f06100 */
/*05f0*/ ISETP.GE.U32.AND.EX P1, PT, R0, c[0x0][0x17c], PT, P1 ; /* 0x00005f0000007a0c */
/* 0x000fe20003f26110 */
/*0600*/ FADD R19, R10, R19 ; /* 0x000000130a137221 */
/* 0x004fca0000000000 */
/*0610*/ STG.E [R2.64+0xc], R19 ; /* 0x00000c1302007986 */
/* 0x0001ee000c101904 */
/*0620*/ @!P0 BRA !P1, 0x440 ; /* 0xfffffe1000008947 */
/* 0x000fea000483ffff */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ BRA 0x640; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11matrix_add3PfS_S_mm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x041fe200078e00ff */
/*0090*/ SHF.L.U64.HI R7, R0, 0x2, R11 ; /* 0x0000000200077819 */
/* 0x000fe2000001020b */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P1, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f3e0ff */
/*00c0*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f1e0ff */
/*00d0*/ IADD3.X R5, R7.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590007057a10 */
/* 0x040fe40000ffe4ff */
/*00e0*/ IADD3.X R3, R7, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0007037a10 */
/* 0x000fc800007fe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R7, R7, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0007077a10 */
/* 0x000fe400007fe4ff */
/*0130*/ IADD3 R0, P0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fc80007f1e0ff */
/*0140*/ IADD3.X R11, R11, c[0x0][0x184], RZ, P0, !PT ; /* 0x000061000b0b7a10 */
/* 0x000fe400007fe4ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0160*/ ISETP.GE.U32.AND.EX P0, PT, R11, c[0x0][0x17c], PT, P0 ; /* 0x00005f000b007a0c */
/* 0x000fe20003f06100 */
/*0170*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0180*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*0190*/ @!P0 BRA 0x80 ; /* 0xfffffee000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_add3PfS_S_mm
.globl _Z11matrix_add3PfS_S_mm
.p2align 8
.type _Z11matrix_add3PfS_S_mm,@function
_Z11matrix_add3PfS_S_mm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_lshl_b64 s[12:13], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v1, vcc_lo, v1, s8
global_load_b32 v0, v[5:6], off
global_load_b32 v7, v[7:8], off
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[1:2]
v_add_co_u32 v3, s0, v3, s12
v_add_co_ci_u32_e64 v4, s0, s13, v4, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v7
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_add3PfS_S_mm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_add3PfS_S_mm, .Lfunc_end0-_Z11matrix_add3PfS_S_mm
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11matrix_add2PfS_S_m
.globl _Z11matrix_add2PfS_S_m
.p2align 8
.type _Z11matrix_add2PfS_S_m,@function
_Z11matrix_add2PfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, s15, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s4, v1, s4
v_add_co_ci_u32_e64 v4, null, 0, 0, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[3:4]
v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, s2, v3
v_cndmask_b32_e32 v4, s3, v4, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
v_cmpx_gt_u64_e64 v[3:4], v[1:2]
s_cbranch_execz .LBB1_3
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[9:10], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v10, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
.p2align 6
.LBB1_2:
global_load_b32 v0, v[9:10], off
global_load_b32 v11, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, 1
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, v7, 4
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_cmp_ge_u64_e32 vcc_lo, v[1:2], v[3:4]
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v11
global_store_b32 v[5:6], v0, off
v_add_co_u32 v5, s0, v5, 4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, 0, v6, s0
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_add2PfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11matrix_add2PfS_S_m, .Lfunc_end1-_Z11matrix_add2PfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10matrix_addPfS_S_m
.globl _Z10matrix_addPfS_S_m
.p2align 8
.type _Z10matrix_addPfS_S_m,@function
_Z10matrix_addPfS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrix_addPfS_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10matrix_addPfS_S_m, .Lfunc_end2-_Z10matrix_addPfS_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_add3PfS_S_mm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_add3PfS_S_mm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_add2PfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_add2PfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrix_addPfS_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrix_addPfS_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e1b22_00000000-6_matrix_add2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/palPrabhakar/tutorials/master/cuda/kirk_hwu/ch3/matrix_add2.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s in %s at line %d\n"
.text
.globl _Z13print_err_msg9cudaError
.type _Z13print_err_msg9cudaError, @function
_Z13print_err_msg9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $10, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13print_err_msg9cudaError, .-_Z13print_err_msg9cudaError
.globl _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm
.type _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm, @function
_Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11matrix_add3PfS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm, .-_Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm
.globl _Z11matrix_add3PfS_S_mm
.type _Z11matrix_add3PfS_S_mm, @function
_Z11matrix_add3PfS_S_mm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11matrix_add3PfS_S_mmPfS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11matrix_add3PfS_S_mm, .-_Z11matrix_add3PfS_S_mm
.globl _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
.type _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m, @function
_Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11matrix_add2PfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m, .-_Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
.globl _Z11matrix_add2PfS_S_m
.type _Z11matrix_add2PfS_S_m, @function
_Z11matrix_add2PfS_S_m:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z11matrix_add2PfS_S_m, .-_Z11matrix_add2PfS_S_m
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
leaq 24(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movl $0, %ebx
movss .LC2(%rip), %xmm2
movss .LC3(%rip), %xmm1
movss .LC4(%rip), %xmm0
.L26:
movss %xmm2, 0(%r13,%rbx,4)
movss %xmm1, (%r12,%rbx,4)
movss %xmm0, 0(%rbp,%rbx,4)
addq $1, %rbx
cmpq $1024, %rbx
jne .L26
movl $1, %ecx
movl $4096, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L27:
movl $2, %ecx
movl $4096, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
.L28:
subq $1, %rbx
jne .L28
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call _Z13print_err_msg9cudaError
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z36__device_stub__Z11matrix_add2PfS_S_mPfS_S_m
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.globl _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m
.type _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m, @function
_Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrix_addPfS_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m, .-_Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m
.globl _Z10matrix_addPfS_S_m
.type _Z10matrix_addPfS_S_m, @function
_Z10matrix_addPfS_S_m:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrix_addPfS_S_mPfS_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z10matrix_addPfS_S_m, .-_Z10matrix_addPfS_S_m
.section .rodata.str1.1
.LC5:
.string "_Z10matrix_addPfS_S_m"
.LC6:
.string "_Z11matrix_add2PfS_S_m"
.LC7:
.string "_Z11matrix_add3PfS_S_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrix_addPfS_S_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_add2PfS_S_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_add3PfS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.align 4
.LC4:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_add2.hip"
.globl _Z13print_err_msg10hipError_t # -- Begin function _Z13print_err_msg10hipError_t
.p2align 4, 0x90
.type _Z13print_err_msg10hipError_t,@function
_Z13print_err_msg10hipError_t: # @_Z13print_err_msg10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $12, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z13print_err_msg10hipError_t, .Lfunc_end0-_Z13print_err_msg10hipError_t
.cfi_endproc
# -- End function
.globl _Z26__device_stub__matrix_add3PfS_S_mm # -- Begin function _Z26__device_stub__matrix_add3PfS_S_mm
.p2align 4, 0x90
.type _Z26__device_stub__matrix_add3PfS_S_mm,@function
_Z26__device_stub__matrix_add3PfS_S_mm: # @_Z26__device_stub__matrix_add3PfS_S_mm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11matrix_add3PfS_S_mm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z26__device_stub__matrix_add3PfS_S_mm, .Lfunc_end1-_Z26__device_stub__matrix_add3PfS_S_mm
.cfi_endproc
# -- End function
.globl _Z26__device_stub__matrix_add2PfS_S_m # -- Begin function _Z26__device_stub__matrix_add2PfS_S_m
.p2align 4, 0x90
.type _Z26__device_stub__matrix_add2PfS_S_m,@function
_Z26__device_stub__matrix_add2PfS_S_m: # @_Z26__device_stub__matrix_add2PfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_add2PfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__matrix_add2PfS_S_m, .Lfunc_end2-_Z26__device_stub__matrix_add2PfS_S_m
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrix_addPfS_S_m # -- Begin function _Z25__device_stub__matrix_addPfS_S_m
.p2align 4, 0x90
.type _Z25__device_stub__matrix_addPfS_S_m,@function
_Z25__device_stub__matrix_addPfS_S_m: # @_Z25__device_stub__matrix_addPfS_S_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrix_addPfS_S_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__matrix_addPfS_S_m, .Lfunc_end3-_Z25__device_stub__matrix_addPfS_S_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB4_14
# %bb.1: # %_Z13print_err_msg10hipError_t.exit
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB4_14
# %bb.2: # %_Z13print_err_msg10hipError_t.exit45
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB4_14
# %bb.3: # %_Z13print_err_msg10hipError_t.exit47.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_4: # %_Z13print_err_msg10hipError_t.exit47
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
movl $1084227584, (%r15,%rax,4) # imm = 0x40A00000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB4_4
# %bb.5:
movq 24(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.6: # %_Z13print_err_msg10hipError_t.exit49
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.7: # %_Z13print_err_msg10hipError_t.exit51
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_9
# %bb.8:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq $1024, 80(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11matrix_add2PfS_S_m, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_9:
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_14
# %bb.10: # %_Z13print_err_msg10hipError_t.exit53.preheader
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_14
# %bb.11: # %_Z13print_err_msg10hipError_t.exit55
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_14
# %bb.12: # %_Z13print_err_msg10hipError_t.exit57
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB4_14
# %bb.13: # %_Z13print_err_msg10hipError_t.exit59
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_14:
.cfi_def_cfa_offset 176
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $12, %ecx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_add3PfS_S_mm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_add2PfS_S_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrix_addPfS_S_m, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s at line %d\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/palPrabhakar/tutorials/master/cuda/kirk_hwu/ch3/matrix_add2.hip"
.size .L.str.1, 121
.type _Z11matrix_add3PfS_S_mm,@object # @_Z11matrix_add3PfS_S_mm
.section .rodata,"a",@progbits
.globl _Z11matrix_add3PfS_S_mm
.p2align 3, 0x0
_Z11matrix_add3PfS_S_mm:
.quad _Z26__device_stub__matrix_add3PfS_S_mm
.size _Z11matrix_add3PfS_S_mm, 8
.type _Z11matrix_add2PfS_S_m,@object # @_Z11matrix_add2PfS_S_m
.globl _Z11matrix_add2PfS_S_m
.p2align 3, 0x0
_Z11matrix_add2PfS_S_m:
.quad _Z26__device_stub__matrix_add2PfS_S_m
.size _Z11matrix_add2PfS_S_m, 8
.type _Z10matrix_addPfS_S_m,@object # @_Z10matrix_addPfS_S_m
.globl _Z10matrix_addPfS_S_m
.p2align 3, 0x0
_Z10matrix_addPfS_S_m:
.quad _Z25__device_stub__matrix_addPfS_S_m
.size _Z10matrix_addPfS_S_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11matrix_add3PfS_S_mm"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11matrix_add2PfS_S_m"
.size .L__unnamed_2, 23
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10matrix_addPfS_S_m"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_add3PfS_S_mm
.addrsig_sym _Z26__device_stub__matrix_add2PfS_S_m
.addrsig_sym _Z25__device_stub__matrix_addPfS_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_add3PfS_S_mm
.addrsig_sym _Z11matrix_add2PfS_S_m
.addrsig_sym _Z10matrix_addPfS_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(int *a, int *b, int *c, int *d, int *e, int *f) {
*c = *a + *b;
*d = *a - *b;
*e = *a * *b;
*f = *a / *b;
} | code for sm_80
Function : _Z3addPiS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0060*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc400078e00ff */
/*00a0*/ IMAD.IADD R13, R0, 0x1, R9 ; /* 0x00000001000d7824 */
/* 0x004fca00078e0209 */
/*00b0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fc400078e00ff */
/*0100*/ IMAD.IADD R15, R0, 0x1, -R11 ; /* 0x00000001000f7824 */
/* 0x004fca00078e0a0b */
/*0110*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0003e8000c101904 */
/*0120*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0140*/ MOV R10, c[0x0][0x180] ; /* 0x00006000000a7a02 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff0b7624 */
/* 0x000fc400078e00ff */
/*0160*/ IMAD R17, R0, R17, RZ ; /* 0x0000001100117224 */
/* 0x004fca00078e02ff */
/*0170*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x000fe8000c101904 */
/*0180*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x001ea8000c1e1900 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x0000e2000c1e1900 */
/*01a0*/ IABS R19, R13.reuse ; /* 0x0000000d00137213 */
/* 0x084fe40000000000 */
/*01b0*/ IABS R3, R13 ; /* 0x0000000d00037213 */
/* 0x001fc40000000000 */
/*01c0*/ I2F.RP R12, R19 ; /* 0x00000013000c7306 */
/* 0x000e220000209400 */
/*01d0*/ IABS R2, R0 ; /* 0x0000000000027213 */
/* 0x008fe40000000000 */
/*01e0*/ IADD3 R3, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fe40007ffe0ff */
/*01f0*/ LOP3.LUT R0, R0, R13, RZ, 0x3c, !PT ; /* 0x0000000d00007212 */
/* 0x000fc800078e3cff */
/*0200*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f26270 */
/*0210*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R6, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c067810 */
/* 0x001fcc0007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0240*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0250*/ IADD3 R8, RZ, -R7, RZ ; /* 0x80000007ff087210 */
/* 0x002fca0007ffe0ff */
/*0260*/ IMAD R5, R8, R19, RZ ; /* 0x0000001308057224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0280*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD R2, R7, R3, R2 ; /* 0x0000000307027224 */
/* 0x000fe200078e0202 */
/*02a0*/ MOV R3, c[0x0][0x18c] ; /* 0x0000630000037a02 */
/* 0x000fc80000000f00 */
/*02b0*/ ISETP.GT.U32.AND P2, PT, R19, R2, PT ; /* 0x000000021300720c */
/* 0x000fda0003f44070 */
/*02c0*/ @!P2 IMAD.IADD R2, R2, 0x1, -R19 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a13 */
/*02d0*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*02f0*/ ISETP.GE.U32.AND P0, PT, R2, R19, PT ; /* 0x000000130200720c */
/* 0x000fe20003f06070 */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fd800078e00ff */
/*0310*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0320*/ @!P1 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07079210 */
/* 0x000fe40007ffe1ff */
/*0330*/ @!P2 LOP3.LUT R7, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff07a212 */
/* 0x000fca00078e33ff */
/*0340*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(int *a, int *b, int *c, int *d, int *e, int *f) {
*c = *a + *b;
*d = *a - *b;
*e = *a * *b;
*f = *a / *b;
} | .file "tmpxft_001b9237_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_
.type _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_, @function
_Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3addPiS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_, .-_Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_
.globl _Z3addPiS_S_S_S_S_
.type _Z3addPiS_S_S_S_S_, @function
_Z3addPiS_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_S_S_S_, .-_Z3addPiS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(int *a, int *b, int *c, int *d, int *e, int *f) {
*c = *a + *b;
*d = *a - *b;
*e = *a * *b;
*f = *a / *b;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c, int *d, int *e, int *f) {
*c = *a + *b;
*d = *a - *b;
*e = *a * *b;
*f = *a / *b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c, int *d, int *e, int *f) {
*c = *a + *b;
*d = *a - *b;
*e = *a * *b;
*f = *a / *b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_S_S_S_
.globl _Z3addPiS_S_S_S_S_
.p2align 8
.type _Z3addPiS_S_S_S_S_,@function
_Z3addPiS_S_S_S_S_:
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_load_b128 s[0:3], s[0:1], 0x20
global_store_b32 v0, v1, s[8:9]
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, v1, v2
global_store_b32 v0, v1, s[10:11]
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s0, v1
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
s_ashr_i32 s7, s4, 31
s_add_i32 s0, s0, s1
s_add_i32 s4, s4, s7
s_xor_b32 s0, s0, s1
s_xor_b32 s4, s4, s7
v_cvt_f32_u32_e32 v1, s0
s_sub_i32 s6, 0, s0
s_xor_b32 s1, s7, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v1
s_mul_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s5, s6
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_mul_i32 s6, s5, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, s4, s6
s_add_i32 s6, s5, 1
s_sub_i32 s7, s4, s0
s_cmp_ge_u32 s4, s0
s_cselect_b32 s5, s6, s5
s_cselect_b32 s4, s7, s4
s_add_i32 s6, s5, 1
s_cmp_ge_u32 s4, s0
s_cselect_b32 s0, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s1
s_sub_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_S_S_S_, .Lfunc_end0-_Z3addPiS_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c, int *d, int *e, int *f) {
*c = *a + *b;
*d = *a - *b;
*e = *a * *b;
*f = *a / *b;
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_S_S_S_ # -- Begin function _Z18__device_stub__addPiS_S_S_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_S_S_S_,@function
_Z18__device_stub__addPiS_S_S_S_S_: # @_Z18__device_stub__addPiS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_S_S_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_S_S_S_,@object # @_Z3addPiS_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_S_S_S_
.p2align 3, 0x0
_Z3addPiS_S_S_S_S_:
.quad _Z18__device_stub__addPiS_S_S_S_S_
.size _Z3addPiS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_S_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0060*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc400078e00ff */
/*00a0*/ IMAD.IADD R13, R0, 0x1, R9 ; /* 0x00000001000d7824 */
/* 0x004fca00078e0209 */
/*00b0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fc400078e00ff */
/*0100*/ IMAD.IADD R15, R0, 0x1, -R11 ; /* 0x00000001000f7824 */
/* 0x004fca00078e0a0b */
/*0110*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0003e8000c101904 */
/*0120*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea2000c1e1900 */
/*0140*/ MOV R10, c[0x0][0x180] ; /* 0x00006000000a7a02 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff0b7624 */
/* 0x000fc400078e00ff */
/*0160*/ IMAD R17, R0, R17, RZ ; /* 0x0000001100117224 */
/* 0x004fca00078e02ff */
/*0170*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x000fe8000c101904 */
/*0180*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x001ea8000c1e1900 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x0000e2000c1e1900 */
/*01a0*/ IABS R19, R13.reuse ; /* 0x0000000d00137213 */
/* 0x084fe40000000000 */
/*01b0*/ IABS R3, R13 ; /* 0x0000000d00037213 */
/* 0x001fc40000000000 */
/*01c0*/ I2F.RP R12, R19 ; /* 0x00000013000c7306 */
/* 0x000e220000209400 */
/*01d0*/ IABS R2, R0 ; /* 0x0000000000027213 */
/* 0x008fe40000000000 */
/*01e0*/ IADD3 R3, RZ, -R3, RZ ; /* 0x80000003ff037210 */
/* 0x000fe40007ffe0ff */
/*01f0*/ LOP3.LUT R0, R0, R13, RZ, 0x3c, !PT ; /* 0x0000000d00007212 */
/* 0x000fc800078e3cff */
/*0200*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f26270 */
/*0210*/ MUFU.RCP R12, R12 ; /* 0x0000000c000c7308 */
/* 0x001e240000001000 */
/*0220*/ IADD3 R6, R12, 0xffffffe, RZ ; /* 0x0ffffffe0c067810 */
/* 0x001fcc0007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0240*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0250*/ IADD3 R8, RZ, -R7, RZ ; /* 0x80000007ff087210 */
/* 0x002fca0007ffe0ff */
/*0260*/ IMAD R5, R8, R19, RZ ; /* 0x0000001308057224 */
/* 0x000fc800078e02ff */
/*0270*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fcc00078e0006 */
/*0280*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD R2, R7, R3, R2 ; /* 0x0000000307027224 */
/* 0x000fe200078e0202 */
/*02a0*/ MOV R3, c[0x0][0x18c] ; /* 0x0000630000037a02 */
/* 0x000fc80000000f00 */
/*02b0*/ ISETP.GT.U32.AND P2, PT, R19, R2, PT ; /* 0x000000021300720c */
/* 0x000fda0003f44070 */
/*02c0*/ @!P2 IMAD.IADD R2, R2, 0x1, -R19 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a13 */
/*02d0*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*02f0*/ ISETP.GE.U32.AND P0, PT, R2, R19, PT ; /* 0x000000130200720c */
/* 0x000fe20003f06070 */
/*0300*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fd800078e00ff */
/*0310*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fc80007ffe0ff */
/*0320*/ @!P1 IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07079210 */
/* 0x000fe40007ffe1ff */
/*0330*/ @!P2 LOP3.LUT R7, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff07a212 */
/* 0x000fca00078e33ff */
/*0340*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_S_S_S_
.globl _Z3addPiS_S_S_S_S_
.p2align 8
.type _Z3addPiS_S_S_S_S_,@function
_Z3addPiS_S_S_S_S_:
s_load_b256 s[4:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_load_b128 s[0:3], s[0:1], 0x20
global_store_b32 v0, v1, s[8:9]
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, v1, v2
global_store_b32 v0, v1, s[10:11]
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[4:5]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s0, v1
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
s_ashr_i32 s7, s4, 31
s_add_i32 s0, s0, s1
s_add_i32 s4, s4, s7
s_xor_b32 s0, s0, s1
s_xor_b32 s4, s4, s7
v_cvt_f32_u32_e32 v1, s0
s_sub_i32 s6, 0, s0
s_xor_b32 s1, s7, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v1
s_mul_i32 s6, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s5, s6
s_add_i32 s5, s5, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s4, s5
s_mul_i32 s6, s5, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s4, s4, s6
s_add_i32 s6, s5, 1
s_sub_i32 s7, s4, s0
s_cmp_ge_u32 s4, s0
s_cselect_b32 s5, s6, s5
s_cselect_b32 s4, s7, s4
s_add_i32 s6, s5, 1
s_cmp_ge_u32 s4, s0
s_cselect_b32 s0, s6, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s1
s_sub_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_S_S_S_, .Lfunc_end0-_Z3addPiS_S_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b9237_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_
.type _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_, @function
_Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3addPiS_S_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_, .-_Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_
.globl _Z3addPiS_S_S_S_S_
.type _Z3addPiS_S_S_S_S_, @function
_Z3addPiS_S_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z3addPiS_S_S_S_S_PiS_S_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_S_S_S_, .-_Z3addPiS_S_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_S_S_S_ # -- Begin function _Z18__device_stub__addPiS_S_S_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_S_S_S_,@function
_Z18__device_stub__addPiS_S_S_S_S_: # @_Z18__device_stub__addPiS_S_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_S_S_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_S_S_S_,@object # @_Z3addPiS_S_S_S_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_S_S_S_
.p2align 3, 0x0
_Z3addPiS_S_S_S_S_:
.quad _Z18__device_stub__addPiS_S_S_S_S_
.size _Z3addPiS_S_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_S_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern int f();
extern float* g();
extern void h();
__global__
void k1(float *a, int b) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
a[gid] += b;
}
void launches_k1(float *a) {
k1<<<8, 8>>>(a, 4);
k1<<<8, f()>>>(a, 4);
k1<<<f(), f()>>>(a, 4);
k1<<<f(), f()>>>(g(), f());
k1<<<f()+f(), f()*2>>>(g(), f()+f());
} | code for sm_80
Function : _Z2k1Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ I2F R0, c[0x0][0x168] ; /* 0x00005a0000007b06 */
/* 0x000ea40000201400 */
/*0090*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern int f();
extern float* g();
extern void h();
__global__
void k1(float *a, int b) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
a[gid] += b;
}
void launches_k1(float *a) {
k1<<<8, 8>>>(a, 4);
k1<<<8, f()>>>(a, 4);
k1<<<f(), f()>>>(a, 4);
k1<<<f(), f()>>>(g(), f());
k1<<<f()+f(), f()*2>>>(g(), f()+f());
} | .file "tmpxft_0015eca5_00000000-6_launches.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z2k1PfiPfi
.type _Z22__device_stub__Z2k1PfiPfi, @function
_Z22__device_stub__Z2k1PfiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2k1Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z22__device_stub__Z2k1PfiPfi, .-_Z22__device_stub__Z2k1PfiPfi
.globl _Z2k1Pfi
.type _Z2k1Pfi, @function
_Z2k1Pfi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z2k1PfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z2k1Pfi, .-_Z2k1Pfi
.globl _Z11launches_k1Pf
.type _Z11launches_k1Pf, @function
_Z11launches_k1Pf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
call _Z1fv@PLT
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call _Z1fv@PLT
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z1fv@PLT
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L14:
call _Z1fv@PLT
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z1fv@PLT
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
call _Z1fv@PLT
addl %eax, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z1fv@PLT
movl %eax, %ebx
call _Z1fv@PLT
addl %eax, %ebx
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $4, %esi
movq %rbx, %rdi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L12
.L19:
movl $4, %esi
movq %rbx, %rdi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L13
.L20:
movl $4, %esi
movq %rbx, %rdi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L14
.L21:
call _Z1fv@PLT
movl %eax, %ebx
call _Z1gv@PLT
movq %rax, %rdi
movl %ebx, %esi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L15
.L22:
call _Z1fv@PLT
movl %eax, %ebx
call _Z1fv@PLT
addl %eax, %ebx
call _Z1gv@PLT
movq %rax, %rdi
movl %ebx, %esi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11launches_k1Pf, .-_Z11launches_k1Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2k1Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2k1Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern int f();
extern float* g();
extern void h();
__global__
void k1(float *a, int b) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
a[gid] += b;
}
void launches_k1(float *a) {
k1<<<8, 8>>>(a, 4);
k1<<<8, f()>>>(a, 4);
k1<<<f(), f()>>>(a, 4);
k1<<<f(), f()>>>(g(), f());
k1<<<f()+f(), f()*2>>>(g(), f()+f());
} | #include <hip/hip_runtime.h>
extern int f();
extern float* g();
extern void h();
__global__
void k1(float *a, int b) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
a[gid] += b;
}
void launches_k1(float *a) {
k1<<<8, 8>>>(a, 4);
k1<<<8, f()>>>(a, 4);
k1<<<f(), f()>>>(a, 4);
k1<<<f(), f()>>>(g(), f());
k1<<<f()+f(), f()*2>>>(g(), f()+f());
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern int f();
extern float* g();
extern void h();
__global__
void k1(float *a, int b) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
a[gid] += b;
}
void launches_k1(float *a) {
k1<<<8, 8>>>(a, 4);
k1<<<8, f()>>>(a, 4);
k1<<<f(), f()>>>(a, 4);
k1<<<f(), f()>>>(g(), f());
k1<<<f()+f(), f()*2>>>(g(), f()+f());
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2k1Pfi
.globl _Z2k1Pfi
.p2align 8
.type _Z2k1Pfi,@function
_Z2k1Pfi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_i32_e32 v3, s0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2k1Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2k1Pfi, .Lfunc_end0-_Z2k1Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2k1Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2k1Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern int f();
extern float* g();
extern void h();
__global__
void k1(float *a, int b) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
a[gid] += b;
}
void launches_k1(float *a) {
k1<<<8, 8>>>(a, 4);
k1<<<8, f()>>>(a, 4);
k1<<<f(), f()>>>(a, 4);
k1<<<f(), f()>>>(g(), f());
k1<<<f()+f(), f()*2>>>(g(), f()+f());
} | .text
.file "launches.hip"
.globl _Z17__device_stub__k1Pfi # -- Begin function _Z17__device_stub__k1Pfi
.p2align 4, 0x90
.type _Z17__device_stub__k1Pfi,@function
_Z17__device_stub__k1Pfi: # @_Z17__device_stub__k1Pfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z17__device_stub__k1Pfi, .Lfunc_end0-_Z17__device_stub__k1Pfi
.cfi_endproc
# -- End function
.globl _Z11launches_k1Pf # -- Begin function _Z11launches_k1Pf
.p2align 4, 0x90
.type _Z11launches_k1Pf,@function
_Z11launches_k1Pf: # @_Z11launches_k1Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 8(%r14), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 56(%rsp)
movl $4, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq _Z1fv
movl %eax, %edx
orq %r14, %rdx
leaq 8(%r14), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %rbx, 56(%rsp)
movl $4, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq _Z1fv
movl %eax, %ebp
callq _Z1fv
movl %ebp, %edi
orq %r14, %rdi
movl %eax, %edx
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq %rbx, 56(%rsp)
movl $4, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq _Z1fv
movl %eax, %ebx
callq _Z1fv
movl %ebx, %edi
orq %r14, %rdi
movl %eax, %edx
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
callq _Z1gv
movq %rax, %rbx
callq _Z1fv
movq %rbx, 56(%rsp)
movl %eax, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq _Z1fv
movl %eax, %ebx
callq _Z1fv
addl %eax, %ebx
callq _Z1fv
# kill: def $eax killed $eax def $rax
leal (%rax,%rax), %edx
orq %r14, %rbx
orq %r14, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
callq _Z1gv
movq %rax, %rbx
callq _Z1fv
movl %eax, %ebp
callq _Z1fv
addl %ebp, %eax
movq %rbx, 56(%rsp)
movl %eax, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11launches_k1Pf, .Lfunc_end1-_Z11launches_k1Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2k1Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2k1Pfi,@object # @_Z2k1Pfi
.section .rodata,"a",@progbits
.globl _Z2k1Pfi
.p2align 3, 0x0
_Z2k1Pfi:
.quad _Z17__device_stub__k1Pfi
.size _Z2k1Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2k1Pfi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__k1Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2k1Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2k1Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ I2F R0, c[0x0][0x168] ; /* 0x00005a0000007b06 */
/* 0x000ea40000201400 */
/*0090*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2k1Pfi
.globl _Z2k1Pfi
.p2align 8
.type _Z2k1Pfi,@function
_Z2k1Pfi:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_i32_e32 v3, s0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2k1Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2k1Pfi, .Lfunc_end0-_Z2k1Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2k1Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2k1Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015eca5_00000000-6_launches.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z2k1PfiPfi
.type _Z22__device_stub__Z2k1PfiPfi, @function
_Z22__device_stub__Z2k1PfiPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2k1Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z22__device_stub__Z2k1PfiPfi, .-_Z22__device_stub__Z2k1PfiPfi
.globl _Z2k1Pfi
.type _Z2k1Pfi, @function
_Z2k1Pfi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z2k1PfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z2k1Pfi, .-_Z2k1Pfi
.globl _Z11launches_k1Pf
.type _Z11launches_k1Pf, @function
_Z11launches_k1Pf:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
call _Z1fv@PLT
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $8, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call _Z1fv@PLT
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z1fv@PLT
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L14:
call _Z1fv@PLT
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z1fv@PLT
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
call _Z1fv@PLT
addl %eax, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
call _Z1fv@PLT
movl %eax, %ebx
call _Z1fv@PLT
addl %eax, %ebx
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $4, %esi
movq %rbx, %rdi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L12
.L19:
movl $4, %esi
movq %rbx, %rdi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L13
.L20:
movl $4, %esi
movq %rbx, %rdi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L14
.L21:
call _Z1fv@PLT
movl %eax, %ebx
call _Z1gv@PLT
movq %rax, %rdi
movl %ebx, %esi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L15
.L22:
call _Z1fv@PLT
movl %eax, %ebx
call _Z1fv@PLT
addl %eax, %ebx
call _Z1gv@PLT
movq %rax, %rdi
movl %ebx, %esi
call _Z22__device_stub__Z2k1PfiPfi
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11launches_k1Pf, .-_Z11launches_k1Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2k1Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2k1Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "launches.hip"
.globl _Z17__device_stub__k1Pfi # -- Begin function _Z17__device_stub__k1Pfi
.p2align 4, 0x90
.type _Z17__device_stub__k1Pfi,@function
_Z17__device_stub__k1Pfi: # @_Z17__device_stub__k1Pfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z17__device_stub__k1Pfi, .Lfunc_end0-_Z17__device_stub__k1Pfi
.cfi_endproc
# -- End function
.globl _Z11launches_k1Pf # -- Begin function _Z11launches_k1Pf
.p2align 4, 0x90
.type _Z11launches_k1Pf,@function
_Z11launches_k1Pf: # @_Z11launches_k1Pf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 8(%r14), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 56(%rsp)
movl $4, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq _Z1fv
movl %eax, %edx
orq %r14, %rdx
leaq 8(%r14), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq %rbx, 56(%rsp)
movl $4, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq _Z1fv
movl %eax, %ebp
callq _Z1fv
movl %ebp, %edi
orq %r14, %rdi
movl %eax, %edx
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq %rbx, 56(%rsp)
movl $4, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq _Z1fv
movl %eax, %ebx
callq _Z1fv
movl %ebx, %edi
orq %r14, %rdi
movl %eax, %edx
orq %r14, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
callq _Z1gv
movq %rax, %rbx
callq _Z1fv
movq %rbx, 56(%rsp)
movl %eax, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq _Z1fv
movl %eax, %ebx
callq _Z1fv
addl %eax, %ebx
callq _Z1fv
# kill: def $eax killed $eax def $rax
leal (%rax,%rax), %edx
orq %r14, %rbx
orq %r14, %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
callq _Z1gv
movq %rax, %rbx
callq _Z1fv
movl %eax, %ebp
callq _Z1fv
addl %ebp, %eax
movq %rbx, 56(%rsp)
movl %eax, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2k1Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11launches_k1Pf, .Lfunc_end1-_Z11launches_k1Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2k1Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2k1Pfi,@object # @_Z2k1Pfi
.section .rodata,"a",@progbits
.globl _Z2k1Pfi
.p2align 3, 0x0
_Z2k1Pfi:
.quad _Z17__device_stub__k1Pfi
.size _Z2k1Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2k1Pfi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__k1Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2k1Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(int *memory, int *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ int temp;
int temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(int *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
//memory[tid]++;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(int *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N*N/(16*16) ;k++)
memory[k]=5;
}
}
void verify(int* memory, int N)
{
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(int* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
__global__ void pollute_L2_cache(int *junk)
{
int tid=threadIdx.x+blockDim.x*blockIdx.x;
junk[tid]= 5 & 0xDEADBEEF;
}
int
main( int argc, char *argv[] )
{
int *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1024;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int pollute = 0;
while ((opt = getopt(argc, argv, "m:b:i:r:p")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'p':
pollute = 1;
break;
default: /* '?' */
break;
}
}
cpuMallocd = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16));
assert(cpuMallocd);
HANDLE_ERROR( cudaHostAlloc( &hostAllocd, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
int *junk;
HANDLE_ERROR( cudaHostAlloc( &junk, sizeof(int)*512*64, 0 ) );
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
hostAllocd[k]=1;
}
HANDLE_ERROR( cudaMalloc( &cudaMallocd, sizeof(int)*numBytes) );
HANDLE_ERROR( cudaMemcpy( cudaMallocd,hostAllocd, sizeof(int)*numBytes,cudaMemcpyDefault) );
//int num_of_blocks=1;
//int num_of_threads_per_block=numBytes;
//if(numBytes>1024){
// num_of_blocks = 16;
// num_of_threads_per_block = numBytes/16;
//}
int num_of_blocks,num_of_threads_per_block;
// if(numBytes==1)
// {
// num_of_blocks=1;
// num_of_threads_per_block=1;
// }
// else
// {
// assert(numBytes%2==0);
// num_of_blocks=2;
// num_of_threads_per_block=numBytes/2;
// }
num_of_blocks=numBytes/16;
num_of_threads_per_block=numBytes/16;
//HANDLE_ERROR(cudaDeviceReset()); //this causes kernel launch failure!! check with cuda-memcheck
HANDLE_ERROR(cudaFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( cudaHostAlloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFreeHost(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verify(hostAllocd,numBytes);
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 1: {//read/Write to cudaMalloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( cudaMalloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16) ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( cudaDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
case 3: {//read/Write to cpu mallocd data
if(read)
{
int temp;
int *memoryToRead = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16) );
assert(memoryToRead);
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int j=0; j<numBytes*numBytes/(16*16); j++){
temp=memoryToRead[j];
if(!temp)
cpuMallocd[j]=temp;
}
}
gettimeofday(&tv2, NULL);
free(memoryToRead);
//verify(cpuMallocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
cpuMallocd[k]=5;
}
gettimeofday(&tv2, NULL);
verify(cpuMallocd,numBytes);
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
}
free(cpuMallocd);
cudaFree(cudaMallocd);
cudaFreeHost(hostAllocd);
cudaFreeHost(junk);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z16pollute_L2_cachePi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x5 ; /* 0x0000000500077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17verifyCudaMallocdPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0050*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fc8000f8e023f */
/*0060*/ USHF.R.U32.HI UR4, URZ, 0x8, UR4 ; /* 0x000000083f047899 */
/* 0x000fcc0008011604 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*0080*/ @!P0 BRA 0x130 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R2, 0x5, PT ; /* 0x000000050200780c */
/* 0x004fda0003f05270 */
/*00f0*/ @P0 BRA 0x210 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0120*/ @!P0 BRA 0xb0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0130*/ MOV R0, 0x10 ; /* 0x0000001000007802 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0150*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0170*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0180*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0190*/ MOV R11, 0x200 ; /* 0x00000200000b7802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R20, 0x180 ; /* 0x0000018000147802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*01d0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01e0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01f0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ MOV R0, 0x10 ; /* 0x0000001000007802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0230*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe200078e00ff */
/*0250*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0260*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0270*/ MOV R11, 0x2e0 ; /* 0x000002e0000b7802 */
/* 0x000fe40000000f00 */
/*0280*/ MOV R20, 0x260 ; /* 0x0000026000147802 */
/* 0x000fe40000000f00 */
/*0290*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*02b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*02c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*02d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15initCudaMallocdPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fc800078e00ff */
/*0050*/ IMAD R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a24 */
/* 0x000fca00078e02ff */
/*0060*/ SHF.R.U32.HI R0, RZ, 0x8, R0 ; /* 0x00000008ff007819 */
/* 0x000fc80000011600 */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00b0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe200078ec0ff */
/*00c0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*00e0*/ @!P0 BRA 0x530 ; /* 0x0000044000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100007824 */
/* 0x000fe200078e0a05 */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GT.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f04270 */
/*0140*/ @!P0 BRA 0x460 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0x320 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x5 ; /* 0x00000005ff097424 */
/* 0x000fc800078e00ff */
/*01a0*/ IADD3 R0, R0, -0x10, RZ ; /* 0xfffffff000007810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101908 */
/*01c0*/ IADD3 R4, P2, R2, 0x40, RZ ; /* 0x0000004002047810 */
/* 0x000fe20007f5e0ff */
/*01d0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*01e0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe20003f24270 */
/*01f0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe4000c101908 */
/*0200*/ IMAD.X R7, RZ, RZ, R3, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0603 */
/*0210*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101908 */
/*0220*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x000fe8000c101908 */
/*0230*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x000fe8000c101908 */
/*0240*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101908 */
/*0250*/ STG.E [R2.64+0x18], R9 ; /* 0x0000180902007986 */
/* 0x000fe8000c101908 */
/*0260*/ STG.E [R2.64+0x1c], R9 ; /* 0x00001c0902007986 */
/* 0x000fe8000c101908 */
/*0270*/ STG.E [R2.64+0x20], R9 ; /* 0x0000200902007986 */
/* 0x000fe8000c101908 */
/*0280*/ STG.E [R2.64+0x24], R9 ; /* 0x0000240902007986 */
/* 0x000fe8000c101908 */
/*0290*/ STG.E [R2.64+0x28], R9 ; /* 0x0000280902007986 */
/* 0x000fe8000c101908 */
/*02a0*/ STG.E [R2.64+0x2c], R9 ; /* 0x00002c0902007986 */
/* 0x000fe8000c101908 */
/*02b0*/ STG.E [R2.64+0x30], R9 ; /* 0x0000300902007986 */
/* 0x000fe8000c101908 */
/*02c0*/ STG.E [R2.64+0x34], R9 ; /* 0x0000340902007986 */
/* 0x000fe8000c101908 */
/*02d0*/ STG.E [R2.64+0x38], R9 ; /* 0x0000380902007986 */
/* 0x000fe8000c101908 */
/*02e0*/ STG.E [R2.64+0x3c], R9 ; /* 0x00003c0902007986 */
/* 0x0001e4000c101908 */
/*02f0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*0300*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0310*/ @P1 BRA 0x1a0 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*0320*/ ISETP.GT.AND P1, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fda0003f24270 */
/*0330*/ @!P1 BRA 0x440 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R4, P1, R2, 0x20, RZ ; /* 0x0000002002047810 */
/* 0x000fe20007f3e0ff */
/*0350*/ IMAD.MOV.U32 R9, RZ, RZ, 0x5 ; /* 0x00000005ff097424 */
/* 0x000fe200078e00ff */
/*0360*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0370*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0380*/ IADD3 R0, R0, -0x8, RZ ; /* 0xfffffff800007810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0603 */
/*03a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101908 */
/*03b0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe8000c101908 */
/*03c0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101908 */
/*03d0*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x000fe8000c101908 */
/*03e0*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x000fe8000c101908 */
/*03f0*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101908 */
/*0400*/ STG.E [R2.64+0x18], R9 ; /* 0x0000180902007986 */
/* 0x000fe8000c101908 */
/*0410*/ STG.E [R2.64+0x1c], R9 ; /* 0x00001c0902007986 */
/* 0x0001e4000c101908 */
/*0420*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*0430*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0440*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0450*/ @!P0 BRA 0x530 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0460*/ IMAD.MOV.U32 R9, RZ, RZ, 0x5 ; /* 0x00000005ff097424 */
/* 0x000fc800078e00ff */
/*0470*/ IADD3 R0, R0, -0x4, RZ ; /* 0xfffffffc00007810 */
/* 0x000fe20007ffe0ff */
/*0480*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101908 */
/*0490*/ IADD3 R4, P1, R2, 0x10, RZ ; /* 0x0000001002047810 */
/* 0x000fe20007f3e0ff */
/*04a0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*04b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*04c0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe4000c101908 */
/*04d0*/ IMAD.X R7, RZ, RZ, R3, P1 ; /* 0x000000ffff077224 */
/* 0x000fe400008e0603 */
/*04e0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101908 */
/*04f0*/ STG.E [R2.64+0xc], R9 ; /* 0x00000c0902007986 */
/* 0x0001e4000c101908 */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0004 */
/*0510*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0007 */
/*0520*/ @P0 BRA 0x470 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0530*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0540*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0550*/ IMAD.MOV.U32 R7, RZ, RZ, 0x5 ; /* 0x00000005ff077424 */
/* 0x000fe200078e00ff */
/*0560*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0570*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*0580*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fca000f8e0206 */
/*0590*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x001fe2000f8e00ff */
/*05b0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*05d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*05e0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc400087fe43f */
/*05f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001f2000c101908 */
/*0600*/ @P0 BRA 0x590 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10nullKernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11writeKernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x5 ; /* 0x0000000500077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0070*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10readKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e9900 */
/*0080*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(int *memory, int *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ int temp;
int temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(int *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
//memory[tid]++;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(int *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N*N/(16*16) ;k++)
memory[k]=5;
}
}
void verify(int* memory, int N)
{
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(int* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
__global__ void pollute_L2_cache(int *junk)
{
int tid=threadIdx.x+blockDim.x*blockIdx.x;
junk[tid]= 5 & 0xDEADBEEF;
}
int
main( int argc, char *argv[] )
{
int *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1024;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int pollute = 0;
while ((opt = getopt(argc, argv, "m:b:i:r:p")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'p':
pollute = 1;
break;
default: /* '?' */
break;
}
}
cpuMallocd = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16));
assert(cpuMallocd);
HANDLE_ERROR( cudaHostAlloc( &hostAllocd, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
int *junk;
HANDLE_ERROR( cudaHostAlloc( &junk, sizeof(int)*512*64, 0 ) );
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
hostAllocd[k]=1;
}
HANDLE_ERROR( cudaMalloc( &cudaMallocd, sizeof(int)*numBytes) );
HANDLE_ERROR( cudaMemcpy( cudaMallocd,hostAllocd, sizeof(int)*numBytes,cudaMemcpyDefault) );
//int num_of_blocks=1;
//int num_of_threads_per_block=numBytes;
//if(numBytes>1024){
// num_of_blocks = 16;
// num_of_threads_per_block = numBytes/16;
//}
int num_of_blocks,num_of_threads_per_block;
// if(numBytes==1)
// {
// num_of_blocks=1;
// num_of_threads_per_block=1;
// }
// else
// {
// assert(numBytes%2==0);
// num_of_blocks=2;
// num_of_threads_per_block=numBytes/2;
// }
num_of_blocks=numBytes/16;
num_of_threads_per_block=numBytes/16;
//HANDLE_ERROR(cudaDeviceReset()); //this causes kernel launch failure!! check with cuda-memcheck
HANDLE_ERROR(cudaFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( cudaHostAlloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFreeHost(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verify(hostAllocd,numBytes);
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 1: {//read/Write to cudaMalloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( cudaMalloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16) ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( cudaDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
case 3: {//read/Write to cpu mallocd data
if(read)
{
int temp;
int *memoryToRead = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16) );
assert(memoryToRead);
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int j=0; j<numBytes*numBytes/(16*16); j++){
temp=memoryToRead[j];
if(!temp)
cpuMallocd[j]=temp;
}
}
gettimeofday(&tv2, NULL);
free(memoryToRead);
//verify(cpuMallocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
cpuMallocd[k]=5;
}
gettimeofday(&tv2, NULL);
verify(cpuMallocd,numBytes);
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
}
free(cpuMallocd);
cudaFree(cudaMallocd);
cudaFreeHost(hostAllocd);
cudaFreeHost(junk);
cudaDeviceReset();
return 0;
} | .file "tmpxft_0009b848_00000000-6_latencyTest.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2070:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "verified SUCCESS\n"
.LC2:
.string "error in verification\n"
.text
.globl _Z6verifyPii
.type _Z6verifyPii, @function
_Z6verifyPii:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
imull %esi, %esi
leal 255(%rsi), %edx
testl %esi, %esi
cmovns %esi, %edx
sarl $8, %edx
cmpl $255, %esi
jle .L10
movl $0, %eax
.L12:
cmpl $5, (%rdi,%rax,4)
jne .L11
addq $1, %rax
cmpl %eax, %edx
jg .L12
.L10:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L9:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L9
.cfi_endproc
.LFE2072:
.size _Z6verifyPii, .-_Z6verifyPii
.globl _Z32__device_stub__Z10readKernelPiS_PiS_
.type _Z32__device_stub__Z10readKernelPiS_PiS_, @function
_Z32__device_stub__Z10readKernelPiS_PiS_:
.LFB2098:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10readKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z32__device_stub__Z10readKernelPiS_PiS_, .-_Z32__device_stub__Z10readKernelPiS_PiS_
.globl _Z10readKernelPiS_
.type _Z10readKernelPiS_, @function
_Z10readKernelPiS_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10readKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z10readKernelPiS_, .-_Z10readKernelPiS_
.globl _Z31__device_stub__Z11writeKernelPiPi
.type _Z31__device_stub__Z11writeKernelPiPi, @function
_Z31__device_stub__Z11writeKernelPiPi:
.LFB2100:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11writeKernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z31__device_stub__Z11writeKernelPiPi, .-_Z31__device_stub__Z11writeKernelPiPi
.globl _Z11writeKernelPi
.type _Z11writeKernelPi, @function
_Z11writeKernelPi:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11writeKernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z11writeKernelPi, .-_Z11writeKernelPi
.globl _Z30__device_stub__Z10nullKernelPiPi
.type _Z30__device_stub__Z10nullKernelPiPi, @function
_Z30__device_stub__Z10nullKernelPiPi:
.LFB2102:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10nullKernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z30__device_stub__Z10nullKernelPiPi, .-_Z30__device_stub__Z10nullKernelPiPi
.globl _Z10nullKernelPi
.type _Z10nullKernelPi, @function
_Z10nullKernelPi:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10nullKernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z10nullKernelPi, .-_Z10nullKernelPi
.globl _Z36__device_stub__Z15initCudaMallocdPiiPii
.type _Z36__device_stub__Z15initCudaMallocdPiiPii, @function
_Z36__device_stub__Z15initCudaMallocdPiiPii:
.LFB2104:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15initCudaMallocdPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z36__device_stub__Z15initCudaMallocdPiiPii, .-_Z36__device_stub__Z15initCudaMallocdPiiPii
.globl _Z15initCudaMallocdPii
.type _Z15initCudaMallocdPii, @function
_Z15initCudaMallocdPii:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15initCudaMallocdPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z15initCudaMallocdPii, .-_Z15initCudaMallocdPii
.globl _Z38__device_stub__Z17verifyCudaMallocdPiiPii
.type _Z38__device_stub__Z17verifyCudaMallocdPiiPii, @function
_Z38__device_stub__Z17verifyCudaMallocdPiiPii:
.LFB2106:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17verifyCudaMallocdPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z38__device_stub__Z17verifyCudaMallocdPiiPii, .-_Z38__device_stub__Z17verifyCudaMallocdPiiPii
.globl _Z17verifyCudaMallocdPii
.type _Z17verifyCudaMallocdPii, @function
_Z17verifyCudaMallocdPii:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z17verifyCudaMallocdPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z17verifyCudaMallocdPii, .-_Z17verifyCudaMallocdPii
.globl _Z36__device_stub__Z16pollute_L2_cachePiPi
.type _Z36__device_stub__Z16pollute_L2_cachePiPi, @function
_Z36__device_stub__Z16pollute_L2_cachePiPi:
.LFB2108:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16pollute_L2_cachePi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _Z36__device_stub__Z16pollute_L2_cachePiPi, .-_Z36__device_stub__Z16pollute_L2_cachePiPi
.globl _Z16pollute_L2_cachePi
.type _Z16pollute_L2_cachePi, @function
_Z16pollute_L2_cachePi:
.LFB2109:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16pollute_L2_cachePiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _Z16pollute_L2_cachePi, .-_Z16pollute_L2_cachePi
.section .rodata.str1.1
.LC3:
.string "read"
.LC4:
.string "write"
.LC5:
.string "m:b:i:r:p"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/mkdashti/bandwidthTest/master/latency-ints/latencyTest.cu"
.align 8
.LC8:
.string "[%s] Latency including kernel launch overhead = %f us\n"
.align 8
.LC9:
.string "null kernel launch overhead = %f us\n"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %r13d
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
movl $0, 8(%rsp)
movl $0, 4(%rsp)
movl $1024, %ebp
movl $100000, %ebx
leaq .LC5(%rip), %r15
leaq .L68(%rip), %r14
jmp .L65
.L70:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebp
.L65:
movq %r15, %rdx
movq %r12, %rsi
movl %r13d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L149
subl $98, %eax
cmpl $16, %eax
ja .L65
movl %eax, %eax
movslq (%r14,%rax,4), %rax
addq %r14, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L68:
.long .L72-.L68
.long .L65-.L68
.long .L65-.L68
.long .L65-.L68
.long .L65-.L68
.long .L65-.L68
.long .L65-.L68
.long .L71-.L68
.long .L65-.L68
.long .L65-.L68
.long .L65-.L68
.long .L70-.L68
.long .L65-.L68
.long .L65-.L68
.long .L128-.L68
.long .L65-.L68
.long .L67-.L68
.text
.L72:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
jmp .L65
.L71:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L65
.L67:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
jmp .L65
.L128:
movl $1, 12(%rsp)
jmp .L65
.L149:
movslq %ebp, %r13
movq %r13, %rax
imulq %r13, %rax
salq $2, %rax
shrq $8, %rax
movq %rax, %r15
movq %rax, %rdi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $0, %edx
movq %r15, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $134, %edx
leaq .LC6(%rip), %r14
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 32(%rsp), %rdi
movl $0, %edx
movl $131072, %esi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $136, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
testl %ebp, %ebp
jle .L74
leaq 0(,%r13,4), %rcx
movl $0, %eax
.L75:
movl $1, (%r12,%rax)
movq 16(%rsp), %rdx
movl $1, (%rdx,%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L75
.L74:
salq $2, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $142, %edx
leaq .LC6(%rip), %r14
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $4, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $143, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
leal 15(%rbp), %r13d
testl %ebp, %ebp
cmovns %ebp, %r13d
sarl $4, %r13d
movl $0, %edi
call cudaFree@PLT
movl %eax, %edi
movl $166, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 8(%rsp), %eax
cmpl $2, %eax
je .L76
jg .L77
testl %eax, %eax
je .L78
cmpl $1, %eax
jne .L80
cmpl $0, 4(%rsp)
je .L97
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $215, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L150
.L98:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $217, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
jle .L99
movl $0, %ebp
leaq .LC6(%rip), %r14
jmp .L103
.L77:
cmpl $3, 8(%rsp)
jne .L80
.L81:
cmpl $0, 4(%rsp)
je .L114
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
imull %ebp, %ebp
movl $256, %ecx
movl %ebp, %eax
cltd
idivl %ecx
movl %eax, %r14d
cmpl $255, %ebp
jle .L115
movl $0, %eax
.L116:
movl $5, 0(%r13,%rax,4)
addq $1, %rax
cmpl %eax, %r14d
jg .L116
.L115:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %edx
testl %ebx, %ebx
jg .L117
.L118:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq %r13, %rdi
call free@PLT
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
.L122:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L80:
movq %r12, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
call cudaDeviceReset@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L151
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
cmpl $0, 4(%rsp)
je .L82
leaq 40(%rsp), %rdi
movl $0, %edx
movq %r15, %rsi
call cudaHostAlloc@PLT
movl %eax, %edi
movl $173, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
imull %ebp, %ebp
movl $256, %ecx
movl %ebp, %eax
cltd
idivl %ecx
cmpl $255, %ebp
jle .L83
movl $0, %edx
.L84:
movq 40(%rsp), %rcx
movl $5, (%rcx,%rdx,4)
addq $1, %rdx
cmpl %edx, %eax
jg .L84
.L83:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
jle .L85
leaq .LC6(%rip), %rbp
jmp .L89
.L153:
movl $64, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L152
.L87:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $180, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
jmp .L86
.L152:
movq 32(%rsp), %rdi
call _Z36__device_stub__Z16pollute_L2_cachePiPi
jmp .L87
.L88:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $183, %edx
movq %rbp, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, 8(%rsp)
movl 8(%rsp), %eax
cmpl %eax, %ebx
je .L85
.L89:
cmpl $0, 12(%rsp)
jne .L153
.L86:
movl %r13d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L88
movq 40(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z10readKernelPiS_PiS_
jmp .L88
.L85:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
.L90:
call cudaGetLastError@PLT
movl %eax, %edi
movl $204, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L80
.L82:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
jle .L91
movl 4(%rsp), %ebp
leaq .LC6(%rip), %r14
jmp .L95
.L155:
movl $64, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L154
.L93:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $195, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
jmp .L92
.L154:
movq 32(%rsp), %rdi
call _Z36__device_stub__Z16pollute_L2_cachePiPi
jmp .L93
.L94:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $199, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %ebp
cmpl %ebp, %ebx
je .L91
.L95:
cmpl $0, 12(%rsp)
jne .L155
.L92:
movl %r13d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L94
movq 16(%rsp), %rdi
call _Z31__device_stub__Z11writeKernelPiPi
jmp .L94
.L91:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L90
.L150:
movl %ebp, %esi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z15initCudaMallocdPiiPii
jmp .L98
.L157:
movl $64, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L156
.L101:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $222, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
jmp .L100
.L156:
movq 32(%rsp), %rdi
call _Z36__device_stub__Z16pollute_L2_cachePiPi
jmp .L101
.L102:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $226, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %ebp
cmpl %ebp, %ebx
je .L99
.L103:
cmpl $0, 12(%rsp)
jne .L157
.L100:
movl %r13d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L102
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10readKernelPiS_PiS_
jmp .L102
.L99:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
.L104:
call cudaGetLastError@PLT
movl %eax, %edi
movl $249, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
cmpl $1, 4(%rsp)
leaq .LC4(%rip), %rdx
leaq .LC3(%rip), %rax
cmove %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L80
.L97:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
jle .L105
movl 4(%rsp), %ebp
leaq .LC6(%rip), %r14
jmp .L109
.L159:
movl $64, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L158
.L107:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $239, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
jmp .L106
.L158:
movq 32(%rsp), %rdi
call _Z36__device_stub__Z16pollute_L2_cachePiPi
jmp .L107
.L108:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $243, %edx
movq %r14, %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %ebp
cmpl %ebp, %ebx
je .L105
.L109:
cmpl $0, 12(%rsp)
jne .L159
.L106:
movl %r13d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L108
movq 24(%rsp), %rdi
call _Z31__device_stub__Z11writeKernelPiPi
jmp .L108
.L105:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L104
.L76:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
jle .L111
movl $0, %r14d
jmp .L113
.L112:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $260, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
addl $1, %r14d
cmpl %r14d, %ebx
je .L111
.L113:
movl %r13d, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl %r13d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L112
movl $0, %edi
call _Z30__device_stub__Z10nullKernelPiPi
jmp .L112
.L111:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $263, %edx
leaq .LC6(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
movsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
addsd %xmm2, %xmm0
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L81
.L119:
addq $1, %rax
cmpl %eax, %r14d
jle .L121
.L120:
cmpl $0, 0(%r13,%rax,4)
jne .L119
movl $0, (%r12,%rax,4)
jmp .L119
.L121:
addl $1, %edx
cmpl %edx, %ebx
je .L118
.L117:
movl $0, %eax
cmpl $255, %ebp
jg .L120
jmp .L121
.L114:
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
testl %ebx, %ebx
jle .L123
movl %ebp, %ecx
imull %ebp, %ecx
movl $256, %esi
movl %ecx, %eax
cltd
idivl %esi
jmp .L124
.L125:
movl $5, (%r12,%rdx,4)
addq $1, %rdx
cmpl %edx, %eax
jg .L125
.L126:
addl $1, 4(%rsp)
movl 4(%rsp), %esi
cmpl %esi, %ebx
je .L123
.L124:
movl $0, %edx
cmpl $255, %ecx
jg .L125
jmp .L126
.L123:
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebp, %esi
movq %r12, %rdi
call _Z6verifyPii
movq 88(%rsp), %rax
subq 72(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
movsd .LC7(%rip), %xmm2
divsd %xmm2, %xmm1
movq 80(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
leaq .LC4(%rip), %rdx
jmp .L122
.L151:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z16pollute_L2_cachePi"
.LC11:
.string "_Z17verifyCudaMallocdPii"
.LC12:
.string "_Z15initCudaMallocdPii"
.LC13:
.string "_Z10nullKernelPi"
.LC14:
.string "_Z11writeKernelPi"
.LC15:
.string "_Z10readKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2111:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z16pollute_L2_cachePi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z17verifyCudaMallocdPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z15initCudaMallocdPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z10nullKernelPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z11writeKernelPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z10readKernelPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2111:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
static void HandleError( cudaError_t err, const char *file, int line ) {
if (err != cudaSuccess) {
printf( "%s in %s at line %d\n", cudaGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(int *memory, int *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ int temp;
int temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(int *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
//memory[tid]++;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(int *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N*N/(16*16) ;k++)
memory[k]=5;
}
}
void verify(int* memory, int N)
{
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(int* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
__global__ void pollute_L2_cache(int *junk)
{
int tid=threadIdx.x+blockDim.x*blockIdx.x;
junk[tid]= 5 & 0xDEADBEEF;
}
int
main( int argc, char *argv[] )
{
int *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1024;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int pollute = 0;
while ((opt = getopt(argc, argv, "m:b:i:r:p")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'p':
pollute = 1;
break;
default: /* '?' */
break;
}
}
cpuMallocd = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16));
assert(cpuMallocd);
HANDLE_ERROR( cudaHostAlloc( &hostAllocd, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
int *junk;
HANDLE_ERROR( cudaHostAlloc( &junk, sizeof(int)*512*64, 0 ) );
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
hostAllocd[k]=1;
}
HANDLE_ERROR( cudaMalloc( &cudaMallocd, sizeof(int)*numBytes) );
HANDLE_ERROR( cudaMemcpy( cudaMallocd,hostAllocd, sizeof(int)*numBytes,cudaMemcpyDefault) );
//int num_of_blocks=1;
//int num_of_threads_per_block=numBytes;
//if(numBytes>1024){
// num_of_blocks = 16;
// num_of_threads_per_block = numBytes/16;
//}
int num_of_blocks,num_of_threads_per_block;
// if(numBytes==1)
// {
// num_of_blocks=1;
// num_of_threads_per_block=1;
// }
// else
// {
// assert(numBytes%2==0);
// num_of_blocks=2;
// num_of_threads_per_block=numBytes/2;
// }
num_of_blocks=numBytes/16;
num_of_threads_per_block=numBytes/16;
//HANDLE_ERROR(cudaDeviceReset()); //this causes kernel launch failure!! check with cuda-memcheck
HANDLE_ERROR(cudaFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( cudaHostAlloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFreeHost(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verify(hostAllocd,numBytes);
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 1: {//read/Write to cudaMalloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( cudaMalloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16) ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( cudaDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
cudaFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( cudaDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( cudaDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( cudaGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
case 3: {//read/Write to cpu mallocd data
if(read)
{
int temp;
int *memoryToRead = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16) );
assert(memoryToRead);
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int j=0; j<numBytes*numBytes/(16*16); j++){
temp=memoryToRead[j];
if(!temp)
cpuMallocd[j]=temp;
}
}
gettimeofday(&tv2, NULL);
free(memoryToRead);
//verify(cpuMallocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
cpuMallocd[k]=5;
}
gettimeofday(&tv2, NULL);
verify(cpuMallocd,numBytes);
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
}
free(cpuMallocd);
cudaFree(cudaMallocd);
cudaFreeHost(hostAllocd);
cudaFreeHost(junk);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(int *memory, int *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ int temp;
int temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(int *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
//memory[tid]++;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(int *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N*N/(16*16) ;k++)
memory[k]=5;
}
}
void verify(int* memory, int N)
{
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(int* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
__global__ void pollute_L2_cache(int *junk)
{
int tid=threadIdx.x+blockDim.x*blockIdx.x;
junk[tid]= 5 & 0xDEADBEEF;
}
int
main( int argc, char *argv[] )
{
int *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1024;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int pollute = 0;
while ((opt = getopt(argc, argv, "m:b:i:r:p")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'p':
pollute = 1;
break;
default: /* '?' */
break;
}
}
cpuMallocd = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16));
assert(cpuMallocd);
HANDLE_ERROR( hipHostAlloc( &hostAllocd, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
int *junk;
HANDLE_ERROR( hipHostAlloc( &junk, sizeof(int)*512*64, 0 ) );
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
hostAllocd[k]=1;
}
HANDLE_ERROR( hipMalloc( &cudaMallocd, sizeof(int)*numBytes) );
HANDLE_ERROR( hipMemcpy( cudaMallocd,hostAllocd, sizeof(int)*numBytes,hipMemcpyDefault) );
//int num_of_blocks=1;
//int num_of_threads_per_block=numBytes;
//if(numBytes>1024){
// num_of_blocks = 16;
// num_of_threads_per_block = numBytes/16;
//}
int num_of_blocks,num_of_threads_per_block;
// if(numBytes==1)
// {
// num_of_blocks=1;
// num_of_threads_per_block=1;
// }
// else
// {
// assert(numBytes%2==0);
// num_of_blocks=2;
// num_of_threads_per_block=numBytes/2;
// }
num_of_blocks=numBytes/16;
num_of_threads_per_block=numBytes/16;
//HANDLE_ERROR(cudaDeviceReset()); //this causes kernel launch failure!! check with cuda-memcheck
HANDLE_ERROR(hipFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( hipHostAlloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
hipHostFree(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verify(hostAllocd,numBytes);
}
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 1: {//read/Write to cudaMalloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( hipMalloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16) ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( hipDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
hipFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
case 3: {//read/Write to cpu mallocd data
if(read)
{
int temp;
int *memoryToRead = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16) );
assert(memoryToRead);
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int j=0; j<numBytes*numBytes/(16*16); j++){
temp=memoryToRead[j];
if(!temp)
cpuMallocd[j]=temp;
}
}
gettimeofday(&tv2, NULL);
free(memoryToRead);
//verify(cpuMallocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
cpuMallocd[k]=5;
}
gettimeofday(&tv2, NULL);
verify(cpuMallocd,numBytes);
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
}
free(cpuMallocd);
hipFree(cudaMallocd);
hipHostFree(hostAllocd);
hipHostFree(junk);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdio.h>
#include <assert.h>
#include <sys/time.h>
#include <time.h>
static void HandleError( hipError_t err, const char *file, int line ) {
if (err != hipSuccess) {
printf( "%s in %s at line %d\n", hipGetErrorString( err ), file, line );
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
#define HANDLE_NULL( a ) {if (a == NULL) { \
printf( "Host memory failed in %s at line %d\n", \
__FILE__, __LINE__ ); \
exit( EXIT_FAILURE );}}
inline double diff_s(struct timeval start, struct timeval end)
{
return ((double) (end.tv_usec - start.tv_usec) / 1000000 + (double) (end.tv_sec - start.tv_sec));
}
__global__ void readKernel(int *memory, int *memoryToRead)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
//memory[tid]=memoryToRead[tid];
//__shared__ int temp;
int temp = memoryToRead[tid];
if(!temp)
__syncthreads();
}
__global__ void writeKernel(int *memory)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
memory[tid]=5;
//memory[tid]++;
}
__global__ void nullKernel(int *memory)
{
}
__global__ void initCudaMallocd(int *memory, int N)
{
int tid =threadIdx.x;
if(tid==0){
for(int k=0;k< N*N/(16*16) ;k++)
memory[k]=5;
}
}
void verify(int* memory, int N)
{
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
__global__ void verifyCudaMallocd(int* memory, int N)
{
int tid=threadIdx.x;
if(tid==0) {
int error = 0;
for(int i =0; i<N*N/(16*16); i++){
if(memory[i]!=5){
error = 1;
break;
}
}
if(error)
printf("error in verification\n");
else
printf("verified SUCCESS\n");
}
}
__global__ void pollute_L2_cache(int *junk)
{
int tid=threadIdx.x+blockDim.x*blockIdx.x;
junk[tid]= 5 & 0xDEADBEEF;
}
int
main( int argc, char *argv[] )
{
int *hostAllocd, *cudaMallocd, *cpuMallocd;
int ITERATIONS = 100000;
int numBytes = 1024;
struct timeval tv1, tv2;
int opt;
int read=0; //read benchmark? or write?
int benchmarkType = 0;
int pollute = 0;
while ((opt = getopt(argc, argv, "m:b:i:r:p")) != -1) {
switch (opt) {
case 'm':
numBytes = atoi(optarg);
//assert(numBytes%16 == 0 && numBytes<=1024);
break;
case 'b':
benchmarkType = atoi(optarg);
break;
case 'i':
ITERATIONS = atoi(optarg);
break;
case 'r':
read = atoi(optarg);
break;
case 'p':
pollute = 1;
break;
default: /* '?' */
break;
}
}
cpuMallocd = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16));
assert(cpuMallocd);
HANDLE_ERROR( hipHostAlloc( &hostAllocd, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
int *junk;
HANDLE_ERROR( hipHostAlloc( &junk, sizeof(int)*512*64, 0 ) );
for(int k=0;k< numBytes ;k++){
cpuMallocd[k]=1;
hostAllocd[k]=1;
}
HANDLE_ERROR( hipMalloc( &cudaMallocd, sizeof(int)*numBytes) );
HANDLE_ERROR( hipMemcpy( cudaMallocd,hostAllocd, sizeof(int)*numBytes,hipMemcpyDefault) );
//int num_of_blocks=1;
//int num_of_threads_per_block=numBytes;
//if(numBytes>1024){
// num_of_blocks = 16;
// num_of_threads_per_block = numBytes/16;
//}
int num_of_blocks,num_of_threads_per_block;
// if(numBytes==1)
// {
// num_of_blocks=1;
// num_of_threads_per_block=1;
// }
// else
// {
// assert(numBytes%2==0);
// num_of_blocks=2;
// num_of_threads_per_block=numBytes/2;
// }
num_of_blocks=numBytes/16;
num_of_threads_per_block=numBytes/16;
//HANDLE_ERROR(cudaDeviceReset()); //this causes kernel launch failure!! check with cuda-memcheck
HANDLE_ERROR(hipFree(0));
switch (benchmarkType) {
case 0: {//read/Write to hostAlloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( hipHostAlloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16), 0 ) );
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd,memoryToRead);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
hipHostFree(memoryToRead);
//verify(hostAllocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(hostAllocd);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verify(hostAllocd,numBytes);
}
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 1: {//read/Write to cudaMalloc'd data
if(read)
{
int *memoryToRead;
HANDLE_ERROR( hipMalloc( &memoryToRead, sizeof(int)*numBytes*numBytes/(16*16) ) );
initCudaMallocd<<<1,1>>>(memoryToRead,numBytes);
HANDLE_ERROR( hipDeviceSynchronize());
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
readKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd,memoryToRead);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
hipFree(memoryToRead);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
if(pollute) {
pollute_L2_cache<<<512,64>>>(junk);
HANDLE_ERROR( hipDeviceSynchronize());
}
writeKernel<<<num_of_blocks,num_of_threads_per_block>>>(cudaMallocd);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
//verifyCudaMallocd<<<1,1>>>(cudaMallocd,numBytes);
//HANDLE_ERROR( cudaDeviceSynchronize());
}
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
case 2:
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
nullKernel<<<num_of_blocks,num_of_threads_per_block>>>(0);
HANDLE_ERROR( hipDeviceSynchronize());
}
gettimeofday(&tv2, NULL);
HANDLE_ERROR( hipGetLastError());
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("null kernel launch overhead = %f us\n",elapsedTimeSeconds*1e6/(float)ITERATIONS);
}
case 3: {//read/Write to cpu mallocd data
if(read)
{
int temp;
int *memoryToRead = (int *)malloc(sizeof(int)*numBytes*numBytes/(16*16) );
assert(memoryToRead);
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
memoryToRead[k]=5;
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int j=0; j<numBytes*numBytes/(16*16); j++){
temp=memoryToRead[j];
if(!temp)
cpuMallocd[j]=temp;
}
}
gettimeofday(&tv2, NULL);
free(memoryToRead);
//verify(cpuMallocd,numBytes);
}
else
{
gettimeofday(&tv1, NULL);
for(int i = 0; i < ITERATIONS; i++) {
for(int k=0;k< numBytes*numBytes/(16*16) ;k++)
cpuMallocd[k]=5;
}
gettimeofday(&tv2, NULL);
verify(cpuMallocd,numBytes);
}
double elapsedTimeSeconds = diff_s(tv1,tv2);
printf("[%s] Latency including kernel launch overhead = %f us\n",(read==1)?"read":"write",elapsedTimeSeconds*1e6/(float)ITERATIONS);
break;
}
}
free(cpuMallocd);
hipFree(cudaMallocd);
hipHostFree(hostAllocd);
hipHostFree(junk);
hipDeviceReset();
return 0;
} | .text
.file "latencyTest.hip"
.globl _Z25__device_stub__readKernelPiS_ # -- Begin function _Z25__device_stub__readKernelPiS_
.p2align 4, 0x90
.type _Z25__device_stub__readKernelPiS_,@function
_Z25__device_stub__readKernelPiS_: # @_Z25__device_stub__readKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10readKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__readKernelPiS_, .Lfunc_end0-_Z25__device_stub__readKernelPiS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__writeKernelPi # -- Begin function _Z26__device_stub__writeKernelPi
.p2align 4, 0x90
.type _Z26__device_stub__writeKernelPi,@function
_Z26__device_stub__writeKernelPi: # @_Z26__device_stub__writeKernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11writeKernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z26__device_stub__writeKernelPi, .Lfunc_end1-_Z26__device_stub__writeKernelPi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__nullKernelPi # -- Begin function _Z25__device_stub__nullKernelPi
.p2align 4, 0x90
.type _Z25__device_stub__nullKernelPi,@function
_Z25__device_stub__nullKernelPi: # @_Z25__device_stub__nullKernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10nullKernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z25__device_stub__nullKernelPi, .Lfunc_end2-_Z25__device_stub__nullKernelPi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__initCudaMallocdPii # -- Begin function _Z30__device_stub__initCudaMallocdPii
.p2align 4, 0x90
.type _Z30__device_stub__initCudaMallocdPii,@function
_Z30__device_stub__initCudaMallocdPii: # @_Z30__device_stub__initCudaMallocdPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15initCudaMallocdPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z30__device_stub__initCudaMallocdPii, .Lfunc_end3-_Z30__device_stub__initCudaMallocdPii
.cfi_endproc
# -- End function
.globl _Z6verifyPii # -- Begin function _Z6verifyPii
.p2align 4, 0x90
.type _Z6verifyPii,@function
_Z6verifyPii: # @_Z6verifyPii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
movq %rdi, %rax
imull %esi, %esi
movl $.Lstr, %edi
cmpl $256, %esi # imm = 0x100
jb puts@PLT # TAILCALL
# %bb.1: # %.lr.ph.preheader
shrl $8, %esi
cmpl $1, %esi
adcl $0, %esi
xorl %ecx, %ecx
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_2: # in Loop: Header=BB4_3 Depth=1
incq %rcx
cmpq %rcx, %rsi
je puts@PLT # TAILCALL
.LBB4_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpl $5, (%rax,%rcx,4)
je .LBB4_2
# %bb.4:
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end4:
.size _Z6verifyPii, .Lfunc_end4-_Z6verifyPii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__verifyCudaMallocdPii # -- Begin function _Z32__device_stub__verifyCudaMallocdPii
.p2align 4, 0x90
.type _Z32__device_stub__verifyCudaMallocdPii,@function
_Z32__device_stub__verifyCudaMallocdPii: # @_Z32__device_stub__verifyCudaMallocdPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17verifyCudaMallocdPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z32__device_stub__verifyCudaMallocdPii, .Lfunc_end5-_Z32__device_stub__verifyCudaMallocdPii
.cfi_endproc
# -- End function
.globl _Z31__device_stub__pollute_L2_cachePi # -- Begin function _Z31__device_stub__pollute_L2_cachePi
.p2align 4, 0x90
.type _Z31__device_stub__pollute_L2_cachePi,@function
_Z31__device_stub__pollute_L2_cachePi: # @_Z31__device_stub__pollute_L2_cachePi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16pollute_L2_cachePi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end6:
.size _Z31__device_stub__pollute_L2_cachePi, .Lfunc_end6-_Z31__device_stub__pollute_L2_cachePi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %r13d
movl $100000, %eax # imm = 0x186A0
movq %rax, 80(%rsp) # 8-byte Spill
movl $1024, %r12d # imm = 0x400
xorl %ebp, %ebp
movb $1, %bl
xorl %r14d, %r14d
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_2: # in Loop: Header=BB7_1 Depth=1
cmpl $-1, %eax
je .LBB7_3
.LBB7_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edx
movl %r13d, %edi
movq %r15, %rsi
callq getopt
# kill: def $eax killed $eax def $rax
leal -98(%rax), %ecx
cmpl $16, %ecx
ja .LBB7_2
# %bb.6: # in Loop: Header=BB7_1 Depth=1
jmpq *.LJTI7_0(,%rcx,8)
.LBB7_8: # in Loop: Header=BB7_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
jmp .LBB7_1
.LBB7_10: # in Loop: Header=BB7_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB7_1
.LBB7_7: # in Loop: Header=BB7_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB7_1
.LBB7_11: # in Loop: Header=BB7_1 Depth=1
xorl %ebx, %ebx
jmp .LBB7_1
.LBB7_9: # in Loop: Header=BB7_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 80(%rsp) # 8-byte Spill
jmp .LBB7_1
.LBB7_3:
movq %r14, 112(%rsp) # 8-byte Spill
movslq %r12d, %r13
leaq (,%r13,4), %r14
imulq %r14, %r13
shrq $8, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
leaq 128(%rsp), %rdi
movq %r13, %rsi
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB7_4
# %bb.12: # %_ZL11HandleError10hipError_tPKci.exit
leaq 120(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB7_130
# %bb.13: # %_ZL11HandleError10hipError_tPKci.exit201.preheader
testl %r12d, %r12d
jle .LBB7_16
# %bb.14: # %.lr.ph
movq 128(%rsp), %rax
movl %r12d, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_15: # %_ZL11HandleError10hipError_tPKci.exit201
# =>This Inner Loop Header: Depth=1
movl $1, (%r15,%rdx,4)
movl $1, (%rax,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB7_15
.LBB7_16: # %_ZL11HandleError10hipError_tPKci.exit201._crit_edge
leaq 136(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_17
# %bb.18: # %_ZL11HandleError10hipError_tPKci.exit203
movq 136(%rsp), %rdi
movq 128(%rsp), %rsi
movq %r14, %rdx
movl $4, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_19
# %bb.20: # %_ZL11HandleError10hipError_tPKci.exit205
leal 15(%r12), %r14d
testl %r12d, %r12d
cmovnsl %r12d, %r14d
xorl %edi, %edi
callq hipFree
testl %eax, %eax
jne .LBB7_21
# %bb.22: # %_ZL11HandleError10hipError_tPKci.exit207
cmpl $3, %ebp
ja .LBB7_129
# %bb.23: # %_ZL11HandleError10hipError_tPKci.exit207
sarl $4, %r14d
movl %ebp, %eax
movq 80(%rsp), %rbp # 8-byte Reload
jmpq *.LJTI7_1(,%rax,8)
.LBB7_24:
cmpl $0, 112(%rsp) # 4-byte Folded Reload
je .LBB7_44
# %bb.25:
leaq 104(%rsp), %rdi
movq %r13, %rsi
xorl %edx, %edx
callq hipHostAlloc
testl %eax, %eax
jne .LBB7_131
# %bb.26: # %_ZL11HandleError10hipError_tPKci.exit209.preheader
imull %r12d, %r12d
cmpl $256, %r12d # imm = 0x100
jb .LBB7_29
# %bb.27: # %.lr.ph385
shrl $8, %r12d
movq 104(%rsp), %rax
cmpl $1, %r12d
adcl $0, %r12d
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_28: # %_ZL11HandleError10hipError_tPKci.exit209
# =>This Inner Loop Header: Depth=1
movl $5, (%rax,%rcx,4)
incq %rcx
cmpq %rcx, %r12
jne .LBB7_28
.LBB7_29: # %_ZL11HandleError10hipError_tPKci.exit209._crit_edge
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jle .LBB7_37
# %bb.30: # %.lr.ph388
movabsq $4294967296, %r12 # imm = 0x100000000
movl %r14d, %r13d
orq %r12, %r13
leaq 64(%r12), %rbp
addq $512, %r12 # imm = 0x200
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
.p2align 4, 0x90
.LBB7_31: # =>This Inner Loop Header: Depth=1
testb $1, %bl
jne .LBB7_40
# %bb.32: # in Loop: Header=BB7_31 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_34
# %bb.33: # in Loop: Header=BB7_31 Depth=1
movq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z16pollute_L2_cachePi, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_34: # in Loop: Header=BB7_31 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_35
.LBB7_40: # %_ZL11HandleError10hipError_tPKci.exit211
# in Loop: Header=BB7_31 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_42
# %bb.41: # in Loop: Header=BB7_31 Depth=1
movq 128(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 8(%rsp)
leaq 48(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z10readKernelPiS_, %edi
movq %rsp, %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_42: # %_ZL11HandleError10hipError_tPKci.exit219
# in Loop: Header=BB7_31 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_43
# %bb.36: # in Loop: Header=BB7_31 Depth=1
decl %r14d
jne .LBB7_31
.LBB7_37: # %._crit_edge389
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq 104(%rsp), %rdi
callq hipHostFree
jmp .LBB7_38
.LBB7_92:
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jle .LBB7_98
# %bb.93: # %.lr.ph362
movl %r14d, %eax
movabsq $4294967296, %r14 # imm = 0x100000000
orq %rax, %r14
leaq 16(%rsp), %rbx
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, %ebp
.p2align 4, 0x90
.LBB7_94: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_96
# %bb.95: # in Loop: Header=BB7_94 Depth=1
movq $0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10nullKernelPi, %edi
movq %rbx, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_96: # %_ZL11HandleError10hipError_tPKci.exit291
# in Loop: Header=BB7_94 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_100
# %bb.97: # in Loop: Header=BB7_94 Depth=1
decl %ebp
jne .LBB7_94
.LBB7_98: # %._crit_edge
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
callq hipGetLastError
testl %eax, %eax
jne .LBB7_99
# %bb.101: # %_ZL11HandleError10hipError_tPKci.exit283
movq 8(%rsp), %rax
subq 96(%rsp), %rax
movq (%rsp), %rcx
cvtsi2sd %rax, %xmm1
movsd .LCPI7_0(%rip), %xmm2 # xmm2 = mem[0],zero
subq 88(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd %xmm2, %xmm1
movq 80(%rsp), %rbp # 8-byte Reload
cvtsi2ss %ebp, %xmm3
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
.LBB7_102:
movq 112(%rsp), %r14 # 8-byte Reload
testl %r14d, %r14d
je .LBB7_115
# %bb.103:
movq %r13, %rdi
callq malloc
movq %rax, %r14
imull %r12d, %r12d
movl %r12d, %ebx
shrl $8, %ebx
cmpl $256, %r12d # imm = 0x100
jb .LBB7_106
# %bb.104: # %.lr.ph365.preheader
cmpl $1, %ebx
movl %ebx, %eax
adcl $0, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_105: # %.lr.ph365
# =>This Inner Loop Header: Depth=1
movl $5, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB7_105
.LBB7_106: # %._crit_edge366
xorl %r13d, %r13d
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jle .LBB7_114
# %bb.107: # %.preheader350.lr.ph
cmpl $1, %ebx
adcl $0, %ebx
jmp .LBB7_108
.p2align 4, 0x90
.LBB7_113: # %._crit_edge369
# in Loop: Header=BB7_108 Depth=1
incl %r13d
cmpl %ebp, %r13d
je .LBB7_114
.LBB7_108: # %.preheader350
# =>This Loop Header: Depth=1
# Child Loop BB7_110 Depth 2
cmpl $256, %r12d # imm = 0x100
jb .LBB7_113
# %bb.109: # %.lr.ph368.preheader
# in Loop: Header=BB7_108 Depth=1
xorl %eax, %eax
jmp .LBB7_110
.p2align 4, 0x90
.LBB7_112: # in Loop: Header=BB7_110 Depth=2
incq %rax
cmpq %rax, %rbx
je .LBB7_113
.LBB7_110: # %.lr.ph368
# Parent Loop BB7_108 Depth=1
# => This Inner Loop Header: Depth=2
cmpl $0, (%r14,%rax,4)
jne .LBB7_112
# %bb.111: # in Loop: Header=BB7_110 Depth=2
movl $0, (%r15,%rax,4)
jmp .LBB7_112
.LBB7_114: # %._crit_edge371
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq %r14, %rdi
callq free
movq 112(%rsp), %r14 # 8-byte Reload
jmp .LBB7_128
.LBB7_57:
cmpl $0, 112(%rsp) # 4-byte Folded Reload
je .LBB7_79
# %bb.58:
leaq 104(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB7_59
# %bb.60: # %_ZL11HandleError10hipError_tPKci.exit239
movabsq $4294967296, %r13 # imm = 0x100000000
leaq 1(%r13), %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_62
# %bb.61:
movq 104(%rsp), %rax
movq %rax, 64(%rsp)
movl %r12d, 16(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 16(%rsp), %rax
movq %rax, 8(%rsp)
leaq 88(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movq %rsp, %r9
movl $_Z15initCudaMallocdPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_62:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_63
# %bb.64: # %_ZL11HandleError10hipError_tPKci.exit247
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jle .LBB7_72
# %bb.65: # %.lr.ph378
movl %r14d, %r12d
orq %r13, %r12
leaq 64(%r13), %rbp
addq $512, %r13 # imm = 0x200
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
.p2align 4, 0x90
.LBB7_66: # =>This Inner Loop Header: Depth=1
testb $1, %bl
jne .LBB7_75
# %bb.67: # in Loop: Header=BB7_66 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_69
# %bb.68: # in Loop: Header=BB7_66 Depth=1
movq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z16pollute_L2_cachePi, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_69: # in Loop: Header=BB7_66 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_70
.LBB7_75: # %_ZL11HandleError10hipError_tPKci.exit255
# in Loop: Header=BB7_66 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_77
# %bb.76: # in Loop: Header=BB7_66 Depth=1
movq 136(%rsp), %rax
movq 104(%rsp), %rcx
movq %rax, 40(%rsp)
movq %rcx, 32(%rsp)
leaq 40(%rsp), %rax
movq %rax, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 8(%rsp)
leaq 48(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 144(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z10readKernelPiS_, %edi
movq %rsp, %r9
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_77: # %_ZL11HandleError10hipError_tPKci.exit263
# in Loop: Header=BB7_66 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_78
# %bb.71: # in Loop: Header=BB7_66 Depth=1
decl %r14d
jne .LBB7_66
.LBB7_72: # %._crit_edge379
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq 104(%rsp), %rdi
callq hipFree
jmp .LBB7_73
.LBB7_115:
xorl %ebx, %ebx
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jle .LBB7_121
# %bb.116: # %.preheader.lr.ph
movl %r12d, %eax
imull %r12d, %eax
movl %eax, %ecx
shrl $8, %ecx
cmpl $1, %ecx
adcl $0, %ecx
jmp .LBB7_117
.p2align 4, 0x90
.LBB7_120: # %._crit_edge374
# in Loop: Header=BB7_117 Depth=1
incl %ebx
cmpl %ebp, %ebx
je .LBB7_121
.LBB7_117: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_119 Depth 2
cmpl $256, %eax # imm = 0x100
jb .LBB7_120
# %bb.118: # %.lr.ph373.preheader
# in Loop: Header=BB7_117 Depth=1
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_119: # %.lr.ph373
# Parent Loop BB7_117 Depth=1
# => This Inner Loop Header: Depth=2
movl $5, (%r15,%rdx,4)
incq %rdx
cmpq %rdx, %rcx
jne .LBB7_119
jmp .LBB7_120
.LBB7_121: # %._crit_edge376
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
imull %r12d, %r12d
cmpl $256, %r12d # imm = 0x100
jb .LBB7_126
# %bb.122: # %.lr.ph.preheader.i
shrl $8, %r12d
cmpl $1, %r12d
adcl $0, %r12d
xorl %eax, %eax
.p2align 4, 0x90
.LBB7_124: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpl $5, (%r15,%rax,4)
jne .LBB7_125
# %bb.123: # in Loop: Header=BB7_124 Depth=1
incq %rax
cmpq %rax, %r12
jne .LBB7_124
.LBB7_126: # %.critedge.i
movl $.Lstr, %edi
jmp .LBB7_127
.LBB7_44:
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jle .LBB7_52
# %bb.45: # %.lr.ph392
movabsq $4294967296, %r12 # imm = 0x100000000
movl %r14d, %r13d
orq %r12, %r13
leaq 64(%r12), %rbp
addq $512, %r12 # imm = 0x200
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
.p2align 4, 0x90
.LBB7_46: # =>This Inner Loop Header: Depth=1
testb $1, %bl
jne .LBB7_53
# %bb.47: # in Loop: Header=BB7_46 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_49
# %bb.48: # in Loop: Header=BB7_46 Depth=1
movq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z16pollute_L2_cachePi, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_49: # in Loop: Header=BB7_46 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_50
.LBB7_53: # %_ZL11HandleError10hipError_tPKci.exit227
# in Loop: Header=BB7_46 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_55
# %bb.54: # in Loop: Header=BB7_46 Depth=1
movq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11writeKernelPi, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_55: # %_ZL11HandleError10hipError_tPKci.exit235
# in Loop: Header=BB7_46 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_56
# %bb.51: # in Loop: Header=BB7_46 Depth=1
decl %r14d
jne .LBB7_46
.LBB7_52: # %._crit_edge393
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
.LBB7_38:
callq hipGetLastError
testl %eax, %eax
movq 80(%rsp), %rbp # 8-byte Reload
movq 112(%rsp), %r14 # 8-byte Reload
je .LBB7_128
# %bb.39:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $206, %ecx
jmp .LBB7_5
.LBB7_79:
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %ebp, %ebp
jle .LBB7_87
# %bb.80: # %.lr.ph382
movabsq $4294967296, %r12 # imm = 0x100000000
movl %r14d, %r13d
orq %r12, %r13
leaq 64(%r12), %rbp
addq $512, %r12 # imm = 0x200
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
.p2align 4, 0x90
.LBB7_81: # =>This Inner Loop Header: Depth=1
testb $1, %bl
jne .LBB7_88
# %bb.82: # in Loop: Header=BB7_81 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_84
# %bb.83: # in Loop: Header=BB7_81 Depth=1
movq 120(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z16pollute_L2_cachePi, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_84: # in Loop: Header=BB7_81 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_85
.LBB7_88: # %_ZL11HandleError10hipError_tPKci.exit271
# in Loop: Header=BB7_81 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_90
# %bb.89: # in Loop: Header=BB7_81 Depth=1
movq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
movq %rsp, %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11writeKernelPi, %edi
leaq 16(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_90: # %_ZL11HandleError10hipError_tPKci.exit279
# in Loop: Header=BB7_81 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB7_91
# %bb.86: # in Loop: Header=BB7_81 Depth=1
decl %r14d
jne .LBB7_81
.LBB7_87: # %._crit_edge383
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
.LBB7_73:
callq hipGetLastError
testl %eax, %eax
movq 80(%rsp), %rbp # 8-byte Reload
movq 112(%rsp), %r14 # 8-byte Reload
je .LBB7_128
# %bb.74:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $251, %ecx
jmp .LBB7_5
.LBB7_125:
movl $.Lstr.1, %edi
.LBB7_127: # %_Z6verifyPii.exit
callq puts@PLT
.LBB7_128: # %_Z6verifyPii.exit
movq (%rsp), %rax
movq 8(%rsp), %rcx
subq 96(%rsp), %rcx
subq 88(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rcx, %xmm1
movsd .LCPI7_0(%rip), %xmm2 # xmm2 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
cmpl $1, %r14d
movl $.L.str.5, %eax
movl $.L.str.6, %esi
cmoveq %rax, %rsi
divsd %xmm2, %xmm1
xorps %xmm3, %xmm3
cvtsi2ss %ebp, %xmm3
addsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
.LBB7_129:
movq %r15, %rdi
callq free
movq 136(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi
callq hipHostFree
movq 120(%rsp), %rdi
callq hipHostFree
callq hipDeviceReset
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_100:
.cfi_def_cfa_offset 208
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $262, %ecx # imm = 0x106
jmp .LBB7_5
.LBB7_43:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $185, %ecx
jmp .LBB7_5
.LBB7_78:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $228, %ecx
jmp .LBB7_5
.LBB7_56:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $201, %ecx
jmp .LBB7_5
.LBB7_91:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $245, %ecx
jmp .LBB7_5
.LBB7_35:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $182, %ecx
jmp .LBB7_5
.LBB7_70:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $224, %ecx
jmp .LBB7_5
.LBB7_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $136, %ecx
jmp .LBB7_5
.LBB7_130:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $138, %ecx
jmp .LBB7_5
.LBB7_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $144, %ecx
jmp .LBB7_5
.LBB7_19:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $145, %ecx
jmp .LBB7_5
.LBB7_21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $168, %ecx
jmp .LBB7_5
.LBB7_50:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $197, %ecx
jmp .LBB7_5
.LBB7_85:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $241, %ecx
jmp .LBB7_5
.LBB7_99:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $265, %ecx # imm = 0x109
jmp .LBB7_5
.LBB7_131:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $175, %ecx
jmp .LBB7_5
.LBB7_59:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $217, %ecx
jmp .LBB7_5
.LBB7_63:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movl $.L.str.3, %edx
movq %rax, %rsi
movl $219, %ecx
.LBB7_5:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI7_0:
.quad .LBB7_8
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_9
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_7
.quad .LBB7_1
.quad .LBB7_1
.quad .LBB7_11
.quad .LBB7_1
.quad .LBB7_10
.LJTI7_1:
.quad .LBB7_24
.quad .LBB7_57
.quad .LBB7_92
.quad .LBB7_102
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10readKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11writeKernelPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10nullKernelPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15initCudaMallocdPii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17verifyCudaMallocdPii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16pollute_L2_cachePi, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10readKernelPiS_,@object # @_Z10readKernelPiS_
.section .rodata,"a",@progbits
.globl _Z10readKernelPiS_
.p2align 3, 0x0
_Z10readKernelPiS_:
.quad _Z25__device_stub__readKernelPiS_
.size _Z10readKernelPiS_, 8
.type _Z11writeKernelPi,@object # @_Z11writeKernelPi
.globl _Z11writeKernelPi
.p2align 3, 0x0
_Z11writeKernelPi:
.quad _Z26__device_stub__writeKernelPi
.size _Z11writeKernelPi, 8
.type _Z10nullKernelPi,@object # @_Z10nullKernelPi
.globl _Z10nullKernelPi
.p2align 3, 0x0
_Z10nullKernelPi:
.quad _Z25__device_stub__nullKernelPi
.size _Z10nullKernelPi, 8
.type _Z15initCudaMallocdPii,@object # @_Z15initCudaMallocdPii
.globl _Z15initCudaMallocdPii
.p2align 3, 0x0
_Z15initCudaMallocdPii:
.quad _Z30__device_stub__initCudaMallocdPii
.size _Z15initCudaMallocdPii, 8
.type _Z17verifyCudaMallocdPii,@object # @_Z17verifyCudaMallocdPii
.globl _Z17verifyCudaMallocdPii
.p2align 3, 0x0
_Z17verifyCudaMallocdPii:
.quad _Z32__device_stub__verifyCudaMallocdPii
.size _Z17verifyCudaMallocdPii, 8
.type _Z16pollute_L2_cachePi,@object # @_Z16pollute_L2_cachePi
.globl _Z16pollute_L2_cachePi
.p2align 3, 0x0
_Z16pollute_L2_cachePi:
.quad _Z31__device_stub__pollute_L2_cachePi
.size _Z16pollute_L2_cachePi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "m:b:i:r:p"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/mkdashti/bandwidthTest/master/latency-ints/latencyTest.hip"
.size .L.str.3, 116
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[%s] Latency including kernel launch overhead = %f us\n"
.size .L.str.4, 55
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "read"
.size .L.str.5, 5
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "write"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "null kernel launch overhead = %f us\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%s in %s at line %d\n"
.size .L.str.8, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10readKernelPiS_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11writeKernelPi"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10nullKernelPi"
.size .L__unnamed_3, 17
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15initCudaMallocdPii"
.size .L__unnamed_4, 23
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z17verifyCudaMallocdPii"
.size .L__unnamed_5, 25
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z16pollute_L2_cachePi"
.size .L__unnamed_6, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "verified SUCCESS"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "error in verification"
.size .Lstr.1, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__readKernelPiS_
.addrsig_sym _Z26__device_stub__writeKernelPi
.addrsig_sym _Z25__device_stub__nullKernelPi
.addrsig_sym _Z30__device_stub__initCudaMallocdPii
.addrsig_sym _Z32__device_stub__verifyCudaMallocdPii
.addrsig_sym _Z31__device_stub__pollute_L2_cachePi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10readKernelPiS_
.addrsig_sym _Z11writeKernelPi
.addrsig_sym _Z10nullKernelPi
.addrsig_sym _Z15initCudaMallocdPii
.addrsig_sym _Z17verifyCudaMallocdPii
.addrsig_sym _Z16pollute_L2_cachePi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <iomanip>
#include <chrono>
#include <thread>
using namespace std;
constexpr int BLOCK_DIM = 16;
// determines if this node (pixel) is inside the circle
// result is stored in a [16*16] array
// thread 0 then computes the number of "in" nodes (value from 0 to 16*16)
__global__ void flagKernel(unsigned *block_counts) {
bool __shared__ ins[BLOCK_DIM*BLOCK_DIM];
// compute our coordinate in the global grid
unsigned i = blockIdx.x*blockDim.x + threadIdx.x; // my i
unsigned j = blockIdx.y*blockDim.y + threadIdx.y; // my j
unsigned Ni = gridDim.x*blockDim.x; // total number of nodes in x
unsigned Nj = gridDim.y*blockDim.y; // total number of nodex in y
//get 1D index from i,j, u=j*ni+i
unsigned u = threadIdx.y*blockDim.x + threadIdx.x;
float x = i/(float)Ni; // compute x in [0,1)
float y = j/(float)Nj; // y in [0,1)
if (x*x+y*y<=1) ins[u] = true; // check if in the circle
else ins[u] = false;
// wait for all threads in the block to finish
__syncthreads();
// let the first thread in the block add up "ins"
if (u==0) {
unsigned count = 0;
for (int i=0;i<blockDim.x*blockDim.y;i++)
if (ins[u]) count++;
// flattened index for the block, u=j*ni+i
int block_u = blockIdx.y*gridDim.x+blockIdx.x;
// store the sum in global memory
block_counts[block_u] = count;
}
}
// this kernel adds up block-level sums to the global sum
// this could be further optimized by splitting up the sum over threads
__global__ void addKernel(dim3 numBlocks, unsigned *block_counts, unsigned long *glob_count) {
// compute total number of blocks
unsigned N = numBlocks.x*numBlocks.y;
unsigned long sum = 0;
for (int i=0;i<N;i++)
sum+=block_counts[i];
// store result in global memory
*glob_count = sum;
}
int main() {
// grab starting time
auto time_start = chrono::high_resolution_clock::now();
// figure out how many samples I should process
size_t N = BLOCK_DIM*1000; // grid size
// figure out our grid size
dim3 threadsPerBlock(BLOCK_DIM, BLOCK_DIM);
dim3 numBlocks(N / threadsPerBlock.x, N / threadsPerBlock.y);
// allocate memory on the GPU
unsigned *block_counts;
cudaMalloc((void**)&block_counts, numBlocks.x*numBlocks.y*sizeof(unsigned));
unsigned long *N_in_gpu; // GPU variable to hold the total N_in
unsigned long N_in; // CPU variable to hold this data
cudaMalloc((void**)&N_in_gpu, sizeof(N_in));
// launch the kernel to flag nodes, each block has BLOCK_DIM*BLOCK_DIM threads
flagKernel<<<numBlocks, threadsPerBlock>>>(block_counts);
// launch kernel to add up per-block "in" counts
addKernel<<<1, 1>>>(numBlocks, block_counts, N_in_gpu);
// transfer N_in from the GPU to the CPU
cudaMemcpy(&N_in, N_in_gpu, sizeof(N_in), cudaMemcpyDeviceToHost);
auto time_now = chrono::high_resolution_clock::now();
chrono::duration<double> time_delta = time_now-time_start;
// compute pi and show the result on rank 0 (root) using the global data
size_t N_tot = N*N;
double pi = 4*N_in/(double)N_tot;
cout<<"Using a "<<N<<"x"<<N<<" grid ("<<N_tot<<" samples), pi is "<<pi
<<" in "<<setprecision(3)<<time_delta.count()<<" seconds"<<endl;
// be a good neighbor and free memory
cudaFree(block_counts);
cudaFree(N_in_gpu);
return 0;
} | .file "tmpxft_000ce33c_00000000-6_pi-cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4166:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4166:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10flagKernelPjPj
.type _Z30__device_stub__Z10flagKernelPjPj, @function
_Z30__device_stub__Z10flagKernelPjPj:
.LFB4188:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10flagKernelPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4188:
.size _Z30__device_stub__Z10flagKernelPjPj, .-_Z30__device_stub__Z10flagKernelPjPj
.globl _Z10flagKernelPj
.type _Z10flagKernelPj, @function
_Z10flagKernelPj:
.LFB4189:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10flagKernelPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4189:
.size _Z10flagKernelPj, .-_Z10flagKernelPj
.globl _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
.type _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm, @function
_Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm:
.LFB4190:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernel4dim3PjPm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4190:
.size _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm, .-_Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
.globl _Z9addKernel4dim3PjPm
.type _Z9addKernel4dim3PjPm, @function
_Z9addKernel4dim3PjPm:
.LFB4191:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %esi, %eax
movq %rdx, %rsi
movq %rcx, %rdx
movq %rdi, (%rsp)
movl %eax, 8(%rsp)
movq %rsp, %rdi
call _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4191:
.size _Z9addKernel4dim3PjPm, .-_Z9addKernel4dim3PjPm
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Using a "
.LC3:
.string "x"
.LC4:
.string " grid ("
.LC5:
.string " samples), pi is "
.LC6:
.string " in "
.LC7:
.string " seconds"
.text
.globl main
.type main, @function
main:
.LFB4159:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, 48(%rsp)
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $16, 40(%rsp)
movl $16, 44(%rsp)
movl $1000, 52(%rsp)
movl $1000, 56(%rsp)
movl $1, 60(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L20:
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
leaq 88(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
movq 88(%rsp), %rax
salq $2, %rax
js .L22
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L23:
divsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $16000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $16000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $256000000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $3, 8(%rdi,%rax)
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 24(%rsp), %rdi
call _Z30__device_stub__Z10flagKernelPjPj
jmp .L20
.L27:
movl $1000, 88(%rsp)
movl $1000, 92(%rsp)
movl $1, 96(%rsp)
leaq 88(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
jmp .L21
.L22:
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4159:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9addKernel4dim3PjPm"
.LC9:
.string "_Z10flagKernelPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4193:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernel4dim3PjPm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10flagKernelPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4193:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.align 8
.LC1:
.long 0
.long 1101956224
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <iomanip>
#include <chrono>
#include <thread>
using namespace std;
constexpr int BLOCK_DIM = 16;
// determines if this node (pixel) is inside the circle
// result is stored in a [16*16] array
// thread 0 then computes the number of "in" nodes (value from 0 to 16*16)
__global__ void flagKernel(unsigned *block_counts) {
bool __shared__ ins[BLOCK_DIM*BLOCK_DIM];
// compute our coordinate in the global grid
unsigned i = blockIdx.x*blockDim.x + threadIdx.x; // my i
unsigned j = blockIdx.y*blockDim.y + threadIdx.y; // my j
unsigned Ni = gridDim.x*blockDim.x; // total number of nodes in x
unsigned Nj = gridDim.y*blockDim.y; // total number of nodex in y
//get 1D index from i,j, u=j*ni+i
unsigned u = threadIdx.y*blockDim.x + threadIdx.x;
float x = i/(float)Ni; // compute x in [0,1)
float y = j/(float)Nj; // y in [0,1)
if (x*x+y*y<=1) ins[u] = true; // check if in the circle
else ins[u] = false;
// wait for all threads in the block to finish
__syncthreads();
// let the first thread in the block add up "ins"
if (u==0) {
unsigned count = 0;
for (int i=0;i<blockDim.x*blockDim.y;i++)
if (ins[u]) count++;
// flattened index for the block, u=j*ni+i
int block_u = blockIdx.y*gridDim.x+blockIdx.x;
// store the sum in global memory
block_counts[block_u] = count;
}
}
// this kernel adds up block-level sums to the global sum
// this could be further optimized by splitting up the sum over threads
__global__ void addKernel(dim3 numBlocks, unsigned *block_counts, unsigned long *glob_count) {
// compute total number of blocks
unsigned N = numBlocks.x*numBlocks.y;
unsigned long sum = 0;
for (int i=0;i<N;i++)
sum+=block_counts[i];
// store result in global memory
*glob_count = sum;
}
int main() {
// grab starting time
auto time_start = chrono::high_resolution_clock::now();
// figure out how many samples I should process
size_t N = BLOCK_DIM*1000; // grid size
// figure out our grid size
dim3 threadsPerBlock(BLOCK_DIM, BLOCK_DIM);
dim3 numBlocks(N / threadsPerBlock.x, N / threadsPerBlock.y);
// allocate memory on the GPU
unsigned *block_counts;
cudaMalloc((void**)&block_counts, numBlocks.x*numBlocks.y*sizeof(unsigned));
unsigned long *N_in_gpu; // GPU variable to hold the total N_in
unsigned long N_in; // CPU variable to hold this data
cudaMalloc((void**)&N_in_gpu, sizeof(N_in));
// launch the kernel to flag nodes, each block has BLOCK_DIM*BLOCK_DIM threads
flagKernel<<<numBlocks, threadsPerBlock>>>(block_counts);
// launch kernel to add up per-block "in" counts
addKernel<<<1, 1>>>(numBlocks, block_counts, N_in_gpu);
// transfer N_in from the GPU to the CPU
cudaMemcpy(&N_in, N_in_gpu, sizeof(N_in), cudaMemcpyDeviceToHost);
auto time_now = chrono::high_resolution_clock::now();
chrono::duration<double> time_delta = time_now-time_start;
// compute pi and show the result on rank 0 (root) using the global data
size_t N_tot = N*N;
double pi = 4*N_in/(double)N_tot;
cout<<"Using a "<<N<<"x"<<N<<" grid ("<<N_tot<<" samples), pi is "<<pi
<<" in "<<setprecision(3)<<time_delta.count()<<" seconds"<<endl;
// be a good neighbor and free memory
cudaFree(block_counts);
cudaFree(N_in_gpu);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <chrono>
#include <thread>
using namespace std;
constexpr int BLOCK_DIM = 16;
// determines if this node (pixel) is inside the circle
// result is stored in a [16*16] array
// thread 0 then computes the number of "in" nodes (value from 0 to 16*16)
__global__ void flagKernel(unsigned *block_counts) {
bool __shared__ ins[BLOCK_DIM*BLOCK_DIM];
// compute our coordinate in the global grid
unsigned i = blockIdx.x*blockDim.x + threadIdx.x; // my i
unsigned j = blockIdx.y*blockDim.y + threadIdx.y; // my j
unsigned Ni = gridDim.x*blockDim.x; // total number of nodes in x
unsigned Nj = gridDim.y*blockDim.y; // total number of nodex in y
//get 1D index from i,j, u=j*ni+i
unsigned u = threadIdx.y*blockDim.x + threadIdx.x;
float x = i/(float)Ni; // compute x in [0,1)
float y = j/(float)Nj; // y in [0,1)
if (x*x+y*y<=1) ins[u] = true; // check if in the circle
else ins[u] = false;
// wait for all threads in the block to finish
__syncthreads();
// let the first thread in the block add up "ins"
if (u==0) {
unsigned count = 0;
for (int i=0;i<blockDim.x*blockDim.y;i++)
if (ins[u]) count++;
// flattened index for the block, u=j*ni+i
int block_u = blockIdx.y*gridDim.x+blockIdx.x;
// store the sum in global memory
block_counts[block_u] = count;
}
}
// this kernel adds up block-level sums to the global sum
// this could be further optimized by splitting up the sum over threads
__global__ void addKernel(dim3 numBlocks, unsigned *block_counts, unsigned long *glob_count) {
// compute total number of blocks
unsigned N = numBlocks.x*numBlocks.y;
unsigned long sum = 0;
for (int i=0;i<N;i++)
sum+=block_counts[i];
// store result in global memory
*glob_count = sum;
}
int main() {
// grab starting time
auto time_start = chrono::high_resolution_clock::now();
// figure out how many samples I should process
size_t N = BLOCK_DIM*1000; // grid size
// figure out our grid size
dim3 threadsPerBlock(BLOCK_DIM, BLOCK_DIM);
dim3 numBlocks(N / threadsPerBlock.x, N / threadsPerBlock.y);
// allocate memory on the GPU
unsigned *block_counts;
hipMalloc((void**)&block_counts, numBlocks.x*numBlocks.y*sizeof(unsigned));
unsigned long *N_in_gpu; // GPU variable to hold the total N_in
unsigned long N_in; // CPU variable to hold this data
hipMalloc((void**)&N_in_gpu, sizeof(N_in));
// launch the kernel to flag nodes, each block has BLOCK_DIM*BLOCK_DIM threads
flagKernel<<<numBlocks, threadsPerBlock>>>(block_counts);
// launch kernel to add up per-block "in" counts
addKernel<<<1, 1>>>(numBlocks, block_counts, N_in_gpu);
// transfer N_in from the GPU to the CPU
hipMemcpy(&N_in, N_in_gpu, sizeof(N_in), hipMemcpyDeviceToHost);
auto time_now = chrono::high_resolution_clock::now();
chrono::duration<double> time_delta = time_now-time_start;
// compute pi and show the result on rank 0 (root) using the global data
size_t N_tot = N*N;
double pi = 4*N_in/(double)N_tot;
cout<<"Using a "<<N<<"x"<<N<<" grid ("<<N_tot<<" samples), pi is "<<pi
<<" in "<<setprecision(3)<<time_delta.count()<<" seconds"<<endl;
// be a good neighbor and free memory
hipFree(block_counts);
hipFree(N_in_gpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <chrono>
#include <thread>
using namespace std;
constexpr int BLOCK_DIM = 16;
// determines if this node (pixel) is inside the circle
// result is stored in a [16*16] array
// thread 0 then computes the number of "in" nodes (value from 0 to 16*16)
__global__ void flagKernel(unsigned *block_counts) {
bool __shared__ ins[BLOCK_DIM*BLOCK_DIM];
// compute our coordinate in the global grid
unsigned i = blockIdx.x*blockDim.x + threadIdx.x; // my i
unsigned j = blockIdx.y*blockDim.y + threadIdx.y; // my j
unsigned Ni = gridDim.x*blockDim.x; // total number of nodes in x
unsigned Nj = gridDim.y*blockDim.y; // total number of nodex in y
//get 1D index from i,j, u=j*ni+i
unsigned u = threadIdx.y*blockDim.x + threadIdx.x;
float x = i/(float)Ni; // compute x in [0,1)
float y = j/(float)Nj; // y in [0,1)
if (x*x+y*y<=1) ins[u] = true; // check if in the circle
else ins[u] = false;
// wait for all threads in the block to finish
__syncthreads();
// let the first thread in the block add up "ins"
if (u==0) {
unsigned count = 0;
for (int i=0;i<blockDim.x*blockDim.y;i++)
if (ins[u]) count++;
// flattened index for the block, u=j*ni+i
int block_u = blockIdx.y*gridDim.x+blockIdx.x;
// store the sum in global memory
block_counts[block_u] = count;
}
}
// this kernel adds up block-level sums to the global sum
// this could be further optimized by splitting up the sum over threads
__global__ void addKernel(dim3 numBlocks, unsigned *block_counts, unsigned long *glob_count) {
// compute total number of blocks
unsigned N = numBlocks.x*numBlocks.y;
unsigned long sum = 0;
for (int i=0;i<N;i++)
sum+=block_counts[i];
// store result in global memory
*glob_count = sum;
}
int main() {
// grab starting time
auto time_start = chrono::high_resolution_clock::now();
// figure out how many samples I should process
size_t N = BLOCK_DIM*1000; // grid size
// figure out our grid size
dim3 threadsPerBlock(BLOCK_DIM, BLOCK_DIM);
dim3 numBlocks(N / threadsPerBlock.x, N / threadsPerBlock.y);
// allocate memory on the GPU
unsigned *block_counts;
hipMalloc((void**)&block_counts, numBlocks.x*numBlocks.y*sizeof(unsigned));
unsigned long *N_in_gpu; // GPU variable to hold the total N_in
unsigned long N_in; // CPU variable to hold this data
hipMalloc((void**)&N_in_gpu, sizeof(N_in));
// launch the kernel to flag nodes, each block has BLOCK_DIM*BLOCK_DIM threads
flagKernel<<<numBlocks, threadsPerBlock>>>(block_counts);
// launch kernel to add up per-block "in" counts
addKernel<<<1, 1>>>(numBlocks, block_counts, N_in_gpu);
// transfer N_in from the GPU to the CPU
hipMemcpy(&N_in, N_in_gpu, sizeof(N_in), hipMemcpyDeviceToHost);
auto time_now = chrono::high_resolution_clock::now();
chrono::duration<double> time_delta = time_now-time_start;
// compute pi and show the result on rank 0 (root) using the global data
size_t N_tot = N*N;
double pi = 4*N_in/(double)N_tot;
cout<<"Using a "<<N<<"x"<<N<<" grid ("<<N_tot<<" samples), pi is "<<pi
<<" in "<<setprecision(3)<<time_delta.count()<<" seconds"<<endl;
// be a good neighbor and free memory
hipFree(block_counts);
hipFree(N_in_gpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10flagKernelPj
.globl _Z10flagKernelPj
.p2align 8
.type _Z10flagKernelPj,@function
_Z10flagKernelPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s6, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s2, s4, s3
s_mul_i32 s5, s5, s6
v_cvt_f32_u32_e32 v4, s2
v_cvt_f32_u32_e32 v5, s5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v2, v2
v_mad_u32_u24 v0, v0, s3, v1
v_cvt_f32_u32_e32 v3, v3
v_div_scale_f32 v6, null, v4, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v7, null, v5, v5, v3
v_div_scale_f32 v12, vcc_lo, v2, v4, v2
v_rcp_f32_e32 v8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fma_f32 v11, -v7, v9, 1.0
v_dual_fmac_f32 v8, v10, v8 :: v_dual_fmac_f32 v9, v11, v9
v_div_scale_f32 v10, s2, v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, v12, v8
v_mul_f32_e32 v13, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v6, v11, v12
v_fma_f32 v15, -v7, v13, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v14, v8
v_fmac_f32_e32 v13, v15, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v6, v11, v12
v_fma_f32 v7, -v7, v13, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v6, v6, v8, v11
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, exec_lo
v_div_fmas_f32 v7, v7, v9, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v6, v4, v2
v_div_fixup_f32 v3, v7, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v3, v3
v_fmac_f32_e32 v3, v2, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_f32_e32 vcc_lo, 1.0, v3
v_cndmask_b32_e64 v1, 0, 1, vcc_lo
ds_store_b8 v0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
s_cmp_eq_u32 s3, 0
v_mov_b32_e32 v0, 0
s_cselect_b32 s2, -1, 0
s_cmp_eq_u32 s6, 0
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s5, s2
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_3
v_mov_b32_e32 v0, 0
s_mul_i32 s6, s6, s3
ds_load_u8 v0, v0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, s6, v0
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s2, s4, s15
v_mov_b32_e32 v1, 0
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10flagKernelPj
.amdhsa_group_segment_fixed_size 256
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10flagKernelPj, .Lfunc_end0-_Z10flagKernelPj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9addKernel4dim3PjPm
.globl _Z9addKernel4dim3PjPm
.p2align 8
.type _Z9addKernel4dim3PjPm,@function
_Z9addKernel4dim3PjPm:
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_3
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b64 s[2:3], 0
.LBB1_2:
s_waitcnt lgkmcnt(0)
s_load_b32 s7, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s7
s_addc_u32 s3, s3, 0
s_add_i32 s6, s6, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s6, 0
s_cbranch_scc0 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
s_mov_b64 s[2:3], 0
.LBB1_4:
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v0, s2
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernel4dim3PjPm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9addKernel4dim3PjPm, .Lfunc_end1-_Z9addKernel4dim3PjPm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 256
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10flagKernelPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10flagKernelPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 12
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernel4dim3PjPm
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernel4dim3PjPm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <chrono>
#include <thread>
using namespace std;
constexpr int BLOCK_DIM = 16;
// determines if this node (pixel) is inside the circle
// result is stored in a [16*16] array
// thread 0 then computes the number of "in" nodes (value from 0 to 16*16)
__global__ void flagKernel(unsigned *block_counts) {
bool __shared__ ins[BLOCK_DIM*BLOCK_DIM];
// compute our coordinate in the global grid
unsigned i = blockIdx.x*blockDim.x + threadIdx.x; // my i
unsigned j = blockIdx.y*blockDim.y + threadIdx.y; // my j
unsigned Ni = gridDim.x*blockDim.x; // total number of nodes in x
unsigned Nj = gridDim.y*blockDim.y; // total number of nodex in y
//get 1D index from i,j, u=j*ni+i
unsigned u = threadIdx.y*blockDim.x + threadIdx.x;
float x = i/(float)Ni; // compute x in [0,1)
float y = j/(float)Nj; // y in [0,1)
if (x*x+y*y<=1) ins[u] = true; // check if in the circle
else ins[u] = false;
// wait for all threads in the block to finish
__syncthreads();
// let the first thread in the block add up "ins"
if (u==0) {
unsigned count = 0;
for (int i=0;i<blockDim.x*blockDim.y;i++)
if (ins[u]) count++;
// flattened index for the block, u=j*ni+i
int block_u = blockIdx.y*gridDim.x+blockIdx.x;
// store the sum in global memory
block_counts[block_u] = count;
}
}
// this kernel adds up block-level sums to the global sum
// this could be further optimized by splitting up the sum over threads
__global__ void addKernel(dim3 numBlocks, unsigned *block_counts, unsigned long *glob_count) {
// compute total number of blocks
unsigned N = numBlocks.x*numBlocks.y;
unsigned long sum = 0;
for (int i=0;i<N;i++)
sum+=block_counts[i];
// store result in global memory
*glob_count = sum;
}
int main() {
// grab starting time
auto time_start = chrono::high_resolution_clock::now();
// figure out how many samples I should process
size_t N = BLOCK_DIM*1000; // grid size
// figure out our grid size
dim3 threadsPerBlock(BLOCK_DIM, BLOCK_DIM);
dim3 numBlocks(N / threadsPerBlock.x, N / threadsPerBlock.y);
// allocate memory on the GPU
unsigned *block_counts;
hipMalloc((void**)&block_counts, numBlocks.x*numBlocks.y*sizeof(unsigned));
unsigned long *N_in_gpu; // GPU variable to hold the total N_in
unsigned long N_in; // CPU variable to hold this data
hipMalloc((void**)&N_in_gpu, sizeof(N_in));
// launch the kernel to flag nodes, each block has BLOCK_DIM*BLOCK_DIM threads
flagKernel<<<numBlocks, threadsPerBlock>>>(block_counts);
// launch kernel to add up per-block "in" counts
addKernel<<<1, 1>>>(numBlocks, block_counts, N_in_gpu);
// transfer N_in from the GPU to the CPU
hipMemcpy(&N_in, N_in_gpu, sizeof(N_in), hipMemcpyDeviceToHost);
auto time_now = chrono::high_resolution_clock::now();
chrono::duration<double> time_delta = time_now-time_start;
// compute pi and show the result on rank 0 (root) using the global data
size_t N_tot = N*N;
double pi = 4*N_in/(double)N_tot;
cout<<"Using a "<<N<<"x"<<N<<" grid ("<<N_tot<<" samples), pi is "<<pi
<<" in "<<setprecision(3)<<time_delta.count()<<" seconds"<<endl;
// be a good neighbor and free memory
hipFree(block_counts);
hipFree(N_in_gpu);
return 0;
} | .text
.file "pi-cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__flagKernelPj # -- Begin function _Z25__device_stub__flagKernelPj
.p2align 4, 0x90
.type _Z25__device_stub__flagKernelPj,@function
_Z25__device_stub__flagKernelPj: # @_Z25__device_stub__flagKernelPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10flagKernelPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__flagKernelPj, .Lfunc_end0-_Z25__device_stub__flagKernelPj
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addKernel4dim3PjPm # -- Begin function _Z24__device_stub__addKernel4dim3PjPm
.p2align 4, 0x90
.type _Z24__device_stub__addKernel4dim3PjPm,@function
_Z24__device_stub__addKernel4dim3PjPm: # @_Z24__device_stub__addKernel4dim3PjPm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 64(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernel4dim3PjPm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__addKernel4dim3PjPm, .Lfunc_end1-_Z24__device_stub__addKernel4dim3PjPm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI2_3:
.quad 0x41ae848000000000 # double 2.56E+8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967297000, %r14 # imm = 0x3E8000003E8
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10flagKernelPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %r14, 32(%rsp)
movl $1, 40(%rsp)
movq %rax, 24(%rsp)
movq %rcx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernel4dim3PjPm, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%rsp), %rax
shlq $2, %rax
movq %rax, %xmm0
punpckldq .LCPI2_1(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_2(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd .LCPI2_3(%rip), %xmm1
movapd %xmm1, 128(%rsp) # 16-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $16000, %esi # imm = 0x3E80
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $16000, %esi # imm = 0x3E80
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.2, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $256000000, %esi # imm = 0xF424000
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $17, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movaps 128(%rsp), %xmm0 # 16-byte Reload
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq $3, 8(%rbx,%rax)
movq %rbx, %rdi
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB2_8
.LBB2_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10flagKernelPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernel4dim3PjPm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10flagKernelPj,@object # @_Z10flagKernelPj
.section .rodata,"a",@progbits
.globl _Z10flagKernelPj
.p2align 3, 0x0
_Z10flagKernelPj:
.quad _Z25__device_stub__flagKernelPj
.size _Z10flagKernelPj, 8
.type _Z9addKernel4dim3PjPm,@object # @_Z9addKernel4dim3PjPm
.globl _Z9addKernel4dim3PjPm
.p2align 3, 0x0
_Z9addKernel4dim3PjPm:
.quad _Z24__device_stub__addKernel4dim3PjPm
.size _Z9addKernel4dim3PjPm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Using a "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "x"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " grid ("
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " samples), pi is "
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " in "
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " seconds"
.size .L.str.5, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10flagKernelPj"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9addKernel4dim3PjPm"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__flagKernelPj
.addrsig_sym _Z24__device_stub__addKernel4dim3PjPm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10flagKernelPj
.addrsig_sym _Z9addKernel4dim3PjPm
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce33c_00000000-6_pi-cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4166:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4166:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10flagKernelPjPj
.type _Z30__device_stub__Z10flagKernelPjPj, @function
_Z30__device_stub__Z10flagKernelPjPj:
.LFB4188:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10flagKernelPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4188:
.size _Z30__device_stub__Z10flagKernelPjPj, .-_Z30__device_stub__Z10flagKernelPjPj
.globl _Z10flagKernelPj
.type _Z10flagKernelPj, @function
_Z10flagKernelPj:
.LFB4189:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10flagKernelPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4189:
.size _Z10flagKernelPj, .-_Z10flagKernelPj
.globl _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
.type _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm, @function
_Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm:
.LFB4190:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernel4dim3PjPm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4190:
.size _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm, .-_Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
.globl _Z9addKernel4dim3PjPm
.type _Z9addKernel4dim3PjPm, @function
_Z9addKernel4dim3PjPm:
.LFB4191:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movl %esi, %eax
movq %rdx, %rsi
movq %rcx, %rdx
movq %rdi, (%rsp)
movl %eax, 8(%rsp)
movq %rsp, %rdi
call _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4191:
.size _Z9addKernel4dim3PjPm, .-_Z9addKernel4dim3PjPm
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Using a "
.LC3:
.string "x"
.LC4:
.string " grid ("
.LC5:
.string " samples), pi is "
.LC6:
.string " in "
.LC7:
.string " seconds"
.text
.globl main
.type main, @function
main:
.LFB4159:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movl $1, 48(%rsp)
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
movl $16, 40(%rsp)
movl $16, 44(%rsp)
movl $1000, 52(%rsp)
movl $1000, 56(%rsp)
movl $1, 60(%rsp)
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L20:
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L21:
leaq 88(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
movq 88(%rsp), %rax
salq $2, %rax
js .L22
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L23:
divsd .LC1(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $16000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $16000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $256000000, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $3, 8(%rdi,%rax)
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 24(%rsp), %rdi
call _Z30__device_stub__Z10flagKernelPjPj
jmp .L20
.L27:
movl $1000, 88(%rsp)
movl $1000, 92(%rsp)
movl $1, 96(%rsp)
leaq 88(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call _Z35__device_stub__Z9addKernel4dim3PjPmR4dim3PjPm
jmp .L21
.L22:
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4159:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9addKernel4dim3PjPm"
.LC9:
.string "_Z10flagKernelPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4193:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernel4dim3PjPm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10flagKernelPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4193:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.align 8
.LC1:
.long 0
.long 1101956224
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pi-cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__flagKernelPj # -- Begin function _Z25__device_stub__flagKernelPj
.p2align 4, 0x90
.type _Z25__device_stub__flagKernelPj,@function
_Z25__device_stub__flagKernelPj: # @_Z25__device_stub__flagKernelPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10flagKernelPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__flagKernelPj, .Lfunc_end0-_Z25__device_stub__flagKernelPj
.cfi_endproc
# -- End function
.globl _Z24__device_stub__addKernel4dim3PjPm # -- Begin function _Z24__device_stub__addKernel4dim3PjPm
.p2align 4, 0x90
.type _Z24__device_stub__addKernel4dim3PjPm,@function
_Z24__device_stub__addKernel4dim3PjPm: # @_Z24__device_stub__addKernel4dim3PjPm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 64(%rsp)
movl %esi, 72(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernel4dim3PjPm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__addKernel4dim3PjPm, .Lfunc_end1-_Z24__device_stub__addKernel4dim3PjPm
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.LCPI2_3:
.quad 0x41ae848000000000 # double 2.56E+8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI2_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI2_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967297000, %r14 # imm = 0x3E8000003E8
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10flagKernelPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %r14, 32(%rsp)
movl $1, 40(%rsp)
movq %rax, 24(%rsp)
movq %rcx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernel4dim3PjPm, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 80(%rsp), %rax
shlq $2, %rax
movq %rax, %xmm0
punpckldq .LCPI2_1(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI2_2(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
divsd .LCPI2_3(%rip), %xmm1
movapd %xmm1, 128(%rsp) # 16-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $16000, %esi # imm = 0x3E80
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $16000, %esi # imm = 0x3E80
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.2, %esi
movl $7, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $256000000, %esi # imm = 0xF424000
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $17, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movaps 128(%rsp), %xmm0 # 16-byte Reload
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq $3, 8(%rbx,%rax)
movq %rbx, %rdi
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB2_8
.LBB2_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10flagKernelPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernel4dim3PjPm, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10flagKernelPj,@object # @_Z10flagKernelPj
.section .rodata,"a",@progbits
.globl _Z10flagKernelPj
.p2align 3, 0x0
_Z10flagKernelPj:
.quad _Z25__device_stub__flagKernelPj
.size _Z10flagKernelPj, 8
.type _Z9addKernel4dim3PjPm,@object # @_Z9addKernel4dim3PjPm
.globl _Z9addKernel4dim3PjPm
.p2align 3, 0x0
_Z9addKernel4dim3PjPm:
.quad _Z24__device_stub__addKernel4dim3PjPm
.size _Z9addKernel4dim3PjPm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Using a "
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "x"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " grid ("
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " samples), pi is "
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " in "
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " seconds"
.size .L.str.5, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10flagKernelPj"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9addKernel4dim3PjPm"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__flagKernelPj
.addrsig_sym _Z24__device_stub__addKernel4dim3PjPm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10flagKernelPj
.addrsig_sym _Z9addKernel4dim3PjPm
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<vector>
#include<cstdlib>
__global__ void convolution_kernel(double *arr, double *mask, double *output, int N, int M){
auto i = blockDim.x*blockIdx.x+threadIdx.x;
auto start = i - (M/2);
auto temp = 0.0;
for(auto k = 0; k < M; k++){
if((start+k >=0) && (start+k <N)){
temp += arr[start+k]*mask[k];
}
}
output[i] = temp;
}
int main(){
int N = 1048576; // size of the array = 2^20
size_t size_N = N*sizeof(double);
int M = 7; // size of the mask
size_t size_M = M*sizeof(double);
std::vector<double> h_array(N);
std::vector<double> h_mask(M);
std::vector<double> h_output(N);
for(auto& i:h_array){i = rand()%100;}
for(auto& j:h_mask){j = rand()%10;}
double *d_array, *d_mask, *d_output;
cudaMalloc(&d_array, size_N);
cudaMalloc(&d_output, size_N);
cudaMalloc(&d_mask, size_M);
cudaMemcpy(d_array, h_array.data(), size_N, cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, h_mask.data(), size_M, cudaMemcpyHostToDevice);
int threadsPerBlock = 32;
int blocksPerGrid = (N+threadsPerBlock-1)/threadsPerBlock;
convolution_kernel<<<blocksPerGrid, threadsPerBlock>>>(d_array, d_mask, d_output, N, M);
cudaMemcpy(h_output.data(), d_output, size_N, cudaMemcpyDeviceToHost);
// Uncomment to print the output
// for(auto& i:h_output){std::cout << i << std::endl;}
cudaFree(d_array);
cudaFree(d_output);
cudaFree(d_mask);
return 0;
} | code for sm_80
Function : _Z18convolution_kernelPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fd800078e0203 */
/*0080*/ @!P0 BRA 0x4f0 ; /* 0x0000046000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R6, R5.reuse, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00b0*/ LOP3.LUT R4, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305047812 */
/* 0x040fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*00d0*/ LEA.HI R5, R5, c[0x0][0x17c], RZ, 0x1 ; /* 0x00005f0005057a11 */
/* 0x000fe200078f08ff */
/*00e0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0100*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fce0000011405 */
/*0110*/ @!P1 BRA 0x3a0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R24, -R5, 0x3, R2 ; /* 0x0000000305187810 */
/* 0x000fe20007ffe102 */
/*0130*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R25, R4, -c[0x0][0x17c], RZ ; /* 0x80005f0004197a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe200078e00ff */
/*0160*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0180*/ IADD3 R13, R24, -0x3, RZ ; /* 0xfffffffd180d7810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P2, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fda0003f46070 */
/*01a0*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, 0x8 ; /* 0x00000008ff0ca424 */
/* 0x000fe200078e00ff */
/*01b0*/ @!P2 LDG.E.64 R10, [R8.64] ; /* 0x00000008080aa981 */
/* 0x001ea6000c1e1b00 */
/*01c0*/ @!P2 IMAD.WIDE.U32 R12, R13, R12, c[0x0][0x160] ; /* 0x000058000d0ca625 */
/* 0x000fcc00078e000c */
/*01d0*/ @!P2 LDG.E.64 R12, [R12.64] ; /* 0x000000080c0ca981 */
/* 0x000ea2000c1e1b00 */
/*01e0*/ IADD3 R16, R24.reuse, -0x2, RZ ; /* 0xfffffffe18107810 */
/* 0x040fe40007ffe0ff */
/*01f0*/ IADD3 R20, R24, -0x1, RZ ; /* 0xffffffff18147810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P3, PT, R16, c[0x0][0x178], PT ; /* 0x00005e0010007a0c */
/* 0x000fe40003f66070 */
/*0210*/ ISETP.GE.U32.AND P4, PT, R20, c[0x0][0x178], PT ; /* 0x00005e0014007a0c */
/* 0x000fe40003f86070 */
/*0220*/ ISETP.GE.U32.AND P1, PT, R24, c[0x0][0x178], PT ; /* 0x00005e0018007a0c */
/* 0x000fd20003f26070 */
/*0230*/ @!P3 IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff11b424 */
/* 0x000fe200078e00ff */
/*0240*/ @!P3 LDG.E.64 R14, [R8.64+0x8] ; /* 0x00000808080eb981 */
/* 0x000ee2000c1e1b00 */
/*0250*/ @!P4 IMAD.MOV.U32 R21, RZ, RZ, 0x8 ; /* 0x00000008ff15c424 */
/* 0x000fe400078e00ff */
/*0260*/ @!P3 IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x160] ; /* 0x000058001010b625 */
/* 0x000fe200078e0011 */
/*0270*/ @!P4 LDG.E.64 R18, [R8.64+0x10] ; /* 0x000010080812c981 */
/* 0x000126000c1e1b00 */
/*0280*/ @!P4 IMAD.WIDE.U32 R20, R20, R21, c[0x0][0x160] ; /* 0x000058001414c625 */
/* 0x000fe400078e0015 */
/*0290*/ @!P3 LDG.E.64 R16, [R16.64] ; /* 0x000000081010b981 */
/* 0x000ee4000c1e1b00 */
/*02a0*/ @!P1 IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff179424 */
/* 0x000fc400078e00ff */
/*02b0*/ @!P4 LDG.E.64 R20, [R20.64] ; /* 0x000000081414c981 */
/* 0x000f24000c1e1b00 */
/*02c0*/ @!P1 IMAD.WIDE.U32 R22, R24, R23, c[0x0][0x160] ; /* 0x0000580018169625 */
/* 0x000fcc00078e0017 */
/*02d0*/ @!P1 LDG.E.64 R22, [R22.64] ; /* 0x0000000816169981 */
/* 0x000f62000c1e1b00 */
/*02e0*/ @!P2 DFMA R6, R10, R12, R6 ; /* 0x0000000c0a06a22b */
/* 0x0062c60000000006 */
/*02f0*/ @!P1 LDG.E.64 R10, [R8.64+0x18] ; /* 0x00001808080a9981 */
/* 0x002162000c1e1b00 */
/*0300*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fcc000fffe03f */
/*0310*/ IADD3 R12, R25, UR4, RZ ; /* 0x00000004190c7c10 */
/* 0x000fc8000fffe0ff */
/*0320*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f45270 */
/*0330*/ @!P3 DFMA R6, R14, R16, R6 ; /* 0x000000100e06b22b */
/* 0x008f220000000006 */
/*0340*/ IADD3 R8, P3, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x001fca0007f7e0ff */
/*0350*/ @!P4 DFMA R6, R18, R20, R6 ; /* 0x000000141206c22b */
/* 0x010f620000000006 */
/*0360*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0370*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fc80007ffe0ff */
/*0380*/ @!P1 DFMA R6, R10, R22, R6 ; /* 0x000000160a06922b */
/* 0x0200620000000006 */
/*0390*/ @P2 BRA 0x180 ; /* 0xfffffde000002947 */
/* 0x000fea000383ffff */
/*03a0*/ @!P0 BRA 0x4f0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*03b0*/ IADD3 R3, R3, UR4, RZ ; /* 0x0000000403037c10 */
/* 0x000fe2000fffe0ff */
/*03c0*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*03d0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*03e0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fe200078e0203 */
/*03f0*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fc6000f8e0206 */
/*0400*/ IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a05 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0420*/ IMAD.U32 R10, RZ, RZ, UR4 ; /* 0x00000004ff0a7e24 */
/* 0x001fe4000f8e00ff */
/*0430*/ IMAD.U32 R11, RZ, RZ, UR5 ; /* 0x00000005ff0b7e24 */
/* 0x000fd4000f8e00ff */
/*0440*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff098424 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 LDG.E.64 R10, [R10.64] ; /* 0x000000080a0a8981 */
/* 0x000ea6000c1e1b00 */
/*0460*/ @!P0 IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000088625 */
/* 0x000fcc00078e0009 */
/*0470*/ @!P0 LDG.E.64 R8, [R8.64] ; /* 0x0000000808088981 */
/* 0x000ea2000c1e1b00 */
/*0480*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0490*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*04a0*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000ff1e03f */
/*04b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*04d0*/ @!P0 DFMA R6, R10, R8, R6 ; /* 0x000000080a06822b */
/* 0x00604e0000000006 */
/*04e0*/ @P1 BRA 0x410 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*04f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0003 */
/*0510*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x002fe2000c101b08 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<vector>
#include<cstdlib>
__global__ void convolution_kernel(double *arr, double *mask, double *output, int N, int M){
auto i = blockDim.x*blockIdx.x+threadIdx.x;
auto start = i - (M/2);
auto temp = 0.0;
for(auto k = 0; k < M; k++){
if((start+k >=0) && (start+k <N)){
temp += arr[start+k]*mask[k];
}
}
output[i] = temp;
}
int main(){
int N = 1048576; // size of the array = 2^20
size_t size_N = N*sizeof(double);
int M = 7; // size of the mask
size_t size_M = M*sizeof(double);
std::vector<double> h_array(N);
std::vector<double> h_mask(M);
std::vector<double> h_output(N);
for(auto& i:h_array){i = rand()%100;}
for(auto& j:h_mask){j = rand()%10;}
double *d_array, *d_mask, *d_output;
cudaMalloc(&d_array, size_N);
cudaMalloc(&d_output, size_N);
cudaMalloc(&d_mask, size_M);
cudaMemcpy(d_array, h_array.data(), size_N, cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, h_mask.data(), size_M, cudaMemcpyHostToDevice);
int threadsPerBlock = 32;
int blocksPerGrid = (N+threadsPerBlock-1)/threadsPerBlock;
convolution_kernel<<<blocksPerGrid, threadsPerBlock>>>(d_array, d_mask, d_output, N, M);
cudaMemcpy(h_output.data(), d_output, size_N, cudaMemcpyDeviceToHost);
// Uncomment to print the output
// for(auto& i:h_output){std::cout << i << std::endl;}
cudaFree(d_array);
cudaFree(d_output);
cudaFree(d_mask);
return 0;
} | .file "tmpxft_000462e8_00000000-6_convulation_simple.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
.type _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii, @function
_Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_kernelPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii, .-_Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
.globl _Z18convolution_kernelPdS_S_ii
.type _Z18convolution_kernelPdS_S_ii, @function
_Z18convolution_kernelPdS_S_ii:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z18convolution_kernelPdS_S_ii, .-_Z18convolution_kernelPdS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18convolution_kernelPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_kernelPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIdSaIdEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIdSaIdEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIdSaIdEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEEC2EmRKS0_
.type _ZNSt6vectorIdSaIdEEC2EmRKS0_, @function
_ZNSt6vectorIdSaIdEEC2EmRKS0_:
.LFB4367:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $60, %rax
jne .L23
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L15
leaq 0(,%rsi,8), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movq $0x000000000, (%rax)
addq $8, %rax
cmpq $1, %rbp
je .L18
cmpq %rax, %rdx
je .L19
.L17:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L17
jmp .L16
.L23:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L18:
movq %rax, %rdx
jmp .L16
.L19:
movq %rax, %rdx
jmp .L16
.L15:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L16:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4367:
.size _ZNSt6vectorIdSaIdEEC2EmRKS0_, .-_ZNSt6vectorIdSaIdEEC2EmRKS0_
.weak _ZNSt6vectorIdSaIdEEC1EmRKS0_
.set _ZNSt6vectorIdSaIdEEC1EmRKS0_,_ZNSt6vectorIdSaIdEEC2EmRKS0_
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4370:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L27
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L27:
ret
.cfi_endproc
.LFE4370:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 112(%rsp), %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rdx
movl $1048576, %esi
.LEHB0:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE0:
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $7, %esi
.LEHB1:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE1:
leaq 36(%rsp), %rdx
movq %rbx, %rdi
movl $1048576, %esi
.LEHB2:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE2:
movq 48(%rsp), %r12
movq 56(%rsp), %rbp
cmpq %rbp, %r12
je .L31
movq %r12, %rbx
.L32:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
jne .L32
.L31:
movq 80(%rsp), %r13
movq 88(%rsp), %rbp
cmpq %rbp, %r13
je .L33
movq %r13, %rbx
.L34:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
jne .L34
.L33:
movq %rsp, %rdi
movl $8388608, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $56, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $56, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32768, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
movl $7, %r8d
movl $1048576, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
.L35:
movl $2, %ecx
movl $8388608, %edx
movq 16(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L37:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L38:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L42:
endbr64
movq %rax, %rbx
jmp .L37
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L43-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<vector>
#include<cstdlib>
__global__ void convolution_kernel(double *arr, double *mask, double *output, int N, int M){
auto i = blockDim.x*blockIdx.x+threadIdx.x;
auto start = i - (M/2);
auto temp = 0.0;
for(auto k = 0; k < M; k++){
if((start+k >=0) && (start+k <N)){
temp += arr[start+k]*mask[k];
}
}
output[i] = temp;
}
int main(){
int N = 1048576; // size of the array = 2^20
size_t size_N = N*sizeof(double);
int M = 7; // size of the mask
size_t size_M = M*sizeof(double);
std::vector<double> h_array(N);
std::vector<double> h_mask(M);
std::vector<double> h_output(N);
for(auto& i:h_array){i = rand()%100;}
for(auto& j:h_mask){j = rand()%10;}
double *d_array, *d_mask, *d_output;
cudaMalloc(&d_array, size_N);
cudaMalloc(&d_output, size_N);
cudaMalloc(&d_mask, size_M);
cudaMemcpy(d_array, h_array.data(), size_N, cudaMemcpyHostToDevice);
cudaMemcpy(d_mask, h_mask.data(), size_M, cudaMemcpyHostToDevice);
int threadsPerBlock = 32;
int blocksPerGrid = (N+threadsPerBlock-1)/threadsPerBlock;
convolution_kernel<<<blocksPerGrid, threadsPerBlock>>>(d_array, d_mask, d_output, N, M);
cudaMemcpy(h_output.data(), d_output, size_N, cudaMemcpyDeviceToHost);
// Uncomment to print the output
// for(auto& i:h_output){std::cout << i << std::endl;}
cudaFree(d_array);
cudaFree(d_output);
cudaFree(d_mask);
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include<vector>
#include<cstdlib>
__global__ void convolution_kernel(double *arr, double *mask, double *output, int N, int M){
auto i = blockDim.x*blockIdx.x+threadIdx.x;
auto start = i - (M/2);
auto temp = 0.0;
for(auto k = 0; k < M; k++){
if((start+k >=0) && (start+k <N)){
temp += arr[start+k]*mask[k];
}
}
output[i] = temp;
}
int main(){
int N = 1048576; // size of the array = 2^20
size_t size_N = N*sizeof(double);
int M = 7; // size of the mask
size_t size_M = M*sizeof(double);
std::vector<double> h_array(N);
std::vector<double> h_mask(M);
std::vector<double> h_output(N);
for(auto& i:h_array){i = rand()%100;}
for(auto& j:h_mask){j = rand()%10;}
double *d_array, *d_mask, *d_output;
hipMalloc(&d_array, size_N);
hipMalloc(&d_output, size_N);
hipMalloc(&d_mask, size_M);
hipMemcpy(d_array, h_array.data(), size_N, hipMemcpyHostToDevice);
hipMemcpy(d_mask, h_mask.data(), size_M, hipMemcpyHostToDevice);
int threadsPerBlock = 32;
int blocksPerGrid = (N+threadsPerBlock-1)/threadsPerBlock;
convolution_kernel<<<blocksPerGrid, threadsPerBlock>>>(d_array, d_mask, d_output, N, M);
hipMemcpy(h_output.data(), d_output, size_N, hipMemcpyDeviceToHost);
// Uncomment to print the output
// for(auto& i:h_output){std::cout << i << std::endl;}
hipFree(d_array);
hipFree(d_output);
hipFree(d_mask);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<vector>
#include<cstdlib>
__global__ void convolution_kernel(double *arr, double *mask, double *output, int N, int M){
auto i = blockDim.x*blockIdx.x+threadIdx.x;
auto start = i - (M/2);
auto temp = 0.0;
for(auto k = 0; k < M; k++){
if((start+k >=0) && (start+k <N)){
temp += arr[start+k]*mask[k];
}
}
output[i] = temp;
}
int main(){
int N = 1048576; // size of the array = 2^20
size_t size_N = N*sizeof(double);
int M = 7; // size of the mask
size_t size_M = M*sizeof(double);
std::vector<double> h_array(N);
std::vector<double> h_mask(M);
std::vector<double> h_output(N);
for(auto& i:h_array){i = rand()%100;}
for(auto& j:h_mask){j = rand()%10;}
double *d_array, *d_mask, *d_output;
hipMalloc(&d_array, size_N);
hipMalloc(&d_output, size_N);
hipMalloc(&d_mask, size_M);
hipMemcpy(d_array, h_array.data(), size_N, hipMemcpyHostToDevice);
hipMemcpy(d_mask, h_mask.data(), size_M, hipMemcpyHostToDevice);
int threadsPerBlock = 32;
int blocksPerGrid = (N+threadsPerBlock-1)/threadsPerBlock;
convolution_kernel<<<blocksPerGrid, threadsPerBlock>>>(d_array, d_mask, d_output, N, M);
hipMemcpy(h_output.data(), d_output, size_N, hipMemcpyDeviceToHost);
// Uncomment to print the output
// for(auto& i:h_output){std::cout << i << std::endl;}
hipFree(d_array);
hipFree(d_output);
hipFree(d_mask);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convolution_kernelPdS_S_ii
.globl _Z18convolution_kernelPdS_S_ii
.p2align 8
.type _Z18convolution_kernelPdS_S_ii,@function
_Z18convolution_kernelPdS_S_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
s_mul_i32 s15, s15, s3
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x18
s_lshr_b32 s8, s2, 31
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
s_add_i32 s8, s2, s8
v_mov_b32_e32 v2, 0
s_ashr_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s8, s15, s8
v_add_nc_u32_e32 v3, s8, v0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s2, s2, -1
v_add_nc_u32_e32 v3, 1, v3
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v3
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 3, v[3:4]
s_load_b64 s[10:11], s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[1:2], v[5:6], s[10:11], v[1:2]
s_branch .LBB0_2
.LBB0_5:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convolution_kernelPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convolution_kernelPdS_S_ii, .Lfunc_end0-_Z18convolution_kernelPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convolution_kernelPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18convolution_kernelPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include<vector>
#include<cstdlib>
__global__ void convolution_kernel(double *arr, double *mask, double *output, int N, int M){
auto i = blockDim.x*blockIdx.x+threadIdx.x;
auto start = i - (M/2);
auto temp = 0.0;
for(auto k = 0; k < M; k++){
if((start+k >=0) && (start+k <N)){
temp += arr[start+k]*mask[k];
}
}
output[i] = temp;
}
int main(){
int N = 1048576; // size of the array = 2^20
size_t size_N = N*sizeof(double);
int M = 7; // size of the mask
size_t size_M = M*sizeof(double);
std::vector<double> h_array(N);
std::vector<double> h_mask(M);
std::vector<double> h_output(N);
for(auto& i:h_array){i = rand()%100;}
for(auto& j:h_mask){j = rand()%10;}
double *d_array, *d_mask, *d_output;
hipMalloc(&d_array, size_N);
hipMalloc(&d_output, size_N);
hipMalloc(&d_mask, size_M);
hipMemcpy(d_array, h_array.data(), size_N, hipMemcpyHostToDevice);
hipMemcpy(d_mask, h_mask.data(), size_M, hipMemcpyHostToDevice);
int threadsPerBlock = 32;
int blocksPerGrid = (N+threadsPerBlock-1)/threadsPerBlock;
convolution_kernel<<<blocksPerGrid, threadsPerBlock>>>(d_array, d_mask, d_output, N, M);
hipMemcpy(h_output.data(), d_output, size_N, hipMemcpyDeviceToHost);
// Uncomment to print the output
// for(auto& i:h_output){std::cout << i << std::endl;}
hipFree(d_array);
hipFree(d_output);
hipFree(d_mask);
return 0;
} | .text
.file "convulation_simple.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__convolution_kernelPdS_S_ii # -- Begin function _Z33__device_stub__convolution_kernelPdS_S_ii
.p2align 4, 0x90
.type _Z33__device_stub__convolution_kernelPdS_S_ii,@function
_Z33__device_stub__convolution_kernelPdS_S_ii: # @_Z33__device_stub__convolution_kernelPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_kernelPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_kernelPdS_S_ii, .Lfunc_end0-_Z33__device_stub__convolution_kernelPdS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $8388608, %edi # imm = 0x800000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $56, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit36
movq %rax, %r14
xorpd %xmm0, %xmm0
movupd %xmm0, 32(%rax)
movupd %xmm0, 16(%rax)
movupd %xmm0, (%rax)
movq $0, 48(%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $8388608, %edi # imm = 0x800000
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit37
movq %rax, %r15
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r12)
addq $8, %r12
cmpq $8388608, %r12 # imm = 0x800000
jne .LBB1_3
# %bb.4: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%r12)
addq $8, %r12
cmpq $56, %r12
jne .LBB1_5
# %bb.6:
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
.Ltmp7:
# %bb.7: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
.Ltmp9:
# %bb.8: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit38
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $56, %esi
callq hipMalloc
.Ltmp11:
# %bb.9: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit39
movq 24(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10:
movq 16(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $56, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.11:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4295000064, %rdi # imm = 0x100008000
movabsq $4294967328, %rdx # imm = 0x100000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.12:
testl %eax, %eax
jne .LBB1_15
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1048576, 36(%rsp) # imm = 0x100000
movl $7, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.14: # %.noexc
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z18convolution_kernelPdS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB1_15:
movq 8(%rsp), %rsi
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $8388608, %edx # imm = 0x800000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp24:
# %bb.16:
movq 24(%rsp), %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp26:
# %bb.17:
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.18:
movq 16(%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp30:
# %bb.19: # %_ZNSt6vectorIdSaIdEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 192
.Ltmp5:
movq %rax, %r12
jmp .LBB1_24
.LBB1_20:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_25
.LBB1_22:
.Ltmp16:
jmp .LBB1_23
.LBB1_26:
.Ltmp31:
.LBB1_23: # %_ZNSt6vectorIdSaIdEED2Ev.exit46
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIdSaIdEED2Ev.exit48
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_25: # %_ZNSt6vectorIdSaIdEED2Ev.exit50
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp6 # Call between .Ltmp6 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp17 # Call between .Ltmp17 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end1-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_kernelPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_kernelPdS_S_ii,@object # @_Z18convolution_kernelPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z18convolution_kernelPdS_S_ii
.p2align 3, 0x0
_Z18convolution_kernelPdS_S_ii:
.quad _Z33__device_stub__convolution_kernelPdS_S_ii
.size _Z18convolution_kernelPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_kernelPdS_S_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_kernelPdS_S_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z18convolution_kernelPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18convolution_kernelPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fd800078e0203 */
/*0080*/ @!P0 BRA 0x4f0 ; /* 0x0000046000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R6, R5.reuse, -0x1, RZ ; /* 0xffffffff05067810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00b0*/ LOP3.LUT R4, R5.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305047812 */
/* 0x040fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*00d0*/ LEA.HI R5, R5, c[0x0][0x17c], RZ, 0x1 ; /* 0x00005f0005057a11 */
/* 0x000fe200078f08ff */
/*00e0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*00f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0100*/ SHF.R.S32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fce0000011405 */
/*0110*/ @!P1 BRA 0x3a0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R24, -R5, 0x3, R2 ; /* 0x0000000305187810 */
/* 0x000fe20007ffe102 */
/*0130*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3 R25, R4, -c[0x0][0x17c], RZ ; /* 0x80005f0004197a10 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe200078e00ff */
/*0160*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0180*/ IADD3 R13, R24, -0x3, RZ ; /* 0xfffffffd180d7810 */
/* 0x000fc80007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P2, PT, R13, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x000fda0003f46070 */
/*01a0*/ @!P2 IMAD.MOV.U32 R12, RZ, RZ, 0x8 ; /* 0x00000008ff0ca424 */
/* 0x000fe200078e00ff */
/*01b0*/ @!P2 LDG.E.64 R10, [R8.64] ; /* 0x00000008080aa981 */
/* 0x001ea6000c1e1b00 */
/*01c0*/ @!P2 IMAD.WIDE.U32 R12, R13, R12, c[0x0][0x160] ; /* 0x000058000d0ca625 */
/* 0x000fcc00078e000c */
/*01d0*/ @!P2 LDG.E.64 R12, [R12.64] ; /* 0x000000080c0ca981 */
/* 0x000ea2000c1e1b00 */
/*01e0*/ IADD3 R16, R24.reuse, -0x2, RZ ; /* 0xfffffffe18107810 */
/* 0x040fe40007ffe0ff */
/*01f0*/ IADD3 R20, R24, -0x1, RZ ; /* 0xffffffff18147810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P3, PT, R16, c[0x0][0x178], PT ; /* 0x00005e0010007a0c */
/* 0x000fe40003f66070 */
/*0210*/ ISETP.GE.U32.AND P4, PT, R20, c[0x0][0x178], PT ; /* 0x00005e0014007a0c */
/* 0x000fe40003f86070 */
/*0220*/ ISETP.GE.U32.AND P1, PT, R24, c[0x0][0x178], PT ; /* 0x00005e0018007a0c */
/* 0x000fd20003f26070 */
/*0230*/ @!P3 IMAD.MOV.U32 R17, RZ, RZ, 0x8 ; /* 0x00000008ff11b424 */
/* 0x000fe200078e00ff */
/*0240*/ @!P3 LDG.E.64 R14, [R8.64+0x8] ; /* 0x00000808080eb981 */
/* 0x000ee2000c1e1b00 */
/*0250*/ @!P4 IMAD.MOV.U32 R21, RZ, RZ, 0x8 ; /* 0x00000008ff15c424 */
/* 0x000fe400078e00ff */
/*0260*/ @!P3 IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x160] ; /* 0x000058001010b625 */
/* 0x000fe200078e0011 */
/*0270*/ @!P4 LDG.E.64 R18, [R8.64+0x10] ; /* 0x000010080812c981 */
/* 0x000126000c1e1b00 */
/*0280*/ @!P4 IMAD.WIDE.U32 R20, R20, R21, c[0x0][0x160] ; /* 0x000058001414c625 */
/* 0x000fe400078e0015 */
/*0290*/ @!P3 LDG.E.64 R16, [R16.64] ; /* 0x000000081010b981 */
/* 0x000ee4000c1e1b00 */
/*02a0*/ @!P1 IMAD.MOV.U32 R23, RZ, RZ, 0x8 ; /* 0x00000008ff179424 */
/* 0x000fc400078e00ff */
/*02b0*/ @!P4 LDG.E.64 R20, [R20.64] ; /* 0x000000081414c981 */
/* 0x000f24000c1e1b00 */
/*02c0*/ @!P1 IMAD.WIDE.U32 R22, R24, R23, c[0x0][0x160] ; /* 0x0000580018169625 */
/* 0x000fcc00078e0017 */
/*02d0*/ @!P1 LDG.E.64 R22, [R22.64] ; /* 0x0000000816169981 */
/* 0x000f62000c1e1b00 */
/*02e0*/ @!P2 DFMA R6, R10, R12, R6 ; /* 0x0000000c0a06a22b */
/* 0x0062c60000000006 */
/*02f0*/ @!P1 LDG.E.64 R10, [R8.64+0x18] ; /* 0x00001808080a9981 */
/* 0x002162000c1e1b00 */
/*0300*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fcc000fffe03f */
/*0310*/ IADD3 R12, R25, UR4, RZ ; /* 0x00000004190c7c10 */
/* 0x000fc8000fffe0ff */
/*0320*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f45270 */
/*0330*/ @!P3 DFMA R6, R14, R16, R6 ; /* 0x000000100e06b22b */
/* 0x008f220000000006 */
/*0340*/ IADD3 R8, P3, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x001fca0007f7e0ff */
/*0350*/ @!P4 DFMA R6, R18, R20, R6 ; /* 0x000000141206c22b */
/* 0x010f620000000006 */
/*0360*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe200018e0609 */
/*0370*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fc80007ffe0ff */
/*0380*/ @!P1 DFMA R6, R10, R22, R6 ; /* 0x000000160a06922b */
/* 0x0200620000000006 */
/*0390*/ @P2 BRA 0x180 ; /* 0xfffffde000002947 */
/* 0x000fea000383ffff */
/*03a0*/ @!P0 BRA 0x4f0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*03b0*/ IADD3 R3, R3, UR4, RZ ; /* 0x0000000403037c10 */
/* 0x000fe2000fffe0ff */
/*03c0*/ UMOV UR5, 0x8 ; /* 0x0000000800057882 */
/* 0x000fe40000000000 */
/*03d0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*03e0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fe200078e0203 */
/*03f0*/ UIMAD.WIDE UR4, UR4, UR5, UR6 ; /* 0x00000005040472a5 */
/* 0x000fc6000f8e0206 */
/*0400*/ IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a05 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0420*/ IMAD.U32 R10, RZ, RZ, UR4 ; /* 0x00000004ff0a7e24 */
/* 0x001fe4000f8e00ff */
/*0430*/ IMAD.U32 R11, RZ, RZ, UR5 ; /* 0x00000005ff0b7e24 */
/* 0x000fd4000f8e00ff */
/*0440*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff098424 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 LDG.E.64 R10, [R10.64] ; /* 0x000000080a0a8981 */
/* 0x000ea6000c1e1b00 */
/*0460*/ @!P0 IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000088625 */
/* 0x000fcc00078e0009 */
/*0470*/ @!P0 LDG.E.64 R8, [R8.64] ; /* 0x0000000808088981 */
/* 0x000ea2000c1e1b00 */
/*0480*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0490*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f25270 */
/*04a0*/ UIADD3 UR4, UP0, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000ff1e03f */
/*04b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*04d0*/ @!P0 DFMA R6, R10, R8, R6 ; /* 0x000000080a06822b */
/* 0x00604e0000000006 */
/*04e0*/ @P1 BRA 0x410 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*04f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0003 */
/*0510*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x002fe2000c101b08 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18convolution_kernelPdS_S_ii
.globl _Z18convolution_kernelPdS_S_ii
.p2align 8
.type _Z18convolution_kernelPdS_S_ii,@function
_Z18convolution_kernelPdS_S_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
s_mul_i32 s15, s15, s3
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x18
s_lshr_b32 s8, s2, 31
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
s_add_i32 s8, s2, s8
v_mov_b32_e32 v2, 0
s_ashr_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s8, s15, s8
v_add_nc_u32_e32 v3, s8, v0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s8
s_add_i32 s2, s2, -1
v_add_nc_u32_e32 v3, 1, v3
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s3, v3
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[5:6], 3, v[3:4]
s_load_b64 s[10:11], s[6:7], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[1:2], v[5:6], s[10:11], v[1:2]
s_branch .LBB0_2
.LBB0_5:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s15, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18convolution_kernelPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18convolution_kernelPdS_S_ii, .Lfunc_end0-_Z18convolution_kernelPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18convolution_kernelPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18convolution_kernelPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000462e8_00000000-6_convulation_simple.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
.type _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii, @function
_Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18convolution_kernelPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii, .-_Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
.globl _Z18convolution_kernelPdS_S_ii
.type _Z18convolution_kernelPdS_S_ii, @function
_Z18convolution_kernelPdS_S_ii:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z18convolution_kernelPdS_S_ii, .-_Z18convolution_kernelPdS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18convolution_kernelPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18convolution_kernelPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIdSaIdEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIdSaIdEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIdSaIdEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEEC2EmRKS0_
.type _ZNSt6vectorIdSaIdEEC2EmRKS0_, @function
_ZNSt6vectorIdSaIdEEC2EmRKS0_:
.LFB4367:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $60, %rax
jne .L23
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L15
leaq 0(,%rsi,8), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movq $0x000000000, (%rax)
addq $8, %rax
cmpq $1, %rbp
je .L18
cmpq %rax, %rdx
je .L19
.L17:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L17
jmp .L16
.L23:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L18:
movq %rax, %rdx
jmp .L16
.L19:
movq %rax, %rdx
jmp .L16
.L15:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L16:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4367:
.size _ZNSt6vectorIdSaIdEEC2EmRKS0_, .-_ZNSt6vectorIdSaIdEEC2EmRKS0_
.weak _ZNSt6vectorIdSaIdEEC1EmRKS0_
.set _ZNSt6vectorIdSaIdEEC1EmRKS0_,_ZNSt6vectorIdSaIdEEC2EmRKS0_
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4370:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L27
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L27:
ret
.cfi_endproc
.LFE4370:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 112(%rsp), %rbx
leaq 48(%rsp), %rdi
movq %rbx, %rdx
movl $1048576, %esi
.LEHB0:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE0:
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $7, %esi
.LEHB1:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE1:
leaq 36(%rsp), %rdx
movq %rbx, %rdi
movl $1048576, %esi
.LEHB2:
call _ZNSt6vectorIdSaIdEEC1EmRKS0_
.LEHE2:
movq 48(%rsp), %r12
movq 56(%rsp), %rbp
cmpq %rbp, %r12
je .L31
movq %r12, %rbx
.L32:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
jne .L32
.L31:
movq 80(%rsp), %r13
movq 88(%rsp), %rbp
cmpq %rbp, %r13
je .L33
movq %r13, %rbx
.L34:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbx, %rbp
jne .L34
.L33:
movq %rsp, %rdi
movl $8388608, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $56, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $56, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32768, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L35
movl $7, %r8d
movl $1048576, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z44__device_stub__Z18convolution_kernelPdS_S_iiPdS_S_ii
.L35:
movl $2, %ecx
movl $8388608, %edx
movq 16(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L37:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L38:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L39
call __stack_chk_fail@PLT
.L42:
endbr64
movq %rax, %rbx
jmp .L37
.L41:
endbr64
movq %rax, %rbx
jmp .L38
.L39:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L41-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L42-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L43-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convulation_simple.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__convolution_kernelPdS_S_ii # -- Begin function _Z33__device_stub__convolution_kernelPdS_S_ii
.p2align 4, 0x90
.type _Z33__device_stub__convolution_kernelPdS_S_ii,@function
_Z33__device_stub__convolution_kernelPdS_S_ii: # @_Z33__device_stub__convolution_kernelPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18convolution_kernelPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__convolution_kernelPdS_S_ii, .Lfunc_end0-_Z33__device_stub__convolution_kernelPdS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $8388608, %edi # imm = 0x800000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $56, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit36
movq %rax, %r14
xorpd %xmm0, %xmm0
movupd %xmm0, 32(%rax)
movupd %xmm0, 16(%rax)
movupd %xmm0, (%rax)
movq $0, 48(%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $8388608, %edi # imm = 0x800000
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIdSaIdEEC2EmRKS0_.exit37
movq %rax, %r15
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
movl $8388608, %edx # imm = 0x800000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%r12)
addq $8, %r12
cmpq $8388608, %r12 # imm = 0x800000
jne .LBB1_3
# %bb.4: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%r12)
addq $8, %r12
cmpq $56, %r12
jne .LBB1_5
# %bb.6:
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
.Ltmp7:
# %bb.7: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
.Ltmp9:
# %bb.8: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit38
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $56, %esi
callq hipMalloc
.Ltmp11:
# %bb.9: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit39
movq 24(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $8388608, %edx # imm = 0x800000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10:
movq 16(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $56, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.11:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4295000064, %rdi # imm = 0x100008000
movabsq $4294967328, %rdx # imm = 0x100000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.12:
testl %eax, %eax
jne .LBB1_15
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1048576, 36(%rsp) # imm = 0x100000
movl $7, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.14: # %.noexc
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 112(%rsp), %r9
movl $_Z18convolution_kernelPdS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB1_15:
movq 8(%rsp), %rsi
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $8388608, %edx # imm = 0x800000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp24:
# %bb.16:
movq 24(%rsp), %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp26:
# %bb.17:
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.18:
movq 16(%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp30:
# %bb.19: # %_ZNSt6vectorIdSaIdEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 192
.Ltmp5:
movq %rax, %r12
jmp .LBB1_24
.LBB1_20:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_25
.LBB1_22:
.Ltmp16:
jmp .LBB1_23
.LBB1_26:
.Ltmp31:
.LBB1_23: # %_ZNSt6vectorIdSaIdEED2Ev.exit46
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIdSaIdEED2Ev.exit48
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_25: # %_ZNSt6vectorIdSaIdEED2Ev.exit50
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp15-.Ltmp6 # Call between .Ltmp6 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp17 # Call between .Ltmp17 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end1-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18convolution_kernelPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18convolution_kernelPdS_S_ii,@object # @_Z18convolution_kernelPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z18convolution_kernelPdS_S_ii
.p2align 3, 0x0
_Z18convolution_kernelPdS_S_ii:
.quad _Z33__device_stub__convolution_kernelPdS_S_ii
.size _Z18convolution_kernelPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18convolution_kernelPdS_S_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__convolution_kernelPdS_S_ii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z18convolution_kernelPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void UpdateCC_XY( float *CCXY, int id_CC, float *XY_tofill, int dim_XY ){
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if(id < dim_XY)
CCXY[id_CC*dim_XY + id] = XY_tofill[id];
} | code for sm_80
Function : _Z11UpdateCC_XYPfiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD R4, R7, c[0x0][0x168], R0 ; /* 0x00005a0007047a24 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void UpdateCC_XY( float *CCXY, int id_CC, float *XY_tofill, int dim_XY ){
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if(id < dim_XY)
CCXY[id_CC*dim_XY + id] = XY_tofill[id];
} | .file "tmpxft_0009b7ac_00000000-6_UpdateCC_XY.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i
.type _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i, @function
_Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11UpdateCC_XYPfiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i, .-_Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i
.globl _Z11UpdateCC_XYPfiS_i
.type _Z11UpdateCC_XYPfiS_i, @function
_Z11UpdateCC_XYPfiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11UpdateCC_XYPfiS_i, .-_Z11UpdateCC_XYPfiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11UpdateCC_XYPfiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11UpdateCC_XYPfiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void UpdateCC_XY( float *CCXY, int id_CC, float *XY_tofill, int dim_XY ){
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if(id < dim_XY)
CCXY[id_CC*dim_XY + id] = XY_tofill[id];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateCC_XY( float *CCXY, int id_CC, float *XY_tofill, int dim_XY ){
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if(id < dim_XY)
CCXY[id_CC*dim_XY + id] = XY_tofill[id];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateCC_XY( float *CCXY, int id_CC, float *XY_tofill, int dim_XY ){
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if(id < dim_XY)
CCXY[id_CC*dim_XY + id] = XY_tofill[id];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11UpdateCC_XYPfiS_i
.globl _Z11UpdateCC_XYPfiS_i
.p2align 8
.type _Z11UpdateCC_XYPfiS_i,@function
_Z11UpdateCC_XYPfiS_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_clause 0x1
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11UpdateCC_XYPfiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11UpdateCC_XYPfiS_i, .Lfunc_end0-_Z11UpdateCC_XYPfiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11UpdateCC_XYPfiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11UpdateCC_XYPfiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateCC_XY( float *CCXY, int id_CC, float *XY_tofill, int dim_XY ){
int id = blockDim.x*blockIdx.y*gridDim.x + blockDim.x*blockIdx.x + threadIdx.x;
if(id < dim_XY)
CCXY[id_CC*dim_XY + id] = XY_tofill[id];
} | .text
.file "UpdateCC_XY.hip"
.globl _Z26__device_stub__UpdateCC_XYPfiS_i # -- Begin function _Z26__device_stub__UpdateCC_XYPfiS_i
.p2align 4, 0x90
.type _Z26__device_stub__UpdateCC_XYPfiS_i,@function
_Z26__device_stub__UpdateCC_XYPfiS_i: # @_Z26__device_stub__UpdateCC_XYPfiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11UpdateCC_XYPfiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__UpdateCC_XYPfiS_i, .Lfunc_end0-_Z26__device_stub__UpdateCC_XYPfiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11UpdateCC_XYPfiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11UpdateCC_XYPfiS_i,@object # @_Z11UpdateCC_XYPfiS_i
.section .rodata,"a",@progbits
.globl _Z11UpdateCC_XYPfiS_i
.p2align 3, 0x0
_Z11UpdateCC_XYPfiS_i:
.quad _Z26__device_stub__UpdateCC_XYPfiS_i
.size _Z11UpdateCC_XYPfiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11UpdateCC_XYPfiS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__UpdateCC_XYPfiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11UpdateCC_XYPfiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11UpdateCC_XYPfiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD R4, R7, c[0x0][0x168], R0 ; /* 0x00005a0007047a24 */
/* 0x000fc800078e0200 */
/*00e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11UpdateCC_XYPfiS_i
.globl _Z11UpdateCC_XYPfiS_i
.p2align 8
.type _Z11UpdateCC_XYPfiS_i,@function
_Z11UpdateCC_XYPfiS_i:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_clause 0x1
s_load_b32 s3, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11UpdateCC_XYPfiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11UpdateCC_XYPfiS_i, .Lfunc_end0-_Z11UpdateCC_XYPfiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11UpdateCC_XYPfiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11UpdateCC_XYPfiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009b7ac_00000000-6_UpdateCC_XY.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i
.type _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i, @function
_Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11UpdateCC_XYPfiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i, .-_Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i
.globl _Z11UpdateCC_XYPfiS_i
.type _Z11UpdateCC_XYPfiS_i, @function
_Z11UpdateCC_XYPfiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11UpdateCC_XYPfiS_iPfiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11UpdateCC_XYPfiS_i, .-_Z11UpdateCC_XYPfiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11UpdateCC_XYPfiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11UpdateCC_XYPfiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "UpdateCC_XY.hip"
.globl _Z26__device_stub__UpdateCC_XYPfiS_i # -- Begin function _Z26__device_stub__UpdateCC_XYPfiS_i
.p2align 4, 0x90
.type _Z26__device_stub__UpdateCC_XYPfiS_i,@function
_Z26__device_stub__UpdateCC_XYPfiS_i: # @_Z26__device_stub__UpdateCC_XYPfiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11UpdateCC_XYPfiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__UpdateCC_XYPfiS_i, .Lfunc_end0-_Z26__device_stub__UpdateCC_XYPfiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11UpdateCC_XYPfiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11UpdateCC_XYPfiS_i,@object # @_Z11UpdateCC_XYPfiS_i
.section .rodata,"a",@progbits
.globl _Z11UpdateCC_XYPfiS_i
.p2align 3, 0x0
_Z11UpdateCC_XYPfiS_i:
.quad _Z26__device_stub__UpdateCC_XYPfiS_i
.size _Z11UpdateCC_XYPfiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11UpdateCC_XYPfiS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__UpdateCC_XYPfiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11UpdateCC_XYPfiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define N 10000
int main()
{
int sum = 0;
double x, y;
double start, end;
start = clock();
for (int i = 0; i < N; i++)
{
x = (double) rand() / RAND_MAX;
y = (double) rand() / RAND_MAX;
if(x*x + y*y < 1)
sum++;
}
end = clock();
printf("PI = %f\n", (double) 4 * sum / (N - 1));
printf("Cost time %lf sec. \n", (double)(end - start)/CLOCKS_PER_SEC);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define N 10000
int main()
{
int sum = 0;
double x, y;
double start, end;
start = clock();
for (int i = 0; i < N; i++)
{
x = (double) rand() / RAND_MAX;
y = (double) rand() / RAND_MAX;
if(x*x + y*y < 1)
sum++;
}
end = clock();
printf("PI = %f\n", (double) 4 * sum / (N - 1));
printf("Cost time %lf sec. \n", (double)(end - start)/CLOCKS_PER_SEC);
return 0;
} | .file "tmpxft_00144f91_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "PI = %f\n"
.LC6:
.string "Cost time %lf sec. \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
call clock@PLT
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
movsd %xmm3, 8(%rsp)
movl $10000, %ebx
movl $0, %ebp
.L6:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rsp)
call rand@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd .LC0(%rip), %xmm1
movsd (%rsp), %xmm0
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
movsd .LC1(%rip), %xmm2
comisd %xmm0, %xmm2
seta %al
movzbl %al, %eax
addl %eax, %ebp
subl $1, %ebx
jne .L6
call clock@PLT
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movq %xmm4, %rbx
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1074790400
.align 8
.LC3:
.long 0
.long 1086556032
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define N 10000
int main()
{
int sum = 0;
double x, y;
double start, end;
start = clock();
for (int i = 0; i < N; i++)
{
x = (double) rand() / RAND_MAX;
y = (double) rand() / RAND_MAX;
if(x*x + y*y < 1)
sum++;
}
end = clock();
printf("PI = %f\n", (double) 4 * sum / (N - 1));
printf("Cost time %lf sec. \n", (double)(end - start)/CLOCKS_PER_SEC);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define N 10000
int main()
{
int sum = 0;
double x, y;
double start, end;
start = clock();
for (int i = 0; i < N; i++)
{
x = (double) rand() / RAND_MAX;
y = (double) rand() / RAND_MAX;
if(x*x + y*y < 1)
sum++;
}
end = clock();
printf("PI = %f\n", (double) 4 * sum / (N - 1));
printf("Cost time %lf sec. \n", (double)(end - start)/CLOCKS_PER_SEC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define N 10000
int main()
{
int sum = 0;
double x, y;
double start, end;
start = clock();
for (int i = 0; i < N; i++)
{
x = (double) rand() / RAND_MAX;
y = (double) rand() / RAND_MAX;
if(x*x + y*y < 1)
sum++;
}
end = clock();
printf("PI = %f\n", (double) 4 * sum / (N - 1));
printf("Cost time %lf sec. \n", (double)(end - start)/CLOCKS_PER_SEC);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define N 10000
int main()
{
int sum = 0;
double x, y;
double start, end;
start = clock();
for (int i = 0; i < N; i++)
{
x = (double) rand() / RAND_MAX;
y = (double) rand() / RAND_MAX;
if(x*x + y*y < 1)
sum++;
}
end = clock();
printf("PI = %f\n", (double) 4 * sum / (N - 1));
printf("Cost time %lf sec. \n", (double)(end - start)/CLOCKS_PER_SEC);
return 0;
} | .text
.file "test.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.LCPI0_2:
.quad 0x4010000000000000 # double 4
.LCPI0_3:
.quad 0x40c3878000000000 # double 9999
.LCPI0_4:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %ebp, %ebp
movl $10000, %r14d # imm = 0x2710
callq clock
movq %rax, %rbx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
xorl %eax, %eax
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
seta %al
addl %eax, %ebp
decl %r14d
jne .LBB0_1
# %bb.2:
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
divsd .LCPI0_3(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI0_4(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI = %f\n"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cost time %lf sec. \n"
.size .L.str.1, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00144f91_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "PI = %f\n"
.LC6:
.string "Cost time %lf sec. \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
call clock@PLT
pxor %xmm3, %xmm3
cvtsi2sdq %rax, %xmm3
movsd %xmm3, 8(%rsp)
movl $10000, %ebx
movl $0, %ebp
.L6:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, (%rsp)
call rand@PLT
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd .LC0(%rip), %xmm1
movsd (%rsp), %xmm0
mulsd %xmm0, %xmm0
mulsd %xmm1, %xmm1
addsd %xmm1, %xmm0
movsd .LC1(%rip), %xmm2
comisd %xmm0, %xmm2
seta %al
movzbl %al, %eax
addl %eax, %ebp
subl $1, %ebx
jne .L6
call clock@PLT
pxor %xmm4, %xmm4
cvtsi2sdq %rax, %xmm4
movq %xmm4, %rbx
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
subsd 8(%rsp), %xmm0
divsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -4194304
.long 1105199103
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1074790400
.align 8
.LC3:
.long 0
.long 1086556032
.align 8
.LC5:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI0_1:
.quad 0x3ff0000000000000 # double 1
.LCPI0_2:
.quad 0x4010000000000000 # double 4
.LCPI0_3:
.quad 0x40c3878000000000 # double 9999
.LCPI0_4:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %ebp, %ebp
movl $10000, %r14d # imm = 0x2710
callq clock
movq %rax, %rbx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
xorl %eax, %eax
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
seta %al
addl %eax, %ebp
decl %r14d
jne .LBB0_1
# %bb.2:
xorps %xmm0, %xmm0
cvtsi2sd %rbx, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
divsd .LCPI0_3(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd .LCPI0_4(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI = %f\n"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cost time %lf sec. \n"
.size .L.str.1, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstring>
#include <ctime>
#include <iostream>
using namespace std;
#define REPEAT256(S) \
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
__global__ void setup_global(int **global, unsigned num_elements, unsigned stride) {
unsigned num_iters = num_elements / 32;
num_iters += (num_elements % num_iters) ? 1 : 0;
unsigned id = threadIdx.x;
int *end_array = (int*)&global[num_elements];
int **ptr = &global[id];
unsigned type_corrected_stride = stride * sizeof(int*) / sizeof(unsigned);
for (unsigned i = 0; i < num_iters; i++) {
if ((int*)ptr < end_array) {
int *next_address = (int*)ptr + type_corrected_stride;
if (next_address >= end_array)
next_address -= num_elements;
*ptr = next_address;
}
ptr += 32;
}
}
__global__ void global_reads_opt(int iters, unsigned array_size, int **array, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
unsigned start_index = (thread_stride * id) % array_size;
int *ptr = array[start_index];
__syncthreads();
for (int i = 0; i < iters; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
final_ptr[id] = ptr;
}
__global__ void global_reads(int warmup, int iters, unsigned array_size, int **array, unsigned block_start_offset, unsigned *total_clocks, unsigned *start_clocks, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
start_clocks[id] = 0;
total_clocks[id] = 0;
unsigned start_index = (thread_stride * id + block_start_offset) % array_size;
unsigned start_time, end_time, real_start_time;
double total_time;
int *ptr = array[start_index];
// Warmup the icache and dcache as necessary
for (int i = 0; i < warmup; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
real_start_time = clock();
for (int i = 0; i < iters; i++) {
start_time = clock();
REPEAT256(ptr = *(int**)ptr;)
end_time = clock();
if (end_time < start_time) {
total_time += ((double)(0xFFFFFFFF - (start_time - end_time)) / 1000.0);
} else {
total_time += ((double)(end_time - start_time) / 1000.0);
}
}
__syncthreads();
start_clocks[id] = real_start_time;
total_clocks[id] = (unsigned) total_time;
final_ptr[id] = ptr;
}
int main(int argc, char** argv) {
clock_t start_timer, end_timer;
int num_iterations = 8;
unsigned num_elements = 2048;
unsigned block_start_offset = 0;
unsigned warp_stride = 16;
unsigned thread_stride = 1;
int num_threads = -1;
int num_blocks = -1;
int threads_per_block = -1;
bool nice_output = false;
bool register_optimized = false;
for (int i = 1; i < argc; i++) {
if (!strcmp(argv[i], "-b")) {
if (i < argc) {
num_blocks = atoi(argv[++i]);
} else {
cout << "Need to specify number of blocks to '-b'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-e")) {
if (i < argc) {
num_elements = atoi(argv[++i]);
} else {
cout << "Need to specify number of array elements to '-e'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-i")) {
if (i < argc) {
num_iterations = atoi(argv[++i]);
} else {
cout << "Need to specify number of iterations to '-i'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-n")) {
nice_output = true;
} else if (!strcmp(argv[i], "-o")) {
if (i < argc) {
block_start_offset = atoi(argv[++i]);
} else {
cout << "Need to specify block offset to '-o'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-p")) {
if (i < argc) {
threads_per_block = atoi(argv[++i]);
} else {
cout << "Need to specify threads per block to '-p'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-r")) {
register_optimized = true;
} else if (!strcmp(argv[i], "-s")) {
if (i < argc) {
thread_stride = atoi(argv[++i]);
} else {
cout << "Need to specify thread stride to '-s'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-t")) {
if (i < argc) {
num_threads = atoi(argv[++i]);
} else {
cout << "Need to specify number of threads to '-t'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-w")) {
if (i < argc) {
warp_stride = atoi(argv[++i]);
} else {
cout << "Need to specify warp stride to '-w'\n";
exit(-1);
}
}
}
// Setup blocks and threads
if (num_threads < 0) {
if (num_blocks < 0) {
num_blocks = 1;
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
}
} else {
if (num_blocks < 0) {
if (threads_per_block < 0) {
threads_per_block = 32;
}
num_blocks = num_threads / threads_per_block;
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
} else {
if (num_blocks * threads_per_block != num_threads) {
cout << "WARNING: Your math is wrong, fixing it up\n";
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
}
}
}
}
// Host data and pointers
unsigned *start_clocks = new unsigned[num_threads];
unsigned *total_clocks = new unsigned[num_threads];
int **final_ptr = new int*[num_threads];
// Device data and pointers
int **d_global;
unsigned *d_total_clocks, *d_start_clocks;
int **d_final_ptr;
cudaMalloc(&d_global, num_elements * sizeof(int*));
cudaMalloc(&d_start_clocks, num_threads * sizeof(unsigned));
cudaMalloc(&d_total_clocks, num_threads * sizeof(unsigned));
cudaMalloc(&d_final_ptr, num_threads * sizeof(int*));
setup_global<<<1, 32>>>(d_global, num_elements, warp_stride);
cudaThreadSynchronize();
start_timer = std::clock();
if (!register_optimized) {
global_reads<<<num_blocks, threads_per_block>>>(3, num_iterations, num_elements, d_global, block_start_offset, d_total_clocks, d_start_clocks, d_final_ptr, thread_stride);
} else {
global_reads_opt<<<num_blocks, threads_per_block>>>(num_iterations, num_elements, d_global, d_final_ptr, thread_stride);
}
cudaThreadSynchronize();
end_timer = std::clock();
cudaError err = cudaGetLastError();
if (err != cudaSuccess) {
cout << "ERROR: Kernel execution failed with code: " << err
<< ", message: " << cudaGetErrorString(err) << endl;
exit(-1);
}
cudaMemcpy(start_clocks, d_start_clocks, num_threads * sizeof(unsigned), cudaMemcpyDeviceToHost);
cudaMemcpy(total_clocks, d_total_clocks, num_threads * sizeof(unsigned), cudaMemcpyDeviceToHost);
cudaMemcpy(final_ptr, d_final_ptr, num_threads * sizeof(int*), cudaMemcpyDeviceToHost);
unsigned min_kernel_time = (unsigned)0xffffffff;
unsigned max_kernel_time = 0;
for (int i = 0; i < num_threads; i++) {
if (total_clocks[i] < min_kernel_time) min_kernel_time = total_clocks[i];
if (total_clocks[i] > max_kernel_time) max_kernel_time = total_clocks[i];
}
unsigned overall_kernel_time = end_timer - start_timer;
if (!nice_output) {
cout << "Number of blocks = " << num_blocks << endl;
cout << "Threads per block = " << threads_per_block << endl;
cout << "Number of threads = " << num_threads << endl;
cout << "Stride within warp (B) = " << thread_stride * sizeof(int*) << endl;
cout << "Stride between loads (B) = " << warp_stride * sizeof(int*) << endl;
cout << "Number of iterations = " << num_iterations << endl;
cout << "Number of array elements = " << num_elements << endl;
cout << "Array size (B) = " << num_elements * sizeof(int*) << endl;
cout << "Total kernel time = " << overall_kernel_time << endl;
cout << "Min kernel time = " << min_kernel_time << endl;
cout << "Max kernel time = " << max_kernel_time << endl;
cout << "Per thread timings:\n";
for (int i = 0; i < num_threads; i++) {
cout << " " << i
<< ": start = " << start_clocks[i]
<< ", total = " << total_clocks[i]
<< ", per = " << ((double)total_clocks[i] * 1000.0 / (double)(256.0 * num_iterations))
<< ", ptr = " << final_ptr[i]
<< endl;
}
} else {
cout << num_iterations << ", "
<< num_threads << ", "
<< num_blocks << ", "
<< threads_per_block << ", "
<< (num_elements * sizeof(int*)) << ", "
<< (thread_stride * sizeof(int*)) << ", "
<< (warp_stride * sizeof(int*)) << ", "
<< overall_kernel_time << ", "
<< min_kernel_time << ", "
<< max_kernel_time
<< endl;
}
return 0;
} | .file "tmpxft_000e6329_00000000-6_global_reads.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12setup_globalPPijjPPijj
.type _Z35__device_stub__Z12setup_globalPPijjPPijj, @function
_Z35__device_stub__Z12setup_globalPPijjPPijj:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12setup_globalPPijj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z12setup_globalPPijjPPijj, .-_Z35__device_stub__Z12setup_globalPPijjPPijj
.globl _Z12setup_globalPPijj
.type _Z12setup_globalPPijj, @function
_Z12setup_globalPPijj:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12setup_globalPPijjPPijj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12setup_globalPPijj, .-_Z12setup_globalPPijj
.globl _Z43__device_stub__Z16global_reads_optijPPiS0_jijPPiS0_j
.type _Z43__device_stub__Z16global_reads_optijPPiS0_jijPPiS0_j, @function
_Z43__device_stub__Z16global_reads_optijPPiS0_jijPPiS0_j:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16global_reads_optijPPiS0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z43__device_stub__Z16global_reads_optijPPiS0_jijPPiS0_j, .-_Z43__device_stub__Z16global_reads_optijPPiS0_jijPPiS0_j
.globl _Z16global_reads_optijPPiS0_j
.type _Z16global_reads_optijPPiS0_j, @function
_Z16global_reads_optijPPiS0_j:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16global_reads_optijPPiS0_jijPPiS0_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z16global_reads_optijPPiS0_j, .-_Z16global_reads_optijPPiS0_j
.globl _Z46__device_stub__Z12global_readsiijPPijPjS1_S0_jiijPPijPjS1_S0_j
.type _Z46__device_stub__Z12global_readsiijPPijPjS1_S0_jiijPPijPjS1_S0_j, @function
_Z46__device_stub__Z12global_readsiijPPijPjS1_S0_jiijPPijPjS1_S0_j:
.LFB3698:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 32(%rsp)
movq %r9, 16(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12global_readsiijPPijPjS1_S0_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z46__device_stub__Z12global_readsiijPPijPjS1_S0_jiijPPijPjS1_S0_j, .-_Z46__device_stub__Z12global_readsiijPPijPjS1_S0_jiijPPijPjS1_S0_j
.globl _Z12global_readsiijPPijPjS1_S0_j
.type _Z12global_readsiijPPijPjS1_S0_j, @function
_Z12global_readsiijPPijPjS1_S0_j:
.LFB3699:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z12global_readsiijPPijPjS1_S0_jiijPPijPjS1_S0_j
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z12global_readsiijPPijPjS1_S0_j, .-_Z12global_readsiijPPijPjS1_S0_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "-b"
.LC1:
.string "-e"
.LC2:
.string "-i"
.LC3:
.string "-n"
.LC4:
.string "-o"
.LC5:
.string "-p"
.LC6:
.string "-r"
.LC7:
.string "-s"
.LC8:
.string "-t"
.LC9:
.string "-w"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "WARNING: Your math is wrong, fixing it up\n"
.align 8
.LC11:
.string "ERROR: Kernel execution failed with code: "
.section .rodata.str1.1
.LC12:
.string ", message: "
.LC13:
.string "Number of blocks = "
.LC14:
.string "Threads per block = "
.LC15:
.string "Number of threads = "
.LC16:
.string "Stride within warp (B) = "
.LC17:
.string "Stride between loads (B) = "
.LC18:
.string "Number of iterations = "
.LC19:
.string "Number of array elements = "
.LC20:
.string "Array size (B) = "
.LC21:
.string "Total kernel time = "
.LC22:
.string "Min kernel time = "
.LC23:
.string "Max kernel time = "
.LC24:
.string "Per thread timings:\n"
.LC25:
.string " "
.LC26:
.string ": start = "
.LC27:
.string ", total = "
.LC28:
.string ", per = "
.LC31:
.string ", ptr = "
.LC32:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L62
movl %edi, %r15d
movq %rsi, %r12
movl $1, %ebx
movb $0, 67(%rsp)
movb $0, 66(%rsp)
movl $-1, 32(%rsp)
movl $-1, 8(%rsp)
movl $-1, 12(%rsp)
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $0, 68(%rsp)
movl $2048, 36(%rsp)
movl $8, 4(%rsp)
leaq .LC0(%rip), %r14
jmp .L37
.L74:
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 8(%rsp)
.L30:
addl $1, %ebx
cmpl %ebx, %r15d
jle .L73
.L37:
movslq %ebx, %rax
leaq 0(,%rax,8), %r13
movq (%r12,%rax,8), %rbp
movq %r14, %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L74
leaq .LC1(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L75
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L76
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L63
leaq .LC4(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L77
leaq .LC5(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L78
leaq .LC6(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L64
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L79
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
je .L80
leaq .LC9(%rip), %rsi
movq %rbp, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L30
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 44(%rsp)
jmp .L30
.L75:
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 36(%rsp)
jmp .L30
.L76:
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
jmp .L30
.L77:
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 68(%rsp)
jmp .L30
.L78:
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 32(%rsp)
jmp .L30
.L79:
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 40(%rsp)
jmp .L30
.L80:
addl $1, %ebx
movq 8(%r12,%r13), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 12(%rsp)
jmp .L30
.L63:
movb $1, 66(%rsp)
jmp .L30
.L64:
movb $1, 67(%rsp)
jmp .L30
.L73:
cmpl $0, 12(%rsp)
js .L81
cmpl $0, 8(%rsp)
js .L82
cmpl $0, 32(%rsp)
js .L83
movl 8(%rsp), %ebx
movl %ebx, %eax
movl 32(%rsp), %ecx
imull %ecx, %eax
movl 12(%rsp), %r15d
cmpl %r15d, %eax
je .L28
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r15d, %eax
cltd
idivl %ebx
movl %eax, 32(%rsp)
imull %ebx, %eax
movl %eax, 12(%rsp)
jmp .L28
.L81:
cmpl $0, 8(%rsp)
js .L84
cmpl $0, 32(%rsp)
js .L85
.L40:
movl 8(%rsp), %eax
movl 32(%rsp), %ecx
imull %ecx, %eax
movl %eax, 12(%rsp)
.L28:
movslq 12(%rsp), %rbx
movq %rbx, 24(%rsp)
leaq 0(,%rbx,4), %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, 16(%rsp)
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %r13
leaq 0(,%rbx,8), %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r15
movl 36(%rsp), %eax
movq %rax, 72(%rsp)
salq $3, %rax
movq %rax, 48(%rsp)
leaq 80(%rsp), %rdi
movq %rax, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $32, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L44:
call cudaThreadSynchronize@PLT
call clock@PLT
movq %rax, 56(%rsp)
cmpb $0, 67(%rsp)
jne .L45
movl 32(%rsp), %eax
movl %eax, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl 8(%rsp), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L87
.L47:
call cudaThreadSynchronize@PLT
call clock@PLT
movq %rax, %r14
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L88
movl $2, %ecx
movq %rbp, %rdx
movq 96(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 88(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq 104(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
cmpl $0, 12(%rsp)
jle .L68
movq %r13, %rdx
leaq 0(%rbp,%r13), %rcx
movl $-1, %ebp
.L51:
movl (%rdx), %eax
cmpl %eax, %ebp
cmova %eax, %ebp
cmpl %eax, %ebx
cmovb %eax, %ebx
addq $4, %rdx
cmpq %rdx, %rcx
jne .L51
.L50:
movl 56(%rsp), %eax
subl %eax, %r14d
cmpb $0, 66(%rsp)
jne .L52
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC14(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 32(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC15(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC16(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 40(%rsp), %esi
salq $3, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC17(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 44(%rsp), %esi
salq $3, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC19(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 72(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC20(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 48(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC21(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC22(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC23(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC24(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 12(%rsp)
jle .L53
movl $0, %ebx
movq %r12, %r14
jmp .L60
.L84:
movl 32(%rsp), %eax
testl %eax, %eax
js .L65
movl %eax, 12(%rsp)
movl $1, 8(%rsp)
jmp .L28
.L85:
movl $1, 32(%rsp)
jmp .L40
.L82:
cmpl $0, 32(%rsp)
js .L89
.L42:
movl 12(%rsp), %eax
movl 32(%rsp), %ecx
cltd
idivl %ecx
movl %eax, 8(%rsp)
imull %ecx, %eax
movl %eax, 12(%rsp)
jmp .L28
.L89:
movl $32, 32(%rsp)
jmp .L42
.L83:
movl 12(%rsp), %eax
movl 8(%rsp), %ecx
cltd
idivl %ecx
movl %eax, 32(%rsp)
imull %ecx, %eax
movl %eax, 12(%rsp)
jmp .L28
.L62:
movl $1, 40(%rsp)
movl $16, 44(%rsp)
movl $0, 68(%rsp)
movb $0, 66(%rsp)
movb $0, 67(%rsp)
movl $8, 4(%rsp)
movl $2048, 36(%rsp)
movl $1, 32(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
jmp .L28
.L65:
movl $1, 32(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
jmp .L28
.L86:
movl 44(%rsp), %edx
movl 36(%rsp), %esi
movq 80(%rsp), %rdi
call _Z35__device_stub__Z12setup_globalPPijjPPijj
jmp .L44
.L87:
subq $8, %rsp
.cfi_def_cfa_offset 216
movl 48(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 224
pushq 120(%rsp)
.cfi_def_cfa_offset 232
pushq 120(%rsp)
.cfi_def_cfa_offset 240
movq 120(%rsp), %r9
movl 100(%rsp), %r8d
movq 112(%rsp), %rcx
movl 68(%rsp), %edx
movl 36(%rsp), %esi
movl $3, %edi
call _Z46__device_stub__Z12global_readsiijPPijPjS1_S0_jiijPPijPjS1_S0_j
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L47
.L45:
movl 32(%rsp), %eax
movl %eax, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl 8(%rsp), %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L47
movl 40(%rsp), %r8d
movq 104(%rsp), %rcx
movq 80(%rsp), %rdx
movl 36(%rsp), %esi
movl 4(%rsp), %edi
call _Z43__device_stub__Z16global_reads_optijPPiS0_jijPPiS0_j
jmp .L47
.L88:
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC12(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %edi
call exit@PLT
.L68:
movl $-1, %ebp
jmp .L50
.L91:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L90
call _ZSt16__throw_bad_castv@PLT
.L90:
call __stack_chk_fail@PLT
.L58:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L59:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq %rbx, 24(%rsp)
je .L53
.L60:
movl $2, %edx
leaq .LC25(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $10, %edx
leaq .LC26(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $10, %edx
leaq .LC27(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC28(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 0(%r13,%rbx,4), %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC29(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 4(%rsp), %xmm1
mulsd .LC30(%rip), %xmm1
divsd %xmm1, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC31(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r15,%rbx,8), %rsi
movq %rbp, %rdi
call _ZNSo9_M_insertIPKvEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L91
cmpb $0, 56(%r12)
je .L58
movzbl 67(%r12), %esi
jmp .L59
.L52:
movl 4(%rsp), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC32(%rip), %r12
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 8(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 32(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 48(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 40(%rsp), %esi
salq $3, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 44(%rsp), %esi
salq $3, %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r14d, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L53:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L92
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L92:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC33:
.string "_Z12global_readsiijPPijPjS1_S0_j"
.section .rodata.str1.1
.LC34:
.string "_Z16global_reads_optijPPiS0_j"
.LC35:
.string "_Z12setup_globalPPijj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC33(%rip), %rdx
movq %rdx, %rcx
leaq _Z12global_readsiijPPijPjS1_S0_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC34(%rip), %rdx
movq %rdx, %rcx
leaq _Z16global_reads_optijPPiS0_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC35(%rip), %rdx
movq %rdx, %rcx
leaq _Z12setup_globalPPijj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC29:
.long 0
.long 1083129856
.align 8
.LC30:
.long 0
.long 1081081856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstring>
#include <ctime>
#include <iostream>
using namespace std;
#define REPEAT256(S) \
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
__global__ void setup_global(int **global, unsigned num_elements, unsigned stride) {
unsigned num_iters = num_elements / 32;
num_iters += (num_elements % num_iters) ? 1 : 0;
unsigned id = threadIdx.x;
int *end_array = (int*)&global[num_elements];
int **ptr = &global[id];
unsigned type_corrected_stride = stride * sizeof(int*) / sizeof(unsigned);
for (unsigned i = 0; i < num_iters; i++) {
if ((int*)ptr < end_array) {
int *next_address = (int*)ptr + type_corrected_stride;
if (next_address >= end_array)
next_address -= num_elements;
*ptr = next_address;
}
ptr += 32;
}
}
__global__ void global_reads_opt(int iters, unsigned array_size, int **array, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
unsigned start_index = (thread_stride * id) % array_size;
int *ptr = array[start_index];
__syncthreads();
for (int i = 0; i < iters; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
final_ptr[id] = ptr;
}
__global__ void global_reads(int warmup, int iters, unsigned array_size, int **array, unsigned block_start_offset, unsigned *total_clocks, unsigned *start_clocks, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
start_clocks[id] = 0;
total_clocks[id] = 0;
unsigned start_index = (thread_stride * id + block_start_offset) % array_size;
unsigned start_time, end_time, real_start_time;
double total_time;
int *ptr = array[start_index];
// Warmup the icache and dcache as necessary
for (int i = 0; i < warmup; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
real_start_time = clock();
for (int i = 0; i < iters; i++) {
start_time = clock();
REPEAT256(ptr = *(int**)ptr;)
end_time = clock();
if (end_time < start_time) {
total_time += ((double)(0xFFFFFFFF - (start_time - end_time)) / 1000.0);
} else {
total_time += ((double)(end_time - start_time) / 1000.0);
}
}
__syncthreads();
start_clocks[id] = real_start_time;
total_clocks[id] = (unsigned) total_time;
final_ptr[id] = ptr;
}
int main(int argc, char** argv) {
clock_t start_timer, end_timer;
int num_iterations = 8;
unsigned num_elements = 2048;
unsigned block_start_offset = 0;
unsigned warp_stride = 16;
unsigned thread_stride = 1;
int num_threads = -1;
int num_blocks = -1;
int threads_per_block = -1;
bool nice_output = false;
bool register_optimized = false;
for (int i = 1; i < argc; i++) {
if (!strcmp(argv[i], "-b")) {
if (i < argc) {
num_blocks = atoi(argv[++i]);
} else {
cout << "Need to specify number of blocks to '-b'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-e")) {
if (i < argc) {
num_elements = atoi(argv[++i]);
} else {
cout << "Need to specify number of array elements to '-e'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-i")) {
if (i < argc) {
num_iterations = atoi(argv[++i]);
} else {
cout << "Need to specify number of iterations to '-i'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-n")) {
nice_output = true;
} else if (!strcmp(argv[i], "-o")) {
if (i < argc) {
block_start_offset = atoi(argv[++i]);
} else {
cout << "Need to specify block offset to '-o'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-p")) {
if (i < argc) {
threads_per_block = atoi(argv[++i]);
} else {
cout << "Need to specify threads per block to '-p'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-r")) {
register_optimized = true;
} else if (!strcmp(argv[i], "-s")) {
if (i < argc) {
thread_stride = atoi(argv[++i]);
} else {
cout << "Need to specify thread stride to '-s'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-t")) {
if (i < argc) {
num_threads = atoi(argv[++i]);
} else {
cout << "Need to specify number of threads to '-t'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-w")) {
if (i < argc) {
warp_stride = atoi(argv[++i]);
} else {
cout << "Need to specify warp stride to '-w'\n";
exit(-1);
}
}
}
// Setup blocks and threads
if (num_threads < 0) {
if (num_blocks < 0) {
num_blocks = 1;
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
}
} else {
if (num_blocks < 0) {
if (threads_per_block < 0) {
threads_per_block = 32;
}
num_blocks = num_threads / threads_per_block;
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
} else {
if (num_blocks * threads_per_block != num_threads) {
cout << "WARNING: Your math is wrong, fixing it up\n";
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
}
}
}
}
// Host data and pointers
unsigned *start_clocks = new unsigned[num_threads];
unsigned *total_clocks = new unsigned[num_threads];
int **final_ptr = new int*[num_threads];
// Device data and pointers
int **d_global;
unsigned *d_total_clocks, *d_start_clocks;
int **d_final_ptr;
cudaMalloc(&d_global, num_elements * sizeof(int*));
cudaMalloc(&d_start_clocks, num_threads * sizeof(unsigned));
cudaMalloc(&d_total_clocks, num_threads * sizeof(unsigned));
cudaMalloc(&d_final_ptr, num_threads * sizeof(int*));
setup_global<<<1, 32>>>(d_global, num_elements, warp_stride);
cudaThreadSynchronize();
start_timer = std::clock();
if (!register_optimized) {
global_reads<<<num_blocks, threads_per_block>>>(3, num_iterations, num_elements, d_global, block_start_offset, d_total_clocks, d_start_clocks, d_final_ptr, thread_stride);
} else {
global_reads_opt<<<num_blocks, threads_per_block>>>(num_iterations, num_elements, d_global, d_final_ptr, thread_stride);
}
cudaThreadSynchronize();
end_timer = std::clock();
cudaError err = cudaGetLastError();
if (err != cudaSuccess) {
cout << "ERROR: Kernel execution failed with code: " << err
<< ", message: " << cudaGetErrorString(err) << endl;
exit(-1);
}
cudaMemcpy(start_clocks, d_start_clocks, num_threads * sizeof(unsigned), cudaMemcpyDeviceToHost);
cudaMemcpy(total_clocks, d_total_clocks, num_threads * sizeof(unsigned), cudaMemcpyDeviceToHost);
cudaMemcpy(final_ptr, d_final_ptr, num_threads * sizeof(int*), cudaMemcpyDeviceToHost);
unsigned min_kernel_time = (unsigned)0xffffffff;
unsigned max_kernel_time = 0;
for (int i = 0; i < num_threads; i++) {
if (total_clocks[i] < min_kernel_time) min_kernel_time = total_clocks[i];
if (total_clocks[i] > max_kernel_time) max_kernel_time = total_clocks[i];
}
unsigned overall_kernel_time = end_timer - start_timer;
if (!nice_output) {
cout << "Number of blocks = " << num_blocks << endl;
cout << "Threads per block = " << threads_per_block << endl;
cout << "Number of threads = " << num_threads << endl;
cout << "Stride within warp (B) = " << thread_stride * sizeof(int*) << endl;
cout << "Stride between loads (B) = " << warp_stride * sizeof(int*) << endl;
cout << "Number of iterations = " << num_iterations << endl;
cout << "Number of array elements = " << num_elements << endl;
cout << "Array size (B) = " << num_elements * sizeof(int*) << endl;
cout << "Total kernel time = " << overall_kernel_time << endl;
cout << "Min kernel time = " << min_kernel_time << endl;
cout << "Max kernel time = " << max_kernel_time << endl;
cout << "Per thread timings:\n";
for (int i = 0; i < num_threads; i++) {
cout << " " << i
<< ": start = " << start_clocks[i]
<< ", total = " << total_clocks[i]
<< ", per = " << ((double)total_clocks[i] * 1000.0 / (double)(256.0 * num_iterations))
<< ", ptr = " << final_ptr[i]
<< endl;
}
} else {
cout << num_iterations << ", "
<< num_threads << ", "
<< num_blocks << ", "
<< threads_per_block << ", "
<< (num_elements * sizeof(int*)) << ", "
<< (thread_stride * sizeof(int*)) << ", "
<< (warp_stride * sizeof(int*)) << ", "
<< overall_kernel_time << ", "
<< min_kernel_time << ", "
<< max_kernel_time
<< endl;
}
return 0;
} | #include <hip/hip_runtime.h>
#include <cstring>
#include <ctime>
#include <iostream>
using namespace std;
#define REPEAT256(S) \
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
__global__ void setup_global(int **global, unsigned num_elements, unsigned stride) {
unsigned num_iters = num_elements / 32;
num_iters += (num_elements % num_iters) ? 1 : 0;
unsigned id = threadIdx.x;
int *end_array = (int*)&global[num_elements];
int **ptr = &global[id];
unsigned type_corrected_stride = stride * sizeof(int*) / sizeof(unsigned);
for (unsigned i = 0; i < num_iters; i++) {
if ((int*)ptr < end_array) {
int *next_address = (int*)ptr + type_corrected_stride;
if (next_address >= end_array)
next_address -= num_elements;
*ptr = next_address;
}
ptr += 32;
}
}
__global__ void global_reads_opt(int iters, unsigned array_size, int **array, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
unsigned start_index = (thread_stride * id) % array_size;
int *ptr = array[start_index];
__syncthreads();
for (int i = 0; i < iters; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
final_ptr[id] = ptr;
}
__global__ void global_reads(int warmup, int iters, unsigned array_size, int **array, unsigned block_start_offset, unsigned *total_clocks, unsigned *start_clocks, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
start_clocks[id] = 0;
total_clocks[id] = 0;
unsigned start_index = (thread_stride * id + block_start_offset) % array_size;
unsigned start_time, end_time, real_start_time;
double total_time;
int *ptr = array[start_index];
// Warmup the icache and dcache as necessary
for (int i = 0; i < warmup; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
real_start_time = clock();
for (int i = 0; i < iters; i++) {
start_time = clock();
REPEAT256(ptr = *(int**)ptr;)
end_time = clock();
if (end_time < start_time) {
total_time += ((double)(0xFFFFFFFF - (start_time - end_time)) / 1000.0);
} else {
total_time += ((double)(end_time - start_time) / 1000.0);
}
}
__syncthreads();
start_clocks[id] = real_start_time;
total_clocks[id] = (unsigned) total_time;
final_ptr[id] = ptr;
}
int main(int argc, char** argv) {
clock_t start_timer, end_timer;
int num_iterations = 8;
unsigned num_elements = 2048;
unsigned block_start_offset = 0;
unsigned warp_stride = 16;
unsigned thread_stride = 1;
int num_threads = -1;
int num_blocks = -1;
int threads_per_block = -1;
bool nice_output = false;
bool register_optimized = false;
for (int i = 1; i < argc; i++) {
if (!strcmp(argv[i], "-b")) {
if (i < argc) {
num_blocks = atoi(argv[++i]);
} else {
cout << "Need to specify number of blocks to '-b'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-e")) {
if (i < argc) {
num_elements = atoi(argv[++i]);
} else {
cout << "Need to specify number of array elements to '-e'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-i")) {
if (i < argc) {
num_iterations = atoi(argv[++i]);
} else {
cout << "Need to specify number of iterations to '-i'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-n")) {
nice_output = true;
} else if (!strcmp(argv[i], "-o")) {
if (i < argc) {
block_start_offset = atoi(argv[++i]);
} else {
cout << "Need to specify block offset to '-o'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-p")) {
if (i < argc) {
threads_per_block = atoi(argv[++i]);
} else {
cout << "Need to specify threads per block to '-p'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-r")) {
register_optimized = true;
} else if (!strcmp(argv[i], "-s")) {
if (i < argc) {
thread_stride = atoi(argv[++i]);
} else {
cout << "Need to specify thread stride to '-s'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-t")) {
if (i < argc) {
num_threads = atoi(argv[++i]);
} else {
cout << "Need to specify number of threads to '-t'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-w")) {
if (i < argc) {
warp_stride = atoi(argv[++i]);
} else {
cout << "Need to specify warp stride to '-w'\n";
exit(-1);
}
}
}
// Setup blocks and threads
if (num_threads < 0) {
if (num_blocks < 0) {
num_blocks = 1;
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
}
} else {
if (num_blocks < 0) {
if (threads_per_block < 0) {
threads_per_block = 32;
}
num_blocks = num_threads / threads_per_block;
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
} else {
if (num_blocks * threads_per_block != num_threads) {
cout << "WARNING: Your math is wrong, fixing it up\n";
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
}
}
}
}
// Host data and pointers
unsigned *start_clocks = new unsigned[num_threads];
unsigned *total_clocks = new unsigned[num_threads];
int **final_ptr = new int*[num_threads];
// Device data and pointers
int **d_global;
unsigned *d_total_clocks, *d_start_clocks;
int **d_final_ptr;
hipMalloc(&d_global, num_elements * sizeof(int*));
hipMalloc(&d_start_clocks, num_threads * sizeof(unsigned));
hipMalloc(&d_total_clocks, num_threads * sizeof(unsigned));
hipMalloc(&d_final_ptr, num_threads * sizeof(int*));
setup_global<<<1, 32>>>(d_global, num_elements, warp_stride);
hipDeviceSynchronize();
start_timer = std::clock();
if (!register_optimized) {
global_reads<<<num_blocks, threads_per_block>>>(3, num_iterations, num_elements, d_global, block_start_offset, d_total_clocks, d_start_clocks, d_final_ptr, thread_stride);
} else {
global_reads_opt<<<num_blocks, threads_per_block>>>(num_iterations, num_elements, d_global, d_final_ptr, thread_stride);
}
hipDeviceSynchronize();
end_timer = std::clock();
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
cout << "ERROR: Kernel execution failed with code: " << err
<< ", message: " << hipGetErrorString(err) << endl;
exit(-1);
}
hipMemcpy(start_clocks, d_start_clocks, num_threads * sizeof(unsigned), hipMemcpyDeviceToHost);
hipMemcpy(total_clocks, d_total_clocks, num_threads * sizeof(unsigned), hipMemcpyDeviceToHost);
hipMemcpy(final_ptr, d_final_ptr, num_threads * sizeof(int*), hipMemcpyDeviceToHost);
unsigned min_kernel_time = (unsigned)0xffffffff;
unsigned max_kernel_time = 0;
for (int i = 0; i < num_threads; i++) {
if (total_clocks[i] < min_kernel_time) min_kernel_time = total_clocks[i];
if (total_clocks[i] > max_kernel_time) max_kernel_time = total_clocks[i];
}
unsigned overall_kernel_time = end_timer - start_timer;
if (!nice_output) {
cout << "Number of blocks = " << num_blocks << endl;
cout << "Threads per block = " << threads_per_block << endl;
cout << "Number of threads = " << num_threads << endl;
cout << "Stride within warp (B) = " << thread_stride * sizeof(int*) << endl;
cout << "Stride between loads (B) = " << warp_stride * sizeof(int*) << endl;
cout << "Number of iterations = " << num_iterations << endl;
cout << "Number of array elements = " << num_elements << endl;
cout << "Array size (B) = " << num_elements * sizeof(int*) << endl;
cout << "Total kernel time = " << overall_kernel_time << endl;
cout << "Min kernel time = " << min_kernel_time << endl;
cout << "Max kernel time = " << max_kernel_time << endl;
cout << "Per thread timings:\n";
for (int i = 0; i < num_threads; i++) {
cout << " " << i
<< ": start = " << start_clocks[i]
<< ", total = " << total_clocks[i]
<< ", per = " << ((double)total_clocks[i] * 1000.0 / (double)(256.0 * num_iterations))
<< ", ptr = " << final_ptr[i]
<< endl;
}
} else {
cout << num_iterations << ", "
<< num_threads << ", "
<< num_blocks << ", "
<< threads_per_block << ", "
<< (num_elements * sizeof(int*)) << ", "
<< (thread_stride * sizeof(int*)) << ", "
<< (warp_stride * sizeof(int*)) << ", "
<< overall_kernel_time << ", "
<< min_kernel_time << ", "
<< max_kernel_time
<< endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstring>
#include <ctime>
#include <iostream>
using namespace std;
#define REPEAT256(S) \
S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S
__global__ void setup_global(int **global, unsigned num_elements, unsigned stride) {
unsigned num_iters = num_elements / 32;
num_iters += (num_elements % num_iters) ? 1 : 0;
unsigned id = threadIdx.x;
int *end_array = (int*)&global[num_elements];
int **ptr = &global[id];
unsigned type_corrected_stride = stride * sizeof(int*) / sizeof(unsigned);
for (unsigned i = 0; i < num_iters; i++) {
if ((int*)ptr < end_array) {
int *next_address = (int*)ptr + type_corrected_stride;
if (next_address >= end_array)
next_address -= num_elements;
*ptr = next_address;
}
ptr += 32;
}
}
__global__ void global_reads_opt(int iters, unsigned array_size, int **array, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
unsigned start_index = (thread_stride * id) % array_size;
int *ptr = array[start_index];
__syncthreads();
for (int i = 0; i < iters; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
final_ptr[id] = ptr;
}
__global__ void global_reads(int warmup, int iters, unsigned array_size, int **array, unsigned block_start_offset, unsigned *total_clocks, unsigned *start_clocks, int **final_ptr, unsigned thread_stride) {
unsigned id = blockDim.x * blockIdx.x + threadIdx.x;
start_clocks[id] = 0;
total_clocks[id] = 0;
unsigned start_index = (thread_stride * id + block_start_offset) % array_size;
unsigned start_time, end_time, real_start_time;
double total_time;
int *ptr = array[start_index];
// Warmup the icache and dcache as necessary
for (int i = 0; i < warmup; i++) {
REPEAT256(ptr = *(int**)ptr;)
}
__syncthreads();
real_start_time = clock();
for (int i = 0; i < iters; i++) {
start_time = clock();
REPEAT256(ptr = *(int**)ptr;)
end_time = clock();
if (end_time < start_time) {
total_time += ((double)(0xFFFFFFFF - (start_time - end_time)) / 1000.0);
} else {
total_time += ((double)(end_time - start_time) / 1000.0);
}
}
__syncthreads();
start_clocks[id] = real_start_time;
total_clocks[id] = (unsigned) total_time;
final_ptr[id] = ptr;
}
int main(int argc, char** argv) {
clock_t start_timer, end_timer;
int num_iterations = 8;
unsigned num_elements = 2048;
unsigned block_start_offset = 0;
unsigned warp_stride = 16;
unsigned thread_stride = 1;
int num_threads = -1;
int num_blocks = -1;
int threads_per_block = -1;
bool nice_output = false;
bool register_optimized = false;
for (int i = 1; i < argc; i++) {
if (!strcmp(argv[i], "-b")) {
if (i < argc) {
num_blocks = atoi(argv[++i]);
} else {
cout << "Need to specify number of blocks to '-b'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-e")) {
if (i < argc) {
num_elements = atoi(argv[++i]);
} else {
cout << "Need to specify number of array elements to '-e'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-i")) {
if (i < argc) {
num_iterations = atoi(argv[++i]);
} else {
cout << "Need to specify number of iterations to '-i'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-n")) {
nice_output = true;
} else if (!strcmp(argv[i], "-o")) {
if (i < argc) {
block_start_offset = atoi(argv[++i]);
} else {
cout << "Need to specify block offset to '-o'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-p")) {
if (i < argc) {
threads_per_block = atoi(argv[++i]);
} else {
cout << "Need to specify threads per block to '-p'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-r")) {
register_optimized = true;
} else if (!strcmp(argv[i], "-s")) {
if (i < argc) {
thread_stride = atoi(argv[++i]);
} else {
cout << "Need to specify thread stride to '-s'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-t")) {
if (i < argc) {
num_threads = atoi(argv[++i]);
} else {
cout << "Need to specify number of threads to '-t'\n";
exit(-1);
}
} else if (!strcmp(argv[i], "-w")) {
if (i < argc) {
warp_stride = atoi(argv[++i]);
} else {
cout << "Need to specify warp stride to '-w'\n";
exit(-1);
}
}
}
// Setup blocks and threads
if (num_threads < 0) {
if (num_blocks < 0) {
num_blocks = 1;
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = 1;
}
num_threads = num_blocks * threads_per_block;
}
} else {
if (num_blocks < 0) {
if (threads_per_block < 0) {
threads_per_block = 32;
}
num_blocks = num_threads / threads_per_block;
num_threads = num_blocks * threads_per_block;
} else {
if (threads_per_block < 0) {
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
} else {
if (num_blocks * threads_per_block != num_threads) {
cout << "WARNING: Your math is wrong, fixing it up\n";
threads_per_block = num_threads / num_blocks;
num_threads = num_blocks * threads_per_block;
}
}
}
}
// Host data and pointers
unsigned *start_clocks = new unsigned[num_threads];
unsigned *total_clocks = new unsigned[num_threads];
int **final_ptr = new int*[num_threads];
// Device data and pointers
int **d_global;
unsigned *d_total_clocks, *d_start_clocks;
int **d_final_ptr;
hipMalloc(&d_global, num_elements * sizeof(int*));
hipMalloc(&d_start_clocks, num_threads * sizeof(unsigned));
hipMalloc(&d_total_clocks, num_threads * sizeof(unsigned));
hipMalloc(&d_final_ptr, num_threads * sizeof(int*));
setup_global<<<1, 32>>>(d_global, num_elements, warp_stride);
hipDeviceSynchronize();
start_timer = std::clock();
if (!register_optimized) {
global_reads<<<num_blocks, threads_per_block>>>(3, num_iterations, num_elements, d_global, block_start_offset, d_total_clocks, d_start_clocks, d_final_ptr, thread_stride);
} else {
global_reads_opt<<<num_blocks, threads_per_block>>>(num_iterations, num_elements, d_global, d_final_ptr, thread_stride);
}
hipDeviceSynchronize();
end_timer = std::clock();
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
cout << "ERROR: Kernel execution failed with code: " << err
<< ", message: " << hipGetErrorString(err) << endl;
exit(-1);
}
hipMemcpy(start_clocks, d_start_clocks, num_threads * sizeof(unsigned), hipMemcpyDeviceToHost);
hipMemcpy(total_clocks, d_total_clocks, num_threads * sizeof(unsigned), hipMemcpyDeviceToHost);
hipMemcpy(final_ptr, d_final_ptr, num_threads * sizeof(int*), hipMemcpyDeviceToHost);
unsigned min_kernel_time = (unsigned)0xffffffff;
unsigned max_kernel_time = 0;
for (int i = 0; i < num_threads; i++) {
if (total_clocks[i] < min_kernel_time) min_kernel_time = total_clocks[i];
if (total_clocks[i] > max_kernel_time) max_kernel_time = total_clocks[i];
}
unsigned overall_kernel_time = end_timer - start_timer;
if (!nice_output) {
cout << "Number of blocks = " << num_blocks << endl;
cout << "Threads per block = " << threads_per_block << endl;
cout << "Number of threads = " << num_threads << endl;
cout << "Stride within warp (B) = " << thread_stride * sizeof(int*) << endl;
cout << "Stride between loads (B) = " << warp_stride * sizeof(int*) << endl;
cout << "Number of iterations = " << num_iterations << endl;
cout << "Number of array elements = " << num_elements << endl;
cout << "Array size (B) = " << num_elements * sizeof(int*) << endl;
cout << "Total kernel time = " << overall_kernel_time << endl;
cout << "Min kernel time = " << min_kernel_time << endl;
cout << "Max kernel time = " << max_kernel_time << endl;
cout << "Per thread timings:\n";
for (int i = 0; i < num_threads; i++) {
cout << " " << i
<< ": start = " << start_clocks[i]
<< ", total = " << total_clocks[i]
<< ", per = " << ((double)total_clocks[i] * 1000.0 / (double)(256.0 * num_iterations))
<< ", ptr = " << final_ptr[i]
<< endl;
}
} else {
cout << num_iterations << ", "
<< num_threads << ", "
<< num_blocks << ", "
<< threads_per_block << ", "
<< (num_elements * sizeof(int*)) << ", "
<< (thread_stride * sizeof(int*)) << ", "
<< (warp_stride * sizeof(int*)) << ", "
<< overall_kernel_time << ", "
<< min_kernel_time << ", "
<< max_kernel_time
<< endl;
}
return 0;
} | .text
.file "global_reads.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__setup_globalPPijj # -- Begin function _Z27__device_stub__setup_globalPPijj
.p2align 4, 0x90
.type _Z27__device_stub__setup_globalPPijj,@function
_Z27__device_stub__setup_globalPPijj: # @_Z27__device_stub__setup_globalPPijj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12setup_globalPPijj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__setup_globalPPijj, .Lfunc_end0-_Z27__device_stub__setup_globalPPijj
.cfi_endproc
# -- End function
.globl _Z31__device_stub__global_reads_optijPPiS0_j # -- Begin function _Z31__device_stub__global_reads_optijPPiS0_j
.p2align 4, 0x90
.type _Z31__device_stub__global_reads_optijPPiS0_j,@function
_Z31__device_stub__global_reads_optijPPiS0_j: # @_Z31__device_stub__global_reads_optijPPiS0_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16global_reads_optijPPiS0_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z31__device_stub__global_reads_optijPPiS0_j, .Lfunc_end1-_Z31__device_stub__global_reads_optijPPiS0_j
.cfi_endproc
# -- End function
.globl _Z27__device_stub__global_readsiijPPijPjS1_S0_j # -- Begin function _Z27__device_stub__global_readsiijPPijPjS1_S0_j
.p2align 4, 0x90
.type _Z27__device_stub__global_readsiijPPijPjS1_S0_j,@function
_Z27__device_stub__global_readsiijPPijPjS1_S0_j: # @_Z27__device_stub__global_readsiijPPijPjS1_S0_j
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12global_readsiijPPijPjS1_S0_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z27__device_stub__global_readsiijPPijPjS1_S0_j, .Lfunc_end2-_Z27__device_stub__global_readsiijPPijPjS1_S0_j
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x4070000000000000 # double 256
.LCPI3_1:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 384
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jl .LBB3_1
# %bb.4: # %.lr.ph.preheader
movq %rsi, %r15
movl %edi, %ebp
movl $-1, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl $1, %eax
movq %rax, 48(%rsp) # 8-byte Spill
movl $16, %eax
movq %rax, 56(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 144(%rsp) # 8-byte Spill
movl $2048, %eax # imm = 0x800
movq %rax, 8(%rsp) # 8-byte Spill
movl $8, %eax
movq %rax, 24(%rsp) # 8-byte Spill
movl $-1, %r12d
movl $-1, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $0, 40(%rsp) # 4-byte Folded Spill
movl $0, 36(%rsp) # 4-byte Folded Spill
movl $1, %r14d
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
.LBB3_25: # in Loop: Header=BB3_5 Depth=1
incl %r14d
cmpl %ebp, %r14d
jge .LBB3_2
.LBB3_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %r14d, %r13
movq (%r15,%r13,8), %rbx
movl $.L.str, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_6
# %bb.7: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.2, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_8
# %bb.9: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.4, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_10
# %bb.11: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.6, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_12
# %bb.13: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.7, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_14
# %bb.15: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.9, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_16
# %bb.17: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.11, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_18
# %bb.19: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.12, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_20
# %bb.21: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.14, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
je .LBB3_22
# %bb.23: # in Loop: Header=BB3_5 Depth=1
movl $.L.str.16, %esi
movq %rbx, %rdi
callq strcmp
testl %eax, %eax
jne .LBB3_25
# %bb.24: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 56(%rsp) # 8-byte Spill
jmp .LBB3_25
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 8(%rsp) # 8-byte Spill
jmp .LBB3_25
.LBB3_10: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 24(%rsp) # 8-byte Spill
jmp .LBB3_25
.LBB3_12: # in Loop: Header=BB3_5 Depth=1
movb $1, %al
movl %eax, 40(%rsp) # 4-byte Spill
jmp .LBB3_25
.LBB3_14: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 144(%rsp) # 8-byte Spill
jmp .LBB3_25
.LBB3_16: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB3_25
.LBB3_18: # in Loop: Header=BB3_5 Depth=1
movb $1, %al
movl %eax, 36(%rsp) # 4-byte Spill
jmp .LBB3_25
.LBB3_20: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 48(%rsp) # 8-byte Spill
jmp .LBB3_25
.LBB3_22: # in Loop: Header=BB3_5 Depth=1
leal 1(%r13), %r14d
movq 8(%r15,%r13,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB3_25
.LBB3_1:
movl $8, %eax
movq %rax, 24(%rsp) # 8-byte Spill
movl $2048, %eax # imm = 0x800
movq %rax, 8(%rsp) # 8-byte Spill
movl $0, 36(%rsp) # 4-byte Folded Spill
movl $16, %eax
movq %rax, 56(%rsp) # 8-byte Spill
movl $1, %eax
movq %rax, 48(%rsp) # 8-byte Spill
movl $-1, %eax
movq %rax, (%rsp) # 8-byte Spill
movl $0, 40(%rsp) # 4-byte Folded Spill
movl $-1, %r12d
movl $-1, %eax
movq %rax, 16(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 144(%rsp) # 8-byte Spill
.LBB3_2: # %._crit_edge
movq 16(%rsp), %r14 # 8-byte Reload
testl %r14d, %r14d
js .LBB3_3
# %bb.26:
testl %r12d, %r12d
movq (%rsp), %rdx # 8-byte Reload
js .LBB3_27
# %bb.28:
testl %edx, %edx
movq %r12, 136(%rsp) # 8-byte Spill
js .LBB3_31
# %bb.29:
movl %r12d, %eax
imull %edx, %eax
cmpl %r14d, %eax
je .LBB3_33
# %bb.30:
movl $_ZSt4cout, %edi
movl $.L.str.18, %esi
movl $42, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB3_31:
movl %r14d, %eax
xorl %edx, %edx
divl %r12d
# kill: def $eax killed $eax def $rax
movq %rax, %rcx
movq %rax, (%rsp) # 8-byte Spill
movl %eax, %r14d
jmp .LBB3_32
.LBB3_3:
movq (%rsp), %r14 # 8-byte Reload
testl %r14d, %r14d
movl $1, %eax
cmovsl %eax, %r14d
testl %r12d, %r12d
cmovsl %eax, %r12d
movq %r14, (%rsp) # 8-byte Spill
# kill: def $r14d killed $r14d killed $r14 def $r14
movq %r12, 136(%rsp) # 8-byte Spill
.LBB3_32:
imull %r12d, %r14d
jmp .LBB3_33
.LBB3_27:
testl %edx, %edx
movl $32, %ecx
cmovnsl %edx, %ecx
movl %r14d, %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movq %rax, 136(%rsp) # 8-byte Spill
movl %eax, %r14d
imull %ecx, %r14d
movl %ecx, %eax
movq %rax, (%rsp) # 8-byte Spill
.LBB3_33:
movabsq $4294967296, %rbx # imm = 0x100000000
movq %r14, 16(%rsp) # 8-byte Spill
movslq %r14d, %rax
leaq (,%rax,4), %r14
testl %eax, %eax
movq $-1, %r15
movq %r14, %r13
cmovsq %r15, %r13
leaq (,%rax,8), %r12
cmovnsq %r12, %r15
movq %r13, %rdi
callq _Znam
movq %rax, 152(%rsp) # 8-byte Spill
movq %r13, %rdi
callq _Znam
movq %rax, %rbp
movq %r15, %rdi
callq _Znam
movq %rax, %r15
movl 8(%rsp), %eax # 4-byte Reload
movq %rax, 304(%rsp) # 8-byte Spill
leaq (,%rax,8), %r13
leaq 168(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 208(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 216(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 160(%rsp), %rdi
movq %r12, 320(%rsp) # 8-byte Spill
movq %r12, %rsi
callq hipMalloc
leaq 1(%rbx), %rdi
leaq 32(%rbx), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_35
# %bb.34:
movq 168(%rsp), %rax
movq %rax, 128(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 72(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 224(%rsp)
leaq 72(%rsp), %rax
movq %rax, 232(%rsp)
leaq 64(%rsp), %rax
movq %rax, 240(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z12setup_globalPPijj, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_35:
callq hipDeviceSynchronize
callq clock
movq %rax, 312(%rsp) # 8-byte Spill
movq 136(%rsp), %r12 # 8-byte Reload
movl %r12d, %edi
orq %rbx, %rdi
movl (%rsp), %edx # 4-byte Reload
orq %rbx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, 36(%rsp) # 1-byte Folded Reload
movq %r13, 200(%rsp) # 8-byte Spill
jne .LBB3_38
# %bb.36:
testl %eax, %eax
jne .LBB3_41
# %bb.37:
movq 168(%rsp), %rax
movq 216(%rsp), %rcx
movq 208(%rsp), %rdx
movq 160(%rsp), %rsi
movl $3, 44(%rsp)
movq 24(%rsp), %rdi # 8-byte Reload
movl %edi, 196(%rsp)
movq 8(%rsp), %rdi # 8-byte Reload
movl %edi, 192(%rsp)
movq %rax, 128(%rsp)
movq 144(%rsp), %rax # 8-byte Reload
movl %eax, 188(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 80(%rsp)
movq %rsi, 72(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 184(%rsp)
leaq 44(%rsp), %rax
movq %rax, 224(%rsp)
leaq 196(%rsp), %rax
movq %rax, 232(%rsp)
leaq 192(%rsp), %rax
movq %rax, 240(%rsp)
leaq 128(%rsp), %rax
movq %rax, 248(%rsp)
leaq 188(%rsp), %rax
movq %rax, 256(%rsp)
leaq 120(%rsp), %rax
movq %rax, 264(%rsp)
leaq 80(%rsp), %rax
movq %rax, 272(%rsp)
leaq 72(%rsp), %rax
movq %rax, 280(%rsp)
leaq 184(%rsp), %rax
movq %rax, 288(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z12global_readsiijPPijPjS1_S0_j, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
jmp .LBB3_40
.LBB3_38:
.cfi_def_cfa_offset 384
testl %eax, %eax
jne .LBB3_41
# %bb.39:
movq 168(%rsp), %rax
movq 160(%rsp), %rcx
movq 24(%rsp), %rdx # 8-byte Reload
movl %edx, 64(%rsp)
movq 8(%rsp), %rdx # 8-byte Reload
movl %edx, 176(%rsp)
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 44(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 176(%rsp), %rax
movq %rax, 232(%rsp)
leaq 128(%rsp), %rax
movq %rax, 240(%rsp)
leaq 120(%rsp), %rax
movq %rax, 248(%rsp)
leaq 44(%rsp), %rax
movq %rax, 256(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 224(%rsp), %r9
movl $_Z16global_reads_optijPPiS0_j, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
.LBB3_40:
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_41:
callq hipDeviceSynchronize
callq clock
movq %rax, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB3_105
# %bb.42:
movq 208(%rsp), %rsi
movq 152(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 216(%rsp), %rsi
movq %rbp, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 160(%rsp), %rsi
movq %r15, %rdi
movq 320(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rax # 8-byte Reload
testl %eax, %eax
jle .LBB3_43
# %bb.47: # %.lr.ph330.preheader
movl %eax, %eax
movl $-1, %r13d
xorl %ecx, %ecx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_48: # %.lr.ph330
# =>This Inner Loop Header: Depth=1
movl (%rbp,%rcx,4), %edx
cmpl %r13d, %edx
cmovbl %edx, %r13d
cmpl %r14d, %edx
cmoval %edx, %r14d
incq %rcx
cmpq %rcx, %rax
jne .LBB3_48
jmp .LBB3_44
.LBB3_43:
xorl %r14d, %r14d
movl $-1, %r13d
.LBB3_44: # %._crit_edge331
subq 312(%rsp), %rbx # 8-byte Folded Reload
testb $1, 40(%rsp) # 1-byte Folded Reload
jne .LBB3_99
# %bb.45:
movq %rbx, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r12d, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_51
# %bb.50:
movzbl 67(%rbx), %ecx
jmp .LBB3_52
.LBB3_99:
movl $_ZSt4cout, %edi
movq 24(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rbx, %r15
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq 16(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl %r12d, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq (%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq 200(%rsp), %rsi # 8-byte Reload
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 48(%rsp), %esi # 4-byte Reload
shlq $3, %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 56(%rsp), %esi # 4-byte Reload
shlq $3, %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r15d, %esi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r13d, %esi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.38, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r14d, %esi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.100: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i287
cmpb $0, 56(%rbx)
je .LBB3_102
# %bb.101:
movzbl 67(%rbx), %ecx
jmp .LBB3_103
.LBB3_51:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.22, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq (%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i232
cmpb $0, 56(%rbx)
je .LBB3_55
# %bb.54:
movzbl 67(%rbx), %ecx
jmp .LBB3_56
.LBB3_102:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_103: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit290
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
jmp .LBB3_104
.LBB3_55:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_56: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit235
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.23, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq 16(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.57: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i237
cmpb $0, 56(%rbx)
je .LBB3_59
# %bb.58:
movzbl 67(%rbx), %ecx
jmp .LBB3_60
.LBB3_59:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_60: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit240
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.24, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 48(%rsp), %esi # 4-byte Reload
shlq $3, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.61: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i242
cmpb $0, 56(%rbx)
je .LBB3_63
# %bb.62:
movzbl 67(%rbx), %ecx
jmp .LBB3_64
.LBB3_63:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_64: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit245
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.25, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 56(%rsp), %esi # 4-byte Reload
shlq $3, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.65: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i247
cmpb $0, 56(%rbx)
je .LBB3_67
# %bb.66:
movzbl 67(%rbx), %ecx
jmp .LBB3_68
.LBB3_67:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_68: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit250
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.26, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq 24(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.69: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i252
cmpb $0, 56(%rbx)
je .LBB3_71
# %bb.70:
movzbl 67(%rbx), %ecx
jmp .LBB3_72
.LBB3_71:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_72: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit255
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.27, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq 304(%rsp), %rsi # 8-byte Reload
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.73: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i257
cmpb $0, 56(%rbx)
je .LBB3_75
# %bb.74:
movzbl 67(%rbx), %ecx
jmp .LBB3_76
.LBB3_75:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_76: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit260
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.28, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq 200(%rsp), %rsi # 8-byte Reload
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.77: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i262
cmpb $0, 56(%rbx)
je .LBB3_79
# %bb.78:
movzbl 67(%rbx), %ecx
jmp .LBB3_80
.LBB3_79:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_80: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit265
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.29, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi # 4-byte Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i267
cmpb $0, 56(%rbx)
je .LBB3_83
# %bb.82:
movzbl 67(%rbx), %ecx
jmp .LBB3_84
.LBB3_83:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_84: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit270
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.30, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r13d, %esi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.85: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i272
cmpb $0, 56(%rbx)
movq 152(%rsp), %r13 # 8-byte Reload
je .LBB3_87
# %bb.86:
movzbl 67(%rbx), %ecx
jmp .LBB3_88
.LBB3_87:
movq %rbx, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB3_88: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit275
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.31, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r14d, %esi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_46
# %bb.89: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i277
cmpb $0, 56(%rbx)
movq 16(%rsp), %r14 # 8-byte Reload
je .LBB3_91
# %bb.90:
movzbl 67(%rbx), %ecx
jmp .LBB3_92
.LBB3_91:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
movq 16(%rsp), %r14 # 8-byte Reload
.LBB3_92: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit280
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.32, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %r14d, %r14d
jle .LBB3_104
# %bb.93: # %.lr.ph335
cvtsi2sdl 24(%rsp), %xmm0 # 4-byte Folded Reload
mulsd .LCPI3_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %r14d, %r12d
xorl %ebx, %ebx
jmp .LBB3_94
.p2align 4, 0x90
.LBB3_96: # in Loop: Header=BB3_94 Depth=1
movzbl 67(%r14), %ecx
.LBB3_98: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit285
# in Loop: Header=BB3_94 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
cmpq %rbx, %r12
je .LBB3_104
.LBB3_94: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.33, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.34, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r13,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str.35, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbp,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r14
movl $.L.str.36, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbp,%rbx,4), %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI3_1(%rip), %xmm0
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movq %r14, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r14
movl $.L.str.37, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15,%rbx,8), %rsi
movq %r14, %rdi
callq _ZNSo9_M_insertIPKvEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB3_46
# %bb.95: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i282
# in Loop: Header=BB3_94 Depth=1
cmpb $0, 56(%r14)
jne .LBB3_96
# %bb.97: # in Loop: Header=BB3_94 Depth=1
movq %r14, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
movq 152(%rsp), %r13 # 8-byte Reload
jmp .LBB3_98
.LBB3_104: # %.loopexit
xorl %eax, %eax
addq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_46:
.cfi_def_cfa_offset 384
callq _ZSt16__throw_bad_castv
.LBB3_105:
movl %eax, %r13d
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %r13d, %esi
callq _ZNSolsEi
movl $.L.str.20, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
movl %r13d, %edi
callq hipGetErrorString
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $-1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12setup_globalPPijj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16global_reads_optijPPiS0_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12global_readsiijPPijPjS1_S0_j, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12setup_globalPPijj,@object # @_Z12setup_globalPPijj
.section .rodata,"a",@progbits
.globl _Z12setup_globalPPijj
.p2align 3, 0x0
_Z12setup_globalPPijj:
.quad _Z27__device_stub__setup_globalPPijj
.size _Z12setup_globalPPijj, 8
.type _Z16global_reads_optijPPiS0_j,@object # @_Z16global_reads_optijPPiS0_j
.globl _Z16global_reads_optijPPiS0_j
.p2align 3, 0x0
_Z16global_reads_optijPPiS0_j:
.quad _Z31__device_stub__global_reads_optijPPiS0_j
.size _Z16global_reads_optijPPiS0_j, 8
.type _Z12global_readsiijPPijPjS1_S0_j,@object # @_Z12global_readsiijPPijPjS1_S0_j
.globl _Z12global_readsiijPPijPjS1_S0_j
.p2align 3, 0x0
_Z12global_readsiijPPijPjS1_S0_j:
.quad _Z27__device_stub__global_readsiijPPijPjS1_S0_j
.size _Z12global_readsiijPPijPjS1_S0_j, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "-b"
.size .L.str, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "-e"
.size .L.str.2, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "-i"
.size .L.str.4, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "-n"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "-o"
.size .L.str.7, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "-p"
.size .L.str.9, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "-r"
.size .L.str.11, 3
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "-s"
.size .L.str.12, 3
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "-t"
.size .L.str.14, 3
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "-w"
.size .L.str.16, 3
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "WARNING: Your math is wrong, fixing it up\n"
.size .L.str.18, 43
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "ERROR: Kernel execution failed with code: "
.size .L.str.19, 43
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz ", message: "
.size .L.str.20, 12
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "Number of blocks = "
.size .L.str.21, 20
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Threads per block = "
.size .L.str.22, 21
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Number of threads = "
.size .L.str.23, 21
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "Stride within warp (B) = "
.size .L.str.24, 26
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "Stride between loads (B) = "
.size .L.str.25, 28
.type .L.str.26,@object # @.str.26
.L.str.26:
.asciz "Number of iterations = "
.size .L.str.26, 24
.type .L.str.27,@object # @.str.27
.L.str.27:
.asciz "Number of array elements = "
.size .L.str.27, 28
.type .L.str.28,@object # @.str.28
.L.str.28:
.asciz "Array size (B) = "
.size .L.str.28, 18
.type .L.str.29,@object # @.str.29
.L.str.29:
.asciz "Total kernel time = "
.size .L.str.29, 21
.type .L.str.30,@object # @.str.30
.L.str.30:
.asciz "Min kernel time = "
.size .L.str.30, 19
.type .L.str.31,@object # @.str.31
.L.str.31:
.asciz "Max kernel time = "
.size .L.str.31, 19
.type .L.str.32,@object # @.str.32
.L.str.32:
.asciz "Per thread timings:\n"
.size .L.str.32, 21
.type .L.str.33,@object # @.str.33
.L.str.33:
.asciz " "
.size .L.str.33, 3
.type .L.str.34,@object # @.str.34
.L.str.34:
.asciz ": start = "
.size .L.str.34, 11
.type .L.str.35,@object # @.str.35
.L.str.35:
.asciz ", total = "
.size .L.str.35, 11
.type .L.str.36,@object # @.str.36
.L.str.36:
.asciz ", per = "
.size .L.str.36, 9
.type .L.str.37,@object # @.str.37
.L.str.37:
.asciz ", ptr = "
.size .L.str.37, 9
.type .L.str.38,@object # @.str.38
.L.str.38:
.asciz ", "
.size .L.str.38, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12setup_globalPPijj"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16global_reads_optijPPiS0_j"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12global_readsiijPPijPjS1_S0_j"
.size .L__unnamed_3, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__setup_globalPPijj
.addrsig_sym _Z31__device_stub__global_reads_optijPPiS0_j
.addrsig_sym _Z27__device_stub__global_readsiijPPijPjS1_S0_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12setup_globalPPijj
.addrsig_sym _Z16global_reads_optijPPiS0_j
.addrsig_sym _Z12global_readsiijPPijPjS1_S0_j
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Babak Poursartip
// 10/01/2020
// profile/profiling with nvprof
/*
nvprof modes:
1- summary mode
2- GPU and API trace mode
3- event metrics summary mode
4- event, metrics trace mode
- To run nvprof, first create the executable (nvcc file.cu -o file.out). Then,
profile using: nvprof ./file.out (This would be the summary mode)
metrics:
- sm_efficiency
- achieved_occupancy
- branch_efficiency
- gld_efficiency
- gld_throughput
- dram_read_throughput
-inst_per_warp
- stall_sync
- To run with metrics: nvprof --metrics
gld_efficiency,sm_efficiency,achieved_occupancy ./file.out
*/
#include <cstdio>
#include <iostream>
// =================================
// cuda error check macro
#define gpuErrchk(ans) \
{ gpuAssert(ans, __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s. File: %s, line: %d. \n",
cudaGetErrorString(code), file, line);
if (abort) {
// printf(" Exists from the gpuErrorCheck func.\n");
exit(code);
}
}
}
// ==============================================
void compare_arrays(const float *a, const float *b, const int size) {
for (int i = 0; i < size; ++i) {
if (a[i] != b[i]) {
printf("\n Arrays are not equal!! %d %f %f \n", i, a[i], b[i]);
return;
}
}
printf("\n Arrays are identical!! \n");
}
// ==============================================
void sum_array_cpu(float *a, float *b, float *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// ==============================================
// 1D grid, and 1D block. Thus, nx = size
__global__ void sum_array_1Dgrid_1Dblock(float *a, float *b, float *c, int nx) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
c[gid] = a[gid] + b[gid];
// printf("inside %d \n", gid);
}
// ==============================================
// 2D grid, and 2D block. Thus, nx*ny = size.
__global__ void sum_arrays_2Dgrid_2Dblock(float *a, float *b, float *c, int nx,
int ny) {
int gidx = blockDim.x * blockIdx.x + threadIdx.x;
int gidy = blockDim.y * blockIdx.y + threadIdx.y;
int gid = gidy * nx + gidx;
if (gidx < nx && gidy < ny)
c[gid] = a[gid] + b[gid];
}
// ==============================================
void run_sum_array_1d(int argc, char **argv) {
printf(" Running 1D grid ");
int size = 1 << 22; // the default size of the array.
int block_size = 128;
// int nx, ny = 0;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 4)
block_size = 1 << atoi(argv[4]);
const int byte_size = size * sizeof(float);
printf(" size of the array: %d, %d \n", size, byte_size);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_size);
dim3 grid((size + block.x - 1) / block.x);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(cudaMalloc((void **)&d_a, byte_size));
gpuErrchk(cudaMalloc((void **)&d_b, byte_size));
gpuErrchk(cudaMalloc((void **)&d_c, byte_size));
gpuErrchk(cudaMemset(d_c, 0, byte_size));
gpuErrchk(cudaMemcpy(d_a, h_a, byte_size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_b, h_b, byte_size, cudaMemcpyHostToDevice));
sum_array_1Dgrid_1Dblock<<<grid, block>>>(d_a, d_b, d_c, size);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(h_ref, d_c, byte_size, cudaMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
void run_sum_array_2d(int argc, char **argv) {
printf(" Running 2D grid ");
int size = 1 << 22; // the default size of the array = 4194304
int block_x = 128;
int nx = 1 << 14; // 16384
int ny = size / nx;
int block_y = 8;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 3) {
nx = 1 << atoi(argv[3]);
ny = size / nx;
}
if (argc > 4) {
int pow = atoi(argv[4]);
if (pow < 3 || pow > 10) {
printf("Block size is invalid, default block size used (%d,%d)\n",
block_x, block_y);
} else {
block_x = 1 << pow;
block_y = 1024 / block_x;
}
}
unsigned int byte_size = size * sizeof(float);
printf("Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n",
size, nx, ny, block_x, block_y);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_x, block_y);
dim3 grid((nx + block_x - 1) / block_x, (ny + block_y - 1) / block_y);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(cudaMalloc((void **)&d_a, byte_size));
gpuErrchk(cudaMalloc((void **)&d_b, byte_size));
gpuErrchk(cudaMalloc((void **)&d_c, byte_size));
gpuErrchk(cudaMemset(d_c, 0, byte_size));
gpuErrchk(cudaMemcpy(d_a, h_a, byte_size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_b, h_b, byte_size, cudaMemcpyHostToDevice));
sum_arrays_2Dgrid_2Dblock<<<grid, block>>>(d_a, d_b, d_c, nx, ny);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(h_ref, d_c, byte_size, cudaMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
////arguments :
////1 - kernel (0:1D or 1:2D),
////2 - input size (2 pow (x))
////3 - for 2D kernel nx,
////4 - block.x
////5 - block.y
// ==============================================
int main(int argc, char **argv) {
printf("Sum array code for nvprof: \n");
if (argc > 1) {
if (atoi(argv[1]) > 0)
run_sum_array_2d(argc, argv);
else
run_sum_array_1d(argc, argv);
} else
run_sum_array_1d(argc, argv);
// query_device();
return 0;
} | code for sm_80
Function : _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24sum_array_1Dgrid_1DblockPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Babak Poursartip
// 10/01/2020
// profile/profiling with nvprof
/*
nvprof modes:
1- summary mode
2- GPU and API trace mode
3- event metrics summary mode
4- event, metrics trace mode
- To run nvprof, first create the executable (nvcc file.cu -o file.out). Then,
profile using: nvprof ./file.out (This would be the summary mode)
metrics:
- sm_efficiency
- achieved_occupancy
- branch_efficiency
- gld_efficiency
- gld_throughput
- dram_read_throughput
-inst_per_warp
- stall_sync
- To run with metrics: nvprof --metrics
gld_efficiency,sm_efficiency,achieved_occupancy ./file.out
*/
#include <cstdio>
#include <iostream>
// =================================
// cuda error check macro
#define gpuErrchk(ans) \
{ gpuAssert(ans, __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s. File: %s, line: %d. \n",
cudaGetErrorString(code), file, line);
if (abort) {
// printf(" Exists from the gpuErrorCheck func.\n");
exit(code);
}
}
}
// ==============================================
void compare_arrays(const float *a, const float *b, const int size) {
for (int i = 0; i < size; ++i) {
if (a[i] != b[i]) {
printf("\n Arrays are not equal!! %d %f %f \n", i, a[i], b[i]);
return;
}
}
printf("\n Arrays are identical!! \n");
}
// ==============================================
void sum_array_cpu(float *a, float *b, float *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// ==============================================
// 1D grid, and 1D block. Thus, nx = size
__global__ void sum_array_1Dgrid_1Dblock(float *a, float *b, float *c, int nx) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
c[gid] = a[gid] + b[gid];
// printf("inside %d \n", gid);
}
// ==============================================
// 2D grid, and 2D block. Thus, nx*ny = size.
__global__ void sum_arrays_2Dgrid_2Dblock(float *a, float *b, float *c, int nx,
int ny) {
int gidx = blockDim.x * blockIdx.x + threadIdx.x;
int gidy = blockDim.y * blockIdx.y + threadIdx.y;
int gid = gidy * nx + gidx;
if (gidx < nx && gidy < ny)
c[gid] = a[gid] + b[gid];
}
// ==============================================
void run_sum_array_1d(int argc, char **argv) {
printf(" Running 1D grid ");
int size = 1 << 22; // the default size of the array.
int block_size = 128;
// int nx, ny = 0;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 4)
block_size = 1 << atoi(argv[4]);
const int byte_size = size * sizeof(float);
printf(" size of the array: %d, %d \n", size, byte_size);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_size);
dim3 grid((size + block.x - 1) / block.x);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(cudaMalloc((void **)&d_a, byte_size));
gpuErrchk(cudaMalloc((void **)&d_b, byte_size));
gpuErrchk(cudaMalloc((void **)&d_c, byte_size));
gpuErrchk(cudaMemset(d_c, 0, byte_size));
gpuErrchk(cudaMemcpy(d_a, h_a, byte_size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_b, h_b, byte_size, cudaMemcpyHostToDevice));
sum_array_1Dgrid_1Dblock<<<grid, block>>>(d_a, d_b, d_c, size);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(h_ref, d_c, byte_size, cudaMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
void run_sum_array_2d(int argc, char **argv) {
printf(" Running 2D grid ");
int size = 1 << 22; // the default size of the array = 4194304
int block_x = 128;
int nx = 1 << 14; // 16384
int ny = size / nx;
int block_y = 8;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 3) {
nx = 1 << atoi(argv[3]);
ny = size / nx;
}
if (argc > 4) {
int pow = atoi(argv[4]);
if (pow < 3 || pow > 10) {
printf("Block size is invalid, default block size used (%d,%d)\n",
block_x, block_y);
} else {
block_x = 1 << pow;
block_y = 1024 / block_x;
}
}
unsigned int byte_size = size * sizeof(float);
printf("Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n",
size, nx, ny, block_x, block_y);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_x, block_y);
dim3 grid((nx + block_x - 1) / block_x, (ny + block_y - 1) / block_y);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(cudaMalloc((void **)&d_a, byte_size));
gpuErrchk(cudaMalloc((void **)&d_b, byte_size));
gpuErrchk(cudaMalloc((void **)&d_c, byte_size));
gpuErrchk(cudaMemset(d_c, 0, byte_size));
gpuErrchk(cudaMemcpy(d_a, h_a, byte_size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_b, h_b, byte_size, cudaMemcpyHostToDevice));
sum_arrays_2Dgrid_2Dblock<<<grid, block>>>(d_a, d_b, d_c, nx, ny);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(h_ref, d_c, byte_size, cudaMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
////arguments :
////1 - kernel (0:1D or 1:2D),
////2 - input size (2 pow (x))
////3 - for 2D kernel nx,
////4 - block.x
////5 - block.y
// ==============================================
int main(int argc, char **argv) {
printf("Sum array code for nvprof: \n");
if (argc > 1) {
if (atoi(argv[1]) > 0)
run_sum_array_2d(argc, argv);
else
run_sum_array_1d(argc, argv);
} else
run_sum_array_1d(argc, argv);
// query_device();
return 0;
} | .file "tmpxft_0007fa7c_00000000-6_5_sum_array_profiling.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3677:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n Arrays are not equal!! %d %f %f \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\n Arrays are identical!! \n"
.text
.globl _Z14compare_arraysPKfS0_i
.type _Z14compare_arraysPKfS0_i, @function
_Z14compare_arraysPKfS0_i:
.LFB3670:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .L4
movslq %edx, %rax
movl $0, %edx
.L8:
movss (%rdi,%rdx,4), %xmm0
movss (%rsi,%rdx,4), %xmm1
ucomiss %xmm1, %xmm0
jp .L9
jne .L9
addq $1, %rdx
cmpq %rax, %rdx
jne .L8
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L3:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L3
.cfi_endproc
.LFE3670:
.size _Z14compare_arraysPKfS0_i, .-_Z14compare_arraysPKfS0_i
.globl _Z13sum_array_cpuPfS_S_i
.type _Z13sum_array_cpuPfS_S_i, @function
_Z13sum_array_cpuPfS_S_i:
.LFB3671:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L12
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L14:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L14
.L12:
ret
.cfi_endproc
.LFE3671:
.size _Z13sum_array_cpuPfS_S_i, .-_Z13sum_array_cpuPfS_S_i
.globl _Z49__device_stub__Z24sum_array_1Dgrid_1DblockPfS_S_iPfS_S_i
.type _Z49__device_stub__Z24sum_array_1Dgrid_1DblockPfS_S_iPfS_S_i, @function
_Z49__device_stub__Z24sum_array_1Dgrid_1DblockPfS_S_iPfS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24sum_array_1Dgrid_1DblockPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z49__device_stub__Z24sum_array_1Dgrid_1DblockPfS_S_iPfS_S_i, .-_Z49__device_stub__Z24sum_array_1Dgrid_1DblockPfS_S_iPfS_S_i
.globl _Z24sum_array_1Dgrid_1DblockPfS_S_i
.type _Z24sum_array_1Dgrid_1DblockPfS_S_i, @function
_Z24sum_array_1Dgrid_1DblockPfS_S_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z24sum_array_1Dgrid_1DblockPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z24sum_array_1Dgrid_1DblockPfS_S_i, .-_Z24sum_array_1Dgrid_1DblockPfS_S_i
.section .rodata.str1.1
.LC2:
.string " Running 1D grid "
.LC3:
.string " size of the array: %d, %d \n"
.section .rodata.str1.8
.align 8
.LC4:
.string " host memory allocation error\n"
.align 8
.LC5:
.string " launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n"
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/babakpst/Learning/master/HPC/01_Cuda_delete/03_udemy_GPU/2_CUDA_execution_model/5_sum_array_profiling.cu"
.align 8
.LC7:
.string "GPUassert: %s. File: %s, line: %d. \n"
.text
.globl _Z16run_sum_array_1diPPc
.type _Z16run_sum_array_1diPPc, @function
_Z16run_sum_array_1diPPc:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
cmpl $2, %ebx
jg .L47
movl $16777216, %ecx
movl $4194304, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbx
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $16777216, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $16777216, %edi
call malloc@PLT
movq %rax, 24(%rsp)
testq %rbx, %rbx
je .L43
movl $4194304, %r14d
movl $128, %r15d
movl $16777216, %r12d
movl $4194304, %r13d
.L40:
movl $0, %edx
.L29:
movslq %edx, %rax
imulq $1717986919, %rax, %rcx
sarq $34, %rcx
movl %edx, %esi
sarl $31, %esi
subl %esi, %ecx
leal (%rcx,%rcx,4), %ecx
addl %ecx, %ecx
movl %edx, %edi
subl %ecx, %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
movss %xmm0, (%rbx,%rdx,4)
imulq $-1840700269, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $2, %eax
subl %esi, %eax
leal 0(,%rax,8), %ecx
subl %eax, %ecx
movl %edx, %eax
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq %r13, %rdx
jne .L29
.L28:
movl %r14d, %ecx
movq 8(%rsp), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13sum_array_cpuPfS_S_i
movl %r15d, 20(%rsp)
leal -1(%r15,%r14), %eax
movl $0, %edx
divl %r15d
movl %eax, %r13d
pushq $1
.cfi_def_cfa_offset 168
pushq $1
.cfi_def_cfa_offset 176
movl %r15d, %r9d
movl $1, %r8d
movl $1, %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L48
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L49
leaq 56(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L50
movq %r12, %rdx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L51
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L52
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L53
movl %r13d, 76(%rsp)
movl $1, 80(%rsp)
movl 20(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L36:
call cudaDeviceSynchronize@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L55
movl $2, %ecx
movq %r12, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L56
movl %r14d, %edx
movq 24(%rsp), %r15
movq %r15, %rsi
movq 8(%rsp), %r14
movq %r14, %rdi
call _Z14compare_arraysPKfS0_i
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %r14d
movl %eax, %ecx
sall %cl, %r14d
movl $128, %r15d
cmpl $4, %ebx
jg .L58
.L26:
movslq %r14d, %r13
leal 0(,%r14,4), %r12d
movl %r12d, %ecx
movl %r14d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
testq %rbx, %rbx
je .L39
.L27:
testl %r14d, %r14d
jg .L40
jmp .L28
.L58:
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %r15d
movl %eax, %ecx
sall %cl, %r15d
jmp .L26
.L43:
movl $4194304, %r14d
movl $128, %r15d
movl $16777216, %r12d
movl $4194304, %r13d
.L39:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L27
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $135, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $136, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $137, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $139, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $141, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $142, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r15d, %edi
call exit@PLT
.L54:
movl %r14d, %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z49__device_stub__Z24sum_array_1Dgrid_1DblockPfS_S_iPfS_S_i
jmp .L36
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $145, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r13d, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $147, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _Z16run_sum_array_1diPPc, .-_Z16run_sum_array_1diPPc
.globl _Z51__device_stub__Z25sum_arrays_2Dgrid_2DblockPfS_S_iiPfS_S_ii
.type _Z51__device_stub__Z25sum_arrays_2Dgrid_2DblockPfS_S_iiPfS_S_ii, @function
_Z51__device_stub__Z25sum_arrays_2Dgrid_2DblockPfS_S_iiPfS_S_ii:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z51__device_stub__Z25sum_arrays_2Dgrid_2DblockPfS_S_iiPfS_S_ii, .-_Z51__device_stub__Z25sum_arrays_2Dgrid_2DblockPfS_S_iiPfS_S_ii
.globl _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.type _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, @function
_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25sum_arrays_2Dgrid_2DblockPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, .-_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.section .rodata.str1.1
.LC8:
.string " Running 2D grid "
.section .rodata.str1.8
.align 8
.LC9:
.string "Block size is invalid, default block size used (%d,%d)\n"
.align 8
.LC10:
.string "Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n"
.text
.globl _Z16run_sum_array_2diPPc
.type _Z16run_sum_array_2diPPc, @function
_Z16run_sum_array_2diPPc:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC8(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4194304, %r14d
cmpl $2, %ebx
jg .L89
.L68:
movl $256, 12(%rsp)
movl $16384, 8(%rsp)
movl $8, %r15d
movl $128, 24(%rsp)
.L69:
movslq %r14d, %r12
subq $8, %rsp
.cfi_def_cfa_offset 184
pushq %r15
.cfi_def_cfa_offset 192
movl 40(%rsp), %r9d
movl 28(%rsp), %r8d
movl 24(%rsp), %ecx
movl %r14d, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal 0(,%r14,4), %r13d
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, 48(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 176
testq %rbx, %rbx
je .L90
.L71:
testl %r14d, %r14d
jle .L72
movl $0, %edx
.L73:
movslq %edx, %rax
imulq $1717986919, %rax, %rcx
sarq $34, %rcx
movl %edx, %esi
sarl $31, %esi
subl %esi, %ecx
leal (%rcx,%rcx,4), %ecx
addl %ecx, %ecx
movl %edx, %edi
subl %ecx, %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
movss %xmm0, (%rbx,%rdx,4)
imulq $-1840700269, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $2, %eax
subl %esi, %eax
leal 0(,%rax,8), %ecx
subl %eax, %ecx
movl %edx, %eax
subl %ecx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rdx,4)
addq $1, %rdx
cmpq %r12, %rdx
jne .L73
.L72:
movl %r14d, %ecx
movq 16(%rsp), %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13sum_array_cpuPfS_S_i
movl %r15d, 28(%rsp)
movl 24(%rsp), %esi
movl %esi, 40(%rsp)
movl 12(%rsp), %eax
leal -1(%r15,%rax), %eax
cltd
idivl %r15d
movl %eax, 24(%rsp)
movl 8(%rsp), %edx
leal -1(%rsi,%rdx), %eax
cltd
idivl %esi
movl %eax, 44(%rsp)
pushq $1
.cfi_def_cfa_offset 184
pushq %r15
.cfi_def_cfa_offset 192
movl %esi, %r9d
movl $1, %r8d
movl 40(%rsp), %ecx
movl %eax, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
leaq 56(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L91
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L92
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L93
movq %r13, %rdx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L94
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L95
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L96
movl 44(%rsp), %eax
movl %eax, 92(%rsp)
movl 24(%rsp), %eax
movl %eax, 96(%rsp)
movl 40(%rsp), %eax
movl %eax, 80(%rsp)
movl 28(%rsp), %eax
movl %eax, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movl $1, %ecx
movq 92(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L97
.L80:
call cudaDeviceSynchronize@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L98
movl $2, %ecx
movq %r13, %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L99
movl %r14d, %edx
movq 32(%rsp), %r14
movq %r14, %rsi
movq 16(%rsp), %r15
movq %r15, %rdi
call _Z14compare_arraysPKfS0_i
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L100
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %edx
movl %eax, %ecx
sall %cl, %edx
movl %edx, %r14d
cmpl $3, %ebx
jle .L68
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %edx
movl %eax, %ecx
sall %cl, %edx
movl %edx, %edi
movl %edx, 8(%rsp)
movl %r14d, %eax
cltd
idivl %edi
movl %eax, 12(%rsp)
cmpl $4, %ebx
jle .L85
movq 32(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rcx
leal -3(%rax), %eax
cmpl $7, %eax
ja .L101
movl $1, %eax
sall %cl, %eax
movl %eax, 24(%rsp)
movl $1024, %r15d
sarl %cl, %r15d
jmp .L69
.L101:
movl $8, %ecx
movl $128, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %r15d
movl $128, 24(%rsp)
jmp .L69
.L85:
movl $8, %r15d
movl $128, 24(%rsp)
jmp .L69
.L90:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L71
.L91:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $218, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L92:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $219, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L93:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $220, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L94:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $222, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L95:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $224, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L96:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $225, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L97:
movl 12(%rsp), %r8d
movl 8(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z51__device_stub__Z25sum_arrays_2Dgrid_2DblockPfS_S_iiPfS_S_ii
jmp .L80
.L98:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $229, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L99:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $231, %r9d
leaq .LC6(%rip), %r8
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L100:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size _Z16run_sum_array_2diPPc, .-_Z16run_sum_array_2diPPc
.section .rodata.str1.1
.LC11:
.string "Sum array code for nvprof: \n"
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $1, %ebx
jle .L103
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L104
movq %rbp, %rsi
movl %ebx, %edi
call _Z16run_sum_array_2diPPc
jmp .L105
.L104:
movq %rbp, %rsi
movl %ebx, %edi
call _Z16run_sum_array_1diPPc
jmp .L105
.L103:
movq %rbp, %rsi
movl %ebx, %edi
call _Z16run_sum_array_1diPPc
.L105:
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC12:
.string "_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii"
.align 8
.LC13:
.string "_Z24sum_array_1Dgrid_1DblockPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z24sum_array_1Dgrid_1DblockPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Babak Poursartip
// 10/01/2020
// profile/profiling with nvprof
/*
nvprof modes:
1- summary mode
2- GPU and API trace mode
3- event metrics summary mode
4- event, metrics trace mode
- To run nvprof, first create the executable (nvcc file.cu -o file.out). Then,
profile using: nvprof ./file.out (This would be the summary mode)
metrics:
- sm_efficiency
- achieved_occupancy
- branch_efficiency
- gld_efficiency
- gld_throughput
- dram_read_throughput
-inst_per_warp
- stall_sync
- To run with metrics: nvprof --metrics
gld_efficiency,sm_efficiency,achieved_occupancy ./file.out
*/
#include <cstdio>
#include <iostream>
// =================================
// cuda error check macro
#define gpuErrchk(ans) \
{ gpuAssert(ans, __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line,
bool abort = true) {
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s. File: %s, line: %d. \n",
cudaGetErrorString(code), file, line);
if (abort) {
// printf(" Exists from the gpuErrorCheck func.\n");
exit(code);
}
}
}
// ==============================================
void compare_arrays(const float *a, const float *b, const int size) {
for (int i = 0; i < size; ++i) {
if (a[i] != b[i]) {
printf("\n Arrays are not equal!! %d %f %f \n", i, a[i], b[i]);
return;
}
}
printf("\n Arrays are identical!! \n");
}
// ==============================================
void sum_array_cpu(float *a, float *b, float *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// ==============================================
// 1D grid, and 1D block. Thus, nx = size
__global__ void sum_array_1Dgrid_1Dblock(float *a, float *b, float *c, int nx) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
c[gid] = a[gid] + b[gid];
// printf("inside %d \n", gid);
}
// ==============================================
// 2D grid, and 2D block. Thus, nx*ny = size.
__global__ void sum_arrays_2Dgrid_2Dblock(float *a, float *b, float *c, int nx,
int ny) {
int gidx = blockDim.x * blockIdx.x + threadIdx.x;
int gidy = blockDim.y * blockIdx.y + threadIdx.y;
int gid = gidy * nx + gidx;
if (gidx < nx && gidy < ny)
c[gid] = a[gid] + b[gid];
}
// ==============================================
void run_sum_array_1d(int argc, char **argv) {
printf(" Running 1D grid ");
int size = 1 << 22; // the default size of the array.
int block_size = 128;
// int nx, ny = 0;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 4)
block_size = 1 << atoi(argv[4]);
const int byte_size = size * sizeof(float);
printf(" size of the array: %d, %d \n", size, byte_size);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_size);
dim3 grid((size + block.x - 1) / block.x);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(cudaMalloc((void **)&d_a, byte_size));
gpuErrchk(cudaMalloc((void **)&d_b, byte_size));
gpuErrchk(cudaMalloc((void **)&d_c, byte_size));
gpuErrchk(cudaMemset(d_c, 0, byte_size));
gpuErrchk(cudaMemcpy(d_a, h_a, byte_size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_b, h_b, byte_size, cudaMemcpyHostToDevice));
sum_array_1Dgrid_1Dblock<<<grid, block>>>(d_a, d_b, d_c, size);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(h_ref, d_c, byte_size, cudaMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
void run_sum_array_2d(int argc, char **argv) {
printf(" Running 2D grid ");
int size = 1 << 22; // the default size of the array = 4194304
int block_x = 128;
int nx = 1 << 14; // 16384
int ny = size / nx;
int block_y = 8;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 3) {
nx = 1 << atoi(argv[3]);
ny = size / nx;
}
if (argc > 4) {
int pow = atoi(argv[4]);
if (pow < 3 || pow > 10) {
printf("Block size is invalid, default block size used (%d,%d)\n",
block_x, block_y);
} else {
block_x = 1 << pow;
block_y = 1024 / block_x;
}
}
unsigned int byte_size = size * sizeof(float);
printf("Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n",
size, nx, ny, block_x, block_y);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_x, block_y);
dim3 grid((nx + block_x - 1) / block_x, (ny + block_y - 1) / block_y);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(cudaMalloc((void **)&d_a, byte_size));
gpuErrchk(cudaMalloc((void **)&d_b, byte_size));
gpuErrchk(cudaMalloc((void **)&d_c, byte_size));
gpuErrchk(cudaMemset(d_c, 0, byte_size));
gpuErrchk(cudaMemcpy(d_a, h_a, byte_size, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(d_b, h_b, byte_size, cudaMemcpyHostToDevice));
sum_arrays_2Dgrid_2Dblock<<<grid, block>>>(d_a, d_b, d_c, nx, ny);
gpuErrchk(cudaDeviceSynchronize());
gpuErrchk(cudaMemcpy(h_ref, d_c, byte_size, cudaMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
////arguments :
////1 - kernel (0:1D or 1:2D),
////2 - input size (2 pow (x))
////3 - for 2D kernel nx,
////4 - block.x
////5 - block.y
// ==============================================
int main(int argc, char **argv) {
printf("Sum array code for nvprof: \n");
if (argc > 1) {
if (atoi(argv[1]) > 0)
run_sum_array_2d(argc, argv);
else
run_sum_array_1d(argc, argv);
} else
run_sum_array_1d(argc, argv);
// query_device();
return 0;
} | // Babak Poursartip
// 10/01/2020
// profile/profiling with nvprof
/*
nvprof modes:
1- summary mode
2- GPU and API trace mode
3- event metrics summary mode
4- event, metrics trace mode
- To run nvprof, first create the executable (nvcc file.cu -o file.out). Then,
profile using: nvprof ./file.out (This would be the summary mode)
metrics:
- sm_efficiency
- achieved_occupancy
- branch_efficiency
- gld_efficiency
- gld_throughput
- dram_read_throughput
-inst_per_warp
- stall_sync
- To run with metrics: nvprof --metrics
gld_efficiency,sm_efficiency,achieved_occupancy ./file.out
*/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <iostream>
// =================================
// cuda error check macro
#define gpuErrchk(ans) \
{ gpuAssert(ans, __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s. File: %s, line: %d. \n",
hipGetErrorString(code), file, line);
if (abort) {
// printf(" Exists from the gpuErrorCheck func.\n");
exit(code);
}
}
}
// ==============================================
void compare_arrays(const float *a, const float *b, const int size) {
for (int i = 0; i < size; ++i) {
if (a[i] != b[i]) {
printf("\n Arrays are not equal!! %d %f %f \n", i, a[i], b[i]);
return;
}
}
printf("\n Arrays are identical!! \n");
}
// ==============================================
void sum_array_cpu(float *a, float *b, float *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// ==============================================
// 1D grid, and 1D block. Thus, nx = size
__global__ void sum_array_1Dgrid_1Dblock(float *a, float *b, float *c, int nx) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
c[gid] = a[gid] + b[gid];
// printf("inside %d \n", gid);
}
// ==============================================
// 2D grid, and 2D block. Thus, nx*ny = size.
__global__ void sum_arrays_2Dgrid_2Dblock(float *a, float *b, float *c, int nx,
int ny) {
int gidx = blockDim.x * blockIdx.x + threadIdx.x;
int gidy = blockDim.y * blockIdx.y + threadIdx.y;
int gid = gidy * nx + gidx;
if (gidx < nx && gidy < ny)
c[gid] = a[gid] + b[gid];
}
// ==============================================
void run_sum_array_1d(int argc, char **argv) {
printf(" Running 1D grid ");
int size = 1 << 22; // the default size of the array.
int block_size = 128;
// int nx, ny = 0;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 4)
block_size = 1 << atoi(argv[4]);
const int byte_size = size * sizeof(float);
printf(" size of the array: %d, %d \n", size, byte_size);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_size);
dim3 grid((size + block.x - 1) / block.x);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(hipMalloc((void **)&d_a, byte_size));
gpuErrchk(hipMalloc((void **)&d_b, byte_size));
gpuErrchk(hipMalloc((void **)&d_c, byte_size));
gpuErrchk(hipMemset(d_c, 0, byte_size));
gpuErrchk(hipMemcpy(d_a, h_a, byte_size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_b, h_b, byte_size, hipMemcpyHostToDevice));
sum_array_1Dgrid_1Dblock<<<grid, block>>>(d_a, d_b, d_c, size);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(h_ref, d_c, byte_size, hipMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
void run_sum_array_2d(int argc, char **argv) {
printf(" Running 2D grid ");
int size = 1 << 22; // the default size of the array = 4194304
int block_x = 128;
int nx = 1 << 14; // 16384
int ny = size / nx;
int block_y = 8;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 3) {
nx = 1 << atoi(argv[3]);
ny = size / nx;
}
if (argc > 4) {
int pow = atoi(argv[4]);
if (pow < 3 || pow > 10) {
printf("Block size is invalid, default block size used (%d,%d)\n",
block_x, block_y);
} else {
block_x = 1 << pow;
block_y = 1024 / block_x;
}
}
unsigned int byte_size = size * sizeof(float);
printf("Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n",
size, nx, ny, block_x, block_y);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_x, block_y);
dim3 grid((nx + block_x - 1) / block_x, (ny + block_y - 1) / block_y);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(hipMalloc((void **)&d_a, byte_size));
gpuErrchk(hipMalloc((void **)&d_b, byte_size));
gpuErrchk(hipMalloc((void **)&d_c, byte_size));
gpuErrchk(hipMemset(d_c, 0, byte_size));
gpuErrchk(hipMemcpy(d_a, h_a, byte_size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_b, h_b, byte_size, hipMemcpyHostToDevice));
sum_arrays_2Dgrid_2Dblock<<<grid, block>>>(d_a, d_b, d_c, nx, ny);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(h_ref, d_c, byte_size, hipMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
////arguments :
////1 - kernel (0:1D or 1:2D),
////2 - input size (2 pow (x))
////3 - for 2D kernel nx,
////4 - block.x
////5 - block.y
// ==============================================
int main(int argc, char **argv) {
printf("Sum array code for nvprof: \n");
if (argc > 1) {
if (atoi(argv[1]) > 0)
run_sum_array_2d(argc, argv);
else
run_sum_array_1d(argc, argv);
} else
run_sum_array_1d(argc, argv);
// query_device();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Babak Poursartip
// 10/01/2020
// profile/profiling with nvprof
/*
nvprof modes:
1- summary mode
2- GPU and API trace mode
3- event metrics summary mode
4- event, metrics trace mode
- To run nvprof, first create the executable (nvcc file.cu -o file.out). Then,
profile using: nvprof ./file.out (This would be the summary mode)
metrics:
- sm_efficiency
- achieved_occupancy
- branch_efficiency
- gld_efficiency
- gld_throughput
- dram_read_throughput
-inst_per_warp
- stall_sync
- To run with metrics: nvprof --metrics
gld_efficiency,sm_efficiency,achieved_occupancy ./file.out
*/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <iostream>
// =================================
// cuda error check macro
#define gpuErrchk(ans) \
{ gpuAssert(ans, __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s. File: %s, line: %d. \n",
hipGetErrorString(code), file, line);
if (abort) {
// printf(" Exists from the gpuErrorCheck func.\n");
exit(code);
}
}
}
// ==============================================
void compare_arrays(const float *a, const float *b, const int size) {
for (int i = 0; i < size; ++i) {
if (a[i] != b[i]) {
printf("\n Arrays are not equal!! %d %f %f \n", i, a[i], b[i]);
return;
}
}
printf("\n Arrays are identical!! \n");
}
// ==============================================
void sum_array_cpu(float *a, float *b, float *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// ==============================================
// 1D grid, and 1D block. Thus, nx = size
__global__ void sum_array_1Dgrid_1Dblock(float *a, float *b, float *c, int nx) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
c[gid] = a[gid] + b[gid];
// printf("inside %d \n", gid);
}
// ==============================================
// 2D grid, and 2D block. Thus, nx*ny = size.
__global__ void sum_arrays_2Dgrid_2Dblock(float *a, float *b, float *c, int nx,
int ny) {
int gidx = blockDim.x * blockIdx.x + threadIdx.x;
int gidy = blockDim.y * blockIdx.y + threadIdx.y;
int gid = gidy * nx + gidx;
if (gidx < nx && gidy < ny)
c[gid] = a[gid] + b[gid];
}
// ==============================================
void run_sum_array_1d(int argc, char **argv) {
printf(" Running 1D grid ");
int size = 1 << 22; // the default size of the array.
int block_size = 128;
// int nx, ny = 0;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 4)
block_size = 1 << atoi(argv[4]);
const int byte_size = size * sizeof(float);
printf(" size of the array: %d, %d \n", size, byte_size);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_size);
dim3 grid((size + block.x - 1) / block.x);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(hipMalloc((void **)&d_a, byte_size));
gpuErrchk(hipMalloc((void **)&d_b, byte_size));
gpuErrchk(hipMalloc((void **)&d_c, byte_size));
gpuErrchk(hipMemset(d_c, 0, byte_size));
gpuErrchk(hipMemcpy(d_a, h_a, byte_size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_b, h_b, byte_size, hipMemcpyHostToDevice));
sum_array_1Dgrid_1Dblock<<<grid, block>>>(d_a, d_b, d_c, size);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(h_ref, d_c, byte_size, hipMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
void run_sum_array_2d(int argc, char **argv) {
printf(" Running 2D grid ");
int size = 1 << 22; // the default size of the array = 4194304
int block_x = 128;
int nx = 1 << 14; // 16384
int ny = size / nx;
int block_y = 8;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 3) {
nx = 1 << atoi(argv[3]);
ny = size / nx;
}
if (argc > 4) {
int pow = atoi(argv[4]);
if (pow < 3 || pow > 10) {
printf("Block size is invalid, default block size used (%d,%d)\n",
block_x, block_y);
} else {
block_x = 1 << pow;
block_y = 1024 / block_x;
}
}
unsigned int byte_size = size * sizeof(float);
printf("Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n",
size, nx, ny, block_x, block_y);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_x, block_y);
dim3 grid((nx + block_x - 1) / block_x, (ny + block_y - 1) / block_y);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(hipMalloc((void **)&d_a, byte_size));
gpuErrchk(hipMalloc((void **)&d_b, byte_size));
gpuErrchk(hipMalloc((void **)&d_c, byte_size));
gpuErrchk(hipMemset(d_c, 0, byte_size));
gpuErrchk(hipMemcpy(d_a, h_a, byte_size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_b, h_b, byte_size, hipMemcpyHostToDevice));
sum_arrays_2Dgrid_2Dblock<<<grid, block>>>(d_a, d_b, d_c, nx, ny);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(h_ref, d_c, byte_size, hipMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
////arguments :
////1 - kernel (0:1D or 1:2D),
////2 - input size (2 pow (x))
////3 - for 2D kernel nx,
////4 - block.x
////5 - block.y
// ==============================================
int main(int argc, char **argv) {
printf("Sum array code for nvprof: \n");
if (argc > 1) {
if (atoi(argv[1]) > 0)
run_sum_array_2d(argc, argv);
else
run_sum_array_1d(argc, argv);
} else
run_sum_array_1d(argc, argv);
// query_device();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24sum_array_1Dgrid_1DblockPfS_S_i
.globl _Z24sum_array_1Dgrid_1DblockPfS_S_i
.p2align 8
.type _Z24sum_array_1Dgrid_1DblockPfS_S_i,@function
_Z24sum_array_1Dgrid_1DblockPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24sum_array_1Dgrid_1DblockPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24sum_array_1Dgrid_1DblockPfS_S_i, .Lfunc_end0-_Z24sum_array_1Dgrid_1DblockPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.globl _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.p2align 8
.type _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii,@function
_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, .Lfunc_end1-_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24sum_array_1Dgrid_1DblockPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24sum_array_1Dgrid_1DblockPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Babak Poursartip
// 10/01/2020
// profile/profiling with nvprof
/*
nvprof modes:
1- summary mode
2- GPU and API trace mode
3- event metrics summary mode
4- event, metrics trace mode
- To run nvprof, first create the executable (nvcc file.cu -o file.out). Then,
profile using: nvprof ./file.out (This would be the summary mode)
metrics:
- sm_efficiency
- achieved_occupancy
- branch_efficiency
- gld_efficiency
- gld_throughput
- dram_read_throughput
-inst_per_warp
- stall_sync
- To run with metrics: nvprof --metrics
gld_efficiency,sm_efficiency,achieved_occupancy ./file.out
*/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <iostream>
// =================================
// cuda error check macro
#define gpuErrchk(ans) \
{ gpuAssert(ans, __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true) {
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s. File: %s, line: %d. \n",
hipGetErrorString(code), file, line);
if (abort) {
// printf(" Exists from the gpuErrorCheck func.\n");
exit(code);
}
}
}
// ==============================================
void compare_arrays(const float *a, const float *b, const int size) {
for (int i = 0; i < size; ++i) {
if (a[i] != b[i]) {
printf("\n Arrays are not equal!! %d %f %f \n", i, a[i], b[i]);
return;
}
}
printf("\n Arrays are identical!! \n");
}
// ==============================================
void sum_array_cpu(float *a, float *b, float *c, const int size) {
for (int i = 0; i < size; ++i) {
c[i] = a[i] + b[i];
}
}
// ==============================================
// 1D grid, and 1D block. Thus, nx = size
__global__ void sum_array_1Dgrid_1Dblock(float *a, float *b, float *c, int nx) {
int gid = blockDim.x * blockIdx.x + threadIdx.x;
c[gid] = a[gid] + b[gid];
// printf("inside %d \n", gid);
}
// ==============================================
// 2D grid, and 2D block. Thus, nx*ny = size.
__global__ void sum_arrays_2Dgrid_2Dblock(float *a, float *b, float *c, int nx,
int ny) {
int gidx = blockDim.x * blockIdx.x + threadIdx.x;
int gidy = blockDim.y * blockIdx.y + threadIdx.y;
int gid = gidy * nx + gidx;
if (gidx < nx && gidy < ny)
c[gid] = a[gid] + b[gid];
}
// ==============================================
void run_sum_array_1d(int argc, char **argv) {
printf(" Running 1D grid ");
int size = 1 << 22; // the default size of the array.
int block_size = 128;
// int nx, ny = 0;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 4)
block_size = 1 << atoi(argv[4]);
const int byte_size = size * sizeof(float);
printf(" size of the array: %d, %d \n", size, byte_size);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_size);
dim3 grid((size + block.x - 1) / block.x);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(hipMalloc((void **)&d_a, byte_size));
gpuErrchk(hipMalloc((void **)&d_b, byte_size));
gpuErrchk(hipMalloc((void **)&d_c, byte_size));
gpuErrchk(hipMemset(d_c, 0, byte_size));
gpuErrchk(hipMemcpy(d_a, h_a, byte_size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_b, h_b, byte_size, hipMemcpyHostToDevice));
sum_array_1Dgrid_1Dblock<<<grid, block>>>(d_a, d_b, d_c, size);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(h_ref, d_c, byte_size, hipMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
void run_sum_array_2d(int argc, char **argv) {
printf(" Running 2D grid ");
int size = 1 << 22; // the default size of the array = 4194304
int block_x = 128;
int nx = 1 << 14; // 16384
int ny = size / nx;
int block_y = 8;
if (argc > 2)
size = 1 << atoi(argv[2]);
if (argc > 3) {
nx = 1 << atoi(argv[3]);
ny = size / nx;
}
if (argc > 4) {
int pow = atoi(argv[4]);
if (pow < 3 || pow > 10) {
printf("Block size is invalid, default block size used (%d,%d)\n",
block_x, block_y);
} else {
block_x = 1 << pow;
block_y = 1024 / block_x;
}
}
unsigned int byte_size = size * sizeof(float);
printf("Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n",
size, nx, ny, block_x, block_y);
float *h_a, *h_b, *h_out, *h_ref;
h_a = (float *)malloc(byte_size);
h_b = (float *)malloc(byte_size);
h_out = (float *)malloc(byte_size);
h_ref = (float *)malloc(byte_size);
if (!h_a)
printf(" host memory allocation error\n");
for (int i = 0; i < size; ++i) {
h_a[i] = i % 10;
h_b[i] = i % 7;
}
sum_array_cpu(h_a, h_b, h_out, size);
dim3 block(block_x, block_y);
dim3 grid((nx + block_x - 1) / block_x, (ny + block_y - 1) / block_y);
printf(" launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n", grid.x,
grid.y, grid.z, block.x, block.y, block.z);
float *d_a, *d_b, *d_c;
gpuErrchk(hipMalloc((void **)&d_a, byte_size));
gpuErrchk(hipMalloc((void **)&d_b, byte_size));
gpuErrchk(hipMalloc((void **)&d_c, byte_size));
gpuErrchk(hipMemset(d_c, 0, byte_size));
gpuErrchk(hipMemcpy(d_a, h_a, byte_size, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(d_b, h_b, byte_size, hipMemcpyHostToDevice));
sum_arrays_2Dgrid_2Dblock<<<grid, block>>>(d_a, d_b, d_c, nx, ny);
gpuErrchk(hipDeviceSynchronize());
gpuErrchk(hipMemcpy(h_ref, d_c, byte_size, hipMemcpyDeviceToHost));
compare_arrays(h_out, h_ref, size);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
free(h_ref);
free(h_out);
free(h_b);
free(h_a);
}
// ==============================================
////arguments :
////1 - kernel (0:1D or 1:2D),
////2 - input size (2 pow (x))
////3 - for 2D kernel nx,
////4 - block.x
////5 - block.y
// ==============================================
int main(int argc, char **argv) {
printf("Sum array code for nvprof: \n");
if (argc > 1) {
if (atoi(argv[1]) > 0)
run_sum_array_2d(argc, argv);
else
run_sum_array_1d(argc, argv);
} else
run_sum_array_1d(argc, argv);
// query_device();
return 0;
} | .text
.file "5_sum_array_profiling.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14compare_arraysPKfS0_i # -- Begin function _Z14compare_arraysPKfS0_i
.p2align 4, 0x90
.type _Z14compare_arraysPKfS0_i,@function
_Z14compare_arraysPKfS0_i: # @_Z14compare_arraysPKfS0_i
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
testl %edx, %edx
setg %bl
jle .LBB0_8
# %bb.1: # %.lr.ph.preheader
movq %rsi, %rax
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %esi, %esi
ucomiss %xmm1, %xmm0
jne .LBB0_6
jp .LBB0_6
# %bb.2: # %.lr.ph32.preheader
movl %edx, %ecx
leaq -1(%rcx), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_3: # %.lr.ph32
# =>This Inner Loop Header: Depth=1
cmpq %rsi, %rdx
je .LBB0_8
# %bb.4: # %.lr.ph
# in Loop: Header=BB0_3 Depth=1
movss 4(%rdi,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rax,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
incq %rsi
ucomiss %xmm1, %xmm0
jne .LBB0_5
jnp .LBB0_3
.LBB0_5: # %.lr.ph._crit_edge
cmpq %rcx, %rsi
setb %bl
.LBB0_6:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $2, %al
callq printf
testb %bl, %bl
je .LBB0_8
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_8: # %.critedge
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z14compare_arraysPKfS0_i, .Lfunc_end0-_Z14compare_arraysPKfS0_i
.cfi_endproc
# -- End function
.globl _Z13sum_array_cpuPfS_S_i # -- Begin function _Z13sum_array_cpuPfS_S_i
.p2align 4, 0x90
.type _Z13sum_array_cpuPfS_S_i,@function
_Z13sum_array_cpuPfS_S_i: # @_Z13sum_array_cpuPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13sum_array_cpuPfS_S_i, .Lfunc_end1-_Z13sum_array_cpuPfS_S_i
.cfi_endproc
# -- End function
.globl _Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i # -- Begin function _Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i
.p2align 4, 0x90
.type _Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i,@function
_Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i: # @_Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24sum_array_1Dgrid_1DblockPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i, .Lfunc_end2-_Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i
.cfi_endproc
# -- End function
.globl _Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii # -- Begin function _Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii
.p2align 4, 0x90
.type _Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii,@function
_Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii: # @_Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii, .Lfunc_end3-_Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z16run_sum_array_1diPPc # -- Begin function _Z16run_sum_array_1diPPc
.p2align 4, 0x90
.type _Z16run_sum_array_1diPPc,@function
_Z16run_sum_array_1diPPc: # @_Z16run_sum_array_1diPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $4194304, %r13d # imm = 0x400000
cmpl $3, %ebp
jl .LBB4_2
# %bb.1:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $1, %r13d
movl %eax, %ecx
shll %cl, %r13d
.LBB4_2:
movl $128, %eax
movq %rax, 16(%rsp) # 8-byte Spill
cmpl $5, %ebp
jl .LBB4_4
# %bb.3:
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $1, %edx
movl %eax, %ecx
shll %cl, %edx
movq %rdx, 16(%rsp) # 8-byte Spill
.LBB4_4:
leal (,%r13,4), %ebx
movl $.L.str.3, %edi
movl %r13d, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
movslq %ebx, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, 56(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
testq %rbx, %rbx
jne .LBB4_6
# %bb.5:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB4_6:
movl %r13d, %ebp
testl %r13d, %r13d
jle .LBB4_9
# %bb.7: # %.lr.ph.preheader
leaq (,%rbp,4), %rax
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
xorl %esi, %esi
.p2align 4, 0x90
.LBB4_8: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %esi, %edi
imulq $613566757, %rdi, %r8 # imm = 0x24924925
imulq %rdx, %rdi
shrq $35, %rdi
addl %edi, %edi
leal (%rdi,%rdi,4), %edi
movl %esi, %r9d
subl %edi, %r9d
shrq $32, %r8
movl %esi, %edi
subl %r8d, %edi
shrl %edi
addl %r8d, %edi
shrl $2, %edi
leal (,%rdi,8), %r8d
subl %r8d, %edi
addl %esi, %edi
xorps %xmm0, %xmm0
cvtsi2ss %r9d, %xmm0
movss %xmm0, (%rbx,%rcx)
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%r14,%rcx)
incl %esi
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB4_8
.LBB4_9: # %._crit_edge
movq %r12, 64(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB4_12
# %bb.10: # %.lr.ph.preheader.i
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_11: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq %rax, %rbp
jne .LBB4_11
.LBB4_12: # %_Z13sum_array_cpuPfS_S_i.exit
movq %r13, 48(%rsp) # 8-byte Spill
movq 16(%rsp), %r8 # 8-byte Reload
leal (%r8,%r13), %eax
decl %eax
xorl %edx, %edx
divl %r8d
movl %eax, %r12d
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.5, %edi
movl %eax, %esi
movl $1, %edx
movl $1, %ecx
# kill: def $r8d killed $r8d killed $r8
movl $1, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
leaq 32(%rsp), %rdi
movq 56(%rsp), %r13 # 8-byte Reload
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_13
# %bb.15: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_16
# %bb.17: # %_Z9gpuAssert10hipError_tPKcib.exit54
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_18
# %bb.19: # %_Z9gpuAssert10hipError_tPKcib.exit56
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r13, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB4_20
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit58
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit60
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit62
movl 16(%rsp), %edx # 4-byte Reload
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdx
orq %rax, %r12
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 64(%rsp), %r13 # 8-byte Reload
jne .LBB4_27
# %bb.26:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z24sum_array_1Dgrid_1DblockPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_27:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_28
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit64
movq 8(%rsp), %rsi
movq %r13, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit66
cmpl $0, 48(%rsp) # 4-byte Folded Reload
jle .LBB4_37
# %bb.32: # %.lr.ph.preheader.i67
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r13), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_38
jnp .LBB4_33
.LBB4_38: # %_Z14compare_arraysPKfS0_i.exit.critedge
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
xorl %esi, %esi
movb $2, %al
callq printf
jmp .LBB4_39
.LBB4_33: # %.lr.ph88.preheader
leaq -1(%rbp), %rax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_34: # %.lr.ph88
# =>This Inner Loop Header: Depth=1
cmpq %r12, %rax
je .LBB4_37
# %bb.35: # %.lr.ph.i69
# in Loop: Header=BB4_34 Depth=1
movss 4(%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%r13,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
incq %r12
ucomiss %xmm1, %xmm0
jne .LBB4_36
jnp .LBB4_34
.LBB4_36: # %.lr.ph.i69._crit_edge
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %r12d, %esi
movb $2, %al
callq printf
cmpq %rbp, %r12
jb .LBB4_39
.LBB4_37: # %.critedge.i
movl $.Lstr, %edi
callq puts@PLT
.LBB4_39: # %_Z14compare_arraysPKfS0_i.exit
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %r13, %rdi
callq free
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_13:
.cfi_def_cfa_offset 240
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $137, %r8d
jmp .LBB4_14
.LBB4_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $138, %r8d
jmp .LBB4_14
.LBB4_18:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $139, %r8d
jmp .LBB4_14
.LBB4_20:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $141, %r8d
jmp .LBB4_14
.LBB4_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $143, %r8d
jmp .LBB4_14
.LBB4_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $144, %r8d
jmp .LBB4_14
.LBB4_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $147, %r8d
jmp .LBB4_14
.LBB4_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $149, %r8d
.LBB4_14:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end4:
.size _Z16run_sum_array_1diPPc, .Lfunc_end4-_Z16run_sum_array_1diPPc
.cfi_endproc
# -- End function
.globl _Z16run_sum_array_2diPPc # -- Begin function _Z16run_sum_array_2diPPc
.p2align 4, 0x90
.type _Z16run_sum_array_2diPPc,@function
_Z16run_sum_array_2diPPc: # @_Z16run_sum_array_2diPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl $4194304, %r13d # imm = 0x400000
cmpl $3, %ebp
jl .LBB5_2
# %bb.1:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $1, %r13d
movl %eax, %ecx
shll %cl, %r13d
.LBB5_2:
cmpl $4, %ebp
jl .LBB5_3
# %bb.4:
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl $1, %esi
movl %eax, %ecx
shll %cl, %esi
movl %r13d, %eax
cltd
movq %rsi, 8(%rsp) # 8-byte Spill
idivl %esi
# kill: def $eax killed $eax def $rax
jmp .LBB5_5
.LBB5_3:
movl $16384, %eax # imm = 0x4000
movq %rax, 8(%rsp) # 8-byte Spill
movl $256, %eax # imm = 0x100
.LBB5_5:
movq %rax, 16(%rsp) # 8-byte Spill
cmpl $5, %ebp
jl .LBB5_6
# %bb.7:
movq 32(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leal -11(%rax), %ecx
cmpl $-9, %ecx
movq 8(%rsp), %rbp # 8-byte Reload
ja .LBB5_9
# %bb.8:
movl $128, %r15d
movl $8, %r14d
movl $.L.str.8, %edi
movl $128, %esi
movl $8, %edx
xorl %eax, %eax
callq printf
jmp .LBB5_10
.LBB5_6:
movl $128, %r15d
movl $8, %r14d
movq 8(%rsp), %rbp # 8-byte Reload
jmp .LBB5_10
.LBB5_9:
movl $1, %r15d
movl %eax, %ecx
shll %cl, %r15d
movl $1024, %r14d # imm = 0x400
shrl %cl, %r14d
.LBB5_10:
leal (,%r13,4), %ebx
movl $.L.str.9, %edi
movl %r13d, %esi
movl %ebp, %edx
movq 16(%rsp), %rcx # 8-byte Reload
# kill: def $ecx killed $ecx killed $rcx
movq %r15, 72(%rsp) # 8-byte Spill
movl %r15d, %r8d
movq %r14, 80(%rsp) # 8-byte Spill
movl %r14d, %r9d
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movq %rbx, 64(%rsp) # 8-byte Spill
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
testq %r14, %r14
jne .LBB5_12
# %bb.11:
movl $.Lstr.2, %edi
callq puts@PLT
.LBB5_12:
movq %r13, %rax
movl %eax, %r13d
movq %rax, 56(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB5_15
# %bb.13: # %.lr.ph.preheader
leaq (,%r13,4), %rax
xorl %ecx, %ecx
movl $3435973837, %edx # imm = 0xCCCCCCCD
xorl %esi, %esi
.p2align 4, 0x90
.LBB5_14: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %esi, %edi
imulq $613566757, %rdi, %r8 # imm = 0x24924925
imulq %rdx, %rdi
shrq $35, %rdi
addl %edi, %edi
leal (%rdi,%rdi,4), %edi
movl %esi, %r9d
subl %edi, %r9d
shrq $32, %r8
movl %esi, %edi
subl %r8d, %edi
shrl %edi
addl %r8d, %edi
shrl $2, %edi
leal (,%rdi,8), %r8d
subl %r8d, %edi
addl %esi, %edi
xorps %xmm0, %xmm0
cvtsi2ss %r9d, %xmm0
movss %xmm0, (%r14,%rcx)
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%r15,%rcx)
incl %esi
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB5_14
.LBB5_15: # %._crit_edge
movq %rbx, 96(%rsp) # 8-byte Spill
cmpl $0, 56(%rsp) # 4-byte Folded Reload
jle .LBB5_18
# %bb.16: # %.lr.ph.preheader.i
xorl %eax, %eax
.p2align 4, 0x90
.LBB5_17: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r15,%rax,4), %xmm0
movss %xmm0, (%r12,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB5_17
.LBB5_18: # %_Z13sum_array_cpuPfS_S_i.exit
movq 72(%rsp), %r8 # 8-byte Reload
leal (%r8,%rbp), %eax
decl %eax
cltd
idivl %r8d
movl %eax, %esi
movq 16(%rsp), %rax # 8-byte Reload
movq 80(%rsp), %r9 # 8-byte Reload
addl %r9d, %eax
decl %eax
cltd
idivl %r9d
movl %eax, %ebx
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.5, %edi
movq %rsi, 96(%rsp) # 8-byte Spill
# kill: def $esi killed $esi killed $rsi
movl %eax, %edx
movl $1, %ecx
# kill: def $r8d killed $r8d killed $r8
# kill: def $r9d killed $r9d killed $r9
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
leaq 40(%rsp), %rdi
movq 64(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_19
# %bb.21: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_22
# %bb.23: # %_Z9gpuAssert10hipError_tPKcib.exit82
leaq 24(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB5_24
# %bb.25: # %_Z9gpuAssert10hipError_tPKcib.exit84
movq 24(%rsp), %rdi
xorl %esi, %esi
movq %rbp, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB5_26
# %bb.27: # %_Z9gpuAssert10hipError_tPKcib.exit86
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_28
# %bb.29: # %_Z9gpuAssert10hipError_tPKcib.exit88
movq 32(%rsp), %rdi
movq %r15, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_30
# %bb.31: # %_Z9gpuAssert10hipError_tPKcib.exit90
movl 72(%rsp), %eax # 4-byte Reload
movq 80(%rsp), %rdx # 8-byte Reload
shlq $32, %rdx
orq %rax, %rdx
shlq $32, %rbx
addq 88(%rsp), %rbx # 8-byte Folded Reload
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 96(%rsp), %rbp # 8-byte Reload
jne .LBB5_33
# %bb.32:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 52(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 48(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 52(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_33:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_34
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit92
movq 24(%rsp), %rsi
movq %rbp, %rdi
movq 64(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_36
# %bb.37: # %_Z9gpuAssert10hipError_tPKcib.exit94
cmpl $0, 56(%rsp) # 4-byte Folded Reload
jle .LBB5_43
# %bb.38: # %.lr.ph.preheader.i95
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB5_44
jnp .LBB5_39
.LBB5_44: # %_Z14compare_arraysPKfS0_i.exit.critedge
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
xorl %esi, %esi
movb $2, %al
callq printf
jmp .LBB5_45
.LBB5_39: # %.lr.ph115.preheader
leaq -1(%r13), %rax
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB5_40: # %.lr.ph115
# =>This Inner Loop Header: Depth=1
cmpq %rbx, %rax
je .LBB5_43
# %bb.41: # %.lr.ph.i97
# in Loop: Header=BB5_40 Depth=1
movss 4(%r12,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 4(%rbp,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
incq %rbx
ucomiss %xmm1, %xmm0
jne .LBB5_42
jnp .LBB5_40
.LBB5_42: # %.lr.ph.i97._crit_edge
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str, %edi
movl %ebx, %esi
movb $2, %al
callq printf
cmpq %r13, %rbx
jb .LBB5_45
.LBB5_43: # %.critedge.i
movl $.Lstr, %edi
callq puts@PLT
.LBB5_45: # %_Z14compare_arraysPKfS0_i.exit
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq free
movq %r12, %rdi
callq free
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_19:
.cfi_def_cfa_offset 272
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $220, %r8d
jmp .LBB5_20
.LBB5_22:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $221, %r8d
jmp .LBB5_20
.LBB5_24:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $222, %r8d
jmp .LBB5_20
.LBB5_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $224, %r8d
jmp .LBB5_20
.LBB5_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $226, %r8d
jmp .LBB5_20
.LBB5_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $227, %r8d
jmp .LBB5_20
.LBB5_34:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $231, %r8d
jmp .LBB5_20
.LBB5_36:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.11, %esi
movl $.L.str.6, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $233, %r8d
.LBB5_20:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end5:
.size _Z16run_sum_array_2diPPc, .Lfunc_end5-_Z16run_sum_array_2diPPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $2, %ebp
jl .LBB6_3
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
jle .LBB6_3
# %bb.2:
movl %ebp, %edi
movq %rbx, %rsi
callq _Z16run_sum_array_2diPPc
jmp .LBB6_4
.LBB6_3:
movl %ebp, %edi
movq %rbx, %rsi
callq _Z16run_sum_array_1diPPc
.LBB6_4:
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24sum_array_1Dgrid_1DblockPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Arrays are not equal!! %d %f %f \n"
.size .L.str, 36
.type _Z24sum_array_1Dgrid_1DblockPfS_S_i,@object # @_Z24sum_array_1Dgrid_1DblockPfS_S_i
.section .rodata,"a",@progbits
.globl _Z24sum_array_1Dgrid_1DblockPfS_S_i
.p2align 3, 0x0
_Z24sum_array_1Dgrid_1DblockPfS_S_i:
.quad _Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i
.size _Z24sum_array_1Dgrid_1DblockPfS_S_i, 8
.type _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii,@object # @_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.globl _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.p2align 3, 0x0
_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii:
.quad _Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii
.size _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " Running 1D grid "
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " size of the array: %d, %d \n"
.size .L.str.3, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " launching the Kernel: grid(%d,%d,%d) - block(%d,%d,%d) \n"
.size .L.str.5, 58
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/babakpst/Learning/master/HPC/01_Cuda_delete/03_udemy_GPU/2_CUDA_execution_model/5_sum_array_profiling.hip"
.size .L.str.6, 163
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Running 2D grid "
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Block size is invalid, default block size used (%d,%d)\n"
.size .L.str.8, 56
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Input size : %d, nx : %d, ny : %d, block_x : %d, block_y : %d \n"
.size .L.str.9, 64
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "GPUassert: %s. File: %s, line: %d. \n"
.size .L.str.11, 37
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24sum_array_1Dgrid_1DblockPfS_S_i"
.size .L__unnamed_1, 36
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii"
.size .L__unnamed_2, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n Arrays are identical!! "
.size .Lstr, 26
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " host memory allocation error"
.size .Lstr.2, 30
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Sum array code for nvprof: "
.size .Lstr.3, 28
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__sum_array_1Dgrid_1DblockPfS_S_i
.addrsig_sym _Z40__device_stub__sum_arrays_2Dgrid_2DblockPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24sum_array_1Dgrid_1DblockPfS_S_i
.addrsig_sym _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z24sum_array_1Dgrid_1DblockPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24sum_array_1Dgrid_1DblockPfS_S_i
.globl _Z24sum_array_1Dgrid_1DblockPfS_S_i
.p2align 8
.type _Z24sum_array_1Dgrid_1DblockPfS_S_i,@function
_Z24sum_array_1Dgrid_1DblockPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24sum_array_1Dgrid_1DblockPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24sum_array_1Dgrid_1DblockPfS_S_i, .Lfunc_end0-_Z24sum_array_1Dgrid_1DblockPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.globl _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.p2align 8
.type _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii,@function
_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_load_b128 s[8:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii, .Lfunc_end1-_Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24sum_array_1Dgrid_1DblockPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24sum_array_1Dgrid_1DblockPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25sum_arrays_2Dgrid_2DblockPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define ROW_NUM 10000100
#define COLUMN_NUM 4
#define CONSTRAINT_MAX 100000
__global__
void request(int *tab, int *result)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < ROW_NUM; i += stride)
{
if(tab[i] > 1000 && tab[i] < CONSTRAINT_MAX
&& tab[i+ROW_NUM] > 1000 && tab[i+ROW_NUM] < CONSTRAINT_MAX
&& tab[i+ROW_NUM*2] > 1000 && tab[i+ROW_NUM*2] < CONSTRAINT_MAX)
{
result[i] = 1;
}
else
{
result[i] = 0;
}
}
}
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main(void)
{
/*int *tab, *result; // GPU
int *tabCPU, *resultCPU; // CPU
tabCPU = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
resultCPU = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&tab, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&result, ROW_NUM*sizeof(int));
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
tabCPU[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(tab, tabCPU, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(result, resultCPU, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(tab, result);
cudaEventRecord(stop);
cudaMemcpy(resultCPU, result, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);*/
/*
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize());
*/
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(result[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;
std::cout << milliseconds;
cudaFree(tab);
cudaFree(result);
free(resultCPU);
free(tabCPU);
return 0;*/
int *x, *y, *d_x, *d_y;
x = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
y = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&d_x, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&d_y, ROW_NUM*sizeof(int));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
x[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(d_x, x, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(resultCPU[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;*/
std::cout << milliseconds;
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
} | code for sm_80
Function : _Z7requestPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x9896e3, PT ; /* 0x009896e30300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x410 ; /* 0x0000038000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00d0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R2, R5, R7, R4 ; /* 0x0000000705027227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x9896e3, RZ ; /* 0x009896e303057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*0160*/ IMAD R5, R0, R6, R5 ; /* 0x0000000600057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0190*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*01f0*/ @!P0 BRA 0x400 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*0220*/ IMAD.WIDE R6, R3, R8, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fe200078e0208 */
/*0240*/ IADD3 R6, P0, R6, 0x2625b90, RZ ; /* 0x02625b9006067810 */
/* 0x000fca0007f1e0ff */
/*0250*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe400000e0607 */
/*0260*/ IADD3 R8, P0, R6, -0x2000000, RZ ; /* 0xfe00000006087810 */
/* 0x000fc80007f1e0ff */
/*0270*/ IADD3.X R9, R7, -0x1, RZ, P0, !PT ; /* 0xffffffff07097810 */
/* 0x000fca00007fe4ff */
/*0280*/ LDG.E R8, [R8.64+-0x625b90] ; /* 0x9da4700408087981 */
/* 0x000ea2000c1e1900 */
/*0290*/ BSSY B1, 0x380 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*02a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02b0*/ IADD3 R11, R8, -0x3e9, RZ ; /* 0xfffffc17080b7810 */
/* 0x004fc80007ffe0ff */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R11, 0x182b6, PT ; /* 0x000182b60b00780c */
/* 0x000fda0003f24070 */
/*02d0*/ @P1 BRA 0x370 ; /* 0x0000009000001947 */
/* 0x000fea0003800000 */
/*02e0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IADD3 R8, R8, -0x3e9, RZ ; /* 0xfffffc1708087810 */
/* 0x004fc80007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P1, PT, R8, 0x182b6, PT ; /* 0x000182b60800780c */
/* 0x000fda0003f24070 */
/*0310*/ @P1 BRA 0x370 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0320*/ IADD3 R8, P0, R6, 0x2000000, RZ ; /* 0x0200000006087810 */
/* 0x000fca0007f1e0ff */
/*0330*/ IMAD.X R9, RZ, RZ, R7, P0 ; /* 0x000000ffff097224 */
/* 0x000fca00000e0607 */
/*0340*/ LDG.E R8, [R8.64+0x625b90] ; /* 0x625b900408087981 */
/* 0x000ea4000c1e1900 */
/*0350*/ IADD3 R11, R8, -0x3e9, RZ ; /* 0xfffffc17080b7810 */
/* 0x004fc80007ffe0ff */
/*0360*/ ISETP.LT.U32.AND P0, PT, R11, 0x182b7, PT ; /* 0x000182b70b00780c */
/* 0x000fd00003f01070 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe200078e0206 */
/*03a0*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fe40004000000 */
/*03b0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*03c0*/ IMAD.IADD R3, R0.reuse, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x040fe400078e0203 */
/*03d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*03e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fd000078e0204 */
/*03f0*/ @P0 BRA 0x260 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0420*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fc800078e00ff */
/*0440*/ IMAD.WIDE R10, R3, R10, c[0x0][0x160] ; /* 0x00005800030a7625 */
/* 0x000fca00078e020a */
/*0450*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea2000c1e1900 */
/*0460*/ LEA R6, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003067a11 */
/* 0x000fe200078210ff */
/*0470*/ BSSY B0, 0x5a0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0490*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*04a0*/ ISETP.GT.U32.AND P2, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fe40003f44070 */
/*04b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fc80000011403 */
/*04c0*/ LEA.HI.X R7, R3, c[0x0][0x16c], R2, 0x2, P1 ; /* 0x00005b0003077a11 */
/* 0x000fe400008f1402 */
/*04d0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f2e170 */
/*04e0*/ @P2 BRA 0x590 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R4, P2, R10, 0x2000000, RZ ; /* 0x020000000a047810 */
/* 0x000fca0007f5e0ff */
/*0500*/ IMAD.X R5, RZ, RZ, R11, P2 ; /* 0x000000ffff057224 */
/* 0x000fca00010e060b */
/*0510*/ LDG.E R4, [R4.64+0x625b90] ; /* 0x625b900404047981 */
/* 0x000ea4000c1e1900 */
/*0520*/ IADD3 R2, R4, -0x3e9, RZ ; /* 0xfffffc1704027810 */
/* 0x004fc80007ffe0ff */
/*0530*/ ISETP.GT.U32.AND P2, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f44070 */
/*0540*/ @!P2 IADD3 R8, P3, R10, 0x5000000, RZ ; /* 0x050000000a08a810 */
/* 0x000fca0007f7e0ff */
/*0550*/ @!P2 IMAD.X R9, RZ, RZ, R11, P3 ; /* 0x000000ffff09a224 */
/* 0x000fca00018e060b */
/*0560*/ @!P2 LDG.E R8, [R8.64+-0x3b48e0] ; /* 0xc4b720040808a981 */
/* 0x000ea4000c1e1900 */
/*0570*/ @!P2 IADD3 R2, R8, -0x3e9, RZ ; /* 0xfffffc170802a810 */
/* 0x004fc80007ffe0ff */
/*0580*/ @!P2 ISETP.LT.U32.AND P1, PT, R2, 0x182b7, PT ; /* 0x000182b70200a80c */
/* 0x000fd00003f21070 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ SEL R9, RZ, 0x1, !P1 ; /* 0x00000001ff097807 */
/* 0x000fe20004800000 */
/*05b0*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*05c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*05d0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ BSSY B0, 0x6e0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*05f0*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0206 */
/*0600*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*0610*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0620*/ @P1 BRA 0x6d0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0630*/ IADD3 R6, P1, R4, 0x2000000, RZ ; /* 0x0200000004067810 */
/* 0x001fca0007f3e0ff */
/*0640*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x000fca00008e0605 */
/*0650*/ LDG.E R6, [R6.64+0x625b90] ; /* 0x625b900406067981 */
/* 0x000ea4000c1e1900 */
/*0660*/ IADD3 R2, R6, -0x3e9, RZ ; /* 0xfffffc1706027810 */
/* 0x004fc80007ffe0ff */
/*0670*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0680*/ @!P1 IADD3 R8, P2, R4, 0x5000000, RZ ; /* 0x0500000004089810 */
/* 0x000fca0007f5e0ff */
/*0690*/ @!P1 IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff099224 */
/* 0x000fca00010e0605 */
/*06a0*/ @!P1 LDG.E R8, [R8.64+-0x3b48e0] ; /* 0xc4b7200408089981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ @!P1 IADD3 R2, R8, -0x3e9, RZ ; /* 0xfffffc1708029810 */
/* 0x004fc80007ffe0ff */
/*06c0*/ @!P1 ISETP.LT.U32.AND P0, PT, R2, 0x182b7, PT ; /* 0x000182b70200980c */
/* 0x000fd00003f01070 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*06e0*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fe20004000000 */
/*06f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x000fc800078e0204 */
/*0700*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0720*/ BSSY B0, 0x830 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0730*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x000fe200078e020a */
/*0740*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0750*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*0760*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0770*/ @P1 BRA 0x820 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R8, P1, R4, 0x2000000, RZ ; /* 0x0200000004087810 */
/* 0x001fca0007f3e0ff */
/*0790*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x000fca00008e0605 */
/*07a0*/ LDG.E R8, [R8.64+0x625b90] ; /* 0x625b900408087981 */
/* 0x000ea4000c1e1900 */
/*07b0*/ IADD3 R2, R8, -0x3e9, RZ ; /* 0xfffffc1708027810 */
/* 0x004fc80007ffe0ff */
/*07c0*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*07d0*/ @!P1 IADD3 R10, P2, R4, 0x5000000, RZ ; /* 0x05000000040a9810 */
/* 0x000fca0007f5e0ff */
/*07e0*/ @!P1 IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b9224 */
/* 0x000fca00010e0605 */
/*07f0*/ @!P1 LDG.E R10, [R10.64+-0x3b48e0] ; /* 0xc4b720040a0a9981 */
/* 0x000ea4000c1e1900 */
/*0800*/ @!P1 IADD3 R2, R10, -0x3e9, RZ ; /* 0xfffffc170a029810 */
/* 0x004fc80007ffe0ff */
/*0810*/ @!P1 ISETP.LT.U32.AND P0, PT, R2, 0x182b7, PT ; /* 0x000182b70200980c */
/* 0x000fd00003f01070 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0830*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fe20004000000 */
/*0840*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc800078e0204 */
/*0850*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0860*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*0870*/ BSSY B0, 0x980 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0890*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*08a0*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*08b0*/ @P1 BRA 0x970 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*08c0*/ IADD3 R4, P1, R8, 0x2000000, RZ ; /* 0x0200000008047810 */
/* 0x001fca0007f3e0ff */
/*08d0*/ IMAD.X R5, RZ, RZ, R9, P1 ; /* 0x000000ffff057224 */
/* 0x000fca00008e0609 */
/*08e0*/ LDG.E R4, [R4.64+0x625b90] ; /* 0x625b900404047981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ IADD3 R2, R4, -0x3e9, RZ ; /* 0xfffffc1704027810 */
/* 0x004fc80007ffe0ff */
/*0900*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0910*/ @P1 BRA 0x970 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0920*/ IADD3 R4, P0, R8, 0x5000000, RZ ; /* 0x0500000008047810 */
/* 0x000fca0007f1e0ff */
/*0930*/ IMAD.X R5, RZ, RZ, R9, P0 ; /* 0x000000ffff057224 */
/* 0x000fca00000e0609 */
/*0940*/ LDG.E R4, [R4.64+-0x3b48e0] ; /* 0xc4b7200404047981 */
/* 0x000ea4000c1e1900 */
/*0950*/ IADD3 R2, R4, -0x3e9, RZ ; /* 0xfffffc1704027810 */
/* 0x004fc80007ffe0ff */
/*0960*/ ISETP.LT.U32.AND P0, PT, R2, 0x182b7, PT ; /* 0x000182b70200780c */
/* 0x000fd00003f01070 */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0980*/ IMAD.WIDE R6, R0.reuse, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x040fe200078e0206 */
/*0990*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fe40004000000 */
/*09a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc60007ffe000 */
/*09b0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001e2000c101904 */
/*09c0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*09d0*/ ISETP.GE.AND P0, PT, R3, 0x9896e4, PT ; /* 0x009896e40300780c */
/* 0x000fda0003f06270 */
/*09e0*/ @!P0 BRA 0x430 ; /* 0xfffffa4000008947 */
/* 0x001fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define ROW_NUM 10000100
#define COLUMN_NUM 4
#define CONSTRAINT_MAX 100000
__global__
void request(int *tab, int *result)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < ROW_NUM; i += stride)
{
if(tab[i] > 1000 && tab[i] < CONSTRAINT_MAX
&& tab[i+ROW_NUM] > 1000 && tab[i+ROW_NUM] < CONSTRAINT_MAX
&& tab[i+ROW_NUM*2] > 1000 && tab[i+ROW_NUM*2] < CONSTRAINT_MAX)
{
result[i] = 1;
}
else
{
result[i] = 0;
}
}
}
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main(void)
{
/*int *tab, *result; // GPU
int *tabCPU, *resultCPU; // CPU
tabCPU = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
resultCPU = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&tab, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&result, ROW_NUM*sizeof(int));
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
tabCPU[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(tab, tabCPU, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(result, resultCPU, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(tab, result);
cudaEventRecord(stop);
cudaMemcpy(resultCPU, result, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);*/
/*
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize());
*/
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(result[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;
std::cout << milliseconds;
cudaFree(tab);
cudaFree(result);
free(resultCPU);
free(tabCPU);
return 0;*/
int *x, *y, *d_x, *d_y;
x = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
y = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&d_x, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&d_y, ROW_NUM*sizeof(int));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
x[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(d_x, x, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(resultCPU[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;*/
std::cout << milliseconds;
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
} | .file "tmpxft_00119f3b_00000000-6_test_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7requestPiS_PiS_
.type _Z28__device_stub__Z7requestPiS_PiS_, @function
_Z28__device_stub__Z7requestPiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7requestPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7requestPiS_PiS_, .-_Z28__device_stub__Z7requestPiS_PiS_
.globl _Z7requestPiS_
.type _Z7requestPiS_, @function
_Z7requestPiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7requestPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7requestPiS_, .-_Z7requestPiS_
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $160001600, %edi
call malloc@PLT
movq %rax, %r14
movl $40000400, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $160001600, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40000400, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %edi
call srand@PLT
leaq 40000400(%r14), %rbp
movl $0, %r12d
.L12:
leaq -40000400(%rbp), %rbx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1125899907, %rdx, %rdx
sarq $50, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addl $10000100, %r12d
addq $40000400, %rbp
cmpl $30000300, %r12d
jne .L12
movl $1, %ecx
movl $160001600, %edx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000400, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $39063, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $40000400, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7requestPiS_PiS_
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z7requestPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7requestPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define ROW_NUM 10000100
#define COLUMN_NUM 4
#define CONSTRAINT_MAX 100000
__global__
void request(int *tab, int *result)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < ROW_NUM; i += stride)
{
if(tab[i] > 1000 && tab[i] < CONSTRAINT_MAX
&& tab[i+ROW_NUM] > 1000 && tab[i+ROW_NUM] < CONSTRAINT_MAX
&& tab[i+ROW_NUM*2] > 1000 && tab[i+ROW_NUM*2] < CONSTRAINT_MAX)
{
result[i] = 1;
}
else
{
result[i] = 0;
}
}
}
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main(void)
{
/*int *tab, *result; // GPU
int *tabCPU, *resultCPU; // CPU
tabCPU = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
resultCPU = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&tab, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&result, ROW_NUM*sizeof(int));
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
tabCPU[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(tab, tabCPU, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(result, resultCPU, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(tab, result);
cudaEventRecord(stop);
cudaMemcpy(resultCPU, result, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);*/
/*
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize());
*/
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(result[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;
std::cout << milliseconds;
cudaFree(tab);
cudaFree(result);
free(resultCPU);
free(tabCPU);
return 0;*/
int *x, *y, *d_x, *d_y;
x = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
y = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&d_x, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&d_y, ROW_NUM*sizeof(int));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
x[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(d_x, x, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(d_x, d_y);
cudaEventRecord(stop);
cudaMemcpy(y, d_y, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(resultCPU[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;*/
std::cout << milliseconds;
cudaFree(d_x);
cudaFree(d_y);
free(x);
free(y);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define ROW_NUM 10000100
#define COLUMN_NUM 4
#define CONSTRAINT_MAX 100000
__global__
void request(int *tab, int *result)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < ROW_NUM; i += stride)
{
if(tab[i] > 1000 && tab[i] < CONSTRAINT_MAX
&& tab[i+ROW_NUM] > 1000 && tab[i+ROW_NUM] < CONSTRAINT_MAX
&& tab[i+ROW_NUM*2] > 1000 && tab[i+ROW_NUM*2] < CONSTRAINT_MAX)
{
result[i] = 1;
}
else
{
result[i] = 0;
}
}
}
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main(void)
{
/*int *tab, *result; // GPU
int *tabCPU, *resultCPU; // CPU
tabCPU = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
resultCPU = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&tab, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&result, ROW_NUM*sizeof(int));
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
tabCPU[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(tab, tabCPU, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(result, resultCPU, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(tab, result);
cudaEventRecord(stop);
cudaMemcpy(resultCPU, result, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);*/
/*
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize());
*/
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(result[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;
std::cout << milliseconds;
cudaFree(tab);
cudaFree(result);
free(resultCPU);
free(tabCPU);
return 0;*/
int *x, *y, *d_x, *d_y;
x = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
y = (int*)malloc(ROW_NUM*sizeof(int));
hipMalloc(&d_x, ROW_NUM*COLUMN_NUM*sizeof(int));
hipMalloc(&d_y, ROW_NUM*sizeof(int));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
x[ROW_NUM*column+row] = rand()%1000000;
}
}
hipMemcpy(d_x, x, ROW_NUM*COLUMN_NUM*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, ROW_NUM*sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, ROW_NUM*sizeof(int), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(resultCPU[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;*/
std::cout << milliseconds;
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define ROW_NUM 10000100
#define COLUMN_NUM 4
#define CONSTRAINT_MAX 100000
__global__
void request(int *tab, int *result)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < ROW_NUM; i += stride)
{
if(tab[i] > 1000 && tab[i] < CONSTRAINT_MAX
&& tab[i+ROW_NUM] > 1000 && tab[i+ROW_NUM] < CONSTRAINT_MAX
&& tab[i+ROW_NUM*2] > 1000 && tab[i+ROW_NUM*2] < CONSTRAINT_MAX)
{
result[i] = 1;
}
else
{
result[i] = 0;
}
}
}
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main(void)
{
/*int *tab, *result; // GPU
int *tabCPU, *resultCPU; // CPU
tabCPU = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
resultCPU = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&tab, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&result, ROW_NUM*sizeof(int));
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
tabCPU[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(tab, tabCPU, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(result, resultCPU, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(tab, result);
cudaEventRecord(stop);
cudaMemcpy(resultCPU, result, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);*/
/*
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize());
*/
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(result[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;
std::cout << milliseconds;
cudaFree(tab);
cudaFree(result);
free(resultCPU);
free(tabCPU);
return 0;*/
int *x, *y, *d_x, *d_y;
x = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
y = (int*)malloc(ROW_NUM*sizeof(int));
hipMalloc(&d_x, ROW_NUM*COLUMN_NUM*sizeof(int));
hipMalloc(&d_y, ROW_NUM*sizeof(int));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
x[ROW_NUM*column+row] = rand()%1000000;
}
}
hipMemcpy(d_x, x, ROW_NUM*COLUMN_NUM*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, ROW_NUM*sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, ROW_NUM*sizeof(int), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(resultCPU[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;*/
std::cout << milliseconds;
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7requestPiS_
.globl _Z7requestPiS_
.p2align 8
.type _Z7requestPiS_,@function
_Z7requestPiS_:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x9896e4, v1
s_cbranch_execz .LBB0_9
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0x9896e3, v1
v_add_co_u32 v2, s0, v2, s8
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_9
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 0xfffffc17, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 0x182b6, v0
v_cmpx_gt_u32_e32 0x182b7, v0
s_cbranch_execz .LBB0_7
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, 0x2625000, v0
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
global_load_b32 v0, v[4:5], off offset:2960
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 0xfffffc17, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e64 s11, 0x182b6, v0
v_cmpx_gt_u32_e32 0x182b7, v0
s_cbranch_execz .LBB0_6
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_and_not1_b32 s11, s11, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, 0x4c4b000, v0
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_mov_b32 s10, 1
global_load_b32 v0, v[4:5], off offset:1824
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 0xfffffc17, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_u32_e32 vcc_lo, 0x182b6, v0
s_and_b32 s13, vcc_lo, exec_lo
s_or_b32 s11, s11, s13
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s11, s11, exec_lo
s_or_b32 s0, s0, s11
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v0, s10
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, 0
s_branch .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7requestPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7requestPiS_, .Lfunc_end0-_Z7requestPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7requestPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7requestPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <math.h>
#define ROW_NUM 10000100
#define COLUMN_NUM 4
#define CONSTRAINT_MAX 100000
__global__
void request(int *tab, int *result)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < ROW_NUM; i += stride)
{
if(tab[i] > 1000 && tab[i] < CONSTRAINT_MAX
&& tab[i+ROW_NUM] > 1000 && tab[i+ROW_NUM] < CONSTRAINT_MAX
&& tab[i+ROW_NUM*2] > 1000 && tab[i+ROW_NUM*2] < CONSTRAINT_MAX)
{
result[i] = 1;
}
else
{
result[i] = 0;
}
}
}
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
int main(void)
{
/*int *tab, *result; // GPU
int *tabCPU, *resultCPU; // CPU
tabCPU = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
resultCPU = (int*)malloc(ROW_NUM*sizeof(int));
cudaMalloc(&tab, ROW_NUM*COLUMN_NUM*sizeof(int));
cudaMalloc(&result, ROW_NUM*sizeof(int));
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
tabCPU[ROW_NUM*column+row] = rand()%1000000;
}
}
cudaMemcpy(tab, tabCPU, ROW_NUM*COLUMN_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(result, resultCPU, ROW_NUM*sizeof(int), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(tab, result);
cudaEventRecord(stop);
cudaMemcpy(resultCPU, result, ROW_NUM*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);*/
/*
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize());
*/
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(result[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;
std::cout << milliseconds;
cudaFree(tab);
cudaFree(result);
free(resultCPU);
free(tabCPU);
return 0;*/
int *x, *y, *d_x, *d_y;
x = (int*)malloc(ROW_NUM*COLUMN_NUM*sizeof(int));
y = (int*)malloc(ROW_NUM*sizeof(int));
hipMalloc(&d_x, ROW_NUM*COLUMN_NUM*sizeof(int));
hipMalloc(&d_y, ROW_NUM*sizeof(int));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
srand(0);
for(int column=0;column<COLUMN_NUM-1;++column)
{
for(int row=0;row<ROW_NUM;++row)
{
x[ROW_NUM*column+row] = rand()%1000000;
}
}
hipMemcpy(d_x, x, ROW_NUM*COLUMN_NUM*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, ROW_NUM*sizeof(int), hipMemcpyHostToDevice);
hipEventRecord(start);
request<<<(ROW_NUM+255)/256, 256>>>(d_x, d_y);
hipEventRecord(stop);
hipMemcpy(y, d_y, ROW_NUM*sizeof(int), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
/*int total = 0;
for(int row=0;row<ROW_NUM;++row)
{
if(resultCPU[row])
{
++total;
}
}
std::cout << "Total : " << total << std::endl;*/
std::cout << milliseconds;
hipFree(d_x);
hipFree(d_y);
free(x);
free(y);
} | .text
.file "test_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__requestPiS_ # -- Begin function _Z22__device_stub__requestPiS_
.p2align 4, 0x90
.type _Z22__device_stub__requestPiS_,@function
_Z22__device_stub__requestPiS_: # @_Z22__device_stub__requestPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7requestPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__requestPiS_, .Lfunc_end0-_Z22__device_stub__requestPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $160001600, %edi # imm = 0x9896E40
callq malloc
movq %rax, %rbx
movl $40000400, %edi # imm = 0x2625B90
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $160001600, %esi # imm = 0x9896E40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000400, %esi # imm = 0x2625B90
callq hipMalloc
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
xorl %r15d, %r15d
xorl %edi, %edi
callq srand
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1125899907, %rax, %rcx # imm = 0x431BDE83
movq %rcx, %rdx
shrq $63, %rdx
sarq $50, %rcx
addl %edx, %ecx
imull $1000000, %ecx, %ecx # imm = 0xF4240
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq $10000100, %r13 # imm = 0x9896E4
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $40000400, %r12 # imm = 0x2625B90
cmpq $3, %r15
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $160001600, %edx # imm = 0x9896E40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40000400, %edx # imm = 0x2625B90
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 38807(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7requestPiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $40000400, %edx # imm = 0x2625B90
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7requestPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7requestPiS_,@object # @_Z7requestPiS_
.section .rodata,"a",@progbits
.globl _Z7requestPiS_
.p2align 3, 0x0
_Z7requestPiS_:
.quad _Z22__device_stub__requestPiS_
.size _Z7requestPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7requestPiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__requestPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7requestPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7requestPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x9896e3, PT ; /* 0x009896e30300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x410 ; /* 0x0000038000007945 */
/* 0x000fe40003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00d0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R2, R5, R7, R4 ; /* 0x0000000705027227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x9896e3, RZ ; /* 0x009896e303057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R2, R2, R5, RZ ; /* 0x0000000502027227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a02 */
/*0160*/ IMAD R5, R0, R6, R5 ; /* 0x0000000600057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105050824 */
/* 0x000fe200078e0a00 */
/*0190*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*01f0*/ @!P0 BRA 0x400 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0004 */
/*0220*/ IMAD.WIDE R6, R3, R8, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fe200078e0208 */
/*0240*/ IADD3 R6, P0, R6, 0x2625b90, RZ ; /* 0x02625b9006067810 */
/* 0x000fca0007f1e0ff */
/*0250*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe400000e0607 */
/*0260*/ IADD3 R8, P0, R6, -0x2000000, RZ ; /* 0xfe00000006087810 */
/* 0x000fc80007f1e0ff */
/*0270*/ IADD3.X R9, R7, -0x1, RZ, P0, !PT ; /* 0xffffffff07097810 */
/* 0x000fca00007fe4ff */
/*0280*/ LDG.E R8, [R8.64+-0x625b90] ; /* 0x9da4700408087981 */
/* 0x000ea2000c1e1900 */
/*0290*/ BSSY B1, 0x380 ; /* 0x000000e000017945 */
/* 0x000fe20003800000 */
/*02a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02b0*/ IADD3 R11, R8, -0x3e9, RZ ; /* 0xfffffc17080b7810 */
/* 0x004fc80007ffe0ff */
/*02c0*/ ISETP.GT.U32.AND P1, PT, R11, 0x182b6, PT ; /* 0x000182b60b00780c */
/* 0x000fda0003f24070 */
/*02d0*/ @P1 BRA 0x370 ; /* 0x0000009000001947 */
/* 0x000fea0003800000 */
/*02e0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IADD3 R8, R8, -0x3e9, RZ ; /* 0xfffffc1708087810 */
/* 0x004fc80007ffe0ff */
/*0300*/ ISETP.GT.U32.AND P1, PT, R8, 0x182b6, PT ; /* 0x000182b60800780c */
/* 0x000fda0003f24070 */
/*0310*/ @P1 BRA 0x370 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0320*/ IADD3 R8, P0, R6, 0x2000000, RZ ; /* 0x0200000006087810 */
/* 0x000fca0007f1e0ff */
/*0330*/ IMAD.X R9, RZ, RZ, R7, P0 ; /* 0x000000ffff097224 */
/* 0x000fca00000e0607 */
/*0340*/ LDG.E R8, [R8.64+0x625b90] ; /* 0x625b900408087981 */
/* 0x000ea4000c1e1900 */
/*0350*/ IADD3 R11, R8, -0x3e9, RZ ; /* 0xfffffc17080b7810 */
/* 0x004fc80007ffe0ff */
/*0360*/ ISETP.LT.U32.AND P0, PT, R11, 0x182b7, PT ; /* 0x000182b70b00780c */
/* 0x000fd00003f01070 */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0390*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x000fe200078e0206 */
/*03a0*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fe40004000000 */
/*03b0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*03c0*/ IMAD.IADD R3, R0.reuse, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x040fe400078e0203 */
/*03d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*03e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fd000078e0204 */
/*03f0*/ @P0 BRA 0x260 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0420*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0430*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fc800078e00ff */
/*0440*/ IMAD.WIDE R10, R3, R10, c[0x0][0x160] ; /* 0x00005800030a7625 */
/* 0x000fca00078e020a */
/*0450*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea2000c1e1900 */
/*0460*/ LEA R6, P1, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003067a11 */
/* 0x000fe200078210ff */
/*0470*/ BSSY B0, 0x5a0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0490*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*04a0*/ ISETP.GT.U32.AND P2, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fe40003f44070 */
/*04b0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fc80000011403 */
/*04c0*/ LEA.HI.X R7, R3, c[0x0][0x16c], R2, 0x2, P1 ; /* 0x00005b0003077a11 */
/* 0x000fe400008f1402 */
/*04d0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f2e170 */
/*04e0*/ @P2 BRA 0x590 ; /* 0x000000a000002947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R4, P2, R10, 0x2000000, RZ ; /* 0x020000000a047810 */
/* 0x000fca0007f5e0ff */
/*0500*/ IMAD.X R5, RZ, RZ, R11, P2 ; /* 0x000000ffff057224 */
/* 0x000fca00010e060b */
/*0510*/ LDG.E R4, [R4.64+0x625b90] ; /* 0x625b900404047981 */
/* 0x000ea4000c1e1900 */
/*0520*/ IADD3 R2, R4, -0x3e9, RZ ; /* 0xfffffc1704027810 */
/* 0x004fc80007ffe0ff */
/*0530*/ ISETP.GT.U32.AND P2, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f44070 */
/*0540*/ @!P2 IADD3 R8, P3, R10, 0x5000000, RZ ; /* 0x050000000a08a810 */
/* 0x000fca0007f7e0ff */
/*0550*/ @!P2 IMAD.X R9, RZ, RZ, R11, P3 ; /* 0x000000ffff09a224 */
/* 0x000fca00018e060b */
/*0560*/ @!P2 LDG.E R8, [R8.64+-0x3b48e0] ; /* 0xc4b720040808a981 */
/* 0x000ea4000c1e1900 */
/*0570*/ @!P2 IADD3 R2, R8, -0x3e9, RZ ; /* 0xfffffc170802a810 */
/* 0x004fc80007ffe0ff */
/*0580*/ @!P2 ISETP.LT.U32.AND P1, PT, R2, 0x182b7, PT ; /* 0x000182b70200a80c */
/* 0x000fd00003f21070 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ SEL R9, RZ, 0x1, !P1 ; /* 0x00000001ff097807 */
/* 0x000fe20004800000 */
/*05b0*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*05c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e8000c101904 */
/*05d0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*05e0*/ BSSY B0, 0x6e0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*05f0*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0206 */
/*0600*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*0610*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0620*/ @P1 BRA 0x6d0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0630*/ IADD3 R6, P1, R4, 0x2000000, RZ ; /* 0x0200000004067810 */
/* 0x001fca0007f3e0ff */
/*0640*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x000fca00008e0605 */
/*0650*/ LDG.E R6, [R6.64+0x625b90] ; /* 0x625b900406067981 */
/* 0x000ea4000c1e1900 */
/*0660*/ IADD3 R2, R6, -0x3e9, RZ ; /* 0xfffffc1706027810 */
/* 0x004fc80007ffe0ff */
/*0670*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0680*/ @!P1 IADD3 R8, P2, R4, 0x5000000, RZ ; /* 0x0500000004089810 */
/* 0x000fca0007f5e0ff */
/*0690*/ @!P1 IMAD.X R9, RZ, RZ, R5, P2 ; /* 0x000000ffff099224 */
/* 0x000fca00010e0605 */
/*06a0*/ @!P1 LDG.E R8, [R8.64+-0x3b48e0] ; /* 0xc4b7200408089981 */
/* 0x000ea4000c1e1900 */
/*06b0*/ @!P1 IADD3 R2, R8, -0x3e9, RZ ; /* 0xfffffc1708029810 */
/* 0x004fc80007ffe0ff */
/*06c0*/ @!P1 ISETP.LT.U32.AND P0, PT, R2, 0x182b7, PT ; /* 0x000182b70200980c */
/* 0x000fd00003f01070 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*06e0*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fe20004000000 */
/*06f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x000fc800078e0204 */
/*0700*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0001e8000c101904 */
/*0710*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0720*/ BSSY B0, 0x830 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0730*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x000fe200078e020a */
/*0740*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0750*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*0760*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0770*/ @P1 BRA 0x820 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R8, P1, R4, 0x2000000, RZ ; /* 0x0200000004087810 */
/* 0x001fca0007f3e0ff */
/*0790*/ IMAD.X R9, RZ, RZ, R5, P1 ; /* 0x000000ffff097224 */
/* 0x000fca00008e0605 */
/*07a0*/ LDG.E R8, [R8.64+0x625b90] ; /* 0x625b900408087981 */
/* 0x000ea4000c1e1900 */
/*07b0*/ IADD3 R2, R8, -0x3e9, RZ ; /* 0xfffffc1708027810 */
/* 0x004fc80007ffe0ff */
/*07c0*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*07d0*/ @!P1 IADD3 R10, P2, R4, 0x5000000, RZ ; /* 0x05000000040a9810 */
/* 0x000fca0007f5e0ff */
/*07e0*/ @!P1 IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b9224 */
/* 0x000fca00010e0605 */
/*07f0*/ @!P1 LDG.E R10, [R10.64+-0x3b48e0] ; /* 0xc4b720040a0a9981 */
/* 0x000ea4000c1e1900 */
/*0800*/ @!P1 IADD3 R2, R10, -0x3e9, RZ ; /* 0xfffffc170a029810 */
/* 0x004fc80007ffe0ff */
/*0810*/ @!P1 ISETP.LT.U32.AND P0, PT, R2, 0x182b7, PT ; /* 0x000182b70200980c */
/* 0x000fd00003f01070 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0830*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fe20004000000 */
/*0840*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc800078e0204 */
/*0850*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0860*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*0870*/ BSSY B0, 0x980 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0890*/ IADD3 R2, R2, -0x3e9, RZ ; /* 0xfffffc1702027810 */
/* 0x004fc80007ffe0ff */
/*08a0*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*08b0*/ @P1 BRA 0x970 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*08c0*/ IADD3 R4, P1, R8, 0x2000000, RZ ; /* 0x0200000008047810 */
/* 0x001fca0007f3e0ff */
/*08d0*/ IMAD.X R5, RZ, RZ, R9, P1 ; /* 0x000000ffff057224 */
/* 0x000fca00008e0609 */
/*08e0*/ LDG.E R4, [R4.64+0x625b90] ; /* 0x625b900404047981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ IADD3 R2, R4, -0x3e9, RZ ; /* 0xfffffc1704027810 */
/* 0x004fc80007ffe0ff */
/*0900*/ ISETP.GT.U32.AND P1, PT, R2, 0x182b6, PT ; /* 0x000182b60200780c */
/* 0x000fda0003f24070 */
/*0910*/ @P1 BRA 0x970 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0920*/ IADD3 R4, P0, R8, 0x5000000, RZ ; /* 0x0500000008047810 */
/* 0x000fca0007f1e0ff */
/*0930*/ IMAD.X R5, RZ, RZ, R9, P0 ; /* 0x000000ffff057224 */
/* 0x000fca00000e0609 */
/*0940*/ LDG.E R4, [R4.64+-0x3b48e0] ; /* 0xc4b7200404047981 */
/* 0x000ea4000c1e1900 */
/*0950*/ IADD3 R2, R4, -0x3e9, RZ ; /* 0xfffffc1704027810 */
/* 0x004fc80007ffe0ff */
/*0960*/ ISETP.LT.U32.AND P0, PT, R2, 0x182b7, PT ; /* 0x000182b70200780c */
/* 0x000fd00003f01070 */
/*0970*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0980*/ IMAD.WIDE R6, R0.reuse, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x040fe200078e0206 */
/*0990*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fe40004000000 */
/*09a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc60007ffe000 */
/*09b0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001e2000c101904 */
/*09c0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*09d0*/ ISETP.GE.AND P0, PT, R3, 0x9896e4, PT ; /* 0x009896e40300780c */
/* 0x000fda0003f06270 */
/*09e0*/ @!P0 BRA 0x430 ; /* 0xfffffa4000008947 */
/* 0x001fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7requestPiS_
.globl _Z7requestPiS_
.p2align 8
.type _Z7requestPiS_,@function
_Z7requestPiS_:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x9896e4, v1
s_cbranch_execz .LBB0_9
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s2, v1
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0x9896e3, v1
v_add_co_u32 v2, s0, v2, s8
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_9
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 0xfffffc17, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e64 s0, 0x182b6, v0
v_cmpx_gt_u32_e32 0x182b7, v0
s_cbranch_execz .LBB0_7
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, 0x2625000, v0
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
global_load_b32 v0, v[4:5], off offset:2960
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 0xfffffc17, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_u32_e64 s11, 0x182b6, v0
v_cmpx_gt_u32_e32 0x182b7, v0
s_cbranch_execz .LBB0_6
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_and_not1_b32 s11, s11, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, 0x4c4b000, v0
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_mov_b32 s10, 1
global_load_b32 v0, v[4:5], off offset:1824
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 0xfffffc17, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_u32_e32 vcc_lo, 0x182b6, v0
s_and_b32 s13, vcc_lo, exec_lo
s_or_b32 s11, s11, s13
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
s_and_b32 s11, s11, exec_lo
s_or_b32 s0, s0, s11
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v0, s10
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, 0
s_branch .LBB0_2
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7requestPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7requestPiS_, .Lfunc_end0-_Z7requestPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7requestPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7requestPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00119f3b_00000000-6_test_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7requestPiS_PiS_
.type _Z28__device_stub__Z7requestPiS_PiS_, @function
_Z28__device_stub__Z7requestPiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7requestPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7requestPiS_PiS_, .-_Z28__device_stub__Z7requestPiS_PiS_
.globl _Z7requestPiS_
.type _Z7requestPiS_, @function
_Z7requestPiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7requestPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7requestPiS_, .-_Z7requestPiS_
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $160001600, %edi
call malloc@PLT
movq %rax, %r14
movl $40000400, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $160001600, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40000400, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %edi
call srand@PLT
leaq 40000400(%r14), %rbp
movl $0, %r12d
.L12:
leaq -40000400(%rbp), %rbx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1125899907, %rdx, %rdx
sarq $50, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
addl $10000100, %r12d
addq $40000400, %rbp
cmpl $30000300, %r12d
jne .L12
movl $1, %ecx
movl $160001600, %edx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000400, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $39063, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $40000400, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7requestPiS_PiS_
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z7requestPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7requestPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__requestPiS_ # -- Begin function _Z22__device_stub__requestPiS_
.p2align 4, 0x90
.type _Z22__device_stub__requestPiS_,@function
_Z22__device_stub__requestPiS_: # @_Z22__device_stub__requestPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7requestPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__requestPiS_, .Lfunc_end0-_Z22__device_stub__requestPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $160001600, %edi # imm = 0x9896E40
callq malloc
movq %rax, %rbx
movl $40000400, %edi # imm = 0x2625B90
callq malloc
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $160001600, %esi # imm = 0x9896E40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000400, %esi # imm = 0x2625B90
callq hipMalloc
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
xorl %r15d, %r15d
xorl %edi, %edi
callq srand
movq %rbx, %r12
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1125899907, %rax, %rcx # imm = 0x431BDE83
movq %rcx, %rdx
shrq $63, %rdx
sarq $50, %rcx
addl %edx, %ecx
imull $1000000, %ecx, %ecx # imm = 0xF4240
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
incq %r13
cmpq $10000100, %r13 # imm = 0x9896E4
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $40000400, %r12 # imm = 0x2625B90
cmpq $3, %r15
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $160001600, %edx # imm = 0x9896E40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40000400, %edx # imm = 0x2625B90
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 38807(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7requestPiS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $40000400, %edx # imm = 0x2625B90
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7requestPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7requestPiS_,@object # @_Z7requestPiS_
.section .rodata,"a",@progbits
.globl _Z7requestPiS_
.p2align 3, 0x0
_Z7requestPiS_:
.quad _Z22__device_stub__requestPiS_
.size _Z7requestPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7requestPiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__requestPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7requestPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
/****************************************************************************
*
*
* Compile with:
* nvcc -o cudapass cuda_password.cu
*
* Dr Kevan Buckley, University of Wolverhampton, January 2018
*****************************************************************************/
__device__ int is_a_match(char *attempt){
char plain_password1[] ="AA2434";
char plain_password2[] ="RA3333";
char plain_password3[] ="MI2222";
char plain_password4[] ="TA4444";
char *r = attempt;
char *m = attempt;
char *t = attempt;
char *a = attempt;
char *r1 = plain_password1;
char *r2 = plain_password2;
char *r3 = plain_password3;
char *r4 = plain_password4;
while(*r ==*r1){
if(*r == '\0')
{
printf("password:%s\n", plain_password1);
break;
}
r++;
r1++;
}
while(*m ==*r2){
if(*m == '\0')
{
printf("password:%s\n", plain_password2);
break;
}
m++;
r2++;
}
while(*t ==*r3){
if(*t == '\0')
{
printf("password:%s\n", plain_password3);
break;
}
t++;
r3++;
}
while(*a ==*r4){
if(*a == '\0')
{
printf("password: %s\n", plain_password4);
return 1;
}
a++;
r4++;
}
return 0;
}
__global__ void kernel(){
char n1, n2, n3, n4;
char password[7];
password[6] ='\0';
int i = blockIdx.x +65;
int j = threadIdx.x+65;
char firstMatch =i;
char secondMatch =j;
password[0] =firstMatch;
password[1] =secondMatch;
for(n1='0'; n1<='9'; n1++){
for(n2='0'; n2<='9'; n2++){
for(n3='0'; n3<='9'; n3++){
for(n4='0'; n4<='9'; n4++){
password[2] =n1;
password[3] =n2;
password[4] =n3;
password[5] =n4;
if(is_a_match(password)){
}
else{
//printf("tried: %s\n",password);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish,long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
kernel<<<26,26>>>();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2UR UR39, SR_CTAID.X ; /* 0x00000000002779c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ ULDC UR36, c[0x0][0x20] ; /* 0x0000080000247ab9 */
/* 0x000fe20000000800 */
/*0050*/ BSSY B10, 0xf80 ; /* 0x00000f20000a7945 */
/* 0x000fe20003800000 */
/*0060*/ ULDC UR37, c[0x0][0x24] ; /* 0x0000090000257ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R22, RZ, RZ, 0x30 ; /* 0x00000030ff167424 */
/* 0x000fe200078e00ff */
/*0080*/ STL.U8 [R1+0x2e], RZ ; /* 0x00002eff01007387 */
/* 0x0005e20000100000 */
/*0090*/ R2UR UR50, R1 ; /* 0x00000000013273c2 */
/* 0x000ee200000e0000 */
/*00a0*/ IADD3 R19, R1.reuse, 0x7, RZ ; /* 0x0000000701137810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ IADD3 R17, R1, 0xe, RZ ; /* 0x0000000e01117810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ UIADD3 UR38, UR39, 0x41, URZ ; /* 0x0000004127267890 */
/* 0x001fe2000fffe03f */
/*00d0*/ IADD3 R0, R0, 0x41, RZ ; /* 0x0000004100007810 */
/* 0x002fca0007ffe0ff */
/*00e0*/ IMAD.U32 R2, RZ, RZ, UR38 ; /* 0x00000026ff027e24 */
/* 0x000fe2000f8e00ff */
/*00f0*/ STL.U8 [R1+0x29], R0 ; /* 0x0000290001007387 */
/* 0x0005e20000100000 */
/*0100*/ UIADD3 UR36, UP0, UR50, UR36, URZ ; /* 0x0000002432247290 */
/* 0x008fe4000ff1e03f */
/*0110*/ UIADD3 UR43, UR50, 0x15, URZ ; /* 0x00000015322b7890 */
/* 0x000fe2000fffe03f */
/*0120*/ STL.U8 [R1+0x28], R2 ; /* 0x0000280201007387 */
/* 0x0005e20000100000 */
/*0130*/ UIADD3.X UR37, URZ, UR37, URZ, UP0, !UPT ; /* 0x000000253f257290 */
/* 0x000fe400087fe43f */
/*0140*/ UIADD3 UR48, UP0, UR36, 0x7, URZ ; /* 0x0000000724307890 */
/* 0x000fe4000ff1e03f */
/*0150*/ UIADD3 UR46, UP1, UR36, 0xe, URZ ; /* 0x0000000e242e7890 */
/* 0x000fc4000ff3e03f */
/*0160*/ UIADD3 UR44, UP2, UR36, 0x15, URZ ; /* 0x00000015242c7890 */
/* 0x000fe4000ff5e03f */
/*0170*/ UIADD3 UR41, UP3, UR36, 0x20, URZ ; /* 0x0000002024297890 */
/* 0x000fe4000ff7e03f */
/*0180*/ UIADD3 UR40, UR50, 0x28, URZ ; /* 0x0000002832287890 */
/* 0x000fe4000fffe03f */
/*0190*/ UIADD3.X UR49, URZ, UR37, URZ, UP0, !UPT ; /* 0x000000253f317290 */
/* 0x000fe400087fe43f */
/*01a0*/ UIADD3.X UR47, URZ, UR37, URZ, UP1, !UPT ; /* 0x000000253f2f7290 */
/* 0x000fe40008ffe43f */
/*01b0*/ UIADD3.X UR45, URZ, UR37, URZ, UP2, !UPT ; /* 0x000000253f2d7290 */
/* 0x000fc400097fe43f */
/*01c0*/ UIADD3.X UR42, URZ, UR37, URZ, UP3, !UPT ; /* 0x000000253f2a7290 */
/* 0x004fc80009ffe43f */
/*01d0*/ BSSY B9, 0xf20 ; /* 0x00000d4000097945 */
/* 0x000fe20003800000 */
/*01e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x30 ; /* 0x00000030ff127424 */
/* 0x001fce00078e00ff */
/*01f0*/ BSSY B8, 0xec0 ; /* 0x00000cc000087945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R16, RZ, RZ, 0x30 ; /* 0x00000030ff107424 */
/* 0x001fe400078e00ff */
/*0210*/ BSSY B7, 0xe60 ; /* 0x00000c4000077945 */
/* 0x000fe20003800000 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, 0x30 ; /* 0x00000030ff027424 */
/* 0x001fc800078e00ff */
/*0230*/ IMAD.MOV.U32 R0, RZ, RZ, 0x41 ; /* 0x00000041ff007424 */
/* 0x000fe200078e00ff */
/*0240*/ ULOP3.LUT UP0, URZ, UR39, 0xff, URZ, 0xc0, !UPT ; /* 0x000000ff273f7892 */
/* 0x000fe2000f80c03f */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, 0x33 ; /* 0x00000033ff057424 */
/* 0x000fe200078e00ff */
/*0260*/ STL.U8 [R1+0x2a], R22 ; /* 0x00002a1601007387 */
/* 0x000fe20000100000 */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, 0x32 ; /* 0x00000032ff037424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4d ; /* 0x0000004dff067424 */
/* 0x000fe200078e00ff */
/*0290*/ STL.U8 [R1], R0 ; /* 0x0000000001007387 */
/* 0x000fe20000100000 */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x49 ; /* 0x00000049ff077424 */
/* 0x000fe200078e00ff */
/*02b0*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f008 */
/*02c0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x54 ; /* 0x00000054ff087424 */
/* 0x000fe200078e00ff */
/*02d0*/ STL.U8 [R1+0x1], R0 ; /* 0x0000010001007387 */
/* 0x000fe20000100000 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x34 ; /* 0x00000034ff047424 */
/* 0x000fc600078e00ff */
/*02f0*/ STL.U8 [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x000fe80000100000 */
/*0300*/ STL.U8 [R1+0x16], R0 ; /* 0x0000160001007387 */
/* 0x0011e80000100000 */
/*0310*/ STL.U8 [R1+0x2], R3 ; /* 0x0000020301007387 */
/* 0x000fe80000100000 */
/*0320*/ STL.U8 [R1+0x10], R3 ; /* 0x0000100301007387 */
/* 0x000fe20000100000 */
/*0330*/ PRMT R0, R5, 0x7610, R0 ; /* 0x0000761005007816 */
/* 0x001fe20000000000 */
/*0340*/ IMAD.MOV.U32 R5, RZ, RZ, 0x52 ; /* 0x00000052ff057424 */
/* 0x000fc400078e00ff */
/*0350*/ STL.U8 [R1+0x11], R3 ; /* 0x0000110301007387 */
/* 0x000fe80000100000 */
/*0360*/ STL.U8 [R1+0x12], R3 ; /* 0x0000120301007387 */
/* 0x000fe80000100000 */
/*0370*/ STL.U8 [R1+0x13], R3 ; /* 0x0000130301007387 */
/* 0x0001e80000100000 */
/*0380*/ STL.U8 [R1+0x3], R4 ; /* 0x0000030401007387 */
/* 0x000fe80000100000 */
/*0390*/ STL.U8 [R1+0x5], R4 ; /* 0x0000050401007387 */
/* 0x000fe20000100000 */
/*03a0*/ PRMT R3, R5, 0x7610, R3 ; /* 0x0000761005037816 */
/* 0x001fc40000000003 */
/*03b0*/ PRMT R5, R6, 0x7610, R5 ; /* 0x0000761006057816 */
/* 0x000fe20000000005 */
/*03c0*/ STL.U8 [R1+0x17], R4 ; /* 0x0000170401007387 */
/* 0x000fe20000100000 */
/*03d0*/ PRMT R6, R7, 0x7610, R6 ; /* 0x0000761007067816 */
/* 0x000fe40000000006 */
/*03e0*/ PRMT R7, R8, 0x7610, R7 ; /* 0x0000761008077816 */
/* 0x000fe20000000007 */
/*03f0*/ STL.U8 [R1+0x18], R4 ; /* 0x0000180401007387 */
/* 0x000fe80000100000 */
/*0400*/ STL.U8 [R1+0x19], R4 ; /* 0x0000190401007387 */
/* 0x000fe80000100000 */
/*0410*/ STL.U8 [R1+0x1a], R4 ; /* 0x00001a0401007387 */
/* 0x000fe80000100000 */
/*0420*/ STL.U8 [R1+0x7], R3 ; /* 0x0000070301007387 */
/* 0x000fe80000100000 */
/*0430*/ STL.U8 [R1+0xe], R5 ; /* 0x00000e0501007387 */
/* 0x000fe80000100000 */
/*0440*/ STL.U8 [R1+0xf], R6 ; /* 0x00000f0601007387 */
/* 0x000fe80000100000 */
/*0450*/ STL.U8 [R1+0x15], R7 ; /* 0x0000150701007387 */
/* 0x000fe80000100000 */
/*0460*/ STL.U8 [R1+0x2b], R18 ; /* 0x00002b1201007387 */
/* 0x000fe80000100000 */
/*0470*/ STL.U8 [R1+0x2c], R16 ; /* 0x00002c1001007387 */
/* 0x000fe80000100000 */
/*0480*/ STL.U8 [R1+0x2d], R2 ; /* 0x00002d0201007387 */
/* 0x000fe80000100000 */
/*0490*/ STL.U8 [R1+0x6], RZ ; /* 0x000006ff01007387 */
/* 0x000fe80000100000 */
/*04a0*/ STL.U8 [R1+0xd], RZ ; /* 0x00000dff01007387 */
/* 0x000fe80000100000 */
/*04b0*/ STL.U8 [R1+0x14], RZ ; /* 0x000014ff01007387 */
/* 0x000fe80000100000 */
/*04c0*/ STL.U8 [R1+0x1b], RZ ; /* 0x00001bff01007387 */
/* 0x000fe80000100000 */
/*04d0*/ STL.U8 [R1+0x4], R0 ; /* 0x0000040001007387 */
/* 0x000fe80000100000 */
/*04e0*/ STL.U8 [R1+0x9], R0 ; /* 0x0000090001007387 */
/* 0x000fe80000100000 */
/*04f0*/ STL.U8 [R1+0xa], R0 ; /* 0x00000a0001007387 */
/* 0x000fe80000100000 */
/*0500*/ STL.U8 [R1+0xb], R0 ; /* 0x00000b0001007387 */
/* 0x000fe80000100000 */
/*0510*/ STL.U8 [R1+0xc], R0 ; /* 0x00000c0001007387 */
/* 0x0001e40000100000 */
/*0520*/ IMAD.MOV.U32 R0, RZ, RZ, 0x52 ; /* 0x00000052ff007424 */
/* 0x001fe200078e00ff */
/*0530*/ @P0 BRA 0x750 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0540*/ BSSY B6, 0x750 ; /* 0x0000020000067945 */
/* 0x000fe20003800000 */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, 0x41 ; /* 0x00000041ff047424 */
/* 0x000fc400078e00ff */
/*0560*/ IMAD.U32 R6, RZ, RZ, UR40 ; /* 0x00000028ff067e24 */
/* 0x000fe4000f8e00ff */
/*0570*/ IMAD.MOV.U32 R3, RZ, RZ, R1 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0001 */
/*0580*/ LOP3.LUT P0, RZ, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04ff7812 */
/* 0x000fda000780c0ff */
/*0590*/ @!P0 BRA 0x620 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*05a0*/ LDL.U8 R5, [R3+0x1] ; /* 0x0000010003057983 */
/* 0x0000a80000100000 */
/*05b0*/ LDL.U8 R4, [R6+0x1] ; /* 0x0000010006047983 */
/* 0x000ea20000100000 */
/*05c0*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x001fe40007ffe0ff */
/*05d0*/ ISETP.NE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x004fe40003f05270 */
/*05e0*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fca0007ffe0ff */
/*05f0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0005 */
/*0600*/ @!P0 BRA 0x580 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0610*/ BRA 0x740 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0620*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0630*/ IMAD.U32 R10, RZ, RZ, UR36 ; /* 0x00000024ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0640*/ IMAD.U32 R11, RZ, RZ, UR37 ; /* 0x00000025ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0650*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0660*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e220000000a00 */
/*0670*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0680*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0003e20000100a00 */
/*0690*/ IMAD.U32 R6, RZ, RZ, UR41 ; /* 0x00000029ff067e24 */
/* 0x000fe4000f8e00ff */
/*06a0*/ IMAD.U32 R7, RZ, RZ, UR42 ; /* 0x0000002aff077e24 */
/* 0x000fc6000f8e00ff */
/*06b0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe20000000000 */
/*06c0*/ MOV R3, 0x730 ; /* 0x0000073000037802 */
/* 0x000fc40000000f00 */
/*06d0*/ MOV R20, 0x6b0 ; /* 0x000006b000147802 */
/* 0x000fe40000000f00 */
/*06e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*06f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0700*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0710*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0720*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0730*/ LDL.U8 R0, [R1+0x7] ; /* 0x0000070001007983 */
/* 0x0001640000100000 */
/*0740*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0750*/ IMAD.U32 R23, RZ, RZ, UR38 ; /* 0x00000026ff177e24 */
/* 0x000fe2000f8e00ff */
/*0760*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x020fe200078ec0ff */
/*0770*/ BSSY B6, 0x9a0 ; /* 0x0000022000067945 */
/* 0x000fe60003800000 */
/*0780*/ LOP3.LUT R23, R23, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff17177812 */
/* 0x000fc800078ec0ff */
/*0790*/ ISETP.NE.AND P0, PT, R23, R0, PT ; /* 0x000000001700720c */
/* 0x000fda0003f05270 */
/*07a0*/ @P0 BRA 0x990 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.U32 R0, RZ, RZ, UR38 ; /* 0x00000026ff007e24 */
/* 0x000fe4000f8e00ff */
/*07c0*/ IMAD.U32 R4, RZ, RZ, UR40 ; /* 0x00000028ff047e24 */
/* 0x000fe4000f8e00ff */
/*07d0*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0013 */
/*07e0*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*07f0*/ @!P0 BRA 0x880 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0800*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0810*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0820*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0830*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0840*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*0860*/ @!P0 BRA 0x7e0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0870*/ BRA 0x990 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0880*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0890*/ IMAD.U32 R10, RZ, RZ, UR48 ; /* 0x00000030ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*08a0*/ IMAD.U32 R11, RZ, RZ, UR49 ; /* 0x00000031ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*08b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*08c0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*08d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*08e0*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0005e20000100a00 */
/*08f0*/ IMAD.U32 R6, RZ, RZ, UR41 ; /* 0x00000029ff067e24 */
/* 0x000fe4000f8e00ff */
/*0900*/ IMAD.U32 R7, RZ, RZ, UR42 ; /* 0x0000002aff077e24 */
/* 0x000fc6000f8e00ff */
/*0910*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0920*/ MOV R3, 0x990 ; /* 0x0000099000037802 */
/* 0x000fc40000000f00 */
/*0930*/ MOV R20, 0x910 ; /* 0x0000091000147802 */
/* 0x000fe40000000f00 */
/*0940*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0950*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0960*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0970*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0980*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0990*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*09a0*/ LDL.U8 R0, [R1+0xe] ; /* 0x00000e0001007983 */
/* 0x000ea20000100000 */
/*09b0*/ BSSY B6, 0xbd0 ; /* 0x0000021000067945 */
/* 0x000fe20003800000 */
/*09c0*/ ISETP.NE.AND P0, PT, R23, R0, PT ; /* 0x000000001700720c */
/* 0x004fda0003f05270 */
/*09d0*/ @P0 BRA 0xbc0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*09e0*/ IMAD.U32 R0, RZ, RZ, UR38 ; /* 0x00000026ff007e24 */
/* 0x000fe4000f8e00ff */
/*09f0*/ IMAD.U32 R4, RZ, RZ, UR40 ; /* 0x00000028ff047e24 */
/* 0x000fe4000f8e00ff */
/*0a00*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0011 */
/*0a10*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0a20*/ @!P0 BRA 0xab0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0a30*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0a40*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0a50*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0a70*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0a80*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*0a90*/ @!P0 BRA 0xa10 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0aa0*/ BRA 0xbc0 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0ac0*/ IMAD.U32 R10, RZ, RZ, UR46 ; /* 0x0000002eff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0ad0*/ IMAD.U32 R11, RZ, RZ, UR47 ; /* 0x0000002fff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0ae0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0af0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0b00*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0b10*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0005e20000100a00 */
/*0b20*/ IMAD.U32 R6, RZ, RZ, UR41 ; /* 0x00000029ff067e24 */
/* 0x000fe4000f8e00ff */
/*0b30*/ IMAD.U32 R7, RZ, RZ, UR42 ; /* 0x0000002aff077e24 */
/* 0x000fc6000f8e00ff */
/*0b40*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0b50*/ MOV R3, 0xbc0 ; /* 0x00000bc000037802 */
/* 0x000fc40000000f00 */
/*0b60*/ MOV R20, 0xb40 ; /* 0x00000b4000147802 */
/* 0x000fe40000000f00 */
/*0b70*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0b90*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0ba0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0bb0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0bc0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0bd0*/ LDL.U8 R0, [R1+0x15] ; /* 0x0000150001007983 */
/* 0x000ea20000100000 */
/*0be0*/ BSSY B6, 0xe00 ; /* 0x0000021000067945 */
/* 0x000fe20003800000 */
/*0bf0*/ ISETP.NE.AND P0, PT, R23, R0, PT ; /* 0x000000001700720c */
/* 0x004fda0003f05270 */
/*0c00*/ @P0 BRA 0xdf0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0c10*/ IMAD.U32 R0, RZ, RZ, UR38 ; /* 0x00000026ff007e24 */
/* 0x000fe4000f8e00ff */
/*0c20*/ IMAD.U32 R5, RZ, RZ, UR43 ; /* 0x0000002bff057e24 */
/* 0x000fe4000f8e00ff */
/*0c30*/ IMAD.U32 R4, RZ, RZ, UR40 ; /* 0x00000028ff047e24 */
/* 0x000fe4000f8e00ff */
/*0c40*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0c50*/ @!P0 BRA 0xce0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0c60*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0c70*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0c80*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0c90*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0ca0*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0cb0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*0cc0*/ @!P0 BRA 0xc40 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0cd0*/ BRA 0xdf0 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0ce0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0cf0*/ IMAD.U32 R10, RZ, RZ, UR44 ; /* 0x0000002cff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0d00*/ IMAD.U32 R11, RZ, RZ, UR45 ; /* 0x0000002dff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe200078e00ff */
/*0d20*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0d30*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe200078e00ff */
/*0d40*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0005e20000100a00 */
/*0d50*/ IMAD.U32 R6, RZ, RZ, UR41 ; /* 0x00000029ff067e24 */
/* 0x000fe4000f8e00ff */
/*0d60*/ IMAD.U32 R7, RZ, RZ, UR42 ; /* 0x0000002aff077e24 */
/* 0x000fc6000f8e00ff */
/*0d70*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0d80*/ MOV R3, 0xdf0 ; /* 0x00000df000037802 */
/* 0x000fc40000000f00 */
/*0d90*/ MOV R20, 0xd70 ; /* 0x00000d7000147802 */
/* 0x000fe40000000f00 */
/*0da0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0db0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0dc0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0dd0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0de0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0df0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0e00*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*0e10*/ LOP3.LUT R0, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02007812 */
/* 0x000fc800078ec0ff */
/*0e20*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0e30*/ @P0 CALL.REL.NOINC 0xe50 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0e40*/ BRA 0x230 ; /* 0xfffff3e000007947 */
/* 0x000fea000383ffff */
/*0e50*/ BSYNC B7 ; /* 0x0000000000077941 */
/* 0x000fea0003800000 */
/*0e60*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*0e70*/ LOP3.LUT R0, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10007812 */
/* 0x000fc800078ec0ff */
/*0e80*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0e90*/ @P0 CALL.REL.NOINC 0xeb0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0ea0*/ BRA 0x210 ; /* 0xfffff36000007947 */
/* 0x000fea000383ffff */
/*0eb0*/ BSYNC B8 ; /* 0x0000000000087941 */
/* 0x000fea0003800000 */
/*0ec0*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fc80007ffe0ff */
/*0ed0*/ LOP3.LUT R0, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12007812 */
/* 0x000fc800078ec0ff */
/*0ee0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0ef0*/ @P0 CALL.REL.NOINC 0xf10 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0f00*/ BRA 0x1f0 ; /* 0xfffff2e000007947 */
/* 0x000fea000383ffff */
/*0f10*/ BSYNC B9 ; /* 0x0000000000097941 */
/* 0x000fea0003800000 */
/*0f20*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fc80007ffe0ff */
/*0f30*/ LOP3.LUT R0, R22, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff16007812 */
/* 0x000fc800078ec0ff */
/*0f40*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0f50*/ @P0 CALL.REL.NOINC 0xf70 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0f60*/ BRA 0x1d0 ; /* 0xfffff26000007947 */
/* 0x000fea000383ffff */
/*0f70*/ BSYNC B10 ; /* 0x00000000000a7941 */
/* 0x000fea0003800000 */
/*0f80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f90*/ BRA 0xf90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
/****************************************************************************
*
*
* Compile with:
* nvcc -o cudapass cuda_password.cu
*
* Dr Kevan Buckley, University of Wolverhampton, January 2018
*****************************************************************************/
__device__ int is_a_match(char *attempt){
char plain_password1[] ="AA2434";
char plain_password2[] ="RA3333";
char plain_password3[] ="MI2222";
char plain_password4[] ="TA4444";
char *r = attempt;
char *m = attempt;
char *t = attempt;
char *a = attempt;
char *r1 = plain_password1;
char *r2 = plain_password2;
char *r3 = plain_password3;
char *r4 = plain_password4;
while(*r ==*r1){
if(*r == '\0')
{
printf("password:%s\n", plain_password1);
break;
}
r++;
r1++;
}
while(*m ==*r2){
if(*m == '\0')
{
printf("password:%s\n", plain_password2);
break;
}
m++;
r2++;
}
while(*t ==*r3){
if(*t == '\0')
{
printf("password:%s\n", plain_password3);
break;
}
t++;
r3++;
}
while(*a ==*r4){
if(*a == '\0')
{
printf("password: %s\n", plain_password4);
return 1;
}
a++;
r4++;
}
return 0;
}
__global__ void kernel(){
char n1, n2, n3, n4;
char password[7];
password[6] ='\0';
int i = blockIdx.x +65;
int j = threadIdx.x+65;
char firstMatch =i;
char secondMatch =j;
password[0] =firstMatch;
password[1] =secondMatch;
for(n1='0'; n1<='9'; n1++){
for(n2='0'; n2<='9'; n2++){
for(n3='0'; n3<='9'; n3++){
for(n4='0'; n4<='9'; n4++){
password[2] =n1;
password[3] =n2;
password[4] =n3;
password[5] =n4;
if(is_a_match(password)){
}
else{
//printf("tried: %s\n",password);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish,long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
kernel<<<26,26>>>();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | .file "tmpxft_0009826e_00000000-6_cuda_password.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10is_a_matchPc
.type _Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10is_a_matchPc, .-_Z10is_a_matchPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2058:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
/****************************************************************************
*
*
* Compile with:
* nvcc -o cudapass cuda_password.cu
*
* Dr Kevan Buckley, University of Wolverhampton, January 2018
*****************************************************************************/
__device__ int is_a_match(char *attempt){
char plain_password1[] ="AA2434";
char plain_password2[] ="RA3333";
char plain_password3[] ="MI2222";
char plain_password4[] ="TA4444";
char *r = attempt;
char *m = attempt;
char *t = attempt;
char *a = attempt;
char *r1 = plain_password1;
char *r2 = plain_password2;
char *r3 = plain_password3;
char *r4 = plain_password4;
while(*r ==*r1){
if(*r == '\0')
{
printf("password:%s\n", plain_password1);
break;
}
r++;
r1++;
}
while(*m ==*r2){
if(*m == '\0')
{
printf("password:%s\n", plain_password2);
break;
}
m++;
r2++;
}
while(*t ==*r3){
if(*t == '\0')
{
printf("password:%s\n", plain_password3);
break;
}
t++;
r3++;
}
while(*a ==*r4){
if(*a == '\0')
{
printf("password: %s\n", plain_password4);
return 1;
}
a++;
r4++;
}
return 0;
}
__global__ void kernel(){
char n1, n2, n3, n4;
char password[7];
password[6] ='\0';
int i = blockIdx.x +65;
int j = threadIdx.x+65;
char firstMatch =i;
char secondMatch =j;
password[0] =firstMatch;
password[1] =secondMatch;
for(n1='0'; n1<='9'; n1++){
for(n2='0'; n2<='9'; n2++){
for(n3='0'; n3<='9'; n3++){
for(n4='0'; n4<='9'; n4++){
password[2] =n1;
password[3] =n2;
password[4] =n3;
password[5] =n4;
if(is_a_match(password)){
}
else{
//printf("tried: %s\n",password);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish,long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
kernel<<<26,26>>>();
cudaThreadSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
/****************************************************************************
*
*
* Compile with:
* nvcc -o cudapass cuda_password.cu
*
* Dr Kevan Buckley, University of Wolverhampton, January 2018
*****************************************************************************/
__device__ int is_a_match(char *attempt){
char plain_password1[] ="AA2434";
char plain_password2[] ="RA3333";
char plain_password3[] ="MI2222";
char plain_password4[] ="TA4444";
char *r = attempt;
char *m = attempt;
char *t = attempt;
char *a = attempt;
char *r1 = plain_password1;
char *r2 = plain_password2;
char *r3 = plain_password3;
char *r4 = plain_password4;
while(*r ==*r1){
if(*r == '\0')
{
printf("password:%s\n", plain_password1);
break;
}
r++;
r1++;
}
while(*m ==*r2){
if(*m == '\0')
{
printf("password:%s\n", plain_password2);
break;
}
m++;
r2++;
}
while(*t ==*r3){
if(*t == '\0')
{
printf("password:%s\n", plain_password3);
break;
}
t++;
r3++;
}
while(*a ==*r4){
if(*a == '\0')
{
printf("password: %s\n", plain_password4);
return 1;
}
a++;
r4++;
}
return 0;
}
__global__ void kernel(){
char n1, n2, n3, n4;
char password[7];
password[6] ='\0';
int i = blockIdx.x +65;
int j = threadIdx.x+65;
char firstMatch =i;
char secondMatch =j;
password[0] =firstMatch;
password[1] =secondMatch;
for(n1='0'; n1<='9'; n1++){
for(n2='0'; n2<='9'; n2++){
for(n3='0'; n3<='9'; n3++){
for(n4='0'; n4<='9'; n4++){
password[2] =n1;
password[3] =n2;
password[4] =n3;
password[5] =n4;
if(is_a_match(password)){
}
else{
//printf("tried: %s\n",password);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish,long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
kernel<<<26,26>>>();
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
/****************************************************************************
*
*
* Compile with:
* nvcc -o cudapass cuda_password.cu
*
* Dr Kevan Buckley, University of Wolverhampton, January 2018
*****************************************************************************/
__device__ int is_a_match(char *attempt){
char plain_password1[] ="AA2434";
char plain_password2[] ="RA3333";
char plain_password3[] ="MI2222";
char plain_password4[] ="TA4444";
char *r = attempt;
char *m = attempt;
char *t = attempt;
char *a = attempt;
char *r1 = plain_password1;
char *r2 = plain_password2;
char *r3 = plain_password3;
char *r4 = plain_password4;
while(*r ==*r1){
if(*r == '\0')
{
printf("password:%s\n", plain_password1);
break;
}
r++;
r1++;
}
while(*m ==*r2){
if(*m == '\0')
{
printf("password:%s\n", plain_password2);
break;
}
m++;
r2++;
}
while(*t ==*r3){
if(*t == '\0')
{
printf("password:%s\n", plain_password3);
break;
}
t++;
r3++;
}
while(*a ==*r4){
if(*a == '\0')
{
printf("password: %s\n", plain_password4);
return 1;
}
a++;
r4++;
}
return 0;
}
__global__ void kernel(){
char n1, n2, n3, n4;
char password[7];
password[6] ='\0';
int i = blockIdx.x +65;
int j = threadIdx.x+65;
char firstMatch =i;
char secondMatch =j;
password[0] =firstMatch;
password[1] =secondMatch;
for(n1='0'; n1<='9'; n1++){
for(n2='0'; n2<='9'; n2++){
for(n3='0'; n3<='9'; n3++){
for(n4='0'; n4<='9'; n4++){
password[2] =n1;
password[3] =n2;
password[4] =n3;
password[5] =n4;
if(is_a_match(password)){
}
else{
//printf("tried: %s\n",password);
}
}
}
}
}
}
int time_difference(struct timespec *start, struct timespec *finish,long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main() {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
kernel<<<26,26>>>();
hipDeviceSynchronize();
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | .text
.file "cuda_password.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009826e_00000000-6_cuda_password.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10is_a_matchPc
.type _Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10is_a_matchPc, .-_Z10is_a_matchPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2058:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2058:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_password.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Split(int * xi, bool * xb, size_t idxi, size_t idxb, size_t N, float threshold)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[(idxb)*N+i] = (((float)xi[(idxi-1)*N+i]) == threshold);
}
return;
} | code for sm_80
Function : _Z5SplitPiPbmmmf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x184], PT, P0 ; /* 0x0000610002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff087624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0000 */
/*00d0*/ IADD3 R9, P0, -R9, c[0x0][0x170], RZ ; /* 0x00005c0009097a10 */
/* 0x000fc80007f1e1ff */
/*00e0*/ IADD3.X R8, R8, -0x1, RZ, P0, !PT ; /* 0xffffffff08087810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R2, R8, c[0x0][0x180], RZ ; /* 0x0000600008027a24 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD R7, R9.reuse, c[0x0][0x184], R2 ; /* 0x0000610009077a24 */
/* 0x040fe400078e0202 */
/*0110*/ IMAD.WIDE.U32 R2, R9, c[0x0][0x180], R4 ; /* 0x0000600009027a25 */
/* 0x000fc800078e0004 */
/*0120*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fe200078e0207 */
/*0130*/ LEA R6, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002067a11 */
/* 0x000fc800078010ff */
/*0140*/ LEA.HI.X R7, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002077a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0000a2000c1e1900 */
/*0160*/ MOV R11, c[0x0][0x178] ; /* 0x00005e00000b7a02 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0d7624 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE.U32 R4, R11, c[0x0][0x180], R4 ; /* 0x000060000b047a25 */
/* 0x000fc800078e0004 */
/*0190*/ IMAD R2, R11, c[0x0][0x184], RZ ; /* 0x000061000b027a24 */
/* 0x000fe400078e02ff */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x001fe400078e00ff */
/*01b0*/ IMAD R11, R13, c[0x0][0x17c], R2 ; /* 0x00005f000d0b7a24 */
/* 0x000fe200078e0202 */
/*01c0*/ IADD3 R2, P1, R4, c[0x0][0x168], RZ ; /* 0x00005a0004027a10 */
/* 0x000fe20007f3e0ff */
/*01d0*/ IMAD R4, R7, c[0x0][0xc], R0 ; /* 0x0000030007047a24 */
/* 0x000fca00078e0200 */
/*01e0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe20000000f00 */
/*01f0*/ I2F R3, R6 ; /* 0x0000000600037306 */
/* 0x004e240000201400 */
/*0200*/ FSETP.NEU.AND P0, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0b */
/* 0x001fe40003f0d000 */
/*0210*/ IADD3.X R3, R5, c[0x0][0x16c], R11, P1, !PT ; /* 0x00005b0005037a10 */
/* 0x000fe40000ffe40b */
/*0220*/ SEL R5, RZ, 0x1, P0 ; /* 0x00000001ff057807 */
/* 0x000fe40000000000 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fc60003f06070 */
/*0240*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101104 */
/*0250*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x001fc80000011404 */
/*0260*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x184], PT, P0 ; /* 0x0000610005007a0c */
/* 0x000fda0003f06100 */
/*0270*/ @!P0 BRA 0xf0 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Split(int * xi, bool * xb, size_t idxi, size_t idxb, size_t N, float threshold)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[(idxb)*N+i] = (((float)xi[(idxi-1)*N+i]) == threshold);
}
return;
} | .file "tmpxft_0016c68a_00000000-6_Split.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5SplitPiPbmmmfPiPbmmmf
.type _Z30__device_stub__Z5SplitPiPbmmmfPiPbmmmf, @function
_Z30__device_stub__Z5SplitPiPbmmmfPiPbmmmf:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5SplitPiPbmmmf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5SplitPiPbmmmfPiPbmmmf, .-_Z30__device_stub__Z5SplitPiPbmmmfPiPbmmmf
.globl _Z5SplitPiPbmmmf
.type _Z5SplitPiPbmmmf, @function
_Z5SplitPiPbmmmf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5SplitPiPbmmmfPiPbmmmf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5SplitPiPbmmmf, .-_Z5SplitPiPbmmmf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5SplitPiPbmmmf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5SplitPiPbmmmf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Split(int * xi, bool * xb, size_t idxi, size_t idxb, size_t N, float threshold)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[(idxb)*N+i] = (((float)xi[(idxi-1)*N+i]) == threshold);
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Split(int * xi, bool * xb, size_t idxi, size_t idxb, size_t N, float threshold)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
xb[(idxb)*N+i] = (((float)xi[(idxi-1)*N+i]) == threshold);
}
return;
} |
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