system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001671d3_00000000-6_fragment_gpu_mem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: cudaMemGetInfo fails, %s \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "free: %.f, total %.f\n"
.LC3:
.string "err2: %d\n"
.LC5:
.string "can allocate: %.fMB\n"
.text
.globl _Z12can_allocatev
.type _Z12can_allocatev, @function
_Z12can_allocatev:
.LFB2070:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
leaq 8(%rsp), %rdi
call cudaMemGetInfo@PLT
testl %eax, %eax
jne .L16
movq (%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
.L6:
mulsd .LC1(%rip), %xmm1
movq 8(%rsp), %rax
testq %rax, %rax
js .L7
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L8:
mulsd .LC1(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq $0, 16(%rsp)
movq (%rsp), %rbx
shrq $2, %rbx
leaq 16(%rsp), %rbp
.L9:
leaq 0(,%rbx,4), %rsi
movq %rbp, %rdi
call cudaMalloc@PLT
cmpl $2, %eax
jne .L10
movq 16(%rsp), %rdi
call cudaFree@PLT
subq $262144, %rbx
cmpq $262143, %rbx
ja .L9
.L10:
movq 16(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testq %rbx, %rbx
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L13:
mulsd .LC4(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
addsd %xmm1, %xmm1
jmp .L6
.L7:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L8
.L12:
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z12can_allocatev, .-_Z12can_allocatev
.section .rodata.str1.1
.LC6:
.string "err1: %d\n"
.LC7:
.string "err3: %d\n"
.LC8:
.string "err4: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $410000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC6(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rbp
movl $524000000, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $3144000000, %r12d
movq %r12, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movl $524000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
movl %eax, %edx
leaq .LC8(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
call cudaGetLastError@PLT
movl %eax, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z12can_allocatev
movl $1048000000, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2096000000, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
movl %eax, %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000, %edi
call sleep@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1051721728
.align 8
.LC4:
.long 0
.long 1053818880
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fragment_gpu_mem.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12can_allocatev
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3eb0000000000000 # double 9.5367431640625E-7
.LCPI0_3:
.quad 0x3ed0000000000000 # double 3.814697265625E-6
.text
.globl _Z12can_allocatev
.p2align 4, 0x90
.type _Z12can_allocatev,@function
_Z12can_allocatev: # @_Z12can_allocatev
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq hipMemGetInfo
testl %eax, %eax
jne .LBB0_5
# %bb.1:
movsd 24(%rsp), %xmm1 # xmm1 = mem[0],zero
movapd .LCPI0_0(%rip), %xmm2 # xmm2 = [1127219200,1160773632,0,0]
unpcklps %xmm2, %xmm1 # xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
movapd .LCPI0_1(%rip), %xmm3 # xmm3 = [4.503599627370496E+15,1.9342813113834067E+25]
subpd %xmm3, %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd .LCPI0_2(%rip), %xmm4 # xmm4 = mem[0],zero
mulsd %xmm4, %xmm0
movsd 16(%rsp), %xmm5 # xmm5 = mem[0],zero
unpcklps %xmm2, %xmm5 # xmm5 = xmm5[0],xmm2[0],xmm5[1],xmm2[1]
subpd %xmm3, %xmm5
movapd %xmm5, %xmm1
unpckhpd %xmm5, %xmm1 # xmm1 = xmm1[1],xmm5[1]
addsd %xmm5, %xmm1
mulsd %xmm4, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
movq $0, 8(%rsp)
movq 16(%rsp), %rbx
movq %rbx, %r15
shrq $2, %r15
andq $-4, %rbx
leaq 8(%rsp), %r14
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
cmpl $2, %eax
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movq 8(%rsp), %rdi
callq hipFree
addq $-262144, %r15 # imm = 0xFFFC0000
addq $-1048576, %rbx # imm = 0xFFF00000
cmpq $262143, %r15 # imm = 0x3FFFF
ja .LBB0_2
.LBB0_4:
movq 8(%rsp), %rdi
callq hipFree
callq hipGetLastError
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movq %r15, %xmm1
punpckldq .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_3(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_5:
.cfi_def_cfa_offset 64
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z12can_allocatev, .Lfunc_end0-_Z12can_allocatev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $48, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -16
leaq 40(%rsp), %rdi
movl $410000000, %esi # imm = 0x18701A80
callq hipMalloc
callq hipGetLastError
movl $.L.str.4, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rbx
movl $524000000, %esi # imm = 0x1F3B9B00
movq %rbx, %rdi
callq hipMalloc
callq hipGetLastError
movl $.L.str.4, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $3144000000, %esi # imm = 0xBB65A200
callq hipMalloc
callq hipGetLastError
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rdi
movl $524000000, %esi # imm = 0x1F3B9B00
callq hipMalloc
callq hipGetLastError
movl $.L.str.5, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leaq 24(%rsp), %rdi
movl $3144000000, %esi # imm = 0xBB65A200
callq hipMalloc
callq hipGetLastError
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
callq hipGetLastError
movl $.L.str.6, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
callq hipGetLastError
movl $.L.str.6, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
callq _Z12can_allocatev
movl $1048000000, %esi # imm = 0x3E773600
movq %rbx, %rdi
callq hipMalloc
callq hipGetLastError
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $2096000000, %esi # imm = 0x7CEE6C00
movq %rbx, %rdi
callq hipMalloc
callq hipGetLastError
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $1000, %edi # imm = 0x3E8
callq sleep
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: hipMemGetInfo fails, %s \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "free: %.f, total %.f\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "err2: %d\n"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "can allocate: %.fMB\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "err1: %d\n"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "err3: %d\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "err4: %d\n"
.size .L.str.6, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// Print device properties
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %lu\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ?"Yes" : "No"));
return;
}
int main()
{
int devCount;
cudaGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// Print device properties
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %lu\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ?"Yes" : "No"));
return;
}
int main()
{
int devCount;
cudaGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
return 0;
} | .file "tmpxft_000bae54_00000000-6_devicequery.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Major revision number: %d\n"
.align 8
.LC3:
.string "Minor revision number: %d\n"
.align 8
.LC4:
.string "Name: %s\n"
.align 8
.LC5:
.string "Total global memory: %lu\n"
.align 8
.LC6:
.string "Total shared memory per block: %lu\n"
.align 8
.LC7:
.string "Total registers per block: %d\n"
.align 8
.LC8:
.string "Warp size: %d\n"
.align 8
.LC9:
.string "Maximum memory pitch: %lu\n"
.align 8
.LC10:
.string "Maximum threads per block: %d\n"
.align 8
.LC11:
.string "Maximum dimension %d of block: %d\n"
.align 8
.LC12:
.string "Maximum dimension %d of grid: %d\n"
.align 8
.LC13:
.string "Clock rate: %d\n"
.align 8
.LC14:
.string "Total constant memory: %lu\n"
.align 8
.LC15:
.string "Texture alignment: %lu\n"
.align 8
.LC16:
.string "Concurrent copy and execution: %s\n"
.align 8
.LC17:
.string "Number of multiprocessors: %d\n"
.align 8
.LC18:
.string "Kernel execution timeout: %s\n"
.text
.globl _Z12printDevProp14cudaDeviceProp
.type _Z12printDevProp14cudaDeviceProp, @function
_Z12printDevProp14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC11(%rip), %rbp
.L4:
movl 356(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L4
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 368(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 424(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12printDevProp14cudaDeviceProp, .-_Z12printDevProp14cudaDeviceProp
.section .rodata.str1.1
.LC19:
.string "CUDA Device Query...\n"
.LC20:
.string "There are %d CUDA devices.\n"
.LC21:
.string "\nCUDA Device #%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L14
movl $0, %ebx
leaq .LC21(%rip), %r12
.L15:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z12printDevProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L15
.L14:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// Print device properties
void printDevProp(cudaDeviceProp devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %lu\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ?"Yes" : "No"));
return;
}
int main()
{
int devCount;
cudaGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %lu\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ?"Yes" : "No"));
return;
}
int main()
{
int devCount;
hipGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %lu\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ?"Yes" : "No"));
return;
}
int main()
{
int devCount;
hipGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Print device properties
void printDevProp(hipDeviceProp_t devProp)
{
printf("Major revision number: %d\n", devProp.major);
printf("Minor revision number: %d\n", devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total global memory: %lu\n", devProp.totalGlobalMem);
printf("Total shared memory per block: %lu\n", devProp.sharedMemPerBlock);
printf("Total registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Maximum memory pitch: %lu\n", devProp.memPitch);
printf("Maximum threads per block: %d\n", devProp.maxThreadsPerBlock);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of block: %d\n", i, devProp.maxThreadsDim[i]);
for (int i = 0; i < 3; ++i)
printf("Maximum dimension %d of grid: %d\n", i, devProp.maxGridSize[i]);
printf("Clock rate: %d\n", devProp.clockRate);
printf("Total constant memory: %lu\n", devProp.totalConstMem);
printf("Texture alignment: %lu\n", devProp.textureAlignment);
printf("Concurrent copy and execution: %s\n", (devProp.deviceOverlap ? "Yes" : "No"));
printf("Number of multiprocessors: %d\n", devProp.multiProcessorCount);
printf("Kernel execution timeout: %s\n", (devProp.kernelExecTimeoutEnabled ?"Yes" : "No"));
return;
}
int main()
{
int devCount;
hipGetDeviceCount(&devCount);
printf("CUDA Device Query...\n");
printf("There are %d CUDA devices.\n", devCount);
for (int i = 0; i < devCount; ++i)
{
// Get device properties
printf("\nCUDA Device #%d\n", i);
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
printDevProp(devProp);
}
return 0;
} | .text
.file "devicequery.hip"
.globl _Z12printDevProp20hipDeviceProp_tR0600 # -- Begin function _Z12printDevProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z12printDevProp20hipDeviceProp_tR0600,@function
_Z12printDevProp20hipDeviceProp_tR0600: # @_Z12printDevProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rbx
movl 392(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4:
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 384(%rbx)
movl $.L.str.16, %r15d
movl $.L.str.15, %r14d
movl $.L.str.15, %esi
cmoveq %r15, %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rbx)
cmoveq %r15, %r14
movl $.L.str.18, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12printDevProp20hipDeviceProp_tR0600, .Lfunc_end0-_Z12printDevProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr, %edi
callq puts@PLT
movl 1476(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 1476(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 1480(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.21, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep
callq _Z12printDevProp20hipDeviceProp_tR0600
incl %ebp
cmpl 1476(%rsp), %ebp
jl .LBB1_2
.LBB1_3: # %._crit_edge
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Major revision number: %d\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Minor revision number: %d\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total global memory: %lu\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total shared memory per block: %lu\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total registers per block: %d\n"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Warp size: %d\n"
.size .L.str.6, 35
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum memory pitch: %lu\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum threads per block: %d\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Maximum dimension %d of block: %d\n"
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Maximum dimension %d of grid: %d\n"
.size .L.str.10, 36
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Clock rate: %d\n"
.size .L.str.11, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total constant memory: %lu\n"
.size .L.str.12, 36
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Texture alignment: %lu\n"
.size .L.str.13, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Concurrent copy and execution: %s\n"
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Yes"
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "No"
.size .L.str.16, 3
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Number of multiprocessors: %d\n"
.size .L.str.17, 35
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Kernel execution timeout: %s\n"
.size .L.str.18, 35
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "There are %d CUDA devices.\n"
.size .L.str.20, 28
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "\nCUDA Device #%d\n"
.size .L.str.21, 18
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA Device Query..."
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bae54_00000000-6_devicequery.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Major revision number: %d\n"
.align 8
.LC3:
.string "Minor revision number: %d\n"
.align 8
.LC4:
.string "Name: %s\n"
.align 8
.LC5:
.string "Total global memory: %lu\n"
.align 8
.LC6:
.string "Total shared memory per block: %lu\n"
.align 8
.LC7:
.string "Total registers per block: %d\n"
.align 8
.LC8:
.string "Warp size: %d\n"
.align 8
.LC9:
.string "Maximum memory pitch: %lu\n"
.align 8
.LC10:
.string "Maximum threads per block: %d\n"
.align 8
.LC11:
.string "Maximum dimension %d of block: %d\n"
.align 8
.LC12:
.string "Maximum dimension %d of grid: %d\n"
.align 8
.LC13:
.string "Clock rate: %d\n"
.align 8
.LC14:
.string "Total constant memory: %lu\n"
.align 8
.LC15:
.string "Texture alignment: %lu\n"
.align 8
.LC16:
.string "Concurrent copy and execution: %s\n"
.align 8
.LC17:
.string "Number of multiprocessors: %d\n"
.align 8
.LC18:
.string "Kernel execution timeout: %s\n"
.text
.globl _Z12printDevProp14cudaDeviceProp
.type _Z12printDevProp14cudaDeviceProp, @function
_Z12printDevProp14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 392(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 396(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 320(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 340(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 344(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 352(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC11(%rip), %rbp
.L4:
movl 356(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L4
movl $0, %ebx
leaq .LC12(%rip), %rbp
.L5:
movl 368(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $3, %rbx
jne .L5
movl 380(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 400(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 416(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 420(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 424(%rsp)
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12printDevProp14cudaDeviceProp, .-_Z12printDevProp14cudaDeviceProp
.section .rodata.str1.1
.LC19:
.string "CUDA Device Query...\n"
.LC20:
.string "There are %d CUDA devices.\n"
.LC21:
.string "\nCUDA Device #%d\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1056, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L14
movl $0, %ebx
leaq .LC21(%rip), %r12
.L15:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z12printDevProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L15
.L14:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "devicequery.hip"
.globl _Z12printDevProp20hipDeviceProp_tR0600 # -- Begin function _Z12printDevProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z12printDevProp20hipDeviceProp_tR0600,@function
_Z12printDevProp20hipDeviceProp_tR0600: # @_Z12printDevProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 32(%rsp), %rbx
movl 392(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 344(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl 324(%rbx,%r14,4), %edx
movl $.L.str.9, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_1
# %bb.2: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 336(%rbx,%r14,4), %edx
movl $.L.str.10, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq $3, %r14
jne .LBB0_3
# %bb.4:
movl 348(%rbx), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq 352(%rbx), %rsi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movq 368(%rbx), %rsi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
cmpl $0, 384(%rbx)
movl $.L.str.16, %r15d
movl $.L.str.15, %r14d
movl $.L.str.15, %esi
cmoveq %r15, %rsi
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 388(%rbx), %esi
movl $.L.str.17, %edi
xorl %eax, %eax
callq printf
cmpl $0, 392(%rbx)
cmoveq %r15, %r14
movl $.L.str.18, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12printDevProp20hipDeviceProp_tR0600, .Lfunc_end0-_Z12printDevProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr, %edi
callq puts@PLT
movl 1476(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 1476(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 1480(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.21, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep
callq _Z12printDevProp20hipDeviceProp_tR0600
incl %ebp
cmpl 1476(%rsp), %ebp
jl .LBB1_2
.LBB1_3: # %._crit_edge
xorl %eax, %eax
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Major revision number: %d\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Minor revision number: %d\n"
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Total global memory: %lu\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total shared memory per block: %lu\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Total registers per block: %d\n"
.size .L.str.5, 35
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Warp size: %d\n"
.size .L.str.6, 35
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum memory pitch: %lu\n"
.size .L.str.7, 36
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Maximum threads per block: %d\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Maximum dimension %d of block: %d\n"
.size .L.str.9, 36
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Maximum dimension %d of grid: %d\n"
.size .L.str.10, 36
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Clock rate: %d\n"
.size .L.str.11, 35
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total constant memory: %lu\n"
.size .L.str.12, 36
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Texture alignment: %lu\n"
.size .L.str.13, 36
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Concurrent copy and execution: %s\n"
.size .L.str.14, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Yes"
.size .L.str.15, 4
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "No"
.size .L.str.16, 3
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Number of multiprocessors: %d\n"
.size .L.str.17, 35
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Kernel execution timeout: %s\n"
.size .L.str.18, 35
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "There are %d CUDA devices.\n"
.size .L.str.20, 28
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz "\nCUDA Device #%d\n"
.size .L.str.21, 18
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CUDA Device Query..."
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void dkernel(char *arr, int arrlen) {
unsigned id = threadIdx.x;
if (id < arrlen) {
++arr[id];
}
}
int main() {
char cpuarr[] = "Gdkkn\x1fVnqkc-", *gpuarr;
cudaMalloc(&gpuarr, sizeof(char) * (1 + strlen(cpuarr)));
cudaMemcpy(gpuarr, cpuarr, sizeof(char) * (1 + strlen(cpuarr)), cudaMemcpyHostToDevice);
dkernel<<<1, 32>>>(gpuarr, strlen(cpuarr));
cudaThreadSynchronize(); // unnecessary.
cudaMemcpy(cpuarr, gpuarr, sizeof(char) * (1 + strlen(cpuarr)), cudaMemcpyDeviceToHost);
printf(cpuarr);
return 0;
} | code for sm_80
Function : _Z7dkernelPci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe20007f1e0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0060*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0080*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
__global__ void dkernel(char *arr, int arrlen) {
unsigned id = threadIdx.x;
if (id < arrlen) {
++arr[id];
}
}
int main() {
char cpuarr[] = "Gdkkn\x1fVnqkc-", *gpuarr;
cudaMalloc(&gpuarr, sizeof(char) * (1 + strlen(cpuarr)));
cudaMemcpy(gpuarr, cpuarr, sizeof(char) * (1 + strlen(cpuarr)), cudaMemcpyHostToDevice);
dkernel<<<1, 32>>>(gpuarr, strlen(cpuarr));
cudaThreadSynchronize(); // unnecessary.
cudaMemcpy(cpuarr, gpuarr, sizeof(char) * (1 + strlen(cpuarr)), cudaMemcpyDeviceToHost);
printf(cpuarr);
return 0;
} | .file "tmpxft_001aa205_00000000-6_hellocomm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7dkernelPciPci
.type _Z27__device_stub__Z7dkernelPciPci, @function
_Z27__device_stub__Z7dkernelPciPci:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7dkernelPci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7dkernelPciPci, .-_Z27__device_stub__Z7dkernelPciPci
.globl _Z7dkernelPci
.type _Z7dkernelPci, @function
_Z7dkernelPci:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7dkernelPciPci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelPci, .-_Z7dkernelPci
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $7950576751278253127, %rax
movq %rax, 43(%rsp)
movabsq $12775687067686431, %rax
movq %rax, 48(%rsp)
leaq 43(%rsp), %rbx
movq %rbx, %rdi
call strlen@PLT
leaq 1(%rax), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movq %rbx, %rdi
call strlen@PLT
leaq 1(%rax), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaThreadSynchronize@PLT
leaq 43(%rsp), %rbx
movq %rbx, %rdi
call strlen@PLT
leaq 1(%rax), %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq %rbx, %rdi
call strlen@PLT
movl %eax, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7dkernelPciPci
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelPci"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelPci(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
__global__ void dkernel(char *arr, int arrlen) {
unsigned id = threadIdx.x;
if (id < arrlen) {
++arr[id];
}
}
int main() {
char cpuarr[] = "Gdkkn\x1fVnqkc-", *gpuarr;
cudaMalloc(&gpuarr, sizeof(char) * (1 + strlen(cpuarr)));
cudaMemcpy(gpuarr, cpuarr, sizeof(char) * (1 + strlen(cpuarr)), cudaMemcpyHostToDevice);
dkernel<<<1, 32>>>(gpuarr, strlen(cpuarr));
cudaThreadSynchronize(); // unnecessary.
cudaMemcpy(cpuarr, gpuarr, sizeof(char) * (1 + strlen(cpuarr)), cudaMemcpyDeviceToHost);
printf(cpuarr);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void dkernel(char *arr, int arrlen) {
unsigned id = threadIdx.x;
if (id < arrlen) {
++arr[id];
}
}
int main() {
char cpuarr[] = "Gdkkn\x1fVnqkc-", *gpuarr;
hipMalloc(&gpuarr, sizeof(char) * (1 + strlen(cpuarr)));
hipMemcpy(gpuarr, cpuarr, sizeof(char) * (1 + strlen(cpuarr)), hipMemcpyHostToDevice);
dkernel<<<1, 32>>>(gpuarr, strlen(cpuarr));
hipDeviceSynchronize(); // unnecessary.
hipMemcpy(cpuarr, gpuarr, sizeof(char) * (1 + strlen(cpuarr)), hipMemcpyDeviceToHost);
printf(cpuarr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void dkernel(char *arr, int arrlen) {
unsigned id = threadIdx.x;
if (id < arrlen) {
++arr[id];
}
}
int main() {
char cpuarr[] = "Gdkkn\x1fVnqkc-", *gpuarr;
hipMalloc(&gpuarr, sizeof(char) * (1 + strlen(cpuarr)));
hipMemcpy(gpuarr, cpuarr, sizeof(char) * (1 + strlen(cpuarr)), hipMemcpyHostToDevice);
dkernel<<<1, 32>>>(gpuarr, strlen(cpuarr));
hipDeviceSynchronize(); // unnecessary.
hipMemcpy(cpuarr, gpuarr, sizeof(char) * (1 + strlen(cpuarr)), hipMemcpyDeviceToHost);
printf(cpuarr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7dkernelPci
.globl _Z7dkernelPci
.p2align 8
.type _Z7dkernelPci,@function
_Z7dkernelPci:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, 1
global_store_b8 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7dkernelPci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7dkernelPci, .Lfunc_end0-_Z7dkernelPci
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7dkernelPci
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z7dkernelPci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void dkernel(char *arr, int arrlen) {
unsigned id = threadIdx.x;
if (id < arrlen) {
++arr[id];
}
}
int main() {
char cpuarr[] = "Gdkkn\x1fVnqkc-", *gpuarr;
hipMalloc(&gpuarr, sizeof(char) * (1 + strlen(cpuarr)));
hipMemcpy(gpuarr, cpuarr, sizeof(char) * (1 + strlen(cpuarr)), hipMemcpyHostToDevice);
dkernel<<<1, 32>>>(gpuarr, strlen(cpuarr));
hipDeviceSynchronize(); // unnecessary.
hipMemcpy(cpuarr, gpuarr, sizeof(char) * (1 + strlen(cpuarr)), hipMemcpyDeviceToHost);
printf(cpuarr);
return 0;
} | .text
.file "hellocomm.hip"
.globl _Z22__device_stub__dkernelPci # -- Begin function _Z22__device_stub__dkernelPci
.p2align 4, 0x90
.type _Z22__device_stub__dkernelPci,@function
_Z22__device_stub__dkernelPci: # @_Z22__device_stub__dkernelPci
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7dkernelPci, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelPci, .Lfunc_end0-_Z22__device_stub__dkernelPci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $7950576751278253127, %rax # imm = 0x6E561F6E6B6B6447
movq %rax, 27(%rsp)
movl $761490289, 35(%rsp) # imm = 0x2D636B71
movb $0, 39(%rsp)
leaq 27(%rsp), %rbx
movq %rbx, %rdi
callq strlen
leaq 1(%rax), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %r14
movq %rbx, %rdi
callq strlen
leaq 1(%rax), %rdx
movq %r14, %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rbx
leaq 27(%rsp), %rdi
callq strlen
movq %rbx, 88(%rsp)
movl %eax, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7dkernelPci, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rbx
leaq 27(%rsp), %r14
movq %r14, %rdi
callq strlen
leaq 1(%rax), %rdx
movq %r14, %rdi
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelPci, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelPci,@object # @_Z7dkernelPci
.section .rodata,"a",@progbits
.globl _Z7dkernelPci
.p2align 3, 0x0
_Z7dkernelPci:
.quad _Z22__device_stub__dkernelPci
.size _Z7dkernelPci, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7dkernelPci"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelPci
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelPci
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7dkernelPci
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe20007f1e0ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0060*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.U8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1100 */
/*0080*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7dkernelPci
.globl _Z7dkernelPci
.p2align 8
.type _Z7dkernelPci,@function
_Z7dkernelPci:
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
global_load_u8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u16 v1, v1, 1
global_store_b8 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7dkernelPci
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7dkernelPci, .Lfunc_end0-_Z7dkernelPci
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7dkernelPci
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z7dkernelPci.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aa205_00000000-6_hellocomm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7dkernelPciPci
.type _Z27__device_stub__Z7dkernelPciPci, @function
_Z27__device_stub__Z7dkernelPciPci:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7dkernelPci(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7dkernelPciPci, .-_Z27__device_stub__Z7dkernelPciPci
.globl _Z7dkernelPci
.type _Z7dkernelPci, @function
_Z7dkernelPci:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7dkernelPciPci
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7dkernelPci, .-_Z7dkernelPci
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $7950576751278253127, %rax
movq %rax, 43(%rsp)
movabsq $12775687067686431, %rax
movq %rax, 48(%rsp)
leaq 43(%rsp), %rbx
movq %rbx, %rdi
call strlen@PLT
leaq 1(%rax), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movq %rbx, %rdi
call strlen@PLT
leaq 1(%rax), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaThreadSynchronize@PLT
leaq 43(%rsp), %rbx
movq %rbx, %rdi
call strlen@PLT
leaq 1(%rax), %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq %rbx, %rdi
call strlen@PLT
movl %eax, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7dkernelPciPci
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7dkernelPci"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7dkernelPci(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hellocomm.hip"
.globl _Z22__device_stub__dkernelPci # -- Begin function _Z22__device_stub__dkernelPci
.p2align 4, 0x90
.type _Z22__device_stub__dkernelPci,@function
_Z22__device_stub__dkernelPci: # @_Z22__device_stub__dkernelPci
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7dkernelPci, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__dkernelPci, .Lfunc_end0-_Z22__device_stub__dkernelPci
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $7950576751278253127, %rax # imm = 0x6E561F6E6B6B6447
movq %rax, 27(%rsp)
movl $761490289, 35(%rsp) # imm = 0x2D636B71
movb $0, 39(%rsp)
leaq 27(%rsp), %rbx
movq %rbx, %rdi
callq strlen
leaq 1(%rax), %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 8(%rsp), %r14
movq %rbx, %rdi
callq strlen
leaq 1(%rax), %rdx
movq %r14, %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rbx
leaq 27(%rsp), %rdi
callq strlen
movq %rbx, 88(%rsp)
movl %eax, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7dkernelPci, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rbx
leaq 27(%rsp), %r14
movq %r14, %rdi
callq strlen
leaq 1(%rax), %rdx
movq %r14, %rdi
movq %rbx, %rsi
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7dkernelPci, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7dkernelPci,@object # @_Z7dkernelPci
.section .rodata,"a",@progbits
.globl _Z7dkernelPci
.p2align 3, 0x0
_Z7dkernelPci:
.quad _Z22__device_stub__dkernelPci
.size _Z7dkernelPci, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7dkernelPci"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__dkernelPci
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7dkernelPci
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*** Original Question : https://stackoverflow.com/questions/13215614/
I am new to CUDA. I am trying to parallelize the following code. Right now it's sitting on kernel but is not using threads at all, thus slow. I tried to use this answer but to no avail so far.
The kernel is supposed to generate first n prime numbers, put them into device_primes array and this array is later accessed from host. The code is correct and works fine in serial version but I need to speed it up, perhaps with use of shared memory.
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
//int i = blockIdx.x * blockDim.x + threadIdx.x;
//int j = blockIdx.y * blockDim.y + threadIdx.y;
int counter = 0;
int c = 0;
for (int num = 2; counter < n; num++)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
}
}
My current, preliminary, and definitely wrong attempt to parallelize this looks like the following:
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int num = i + 2;
int c = j + 2;
int counter = 0;
if ((counter >= n) || (c > num - 1))
{
return;
}
if (num % c == 0) //not prime
{
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
num++;
c++;
}
But this code populates the array with data that does not make sense. In addition, many values are zeroes. Thanks in advance for any help, it's appreciated.
***/
__global__ void getPrimes(int *device_primes,int n)
{
int c = 0;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int num = thread_id;
if (thread_id == 0) device_primes[0] = 1;
__syncthreads();
while(device_primes[0] < n)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
int pos = atomicAdd(&device_primes[0],1);
device_primes[pos] = num;
}
num += blockDim.x * gridDim.x; // Next number for this thread
}
} | code for sm_80
Function : _Z9getPrimesPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc600078e00ff */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff058424 */
/* 0x000fca00078e00ff */
/*0090*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x004fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06270 */
/*0100*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0110*/ BSSY B0, 0x320 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0120*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff077435 */
/* 0x000fd400000001ff */
/*0130*/ @!P0 BRA 0x310 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*0160*/ IABS R10, R0.reuse ; /* 0x00000000000a7213 */
/* 0x080fe40000000000 */
/*0170*/ IABS R11, R0 ; /* 0x00000000000b7213 */
/* 0x000fe40000000000 */
/*0180*/ IABS R12, R7.reuse ; /* 0x00000007000c7213 */
/* 0x080fe40000000000 */
/*0190*/ IABS R13, R7 ; /* 0x00000007000d7213 */
/* 0x000fe40000000000 */
/*01a0*/ I2F.RP R8, R12 ; /* 0x0000000c00087306 */
/* 0x000e240000209400 */
/*01b0*/ IADD3 R14, RZ, -R13, RZ ; /* 0x8000000dff0e7210 */
/* 0x000fcc0007ffe0ff */
/*01c0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*01d0*/ IADD3 R4, R8, 0xffffffe, RZ ; /* 0x0ffffffe08047810 */
/* 0x001fcc0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0200*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*0210*/ IMAD R9, R9, R12, RZ ; /* 0x0000000c09097224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0230*/ IMAD.HI.U32 R5, R5, R10, RZ ; /* 0x0000000a05057227 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD R5, R5, R14, R11 ; /* 0x0000000e05057224 */
/* 0x000fca00078e020b */
/*0250*/ ISETP.GT.U32.AND P1, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a0c */
/*0270*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f25270 */
/*0280*/ ISETP.GT.U32.AND P2, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fda0003f44070 */
/*0290*/ @!P2 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x000000010505a824 */
/* 0x000fc800078e0a0c */
/*02a0*/ @!P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff058224 */
/* 0x000fe200078e0a05 */
/*02b0*/ @!P1 LOP3.LUT R5, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff059212 */
/* 0x000fc800078e33ff */
/*02c0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*02d0*/ @!P1 BRA 0x310 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*02f0*/ ISETP.GE.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26270 */
/*0300*/ @!P1 BRA 0x180 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.NE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f05270 */
/*0330*/ BSSY B0, 0x450 ; /* 0x0000011000007945 */
/* 0x000fd80003800000 */
/*0340*/ @P0 BRA 0x440 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*0350*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000e220000000000 */
/*0360*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0370*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0380*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x000e620008000000 */
/*0390*/ ISETP.EQ.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x001fda0003f02070 */
/*03a0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R7, [R2.64], R7 ; /* 0x00000007020709a8 */
/* 0x002ea800081ee1c4 */
/*03b0*/ S2R R5, SR_LTMASK ; /* 0x0000000000057919 */
/* 0x000e240000003900 */
/*03c0*/ LOP3.LUT R9, R5, UR6, RZ, 0xc0, !PT ; /* 0x0000000605097c12 */
/* 0x001fe4000f8ec0ff */
/*03d0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fc80000000f00 */
/*03e0*/ POPC R9, R9 ; /* 0x0000000900097309 */
/* 0x000e220000000000 */
/*03f0*/ SHFL.IDX PT, R4, R7, R8, 0x1f ; /* 0x00001f0807047589 */
/* 0x004e2400000e0000 */
/*0400*/ IMAD.IADD R4, R4, 0x1, R9 ; /* 0x0000000104047824 */
/* 0x001fc800078e0209 */
/*0410*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0420*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000164000c1e1900 */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x020fe20003f06270 */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x001fc800078e00ff */
/*0470*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fd000078e0200 */
/*0480*/ @!P0 BRA 0xf0 ; /* 0xfffffc6000008947 */
/* 0x000fea000383ffff */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*** Original Question : https://stackoverflow.com/questions/13215614/
I am new to CUDA. I am trying to parallelize the following code. Right now it's sitting on kernel but is not using threads at all, thus slow. I tried to use this answer but to no avail so far.
The kernel is supposed to generate first n prime numbers, put them into device_primes array and this array is later accessed from host. The code is correct and works fine in serial version but I need to speed it up, perhaps with use of shared memory.
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
//int i = blockIdx.x * blockDim.x + threadIdx.x;
//int j = blockIdx.y * blockDim.y + threadIdx.y;
int counter = 0;
int c = 0;
for (int num = 2; counter < n; num++)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
}
}
My current, preliminary, and definitely wrong attempt to parallelize this looks like the following:
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int num = i + 2;
int c = j + 2;
int counter = 0;
if ((counter >= n) || (c > num - 1))
{
return;
}
if (num % c == 0) //not prime
{
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
num++;
c++;
}
But this code populates the array with data that does not make sense. In addition, many values are zeroes. Thanks in advance for any help, it's appreciated.
***/
__global__ void getPrimes(int *device_primes,int n)
{
int c = 0;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int num = thread_id;
if (thread_id == 0) device_primes[0] = 1;
__syncthreads();
while(device_primes[0] < n)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
int pos = atomicAdd(&device_primes[0],1);
device_primes[pos] = num;
}
num += blockDim.x * gridDim.x; // Next number for this thread
}
} | .file "tmpxft_0017f281_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9getPrimesPiiPii
.type _Z29__device_stub__Z9getPrimesPiiPii, @function
_Z29__device_stub__Z9getPrimesPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9getPrimesPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9getPrimesPiiPii, .-_Z29__device_stub__Z9getPrimesPiiPii
.globl _Z9getPrimesPii
.type _Z9getPrimesPii, @function
_Z9getPrimesPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9getPrimesPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9getPrimesPii, .-_Z9getPrimesPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9getPrimesPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9getPrimesPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*** Original Question : https://stackoverflow.com/questions/13215614/
I am new to CUDA. I am trying to parallelize the following code. Right now it's sitting on kernel but is not using threads at all, thus slow. I tried to use this answer but to no avail so far.
The kernel is supposed to generate first n prime numbers, put them into device_primes array and this array is later accessed from host. The code is correct and works fine in serial version but I need to speed it up, perhaps with use of shared memory.
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
//int i = blockIdx.x * blockDim.x + threadIdx.x;
//int j = blockIdx.y * blockDim.y + threadIdx.y;
int counter = 0;
int c = 0;
for (int num = 2; counter < n; num++)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
}
}
My current, preliminary, and definitely wrong attempt to parallelize this looks like the following:
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int num = i + 2;
int c = j + 2;
int counter = 0;
if ((counter >= n) || (c > num - 1))
{
return;
}
if (num % c == 0) //not prime
{
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
num++;
c++;
}
But this code populates the array with data that does not make sense. In addition, many values are zeroes. Thanks in advance for any help, it's appreciated.
***/
__global__ void getPrimes(int *device_primes,int n)
{
int c = 0;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int num = thread_id;
if (thread_id == 0) device_primes[0] = 1;
__syncthreads();
while(device_primes[0] < n)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
int pos = atomicAdd(&device_primes[0],1);
device_primes[pos] = num;
}
num += blockDim.x * gridDim.x; // Next number for this thread
}
} | #include <hip/hip_runtime.h>
/*** Original Question : https://stackoverflow.com/questions/13215614/
I am new to CUDA. I am trying to parallelize the following code. Right now it's sitting on kernel but is not using threads at all, thus slow. I tried to use this answer but to no avail so far.
The kernel is supposed to generate first n prime numbers, put them into device_primes array and this array is later accessed from host. The code is correct and works fine in serial version but I need to speed it up, perhaps with use of shared memory.
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
//int i = blockIdx.x * blockDim.x + threadIdx.x;
//int j = blockIdx.y * blockDim.y + threadIdx.y;
int counter = 0;
int c = 0;
for (int num = 2; counter < n; num++)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
}
}
My current, preliminary, and definitely wrong attempt to parallelize this looks like the following:
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int num = i + 2;
int c = j + 2;
int counter = 0;
if ((counter >= n) || (c > num - 1))
{
return;
}
if (num % c == 0) //not prime
{
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
num++;
c++;
}
But this code populates the array with data that does not make sense. In addition, many values are zeroes. Thanks in advance for any help, it's appreciated.
***/
__global__ void getPrimes(int *device_primes,int n)
{
int c = 0;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int num = thread_id;
if (thread_id == 0) device_primes[0] = 1;
__syncthreads();
while(device_primes[0] < n)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
int pos = atomicAdd(&device_primes[0],1);
device_primes[pos] = num;
}
num += blockDim.x * gridDim.x; // Next number for this thread
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*** Original Question : https://stackoverflow.com/questions/13215614/
I am new to CUDA. I am trying to parallelize the following code. Right now it's sitting on kernel but is not using threads at all, thus slow. I tried to use this answer but to no avail so far.
The kernel is supposed to generate first n prime numbers, put them into device_primes array and this array is later accessed from host. The code is correct and works fine in serial version but I need to speed it up, perhaps with use of shared memory.
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
//int i = blockIdx.x * blockDim.x + threadIdx.x;
//int j = blockIdx.y * blockDim.y + threadIdx.y;
int counter = 0;
int c = 0;
for (int num = 2; counter < n; num++)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
}
}
My current, preliminary, and definitely wrong attempt to parallelize this looks like the following:
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int num = i + 2;
int c = j + 2;
int counter = 0;
if ((counter >= n) || (c > num - 1))
{
return;
}
if (num % c == 0) //not prime
{
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
num++;
c++;
}
But this code populates the array with data that does not make sense. In addition, many values are zeroes. Thanks in advance for any help, it's appreciated.
***/
__global__ void getPrimes(int *device_primes,int n)
{
int c = 0;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int num = thread_id;
if (thread_id == 0) device_primes[0] = 1;
__syncthreads();
while(device_primes[0] < n)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
int pos = atomicAdd(&device_primes[0],1);
device_primes[pos] = num;
}
num += blockDim.x * gridDim.x; // Next number for this thread
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9getPrimesPii
.globl _Z9getPrimesPii
.p2align 8
.type _Z9getPrimesPii,@function
_Z9getPrimesPii:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, 1
global_store_b32 v0, v2, s[2:3]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v0, 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_load_b32 s0, s[0:1], 0x8
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s0, v2
s_cbranch_vccnz .LBB0_15
s_mul_i32 s1, s4, s5
s_branch .LBB0_6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s5, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v2, v0, s[2:3]
v_add_nc_u32_e32 v1, s1, v1
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v2
s_cbranch_vccz .LBB0_15
.LBB0_6:
v_mov_b32_e32 v2, 2
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e32 2, v1
s_cbranch_execz .LBB0_12
s_mov_b32 s5, 2
s_mov_b32 s7, -2
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, exec_lo, s8
s_or_b32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_11
.LBB0_9:
v_cvt_f32_u32_e32 v2, s5
s_or_b32 s8, s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s7, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s5
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_mov_b32_e32 v2, s5
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_8
s_add_i32 s5, s5, 1
v_mov_b32_e32 v2, v1
v_cmp_ge_i32_e32 vcc_lo, s5, v1
s_and_not1_b32 s8, s8, exec_lo
s_add_i32 s7, s7, -1
s_and_b32 s10, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e64 v2, v1
s_cbranch_execz .LBB0_5
s_mov_b32 s6, exec_lo
s_mov_b32 s5, exec_lo
v_mbcnt_lo_u32_b32 v2, s6, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_4
s_bcnt1_i32_b32 s6, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s6
global_atomic_add_u32 v3, v0, v3, s[2:3] glc
s_branch .LBB0_4
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9getPrimesPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9getPrimesPii, .Lfunc_end0-_Z9getPrimesPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9getPrimesPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9getPrimesPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*** Original Question : https://stackoverflow.com/questions/13215614/
I am new to CUDA. I am trying to parallelize the following code. Right now it's sitting on kernel but is not using threads at all, thus slow. I tried to use this answer but to no avail so far.
The kernel is supposed to generate first n prime numbers, put them into device_primes array and this array is later accessed from host. The code is correct and works fine in serial version but I need to speed it up, perhaps with use of shared memory.
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
//int i = blockIdx.x * blockDim.x + threadIdx.x;
//int j = blockIdx.y * blockDim.y + threadIdx.y;
int counter = 0;
int c = 0;
for (int num = 2; counter < n; num++)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
}
}
My current, preliminary, and definitely wrong attempt to parallelize this looks like the following:
//CUDA kernel code
__global__ void generatePrimes(int* device_primes, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int num = i + 2;
int c = j + 2;
int counter = 0;
if ((counter >= n) || (c > num - 1))
{
return;
}
if (num % c == 0) //not prime
{
}
if (c == num) //prime
{
device_primes[counter] = num;
counter++;
}
num++;
c++;
}
But this code populates the array with data that does not make sense. In addition, many values are zeroes. Thanks in advance for any help, it's appreciated.
***/
__global__ void getPrimes(int *device_primes,int n)
{
int c = 0;
int thread_id = blockIdx.x * blockDim.x + threadIdx.x;
int num = thread_id;
if (thread_id == 0) device_primes[0] = 1;
__syncthreads();
while(device_primes[0] < n)
{
for (c = 2; c <= num - 1; c++)
{
if (num % c == 0) //not prime
{
break;
}
}
if (c == num) //prime
{
int pos = atomicAdd(&device_primes[0],1);
device_primes[pos] = num;
}
num += blockDim.x * gridDim.x; // Next number for this thread
}
} | .text
.file "kernel.hip"
.globl _Z24__device_stub__getPrimesPii # -- Begin function _Z24__device_stub__getPrimesPii
.p2align 4, 0x90
.type _Z24__device_stub__getPrimesPii,@function
_Z24__device_stub__getPrimesPii: # @_Z24__device_stub__getPrimesPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9getPrimesPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__getPrimesPii, .Lfunc_end0-_Z24__device_stub__getPrimesPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9getPrimesPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9getPrimesPii,@object # @_Z9getPrimesPii
.section .rodata,"a",@progbits
.globl _Z9getPrimesPii
.p2align 3, 0x0
_Z9getPrimesPii:
.quad _Z24__device_stub__getPrimesPii
.size _Z9getPrimesPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9getPrimesPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__getPrimesPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9getPrimesPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9getPrimesPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fc600078e00ff */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff058424 */
/* 0x000fca00078e00ff */
/*0090*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e8000c101904 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x004fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0004 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06270 */
/*0100*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0110*/ BSSY B0, 0x320 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0120*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff077435 */
/* 0x000fd400000001ff */
/*0130*/ @!P0 BRA 0x310 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe200078e00ff */
/*0160*/ IABS R10, R0.reuse ; /* 0x00000000000a7213 */
/* 0x080fe40000000000 */
/*0170*/ IABS R11, R0 ; /* 0x00000000000b7213 */
/* 0x000fe40000000000 */
/*0180*/ IABS R12, R7.reuse ; /* 0x00000007000c7213 */
/* 0x080fe40000000000 */
/*0190*/ IABS R13, R7 ; /* 0x00000007000d7213 */
/* 0x000fe40000000000 */
/*01a0*/ I2F.RP R8, R12 ; /* 0x0000000c00087306 */
/* 0x000e240000209400 */
/*01b0*/ IADD3 R14, RZ, -R13, RZ ; /* 0x8000000dff0e7210 */
/* 0x000fcc0007ffe0ff */
/*01c0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*01d0*/ IADD3 R4, R8, 0xffffffe, RZ ; /* 0x0ffffffe08047810 */
/* 0x001fcc0007ffe0ff */
/*01e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0200*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*0210*/ IMAD R9, R9, R12, RZ ; /* 0x0000000c09097224 */
/* 0x000fc800078e02ff */
/*0220*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0230*/ IMAD.HI.U32 R5, R5, R10, RZ ; /* 0x0000000a05057227 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD R5, R5, R14, R11 ; /* 0x0000000e05057224 */
/* 0x000fca00078e020b */
/*0250*/ ISETP.GT.U32.AND P1, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a0c */
/*0270*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f25270 */
/*0280*/ ISETP.GT.U32.AND P2, PT, R12, R5, PT ; /* 0x000000050c00720c */
/* 0x000fda0003f44070 */
/*0290*/ @!P2 IMAD.IADD R5, R5, 0x1, -R12 ; /* 0x000000010505a824 */
/* 0x000fc800078e0a0c */
/*02a0*/ @!P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff058224 */
/* 0x000fe200078e0a05 */
/*02b0*/ @!P1 LOP3.LUT R5, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff059212 */
/* 0x000fc800078e33ff */
/*02c0*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*02d0*/ @!P1 BRA 0x310 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*02f0*/ ISETP.GE.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26270 */
/*0300*/ @!P1 BRA 0x180 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ ISETP.NE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f05270 */
/*0330*/ BSSY B0, 0x450 ; /* 0x0000011000007945 */
/* 0x000fd80003800000 */
/*0340*/ @P0 BRA 0x440 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*0350*/ S2R R5, SR_LANEID ; /* 0x0000000000057919 */
/* 0x000e220000000000 */
/*0360*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe400038e0100 */
/*0370*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0380*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x000e620008000000 */
/*0390*/ ISETP.EQ.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x001fda0003f02070 */
/*03a0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R7, [R2.64], R7 ; /* 0x00000007020709a8 */
/* 0x002ea800081ee1c4 */
/*03b0*/ S2R R5, SR_LTMASK ; /* 0x0000000000057919 */
/* 0x000e240000003900 */
/*03c0*/ LOP3.LUT R9, R5, UR6, RZ, 0xc0, !PT ; /* 0x0000000605097c12 */
/* 0x001fe4000f8ec0ff */
/*03d0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fc80000000f00 */
/*03e0*/ POPC R9, R9 ; /* 0x0000000900097309 */
/* 0x000e220000000000 */
/*03f0*/ SHFL.IDX PT, R4, R7, R8, 0x1f ; /* 0x00001f0807047589 */
/* 0x004e2400000e0000 */
/*0400*/ IMAD.IADD R4, R4, 0x1, R9 ; /* 0x0000000104047824 */
/* 0x001fc800078e0209 */
/*0410*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0420*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000164000c1e1900 */
/*0440*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0450*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x020fe20003f06270 */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x001fc800078e00ff */
/*0470*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fd000078e0200 */
/*0480*/ @!P0 BRA 0xf0 ; /* 0xfffffc6000008947 */
/* 0x000fea000383ffff */
/*0490*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04a0*/ BRA 0x4a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9getPrimesPii
.globl _Z9getPrimesPii
.p2align 8
.type _Z9getPrimesPii,@function
_Z9getPrimesPii:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x10
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, 1
global_store_b32 v0, v2, s[2:3]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_mov_b32_e32 v0, 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_load_b32 s0, s[0:1], 0x8
global_load_b32 v2, v0, s[2:3]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s0, v2
s_cbranch_vccnz .LBB0_15
s_mul_i32 s1, s4, s5
s_branch .LBB0_6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s5, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v1, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
global_load_b32 v2, v0, s[2:3]
v_add_nc_u32_e32 v1, s1, v1
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s0, v2
s_cbranch_vccz .LBB0_15
.LBB0_6:
v_mov_b32_e32 v2, 2
s_mov_b32 s4, exec_lo
v_cmpx_lt_i32_e32 2, v1
s_cbranch_execz .LBB0_12
s_mov_b32 s5, 2
s_mov_b32 s7, -2
s_mov_b32 s6, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, exec_lo, s8
s_or_b32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_11
.LBB0_9:
v_cvt_f32_u32_e32 v2, s5
s_or_b32 s8, s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s7, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s5
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s7, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_mov_b32_e32 v2, s5
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_8
s_add_i32 s5, s5, 1
v_mov_b32_e32 v2, v1
v_cmp_ge_i32_e32 vcc_lo, s5, v1
s_and_not1_b32 s8, s8, exec_lo
s_add_i32 s7, s7, -1
s_and_b32 s10, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e64 v2, v1
s_cbranch_execz .LBB0_5
s_mov_b32 s6, exec_lo
s_mov_b32 s5, exec_lo
v_mbcnt_lo_u32_b32 v2, s6, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_4
s_bcnt1_i32_b32 s6, s6
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s6
global_atomic_add_u32 v3, v0, v3, s[2:3] glc
s_branch .LBB0_4
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9getPrimesPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9getPrimesPii, .Lfunc_end0-_Z9getPrimesPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9getPrimesPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9getPrimesPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017f281_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9getPrimesPiiPii
.type _Z29__device_stub__Z9getPrimesPiiPii, @function
_Z29__device_stub__Z9getPrimesPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9getPrimesPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9getPrimesPiiPii, .-_Z29__device_stub__Z9getPrimesPiiPii
.globl _Z9getPrimesPii
.type _Z9getPrimesPii, @function
_Z9getPrimesPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9getPrimesPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9getPrimesPii, .-_Z9getPrimesPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9getPrimesPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9getPrimesPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__getPrimesPii # -- Begin function _Z24__device_stub__getPrimesPii
.p2align 4, 0x90
.type _Z24__device_stub__getPrimesPii,@function
_Z24__device_stub__getPrimesPii: # @_Z24__device_stub__getPrimesPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9getPrimesPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__getPrimesPii, .Lfunc_end0-_Z24__device_stub__getPrimesPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9getPrimesPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9getPrimesPii,@object # @_Z9getPrimesPii
.section .rodata,"a",@progbits
.globl _Z9getPrimesPii
.p2align 3, 0x0
_Z9getPrimesPii:
.quad _Z24__device_stub__getPrimesPii
.size _Z9getPrimesPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9getPrimesPii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__getPrimesPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9getPrimesPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void scan_kernel(unsigned int* d_bins, int size) {
int mid = threadIdx.x + blockDim.x * blockIdx.x;
if (mid >= size) return;
for (int s = 1; s <= size; s *= 2) {
int spot = mid - s;
unsigned int val = 0;
if (spot >= 0) val = d_bins[spot];
__syncthreads();
if (spot >= 0) d_bins[mid] += val;
__syncthreads();
}
} | code for sm_80
Function : _Z11scan_kernelPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fce00078e0203 */
/*00c0*/ IMAD.IADD R4, R0, 0x1, -R7 ; /* 0x0000000100047824 */
/* 0x000fe400078e0a07 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*00e0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 MOV R5, 0x4 ; /* 0x0000000400050802 */
/* 0x000fca0000000f00 */
/*0100*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004040625 */
/* 0x000fca00078e0205 */
/*0110*/ @P0 LDG.E R6, [R4.64] ; /* 0x0000000404060981 */
/* 0x000ea8000c1e1900 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 LDG.E R9, [R2.64] ; /* 0x0000000402090981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0150*/ @P0 IADD3 R9, R9, R6, RZ ; /* 0x0000000609090210 */
/* 0x004fca0007ffe0ff */
/*0160*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0001e8000c101904 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f04270 */
/*0190*/ @!P0 BRA 0xc0 ; /* 0xffffff2000008947 */
/* 0x001fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void scan_kernel(unsigned int* d_bins, int size) {
int mid = threadIdx.x + blockDim.x * blockIdx.x;
if (mid >= size) return;
for (int s = 1; s <= size; s *= 2) {
int spot = mid - s;
unsigned int val = 0;
if (spot >= 0) val = d_bins[spot];
__syncthreads();
if (spot >= 0) d_bins[mid] += val;
__syncthreads();
}
} | .file "tmpxft_0002eb4d_00000000-6_scan_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11scan_kernelPjiPji
.type _Z32__device_stub__Z11scan_kernelPjiPji, @function
_Z32__device_stub__Z11scan_kernelPjiPji:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11scan_kernelPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11scan_kernelPjiPji, .-_Z32__device_stub__Z11scan_kernelPjiPji
.globl _Z11scan_kernelPji
.type _Z11scan_kernelPji, @function
_Z11scan_kernelPji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11scan_kernelPjiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11scan_kernelPji, .-_Z11scan_kernelPji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11scan_kernelPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_kernelPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void scan_kernel(unsigned int* d_bins, int size) {
int mid = threadIdx.x + blockDim.x * blockIdx.x;
if (mid >= size) return;
for (int s = 1; s <= size; s *= 2) {
int spot = mid - s;
unsigned int val = 0;
if (spot >= 0) val = d_bins[spot];
__syncthreads();
if (spot >= 0) d_bins[mid] += val;
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan_kernel(unsigned int* d_bins, int size) {
int mid = threadIdx.x + blockDim.x * blockIdx.x;
if (mid >= size) return;
for (int s = 1; s <= size; s *= 2) {
int spot = mid - s;
unsigned int val = 0;
if (spot >= 0) val = d_bins[spot];
__syncthreads();
if (spot >= 0) d_bins[mid] += val;
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan_kernel(unsigned int* d_bins, int size) {
int mid = threadIdx.x + blockDim.x * blockIdx.x;
if (mid >= size) return;
for (int s = 1; s <= size; s *= 2) {
int spot = mid - s;
unsigned int val = 0;
if (spot >= 0) val = d_bins[spot];
__syncthreads();
if (spot >= 0) d_bins[mid] += val;
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11scan_kernelPji
.globl _Z11scan_kernelPji
.p2align 8
.type _Z11scan_kernelPji,@function
_Z11scan_kernelPji:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 0
s_mov_b32 s1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s1, s1, 1
s_waitcnt_vscnt null, 0x0
s_cmp_le_i32 s1, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_subrev_nc_u32_e32 v4, s1, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v4
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s2, v6
v_add_co_ci_u32_e64 v7, s0, s3, v7, s0
global_load_b32 v0, v[6:7], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_kernelPji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11scan_kernelPji, .Lfunc_end0-_Z11scan_kernelPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_kernelPji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11scan_kernelPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void scan_kernel(unsigned int* d_bins, int size) {
int mid = threadIdx.x + blockDim.x * blockIdx.x;
if (mid >= size) return;
for (int s = 1; s <= size; s *= 2) {
int spot = mid - s;
unsigned int val = 0;
if (spot >= 0) val = d_bins[spot];
__syncthreads();
if (spot >= 0) d_bins[mid] += val;
__syncthreads();
}
} | .text
.file "scan_kernel.hip"
.globl _Z26__device_stub__scan_kernelPji # -- Begin function _Z26__device_stub__scan_kernelPji
.p2align 4, 0x90
.type _Z26__device_stub__scan_kernelPji,@function
_Z26__device_stub__scan_kernelPji: # @_Z26__device_stub__scan_kernelPji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11scan_kernelPji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__scan_kernelPji, .Lfunc_end0-_Z26__device_stub__scan_kernelPji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_kernelPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11scan_kernelPji,@object # @_Z11scan_kernelPji
.section .rodata,"a",@progbits
.globl _Z11scan_kernelPji
.p2align 3, 0x0
_Z11scan_kernelPji:
.quad _Z26__device_stub__scan_kernelPji
.size _Z11scan_kernelPji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11scan_kernelPji"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__scan_kernelPji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11scan_kernelPji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11scan_kernelPji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fce00078e0203 */
/*00c0*/ IMAD.IADD R4, R0, 0x1, -R7 ; /* 0x0000000100047824 */
/* 0x000fe400078e0a07 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*00e0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 MOV R5, 0x4 ; /* 0x0000000400050802 */
/* 0x000fca0000000f00 */
/*0100*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004040625 */
/* 0x000fca00078e0205 */
/*0110*/ @P0 LDG.E R6, [R4.64] ; /* 0x0000000404060981 */
/* 0x000ea8000c1e1900 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 LDG.E R9, [R2.64] ; /* 0x0000000402090981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0150*/ @P0 IADD3 R9, R9, R6, RZ ; /* 0x0000000609090210 */
/* 0x004fca0007ffe0ff */
/*0160*/ @P0 STG.E [R2.64], R9 ; /* 0x0000000902000986 */
/* 0x0001e8000c101904 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x168], PT ; /* 0x00005a0007007a0c */
/* 0x000fda0003f04270 */
/*0190*/ @!P0 BRA 0xc0 ; /* 0xffffff2000008947 */
/* 0x001fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11scan_kernelPji
.globl _Z11scan_kernelPji
.p2align 8
.type _Z11scan_kernelPji,@function
_Z11scan_kernelPji:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, 0
s_mov_b32 s1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s1, s1, 1
s_waitcnt_vscnt null, 0x0
s_cmp_le_i32 s1, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_subrev_nc_u32_e32 v4, s1, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_lt_i32_e32 vcc_lo, -1, v4
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s2, v6
v_add_co_ci_u32_e64 v7, s0, s3, v7, s0
global_load_b32 v0, v[6:7], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_2
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_kernelPji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11scan_kernelPji, .Lfunc_end0-_Z11scan_kernelPji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_kernelPji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11scan_kernelPji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002eb4d_00000000-6_scan_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11scan_kernelPjiPji
.type _Z32__device_stub__Z11scan_kernelPjiPji, @function
_Z32__device_stub__Z11scan_kernelPjiPji:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11scan_kernelPji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11scan_kernelPjiPji, .-_Z32__device_stub__Z11scan_kernelPjiPji
.globl _Z11scan_kernelPji
.type _Z11scan_kernelPji, @function
_Z11scan_kernelPji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11scan_kernelPjiPji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11scan_kernelPji, .-_Z11scan_kernelPji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11scan_kernelPji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_kernelPji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan_kernel.hip"
.globl _Z26__device_stub__scan_kernelPji # -- Begin function _Z26__device_stub__scan_kernelPji
.p2align 4, 0x90
.type _Z26__device_stub__scan_kernelPji,@function
_Z26__device_stub__scan_kernelPji: # @_Z26__device_stub__scan_kernelPji
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11scan_kernelPji, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__scan_kernelPji, .Lfunc_end0-_Z26__device_stub__scan_kernelPji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_kernelPji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11scan_kernelPji,@object # @_Z11scan_kernelPji
.section .rodata,"a",@progbits
.globl _Z11scan_kernelPji
.p2align 3, 0x0
_Z11scan_kernelPji:
.quad _Z26__device_stub__scan_kernelPji
.size _Z11scan_kernelPji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11scan_kernelPji"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__scan_kernelPji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11scan_kernelPji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kern_ConvertBuffer(short* agreement, float* output, int size )
{
int idx = CUDASTDOFFSET;
float locAgreement = (float) agreement[idx];
if( idx < size )
{
output[idx] = locAgreement;
}
} | code for sm_80
Function : _Z18kern_ConvertBufferPsPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00d0*/ LDG.E.U16 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1500 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*0100*/ I2F.S16 R7, R2 ; /* 0x0000000200077306 */
/* 0x004e280000101400 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kern_ConvertBuffer(short* agreement, float* output, int size )
{
int idx = CUDASTDOFFSET;
float locAgreement = (float) agreement[idx];
if( idx < size )
{
output[idx] = locAgreement;
}
} | .file "tmpxft_00155b6d_00000000-6_kern_ConvertBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi
.type _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi, @function
_Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kern_ConvertBufferPsPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi, .-_Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi
.globl _Z18kern_ConvertBufferPsPfi
.type _Z18kern_ConvertBufferPsPfi, @function
_Z18kern_ConvertBufferPsPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kern_ConvertBufferPsPfi, .-_Z18kern_ConvertBufferPsPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kern_ConvertBufferPsPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kern_ConvertBufferPsPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kern_ConvertBuffer(short* agreement, float* output, int size )
{
int idx = CUDASTDOFFSET;
float locAgreement = (float) agreement[idx];
if( idx < size )
{
output[idx] = locAgreement;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_ConvertBuffer(short* agreement, float* output, int size )
{
int idx = CUDASTDOFFSET;
float locAgreement = (float) agreement[idx];
if( idx < size )
{
output[idx] = locAgreement;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_ConvertBuffer(short* agreement, float* output, int size )
{
int idx = CUDASTDOFFSET;
float locAgreement = (float) agreement[idx];
if( idx < size )
{
output[idx] = locAgreement;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kern_ConvertBufferPsPfi
.globl _Z18kern_ConvertBufferPsPfi
.p2align 8
.type _Z18kern_ConvertBufferPsPfi,@function
_Z18kern_ConvertBufferPsPfi:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s4, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 1, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_i16 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kern_ConvertBufferPsPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kern_ConvertBufferPsPfi, .Lfunc_end0-_Z18kern_ConvertBufferPsPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kern_ConvertBufferPsPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kern_ConvertBufferPsPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kern_ConvertBuffer(short* agreement, float* output, int size )
{
int idx = CUDASTDOFFSET;
float locAgreement = (float) agreement[idx];
if( idx < size )
{
output[idx] = locAgreement;
}
} | .text
.file "kern_ConvertBuffer.hip"
.globl _Z33__device_stub__kern_ConvertBufferPsPfi # -- Begin function _Z33__device_stub__kern_ConvertBufferPsPfi
.p2align 4, 0x90
.type _Z33__device_stub__kern_ConvertBufferPsPfi,@function
_Z33__device_stub__kern_ConvertBufferPsPfi: # @_Z33__device_stub__kern_ConvertBufferPsPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kern_ConvertBufferPsPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__kern_ConvertBufferPsPfi, .Lfunc_end0-_Z33__device_stub__kern_ConvertBufferPsPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kern_ConvertBufferPsPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kern_ConvertBufferPsPfi,@object # @_Z18kern_ConvertBufferPsPfi
.section .rodata,"a",@progbits
.globl _Z18kern_ConvertBufferPsPfi
.p2align 3, 0x0
_Z18kern_ConvertBufferPsPfi:
.quad _Z33__device_stub__kern_ConvertBufferPsPfi
.size _Z18kern_ConvertBufferPsPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kern_ConvertBufferPsPfi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kern_ConvertBufferPsPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kern_ConvertBufferPsPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kern_ConvertBufferPsPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e280000002700 */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x10], R3 ; /* 0x0000040000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00d0*/ LDG.E.U16 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1500 */
/*00e0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*00f0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e0205 */
/*0100*/ I2F.S16 R7, R2 ; /* 0x0000000200077306 */
/* 0x004e280000101400 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kern_ConvertBufferPsPfi
.globl _Z18kern_ConvertBufferPsPfi
.p2align 8
.type _Z18kern_ConvertBufferPsPfi,@function
_Z18kern_ConvertBufferPsPfi:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s4, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s5, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 1, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_i16 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kern_ConvertBufferPsPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kern_ConvertBufferPsPfi, .Lfunc_end0-_Z18kern_ConvertBufferPsPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kern_ConvertBufferPsPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kern_ConvertBufferPsPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00155b6d_00000000-6_kern_ConvertBuffer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi
.type _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi, @function
_Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kern_ConvertBufferPsPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi, .-_Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi
.globl _Z18kern_ConvertBufferPsPfi
.type _Z18kern_ConvertBufferPsPfi, @function
_Z18kern_ConvertBufferPsPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18kern_ConvertBufferPsPfiPsPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kern_ConvertBufferPsPfi, .-_Z18kern_ConvertBufferPsPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kern_ConvertBufferPsPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kern_ConvertBufferPsPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kern_ConvertBuffer.hip"
.globl _Z33__device_stub__kern_ConvertBufferPsPfi # -- Begin function _Z33__device_stub__kern_ConvertBufferPsPfi
.p2align 4, 0x90
.type _Z33__device_stub__kern_ConvertBufferPsPfi,@function
_Z33__device_stub__kern_ConvertBufferPsPfi: # @_Z33__device_stub__kern_ConvertBufferPsPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kern_ConvertBufferPsPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__kern_ConvertBufferPsPfi, .Lfunc_end0-_Z33__device_stub__kern_ConvertBufferPsPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kern_ConvertBufferPsPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kern_ConvertBufferPsPfi,@object # @_Z18kern_ConvertBufferPsPfi
.section .rodata,"a",@progbits
.globl _Z18kern_ConvertBufferPsPfi
.p2align 3, 0x0
_Z18kern_ConvertBufferPsPfi:
.quad _Z33__device_stub__kern_ConvertBufferPsPfi
.size _Z18kern_ConvertBufferPsPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kern_ConvertBufferPsPfi"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kern_ConvertBufferPsPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kern_ConvertBufferPsPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convolution_rgb(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = (( mask_size-1 )/2)*3;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows*3 + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize ;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (i >= paddingSize) && (i < paddedW-paddingSize) && (j >= paddingSize) && (j<paddedH-paddingSize)) {
unsigned int oPixelPos = (i - paddingSize ) * cols + (j -paddingSize);
g[oPixelPos] = 0;
int iterationK = 0;
for(int k = -paddingSize; k <= paddingSize; k=k+3){
int iterationL = 0;
for(int l = -paddingSize; l<=paddingSize; l=l+3){
unsigned int iPixelPos = (i+k)*paddedH+(j+l);
unsigned int filtrePos = iterationK*mask_size + iterationL;
g[oPixelPos] += N[iPixelPos] * M[filtrePos];
iterationL++;
}
iterationK++;
}
}
} | code for sm_80
Function : _Z15convolution_rgbPhPfS_mmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff007624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IADD3 R0, P0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007f1e0ff */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e640000002600 */
/*0070*/ IADD3.X R5, R5, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630005057a10 */
/* 0x000fc400007fe4ff */
/*0080*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e640000002200 */
/*0090*/ SHF.R.U64 R0, R0, 0x1, R5 ; /* 0x0000000100007819 */
/* 0x000fe20000001205 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD R8, R0.reuse, 0x6, RZ ; /* 0x0000000600087824 */
/* 0x040fe400078e02ff */
/*00c0*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe400078e02ff */
/*00d0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00e0*/ IMAD R3, R5, 0x3, R8 ; /* 0x0000000305037824 */
/* 0x000fe400078e0208 */
/*00f0*/ IMAD.IADD R5, R0, 0x1, R2 ; /* 0x0000000100057824 */
/* 0x000fe400078e0202 */
/*0100*/ IMAD.IADD R4, R3, 0x1, -R0 ; /* 0x0000000103047824 */
/* 0x000fc400078e0a00 */
/*0110*/ IMAD R7, R7, c[0x0][0x4], R6 ; /* 0x0000010007077a24 */
/* 0x002fc600078e0206 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R5.reuse, R4, PT ; /* 0x000000040500720c */
/* 0x040fe20003f06070 */
/*0130*/ IMAD.IADD R3, R0, 0x1, R7 ; /* 0x0000000100037824 */
/* 0x000fe200078e0207 */
/*0140*/ IADD3 R4, R8, c[0x0][0x178], RZ ; /* 0x00005e0008047a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.LT.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x000fc60000701670 */
/*0160*/ IMAD.IADD R6, R4, 0x1, -R0 ; /* 0x0000000104067824 */
/* 0x000fe200078e0a00 */
/*0170*/ ISETP.LT.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fc80000701670 */
/*0180*/ ISETP.GE.U32.OR P0, PT, R3, R6, P0 ; /* 0x000000060300720c */
/* 0x000fda0000706470 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD R2, R2, c[0x0][0x178], R7 ; /* 0x00005e0002027a24 */
/* 0x000fe200078e0207 */
/*01b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a00 */
/*01d0*/ IADD3 R2, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fca0007f1e0ff */
/*01e0*/ IMAD.X R3, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff037624 */
/* 0x000fe200000e06ff */
/*01f0*/ ISETP.GE.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fc80003f06270 */
/*0200*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101106 */
/*0210*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0220*/ PRMT R13, RZ, 0x7610, R13 ; /* 0x00007610ff0d7816 */
/* 0x000fe2000000000d */
/*0230*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*0250*/ IMAD.IADD R8, R0, 0x1, R0 ; /* 0x0000000100087824 */
/* 0x000fe200078e0200 */
/*0260*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe20000000800 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0280*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*0290*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*02a0*/ ISETP.GT.AND P1, PT, R8, 0x8, PT ; /* 0x000000080800780c */
/* 0x000fe20003f24270 */
/*02b0*/ IMAD.IADD R8, R5, 0x1, R6 ; /* 0x0000000105087824 */
/* 0x000fc600078e0206 */
/*02c0*/ IMAD.U32 R10, RZ, RZ, UR5 ; /* 0x00000005ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*02d0*/ IMAD R8, R8, R4, R7 ; /* 0x0000000408087224 */
/* 0x000fce00078e0207 */
/*02e0*/ @!P1 BRA 0x6a0 ; /* 0x000003b000009947 */
/* 0x006fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ IADD3 R12, R0, -0x8, RZ ; /* 0xfffffff8000c7810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R18, P1, R8, c[0x0][0x160], RZ ; /* 0x0000580008127a10 */
/* 0x000fca0007f3e0ff */
/*0320*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x004fca00008e06ff */
/*0330*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.WIDE.U32 R14, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0e7625 */
/* 0x000fcc00078e0011 */
/*0360*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee2000c1e1900 */
/*0370*/ LOP3.LUT R16, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d107812 */
/* 0x000fe400078ec0ff */
/*0380*/ IADD3 R20, R8, 0x3, RZ ; /* 0x0000000308147810 */
/* 0x000fc80007ffe0ff */
/*0390*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x000fe20000101000 */
/*03a0*/ IADD3 R20, P1, R20, c[0x0][0x160], RZ ; /* 0x0000580014147a10 */
/* 0x000fca0007f3e0ff */
/*03b0*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff157624 */
/* 0x000fe400008e06ff */
/*03c0*/ I2F.U16 R13, R18 ; /* 0x00000012000d7306 */
/* 0x004ee40000101000 */
/*03d0*/ FFMA R13, R13, R14, R16 ; /* 0x0000000e0d0d7223 */
/* 0x008fcc0000000010 */
/*03e0*/ F2I.U32.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e62000020f000 */
/*03f0*/ IADD3 R14, R10, 0x1, RZ ; /* 0x000000010a0e7810 */
/* 0x000fe20007ffe0ff */
/*0400*/ STG.E.U8 [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0023e8000c101106 */
/*0410*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000ea2000c1e1100 */
/*0420*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fcc00078e0011 */
/*0430*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000722000c1e1900 */
/*0440*/ LOP3.LUT R22, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d167812 */
/* 0x000fe400078ec0ff */
/*0450*/ IADD3 R18, R8, 0x6, RZ ; /* 0x0000000608127810 */
/* 0x000fc80007ffe0ff */
/*0460*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x000fe20000101000 */
/*0470*/ IADD3 R18, P1, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fca0007f3e0ff */
/*0480*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x000fe200008e06ff */
/*0490*/ IADD3 R14, R10, 0x2, RZ ; /* 0x000000020a0e7810 */
/* 0x008fe20007ffe0ff */
/*04a0*/ I2F.U16 R16, R20 ; /* 0x0000001400107306 */
/* 0x004f240000101000 */
/*04b0*/ FFMA R16, R16, R15, R22 ; /* 0x0000000f10107223 */
/* 0x010fcc0000000016 */
/*04c0*/ F2I.U32.TRUNC.NTZ R23, R16 ; /* 0x0000001000177305 */
/* 0x000ea2000020f000 */
/*04d0*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fe200078e0011 */
/*04e0*/ STG.E.U8 [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x004fe8000c101106 */
/*04f0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000e68000c1e1100 */
/*0500*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1900 */
/*0510*/ LOP3.LUT R22, R23, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff17167812 */
/* 0x000fc400078ec0ff */
/*0520*/ IADD3 R20, R8, 0x9, RZ ; /* 0x0000000908147810 */
/* 0x000fc80007ffe0ff */
/*0530*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x000fe20000101000 */
/*0540*/ IADD3 R20, P1, R20, c[0x0][0x160], RZ ; /* 0x0000580014147a10 */
/* 0x000fca0007f3e0ff */
/*0550*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff157624 */
/* 0x000fe400008e06ff */
/*0560*/ I2F.U16 R13, R18 ; /* 0x00000012000d7306 */
/* 0x002ea40000101000 */
/*0570*/ FFMA R13, R13, R14, R22 ; /* 0x0000000e0d0d7223 */
/* 0x004fcc0000000016 */
/*0580*/ F2I.U32.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e62000020f000 */
/*0590*/ IADD3 R14, R10, 0x3, RZ ; /* 0x000000030a0e7810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ STG.E.U8 [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0023e8000c101106 */
/*05b0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000ea2000c1e1100 */
/*05c0*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fcc00078e0011 */
/*05d0*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ LOP3.LUT R17, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d117812 */
/* 0x000fe400078ec0ff */
/*05f0*/ IADD3 R11, R11, 0xc, RZ ; /* 0x0000000c0b0b7810 */
/* 0x000fe40007ffe0ff */
/*0600*/ IADD3 R8, R8, 0xc, RZ ; /* 0x0000000c08087810 */
/* 0x000fe40007ffe0ff */
/*0610*/ I2F.U16 R17, R17 ; /* 0x0000001100117306 */
/* 0x000fe20000101000 */
/*0620*/ ISETP.GE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f26270 */
/*0630*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fca0007ffe0ff */
/*0640*/ I2F.U16 R16, R20 ; /* 0x0000001400107306 */
/* 0x004ee40000101000 */
/*0650*/ FFMA R16, R16, R15, R17 ; /* 0x0000000f10107223 */
/* 0x008fcc0000000011 */
/*0660*/ F2I.U32.TRUNC.NTZ R19, R16 ; /* 0x0000001000137305 */
/* 0x000ea4000020f000 */
/*0670*/ STG.E.U8 [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0045e2000c101106 */
/*0680*/ PRMT R13, R19, 0x7610, R13 ; /* 0x00007610130d7816 */
/* 0x002fe2000000000d */
/*0690*/ @!P1 BRA 0x310 ; /* 0xfffffc7000009947 */
/* 0x000fea000383ffff */
/*06a0*/ IMAD.IADD R12, R0, 0x1, -R11 ; /* 0x00000001000c7824 */
/* 0x000fe200078e0a0b */
/*06b0*/ IADD3 R6, R6, 0x3, RZ ; /* 0x0000000306067810 */
/* 0x000fc80007ffe0ff */
/*06c0*/ ISETP.GT.AND P2, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f44270 */
/*06d0*/ ISETP.GT.AND P1, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fd60003f24270 */
/*06e0*/ @!P2 BRA 0x8d0 ; /* 0x000001e00000a947 */
/* 0x000fea0003800000 */
/*06f0*/ IADD3 R16, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008107a10 */
/* 0x000fca0007f1e0ff */
/*0700*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff117624 */
/* 0x000fca00000e06ff */
/*0710*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ee2000c1e1100 */
/*0720*/ IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; /* 0x00000004ff177424 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.WIDE.U32 R14, R10, R23, c[0x0][0x168] ; /* 0x00005a000a0e7625 */
/* 0x000fcc00078e0017 */
/*0740*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000f22000c1e1900 */
/*0750*/ LOP3.LUT R20, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d147812 */
/* 0x000fe400078ec0ff */
/*0760*/ IADD3 R18, R8, 0x3, RZ ; /* 0x0000000308127810 */
/* 0x000fc80007ffe0ff */
/*0770*/ I2F.U16 R20, R20 ; /* 0x0000001400147306 */
/* 0x000fe20000101000 */
/*0780*/ IADD3 R18, P0, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fca0007f1e0ff */
/*0790*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x004fe400000e06ff */
/*07a0*/ I2F.U16 R12, R16 ; /* 0x00000010000c7306 */
/* 0x008f240000101000 */
/*07b0*/ FFMA R21, R12, R15, R20 ; /* 0x0000000f0c157223 */
/* 0x010fcc0000000014 */
/*07c0*/ F2I.U32.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e62000020f000 */
/*07d0*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ STG.E.U8 [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0023e8000c101106 */
/*07f0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea2000c1e1100 */
/*0800*/ IMAD.WIDE.U32 R12, R12, R23, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e0017 */
/*0810*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ee2000c1e1900 */
/*0820*/ LOP3.LUT R15, R21, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff150f7812 */
/* 0x000fe400078ec0ff */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0840*/ IADD3 R11, R11, 0x6, RZ ; /* 0x000000060b0b7810 */
/* 0x000fe40007ffe0ff */
/*0850*/ I2F.U16 R15, R15 ; /* 0x0000000f000f7306 */
/* 0x000fe20000101000 */
/*0860*/ IADD3 R8, R8, 0x6, RZ ; /* 0x0000000608087810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R10, R10, 0x2, RZ ; /* 0x000000020a0a7810 */
/* 0x000fca0007ffe0ff */
/*0880*/ I2F.U16 R14, R18 ; /* 0x00000012000e7306 */
/* 0x004ee40000101000 */
/*0890*/ FFMA R14, R14, R13, R15 ; /* 0x0000000d0e0e7223 */
/* 0x008fcc000000000f */
/*08a0*/ F2I.U32.TRUNC.NTZ R17, R14 ; /* 0x0000000e00117305 */
/* 0x000ea4000020f000 */
/*08b0*/ STG.E.U8 [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0043e2000c101106 */
/*08c0*/ PRMT R13, R17, 0x7610, R13 ; /* 0x00007610110d7816 */
/* 0x000fca000000000d */
/*08d0*/ ISETP.LE.OR P0, PT, R11, R0, P0 ; /* 0x000000000b00720c */
/* 0x000fda0000703670 */
/*08e0*/ @!P0 BRA 0x9c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IADD3 R14, P0, R8, c[0x0][0x160], RZ ; /* 0x00005800080e7a10 */
/* 0x000fca0007f1e0ff */
/*0900*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f7624 */
/* 0x000fca00000e06ff */
/*0910*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee2000c1e1100 */
/*0920*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0930*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fcc00078e000b */
/*0940*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f22000c1e1900 */
/*0950*/ LOP3.LUT R12, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0c7812 */
/* 0x000fcc00078ec0ff */
/*0960*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x000ff00000101000 */
/*0970*/ I2F.U16 R8, R14 ; /* 0x0000000e00087306 */
/* 0x008f240000101000 */
/*0980*/ FFMA R8, R8, R11, R12 ; /* 0x0000000b08087223 */
/* 0x010fcc000000000c */
/*0990*/ F2I.U32.TRUNC.NTZ R17, R8 ; /* 0x0000000800117305 */
/* 0x002e64000020f000 */
/*09a0*/ STG.E.U8 [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0023e2000c101106 */
/*09b0*/ PRMT R13, R17, 0x7610, R13 ; /* 0x00007610110d7816 */
/* 0x000fca000000000d */
/*09c0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*09d0*/ @!P1 BRA 0x250 ; /* 0xfffff87000009947 */
/* 0x000fea000383ffff */
/*09e0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convolution_rgb(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = (( mask_size-1 )/2)*3;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows*3 + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize ;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (i >= paddingSize) && (i < paddedW-paddingSize) && (j >= paddingSize) && (j<paddedH-paddingSize)) {
unsigned int oPixelPos = (i - paddingSize ) * cols + (j -paddingSize);
g[oPixelPos] = 0;
int iterationK = 0;
for(int k = -paddingSize; k <= paddingSize; k=k+3){
int iterationL = 0;
for(int l = -paddingSize; l<=paddingSize; l=l+3){
unsigned int iPixelPos = (i+k)*paddedH+(j+l);
unsigned int filtrePos = iterationK*mask_size + iterationL;
g[oPixelPos] += N[iPixelPos] * M[filtrePos];
iterationL++;
}
iterationK++;
}
}
} | .file "tmpxft_000f7d5c_00000000-6_convolution_rgb.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm
.type _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm, @function
_Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15convolution_rgbPhPfS_mmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm, .-_Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm
.globl _Z15convolution_rgbPhPfS_mmm
.type _Z15convolution_rgbPhPfS_mmm, @function
_Z15convolution_rgbPhPfS_mmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15convolution_rgbPhPfS_mmm, .-_Z15convolution_rgbPhPfS_mmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15convolution_rgbPhPfS_mmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15convolution_rgbPhPfS_mmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convolution_rgb(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = (( mask_size-1 )/2)*3;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows*3 + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize ;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (i >= paddingSize) && (i < paddedW-paddingSize) && (j >= paddingSize) && (j<paddedH-paddingSize)) {
unsigned int oPixelPos = (i - paddingSize ) * cols + (j -paddingSize);
g[oPixelPos] = 0;
int iterationK = 0;
for(int k = -paddingSize; k <= paddingSize; k=k+3){
int iterationL = 0;
for(int l = -paddingSize; l<=paddingSize; l=l+3){
unsigned int iPixelPos = (i+k)*paddedH+(j+l);
unsigned int filtrePos = iterationK*mask_size + iterationL;
g[oPixelPos] += N[iPixelPos] * M[filtrePos];
iterationL++;
}
iterationK++;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_rgb(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = (( mask_size-1 )/2)*3;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows*3 + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize ;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (i >= paddingSize) && (i < paddedW-paddingSize) && (j >= paddingSize) && (j<paddedH-paddingSize)) {
unsigned int oPixelPos = (i - paddingSize ) * cols + (j -paddingSize);
g[oPixelPos] = 0;
int iterationK = 0;
for(int k = -paddingSize; k <= paddingSize; k=k+3){
int iterationL = 0;
for(int l = -paddingSize; l<=paddingSize; l=l+3){
unsigned int iPixelPos = (i+k)*paddedH+(j+l);
unsigned int filtrePos = iterationK*mask_size + iterationL;
g[oPixelPos] += N[iPixelPos] * M[filtrePos];
iterationL++;
}
iterationK++;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_rgb(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = (( mask_size-1 )/2)*3;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows*3 + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize ;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (i >= paddingSize) && (i < paddedW-paddingSize) && (j >= paddingSize) && (j<paddedH-paddingSize)) {
unsigned int oPixelPos = (i - paddingSize ) * cols + (j -paddingSize);
g[oPixelPos] = 0;
int iterationK = 0;
for(int k = -paddingSize; k <= paddingSize; k=k+3){
int iterationL = 0;
for(int l = -paddingSize; l<=paddingSize; l=l+3){
unsigned int iPixelPos = (i+k)*paddedH+(j+l);
unsigned int filtrePos = iterationK*mask_size + iterationL;
g[oPixelPos] += N[iPixelPos] * M[filtrePos];
iterationL++;
}
iterationK++;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15convolution_rgbPhPfS_mmm
.globl _Z15convolution_rgbPhPfS_mmm
.p2align 8
.type _Z15convolution_rgbPhPfS_mmm,@function
_Z15convolution_rgbPhPfS_mmm:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s8, s[0:1], 0x3c
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, -1
s_addc_u32 s3, s5, 1
s_add_u32 s6, s0, 48
v_alignbit_b32 v1, s3, s2, 1
s_addc_u32 s7, s1, 0
s_and_b32 s5, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s5
v_readfirstlane_b32 s8, v1
v_add_nc_u32_e32 v3, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mul_i32 s5, s8, 3
s_mov_b32 s8, exec_lo
v_add_nc_u32_e32 v1, s5, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s5, v1
s_cbranch_execz .LBB0_7
s_load_b32 s8, s[6:7], 0xc
s_clause 0x1
s_load_b32 s9, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
s_lshr_b64 s[2:3], s[2:3], 1
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s2, 6
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s8, 16
s_mul_i32 s9, s9, 3
s_mul_i32 s15, s15, s7
s_add_i32 s3, s2, s9
v_add_nc_u32_e32 v0, s15, v5
s_add_i32 s9, s2, s6
s_sub_i32 s2, s3, s5
s_sub_i32 s3, s9, s5
v_cmp_gt_u32_e32 vcc_lo, s2, v1
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s2, s3, v2
v_cmp_le_i32_e64 s3, s5, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v3, s6, v[0:1]
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s5, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
global_store_b8 v1, v0, s[2:3]
s_cbranch_scc1 .LBB0_7
v_add_co_u32 v0, s2, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v3, v3, s9
v_mov_b32_e32 v2, 0
global_load_u8 v4, v[0:1], off
s_sub_i32 s8, 0, s5
s_mul_i32 s9, s9, 3
s_mov_b32 s10, 0
s_mov_b32 s11, s8
v_add3_u32 v3, v5, s15, v3
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v3
s_mov_b32 s6, s10
s_mov_b32 s12, s8
.p2align 6
.LBB0_5:
s_waitcnt lgkmcnt(0)
global_load_u8 v6, v5, s[0:1]
s_lshl_b64 s[14:15], s[6:7], 2
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v4, v4
s_add_u32 s14, s2, s14
s_addc_u32 s15, s3, s15
s_add_i32 s12, s12, 3
global_load_b32 v7, v2, s[14:15]
s_add_i32 s6, s6, 1
s_cmp_gt_i32 s12, s5
v_add_nc_u32_e32 v5, 3, v5
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v6
v_cvt_i32_f32_e32 v4, v4
global_store_b8 v[0:1], v4, off
s_cbranch_scc0 .LBB0_5
v_add_nc_u32_e32 v3, s9, v3
s_add_i32 s11, s11, 3
s_add_i32 s10, s10, s4
s_cmp_gt_i32 s11, s5
s_cbranch_scc0 .LBB0_4
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15convolution_rgbPhPfS_mmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15convolution_rgbPhPfS_mmm, .Lfunc_end0-_Z15convolution_rgbPhPfS_mmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15convolution_rgbPhPfS_mmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15convolution_rgbPhPfS_mmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_rgb(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = (( mask_size-1 )/2)*3;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows*3 + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize ;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (i >= paddingSize) && (i < paddedW-paddingSize) && (j >= paddingSize) && (j<paddedH-paddingSize)) {
unsigned int oPixelPos = (i - paddingSize ) * cols + (j -paddingSize);
g[oPixelPos] = 0;
int iterationK = 0;
for(int k = -paddingSize; k <= paddingSize; k=k+3){
int iterationL = 0;
for(int l = -paddingSize; l<=paddingSize; l=l+3){
unsigned int iPixelPos = (i+k)*paddedH+(j+l);
unsigned int filtrePos = iterationK*mask_size + iterationL;
g[oPixelPos] += N[iPixelPos] * M[filtrePos];
iterationL++;
}
iterationK++;
}
}
} | .text
.file "convolution_rgb.hip"
.globl _Z30__device_stub__convolution_rgbPhPfS_mmm # -- Begin function _Z30__device_stub__convolution_rgbPhPfS_mmm
.p2align 4, 0x90
.type _Z30__device_stub__convolution_rgbPhPfS_mmm,@function
_Z30__device_stub__convolution_rgbPhPfS_mmm: # @_Z30__device_stub__convolution_rgbPhPfS_mmm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15convolution_rgbPhPfS_mmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__convolution_rgbPhPfS_mmm, .Lfunc_end0-_Z30__device_stub__convolution_rgbPhPfS_mmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15convolution_rgbPhPfS_mmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15convolution_rgbPhPfS_mmm,@object # @_Z15convolution_rgbPhPfS_mmm
.section .rodata,"a",@progbits
.globl _Z15convolution_rgbPhPfS_mmm
.p2align 3, 0x0
_Z15convolution_rgbPhPfS_mmm:
.quad _Z30__device_stub__convolution_rgbPhPfS_mmm
.size _Z15convolution_rgbPhPfS_mmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15convolution_rgbPhPfS_mmm"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__convolution_rgbPhPfS_mmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15convolution_rgbPhPfS_mmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15convolution_rgbPhPfS_mmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff007624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IADD3 R0, P0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007f1e0ff */
/*0060*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e640000002600 */
/*0070*/ IADD3.X R5, R5, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630005057a10 */
/* 0x000fc400007fe4ff */
/*0080*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e640000002200 */
/*0090*/ SHF.R.U64 R0, R0, 0x1, R5 ; /* 0x0000000100007819 */
/* 0x000fe20000001205 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD R8, R0.reuse, 0x6, RZ ; /* 0x0000000600087824 */
/* 0x040fe400078e02ff */
/*00c0*/ IMAD R0, R0, 0x3, RZ ; /* 0x0000000300007824 */
/* 0x000fe400078e02ff */
/*00d0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fe400078e0203 */
/*00e0*/ IMAD R3, R5, 0x3, R8 ; /* 0x0000000305037824 */
/* 0x000fe400078e0208 */
/*00f0*/ IMAD.IADD R5, R0, 0x1, R2 ; /* 0x0000000100057824 */
/* 0x000fe400078e0202 */
/*0100*/ IMAD.IADD R4, R3, 0x1, -R0 ; /* 0x0000000103047824 */
/* 0x000fc400078e0a00 */
/*0110*/ IMAD R7, R7, c[0x0][0x4], R6 ; /* 0x0000010007077a24 */
/* 0x002fc600078e0206 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R5.reuse, R4, PT ; /* 0x000000040500720c */
/* 0x040fe20003f06070 */
/*0130*/ IMAD.IADD R3, R0, 0x1, R7 ; /* 0x0000000100037824 */
/* 0x000fe200078e0207 */
/*0140*/ IADD3 R4, R8, c[0x0][0x178], RZ ; /* 0x00005e0008047a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.LT.OR P0, PT, R5, R0, P0 ; /* 0x000000000500720c */
/* 0x000fc60000701670 */
/*0160*/ IMAD.IADD R6, R4, 0x1, -R0 ; /* 0x0000000104067824 */
/* 0x000fe200078e0a00 */
/*0170*/ ISETP.LT.OR P0, PT, R3, R0, P0 ; /* 0x000000000300720c */
/* 0x000fc80000701670 */
/*0180*/ ISETP.GE.U32.OR P0, PT, R3, R6, P0 ; /* 0x000000060300720c */
/* 0x000fda0000706470 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD R2, R2, c[0x0][0x178], R7 ; /* 0x00005e0002027a24 */
/* 0x000fe200078e0207 */
/*01b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01c0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a00 */
/*01d0*/ IADD3 R2, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fca0007f1e0ff */
/*01e0*/ IMAD.X R3, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff037624 */
/* 0x000fe200000e06ff */
/*01f0*/ ISETP.GE.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fc80003f06270 */
/*0200*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f2000c101106 */
/*0210*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0220*/ PRMT R13, RZ, 0x7610, R13 ; /* 0x00007610ff0d7816 */
/* 0x000fe2000000000d */
/*0230*/ IMAD.MOV.U32 R6, RZ, RZ, R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0009 */
/*0240*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc40008000000 */
/*0250*/ IMAD.IADD R8, R0, 0x1, R0 ; /* 0x0000000100087824 */
/* 0x000fe200078e0200 */
/*0260*/ ULDC UR5, c[0x0][0x188] ; /* 0x0000620000057ab9 */
/* 0x000fe20000000800 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f070 */
/*0280*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*0290*/ IMAD.MOV.U32 R11, RZ, RZ, R9 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0009 */
/*02a0*/ ISETP.GT.AND P1, PT, R8, 0x8, PT ; /* 0x000000080800780c */
/* 0x000fe20003f24270 */
/*02b0*/ IMAD.IADD R8, R5, 0x1, R6 ; /* 0x0000000105087824 */
/* 0x000fc600078e0206 */
/*02c0*/ IMAD.U32 R10, RZ, RZ, UR5 ; /* 0x00000005ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*02d0*/ IMAD R8, R8, R4, R7 ; /* 0x0000000408087224 */
/* 0x000fce00078e0207 */
/*02e0*/ @!P1 BRA 0x6a0 ; /* 0x000003b000009947 */
/* 0x006fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ IADD3 R12, R0, -0x8, RZ ; /* 0xfffffff8000c7810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IADD3 R18, P1, R8, c[0x0][0x160], RZ ; /* 0x0000580008127a10 */
/* 0x000fca0007f3e0ff */
/*0320*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x004fca00008e06ff */
/*0330*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.WIDE.U32 R14, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0e7625 */
/* 0x000fcc00078e0011 */
/*0360*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee2000c1e1900 */
/*0370*/ LOP3.LUT R16, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d107812 */
/* 0x000fe400078ec0ff */
/*0380*/ IADD3 R20, R8, 0x3, RZ ; /* 0x0000000308147810 */
/* 0x000fc80007ffe0ff */
/*0390*/ I2F.U16 R16, R16 ; /* 0x0000001000107306 */
/* 0x000fe20000101000 */
/*03a0*/ IADD3 R20, P1, R20, c[0x0][0x160], RZ ; /* 0x0000580014147a10 */
/* 0x000fca0007f3e0ff */
/*03b0*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff157624 */
/* 0x000fe400008e06ff */
/*03c0*/ I2F.U16 R13, R18 ; /* 0x00000012000d7306 */
/* 0x004ee40000101000 */
/*03d0*/ FFMA R13, R13, R14, R16 ; /* 0x0000000e0d0d7223 */
/* 0x008fcc0000000010 */
/*03e0*/ F2I.U32.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e62000020f000 */
/*03f0*/ IADD3 R14, R10, 0x1, RZ ; /* 0x000000010a0e7810 */
/* 0x000fe20007ffe0ff */
/*0400*/ STG.E.U8 [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0023e8000c101106 */
/*0410*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000ea2000c1e1100 */
/*0420*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fcc00078e0011 */
/*0430*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000722000c1e1900 */
/*0440*/ LOP3.LUT R22, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d167812 */
/* 0x000fe400078ec0ff */
/*0450*/ IADD3 R18, R8, 0x6, RZ ; /* 0x0000000608127810 */
/* 0x000fc80007ffe0ff */
/*0460*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x000fe20000101000 */
/*0470*/ IADD3 R18, P1, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fca0007f3e0ff */
/*0480*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x000fe200008e06ff */
/*0490*/ IADD3 R14, R10, 0x2, RZ ; /* 0x000000020a0e7810 */
/* 0x008fe20007ffe0ff */
/*04a0*/ I2F.U16 R16, R20 ; /* 0x0000001400107306 */
/* 0x004f240000101000 */
/*04b0*/ FFMA R16, R16, R15, R22 ; /* 0x0000000f10107223 */
/* 0x010fcc0000000016 */
/*04c0*/ F2I.U32.TRUNC.NTZ R23, R16 ; /* 0x0000001000177305 */
/* 0x000ea2000020f000 */
/*04d0*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fe200078e0011 */
/*04e0*/ STG.E.U8 [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x004fe8000c101106 */
/*04f0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000e68000c1e1100 */
/*0500*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1900 */
/*0510*/ LOP3.LUT R22, R23, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff17167812 */
/* 0x000fc400078ec0ff */
/*0520*/ IADD3 R20, R8, 0x9, RZ ; /* 0x0000000908147810 */
/* 0x000fc80007ffe0ff */
/*0530*/ I2F.U16 R22, R22 ; /* 0x0000001600167306 */
/* 0x000fe20000101000 */
/*0540*/ IADD3 R20, P1, R20, c[0x0][0x160], RZ ; /* 0x0000580014147a10 */
/* 0x000fca0007f3e0ff */
/*0550*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff157624 */
/* 0x000fe400008e06ff */
/*0560*/ I2F.U16 R13, R18 ; /* 0x00000012000d7306 */
/* 0x002ea40000101000 */
/*0570*/ FFMA R13, R13, R14, R22 ; /* 0x0000000e0d0d7223 */
/* 0x004fcc0000000016 */
/*0580*/ F2I.U32.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e62000020f000 */
/*0590*/ IADD3 R14, R10, 0x3, RZ ; /* 0x000000030a0e7810 */
/* 0x000fe20007ffe0ff */
/*05a0*/ STG.E.U8 [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0023e8000c101106 */
/*05b0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000ea2000c1e1100 */
/*05c0*/ IMAD.WIDE.U32 R14, R14, R17, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fcc00078e0011 */
/*05d0*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ LOP3.LUT R17, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d117812 */
/* 0x000fe400078ec0ff */
/*05f0*/ IADD3 R11, R11, 0xc, RZ ; /* 0x0000000c0b0b7810 */
/* 0x000fe40007ffe0ff */
/*0600*/ IADD3 R8, R8, 0xc, RZ ; /* 0x0000000c08087810 */
/* 0x000fe40007ffe0ff */
/*0610*/ I2F.U16 R17, R17 ; /* 0x0000001100117306 */
/* 0x000fe20000101000 */
/*0620*/ ISETP.GE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f26270 */
/*0630*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fca0007ffe0ff */
/*0640*/ I2F.U16 R16, R20 ; /* 0x0000001400107306 */
/* 0x004ee40000101000 */
/*0650*/ FFMA R16, R16, R15, R17 ; /* 0x0000000f10107223 */
/* 0x008fcc0000000011 */
/*0660*/ F2I.U32.TRUNC.NTZ R19, R16 ; /* 0x0000001000137305 */
/* 0x000ea4000020f000 */
/*0670*/ STG.E.U8 [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0045e2000c101106 */
/*0680*/ PRMT R13, R19, 0x7610, R13 ; /* 0x00007610130d7816 */
/* 0x002fe2000000000d */
/*0690*/ @!P1 BRA 0x310 ; /* 0xfffffc7000009947 */
/* 0x000fea000383ffff */
/*06a0*/ IMAD.IADD R12, R0, 0x1, -R11 ; /* 0x00000001000c7824 */
/* 0x000fe200078e0a0b */
/*06b0*/ IADD3 R6, R6, 0x3, RZ ; /* 0x0000000306067810 */
/* 0x000fc80007ffe0ff */
/*06c0*/ ISETP.GT.AND P2, PT, R12, 0x2, PT ; /* 0x000000020c00780c */
/* 0x000fe40003f44270 */
/*06d0*/ ISETP.GT.AND P1, PT, R6, R0, PT ; /* 0x000000000600720c */
/* 0x000fd60003f24270 */
/*06e0*/ @!P2 BRA 0x8d0 ; /* 0x000001e00000a947 */
/* 0x000fea0003800000 */
/*06f0*/ IADD3 R16, P0, R8, c[0x0][0x160], RZ ; /* 0x0000580008107a10 */
/* 0x000fca0007f1e0ff */
/*0700*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff117624 */
/* 0x000fca00000e06ff */
/*0710*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000610107981 */
/* 0x000ee2000c1e1100 */
/*0720*/ IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; /* 0x00000004ff177424 */
/* 0x000fc800078e00ff */
/*0730*/ IMAD.WIDE.U32 R14, R10, R23, c[0x0][0x168] ; /* 0x00005a000a0e7625 */
/* 0x000fcc00078e0017 */
/*0740*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000f22000c1e1900 */
/*0750*/ LOP3.LUT R20, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d147812 */
/* 0x000fe400078ec0ff */
/*0760*/ IADD3 R18, R8, 0x3, RZ ; /* 0x0000000308127810 */
/* 0x000fc80007ffe0ff */
/*0770*/ I2F.U16 R20, R20 ; /* 0x0000001400147306 */
/* 0x000fe20000101000 */
/*0780*/ IADD3 R18, P0, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fca0007f1e0ff */
/*0790*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x004fe400000e06ff */
/*07a0*/ I2F.U16 R12, R16 ; /* 0x00000010000c7306 */
/* 0x008f240000101000 */
/*07b0*/ FFMA R21, R12, R15, R20 ; /* 0x0000000f0c157223 */
/* 0x010fcc0000000014 */
/*07c0*/ F2I.U32.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e62000020f000 */
/*07d0*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ STG.E.U8 [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0023e8000c101106 */
/*07f0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea2000c1e1100 */
/*0800*/ IMAD.WIDE.U32 R12, R12, R23, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fcc00078e0017 */
/*0810*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ee2000c1e1900 */
/*0820*/ LOP3.LUT R15, R21, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff150f7812 */
/* 0x000fe400078ec0ff */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0840*/ IADD3 R11, R11, 0x6, RZ ; /* 0x000000060b0b7810 */
/* 0x000fe40007ffe0ff */
/*0850*/ I2F.U16 R15, R15 ; /* 0x0000000f000f7306 */
/* 0x000fe20000101000 */
/*0860*/ IADD3 R8, R8, 0x6, RZ ; /* 0x0000000608087810 */
/* 0x000fe40007ffe0ff */
/*0870*/ IADD3 R10, R10, 0x2, RZ ; /* 0x000000020a0a7810 */
/* 0x000fca0007ffe0ff */
/*0880*/ I2F.U16 R14, R18 ; /* 0x00000012000e7306 */
/* 0x004ee40000101000 */
/*0890*/ FFMA R14, R14, R13, R15 ; /* 0x0000000d0e0e7223 */
/* 0x008fcc000000000f */
/*08a0*/ F2I.U32.TRUNC.NTZ R17, R14 ; /* 0x0000000e00117305 */
/* 0x000ea4000020f000 */
/*08b0*/ STG.E.U8 [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0043e2000c101106 */
/*08c0*/ PRMT R13, R17, 0x7610, R13 ; /* 0x00007610110d7816 */
/* 0x000fca000000000d */
/*08d0*/ ISETP.LE.OR P0, PT, R11, R0, P0 ; /* 0x000000000b00720c */
/* 0x000fda0000703670 */
/*08e0*/ @!P0 BRA 0x9c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08f0*/ IADD3 R14, P0, R8, c[0x0][0x160], RZ ; /* 0x00005800080e7a10 */
/* 0x000fca0007f1e0ff */
/*0900*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f7624 */
/* 0x000fca00000e06ff */
/*0910*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ee2000c1e1100 */
/*0920*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fc800078e00ff */
/*0930*/ IMAD.WIDE.U32 R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fcc00078e000b */
/*0940*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f22000c1e1900 */
/*0950*/ LOP3.LUT R12, R13, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0d0c7812 */
/* 0x000fcc00078ec0ff */
/*0960*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x000ff00000101000 */
/*0970*/ I2F.U16 R8, R14 ; /* 0x0000000e00087306 */
/* 0x008f240000101000 */
/*0980*/ FFMA R8, R8, R11, R12 ; /* 0x0000000b08087223 */
/* 0x010fcc000000000c */
/*0990*/ F2I.U32.TRUNC.NTZ R17, R8 ; /* 0x0000000800117305 */
/* 0x002e64000020f000 */
/*09a0*/ STG.E.U8 [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0023e2000c101106 */
/*09b0*/ PRMT R13, R17, 0x7610, R13 ; /* 0x00007610110d7816 */
/* 0x000fca000000000d */
/*09c0*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*09d0*/ @!P1 BRA 0x250 ; /* 0xfffff87000009947 */
/* 0x000fea000383ffff */
/*09e0*/ NOP ; /* 0x0000000000007918 */
/* 0x000fc20000000000 */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15convolution_rgbPhPfS_mmm
.globl _Z15convolution_rgbPhPfS_mmm
.p2align 8
.type _Z15convolution_rgbPhPfS_mmm,@function
_Z15convolution_rgbPhPfS_mmm:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s8, s[0:1], 0x3c
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, -1
s_addc_u32 s3, s5, 1
s_add_u32 s6, s0, 48
v_alignbit_b32 v1, s3, s2, 1
s_addc_u32 s7, s1, 0
s_and_b32 s5, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s5
v_readfirstlane_b32 s8, v1
v_add_nc_u32_e32 v3, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mul_i32 s5, s8, 3
s_mov_b32 s8, exec_lo
v_add_nc_u32_e32 v1, s5, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s5, v1
s_cbranch_execz .LBB0_7
s_load_b32 s8, s[6:7], 0xc
s_clause 0x1
s_load_b32 s9, s[0:1], 0x20
s_load_b64 s[6:7], s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
s_lshr_b64 s[2:3], s[2:3], 1
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s2, 6
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s8, 16
s_mul_i32 s9, s9, 3
s_mul_i32 s15, s15, s7
s_add_i32 s3, s2, s9
v_add_nc_u32_e32 v0, s15, v5
s_add_i32 s9, s2, s6
s_sub_i32 s2, s3, s5
s_sub_i32 s3, s9, s5
v_cmp_gt_u32_e32 vcc_lo, s2, v1
v_add_nc_u32_e32 v2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s2, s3, v2
v_cmp_le_i32_e64 s3, s5, v2
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v3, s6, v[0:1]
v_mov_b32_e32 v0, 0
s_cmp_lt_i32 s5, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
global_store_b8 v1, v0, s[2:3]
s_cbranch_scc1 .LBB0_7
v_add_co_u32 v0, s2, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v3, v3, s9
v_mov_b32_e32 v2, 0
global_load_u8 v4, v[0:1], off
s_sub_i32 s8, 0, s5
s_mul_i32 s9, s9, 3
s_mov_b32 s10, 0
s_mov_b32 s11, s8
v_add3_u32 v3, v5, s15, v3
.p2align 6
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v5, v3
s_mov_b32 s6, s10
s_mov_b32 s12, s8
.p2align 6
.LBB0_5:
s_waitcnt lgkmcnt(0)
global_load_u8 v6, v5, s[0:1]
s_lshl_b64 s[14:15], s[6:7], 2
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v4, v4
s_add_u32 s14, s2, s14
s_addc_u32 s15, s3, s15
s_add_i32 s12, s12, 3
global_load_b32 v7, v2, s[14:15]
s_add_i32 s6, s6, 1
s_cmp_gt_i32 s12, s5
v_add_nc_u32_e32 v5, 3, v5
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v6
v_cvt_i32_f32_e32 v4, v4
global_store_b8 v[0:1], v4, off
s_cbranch_scc0 .LBB0_5
v_add_nc_u32_e32 v3, s9, v3
s_add_i32 s11, s11, 3
s_add_i32 s10, s10, s4
s_cmp_gt_i32 s11, s5
s_cbranch_scc0 .LBB0_4
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15convolution_rgbPhPfS_mmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15convolution_rgbPhPfS_mmm, .Lfunc_end0-_Z15convolution_rgbPhPfS_mmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15convolution_rgbPhPfS_mmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15convolution_rgbPhPfS_mmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f7d5c_00000000-6_convolution_rgb.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm
.type _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm, @function
_Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15convolution_rgbPhPfS_mmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm, .-_Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm
.globl _Z15convolution_rgbPhPfS_mmm
.type _Z15convolution_rgbPhPfS_mmm, @function
_Z15convolution_rgbPhPfS_mmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15convolution_rgbPhPfS_mmmPhPfS_mmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15convolution_rgbPhPfS_mmm, .-_Z15convolution_rgbPhPfS_mmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15convolution_rgbPhPfS_mmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15convolution_rgbPhPfS_mmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolution_rgb.hip"
.globl _Z30__device_stub__convolution_rgbPhPfS_mmm # -- Begin function _Z30__device_stub__convolution_rgbPhPfS_mmm
.p2align 4, 0x90
.type _Z30__device_stub__convolution_rgbPhPfS_mmm,@function
_Z30__device_stub__convolution_rgbPhPfS_mmm: # @_Z30__device_stub__convolution_rgbPhPfS_mmm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15convolution_rgbPhPfS_mmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__convolution_rgbPhPfS_mmm, .Lfunc_end0-_Z30__device_stub__convolution_rgbPhPfS_mmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15convolution_rgbPhPfS_mmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15convolution_rgbPhPfS_mmm,@object # @_Z15convolution_rgbPhPfS_mmm
.section .rodata,"a",@progbits
.globl _Z15convolution_rgbPhPfS_mmm
.p2align 3, 0x0
_Z15convolution_rgbPhPfS_mmm:
.quad _Z30__device_stub__convolution_rgbPhPfS_mmm
.size _Z15convolution_rgbPhPfS_mmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15convolution_rgbPhPfS_mmm"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__convolution_rgbPhPfS_mmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15convolution_rgbPhPfS_mmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /************************************************************
Known issues:
This program only works on matrices smaller than or equal to
256x256. 1024x1024 will cause segmentation faults and 512x512
simply causes the program to almost crash and return times of
0 for each kernel call.
The matrices must be square and all matrices must be the same
size.
*/
#include <stdio.h>
#include <stdlib.h>
#define MATSIZE 128
#define THREADS_PER_BLOCK 32
//serial matrix multiplication kernel
__global__ void smultiply(int* g_a, int* g_b, int* g_c)
{
int x, y, z;
for (x = 0; x < MATSIZE; ++ x)
{
for (y = 0; y < MATSIZE; ++ y)
{
for (z = 0; z < MATSIZE; ++ z)
{
g_c[(x * MATSIZE) + y] += g_a[(x * MATSIZE) + z] * g_b[(z * MATSIZE) + y];
}
}
}
}
//parallel matrix multiplication kernel
__global__ void pmultiply(double* g_a, double* g_b, double* g_d , int dim)
{
int z;
double sum = 0.0;
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
for (z = 0; z < dim; ++ z)
{
sum += g_a[x * dim + z] * g_b[y + z * dim];
}
g_d[(x * dim) + y] = sum;
}
extern "C" void Cudamultiply(double* a, double* b, double* d, int Dim)
{
// double *d;
int i;
double *g_a, *g_b, *g_d;
int g_size = Dim * Dim * sizeof(double);
cudaEvent_t start, stop;
float time;
// d=new double[Dim*Dim];
cudaEventCreate(&start);
cudaEventCreate(&stop);
//used for timing the Cuda run
cudaMalloc(&g_a, g_size); //allocate memory on Cuda device
cudaMemcpy(g_a, a, g_size, cudaMemcpyHostToDevice);
//copy matrix A onto the Cuda device
cudaMalloc(&g_b, g_size);
cudaMemcpy(g_b, b, g_size, cudaMemcpyHostToDevice);
// cudaMalloc(&g_c, g_size);
// cudaMemcpy(g_c, c, g_size, cudaMemcpyHostToDevice);
dim3 dimGrid((Dim / THREADS_PER_BLOCK), (Dim / THREADS_PER_BLOCK));
//create the needed number of grids
dim3 threads(THREADS_PER_BLOCK, THREADS_PER_BLOCK);
//create the needed number of threads in each grid
//serial Cuda kernel call
//cudaEventRecord(start, 0);
//smultiply<<<1,1>>>(g_a, g_b, g_c);
//cudaEventRecord(stop, 0);
//cudaEventSynchronize(stop);
//cudaEventElapsedTime(&time, start, stop);
//get run time
// cudaMemcpy(c, g_c, g_size, cudaMemcpyDeviceToHost);
//copy results back to host device
// cudaFree(g_c);
//free up unused user allocated memory on Cuda device
printf("Time = %f milliseconds\n", time);
//create a second answer matrix to use
//This is not done until now so that memory on the
//Cuda device is not wasted.
cudaMalloc(&g_d, g_size);
cudaMemcpy(g_d, d, g_size, cudaMemcpyHostToDevice);
//parallel Cuda kernel call
cudaEventRecord(start, 0);
pmultiply<<<dimGrid,threads>>>(g_a, g_b, g_d,Dim);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time = %f milliseconds\n", time);
cudaMemcpy(d, g_d, g_size, cudaMemcpyDeviceToHost);
cudaFree(g_a);
cudaFree(g_b);
cudaFree(g_d);
//free up all unused user allocated memory on Cuda device
//printf("\n");
/*The next 2 for loops print out the values of both
answer matrices. This can be used to ensure that both
kernel calls are producing the same results, and that
the results are correct. This section can be commented
out when the user only wants the timing of a run.*/
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if (i % Dim == 0)
// {
//// printf("%f ", c[i-1]);
// printf("\n");
// }
//
// else
//// printf("%f ", c[i-1]);
// }
// printf("\n");
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if ( i % Dim == 0)
// {
// printf("%f ", d[i-1]);
// printf("\n");
// }
//
// else
// printf("%f ", d[i-1]);
// }
// delete d;
} | .file "tmpxft_0012c482_00000000-6_cudamatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_
.type _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_, @function
_Z32__device_stub__Z9smultiplyPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9smultiplyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_, .-_Z32__device_stub__Z9smultiplyPiS_S_PiS_S_
.globl _Z9smultiplyPiS_S_
.type _Z9smultiplyPiS_S_, @function
_Z9smultiplyPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9smultiplyPiS_S_, .-_Z9smultiplyPiS_S_
.globl _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
.type _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i, @function
_Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9pmultiplyPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i, .-_Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
.globl _Z9pmultiplyPdS_S_i
.type _Z9pmultiplyPdS_S_i, @function
_Z9pmultiplyPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9pmultiplyPdS_S_i, .-_Z9pmultiplyPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Time = %f milliseconds\n"
.text
.globl Cudamultiply
.type Cudamultiply, @function
Cudamultiply:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebp, %ebx
imull %ebp, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $5, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size Cudamultiply, .-Cudamultiply
.section .rodata.str1.1
.LC1:
.string "_Z9pmultiplyPdS_S_i"
.LC2:
.string "_Z9smultiplyPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9pmultiplyPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9smultiplyPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /************************************************************
Known issues:
This program only works on matrices smaller than or equal to
256x256. 1024x1024 will cause segmentation faults and 512x512
simply causes the program to almost crash and return times of
0 for each kernel call.
The matrices must be square and all matrices must be the same
size.
*/
#include <stdio.h>
#include <stdlib.h>
#define MATSIZE 128
#define THREADS_PER_BLOCK 32
//serial matrix multiplication kernel
__global__ void smultiply(int* g_a, int* g_b, int* g_c)
{
int x, y, z;
for (x = 0; x < MATSIZE; ++ x)
{
for (y = 0; y < MATSIZE; ++ y)
{
for (z = 0; z < MATSIZE; ++ z)
{
g_c[(x * MATSIZE) + y] += g_a[(x * MATSIZE) + z] * g_b[(z * MATSIZE) + y];
}
}
}
}
//parallel matrix multiplication kernel
__global__ void pmultiply(double* g_a, double* g_b, double* g_d , int dim)
{
int z;
double sum = 0.0;
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
for (z = 0; z < dim; ++ z)
{
sum += g_a[x * dim + z] * g_b[y + z * dim];
}
g_d[(x * dim) + y] = sum;
}
extern "C" void Cudamultiply(double* a, double* b, double* d, int Dim)
{
// double *d;
int i;
double *g_a, *g_b, *g_d;
int g_size = Dim * Dim * sizeof(double);
cudaEvent_t start, stop;
float time;
// d=new double[Dim*Dim];
cudaEventCreate(&start);
cudaEventCreate(&stop);
//used for timing the Cuda run
cudaMalloc(&g_a, g_size); //allocate memory on Cuda device
cudaMemcpy(g_a, a, g_size, cudaMemcpyHostToDevice);
//copy matrix A onto the Cuda device
cudaMalloc(&g_b, g_size);
cudaMemcpy(g_b, b, g_size, cudaMemcpyHostToDevice);
// cudaMalloc(&g_c, g_size);
// cudaMemcpy(g_c, c, g_size, cudaMemcpyHostToDevice);
dim3 dimGrid((Dim / THREADS_PER_BLOCK), (Dim / THREADS_PER_BLOCK));
//create the needed number of grids
dim3 threads(THREADS_PER_BLOCK, THREADS_PER_BLOCK);
//create the needed number of threads in each grid
//serial Cuda kernel call
//cudaEventRecord(start, 0);
//smultiply<<<1,1>>>(g_a, g_b, g_c);
//cudaEventRecord(stop, 0);
//cudaEventSynchronize(stop);
//cudaEventElapsedTime(&time, start, stop);
//get run time
// cudaMemcpy(c, g_c, g_size, cudaMemcpyDeviceToHost);
//copy results back to host device
// cudaFree(g_c);
//free up unused user allocated memory on Cuda device
printf("Time = %f milliseconds\n", time);
//create a second answer matrix to use
//This is not done until now so that memory on the
//Cuda device is not wasted.
cudaMalloc(&g_d, g_size);
cudaMemcpy(g_d, d, g_size, cudaMemcpyHostToDevice);
//parallel Cuda kernel call
cudaEventRecord(start, 0);
pmultiply<<<dimGrid,threads>>>(g_a, g_b, g_d,Dim);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time = %f milliseconds\n", time);
cudaMemcpy(d, g_d, g_size, cudaMemcpyDeviceToHost);
cudaFree(g_a);
cudaFree(g_b);
cudaFree(g_d);
//free up all unused user allocated memory on Cuda device
//printf("\n");
/*The next 2 for loops print out the values of both
answer matrices. This can be used to ensure that both
kernel calls are producing the same results, and that
the results are correct. This section can be commented
out when the user only wants the timing of a run.*/
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if (i % Dim == 0)
// {
//// printf("%f ", c[i-1]);
// printf("\n");
// }
//
// else
//// printf("%f ", c[i-1]);
// }
// printf("\n");
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if ( i % Dim == 0)
// {
// printf("%f ", d[i-1]);
// printf("\n");
// }
//
// else
// printf("%f ", d[i-1]);
// }
// delete d;
} | /************************************************************
Known issues:
This program only works on matrices smaller than or equal to
256x256. 1024x1024 will cause segmentation faults and 512x512
simply causes the program to almost crash and return times of
0 for each kernel call.
The matrices must be square and all matrices must be the same
size.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define MATSIZE 128
#define THREADS_PER_BLOCK 32
//serial matrix multiplication kernel
__global__ void smultiply(int* g_a, int* g_b, int* g_c)
{
int x, y, z;
for (x = 0; x < MATSIZE; ++ x)
{
for (y = 0; y < MATSIZE; ++ y)
{
for (z = 0; z < MATSIZE; ++ z)
{
g_c[(x * MATSIZE) + y] += g_a[(x * MATSIZE) + z] * g_b[(z * MATSIZE) + y];
}
}
}
}
//parallel matrix multiplication kernel
__global__ void pmultiply(double* g_a, double* g_b, double* g_d , int dim)
{
int z;
double sum = 0.0;
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
for (z = 0; z < dim; ++ z)
{
sum += g_a[x * dim + z] * g_b[y + z * dim];
}
g_d[(x * dim) + y] = sum;
}
extern "C" void Cudamultiply(double* a, double* b, double* d, int Dim)
{
// double *d;
int i;
double *g_a, *g_b, *g_d;
int g_size = Dim * Dim * sizeof(double);
hipEvent_t start, stop;
float time;
// d=new double[Dim*Dim];
hipEventCreate(&start);
hipEventCreate(&stop);
//used for timing the Cuda run
hipMalloc(&g_a, g_size); //allocate memory on Cuda device
hipMemcpy(g_a, a, g_size, hipMemcpyHostToDevice);
//copy matrix A onto the Cuda device
hipMalloc(&g_b, g_size);
hipMemcpy(g_b, b, g_size, hipMemcpyHostToDevice);
// cudaMalloc(&g_c, g_size);
// cudaMemcpy(g_c, c, g_size, cudaMemcpyHostToDevice);
dim3 dimGrid((Dim / THREADS_PER_BLOCK), (Dim / THREADS_PER_BLOCK));
//create the needed number of grids
dim3 threads(THREADS_PER_BLOCK, THREADS_PER_BLOCK);
//create the needed number of threads in each grid
//serial Cuda kernel call
//cudaEventRecord(start, 0);
//smultiply<<<1,1>>>(g_a, g_b, g_c);
//cudaEventRecord(stop, 0);
//cudaEventSynchronize(stop);
//cudaEventElapsedTime(&time, start, stop);
//get run time
// cudaMemcpy(c, g_c, g_size, cudaMemcpyDeviceToHost);
//copy results back to host device
// cudaFree(g_c);
//free up unused user allocated memory on Cuda device
printf("Time = %f milliseconds\n", time);
//create a second answer matrix to use
//This is not done until now so that memory on the
//Cuda device is not wasted.
hipMalloc(&g_d, g_size);
hipMemcpy(g_d, d, g_size, hipMemcpyHostToDevice);
//parallel Cuda kernel call
hipEventRecord(start, 0);
pmultiply<<<dimGrid,threads>>>(g_a, g_b, g_d,Dim);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time = %f milliseconds\n", time);
hipMemcpy(d, g_d, g_size, hipMemcpyDeviceToHost);
hipFree(g_a);
hipFree(g_b);
hipFree(g_d);
//free up all unused user allocated memory on Cuda device
//printf("\n");
/*The next 2 for loops print out the values of both
answer matrices. This can be used to ensure that both
kernel calls are producing the same results, and that
the results are correct. This section can be commented
out when the user only wants the timing of a run.*/
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if (i % Dim == 0)
// {
//// printf("%f ", c[i-1]);
// printf("\n");
// }
//
// else
//// printf("%f ", c[i-1]);
// }
// printf("\n");
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if ( i % Dim == 0)
// {
// printf("%f ", d[i-1]);
// printf("\n");
// }
//
// else
// printf("%f ", d[i-1]);
// }
// delete d;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /************************************************************
Known issues:
This program only works on matrices smaller than or equal to
256x256. 1024x1024 will cause segmentation faults and 512x512
simply causes the program to almost crash and return times of
0 for each kernel call.
The matrices must be square and all matrices must be the same
size.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define MATSIZE 128
#define THREADS_PER_BLOCK 32
//serial matrix multiplication kernel
__global__ void smultiply(int* g_a, int* g_b, int* g_c)
{
int x, y, z;
for (x = 0; x < MATSIZE; ++ x)
{
for (y = 0; y < MATSIZE; ++ y)
{
for (z = 0; z < MATSIZE; ++ z)
{
g_c[(x * MATSIZE) + y] += g_a[(x * MATSIZE) + z] * g_b[(z * MATSIZE) + y];
}
}
}
}
//parallel matrix multiplication kernel
__global__ void pmultiply(double* g_a, double* g_b, double* g_d , int dim)
{
int z;
double sum = 0.0;
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
for (z = 0; z < dim; ++ z)
{
sum += g_a[x * dim + z] * g_b[y + z * dim];
}
g_d[(x * dim) + y] = sum;
}
extern "C" void Cudamultiply(double* a, double* b, double* d, int Dim)
{
// double *d;
int i;
double *g_a, *g_b, *g_d;
int g_size = Dim * Dim * sizeof(double);
hipEvent_t start, stop;
float time;
// d=new double[Dim*Dim];
hipEventCreate(&start);
hipEventCreate(&stop);
//used for timing the Cuda run
hipMalloc(&g_a, g_size); //allocate memory on Cuda device
hipMemcpy(g_a, a, g_size, hipMemcpyHostToDevice);
//copy matrix A onto the Cuda device
hipMalloc(&g_b, g_size);
hipMemcpy(g_b, b, g_size, hipMemcpyHostToDevice);
// cudaMalloc(&g_c, g_size);
// cudaMemcpy(g_c, c, g_size, cudaMemcpyHostToDevice);
dim3 dimGrid((Dim / THREADS_PER_BLOCK), (Dim / THREADS_PER_BLOCK));
//create the needed number of grids
dim3 threads(THREADS_PER_BLOCK, THREADS_PER_BLOCK);
//create the needed number of threads in each grid
//serial Cuda kernel call
//cudaEventRecord(start, 0);
//smultiply<<<1,1>>>(g_a, g_b, g_c);
//cudaEventRecord(stop, 0);
//cudaEventSynchronize(stop);
//cudaEventElapsedTime(&time, start, stop);
//get run time
// cudaMemcpy(c, g_c, g_size, cudaMemcpyDeviceToHost);
//copy results back to host device
// cudaFree(g_c);
//free up unused user allocated memory on Cuda device
printf("Time = %f milliseconds\n", time);
//create a second answer matrix to use
//This is not done until now so that memory on the
//Cuda device is not wasted.
hipMalloc(&g_d, g_size);
hipMemcpy(g_d, d, g_size, hipMemcpyHostToDevice);
//parallel Cuda kernel call
hipEventRecord(start, 0);
pmultiply<<<dimGrid,threads>>>(g_a, g_b, g_d,Dim);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time = %f milliseconds\n", time);
hipMemcpy(d, g_d, g_size, hipMemcpyDeviceToHost);
hipFree(g_a);
hipFree(g_b);
hipFree(g_d);
//free up all unused user allocated memory on Cuda device
//printf("\n");
/*The next 2 for loops print out the values of both
answer matrices. This can be used to ensure that both
kernel calls are producing the same results, and that
the results are correct. This section can be commented
out when the user only wants the timing of a run.*/
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if (i % Dim == 0)
// {
//// printf("%f ", c[i-1]);
// printf("\n");
// }
//
// else
//// printf("%f ", c[i-1]);
// }
// printf("\n");
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if ( i % Dim == 0)
// {
// printf("%f ", d[i-1]);
// printf("\n");
// }
//
// else
// printf("%f ", d[i-1]);
// }
// delete d;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9smultiplyPiS_S_
.globl _Z9smultiplyPiS_S_
.p2align 8
.type _Z9smultiplyPiS_S_,@function
_Z9smultiplyPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_mov_b32 s16, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_lshl_b32 s17, s16, 7
s_waitcnt lgkmcnt(0)
s_mov_b64 s[8:9], s[6:7]
s_mov_b32 s18, s3
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s18, s17
s_mov_b64 s[12:13], 0
s_lshl_b64 s[10:11], s[2:3], 2
s_mov_b64 s[14:15], s[8:9]
s_add_u32 s10, s0, s10
s_addc_u32 s11, s1, s11
global_load_b32 v1, v0, s[10:11]
.p2align 6
.LBB0_3:
s_add_u32 s20, s4, s12
s_addc_u32 s21, s5, s13
s_add_u32 s12, s12, 4
s_clause 0x1
global_load_b32 v2, v0, s[20:21]
global_load_b32 v3, v0, s[14:15]
s_addc_u32 s13, s13, 0
s_add_u32 s14, s14, 0x200
s_addc_u32 s15, s15, 0
s_cmpk_lg_i32 s12, 0x200
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
global_store_b32 v0, v1, s[10:11]
s_cbranch_scc1 .LBB0_3
s_add_i32 s18, s18, 1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmpk_lg_i32 s18, 0x80
s_cbranch_scc1 .LBB0_2
s_add_i32 s16, s16, 1
s_add_u32 s4, s4, 0x200
s_addc_u32 s5, s5, 0
s_cmpk_lg_i32 s16, 0x80
s_cbranch_scc1 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9smultiplyPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 22
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9smultiplyPiS_S_, .Lfunc_end0-_Z9smultiplyPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9pmultiplyPdS_S_i
.globl _Z9pmultiplyPdS_S_i
.p2align 8
.type _Z9pmultiplyPdS_S_i,@function
_Z9pmultiplyPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc1 .LBB1_2
s_branch .LBB1_4
.LBB1_3:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB1_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9pmultiplyPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9pmultiplyPdS_S_i, .Lfunc_end1-_Z9pmultiplyPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9smultiplyPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z9smultiplyPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9pmultiplyPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9pmultiplyPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /************************************************************
Known issues:
This program only works on matrices smaller than or equal to
256x256. 1024x1024 will cause segmentation faults and 512x512
simply causes the program to almost crash and return times of
0 for each kernel call.
The matrices must be square and all matrices must be the same
size.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define MATSIZE 128
#define THREADS_PER_BLOCK 32
//serial matrix multiplication kernel
__global__ void smultiply(int* g_a, int* g_b, int* g_c)
{
int x, y, z;
for (x = 0; x < MATSIZE; ++ x)
{
for (y = 0; y < MATSIZE; ++ y)
{
for (z = 0; z < MATSIZE; ++ z)
{
g_c[(x * MATSIZE) + y] += g_a[(x * MATSIZE) + z] * g_b[(z * MATSIZE) + y];
}
}
}
}
//parallel matrix multiplication kernel
__global__ void pmultiply(double* g_a, double* g_b, double* g_d , int dim)
{
int z;
double sum = 0.0;
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
for (z = 0; z < dim; ++ z)
{
sum += g_a[x * dim + z] * g_b[y + z * dim];
}
g_d[(x * dim) + y] = sum;
}
extern "C" void Cudamultiply(double* a, double* b, double* d, int Dim)
{
// double *d;
int i;
double *g_a, *g_b, *g_d;
int g_size = Dim * Dim * sizeof(double);
hipEvent_t start, stop;
float time;
// d=new double[Dim*Dim];
hipEventCreate(&start);
hipEventCreate(&stop);
//used for timing the Cuda run
hipMalloc(&g_a, g_size); //allocate memory on Cuda device
hipMemcpy(g_a, a, g_size, hipMemcpyHostToDevice);
//copy matrix A onto the Cuda device
hipMalloc(&g_b, g_size);
hipMemcpy(g_b, b, g_size, hipMemcpyHostToDevice);
// cudaMalloc(&g_c, g_size);
// cudaMemcpy(g_c, c, g_size, cudaMemcpyHostToDevice);
dim3 dimGrid((Dim / THREADS_PER_BLOCK), (Dim / THREADS_PER_BLOCK));
//create the needed number of grids
dim3 threads(THREADS_PER_BLOCK, THREADS_PER_BLOCK);
//create the needed number of threads in each grid
//serial Cuda kernel call
//cudaEventRecord(start, 0);
//smultiply<<<1,1>>>(g_a, g_b, g_c);
//cudaEventRecord(stop, 0);
//cudaEventSynchronize(stop);
//cudaEventElapsedTime(&time, start, stop);
//get run time
// cudaMemcpy(c, g_c, g_size, cudaMemcpyDeviceToHost);
//copy results back to host device
// cudaFree(g_c);
//free up unused user allocated memory on Cuda device
printf("Time = %f milliseconds\n", time);
//create a second answer matrix to use
//This is not done until now so that memory on the
//Cuda device is not wasted.
hipMalloc(&g_d, g_size);
hipMemcpy(g_d, d, g_size, hipMemcpyHostToDevice);
//parallel Cuda kernel call
hipEventRecord(start, 0);
pmultiply<<<dimGrid,threads>>>(g_a, g_b, g_d,Dim);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time = %f milliseconds\n", time);
hipMemcpy(d, g_d, g_size, hipMemcpyDeviceToHost);
hipFree(g_a);
hipFree(g_b);
hipFree(g_d);
//free up all unused user allocated memory on Cuda device
//printf("\n");
/*The next 2 for loops print out the values of both
answer matrices. This can be used to ensure that both
kernel calls are producing the same results, and that
the results are correct. This section can be commented
out when the user only wants the timing of a run.*/
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if (i % Dim == 0)
// {
//// printf("%f ", c[i-1]);
// printf("\n");
// }
//
// else
//// printf("%f ", c[i-1]);
// }
// printf("\n");
// for (i = 1; i <= Dim * Dim; ++ i)
// {
// if ( i % Dim == 0)
// {
// printf("%f ", d[i-1]);
// printf("\n");
// }
//
// else
// printf("%f ", d[i-1]);
// }
// delete d;
} | .text
.file "cudamatrix.hip"
.globl _Z24__device_stub__smultiplyPiS_S_ # -- Begin function _Z24__device_stub__smultiplyPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__smultiplyPiS_S_,@function
_Z24__device_stub__smultiplyPiS_S_: # @_Z24__device_stub__smultiplyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9smultiplyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__smultiplyPiS_S_, .Lfunc_end0-_Z24__device_stub__smultiplyPiS_S_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__pmultiplyPdS_S_i # -- Begin function _Z24__device_stub__pmultiplyPdS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__pmultiplyPdS_S_i,@function
_Z24__device_stub__pmultiplyPdS_S_i: # @_Z24__device_stub__pmultiplyPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9pmultiplyPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__pmultiplyPdS_S_i, .Lfunc_end1-_Z24__device_stub__pmultiplyPdS_S_i
.cfi_endproc
# -- End function
.globl Cudamultiply # -- Begin function Cudamultiply
.p2align 4, 0x90
.type Cudamultiply,@function
Cudamultiply: # @Cudamultiply
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movl %ecx, %ebp
imull %ecx, %ebp
shll $3, %ebp
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 31(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $5, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r15d, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9pmultiplyPdS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size Cudamultiply, .Lfunc_end2-Cudamultiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9smultiplyPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9pmultiplyPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9smultiplyPiS_S_,@object # @_Z9smultiplyPiS_S_
.section .rodata,"a",@progbits
.globl _Z9smultiplyPiS_S_
.p2align 3, 0x0
_Z9smultiplyPiS_S_:
.quad _Z24__device_stub__smultiplyPiS_S_
.size _Z9smultiplyPiS_S_, 8
.type _Z9pmultiplyPdS_S_i,@object # @_Z9pmultiplyPdS_S_i
.globl _Z9pmultiplyPdS_S_i
.p2align 3, 0x0
_Z9pmultiplyPdS_S_i:
.quad _Z24__device_stub__pmultiplyPdS_S_i
.size _Z9pmultiplyPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time = %f milliseconds\n"
.size .L.str, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9smultiplyPiS_S_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9pmultiplyPdS_S_i"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__smultiplyPiS_S_
.addrsig_sym _Z24__device_stub__pmultiplyPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9smultiplyPiS_S_
.addrsig_sym _Z9pmultiplyPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c482_00000000-6_cudamatrix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_
.type _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_, @function
_Z32__device_stub__Z9smultiplyPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9smultiplyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_, .-_Z32__device_stub__Z9smultiplyPiS_S_PiS_S_
.globl _Z9smultiplyPiS_S_
.type _Z9smultiplyPiS_S_, @function
_Z9smultiplyPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9smultiplyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9smultiplyPiS_S_, .-_Z9smultiplyPiS_S_
.globl _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
.type _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i, @function
_Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9pmultiplyPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i, .-_Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
.globl _Z9pmultiplyPdS_S_i
.type _Z9pmultiplyPdS_S_i, @function
_Z9pmultiplyPdS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9pmultiplyPdS_S_i, .-_Z9pmultiplyPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Time = %f milliseconds\n"
.text
.globl Cudamultiply
.type Cudamultiply, @function
Cudamultiply:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl %ebp, %ebx
imull %ebp, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leal 31(%rbp), %eax
testl %ebp, %ebp
cmovns %ebp, %eax
sarl $5, %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $1, 68(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9pmultiplyPdS_S_iPdS_S_i
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size Cudamultiply, .-Cudamultiply
.section .rodata.str1.1
.LC1:
.string "_Z9pmultiplyPdS_S_i"
.LC2:
.string "_Z9smultiplyPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9pmultiplyPdS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9smultiplyPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudamatrix.hip"
.globl _Z24__device_stub__smultiplyPiS_S_ # -- Begin function _Z24__device_stub__smultiplyPiS_S_
.p2align 4, 0x90
.type _Z24__device_stub__smultiplyPiS_S_,@function
_Z24__device_stub__smultiplyPiS_S_: # @_Z24__device_stub__smultiplyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9smultiplyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__smultiplyPiS_S_, .Lfunc_end0-_Z24__device_stub__smultiplyPiS_S_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__pmultiplyPdS_S_i # -- Begin function _Z24__device_stub__pmultiplyPdS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__pmultiplyPdS_S_i,@function
_Z24__device_stub__pmultiplyPdS_S_i: # @_Z24__device_stub__pmultiplyPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9pmultiplyPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__pmultiplyPdS_S_i, .Lfunc_end1-_Z24__device_stub__pmultiplyPdS_S_i
.cfi_endproc
# -- End function
.globl Cudamultiply # -- Begin function Cudamultiply
.p2align 4, 0x90
.type Cudamultiply,@function
Cudamultiply: # @Cudamultiply
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
movl %ecx, %ebp
imull %ecx, %ebp
shll $3, %ebp
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 31(%r15), %eax
testl %r15d, %r15d
cmovnsl %r15d, %eax
sarl $5, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r15d, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9pmultiplyPdS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size Cudamultiply, .Lfunc_end2-Cudamultiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9smultiplyPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9pmultiplyPdS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9smultiplyPiS_S_,@object # @_Z9smultiplyPiS_S_
.section .rodata,"a",@progbits
.globl _Z9smultiplyPiS_S_
.p2align 3, 0x0
_Z9smultiplyPiS_S_:
.quad _Z24__device_stub__smultiplyPiS_S_
.size _Z9smultiplyPiS_S_, 8
.type _Z9pmultiplyPdS_S_i,@object # @_Z9pmultiplyPdS_S_i
.globl _Z9pmultiplyPdS_S_i
.p2align 3, 0x0
_Z9pmultiplyPdS_S_i:
.quad _Z24__device_stub__pmultiplyPdS_S_i
.size _Z9pmultiplyPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time = %f milliseconds\n"
.size .L.str, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9smultiplyPiS_S_"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z9pmultiplyPdS_S_i"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__smultiplyPiS_S_
.addrsig_sym _Z24__device_stub__pmultiplyPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9smultiplyPiS_S_
.addrsig_sym _Z9pmultiplyPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<unistd.h>
#include<stdbool.h>
#include <cuda.h>
#include <cuda_runtime.h>
extern "C" void allocateMemory(int **arr, int arraySize)
{
cudaMallocManaged(arr, ( (arraySize* sizeof(int))));
}
extern "C" void callCudaFree(int* local)
{
cudaFree(local);
}
//extern void callMPI(int* local,int* arr,int arrSize,int mpi_size,int x_rank);
extern "C" void cudaInit( int myrank)
{
int cE;
int cudaDeviceCount = 1;
if( (cE = cudaGetDeviceCount( &cudaDeviceCount)) != cudaSuccess )
{
printf(" Unable to determine cuda device count, error is %d, count is %d\n",
cE, cudaDeviceCount );
exit(-1);
}
if( (cE = cudaSetDevice( myrank % cudaDeviceCount )) != cudaSuccess )
{
printf(" Unable to have rank %d set to cuda device %d, error is %d \n",
myrank, (myrank % cudaDeviceCount), cE);
exit(-1);
}
}
__global__ void mergeKernel(int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
//nt *prev_local = NULL;
//int *next_local = NULL;
bool sameVal = false;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int global_idx = i + arrSize / mpi_size * mpi_rank;
int x = global_idx ^ j;
int x_rank = x / (arrSize / mpi_size);
if ( global_idx >= x ) {
if ( mpi_rank == x_rank ) {
if(sameVal == false)
{
sameVal = true;
}
}
else {
if ( prev_local == NULL ) {
//prev_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&prev_local,arrSize/mpi_size);
prev_local = arr + arrSize / mpi_size * x_rank;
//callMPI(prev_local,arr,arrSize,mpi_size,x_rank);
}
if ( (sizeCompare & x) == 0 && arr[i] < prev_local[i] ) {
arr[i] = prev_local[i];
}
if ( (sizeCompare & x) != 0 && arr[i] > prev_local[i] ) {
arr[i] = prev_local[i];
}
}
}
else {
if ( x_rank == mpi_rank ) {
int y = x - arrSize / mpi_size * mpi_rank;
if ( (global_idx & sizeCompare) == 0 && arr[i] > arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
}
else {
if ( next_local == NULL ) {
//next_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&next_local,arrSize/mpi_size);
next_local = arr + arrSize / mpi_size * x_rank;
//callMPI(next_local,arr,arrSize,mpi_size,x_rank);
}
if ( (global_idx & sizeCompare) == 0 && arr[i] > next_local[i] ) {
arr[i] = next_local[i];
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < next_local[i] ) {
arr[i] = next_local[i];
}
}
}
}
extern "C" void mergeKernelLaunch(int blockSize,int threadsCount,int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
mergeKernel<<<blockSize,threadsCount>>>(j, mpi_size, mpi_rank, arr, arrSize, sizeCompare, prev_local, next_local);
} | code for sm_80
Function : _Z11mergeKerneliiiPiiiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x164] ; /* 0x0000590000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0050*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fcc000f8e3c3f */
/*0060*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0090*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00c0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00d0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00e0*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc60000000000 */
/*00f0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R0, R5.reuse, R0, R4 ; /* 0x0000000005007224 */
/* 0x040fe400078e0204 */
/*0130*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0140*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0150*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0160*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f45270 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0190*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e360000002100 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0003 */
/*01c0*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0a09 */
/*01d0*/ @!P2 LOP3.LUT R9, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff09aa12 */
/* 0x000fe200078e33ff */
/*01e0*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fc600078e0205 */
/*01f0*/ IABS R8, R9.reuse ; /* 0x0000000900087213 */
/* 0x080fe40000000000 */
/*0200*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fe20000000000 */
/*0210*/ IMAD R0, R9, c[0x0][0x168], R4 ; /* 0x00005a0009007a24 */
/* 0x000fe200078e0204 */
/*0220*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e260000209400 */
/*0230*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*0240*/ LOP3.LUT R5, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000057a12 */
/* 0x000fc800078e3cff */
/*0250*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0260*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*0270*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fc80000000000 */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*02b0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fc800078e0002 */
/*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*02e0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*02f0*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD R3, R2, R6, R3 ; /* 0x0000000602037224 */
/* 0x000fe400078e0203 */
/*0310*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0320*/ ISETP.GT.U32.AND P2, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f44070 */
/*0330*/ @!P2 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a08 */
/*0340*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*0350*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0370*/ LOP3.LUT R3, R5, R9, RZ, 0x3c, !PT ; /* 0x0000000905037212 */
/* 0x000fc800078e3cff */
/*0380*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0390*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fc60003f06270 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*03c0*/ IMAD.WIDE R2, R4, R7, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0207 */
/*03d0*/ @!P1 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0a06 */
/*03e0*/ @!P2 LOP3.LUT R6, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff06a212 */
/* 0x000fc600078e33ff */
/*03f0*/ @!P0 BRA 0x550 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f05270 */
/*0410*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0420*/ IMAD R6, R9, R6, RZ ; /* 0x0000000609067224 */
/* 0x000fe200078e02ff */
/*0430*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05070 */
/*0440*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000164000c1e1900 */
/*0450*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0460*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fc80003f05300 */
/*0470*/ SEL R6, R6, c[0x0][0x180], !P0 ; /* 0x0000600006067a07 */
/* 0x000fe40004000000 */
/*0480*/ SEL R7, R7, c[0x0][0x184], !P0 ; /* 0x0000610007077a07 */
/* 0x000fca0004000000 */
/*0490*/ IMAD.WIDE R6, R4, 0x4, R6 ; /* 0x0000000404067825 */
/* 0x000fcc00078e0206 */
/*04a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000162000c1e1900 */
/*04b0*/ LOP3.LUT P0, RZ, R5, c[0x0][0x17c], RZ, 0xc0, !PT ; /* 0x00005f0005ff7a12 */
/* 0x000fda000780c0ff */
/*04c0*/ @!P0 BRA 0x510 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x021fda0003f04270 */
/*04e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x021fda0003f06270 */
/*0520*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0530*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f05270 */
/*0560*/ @!P0 BRA 0x6a0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R6, R9, R6, RZ ; /* 0x0000000609067224 */
/* 0x000fe200078e02ff */
/*0580*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc60003f05070 */
/*0590*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*05a0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fc80003f05300 */
/*05b0*/ SEL R6, R6, c[0x0][0x188], !P0 ; /* 0x0000620006067a07 */
/* 0x000fe40004000000 */
/*05c0*/ SEL R7, R7, c[0x0][0x18c], !P0 ; /* 0x0000630007077a07 */
/* 0x000fca0004000000 */
/*05d0*/ IMAD.WIDE R4, R4, 0x4, R6 ; /* 0x0000000404047825 */
/* 0x000fe400078e0206 */
/*05e0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000168000c1e1900 */
/*05f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000162000c1e1900 */
/*0600*/ LOP3.LUT P0, RZ, R0, c[0x0][0x17c], RZ, 0xc0, !PT ; /* 0x00005f0000ff7a12 */
/* 0x000fda000780c0ff */
/*0610*/ @!P0 BRA 0x660 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x021fda0003f06270 */
/*0630*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0640*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x021fda0003f04270 */
/*0670*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0680*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.MOV R4, RZ, RZ, -R9 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a09 */
/*06b0*/ IMAD R5, R4, c[0x0][0x168], R5 ; /* 0x00005a0004057a24 */
/* 0x000fc800078e0205 */
/*06c0*/ IMAD.WIDE R4, R5, R7, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fe400078e0207 */
/*06d0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*06e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*06f0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x17c], RZ, 0xc0, !PT ; /* 0x00005f0000ff7a12 */
/* 0x000fda000780c0ff */
/*0700*/ @!P0 BRA 0x760 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0720*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0730*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0740*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0770*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0780*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0790*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<unistd.h>
#include<stdbool.h>
#include <cuda.h>
#include <cuda_runtime.h>
extern "C" void allocateMemory(int **arr, int arraySize)
{
cudaMallocManaged(arr, ( (arraySize* sizeof(int))));
}
extern "C" void callCudaFree(int* local)
{
cudaFree(local);
}
//extern void callMPI(int* local,int* arr,int arrSize,int mpi_size,int x_rank);
extern "C" void cudaInit( int myrank)
{
int cE;
int cudaDeviceCount = 1;
if( (cE = cudaGetDeviceCount( &cudaDeviceCount)) != cudaSuccess )
{
printf(" Unable to determine cuda device count, error is %d, count is %d\n",
cE, cudaDeviceCount );
exit(-1);
}
if( (cE = cudaSetDevice( myrank % cudaDeviceCount )) != cudaSuccess )
{
printf(" Unable to have rank %d set to cuda device %d, error is %d \n",
myrank, (myrank % cudaDeviceCount), cE);
exit(-1);
}
}
__global__ void mergeKernel(int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
//nt *prev_local = NULL;
//int *next_local = NULL;
bool sameVal = false;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int global_idx = i + arrSize / mpi_size * mpi_rank;
int x = global_idx ^ j;
int x_rank = x / (arrSize / mpi_size);
if ( global_idx >= x ) {
if ( mpi_rank == x_rank ) {
if(sameVal == false)
{
sameVal = true;
}
}
else {
if ( prev_local == NULL ) {
//prev_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&prev_local,arrSize/mpi_size);
prev_local = arr + arrSize / mpi_size * x_rank;
//callMPI(prev_local,arr,arrSize,mpi_size,x_rank);
}
if ( (sizeCompare & x) == 0 && arr[i] < prev_local[i] ) {
arr[i] = prev_local[i];
}
if ( (sizeCompare & x) != 0 && arr[i] > prev_local[i] ) {
arr[i] = prev_local[i];
}
}
}
else {
if ( x_rank == mpi_rank ) {
int y = x - arrSize / mpi_size * mpi_rank;
if ( (global_idx & sizeCompare) == 0 && arr[i] > arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
}
else {
if ( next_local == NULL ) {
//next_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&next_local,arrSize/mpi_size);
next_local = arr + arrSize / mpi_size * x_rank;
//callMPI(next_local,arr,arrSize,mpi_size,x_rank);
}
if ( (global_idx & sizeCompare) == 0 && arr[i] > next_local[i] ) {
arr[i] = next_local[i];
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < next_local[i] ) {
arr[i] = next_local[i];
}
}
}
}
extern "C" void mergeKernelLaunch(int blockSize,int threadsCount,int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
mergeKernel<<<blockSize,threadsCount>>>(j, mpi_size, mpi_rank, arr, arrSize, sizeCompare, prev_local, next_local);
} | .file "tmpxft_0003930b_00000000-6_bitonicCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl allocateMemory
.type allocateMemory, @function
allocateMemory:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %esi, %rsi
salq $2, %rsi
movl $1, %edx
call cudaMallocManaged@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size allocateMemory, .-allocateMemory
.globl callCudaFree
.type callCudaFree, @function
callCudaFree:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size callCudaFree, .-callCudaFree
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " Unable to determine cuda device count, error is %d, count is %d\n"
.align 8
.LC1:
.string " Unable to have rank %d set to cuda device %d, error is %d \n"
.text
.globl cudaInit
.type cudaInit, @function
cudaInit:
.LFB2072:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $1, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl %ebx, %eax
cltd
idivl 4(%rsp)
movl %edx, %edi
call cudaSetDevice@PLT
movl %eax, %r8d
testl %eax, %eax
jne .L13
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl 4(%rsp), %ecx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
movl %ebx, %eax
cltd
idivl 4(%rsp)
movl %edx, %ecx
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size cudaInit, .-cudaInit
.globl _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
.type _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_, @function
_Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_:
.LFB2098:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 32(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11mergeKerneliiiPiiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_, .-_Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
.globl _Z11mergeKerneliiiPiiiS_S_
.type _Z11mergeKerneliiiPiiiS_S_, @function
_Z11mergeKerneliiiPiiiS_S_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z11mergeKerneliiiPiiiS_S_, .-_Z11mergeKerneliiiPiiiS_S_
.globl mergeKernelLaunch
.type mergeKernelLaunch, @function
mergeKernelLaunch:
.LFB2073:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movq %r9, %r13
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
movl 104(%rsp), %r9d
movl 96(%rsp), %r8d
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
addq $16, %rsp
.cfi_def_cfa_offset 80
jmp .L23
.cfi_endproc
.LFE2073:
.size mergeKernelLaunch, .-mergeKernelLaunch
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z11mergeKerneliiiPiiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mergeKerneliiiPiiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<unistd.h>
#include<stdbool.h>
#include <cuda.h>
#include <cuda_runtime.h>
extern "C" void allocateMemory(int **arr, int arraySize)
{
cudaMallocManaged(arr, ( (arraySize* sizeof(int))));
}
extern "C" void callCudaFree(int* local)
{
cudaFree(local);
}
//extern void callMPI(int* local,int* arr,int arrSize,int mpi_size,int x_rank);
extern "C" void cudaInit( int myrank)
{
int cE;
int cudaDeviceCount = 1;
if( (cE = cudaGetDeviceCount( &cudaDeviceCount)) != cudaSuccess )
{
printf(" Unable to determine cuda device count, error is %d, count is %d\n",
cE, cudaDeviceCount );
exit(-1);
}
if( (cE = cudaSetDevice( myrank % cudaDeviceCount )) != cudaSuccess )
{
printf(" Unable to have rank %d set to cuda device %d, error is %d \n",
myrank, (myrank % cudaDeviceCount), cE);
exit(-1);
}
}
__global__ void mergeKernel(int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
//nt *prev_local = NULL;
//int *next_local = NULL;
bool sameVal = false;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int global_idx = i + arrSize / mpi_size * mpi_rank;
int x = global_idx ^ j;
int x_rank = x / (arrSize / mpi_size);
if ( global_idx >= x ) {
if ( mpi_rank == x_rank ) {
if(sameVal == false)
{
sameVal = true;
}
}
else {
if ( prev_local == NULL ) {
//prev_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&prev_local,arrSize/mpi_size);
prev_local = arr + arrSize / mpi_size * x_rank;
//callMPI(prev_local,arr,arrSize,mpi_size,x_rank);
}
if ( (sizeCompare & x) == 0 && arr[i] < prev_local[i] ) {
arr[i] = prev_local[i];
}
if ( (sizeCompare & x) != 0 && arr[i] > prev_local[i] ) {
arr[i] = prev_local[i];
}
}
}
else {
if ( x_rank == mpi_rank ) {
int y = x - arrSize / mpi_size * mpi_rank;
if ( (global_idx & sizeCompare) == 0 && arr[i] > arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
}
else {
if ( next_local == NULL ) {
//next_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&next_local,arrSize/mpi_size);
next_local = arr + arrSize / mpi_size * x_rank;
//callMPI(next_local,arr,arrSize,mpi_size,x_rank);
}
if ( (global_idx & sizeCompare) == 0 && arr[i] > next_local[i] ) {
arr[i] = next_local[i];
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < next_local[i] ) {
arr[i] = next_local[i];
}
}
}
}
extern "C" void mergeKernelLaunch(int blockSize,int threadsCount,int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
mergeKernel<<<blockSize,threadsCount>>>(j, mpi_size, mpi_rank, arr, arrSize, sizeCompare, prev_local, next_local);
} | #include<stdio.h>
#include<stdlib.h>
#include<unistd.h>
#include<stdbool.h>
#include <hip/hip_runtime.h>
extern "C" void allocateMemory(int **arr, int arraySize)
{
hipMallocManaged(arr, ( (arraySize* sizeof(int))));
}
extern "C" void callCudaFree(int* local)
{
hipFree(local);
}
//extern void callMPI(int* local,int* arr,int arrSize,int mpi_size,int x_rank);
extern "C" void cudaInit( int myrank)
{
int cE;
int cudaDeviceCount = 1;
if( (cE = hipGetDeviceCount( &cudaDeviceCount)) != hipSuccess )
{
printf(" Unable to determine cuda device count, error is %d, count is %d\n",
cE, cudaDeviceCount );
exit(-1);
}
if( (cE = hipSetDevice( myrank % cudaDeviceCount )) != hipSuccess )
{
printf(" Unable to have rank %d set to cuda device %d, error is %d \n",
myrank, (myrank % cudaDeviceCount), cE);
exit(-1);
}
}
__global__ void mergeKernel(int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
//nt *prev_local = NULL;
//int *next_local = NULL;
bool sameVal = false;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int global_idx = i + arrSize / mpi_size * mpi_rank;
int x = global_idx ^ j;
int x_rank = x / (arrSize / mpi_size);
if ( global_idx >= x ) {
if ( mpi_rank == x_rank ) {
if(sameVal == false)
{
sameVal = true;
}
}
else {
if ( prev_local == NULL ) {
//prev_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&prev_local,arrSize/mpi_size);
prev_local = arr + arrSize / mpi_size * x_rank;
//callMPI(prev_local,arr,arrSize,mpi_size,x_rank);
}
if ( (sizeCompare & x) == 0 && arr[i] < prev_local[i] ) {
arr[i] = prev_local[i];
}
if ( (sizeCompare & x) != 0 && arr[i] > prev_local[i] ) {
arr[i] = prev_local[i];
}
}
}
else {
if ( x_rank == mpi_rank ) {
int y = x - arrSize / mpi_size * mpi_rank;
if ( (global_idx & sizeCompare) == 0 && arr[i] > arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
}
else {
if ( next_local == NULL ) {
//next_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&next_local,arrSize/mpi_size);
next_local = arr + arrSize / mpi_size * x_rank;
//callMPI(next_local,arr,arrSize,mpi_size,x_rank);
}
if ( (global_idx & sizeCompare) == 0 && arr[i] > next_local[i] ) {
arr[i] = next_local[i];
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < next_local[i] ) {
arr[i] = next_local[i];
}
}
}
}
extern "C" void mergeKernelLaunch(int blockSize,int threadsCount,int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
mergeKernel<<<blockSize,threadsCount>>>(j, mpi_size, mpi_rank, arr, arrSize, sizeCompare, prev_local, next_local);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<unistd.h>
#include<stdbool.h>
#include <hip/hip_runtime.h>
extern "C" void allocateMemory(int **arr, int arraySize)
{
hipMallocManaged(arr, ( (arraySize* sizeof(int))));
}
extern "C" void callCudaFree(int* local)
{
hipFree(local);
}
//extern void callMPI(int* local,int* arr,int arrSize,int mpi_size,int x_rank);
extern "C" void cudaInit( int myrank)
{
int cE;
int cudaDeviceCount = 1;
if( (cE = hipGetDeviceCount( &cudaDeviceCount)) != hipSuccess )
{
printf(" Unable to determine cuda device count, error is %d, count is %d\n",
cE, cudaDeviceCount );
exit(-1);
}
if( (cE = hipSetDevice( myrank % cudaDeviceCount )) != hipSuccess )
{
printf(" Unable to have rank %d set to cuda device %d, error is %d \n",
myrank, (myrank % cudaDeviceCount), cE);
exit(-1);
}
}
__global__ void mergeKernel(int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
//nt *prev_local = NULL;
//int *next_local = NULL;
bool sameVal = false;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int global_idx = i + arrSize / mpi_size * mpi_rank;
int x = global_idx ^ j;
int x_rank = x / (arrSize / mpi_size);
if ( global_idx >= x ) {
if ( mpi_rank == x_rank ) {
if(sameVal == false)
{
sameVal = true;
}
}
else {
if ( prev_local == NULL ) {
//prev_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&prev_local,arrSize/mpi_size);
prev_local = arr + arrSize / mpi_size * x_rank;
//callMPI(prev_local,arr,arrSize,mpi_size,x_rank);
}
if ( (sizeCompare & x) == 0 && arr[i] < prev_local[i] ) {
arr[i] = prev_local[i];
}
if ( (sizeCompare & x) != 0 && arr[i] > prev_local[i] ) {
arr[i] = prev_local[i];
}
}
}
else {
if ( x_rank == mpi_rank ) {
int y = x - arrSize / mpi_size * mpi_rank;
if ( (global_idx & sizeCompare) == 0 && arr[i] > arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
}
else {
if ( next_local == NULL ) {
//next_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&next_local,arrSize/mpi_size);
next_local = arr + arrSize / mpi_size * x_rank;
//callMPI(next_local,arr,arrSize,mpi_size,x_rank);
}
if ( (global_idx & sizeCompare) == 0 && arr[i] > next_local[i] ) {
arr[i] = next_local[i];
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < next_local[i] ) {
arr[i] = next_local[i];
}
}
}
}
extern "C" void mergeKernelLaunch(int blockSize,int threadsCount,int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
mergeKernel<<<blockSize,threadsCount>>>(j, mpi_size, mpi_rank, arr, arrSize, sizeCompare, prev_local, next_local);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11mergeKerneliiiPiiiS_S_
.globl _Z11mergeKerneliiiPiiiS_S_
.p2align 8
.type _Z11mergeKerneliiiPiiiS_S_,@function
_Z11mergeKerneliiiPiiiS_S_:
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s3, 31
s_ashr_i32 s13, s6, 31
s_add_i32 s3, s3, s9
s_add_i32 s6, s6, s13
s_xor_b32 s3, s3, s9
s_xor_b32 s6, s6, s13
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s12, 0, s3
s_and_b32 s10, s10, 0xffff
s_xor_b32 s9, s13, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s11, v1
s_mul_i32 s12, s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s12, s11, s12
s_add_i32 s11, s11, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s6, s11
s_mul_i32 s12, s11, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s6, s6, s12
s_add_i32 s12, s11, 1
s_sub_i32 s13, s6, s3
s_cmp_ge_u32 s6, s3
s_cselect_b32 s11, s12, s11
s_cselect_b32 s6, s13, s6
s_add_i32 s12, s11, 1
s_cmp_ge_u32 s6, s3
s_cselect_b32 s3, s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s9
s_sub_i32 s6, s3, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s6, 31
s_add_i32 s3, s6, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_xor_b32 s11, s3, s9
s_mul_i32 s3, s6, s8
v_cvt_f32_u32_e32 v1, s11
v_rcp_iflag_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_sub_i32 s10, 0, s11
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v5, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, s2, v5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v6
v_mul_lo_u32 v2, s10, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v6, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s9, v3
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v7, s11, v2
v_cmp_le_u32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_cmp_ne_u32_e32 vcc_lo, s8, v0
s_mov_b32 s8, exec_lo
v_cmpx_ge_i32_e64 v5, v6
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_12
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_11
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11
s_cmp_lg_u64 s[10:11], 0
s_cbranch_scc1 .LBB0_4
v_mul_lo_u32 v2, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s4, v3
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_co_u32 v0, s2, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, s5, v8, s2
v_add_co_u32 v7, s2, v3, v7
v_add_co_ci_u32_e64 v8, s2, v4, v8, s2
v_and_b32_e32 v4, s7, v6
global_load_b32 v3, v[0:1], off
global_load_b32 v2, v[7:8], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_8
s_mov_b32 s11, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v3, v2
s_cbranch_execz .LBB0_7
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_8:
s_and_not1_saveexec_b32 s2, s10
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_11
global_store_b32 v[0:1], v2, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_12:
s_and_not1_saveexec_b32 s2, s8
s_cbranch_execz .LBB0_33
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_25
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt vmcnt(1) lgkmcnt(0)
v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
s_cmp_lg_u64 s[0:1], 0
s_cbranch_scc1 .LBB0_16
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_16:
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, v3, v6
v_add_co_ci_u32_e32 v7, vcc_lo, v4, v7, vcc_lo
v_and_b32_e32 v4, s7, v5
global_load_b32 v3, v[0:1], off
global_load_b32 v2, v[6:7], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_20
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v2
s_cbranch_execz .LBB0_19
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_20:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_24
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v3, v2
s_cbranch_execz .LBB0_23
global_store_b32 v[0:1], v2, off
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
.LBB0_25:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_33
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v3, s3, v6
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v5, s7, v5
s_mov_b32 s0, exec_lo
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v5
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_30
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v6
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v4, off
s_or_b32 exec_lo, exec_lo, s1
.LBB0_30:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_33
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v4, v6
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v4, off
.LBB0_33:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mergeKerneliiiPiiiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11mergeKerneliiiPiiiS_S_, .Lfunc_end0-_Z11mergeKerneliiiPiiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mergeKerneliiiPiiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mergeKerneliiiPiiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<unistd.h>
#include<stdbool.h>
#include <hip/hip_runtime.h>
extern "C" void allocateMemory(int **arr, int arraySize)
{
hipMallocManaged(arr, ( (arraySize* sizeof(int))));
}
extern "C" void callCudaFree(int* local)
{
hipFree(local);
}
//extern void callMPI(int* local,int* arr,int arrSize,int mpi_size,int x_rank);
extern "C" void cudaInit( int myrank)
{
int cE;
int cudaDeviceCount = 1;
if( (cE = hipGetDeviceCount( &cudaDeviceCount)) != hipSuccess )
{
printf(" Unable to determine cuda device count, error is %d, count is %d\n",
cE, cudaDeviceCount );
exit(-1);
}
if( (cE = hipSetDevice( myrank % cudaDeviceCount )) != hipSuccess )
{
printf(" Unable to have rank %d set to cuda device %d, error is %d \n",
myrank, (myrank % cudaDeviceCount), cE);
exit(-1);
}
}
__global__ void mergeKernel(int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
//nt *prev_local = NULL;
//int *next_local = NULL;
bool sameVal = false;
int i = blockIdx.x*blockDim.x + threadIdx.x;
int global_idx = i + arrSize / mpi_size * mpi_rank;
int x = global_idx ^ j;
int x_rank = x / (arrSize / mpi_size);
if ( global_idx >= x ) {
if ( mpi_rank == x_rank ) {
if(sameVal == false)
{
sameVal = true;
}
}
else {
if ( prev_local == NULL ) {
//prev_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&prev_local,arrSize/mpi_size);
prev_local = arr + arrSize / mpi_size * x_rank;
//callMPI(prev_local,arr,arrSize,mpi_size,x_rank);
}
if ( (sizeCompare & x) == 0 && arr[i] < prev_local[i] ) {
arr[i] = prev_local[i];
}
if ( (sizeCompare & x) != 0 && arr[i] > prev_local[i] ) {
arr[i] = prev_local[i];
}
}
}
else {
if ( x_rank == mpi_rank ) {
int y = x - arrSize / mpi_size * mpi_rank;
if ( (global_idx & sizeCompare) == 0 && arr[i] > arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < arr[y] ) {
int temp = arr[i];
arr[i] = arr[y];
arr[y] = temp;
}
}
else {
if ( next_local == NULL ) {
//next_local = calloc(arrSize / mpi_size, sizeof(int));
//allocateMemory(&next_local,arrSize/mpi_size);
next_local = arr + arrSize / mpi_size * x_rank;
//callMPI(next_local,arr,arrSize,mpi_size,x_rank);
}
if ( (global_idx & sizeCompare) == 0 && arr[i] > next_local[i] ) {
arr[i] = next_local[i];
}
if ( (global_idx & sizeCompare) != 0 && arr[i] < next_local[i] ) {
arr[i] = next_local[i];
}
}
}
}
extern "C" void mergeKernelLaunch(int blockSize,int threadsCount,int j, int mpi_size, int mpi_rank, int *arr, int arrSize, int sizeCompare,int* prev_local, int* next_local)
{
mergeKernel<<<blockSize,threadsCount>>>(j, mpi_size, mpi_rank, arr, arrSize, sizeCompare, prev_local, next_local);
} | .text
.file "bitonicCuda.hip"
.globl allocateMemory # -- Begin function allocateMemory
.p2align 4, 0x90
.type allocateMemory,@function
allocateMemory: # @allocateMemory
.cfi_startproc
# %bb.0:
movslq %esi, %rsi
shlq $2, %rsi
movl $1, %edx
jmp hipMallocManaged # TAILCALL
.Lfunc_end0:
.size allocateMemory, .Lfunc_end0-allocateMemory
.cfi_endproc
# -- End function
.globl callCudaFree # -- Begin function callCudaFree
.p2align 4, 0x90
.type callCudaFree,@function
callCudaFree: # @callCudaFree
.cfi_startproc
# %bb.0:
jmp hipFree # TAILCALL
.Lfunc_end1:
.size callCudaFree, .Lfunc_end1-callCudaFree
.cfi_endproc
# -- End function
.globl cudaInit # -- Begin function cudaInit
.p2align 4, 0x90
.type cudaInit,@function
cudaInit: # @cudaInit
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl %edi, %ebx
movl $1, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %ecx
testl %eax, %eax
jne .LBB2_3
# %bb.1:
movl %ebx, %eax
cltd
idivl %ecx
movl %edx, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_4
# %bb.2:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_3:
.cfi_def_cfa_offset 32
movl $.L.str, %edi
movl %eax, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB2_4:
movl %eax, %ecx
movl %ebx, %eax
cltd
idivl 12(%rsp)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size cudaInit, .Lfunc_end2-cudaInit
.cfi_endproc
# -- End function
.globl _Z26__device_stub__mergeKerneliiiPiiiS_S_ # -- Begin function _Z26__device_stub__mergeKerneliiiPiiiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__mergeKerneliiiPiiiS_S_,@function
_Z26__device_stub__mergeKerneliiiPiiiS_S_: # @_Z26__device_stub__mergeKerneliiiPiiiS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11mergeKerneliiiPiiiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z26__device_stub__mergeKerneliiiPiiiS_S_, .Lfunc_end3-_Z26__device_stub__mergeKerneliiiPiiiS_S_
.cfi_endproc
# -- End function
.globl mergeKernelLaunch # -- Begin function mergeKernelLaunch
.p2align 4, 0x90
.type mergeKernelLaunch,@function
mergeKernelLaunch: # @mergeKernelLaunch
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %edi, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %esi, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl 216(%rsp), %edx
movl 208(%rsp), %esi
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 88(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11mergeKerneliiiPiiiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size mergeKernelLaunch, .Lfunc_end4-mergeKernelLaunch
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11mergeKerneliiiPiiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Unable to determine cuda device count, error is %d, count is %d\n"
.size .L.str, 66
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Unable to have rank %d set to cuda device %d, error is %d \n"
.size .L.str.1, 61
.type _Z11mergeKerneliiiPiiiS_S_,@object # @_Z11mergeKerneliiiPiiiS_S_
.section .rodata,"a",@progbits
.globl _Z11mergeKerneliiiPiiiS_S_
.p2align 3, 0x0
_Z11mergeKerneliiiPiiiS_S_:
.quad _Z26__device_stub__mergeKerneliiiPiiiS_S_
.size _Z11mergeKerneliiiPiiiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11mergeKerneliiiPiiiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__mergeKerneliiiPiiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11mergeKerneliiiPiiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11mergeKerneliiiPiiiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x164] ; /* 0x0000590000057a13 */
/* 0x000fe20000000000 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*0050*/ ULOP3.LUT UR4, UR4, UR5, URZ, 0x3c, !UPT ; /* 0x0000000504047292 */
/* 0x000fcc000f8e3c3f */
/*0060*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0090*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00c0*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*00d0*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00e0*/ IABS R4, c[0x0][0x178] ; /* 0x00005e0000047a13 */
/* 0x000fc60000000000 */
/*00f0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0100*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*0120*/ IMAD R0, R5.reuse, R0, R4 ; /* 0x0000000005007224 */
/* 0x040fe400078e0204 */
/*0130*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0140*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0150*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0160*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe40003f45270 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0190*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e360000002100 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0003 */
/*01c0*/ @!P1 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0a09 */
/*01d0*/ @!P2 LOP3.LUT R9, RZ, c[0x0][0x164], RZ, 0x33, !PT ; /* 0x00005900ff09aa12 */
/* 0x000fe200078e33ff */
/*01e0*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fc600078e0205 */
/*01f0*/ IABS R8, R9.reuse ; /* 0x0000000900087213 */
/* 0x080fe40000000000 */
/*0200*/ IABS R10, R9 ; /* 0x00000009000a7213 */
/* 0x000fe20000000000 */
/*0210*/ IMAD R0, R9, c[0x0][0x168], R4 ; /* 0x00005a0009007a24 */
/* 0x000fe200078e0204 */
/*0220*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e260000209400 */
/*0230*/ IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a0a */
/*0240*/ LOP3.LUT R5, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000057a12 */
/* 0x000fc800078e3cff */
/*0250*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0260*/ IADD3 R2, R6, 0xffffffe, RZ ; /* 0x0ffffffe06027810 */
/* 0x001fe40007ffe0ff */
/*0270*/ IABS R6, R5 ; /* 0x0000000500067213 */
/* 0x000fc80000000000 */
/*0280*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0290*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*02a0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*02b0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fc800078e0002 */
/*02d0*/ IMAD.MOV.U32 R3, RZ, RZ, R6 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0006 */
/*02e0*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*02f0*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD R3, R2, R6, R3 ; /* 0x0000000602037224 */
/* 0x000fe400078e0203 */
/*0310*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0320*/ ISETP.GT.U32.AND P2, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f44070 */
/*0330*/ @!P2 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x000000010303a824 */
/* 0x000fe200078e0a08 */
/*0340*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*0350*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f45270 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0370*/ LOP3.LUT R3, R5, R9, RZ, 0x3c, !PT ; /* 0x0000000905037212 */
/* 0x000fc800078e3cff */
/*0380*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f26270 */
/*0390*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fc60003f06270 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*03c0*/ IMAD.WIDE R2, R4, R7, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fc800078e0207 */
/*03d0*/ @!P1 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff069224 */
/* 0x000fe200078e0a06 */
/*03e0*/ @!P2 LOP3.LUT R6, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff06a212 */
/* 0x000fc600078e33ff */
/*03f0*/ @!P0 BRA 0x550 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*0400*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f05270 */
/*0410*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0420*/ IMAD R6, R9, R6, RZ ; /* 0x0000000609067224 */
/* 0x000fe200078e02ff */
/*0430*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05070 */
/*0440*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000164000c1e1900 */
/*0450*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0460*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fc80003f05300 */
/*0470*/ SEL R6, R6, c[0x0][0x180], !P0 ; /* 0x0000600006067a07 */
/* 0x000fe40004000000 */
/*0480*/ SEL R7, R7, c[0x0][0x184], !P0 ; /* 0x0000610007077a07 */
/* 0x000fca0004000000 */
/*0490*/ IMAD.WIDE R6, R4, 0x4, R6 ; /* 0x0000000404067825 */
/* 0x000fcc00078e0206 */
/*04a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000162000c1e1900 */
/*04b0*/ LOP3.LUT P0, RZ, R5, c[0x0][0x17c], RZ, 0xc0, !PT ; /* 0x00005f0005ff7a12 */
/* 0x000fda000780c0ff */
/*04c0*/ @!P0 BRA 0x510 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x021fda0003f04270 */
/*04e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x021fda0003f06270 */
/*0520*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0530*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0540*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0550*/ ISETP.NE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f05270 */
/*0560*/ @!P0 BRA 0x6a0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R6, R9, R6, RZ ; /* 0x0000000609067224 */
/* 0x000fe200078e02ff */
/*0580*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fc60003f05070 */
/*0590*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*05a0*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fc80003f05300 */
/*05b0*/ SEL R6, R6, c[0x0][0x188], !P0 ; /* 0x0000620006067a07 */
/* 0x000fe40004000000 */
/*05c0*/ SEL R7, R7, c[0x0][0x18c], !P0 ; /* 0x0000630007077a07 */
/* 0x000fca0004000000 */
/*05d0*/ IMAD.WIDE R4, R4, 0x4, R6 ; /* 0x0000000404047825 */
/* 0x000fe400078e0206 */
/*05e0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000168000c1e1900 */
/*05f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000162000c1e1900 */
/*0600*/ LOP3.LUT P0, RZ, R0, c[0x0][0x17c], RZ, 0xc0, !PT ; /* 0x00005f0000ff7a12 */
/* 0x000fda000780c0ff */
/*0610*/ @!P0 BRA 0x660 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x021fda0003f06270 */
/*0630*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0640*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0650*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x021fda0003f04270 */
/*0670*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0680*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0690*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06a0*/ IMAD.MOV R4, RZ, RZ, -R9 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a09 */
/*06b0*/ IMAD R5, R4, c[0x0][0x168], R5 ; /* 0x00005a0004057a24 */
/* 0x000fc800078e0205 */
/*06c0*/ IMAD.WIDE R4, R5, R7, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fe400078e0207 */
/*06d0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000168000c1e1900 */
/*06e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000162000c1e1900 */
/*06f0*/ LOP3.LUT P0, RZ, R0, c[0x0][0x17c], RZ, 0xc0, !PT ; /* 0x00005f0000ff7a12 */
/* 0x000fda000780c0ff */
/*0700*/ @!P0 BRA 0x760 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f06270 */
/*0720*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0730*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0740*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x021fda0003f04270 */
/*0770*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0780*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe8000c101904 */
/*0790*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11mergeKerneliiiPiiiS_S_
.globl _Z11mergeKerneliiiPiiiS_S_
.p2align 8
.type _Z11mergeKerneliiiPiiiS_S_,@function
_Z11mergeKerneliiiPiiiS_S_:
s_clause 0x3
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s8, s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s9, s3, 31
s_ashr_i32 s13, s6, 31
s_add_i32 s3, s3, s9
s_add_i32 s6, s6, s13
s_xor_b32 s3, s3, s9
s_xor_b32 s6, s6, s13
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s12, 0, s3
s_and_b32 s10, s10, 0xffff
s_xor_b32 s9, s13, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s11, v1
s_mul_i32 s12, s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s12, s11, s12
s_add_i32 s11, s11, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s6, s11
s_mul_i32 s12, s11, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s6, s6, s12
s_add_i32 s12, s11, 1
s_sub_i32 s13, s6, s3
s_cmp_ge_u32 s6, s3
s_cselect_b32 s11, s12, s11
s_cselect_b32 s6, s13, s6
s_add_i32 s12, s11, 1
s_cmp_ge_u32 s6, s3
s_cselect_b32 s3, s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s3, s9
s_sub_i32 s6, s3, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s6, 31
s_add_i32 s3, s6, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_xor_b32 s11, s3, s9
s_mul_i32 s3, s6, s8
v_cvt_f32_u32_e32 v1, s11
v_rcp_iflag_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_sub_i32 s10, 0, s11
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v5, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, s2, v5
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v6
v_mul_lo_u32 v2, s10, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v6, v3
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s9, v3
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v7, s11, v2
v_cmp_le_u32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_cmp_ne_u32_e32 vcc_lo, s8, v0
s_mov_b32 s8, exec_lo
v_cmpx_ge_i32_e64 v5, v6
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_12
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_11
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11
s_cmp_lg_u64 s[10:11], 0
s_cbranch_scc1 .LBB0_4
v_mul_lo_u32 v2, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s4, v3
v_add_co_ci_u32_e64 v4, s2, s5, v4, s2
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_co_u32 v0, s2, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, s5, v8, s2
v_add_co_u32 v7, s2, v3, v7
v_add_co_ci_u32_e64 v8, s2, v4, v8, s2
v_and_b32_e32 v4, s7, v6
global_load_b32 v3, v[0:1], off
global_load_b32 v2, v[7:8], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s10, exec_lo, s10
s_cbranch_execz .LBB0_8
s_mov_b32 s11, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v3, v2
s_cbranch_execz .LBB0_7
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s11
.LBB0_8:
s_and_not1_saveexec_b32 s2, s10
s_cbranch_execz .LBB0_11
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e64 s2, v3, v2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_11
global_store_b32 v[0:1], v2, off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s9
.LBB0_12:
s_and_not1_saveexec_b32 s2, s8
s_cbranch_execz .LBB0_33
s_and_saveexec_b32 s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_25
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt vmcnt(1) lgkmcnt(0)
v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
s_cmp_lg_u64 s[0:1], 0
s_cbranch_scc1 .LBB0_16
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB0_16:
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, v3, v6
v_add_co_ci_u32_e32 v7, vcc_lo, v4, v7, vcc_lo
v_and_b32_e32 v4, s7, v5
global_load_b32 v3, v[0:1], off
global_load_b32 v2, v[6:7], off
v_cmpx_ne_u32_e32 0, v4
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_20
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v3, v2
s_cbranch_execz .LBB0_19
global_store_b32 v[0:1], v2, off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_20:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_24
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v3, v2
s_cbranch_execz .LBB0_23
global_store_b32 v[0:1], v2, off
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s1
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s0
.LBB0_25:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_33
s_waitcnt vmcnt(1)
v_subrev_nc_u32_e32 v3, s3, v6
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v5, s7, v5
s_mov_b32 s0, exec_lo
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v6, v[2:3], off
v_cmpx_ne_u32_e32 0, v5
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_30
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v6
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v4, off
s_or_b32 exec_lo, exec_lo, s1
.LBB0_30:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_33
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v4, v6
s_clause 0x1
global_store_b32 v[0:1], v6, off
global_store_b32 v[2:3], v4, off
.LBB0_33:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mergeKerneliiiPiiiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11mergeKerneliiiPiiiS_S_, .Lfunc_end0-_Z11mergeKerneliiiPiiiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mergeKerneliiiPiiiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mergeKerneliiiPiiiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003930b_00000000-6_bitonicCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl allocateMemory
.type allocateMemory, @function
allocateMemory:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %esi, %rsi
salq $2, %rsi
movl $1, %edx
call cudaMallocManaged@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size allocateMemory, .-allocateMemory
.globl callCudaFree
.type callCudaFree, @function
callCudaFree:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size callCudaFree, .-callCudaFree
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string " Unable to determine cuda device count, error is %d, count is %d\n"
.align 8
.LC1:
.string " Unable to have rank %d set to cuda device %d, error is %d \n"
.text
.globl cudaInit
.type cudaInit, @function
cudaInit:
.LFB2072:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $1, 4(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl %ebx, %eax
cltd
idivl 4(%rsp)
movl %edx, %edi
call cudaSetDevice@PLT
movl %eax, %r8d
testl %eax, %eax
jne .L13
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl 4(%rsp), %ecx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L13:
movl %ebx, %eax
cltd
idivl 4(%rsp)
movl %edx, %ecx
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size cudaInit, .-cudaInit
.globl _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
.type _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_, @function
_Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_:
.LFB2098:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 32(%rsp)
movl %r9d, 20(%rsp)
movq 208(%rsp), %rax
movq %rax, 8(%rsp)
movq 216(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11mergeKerneliiiPiiiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_, .-_Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
.globl _Z11mergeKerneliiiPiiiS_S_
.type _Z11mergeKerneliiiPiiiS_S_, @function
_Z11mergeKerneliiiPiiiS_S_:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z11mergeKerneliiiPiiiS_S_, .-_Z11mergeKerneliiiPiiiS_S_
.globl mergeKernelLaunch
.type mergeKernelLaunch, @function
mergeKernelLaunch:
.LFB2073:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movq %r9, %r13
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
movl 104(%rsp), %r9d
movl 96(%rsp), %r8d
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z40__device_stub__Z11mergeKerneliiiPiiiS_S_iiiPiiiS_S_
addq $16, %rsp
.cfi_def_cfa_offset 80
jmp .L23
.cfi_endproc
.LFE2073:
.size mergeKernelLaunch, .-mergeKernelLaunch
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z11mergeKerneliiiPiiiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mergeKerneliiiPiiiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bitonicCuda.hip"
.globl allocateMemory # -- Begin function allocateMemory
.p2align 4, 0x90
.type allocateMemory,@function
allocateMemory: # @allocateMemory
.cfi_startproc
# %bb.0:
movslq %esi, %rsi
shlq $2, %rsi
movl $1, %edx
jmp hipMallocManaged # TAILCALL
.Lfunc_end0:
.size allocateMemory, .Lfunc_end0-allocateMemory
.cfi_endproc
# -- End function
.globl callCudaFree # -- Begin function callCudaFree
.p2align 4, 0x90
.type callCudaFree,@function
callCudaFree: # @callCudaFree
.cfi_startproc
# %bb.0:
jmp hipFree # TAILCALL
.Lfunc_end1:
.size callCudaFree, .Lfunc_end1-callCudaFree
.cfi_endproc
# -- End function
.globl cudaInit # -- Begin function cudaInit
.p2align 4, 0x90
.type cudaInit,@function
cudaInit: # @cudaInit
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movl %edi, %ebx
movl $1, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %ecx
testl %eax, %eax
jne .LBB2_3
# %bb.1:
movl %ebx, %eax
cltd
idivl %ecx
movl %edx, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_4
# %bb.2:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB2_3:
.cfi_def_cfa_offset 32
movl $.L.str, %edi
movl %eax, %esi
movl %ecx, %edx
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.LBB2_4:
movl %eax, %ecx
movl %ebx, %eax
cltd
idivl 12(%rsp)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size cudaInit, .Lfunc_end2-cudaInit
.cfi_endproc
# -- End function
.globl _Z26__device_stub__mergeKerneliiiPiiiS_S_ # -- Begin function _Z26__device_stub__mergeKerneliiiPiiiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__mergeKerneliiiPiiiS_S_,@function
_Z26__device_stub__mergeKerneliiiPiiiS_S_: # @_Z26__device_stub__mergeKerneliiiPiiiS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11mergeKerneliiiPiiiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z26__device_stub__mergeKerneliiiPiiiS_S_, .Lfunc_end3-_Z26__device_stub__mergeKerneliiiPiiiS_S_
.cfi_endproc
# -- End function
.globl mergeKernelLaunch # -- Begin function mergeKernelLaunch
.p2align 4, 0x90
.type mergeKernelLaunch,@function
mergeKernelLaunch: # @mergeKernelLaunch
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movl %edi, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %esi, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movl 216(%rsp), %edx
movl 208(%rsp), %esi
movl %r15d, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebp, 12(%rsp)
movq %rbx, 88(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11mergeKerneliiiPiiiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size mergeKernelLaunch, .Lfunc_end4-mergeKernelLaunch
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11mergeKerneliiiPiiiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " Unable to determine cuda device count, error is %d, count is %d\n"
.size .L.str, 66
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Unable to have rank %d set to cuda device %d, error is %d \n"
.size .L.str.1, 61
.type _Z11mergeKerneliiiPiiiS_S_,@object # @_Z11mergeKerneliiiPiiiS_S_
.section .rodata,"a",@progbits
.globl _Z11mergeKerneliiiPiiiS_S_
.p2align 3, 0x0
_Z11mergeKerneliiiPiiiS_S_:
.quad _Z26__device_stub__mergeKerneliiiPiiiS_S_
.size _Z11mergeKerneliiiPiiiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11mergeKerneliiiPiiiS_S_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__mergeKerneliiiPiiiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11mergeKerneliiiPiiiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
#define BLOCKSIZE 32
//test code
__global__ void nmfh(float *a, int r, int c, int k, float *w, float *h, float *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
float temp = 0.0;
float sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | .file "tmpxft_000e3474_00000000-6_nmfh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
.type _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_, @function
_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4nmfhPfiiiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_, .-_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
.globl _Z4nmfhPfiiiS_S_S_
.type _Z4nmfhPfiiiS_S_S_, @function
_Z4nmfhPfiiiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4nmfhPfiiiS_S_S_, .-_Z4nmfhPfiiiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4nmfhPfiiiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4nmfhPfiiiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
#define BLOCKSIZE 32
//test code
__global__ void nmfh(float *a, int r, int c, int k, float *w, float *h, float *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
float temp = 0.0;
float sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define BLOCKSIZE 32
//test code
__global__ void nmfh(float *a, int r, int c, int k, float *w, float *h, float *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
float temp = 0.0;
float sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define BLOCKSIZE 32
//test code
__global__ void nmfh(float *a, int r, int c, int k, float *w, float *h, float *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
float temp = 0.0;
float sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4nmfhPfiiiS_S_S_
.globl _Z4nmfhPfiiiS_S_S_
.p2align 8
.type _Z4nmfhPfiiiS_S_S_,@function
_Z4nmfhPfiiiS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0xc
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
s_clause 0x1
s_load_b32 s10, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v4, v1
s_mov_b32 s8, s10
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s8, 0
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[9:10], 2, v[4:5]
v_add_nc_u32_e32 v4, s4, v4
v_add_nc_u32_e32 v2, s5, v2
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v5, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v3, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[6:7], s[0:1], 0x20
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_cmp_lt_i32 s5, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v5, v[4:5], off
s_cbranch_scc1 .LBB0_11
v_mov_b32_e32 v4, 0
s_cmp_gt_i32 s10, 0
s_mov_b32 s9, 0
s_cselect_b32 s11, -1, 0
s_mov_b32 s12, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s5
s_cbranch_scc1 .LBB0_12
.LBB0_8:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_7
v_mad_u64_u32 v[7:8], null, s12, s4, v[1:2]
s_mov_b32 s13, 0
s_mov_b32 s14, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v7, v[7:8], off
.p2align 6
.LBB0_10:
v_add_nc_u32_e32 v8, s13, v0
s_add_i32 s8, s12, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[8:9], 2
s_add_u32 s16, s2, s16
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
s_addc_u32 s17, s3, s17
s_add_i32 s14, s14, -1
s_add_i32 s13, s13, s5
s_cmp_eq_u32 s14, 0
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_load_b32 s8, s[16:17], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f32_e32 v8, s8, v8
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v8, v7
s_cbranch_scc0 .LBB0_10
s_branch .LBB0_7
.LBB0_11:
v_mov_b32_e32 v4, 0
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, v6, v5
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_div_scale_f32 v0, null, v4, v4, v5
v_div_scale_f32 v7, vcc_lo, v5, v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v0, v1, 1.0
v_fmac_f32_e32 v1, v6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v1
v_fma_f32 v8, -v0, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v1
v_fma_f32 v0, -v0, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v6, v0, v1, v6
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_div_fixup_f32 v2, v6, v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4nmfhPfiiiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4nmfhPfiiiS_S_S_, .Lfunc_end0-_Z4nmfhPfiiiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4nmfhPfiiiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z4nmfhPfiiiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
#define BLOCKSIZE 32
//test code
__global__ void nmfh(float *a, int r, int c, int k, float *w, float *h, float *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
float temp = 0.0;
float sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | .text
.file "nmfh.hip"
.globl _Z19__device_stub__nmfhPfiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfhPfiiiS_S_S_
.p2align 4, 0x90
.type _Z19__device_stub__nmfhPfiiiS_S_S_,@function
_Z19__device_stub__nmfhPfiiiS_S_S_: # @_Z19__device_stub__nmfhPfiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4nmfhPfiiiS_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__nmfhPfiiiS_S_S_, .Lfunc_end0-_Z19__device_stub__nmfhPfiiiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4nmfhPfiiiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4nmfhPfiiiS_S_S_,@object # @_Z4nmfhPfiiiS_S_S_
.section .rodata,"a",@progbits
.globl _Z4nmfhPfiiiS_S_S_
.p2align 3, 0x0
_Z4nmfhPfiiiS_S_S_:
.quad _Z19__device_stub__nmfhPfiiiS_S_S_
.size _Z4nmfhPfiiiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4nmfhPfiiiS_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__nmfhPfiiiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4nmfhPfiiiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e3474_00000000-6_nmfh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
.type _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_, @function
_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4nmfhPfiiiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_, .-_Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
.globl _Z4nmfhPfiiiS_S_S_
.type _Z4nmfhPfiiiS_S_S_, @function
_Z4nmfhPfiiiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z4nmfhPfiiiS_S_S_PfiiiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4nmfhPfiiiS_S_S_, .-_Z4nmfhPfiiiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4nmfhPfiiiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4nmfhPfiiiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nmfh.hip"
.globl _Z19__device_stub__nmfhPfiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfhPfiiiS_S_S_
.p2align 4, 0x90
.type _Z19__device_stub__nmfhPfiiiS_S_S_,@function
_Z19__device_stub__nmfhPfiiiS_S_S_: # @_Z19__device_stub__nmfhPfiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4nmfhPfiiiS_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__nmfhPfiiiS_S_S_, .Lfunc_end0-_Z19__device_stub__nmfhPfiiiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4nmfhPfiiiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4nmfhPfiiiS_S_S_,@object # @_Z4nmfhPfiiiS_S_S_
.section .rodata,"a",@progbits
.globl _Z4nmfhPfiiiS_S_S_
.p2align 3, 0x0
_Z4nmfhPfiiiS_S_S_:
.quad _Z19__device_stub__nmfhPfiiiS_S_S_
.size _Z4nmfhPfiiiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4nmfhPfiiiS_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__nmfhPfiiiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4nmfhPfiiiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // GPU kernel
__global__ void summation_kernel(int data_size, float * data_out)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
data_out[i] += ((i % 2 == 0) ? 1 : - 1) / (i + 1.0f);
/*for(int cpt = i; cpt < i + data_size; cpt++) {
data_out[cpt] += 1.0f;
}*/
}
__global__ void reduce(float data_size, float * data_out, float * data_block) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = (i < data_size) ? data_out[i] : 0;
__syncthreads();
for(unsigned int s = blockDim.x/2; s > 0; s >>= 1) {
if(tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0) data_block[blockIdx.x] = sdata[0];
} | code for sm_80
Function : _Z6reducefPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fc800078e0207 */
/*0060*/ I2F.U32 R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201000 */
/*0070*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0b */
/* 0x001fda0003f0e000 */
/*0080*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fca0000000f00 */
/*0090*/ @!P0 IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000028625 */
/* 0x000fca00078e0003 */
/*00a0*/ @!P0 LDG.E R4, [R2.64] ; /* 0x0000000602048981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00f0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x0041e80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0110*/ @!P1 BRA 0x1e0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0120*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*0130*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0150*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*0160*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0170*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0180*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0190*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*01a0*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01d0*/ @P1 BRA 0x140 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16summation_kerneliPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x180 ; /* 0x0000014000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e220000201400 */
/*0070*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fc800078ec0ff */
/*0080*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05070 */
/*0090*/ FADD R4, R3, 1 ; /* 0x3f80000003047421 */
/* 0x001fe40000000000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, -0x1 ; /* 0xffffffffff037424 */
/* 0x000fe400078e00ff */
/*00b0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e260000001000 */
/*00c0*/ SEL R2, R3, 0x1, !P0 ; /* 0x0000000103027807 */
/* 0x000fca0004000000 */
/*00d0*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x000e620000201400 */
/*00e0*/ FFMA R6, -R4, R5, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000105 */
/*00f0*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc60000000005 */
/*0100*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e220000000000 */
/*0110*/ FFMA R5, R3, R6, RZ ; /* 0x0000000603057223 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R7, -R4, R5, R3 ; /* 0x0000000504077223 */
/* 0x000fc80000000103 */
/*0130*/ FFMA R5, R6, R7, R5 ; /* 0x0000000706057223 */
/* 0x000fe20000000005 */
/*0140*/ @!P0 BRA 0x170 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0150*/ MOV R2, 0x170 ; /* 0x0000017000027802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x1e0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*01a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*01f0*/ BSSY B1, 0x840 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0220*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0240*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0250*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0270*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0280*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0290*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*02a0*/ @!P0 BRA 0x420 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*02c0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02e0*/ @P0 BRA 0x820 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0300*/ @!P0 BRA 0x800 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0320*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0340*/ @!P1 BRA !P2, 0x800 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0350*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0360*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0370*/ @P1 BRA 0x7e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03a0*/ @P0 BRA 0x7b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03c0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03d0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*0400*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*0410*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0420*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0430*/ BSSY B2, 0x7a0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0440*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0450*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0460*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0470*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0480*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0490*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*04a0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*04b0*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*04c0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*04d0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04e0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*04f0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0500*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*0510*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0520*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0530*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0540*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0550*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 BRA 0x780 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0590*/ @P0 BRA 0x750 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05b0*/ @P0 BRA 0x790 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05d0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05e0*/ @!P0 BRA 0x790 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0600*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0610*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0620*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0630*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0640*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0650*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0670*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0690*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*06a0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06c0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06e0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06f0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0700*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0710*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0730*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x790 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0760*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x790 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0790*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x830 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07c0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x830 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07f0*/ BRA 0x830 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0800*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0810*/ BRA 0x830 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0820*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0850*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0860*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff79002007950 */
/* 0x000fea0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // GPU kernel
__global__ void summation_kernel(int data_size, float * data_out)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
data_out[i] += ((i % 2 == 0) ? 1 : - 1) / (i + 1.0f);
/*for(int cpt = i; cpt < i + data_size; cpt++) {
data_out[cpt] += 1.0f;
}*/
}
__global__ void reduce(float data_size, float * data_out, float * data_block) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = (i < data_size) ? data_out[i] : 0;
__syncthreads();
for(unsigned int s = blockDim.x/2; s > 0; s >>= 1) {
if(tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0) data_block[blockIdx.x] = sdata[0];
} | .file "tmpxft_00138760_00000000-6_summation_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16summation_kerneliPfiPf
.type _Z37__device_stub__Z16summation_kerneliPfiPf, @function
_Z37__device_stub__Z16summation_kerneliPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16summation_kerneliPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16summation_kerneliPfiPf, .-_Z37__device_stub__Z16summation_kerneliPfiPf
.globl _Z16summation_kerneliPf
.type _Z16summation_kerneliPf, @function
_Z16summation_kerneliPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16summation_kerneliPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16summation_kerneliPf, .-_Z16summation_kerneliPf
.globl _Z28__device_stub__Z6reducefPfS_fPfS_
.type _Z28__device_stub__Z6reducefPfS_fPfS_, @function
_Z28__device_stub__Z6reducefPfS_fPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducefPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z6reducefPfS_fPfS_, .-_Z28__device_stub__Z6reducefPfS_fPfS_
.globl _Z6reducefPfS_
.type _Z6reducefPfS_, @function
_Z6reducefPfS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducefPfS_fPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6reducefPfS_, .-_Z6reducefPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6reducefPfS_"
.LC1:
.string "_Z16summation_kerneliPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducefPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16summation_kerneliPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // GPU kernel
__global__ void summation_kernel(int data_size, float * data_out)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
data_out[i] += ((i % 2 == 0) ? 1 : - 1) / (i + 1.0f);
/*for(int cpt = i; cpt < i + data_size; cpt++) {
data_out[cpt] += 1.0f;
}*/
}
__global__ void reduce(float data_size, float * data_out, float * data_block) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = (i < data_size) ? data_out[i] : 0;
__syncthreads();
for(unsigned int s = blockDim.x/2; s > 0; s >>= 1) {
if(tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0) data_block[blockIdx.x] = sdata[0];
} | #include <hip/hip_runtime.h>
// GPU kernel
__global__ void summation_kernel(int data_size, float * data_out)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
data_out[i] += ((i % 2 == 0) ? 1 : - 1) / (i + 1.0f);
/*for(int cpt = i; cpt < i + data_size; cpt++) {
data_out[cpt] += 1.0f;
}*/
}
__global__ void reduce(float data_size, float * data_out, float * data_block) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = (i < data_size) ? data_out[i] : 0;
__syncthreads();
for(unsigned int s = blockDim.x/2; s > 0; s >>= 1) {
if(tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0) data_block[blockIdx.x] = sdata[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// GPU kernel
__global__ void summation_kernel(int data_size, float * data_out)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
data_out[i] += ((i % 2 == 0) ? 1 : - 1) / (i + 1.0f);
/*for(int cpt = i; cpt < i + data_size; cpt++) {
data_out[cpt] += 1.0f;
}*/
}
__global__ void reduce(float data_size, float * data_out, float * data_block) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = (i < data_size) ? data_out[i] : 0;
__syncthreads();
for(unsigned int s = blockDim.x/2; s > 0; s >>= 1) {
if(tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0) data_block[blockIdx.x] = sdata[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16summation_kerneliPf
.globl _Z16summation_kerneliPf
.p2align 8
.type _Z16summation_kerneliPf,@function
_Z16summation_kerneliPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cvt_f32_i32_e32 v1, v1
v_add_f32_e32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
global_load_b32 v0, v[2:3], off
v_cndmask_b32_e64 v4, -1, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v4
v_div_scale_f32 v5, null, v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v4, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v7, v6
v_fma_f32 v9, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v6
v_fma_f32 v5, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v8
v_div_fixup_f32 v1, v5, v1, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16summation_kerneliPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16summation_kerneliPf, .Lfunc_end0-_Z16summation_kerneliPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6reducefPfS_
.globl _Z6reducefPfS_
.p2align 8
.type _Z6reducefPfS_,@function
_Z6reducefPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cvt_f32_u32_e32 v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, s4, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_4:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_3
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB1_3
.LBB1_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducefPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6reducefPfS_, .Lfunc_end1-_Z6reducefPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16summation_kerneliPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16summation_kerneliPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducefPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducefPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// GPU kernel
__global__ void summation_kernel(int data_size, float * data_out)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
data_out[i] += ((i % 2 == 0) ? 1 : - 1) / (i + 1.0f);
/*for(int cpt = i; cpt < i + data_size; cpt++) {
data_out[cpt] += 1.0f;
}*/
}
__global__ void reduce(float data_size, float * data_out, float * data_block) {
extern __shared__ float sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
sdata[tid] = (i < data_size) ? data_out[i] : 0;
__syncthreads();
for(unsigned int s = blockDim.x/2; s > 0; s >>= 1) {
if(tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if(tid == 0) data_block[blockIdx.x] = sdata[0];
} | .text
.file "summation_kernel.hip"
.globl _Z31__device_stub__summation_kerneliPf # -- Begin function _Z31__device_stub__summation_kerneliPf
.p2align 4, 0x90
.type _Z31__device_stub__summation_kerneliPf,@function
_Z31__device_stub__summation_kerneliPf: # @_Z31__device_stub__summation_kerneliPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16summation_kerneliPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__summation_kerneliPf, .Lfunc_end0-_Z31__device_stub__summation_kerneliPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__reducefPfS_ # -- Begin function _Z21__device_stub__reducefPfS_
.p2align 4, 0x90
.type _Z21__device_stub__reducefPfS_,@function
_Z21__device_stub__reducefPfS_: # @_Z21__device_stub__reducefPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducefPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__reducefPfS_, .Lfunc_end1-_Z21__device_stub__reducefPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16summation_kerneliPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducefPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16summation_kerneliPf,@object # @_Z16summation_kerneliPf
.section .rodata,"a",@progbits
.globl _Z16summation_kerneliPf
.p2align 3, 0x0
_Z16summation_kerneliPf:
.quad _Z31__device_stub__summation_kerneliPf
.size _Z16summation_kerneliPf, 8
.type _Z6reducefPfS_,@object # @_Z6reducefPfS_
.globl _Z6reducefPfS_
.p2align 3, 0x0
_Z6reducefPfS_:
.quad _Z21__device_stub__reducefPfS_
.size _Z6reducefPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16summation_kerneliPf"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6reducefPfS_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__summation_kerneliPf
.addrsig_sym _Z21__device_stub__reducefPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16summation_kerneliPf
.addrsig_sym _Z6reducefPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6reducefPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fc800078e0207 */
/*0060*/ I2F.U32 R2, R0 ; /* 0x0000000000027306 */
/* 0x000e240000201000 */
/*0070*/ FSETP.GEU.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0b */
/* 0x001fda0003f0e000 */
/*0080*/ @!P0 MOV R3, 0x4 ; /* 0x0000000400038802 */
/* 0x000fca0000000f00 */
/*0090*/ @!P0 IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000028625 */
/* 0x000fca00078e0003 */
/*00a0*/ @!P0 LDG.E R4, [R2.64] ; /* 0x0000000602048981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00f0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x0041e80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0110*/ @!P1 BRA 0x1e0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0120*/ SHF.L.U32 R0, R7, 0x2, RZ ; /* 0x0000000207007819 */
/* 0x001fe200000006ff */
/*0130*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0150*/ @!P1 LEA R2, R3, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x000fe200078e10ff */
/*0160*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0170*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0180*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0190*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*01a0*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01d0*/ @P1 BRA 0x140 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16summation_kerneliPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x180 ; /* 0x0000014000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e220000201400 */
/*0070*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fc800078ec0ff */
/*0080*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05070 */
/*0090*/ FADD R4, R3, 1 ; /* 0x3f80000003047421 */
/* 0x001fe40000000000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, -0x1 ; /* 0xffffffffff037424 */
/* 0x000fe400078e00ff */
/*00b0*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e260000001000 */
/*00c0*/ SEL R2, R3, 0x1, !P0 ; /* 0x0000000103027807 */
/* 0x000fca0004000000 */
/*00d0*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x000e620000201400 */
/*00e0*/ FFMA R6, -R4, R5, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000105 */
/*00f0*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc60000000005 */
/*0100*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e220000000000 */
/*0110*/ FFMA R5, R3, R6, RZ ; /* 0x0000000603057223 */
/* 0x000fc800000000ff */
/*0120*/ FFMA R7, -R4, R5, R3 ; /* 0x0000000504077223 */
/* 0x000fc80000000103 */
/*0130*/ FFMA R5, R6, R7, R5 ; /* 0x0000000706057223 */
/* 0x000fe20000000005 */
/*0140*/ @!P0 BRA 0x170 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0150*/ MOV R2, 0x170 ; /* 0x0000017000027802 */
/* 0x000fe40000000f00 */
/*0160*/ CALL.REL.NOINC 0x1e0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*01a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ FADD R5, R0, R5 ; /* 0x0000000500057221 */
/* 0x004fca0000000000 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*01f0*/ BSSY B1, 0x840 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0200*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*0220*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0240*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0250*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0260*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0270*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0280*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0290*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*02a0*/ @!P0 BRA 0x420 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02b0*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*02c0*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*02d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02e0*/ @P0 BRA 0x820 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0300*/ @!P0 BRA 0x800 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*0320*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*0330*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*0340*/ @!P1 BRA !P2, 0x800 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0350*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0360*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0370*/ @P1 BRA 0x7e0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0380*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0390*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*03a0*/ @P0 BRA 0x7b0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03c0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03d0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03f0*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*0400*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*0410*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0420*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0430*/ BSSY B2, 0x7a0 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0440*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0450*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0460*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0470*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0480*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0490*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*04a0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*04b0*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*04c0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*04d0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04e0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*04f0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0500*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*0510*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0520*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0530*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0540*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0550*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0570*/ @!P0 BRA 0x780 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0590*/ @P0 BRA 0x750 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05b0*/ @P0 BRA 0x790 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05d0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05e0*/ @!P0 BRA 0x790 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05f0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0600*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0610*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0620*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0630*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0640*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0650*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0670*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0690*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*06a0*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06c0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06e0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06f0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0700*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0710*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0720*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0730*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x790 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0760*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0770*/ BRA 0x790 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0780*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0790*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x830 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07c0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x830 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07e0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07f0*/ BRA 0x830 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0800*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0810*/ BRA 0x830 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0820*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0830*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0850*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0860*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff79002007950 */
/* 0x000fea0003c3ffff */
/*0870*/ BRA 0x870; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16summation_kerneliPf
.globl _Z16summation_kerneliPf
.p2align 8
.type _Z16summation_kerneliPf,@function
_Z16summation_kerneliPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_and_b32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_cvt_f32_i32_e32 v1, v1
v_add_f32_e32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
global_load_b32 v0, v[2:3], off
v_cndmask_b32_e64 v4, -1, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v4, v4
v_div_scale_f32 v5, null, v1, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v4, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v7, v6
v_fma_f32 v9, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v6
v_fma_f32 v5, -v5, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v8
v_div_fixup_f32 v1, v5, v1, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v1
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16summation_kerneliPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16summation_kerneliPf, .Lfunc_end0-_Z16summation_kerneliPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6reducefPfS_
.globl _Z6reducefPfS_
.p2align 8
.type _Z6reducefPfS_,@function
_Z6reducefPfS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_cvt_f32_u32_e32 v2, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, s4, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_4:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_3
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB1_3
.LBB1_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducefPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6reducefPfS_, .Lfunc_end1-_Z6reducefPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16summation_kerneliPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16summation_kerneliPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducefPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducefPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00138760_00000000-6_summation_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z16summation_kerneliPfiPf
.type _Z37__device_stub__Z16summation_kerneliPfiPf, @function
_Z37__device_stub__Z16summation_kerneliPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16summation_kerneliPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z16summation_kerneliPfiPf, .-_Z37__device_stub__Z16summation_kerneliPfiPf
.globl _Z16summation_kerneliPf
.type _Z16summation_kerneliPf, @function
_Z16summation_kerneliPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16summation_kerneliPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16summation_kerneliPf, .-_Z16summation_kerneliPf
.globl _Z28__device_stub__Z6reducefPfS_fPfS_
.type _Z28__device_stub__Z6reducefPfS_fPfS_, @function
_Z28__device_stub__Z6reducefPfS_fPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6reducefPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z6reducefPfS_fPfS_, .-_Z28__device_stub__Z6reducefPfS_fPfS_
.globl _Z6reducefPfS_
.type _Z6reducefPfS_, @function
_Z6reducefPfS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6reducefPfS_fPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z6reducefPfS_, .-_Z6reducefPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6reducefPfS_"
.LC1:
.string "_Z16summation_kerneliPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducefPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z16summation_kerneliPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "summation_kernel.hip"
.globl _Z31__device_stub__summation_kerneliPf # -- Begin function _Z31__device_stub__summation_kerneliPf
.p2align 4, 0x90
.type _Z31__device_stub__summation_kerneliPf,@function
_Z31__device_stub__summation_kerneliPf: # @_Z31__device_stub__summation_kerneliPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16summation_kerneliPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__summation_kerneliPf, .Lfunc_end0-_Z31__device_stub__summation_kerneliPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__reducefPfS_ # -- Begin function _Z21__device_stub__reducefPfS_
.p2align 4, 0x90
.type _Z21__device_stub__reducefPfS_,@function
_Z21__device_stub__reducefPfS_: # @_Z21__device_stub__reducefPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6reducefPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__reducefPfS_, .Lfunc_end1-_Z21__device_stub__reducefPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16summation_kerneliPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducefPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16summation_kerneliPf,@object # @_Z16summation_kerneliPf
.section .rodata,"a",@progbits
.globl _Z16summation_kerneliPf
.p2align 3, 0x0
_Z16summation_kerneliPf:
.quad _Z31__device_stub__summation_kerneliPf
.size _Z16summation_kerneliPf, 8
.type _Z6reducefPfS_,@object # @_Z6reducefPfS_
.globl _Z6reducefPfS_
.p2align 3, 0x0
_Z6reducefPfS_:
.quad _Z21__device_stub__reducefPfS_
.size _Z6reducefPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16summation_kerneliPf"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6reducefPfS_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__summation_kerneliPf
.addrsig_sym _Z21__device_stub__reducefPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16summation_kerneliPf
.addrsig_sym _Z6reducefPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
__global__ void mat_add(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M+N;
}
__global__ void mat_sub(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M-N;
}
__global__ void mat_mult(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float Cvalue = 0;
for(int i=0;i<width;i++)
{
float M = A[ty*width + i];
float N = B[i*width + tx];
Cvalue += M*N;
}
C[ty*width + tx] = Cvalue;
}
//Single Thread
void s_mat_add(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M+N;
}
}
}
void s_mat_sub(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M-N;
}
}
}
void s_mat_mul(float *A,float *B,float *C,int width)
{
float Cvalue = 0.0f;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
for(int k=0;k<width;k++)
{
float M = A[i*width + k];
float N = B[j + k*width];
Cvalue += M*N;
}
C[i*width + j] = Cvalue;
Cvalue = 0.0f;
}
}
}
int main()
{
//Matrix for test
float *A,*B,*P;
int width = 5;
A = new float[width*width];
B = new float[width*width];
P = new float[width*width];
for(int i=0;i<width*width;i++)
{
A[i] = i;
B[i] = i;
}
std::cout<<"Input1:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<A[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
std::cout<<"Input2:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<B[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
float *Ad,*Bd,*Pd;
cudaMalloc((void**)&Ad,sizeof(float)*width*width);
cudaMalloc((void**)&Bd,sizeof(float)*width*width);
cudaMalloc((void**)&Pd,sizeof(float)*width*width);
cudaMemcpy(Ad, A, width*width * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(Bd, B, width*width * sizeof(int), cudaMemcpyHostToDevice);
dim3 dimBlock(width,width);
dim3 dimGrid(1,1);
//Add
mat_add<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
mat_sub<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
mat_mult<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Multiple:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Add
std::cout<<"Single Thread:"<<std::endl;
s_mat_add(A,B,P,width);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
s_mat_sub(A,B,P,width);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
s_mat_mul(A,B,P,width);
std::cout<<"Mul:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Pd);
return 0;
} | code for sm_80
Function : _Z8mat_multPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbb0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa90 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fcc00078e0219 */
/*0160*/ @!P0 BRA 0x900 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x640 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0210*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0230*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0240*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0250*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0280*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0300*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0310*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0330*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0340*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0370*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*0380*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03a0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03b0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03d0*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*03e0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03f0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0440*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*0460*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0480*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0490*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04a0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04b0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04c0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04e0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0510*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0520*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0570*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0590*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05a0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05b0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05e0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*05f0*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0600*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0610*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0620*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0630*/ @P1 BRA 0x1b0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0670*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0680*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06a0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06b0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06f0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0720*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0730*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0750*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0790*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*07a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07d0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07e0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0820*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0850*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*0860*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*0870*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*0880*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08b0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*08c0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*08e0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0900*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0910*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0920*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0930*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0940*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0950*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0960*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0990*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a30*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a40*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a50*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a60*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0a70*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0a80*/ @P0 BRA 0x900 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0aa0*/ @!P0 BRA 0xbb0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ae0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b00*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b10*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b20*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b30*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b40*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b90*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0ba0*/ @P0 BRA 0xb10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bc0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R3, c[0x0][0x178], R6 ; /* 0x00005e0003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R3, c[0x0][0x178], R6 ; /* 0x00005e0003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
__global__ void mat_add(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M+N;
}
__global__ void mat_sub(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M-N;
}
__global__ void mat_mult(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float Cvalue = 0;
for(int i=0;i<width;i++)
{
float M = A[ty*width + i];
float N = B[i*width + tx];
Cvalue += M*N;
}
C[ty*width + tx] = Cvalue;
}
//Single Thread
void s_mat_add(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M+N;
}
}
}
void s_mat_sub(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M-N;
}
}
}
void s_mat_mul(float *A,float *B,float *C,int width)
{
float Cvalue = 0.0f;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
for(int k=0;k<width;k++)
{
float M = A[i*width + k];
float N = B[j + k*width];
Cvalue += M*N;
}
C[i*width + j] = Cvalue;
Cvalue = 0.0f;
}
}
}
int main()
{
//Matrix for test
float *A,*B,*P;
int width = 5;
A = new float[width*width];
B = new float[width*width];
P = new float[width*width];
for(int i=0;i<width*width;i++)
{
A[i] = i;
B[i] = i;
}
std::cout<<"Input1:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<A[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
std::cout<<"Input2:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<B[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
float *Ad,*Bd,*Pd;
cudaMalloc((void**)&Ad,sizeof(float)*width*width);
cudaMalloc((void**)&Bd,sizeof(float)*width*width);
cudaMalloc((void**)&Pd,sizeof(float)*width*width);
cudaMemcpy(Ad, A, width*width * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(Bd, B, width*width * sizeof(int), cudaMemcpyHostToDevice);
dim3 dimBlock(width,width);
dim3 dimGrid(1,1);
//Add
mat_add<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
mat_sub<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
mat_mult<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Multiple:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Add
std::cout<<"Single Thread:"<<std::endl;
s_mat_add(A,B,P,width);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
s_mat_sub(A,B,P,width);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
s_mat_mul(A,B,P,width);
std::cout<<"Mul:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Pd);
return 0;
} | .file "tmpxft_001400fd_00000000-6_matrix_math.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9s_mat_addPfS_S_i
.type _Z9s_mat_addPfS_S_i, @function
_Z9s_mat_addPfS_S_i:
.LFB3669:
.cfi_startproc
endbr64
movq %rsi, %r8
testl %ecx, %ecx
jle .L3
movslq %ecx, %r10
leaq 0(,%r10,4), %r11
negq %r10
salq $2, %r10
movq %r11, %rsi
movl $0, %r9d
.L5:
leaq (%rsi,%r10), %rax
.L6:
movss (%rdi,%rax), %xmm0
addss (%r8,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L6
addl $1, %r9d
addq %r11, %rsi
cmpl %r9d, %ecx
jne .L5
.L3:
ret
.cfi_endproc
.LFE3669:
.size _Z9s_mat_addPfS_S_i, .-_Z9s_mat_addPfS_S_i
.globl _Z9s_mat_subPfS_S_i
.type _Z9s_mat_subPfS_S_i, @function
_Z9s_mat_subPfS_S_i:
.LFB3670:
.cfi_startproc
endbr64
movq %rsi, %r8
testl %ecx, %ecx
jle .L8
movslq %ecx, %r10
leaq 0(,%r10,4), %r11
negq %r10
salq $2, %r10
movq %r11, %rsi
movl $0, %r9d
.L10:
leaq (%rsi,%r10), %rax
.L11:
movss (%rdi,%rax), %xmm0
subss (%r8,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L11
addl $1, %r9d
addq %r11, %rsi
cmpl %r9d, %ecx
jne .L10
.L8:
ret
.cfi_endproc
.LFE3670:
.size _Z9s_mat_subPfS_S_i, .-_Z9s_mat_subPfS_S_i
.globl _Z9s_mat_mulPfS_S_i
.type _Z9s_mat_mulPfS_S_i, @function
_Z9s_mat_mulPfS_S_i:
.LFB3671:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L21
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r9
movl %ecx, %r12d
movslq %ecx, %r11
leaq 0(,%r11,4), %rcx
movq %rdi, %r10
leaq (%rdi,%rcx), %rsi
movl $0, %ebp
.L15:
movq %rbx, %r8
movl $0, %edi
.L18:
movq %r8, %rdx
movq %r10, %rax
pxor %xmm1, %xmm1
.L16:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rcx, %rdx
cmpq %rsi, %rax
jne .L16
movss %xmm1, (%r9,%rdi,4)
addq $1, %rdi
addq $4, %r8
cmpq %r11, %rdi
jne .L18
addl $1, %ebp
addq %rcx, %r9
addq %rcx, %r10
addq %rcx, %rsi
cmpl %ebp, %r12d
jne .L15
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE3671:
.size _Z9s_mat_mulPfS_S_i, .-_Z9s_mat_mulPfS_S_i
.globl _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
.globl _Z7mat_addPfS_S_i
.type _Z7mat_addPfS_S_i, @function
_Z7mat_addPfS_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7mat_addPfS_S_i, .-_Z7mat_addPfS_S_i
.globl _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
.type _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i, @function
_Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7mat_subPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i, .-_Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
.globl _Z7mat_subPfS_S_i
.type _Z7mat_subPfS_S_i, @function
_Z7mat_subPfS_S_i:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z7mat_subPfS_S_i, .-_Z7mat_subPfS_S_i
.globl _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
.type _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i, @function
_Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mat_multPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i, .-_Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
.globl _Z8mat_multPfS_S_i
.type _Z8mat_multPfS_S_i, @function
_Z8mat_multPfS_S_i:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z8mat_multPfS_S_i, .-_Z8mat_multPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Input1:"
.LC2:
.string " "
.LC3:
.string "Input2:"
.LC4:
.string "Add:"
.LC5:
.string "Sub:"
.LC6:
.string "Multiple:"
.LC7:
.string "Single Thread:"
.LC8:
.string "Mul:"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $100, %edi
call _Znam@PLT
movq %rax, %r12
movl $100, %edi
call _Znam@PLT
movq %rax, %r13
movl $100, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $0, %eax
.L49:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L49
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r12, %r14
leaq 100(%r12), %rax
movq %rax, (%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC2(%rip), %r15
jmp .L50
.L121:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L120
call _ZSt16__throw_bad_castv@PLT
.L120:
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L55:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %r14
movq (%rsp), %rax
cmpq %rax, %r14
je .L56
.L50:
movl $0, %ebx
.L51:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L51
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L121
cmpb $0, 56(%rbx)
je .L54
movzbl 67(%rbx), %esi
jmp .L55
.L56:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %r14
leaq 100(%r13), %rax
movq %rax, (%rsp)
movq %rbx, %rbp
leaq .LC2(%rip), %r15
jmp .L57
.L123:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L122
call _ZSt16__throw_bad_castv@PLT
.L122:
call __stack_chk_fail@PLT
.L124:
movzbl 67(%rbx), %esi
.L62:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %r14
movq (%rsp), %rax
cmpq %rax, %r14
je .L63
.L57:
movl $0, %ebx
.L58:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L58
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L123
cmpb $0, 56(%rbx)
jne .L124
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L62
.L63:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 24(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $100, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 48(%rsp)
movl $5, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L125
.L64:
movl $2, %ecx
movl $100, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r15, %rbp
leaq 100(%r15), %rax
movq %rax, (%rsp)
leaq _ZSt4cout(%rip), %r14
jmp .L65
.L125:
movl $5, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z7mat_addPfS_S_iPfS_S_i
jmp .L64
.L127:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L126
call _ZSt16__throw_bad_castv@PLT
.L126:
call __stack_chk_fail@PLT
.L69:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L70:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %r15
movq (%rsp), %rax
cmpq %rax, %r15
je .L71
.L65:
movl $0, %ebx
.L66:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L66
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .L127
cmpb $0, 56(%rbx)
je .L69
movzbl 67(%rbx), %esi
jmp .L70
.L71:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L128
.L72:
movl $2, %ecx
movl $100, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq _ZSt4cout(%rip), %r14
jmp .L73
.L128:
movl $5, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z7mat_subPfS_S_iPfS_S_i
jmp .L72
.L130:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L129
call _ZSt16__throw_bad_castv@PLT
.L129:
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L78:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %r15
cmpq %r15, (%rsp)
je .L79
.L73:
movl $0, %ebx
.L74:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L74
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .L130
cmpb $0, 56(%rbx)
je .L77
movzbl 67(%rbx), %esi
jmp .L78
.L79:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L131
.L80:
movl $2, %ecx
movl $100, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq _ZSt4cout(%rip), %r14
jmp .L81
.L131:
movl $5, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z8mat_multPfS_S_iPfS_S_i
jmp .L80
.L133:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L132
call _ZSt16__throw_bad_castv@PLT
.L132:
call __stack_chk_fail@PLT
.L85:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L86:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %r15
cmpq %r15, (%rsp)
je .L87
.L81:
movl $0, %ebx
.L82:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L82
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .L133
cmpb $0, 56(%rbx)
je .L85
movzbl 67(%rbx), %esi
jmp .L86
.L87:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $5, %ecx
movq 8(%rsp), %r15
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z9s_mat_addPfS_S_i
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %r14
jmp .L88
.L135:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L134
call _ZSt16__throw_bad_castv@PLT
.L134:
call __stack_chk_fail@PLT
.L92:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L93:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %r15
movq (%rsp), %rax
cmpq %rax, %r15
je .L94
.L88:
movl $0, %ebx
.L89:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L89
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .L135
cmpb $0, 56(%rbx)
je .L92
movzbl 67(%rbx), %esi
jmp .L93
.L94:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $5, %ecx
movq 8(%rsp), %r15
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z9s_mat_subPfS_S_i
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %r14
jmp .L95
.L137:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L136
call _ZSt16__throw_bad_castv@PLT
.L136:
call __stack_chk_fail@PLT
.L99:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L100:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %r15
cmpq %r15, (%rsp)
je .L101
.L95:
movl $0, %ebx
.L96:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L96
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .L137
cmpb $0, 56(%rbx)
je .L99
movzbl 67(%rbx), %esi
jmp .L100
.L101:
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $5, %ecx
movq 8(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z9s_mat_mulPfS_S_i
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %r12
leaq .LC2(%rip), %r13
jmp .L102
.L139:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L138
call _ZSt16__throw_bad_castv@PLT
.L138:
call __stack_chk_fail@PLT
.L106:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L107:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $20, %rbp
cmpq %rbp, (%rsp)
je .L108
.L102:
movl $0, %ebx
.L103:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L103
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L139
cmpb $0, 56(%rbx)
je .L106
movzbl 67(%rbx), %esi
jmp .L107
.L108:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L140
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L140:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z8mat_multPfS_S_i"
.LC10:
.string "_Z7mat_subPfS_S_i"
.LC11:
.string "_Z7mat_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mat_multPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_subPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7mat_addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
__global__ void mat_add(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M+N;
}
__global__ void mat_sub(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M-N;
}
__global__ void mat_mult(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float Cvalue = 0;
for(int i=0;i<width;i++)
{
float M = A[ty*width + i];
float N = B[i*width + tx];
Cvalue += M*N;
}
C[ty*width + tx] = Cvalue;
}
//Single Thread
void s_mat_add(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M+N;
}
}
}
void s_mat_sub(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M-N;
}
}
}
void s_mat_mul(float *A,float *B,float *C,int width)
{
float Cvalue = 0.0f;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
for(int k=0;k<width;k++)
{
float M = A[i*width + k];
float N = B[j + k*width];
Cvalue += M*N;
}
C[i*width + j] = Cvalue;
Cvalue = 0.0f;
}
}
}
int main()
{
//Matrix for test
float *A,*B,*P;
int width = 5;
A = new float[width*width];
B = new float[width*width];
P = new float[width*width];
for(int i=0;i<width*width;i++)
{
A[i] = i;
B[i] = i;
}
std::cout<<"Input1:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<A[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
std::cout<<"Input2:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<B[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
float *Ad,*Bd,*Pd;
cudaMalloc((void**)&Ad,sizeof(float)*width*width);
cudaMalloc((void**)&Bd,sizeof(float)*width*width);
cudaMalloc((void**)&Pd,sizeof(float)*width*width);
cudaMemcpy(Ad, A, width*width * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(Bd, B, width*width * sizeof(int), cudaMemcpyHostToDevice);
dim3 dimBlock(width,width);
dim3 dimGrid(1,1);
//Add
mat_add<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
mat_sub<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
mat_mult<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
cudaMemcpy(P, Pd, width*width * sizeof(int), cudaMemcpyDeviceToHost);
std::cout<<"Multiple:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Add
std::cout<<"Single Thread:"<<std::endl;
s_mat_add(A,B,P,width);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
s_mat_sub(A,B,P,width);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
s_mat_mul(A,B,P,width);
std::cout<<"Mul:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
cudaFree(Ad);
cudaFree(Bd);
cudaFree(Pd);
return 0;
} | #include "hip/hip_runtime.h"
#include <iostream>
#include <stdio.h>
__global__ void mat_add(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M+N;
}
__global__ void mat_sub(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M-N;
}
__global__ void mat_mult(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float Cvalue = 0;
for(int i=0;i<width;i++)
{
float M = A[ty*width + i];
float N = B[i*width + tx];
Cvalue += M*N;
}
C[ty*width + tx] = Cvalue;
}
//Single Thread
void s_mat_add(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M+N;
}
}
}
void s_mat_sub(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M-N;
}
}
}
void s_mat_mul(float *A,float *B,float *C,int width)
{
float Cvalue = 0.0f;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
for(int k=0;k<width;k++)
{
float M = A[i*width + k];
float N = B[j + k*width];
Cvalue += M*N;
}
C[i*width + j] = Cvalue;
Cvalue = 0.0f;
}
}
}
int main()
{
//Matrix for test
float *A,*B,*P;
int width = 5;
A = new float[width*width];
B = new float[width*width];
P = new float[width*width];
for(int i=0;i<width*width;i++)
{
A[i] = i;
B[i] = i;
}
std::cout<<"Input1:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<A[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
std::cout<<"Input2:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<B[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
float *Ad,*Bd,*Pd;
hipMalloc((void**)&Ad,sizeof(float)*width*width);
hipMalloc((void**)&Bd,sizeof(float)*width*width);
hipMalloc((void**)&Pd,sizeof(float)*width*width);
hipMemcpy(Ad, A, width*width * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(Bd, B, width*width * sizeof(int), hipMemcpyHostToDevice);
dim3 dimBlock(width,width);
dim3 dimGrid(1,1);
//Add
mat_add<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
hipMemcpy(P, Pd, width*width * sizeof(int), hipMemcpyDeviceToHost);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
mat_sub<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
hipMemcpy(P, Pd, width*width * sizeof(int), hipMemcpyDeviceToHost);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
mat_mult<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
hipMemcpy(P, Pd, width*width * sizeof(int), hipMemcpyDeviceToHost);
std::cout<<"Multiple:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Add
std::cout<<"Single Thread:"<<std::endl;
s_mat_add(A,B,P,width);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
s_mat_sub(A,B,P,width);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
s_mat_mul(A,B,P,width);
std::cout<<"Mul:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
hipFree(Ad);
hipFree(Bd);
hipFree(Pd);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <stdio.h>
__global__ void mat_add(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M+N;
}
__global__ void mat_sub(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float M = A[ty*width + tx];
float N = B[ty*width + tx];
C[ty*width + tx] = M-N;
}
__global__ void mat_mult(float *A,float *B,float *C,int width)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float Cvalue = 0;
for(int i=0;i<width;i++)
{
float M = A[ty*width + i];
float N = B[i*width + tx];
Cvalue += M*N;
}
C[ty*width + tx] = Cvalue;
}
//Single Thread
void s_mat_add(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M+N;
}
}
}
void s_mat_sub(float *A,float *B,float *C,int width)
{
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
float M = A[i*width + j];
float N = B[i*width + j];
C[i*width + j] = M-N;
}
}
}
void s_mat_mul(float *A,float *B,float *C,int width)
{
float Cvalue = 0.0f;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
for(int k=0;k<width;k++)
{
float M = A[i*width + k];
float N = B[j + k*width];
Cvalue += M*N;
}
C[i*width + j] = Cvalue;
Cvalue = 0.0f;
}
}
}
int main()
{
//Matrix for test
float *A,*B,*P;
int width = 5;
A = new float[width*width];
B = new float[width*width];
P = new float[width*width];
for(int i=0;i<width*width;i++)
{
A[i] = i;
B[i] = i;
}
std::cout<<"Input1:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<A[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
std::cout<<"Input2:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<B[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
float *Ad,*Bd,*Pd;
hipMalloc((void**)&Ad,sizeof(float)*width*width);
hipMalloc((void**)&Bd,sizeof(float)*width*width);
hipMalloc((void**)&Pd,sizeof(float)*width*width);
hipMemcpy(Ad, A, width*width * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(Bd, B, width*width * sizeof(int), hipMemcpyHostToDevice);
dim3 dimBlock(width,width);
dim3 dimGrid(1,1);
//Add
mat_add<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
hipMemcpy(P, Pd, width*width * sizeof(int), hipMemcpyDeviceToHost);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
mat_sub<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
hipMemcpy(P, Pd, width*width * sizeof(int), hipMemcpyDeviceToHost);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
mat_mult<<<dimGrid,dimBlock>>> (Ad,Bd,Pd,width);
hipMemcpy(P, Pd, width*width * sizeof(int), hipMemcpyDeviceToHost);
std::cout<<"Multiple:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Add
std::cout<<"Single Thread:"<<std::endl;
s_mat_add(A,B,P,width);
std::cout<<"Add:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Sub
s_mat_sub(A,B,P,width);
std::cout<<"Sub:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
//Mul
s_mat_mul(A,B,P,width);
std::cout<<"Mul:"<<std::endl;
for(int i=0;i<width;i++)
{
for(int j=0;j<width;j++)
{
std::cout<<P[i*width + j]<<" ";
}
std::cout<<std::endl;
}
std::cout<<std::endl;
hipFree(Ad);
hipFree(Bd);
hipFree(Pd);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_i
.globl _Z7mat_addPfS_S_i
.p2align 8
.type _Z7mat_addPfS_S_i,@function
_Z7mat_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_i, .Lfunc_end0-_Z7mat_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_i
.globl _Z7mat_subPfS_S_i
.p2align 8
.type _Z7mat_subPfS_S_i,@function
_Z7mat_subPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_i, .Lfunc_end1-_Z7mat_subPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8mat_multPfS_S_i
.globl _Z8mat_multPfS_S_i
.p2align 8
.type _Z8mat_multPfS_S_i,@function
_Z8mat_multPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_4
.LBB2_3:
v_mov_b32_e32 v6, 0
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8mat_multPfS_S_i, .Lfunc_end2-_Z8mat_multPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8mat_multPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mat_multPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002200 */
/*0020*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbb0 ; /* 0x00000b2000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xa90 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x002fcc00078e0219 */
/*0160*/ @!P0 BRA 0x900 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x640 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0210*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0220*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0230*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0240*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0250*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*0260*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*0270*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*0280*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0290*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*02c0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0300*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0310*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0320*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0330*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*0340*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0360*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*0370*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*0380*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*03a0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03b0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*03c0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*03d0*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*03e0*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*03f0*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0430*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*0440*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0450*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*0460*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*0470*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*0480*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0490*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*04a0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*04b0*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*04c0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*04d0*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*04e0*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0510*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0520*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0530*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*0540*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0570*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*0580*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0590*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*05a0*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*05b0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05c0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*05d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05e0*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*05f0*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0600*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0610*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0620*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*0630*/ @P1 BRA 0x1b0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*0670*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0680*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*06a0*/ IMAD.WIDE R12, R2, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0210 */
/*06b0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*06c0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*06d0*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*06e0*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*06f0*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0720*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0730*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*0740*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0750*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0760*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*0770*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0790*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*07a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07b0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07c0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*07d0*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*07e0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0820*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0830*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0850*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*0860*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*0870*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*0880*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0890*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*08b0*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*08c0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*08e0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08f0*/ @!P0 BRA 0xa90 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0900*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0910*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0920*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0930*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*0940*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0950*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*0960*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0980*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0990*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*09f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a00*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a10*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a30*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0a40*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0a50*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0a60*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0a70*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0a80*/ @P0 BRA 0x900 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0aa0*/ @!P0 BRA 0xbb0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0ad0*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x002fd000078e0200 */
/*0ae0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fe200078e0208 */
/*0b00*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0b10*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0b20*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0000aa000c1e1900 */
/*0b30*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0002a2000c1e1900 */
/*0b40*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0b50*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x002fc60000ffe4ff */
/*0b90*/ FFMA R28, R3, R6, R28 ; /* 0x00000006031c7223 */
/* 0x004fd0000000001c */
/*0ba0*/ @P0 BRA 0xb10 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IADD3 R2, R4, R0, RZ ; /* 0x0000000004027210 */
/* 0x002fe40007ffe0ff */
/*0bc0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bd0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0be0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0bf0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_subPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R3, c[0x0][0x178], R6 ; /* 0x00005e0003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, -R5 ; /* 0x8000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7mat_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IMAD R6, R3, c[0x0][0x178], R6 ; /* 0x00005e0003067a24 */
/* 0x001fca00078e0206 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_i
.globl _Z7mat_addPfS_S_i
.p2align 8
.type _Z7mat_addPfS_S_i,@function
_Z7mat_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7mat_addPfS_S_i, .Lfunc_end0-_Z7mat_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mat_subPfS_S_i
.globl _Z7mat_subPfS_S_i
.p2align 8
.type _Z7mat_subPfS_S_i,@function
_Z7mat_subPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mat_subPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7mat_subPfS_S_i, .Lfunc_end1-_Z7mat_subPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8mat_multPfS_S_i
.globl _Z8mat_multPfS_S_i
.p2align 8
.type _Z8mat_multPfS_S_i,@function
_Z8mat_multPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v6, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB2_2:
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v9, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v9, v7
s_cbranch_scc0 .LBB2_2
s_branch .LBB2_4
.LBB2_3:
v_mov_b32_e32 v6, 0
.LBB2_4:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z8mat_multPfS_S_i, .Lfunc_end2-_Z8mat_multPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mat_subPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z7mat_subPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8mat_multPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <algorithm>
#include <chrono>
#include <fstream>
#include <iostream>
#include <string>
#include <vector>
// TODO
// check if file parameter is present
// create array to reference heater locations instead of recalculating values
// make use of cuda shared memory
// restructure project
// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#independent-thread-scheduling
struct block{
uint32_t x;
uint32_t y;
uint32_t z;
uint32_t width;
uint32_t height;
uint32_t depth;
uint32_t size;
float temp;
};
struct config_values {
bool is_3d;
bool padding[3];
float k;
uint32_t num_timesteps;
uint32_t grid_width;
uint32_t grid_height;
uint32_t grid_depth;
float starting_temp;
std::vector<block> blocks;
};
block line_to_block(bool is_3d, std::string & line) {
block out_block;
std::string token;
out_block.x = atoi(line.substr(0, line.find(',')).c_str());
token = line.substr(line.find(',') + 1);
out_block.y = atoi(token.substr(0, token.find(',')).c_str());
if (is_3d) {
token = token.substr(token.find(',') + 1);
out_block.z = atoi(token.substr(0, token.find(',')).c_str());
} else {
out_block.z = 0;
}
token = token.substr(token.find(',') + 1);
out_block.width = atoi(token.substr(0, token.find(',')).c_str());
token = token.substr(token.find(',') + 1);
out_block.height = atoi(token.substr(0, token.find(',')).c_str());
if (is_3d) {
token = token.substr(token.find(',') + 1);
out_block.depth = atoi(token.substr(0, token.find(',')).c_str());
} else {
out_block.depth = 1;
}
token = token.substr(token.find(',') + 1);
out_block.temp = atof(token.substr(0, token.find(',')).c_str());
out_block.size = out_block.width * out_block.height * out_block.depth;
return out_block;
}
void set_config_values(config_values & conf, std::string & file_name) {
std::string buf;
std::string token;
uint8_t count = 0;
std::ifstream conf_file(file_name);
if (!conf_file) {
std::cerr << "Error opening config file.\n";
} else {
while (!conf_file.eof()) {
std::getline(conf_file, buf);
buf.erase(std::remove_if( buf.begin(), buf.end(), ::isspace ), buf.end());
// Filter out line that dont start with a number
if(buf[0 ]== '.' || (buf[0] != '#' && (buf[0] >= '0' && buf[0] <= '9'))) {
switch (count) {
case 0:
conf.is_3d = (buf[0] == '3');
break;
case 1:
conf.k = atof(buf.c_str());
break;
case 2:
conf.num_timesteps = atoi(buf.c_str());
break;
case 3:
// GRID SIZE
conf.grid_width = atoi(buf.substr(0, buf.find(',')).c_str());
token = buf.substr(buf.find(',') + 1);
conf.grid_height = atoi(token.substr(0, token.find(',')).c_str());
if (conf.is_3d) {
conf.grid_depth = atoi(token.substr(token.find(',') + 1).c_str());
} else {
conf.grid_depth = 1;
}
break;
case 4:
conf.starting_temp = atof(buf.c_str());
break;
default:
// PARSE THE REMAIN FILE FOR FIXED BLOCKS
conf.blocks.push_back(line_to_block(conf.is_3d, buf));
break;
}
++count;
}
}
}
conf_file.close();
}
__global__ void init_grid_values(float * a, int size, float value) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
if (idx < size) {
a[idx] = value;
}
}
__global__ void copy_array_elements(float * lhs, float * rhs, int size) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
if (idx < size) {
lhs[idx] = rhs[idx];
}
}
__global__ void place_fixed_temp_block(float * array, int array_width, int array_height, int x, int y, int z, int w, int h, float value, int size) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
// 4d start = x
// + (y * array_width)
// + (z * array_width * array_height)
// + (a * array_width * array_height * array_depth)
// 4d offset = (idx % w)
// + array_width * (idx % (w * h)) / w)
// + (array_width * array_height) * ((idx % (w * h * d)) / (w * h))
// + (array_width * array_height * array_depth) * (idx / (w * h * d))
if (idx < size) {
int start = x + (y * array_width) + (z * array_width * array_height);
int index = start + (idx % w) + array_width * ((idx % (w * h)) / w) + (array_width * array_height) * (idx / (w * h));
array[index] = value;
}
}
__global__ void mono_3d (float * old_grid, float * new_grid, int size, int width, float k, int area) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
/* USE PTX assembly if nvcc doesn't automatically detect optimal instruction
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-mad
mad{.hi,.lo,.wide}.type d, a, b, c;
mad.hi.sat.s32 d, a, b, c;
.type = { .u16, .u32, .u64,
.s16, .s32, .s64 };
use: @p mad.wide.s32 idx, blockIDx.x, blockDim.x, threadIdx.x;
uint idx;
asm("mad.lo.u32 %0, %1, %2, %3"; : "=r"(idx) : "r"(blockIDx.x), "r"(blockDim.x), "r"(threadIdx.x));
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
*/
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
float oldValue = old_grid[idx];
float * newValueLoc = &new_grid[idx];
//left
if (idx < size) {
if (idx % width != 0) {
// if not out of range and not a left edge;
*newValueLoc += k * (old_grid[idx - 1] - oldValue);
}
//right
if (idx % width != width - 1) {
// if not out of range and not a right edge;
*newValueLoc += k * (old_grid[idx + 1] - oldValue);
}
if (idx % area >= width) {
// if not out of range and not a top edge;
*newValueLoc += k * (old_grid[idx - width] - oldValue);
}
if (idx % area < area - width) {
// if not out of range and not a bottom edge;
*newValueLoc += k * (old_grid[idx + width] - oldValue);
}
if (idx >= area) {
// if not out of range and not a front edge;
*newValueLoc += k * (old_grid[idx - area] - oldValue);
}
if (idx < size - area) {
// if not out of range and not a back edge;
*newValueLoc += k * (old_grid[idx + area] - oldValue);
}
}
}
__global__ void mono_2d (float * old_grid, float * new_grid, int size, int width, float k, int area) {
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
float oldValue = old_grid[idx];
float * newValueLoc = &new_grid[idx];
//left
if (idx < size) {
if (idx % width != 0) {
// if not out of range and not a left edge;
*newValueLoc += k * (old_grid[idx - 1] - oldValue);
}
//right
if (idx % width != width - 1) {
// if not out of range and not a right edge;
*newValueLoc += k * (old_grid[idx + 1] - oldValue);
}
if (idx % area >= width) {
// if not out of range and not a top edge;
*newValueLoc += k * (old_grid[idx - width] - oldValue);
}
if (idx % area < area - width) {
// if not out of range and not a bottom edge;
*newValueLoc += k * (old_grid[idx + width] - oldValue);
}
}
}
void copy_fixed_blocks (config_values & conf, int TPB, float *new_grid) {
// Copy fixed values into new_grid
for (int block_idx = 0; block_idx < conf.blocks.size(); ++block_idx) {
int blocks = (conf.blocks[block_idx].size + TPB - 1) / TPB;
place_fixed_temp_block<<<blocks, TPB>>>(new_grid, conf.grid_width, conf.grid_height,
conf.blocks[block_idx].x, conf.blocks[block_idx].y, conf.blocks[block_idx].z,
conf.blocks[block_idx].width, conf.blocks[block_idx].height, conf.blocks[block_idx].temp, conf.blocks[block_idx].size);
cudaThreadSynchronize();
}
}
void output_final_values (config_values & conf, float * host_grid) {
std::ofstream out_file("heatOutput.csv");
int index = 0;
for (int layer = 0; layer < conf.grid_depth - 1; ++layer) {
for (int row = 0; row < conf.grid_height; ++row) {
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
out_file << '\n';
}
for (int row = 0; row < conf.grid_height - 1; ++row) {
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
int main(int argc, char * argv[]) {
auto start = std::chrono::high_resolution_clock::now();
config_values conf;
std::string file_name(argv[1]);
set_config_values(conf, file_name);
int TPB = 512; // could change to a define (need to edit copy_fixed_blocks())
int area = conf.grid_width * conf.grid_height;
int size = area * conf.grid_depth;
int num_blocks = (size + TPB - 1) / TPB;
float * new_grid;
float * old_grid;
float * host_grid = new float[size];
auto stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> duration = (stop - start);
std::cout << duration.count() * 1000 * 1000 << "us" << '\n';
start = std::chrono::high_resolution_clock::now();
cudaMalloc((void**) & new_grid, size * sizeof(float));
cudaMalloc((void**) & old_grid, size * sizeof(float));
init_grid_values<<<num_blocks, TPB>>>(new_grid, size, conf.starting_temp);
cudaThreadSynchronize();
copy_fixed_blocks(conf , TPB, new_grid);
cudaThreadSynchronize();
if (conf.is_3d) {
for (int i = 0; i < conf.num_timesteps; ++i) {
copy_array_elements<<<num_blocks, TPB>>>(old_grid, new_grid, size); // old = new
cudaThreadSynchronize();
mono_3d<<<num_blocks, TPB>>>(old_grid, new_grid, size, conf.grid_width, conf.k, area);
cudaThreadSynchronize();
copy_fixed_blocks(conf, TPB, new_grid);
cudaThreadSynchronize();
}
} else {
for (int i = 0; i < conf.num_timesteps; ++i) {
copy_array_elements<<<num_blocks, TPB>>>(old_grid, new_grid, size); // old = new
cudaThreadSynchronize();
mono_2d<<<num_blocks, TPB>>>(old_grid, new_grid, size, conf.grid_width, conf.k, area);
cudaThreadSynchronize();
copy_fixed_blocks(conf, TPB, new_grid);
cudaThreadSynchronize();
}
}
cudaMemcpy(host_grid, new_grid, size * sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(old_grid);
cudaFree(new_grid);
stop = std::chrono::high_resolution_clock::now();
duration = (stop - start);
std::cout << duration.count() * 1000 * 1000 << "us" << '\n';
// Output host_grid values to files and std::cout
output_final_values(conf, host_grid);
delete[] host_grid;
return 0;
} | #include <hip/hip_runtime.h>
#include <algorithm>
#include <chrono>
#include <fstream>
#include <iostream>
#include <string>
#include <vector>
// TODO
// check if file parameter is present
// create array to reference heater locations instead of recalculating values
// make use of cuda shared memory
// restructure project
// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#independent-thread-scheduling
struct block{
uint32_t x;
uint32_t y;
uint32_t z;
uint32_t width;
uint32_t height;
uint32_t depth;
uint32_t size;
float temp;
};
struct config_values {
bool is_3d;
bool padding[3];
float k;
uint32_t num_timesteps;
uint32_t grid_width;
uint32_t grid_height;
uint32_t grid_depth;
float starting_temp;
std::vector<block> blocks;
};
block line_to_block(bool is_3d, std::string & line) {
block out_block;
std::string token;
out_block.x = atoi(line.substr(0, line.find(',')).c_str());
token = line.substr(line.find(',') + 1);
out_block.y = atoi(token.substr(0, token.find(',')).c_str());
if (is_3d) {
token = token.substr(token.find(',') + 1);
out_block.z = atoi(token.substr(0, token.find(',')).c_str());
} else {
out_block.z = 0;
}
token = token.substr(token.find(',') + 1);
out_block.width = atoi(token.substr(0, token.find(',')).c_str());
token = token.substr(token.find(',') + 1);
out_block.height = atoi(token.substr(0, token.find(',')).c_str());
if (is_3d) {
token = token.substr(token.find(',') + 1);
out_block.depth = atoi(token.substr(0, token.find(',')).c_str());
} else {
out_block.depth = 1;
}
token = token.substr(token.find(',') + 1);
out_block.temp = atof(token.substr(0, token.find(',')).c_str());
out_block.size = out_block.width * out_block.height * out_block.depth;
return out_block;
}
void set_config_values(config_values & conf, std::string & file_name) {
std::string buf;
std::string token;
uint8_t count = 0;
std::ifstream conf_file(file_name);
if (!conf_file) {
std::cerr << "Error opening config file.\n";
} else {
while (!conf_file.eof()) {
std::getline(conf_file, buf);
buf.erase(std::remove_if( buf.begin(), buf.end(), ::isspace ), buf.end());
// Filter out line that dont start with a number
if(buf[0 ]== '.' || (buf[0] != '#' && (buf[0] >= '0' && buf[0] <= '9'))) {
switch (count) {
case 0:
conf.is_3d = (buf[0] == '3');
break;
case 1:
conf.k = atof(buf.c_str());
break;
case 2:
conf.num_timesteps = atoi(buf.c_str());
break;
case 3:
// GRID SIZE
conf.grid_width = atoi(buf.substr(0, buf.find(',')).c_str());
token = buf.substr(buf.find(',') + 1);
conf.grid_height = atoi(token.substr(0, token.find(',')).c_str());
if (conf.is_3d) {
conf.grid_depth = atoi(token.substr(token.find(',') + 1).c_str());
} else {
conf.grid_depth = 1;
}
break;
case 4:
conf.starting_temp = atof(buf.c_str());
break;
default:
// PARSE THE REMAIN FILE FOR FIXED BLOCKS
conf.blocks.push_back(line_to_block(conf.is_3d, buf));
break;
}
++count;
}
}
}
conf_file.close();
}
__global__ void init_grid_values(float * a, int size, float value) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
if (idx < size) {
a[idx] = value;
}
}
__global__ void copy_array_elements(float * lhs, float * rhs, int size) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
if (idx < size) {
lhs[idx] = rhs[idx];
}
}
__global__ void place_fixed_temp_block(float * array, int array_width, int array_height, int x, int y, int z, int w, int h, float value, int size) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
// 4d start = x
// + (y * array_width)
// + (z * array_width * array_height)
// + (a * array_width * array_height * array_depth)
// 4d offset = (idx % w)
// + array_width * (idx % (w * h)) / w)
// + (array_width * array_height) * ((idx % (w * h * d)) / (w * h))
// + (array_width * array_height * array_depth) * (idx / (w * h * d))
if (idx < size) {
int start = x + (y * array_width) + (z * array_width * array_height);
int index = start + (idx % w) + array_width * ((idx % (w * h)) / w) + (array_width * array_height) * (idx / (w * h));
array[index] = value;
}
}
__global__ void mono_3d (float * old_grid, float * new_grid, int size, int width, float k, int area) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
/* USE PTX assembly if nvcc doesn't automatically detect optimal instruction
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-mad
mad{.hi,.lo,.wide}.type d, a, b, c;
mad.hi.sat.s32 d, a, b, c;
.type = { .u16, .u32, .u64,
.s16, .s32, .s64 };
use: @p mad.wide.s32 idx, blockIDx.x, blockDim.x, threadIdx.x;
uint idx;
asm("mad.lo.u32 %0, %1, %2, %3"; : "=r"(idx) : "r"(blockIDx.x), "r"(blockDim.x), "r"(threadIdx.x));
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
*/
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
float oldValue = old_grid[idx];
float * newValueLoc = &new_grid[idx];
//left
if (idx < size) {
if (idx % width != 0) {
// if not out of range and not a left edge;
*newValueLoc += k * (old_grid[idx - 1] - oldValue);
}
//right
if (idx % width != width - 1) {
// if not out of range and not a right edge;
*newValueLoc += k * (old_grid[idx + 1] - oldValue);
}
if (idx % area >= width) {
// if not out of range and not a top edge;
*newValueLoc += k * (old_grid[idx - width] - oldValue);
}
if (idx % area < area - width) {
// if not out of range and not a bottom edge;
*newValueLoc += k * (old_grid[idx + width] - oldValue);
}
if (idx >= area) {
// if not out of range and not a front edge;
*newValueLoc += k * (old_grid[idx - area] - oldValue);
}
if (idx < size - area) {
// if not out of range and not a back edge;
*newValueLoc += k * (old_grid[idx + area] - oldValue);
}
}
}
__global__ void mono_2d (float * old_grid, float * new_grid, int size, int width, float k, int area) {
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
float oldValue = old_grid[idx];
float * newValueLoc = &new_grid[idx];
//left
if (idx < size) {
if (idx % width != 0) {
// if not out of range and not a left edge;
*newValueLoc += k * (old_grid[idx - 1] - oldValue);
}
//right
if (idx % width != width - 1) {
// if not out of range and not a right edge;
*newValueLoc += k * (old_grid[idx + 1] - oldValue);
}
if (idx % area >= width) {
// if not out of range and not a top edge;
*newValueLoc += k * (old_grid[idx - width] - oldValue);
}
if (idx % area < area - width) {
// if not out of range and not a bottom edge;
*newValueLoc += k * (old_grid[idx + width] - oldValue);
}
}
}
void copy_fixed_blocks (config_values & conf, int TPB, float *new_grid) {
// Copy fixed values into new_grid
for (int block_idx = 0; block_idx < conf.blocks.size(); ++block_idx) {
int blocks = (conf.blocks[block_idx].size + TPB - 1) / TPB;
place_fixed_temp_block<<<blocks, TPB>>>(new_grid, conf.grid_width, conf.grid_height,
conf.blocks[block_idx].x, conf.blocks[block_idx].y, conf.blocks[block_idx].z,
conf.blocks[block_idx].width, conf.blocks[block_idx].height, conf.blocks[block_idx].temp, conf.blocks[block_idx].size);
hipDeviceSynchronize();
}
}
void output_final_values (config_values & conf, float * host_grid) {
std::ofstream out_file("heatOutput.csv");
int index = 0;
for (int layer = 0; layer < conf.grid_depth - 1; ++layer) {
for (int row = 0; row < conf.grid_height; ++row) {
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
out_file << '\n';
}
for (int row = 0; row < conf.grid_height - 1; ++row) {
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
int main(int argc, char * argv[]) {
auto start = std::chrono::high_resolution_clock::now();
config_values conf;
std::string file_name(argv[1]);
set_config_values(conf, file_name);
int TPB = 512; // could change to a define (need to edit copy_fixed_blocks())
int area = conf.grid_width * conf.grid_height;
int size = area * conf.grid_depth;
int num_blocks = (size + TPB - 1) / TPB;
float * new_grid;
float * old_grid;
float * host_grid = new float[size];
auto stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> duration = (stop - start);
std::cout << duration.count() * 1000 * 1000 << "us" << '\n';
start = std::chrono::high_resolution_clock::now();
hipMalloc((void**) & new_grid, size * sizeof(float));
hipMalloc((void**) & old_grid, size * sizeof(float));
init_grid_values<<<num_blocks, TPB>>>(new_grid, size, conf.starting_temp);
hipDeviceSynchronize();
copy_fixed_blocks(conf , TPB, new_grid);
hipDeviceSynchronize();
if (conf.is_3d) {
for (int i = 0; i < conf.num_timesteps; ++i) {
copy_array_elements<<<num_blocks, TPB>>>(old_grid, new_grid, size); // old = new
hipDeviceSynchronize();
mono_3d<<<num_blocks, TPB>>>(old_grid, new_grid, size, conf.grid_width, conf.k, area);
hipDeviceSynchronize();
copy_fixed_blocks(conf, TPB, new_grid);
hipDeviceSynchronize();
}
} else {
for (int i = 0; i < conf.num_timesteps; ++i) {
copy_array_elements<<<num_blocks, TPB>>>(old_grid, new_grid, size); // old = new
hipDeviceSynchronize();
mono_2d<<<num_blocks, TPB>>>(old_grid, new_grid, size, conf.grid_width, conf.k, area);
hipDeviceSynchronize();
copy_fixed_blocks(conf, TPB, new_grid);
hipDeviceSynchronize();
}
}
hipMemcpy(host_grid, new_grid, size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(old_grid);
hipFree(new_grid);
stop = std::chrono::high_resolution_clock::now();
duration = (stop - start);
std::cout << duration.count() * 1000 * 1000 << "us" << '\n';
// Output host_grid values to files and std::cout
output_final_values(conf, host_grid);
delete[] host_grid;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <chrono>
#include <fstream>
#include <iostream>
#include <string>
#include <vector>
// TODO
// check if file parameter is present
// create array to reference heater locations instead of recalculating values
// make use of cuda shared memory
// restructure project
// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#independent-thread-scheduling
struct block{
uint32_t x;
uint32_t y;
uint32_t z;
uint32_t width;
uint32_t height;
uint32_t depth;
uint32_t size;
float temp;
};
struct config_values {
bool is_3d;
bool padding[3];
float k;
uint32_t num_timesteps;
uint32_t grid_width;
uint32_t grid_height;
uint32_t grid_depth;
float starting_temp;
std::vector<block> blocks;
};
block line_to_block(bool is_3d, std::string & line) {
block out_block;
std::string token;
out_block.x = atoi(line.substr(0, line.find(',')).c_str());
token = line.substr(line.find(',') + 1);
out_block.y = atoi(token.substr(0, token.find(',')).c_str());
if (is_3d) {
token = token.substr(token.find(',') + 1);
out_block.z = atoi(token.substr(0, token.find(',')).c_str());
} else {
out_block.z = 0;
}
token = token.substr(token.find(',') + 1);
out_block.width = atoi(token.substr(0, token.find(',')).c_str());
token = token.substr(token.find(',') + 1);
out_block.height = atoi(token.substr(0, token.find(',')).c_str());
if (is_3d) {
token = token.substr(token.find(',') + 1);
out_block.depth = atoi(token.substr(0, token.find(',')).c_str());
} else {
out_block.depth = 1;
}
token = token.substr(token.find(',') + 1);
out_block.temp = atof(token.substr(0, token.find(',')).c_str());
out_block.size = out_block.width * out_block.height * out_block.depth;
return out_block;
}
void set_config_values(config_values & conf, std::string & file_name) {
std::string buf;
std::string token;
uint8_t count = 0;
std::ifstream conf_file(file_name);
if (!conf_file) {
std::cerr << "Error opening config file.\n";
} else {
while (!conf_file.eof()) {
std::getline(conf_file, buf);
buf.erase(std::remove_if( buf.begin(), buf.end(), ::isspace ), buf.end());
// Filter out line that dont start with a number
if(buf[0 ]== '.' || (buf[0] != '#' && (buf[0] >= '0' && buf[0] <= '9'))) {
switch (count) {
case 0:
conf.is_3d = (buf[0] == '3');
break;
case 1:
conf.k = atof(buf.c_str());
break;
case 2:
conf.num_timesteps = atoi(buf.c_str());
break;
case 3:
// GRID SIZE
conf.grid_width = atoi(buf.substr(0, buf.find(',')).c_str());
token = buf.substr(buf.find(',') + 1);
conf.grid_height = atoi(token.substr(0, token.find(',')).c_str());
if (conf.is_3d) {
conf.grid_depth = atoi(token.substr(token.find(',') + 1).c_str());
} else {
conf.grid_depth = 1;
}
break;
case 4:
conf.starting_temp = atof(buf.c_str());
break;
default:
// PARSE THE REMAIN FILE FOR FIXED BLOCKS
conf.blocks.push_back(line_to_block(conf.is_3d, buf));
break;
}
++count;
}
}
}
conf_file.close();
}
__global__ void init_grid_values(float * a, int size, float value) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
if (idx < size) {
a[idx] = value;
}
}
__global__ void copy_array_elements(float * lhs, float * rhs, int size) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
if (idx < size) {
lhs[idx] = rhs[idx];
}
}
__global__ void place_fixed_temp_block(float * array, int array_width, int array_height, int x, int y, int z, int w, int h, float value, int size) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
// 4d start = x
// + (y * array_width)
// + (z * array_width * array_height)
// + (a * array_width * array_height * array_depth)
// 4d offset = (idx % w)
// + array_width * (idx % (w * h)) / w)
// + (array_width * array_height) * ((idx % (w * h * d)) / (w * h))
// + (array_width * array_height * array_depth) * (idx / (w * h * d))
if (idx < size) {
int start = x + (y * array_width) + (z * array_width * array_height);
int index = start + (idx % w) + array_width * ((idx % (w * h)) / w) + (array_width * array_height) * (idx / (w * h));
array[index] = value;
}
}
__global__ void mono_3d (float * old_grid, float * new_grid, int size, int width, float k, int area) {
//int idx = threadIdx.x + blockIdx.x * blockDim.x;
/* USE PTX assembly if nvcc doesn't automatically detect optimal instruction
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-mad
mad{.hi,.lo,.wide}.type d, a, b, c;
mad.hi.sat.s32 d, a, b, c;
.type = { .u16, .u32, .u64,
.s16, .s32, .s64 };
use: @p mad.wide.s32 idx, blockIDx.x, blockDim.x, threadIdx.x;
uint idx;
asm("mad.lo.u32 %0, %1, %2, %3"; : "=r"(idx) : "r"(blockIDx.x), "r"(blockDim.x), "r"(threadIdx.x));
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
*/
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
float oldValue = old_grid[idx];
float * newValueLoc = &new_grid[idx];
//left
if (idx < size) {
if (idx % width != 0) {
// if not out of range and not a left edge;
*newValueLoc += k * (old_grid[idx - 1] - oldValue);
}
//right
if (idx % width != width - 1) {
// if not out of range and not a right edge;
*newValueLoc += k * (old_grid[idx + 1] - oldValue);
}
if (idx % area >= width) {
// if not out of range and not a top edge;
*newValueLoc += k * (old_grid[idx - width] - oldValue);
}
if (idx % area < area - width) {
// if not out of range and not a bottom edge;
*newValueLoc += k * (old_grid[idx + width] - oldValue);
}
if (idx >= area) {
// if not out of range and not a front edge;
*newValueLoc += k * (old_grid[idx - area] - oldValue);
}
if (idx < size - area) {
// if not out of range and not a back edge;
*newValueLoc += k * (old_grid[idx + area] - oldValue);
}
}
}
__global__ void mono_2d (float * old_grid, float * new_grid, int size, int width, float k, int area) {
uint idx;
uint blkID = blockIdx.x;
uint blkDim = blockDim.x;
uint thrID = threadIdx.x;
asm("mad.lo.u32 %0, %1, %2, %3;" : "=r"(idx) : "r"(blkID), "r"(blkDim), "r"(thrID));
float oldValue = old_grid[idx];
float * newValueLoc = &new_grid[idx];
//left
if (idx < size) {
if (idx % width != 0) {
// if not out of range and not a left edge;
*newValueLoc += k * (old_grid[idx - 1] - oldValue);
}
//right
if (idx % width != width - 1) {
// if not out of range and not a right edge;
*newValueLoc += k * (old_grid[idx + 1] - oldValue);
}
if (idx % area >= width) {
// if not out of range and not a top edge;
*newValueLoc += k * (old_grid[idx - width] - oldValue);
}
if (idx % area < area - width) {
// if not out of range and not a bottom edge;
*newValueLoc += k * (old_grid[idx + width] - oldValue);
}
}
}
void copy_fixed_blocks (config_values & conf, int TPB, float *new_grid) {
// Copy fixed values into new_grid
for (int block_idx = 0; block_idx < conf.blocks.size(); ++block_idx) {
int blocks = (conf.blocks[block_idx].size + TPB - 1) / TPB;
place_fixed_temp_block<<<blocks, TPB>>>(new_grid, conf.grid_width, conf.grid_height,
conf.blocks[block_idx].x, conf.blocks[block_idx].y, conf.blocks[block_idx].z,
conf.blocks[block_idx].width, conf.blocks[block_idx].height, conf.blocks[block_idx].temp, conf.blocks[block_idx].size);
hipDeviceSynchronize();
}
}
void output_final_values (config_values & conf, float * host_grid) {
std::ofstream out_file("heatOutput.csv");
int index = 0;
for (int layer = 0; layer < conf.grid_depth - 1; ++layer) {
for (int row = 0; row < conf.grid_height; ++row) {
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
out_file << '\n';
}
for (int row = 0; row < conf.grid_height - 1; ++row) {
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
for(int col = 0; col < conf.grid_width - 1; ++col) {
out_file << host_grid[index++] << ", ";
}
out_file << host_grid[index++] << '\n';
}
int main(int argc, char * argv[]) {
auto start = std::chrono::high_resolution_clock::now();
config_values conf;
std::string file_name(argv[1]);
set_config_values(conf, file_name);
int TPB = 512; // could change to a define (need to edit copy_fixed_blocks())
int area = conf.grid_width * conf.grid_height;
int size = area * conf.grid_depth;
int num_blocks = (size + TPB - 1) / TPB;
float * new_grid;
float * old_grid;
float * host_grid = new float[size];
auto stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double> duration = (stop - start);
std::cout << duration.count() * 1000 * 1000 << "us" << '\n';
start = std::chrono::high_resolution_clock::now();
hipMalloc((void**) & new_grid, size * sizeof(float));
hipMalloc((void**) & old_grid, size * sizeof(float));
init_grid_values<<<num_blocks, TPB>>>(new_grid, size, conf.starting_temp);
hipDeviceSynchronize();
copy_fixed_blocks(conf , TPB, new_grid);
hipDeviceSynchronize();
if (conf.is_3d) {
for (int i = 0; i < conf.num_timesteps; ++i) {
copy_array_elements<<<num_blocks, TPB>>>(old_grid, new_grid, size); // old = new
hipDeviceSynchronize();
mono_3d<<<num_blocks, TPB>>>(old_grid, new_grid, size, conf.grid_width, conf.k, area);
hipDeviceSynchronize();
copy_fixed_blocks(conf, TPB, new_grid);
hipDeviceSynchronize();
}
} else {
for (int i = 0; i < conf.num_timesteps; ++i) {
copy_array_elements<<<num_blocks, TPB>>>(old_grid, new_grid, size); // old = new
hipDeviceSynchronize();
mono_2d<<<num_blocks, TPB>>>(old_grid, new_grid, size, conf.grid_width, conf.k, area);
hipDeviceSynchronize();
copy_fixed_blocks(conf, TPB, new_grid);
hipDeviceSynchronize();
}
}
hipMemcpy(host_grid, new_grid, size * sizeof(float), hipMemcpyDeviceToHost);
hipFree(old_grid);
hipFree(new_grid);
stop = std::chrono::high_resolution_clock::now();
duration = (stop - start);
std::cout << duration.count() * 1000 * 1000 << "us" << '\n';
// Output host_grid values to files and std::cout
output_final_values(conf, host_grid);
delete[] host_grid;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16init_grid_valuesPfif
.globl _Z16init_grid_valuesPfif
.p2align 8
.type _Z16init_grid_valuesPfif,@function
_Z16init_grid_valuesPfif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
mad.lo.u32 s2, s15, s2, v0
v_cmp_ge_u32_e64 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s3, s3, exec_lo
s_cbranch_scc1 .LBB0_2
s_clause 0x1
s_load_b32 s4, s[0:1], 0xc
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s3, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16init_grid_valuesPfif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16init_grid_valuesPfif, .Lfunc_end0-_Z16init_grid_valuesPfif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19copy_array_elementsPfS_i
.globl _Z19copy_array_elementsPfS_i
.p2align 8
.type _Z19copy_array_elementsPfS_i,@function
_Z19copy_array_elementsPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
mad.lo.u32 s2, s15, s2, v0
v_cmp_ge_u32_e64 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s3, s3, exec_lo
s_cbranch_scc1 .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s6, s0
s_addc_u32 s3, s7, s1
s_add_u32 s0, s4, s0
s_load_b32 s2, s[2:3], 0x0
v_mov_b32_e32 v0, 0
s_addc_u32 s1, s5, s1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v1, s2
global_store_b32 v0, v1, s[0:1]
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19copy_array_elementsPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19copy_array_elementsPfS_i, .Lfunc_end1-_Z19copy_array_elementsPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22place_fixed_temp_blockPfiiiiiiifi
.globl _Z22place_fixed_temp_blockPfiiiiiiifi
.p2align 8
.type _Z22place_fixed_temp_blockPfiiiiiiifi,@function
_Z22place_fixed_temp_blockPfiiiiiiifi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
mad.lo.u32 s2, s15, s2, v0
v_cmp_ge_u32_e64 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s3, s3, exec_lo
s_cbranch_scc1 .LBB2_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s11
s_mul_i32 s0, s0, s11
s_sub_i32 s12, 0, s11
v_cvt_f32_u32_e32 v1, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_readfirstlane_b32 s3, v0
v_dual_mul_f32 v0, 0x4f7ffffe, v1 :: v_dual_mov_b32 v1, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s12, s12, s3
v_cvt_u32_f32_e32 v0, v0
s_mul_hi_u32 s12, s3, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s12
s_mul_hi_u32 s12, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s12, s11
s_sub_i32 s12, s2, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s13, s12, s11
s_cmp_ge_u32 s12, s11
s_cselect_b32 s12, s13, s12
v_readfirstlane_b32 s13, v0
s_sub_i32 s14, s12, s11
s_cmp_ge_u32 s12, s11
v_mov_b32_e32 v0, 0
s_cselect_b32 s12, s14, s12
s_sub_i32 s14, 0, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s14, s14, s13
s_mul_hi_u32 s14, s13, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s14
s_mul_hi_u32 s13, s2, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s14, s13, s0
s_add_i32 s15, s13, 1
s_sub_i32 s14, s2, s14
s_sub_i32 s16, s14, s0
s_cmp_ge_u32 s14, s0
s_cselect_b32 s13, s15, s13
s_cselect_b32 s14, s16, s14
s_add_i32 s15, s13, 1
s_cmp_ge_u32 s14, s0
s_cselect_b32 s13, s15, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s0, s13, s0
s_sub_i32 s0, s2, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s0, s3
s_mul_i32 s3, s2, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s0, s0, s3
s_add_i32 s3, s2, 1
s_sub_i32 s14, s0, s11
s_cmp_ge_u32 s0, s11
s_cselect_b32 s2, s3, s2
s_cselect_b32 s0, s14, s0
s_add_i32 s3, s2, 1
s_cmp_ge_u32 s0, s11
s_cselect_b32 s0, s3, s2
s_add_i32 s2, s13, s10
s_add_i32 s0, s0, s9
s_mul_i32 s2, s2, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s2
s_add_i32 s2, s12, s8
s_mul_i32 s0, s0, s6
s_add_i32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s2
s_addc_u32 s1, s5, s3
global_store_b32 v0, v1, s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22place_fixed_temp_blockPfiiiiiiifi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 17
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z22place_fixed_temp_blockPfiiiiiiifi, .Lfunc_end2-_Z22place_fixed_temp_blockPfiiiiiiifi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mono_3dPfS_iifi
.globl _Z7mono_3dPfS_iifi
.p2align 8
.type _Z7mono_3dPfS_iifi,@function
_Z7mono_3dPfS_iifi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
mad.lo.u32 s8, s15, s2, v0
v_cmp_ge_u32_e64 s2, s8, s10
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, s2, exec_lo
s_cbranch_scc1 .LBB3_13
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[8:9], 2
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s2
s_add_u32 s14, s4, s12
s_addc_u32 s15, s5, s13
s_add_u32 s6, s6, s12
s_addc_u32 s7, s7, s13
v_rcp_iflag_f32_e32 v0, v0
s_sub_i32 s12, 0, s2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_readfirstlane_b32 s11, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s12, s12, s11
s_mul_hi_u32 s12, s11, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s11, s12
s_load_b32 s11, s[14:15], 0x0
s_mul_hi_u32 s12, s8, s12
s_mul_i32 s12, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s12, s8, s12
s_sub_i32 s13, s12, s2
s_cmp_ge_u32 s12, s2
s_cselect_b32 s12, s13, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s13, s12, s2
s_cmp_ge_u32 s12, s2
s_cselect_b32 s12, s13, s12
s_cmp_eq_u32 s12, 0
s_cbranch_scc1 .LBB3_3
s_add_i32 s14, s8, -1
s_mov_b32 s15, s9
v_mov_b32_e32 v1, 0
s_lshl_b64 s[14:15], s[14:15], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s4, s14
s_addc_u32 s15, s5, s15
s_load_b32 s9, s[14:15], 0x0
s_load_b32 s13, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v0, s9, s11
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v0, v0, s3, s13
global_store_b32 v1, v0, s[6:7]
.LBB3_3:
s_add_i32 s9, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s9
s_cbranch_scc1 .LBB3_5
s_add_i32 s12, s8, 1
s_mov_b32 s13, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[12:13], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_clause 0x1
global_load_b32 v1, v0, s[12:13]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1) lgkmcnt(0)
v_subrev_f32_e32 v1, s11, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB3_5:
s_load_b32 s9, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s1, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v0
s_mul_i32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s0, s1
s_add_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s0, s8, s0
s_mul_i32 s0, s0, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s0, s8, s0
s_sub_i32 s1, s0, s9
s_cmp_ge_u32 s0, s9
s_cselect_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s1, s0, s9
s_cmp_ge_u32 s0, s9
s_cselect_b32 s12, s1, s0
s_mov_b32 s1, 0
s_cmp_lt_u32 s12, s2
s_cbranch_scc1 .LBB3_7
s_sub_i32 s0, s8, s2
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1)
v_subrev_f32_e32 v1, s11, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB3_7:
s_sub_i32 s0, s9, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s12, s0
s_cbranch_scc1 .LBB3_9
s_add_i32 s0, s8, s2
s_mov_b32 s1, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1)
v_subrev_f32_e32 v1, s11, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB3_9:
s_cmp_lt_u32 s8, s9
s_cbranch_scc1 .LBB3_11
s_sub_i32 s0, s8, s9
s_mov_b32 s1, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1)
v_subrev_f32_e32 v1, s11, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB3_11:
s_sub_i32 s0, s10, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s8, s0
s_cbranch_scc1 .LBB3_13
s_add_i32 s0, s8, s9
s_mov_b32 s1, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1)
v_subrev_f32_e32 v1, s11, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB3_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mono_3dPfS_iifi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z7mono_3dPfS_iifi, .Lfunc_end3-_Z7mono_3dPfS_iifi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7mono_2dPfS_iifi
.globl _Z7mono_2dPfS_iifi
.p2align 8
.type _Z7mono_2dPfS_iifi,@function
_Z7mono_2dPfS_iifi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
mad.lo.u32 s8, s15, s2, v0
v_cmp_ge_u32_e64 s2, s8, s3
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s2, s2, exec_lo
s_cbranch_scc1 .LBB4_9
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s9, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s2
s_add_u32 s12, s4, s10
s_addc_u32 s13, s5, s11
s_add_u32 s6, s6, s10
s_addc_u32 s7, s7, s11
v_rcp_iflag_f32_e32 v0, v0
s_sub_i32 s10, 0, s2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_readfirstlane_b32 s14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s10, s14
s_mul_hi_u32 s10, s14, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s14, s14, s10
s_load_b32 s10, s[12:13], 0x0
s_mul_hi_u32 s11, s8, s14
s_mul_i32 s11, s11, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s11, s8, s11
s_sub_i32 s12, s11, s2
s_cmp_ge_u32 s11, s2
s_cselect_b32 s11, s12, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_sub_i32 s12, s11, s2
s_cmp_ge_u32 s11, s2
s_cselect_b32 s11, s12, s11
s_cmp_eq_u32 s11, 0
s_cbranch_scc1 .LBB4_3
s_add_i32 s12, s8, -1
s_mov_b32 s13, s9
v_mov_b32_e32 v1, 0
s_lshl_b64 s[12:13], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_load_b32 s9, s[12:13], 0x0
s_load_b32 s12, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v0, s9, s10
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v0, v0, s3, s12
global_store_b32 v1, v0, s[6:7]
.LBB4_3:
s_add_i32 s9, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s9
s_cbranch_scc1 .LBB4_5
s_add_i32 s12, s8, 1
s_mov_b32 s13, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[12:13], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s12, s4, s12
s_addc_u32 s13, s5, s13
s_clause 0x1
global_load_b32 v1, v0, s[12:13]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1) lgkmcnt(0)
v_subrev_f32_e32 v1, s10, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB4_5:
s_load_b32 s9, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s1, 0, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v0
s_mul_i32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s0, s1
s_add_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s0, s8, s0
s_mul_i32 s0, s0, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s0, s8, s0
s_sub_i32 s1, s0, s9
s_cmp_ge_u32 s0, s9
s_cselect_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s1, s0, s9
s_cmp_ge_u32 s0, s9
s_cselect_b32 s11, s1, s0
s_mov_b32 s1, 0
s_cmp_lt_u32 s11, s2
s_cbranch_scc1 .LBB4_7
s_sub_i32 s0, s8, s2
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1)
v_subrev_f32_e32 v1, s10, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB4_7:
s_sub_i32 s0, s9, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s11, s0
s_cbranch_scc1 .LBB4_9
s_add_i32 s0, s8, s2
s_mov_b32 s1, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(1)
v_subrev_f32_e32 v1, s10, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s3, v1
global_store_b32 v0, v2, s[6:7]
.LBB4_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7mono_2dPfS_iifi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z7mono_2dPfS_iifi, .Lfunc_end4-_Z7mono_2dPfS_iifi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16init_grid_valuesPfif
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z16init_grid_valuesPfif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19copy_array_elementsPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z19copy_array_elementsPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22place_fixed_temp_blockPfiiiiiiifi
.private_segment_fixed_size: 0
.sgpr_count: 17
.sgpr_spill_count: 0
.symbol: _Z22place_fixed_temp_blockPfiiiiiiifi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mono_3dPfS_iifi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z7mono_3dPfS_iifi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7mono_2dPfS_iifi
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z7mono_2dPfS_iifi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void GetScaleFactorsKernel(float *indata, float *base, float *stdev, float *factors, int nchans, int processed) {
// NOTE: Filterbank file format coming in
//float mean = indata[threadIdx.x];
float mean = 0.0f;
// NOTE: Depending whether I save STD or VAR at the end of every run
// float estd = stdev[threadIdx.x];
float estd = stdev[threadIdx.x] * stdev[threadIdx.x] * (processed - 1.0f);
float oldmean = base[threadIdx.x];
//float estd = 0.0f;
//float oldmean = 0.0;
float val = 0.0f;
float diff = 0.0;
for (int isamp = 0; isamp < 2 * NACCUMULATE; ++isamp) {
val = indata[isamp * nchans + threadIdx.x];
diff = val - oldmean;
mean = oldmean + diff * factors[processed + isamp + 1];
estd += diff * (val - mean);
oldmean = mean;
}
base[threadIdx.x] = mean;
stdev[threadIdx.x] = sqrtf(estd / (float)(processed + 2 * NACCUMULATE - 1.0f));
// stdev[threadIdx.x] = estd;
} | code for sm_80
Function : _Z21GetScaleFactorsKernelPfS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R28, SR_TID.X ; /* 0x00000000001c7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R14, R28, R3, c[0x0][0x170] ; /* 0x00005c001c0e7625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R14.64] ; /* 0x000000040e007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R16, R28, R3, c[0x0][0x168] ; /* 0x00005a001c107625 */
/* 0x000fca00078e0003 */
/*0070*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000162000c1e1900 */
/*0080*/ I2F R2, c[0x0][0x184] ; /* 0x0000610000027b06 */
/* 0x000e620000201400 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R12, c[0x0][0x178] ; /* 0x00005e00000c7a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0d7624 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R8, R28, c[0x0][0x180], RZ ; /* 0x000060001c087a10 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R10, R5.reuse, 0x3, R28.reuse ; /* 0x00000003050a7824 */
/* 0x140fe200078e021c */
/*0100*/ IADD3 R7, R4, 0x1, RZ ; /* 0x0000000104077810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R6, R5, 0x4, R28 ; /* 0x0000000405067824 */
/* 0x000fc400078e021c */
/*0120*/ IMAD R24, R5.reuse, 0x5, R28.reuse ; /* 0x0000000505187824 */
/* 0x140fe400078e021c */
/*0130*/ IMAD R26, R5.reuse, 0x6, R28 ; /* 0x00000006051a7824 */
/* 0x040fe400078e021c */
/*0140*/ FADD R11, R2, -1 ; /* 0xbf800000020b7421 */
/* 0x002fe20000000000 */
/*0150*/ LEA R2, R5, R28, 0x1 ; /* 0x0000001c05027211 */
/* 0x000fe200078e08ff */
/*0160*/ FMUL R0, R0, R0 ; /* 0x0000000000007220 */
/* 0x004fc80000400000 */
/*0170*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x000fe40000400000 */
/*0180*/ IMAD R0, R5, 0x7, R28 ; /* 0x0000000705007824 */
/* 0x001fe400078e021c */
/*0190*/ IMAD.WIDE.U32 R18, R28, R3, c[0x0][0x160] ; /* 0x000058001c127625 */
/* 0x000fc800078e0003 */
/*01a0*/ IMAD.WIDE R20, R7, 0x4, R12 ; /* 0x0000000407147825 */
/* 0x000fe200078e020c */
/*01b0*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x0000a8000c1e1900 */
/*01c0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R18, R8, R3, c[0x0][0x160] ; /* 0x0000580008127625 */
/* 0x001fca00078e0003 */
/*01e0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000128000c1e1900 */
/*01f0*/ LDG.E R18, [R20.64+0x8] ; /* 0x0000080414127981 */
/* 0x001f22000c1e1900 */
/*0200*/ FADD R27, R29, -R23 ; /* 0x800000171d1b7221 */
/* 0x024fc80000000000 */
/*0210*/ FFMA R22, R27, R22, R23 ; /* 0x000000161b167223 */
/* 0x008fe40000000017 */
/*0220*/ LDG.E R23, [R20.64+0x4] ; /* 0x0000040414177981 */
/* 0x000ea4000c1e1900 */
/*0230*/ FADD R29, R29, -R22 ; /* 0x800000161d1d7221 */
/* 0x000fc80000000000 */
/*0240*/ FFMA R27, R27, R29, R11 ; /* 0x0000001d1b1b7223 */
/* 0x000fe4000000000b */
/*0250*/ FADD R29, -R22, R25 ; /* 0x00000019161d7221 */
/* 0x010fc80000000100 */
/*0260*/ FFMA R11, R29, R23, R22 ; /* 0x000000171d0b7223 */
/* 0x004fe40000000016 */
/*0270*/ IMAD.WIDE.U32 R22, R2, R3, c[0x0][0x160] ; /* 0x0000580002167625 */
/* 0x000fcc00078e0003 */
/*0280*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea2000c1e1900 */
/*0290*/ FADD R25, R25, -R11 ; /* 0x8000000b19197221 */
/* 0x000fc80000000000 */
/*02a0*/ FFMA R27, R29, R25, R27 ; /* 0x000000191d1b7223 */
/* 0x000fe4000000001b */
/*02b0*/ LDG.E R29, [R20.64+0xc] ; /* 0x00000c04141d7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FADD R25, -R11, R22 ; /* 0x000000160b197221 */
/* 0x004fc80000000100 */
/*02d0*/ FFMA R11, R25, R18, R11 ; /* 0x00000012190b7223 */
/* 0x000fe4000000000b */
/*02e0*/ IMAD.WIDE.U32 R18, R10, R3, c[0x0][0x160] ; /* 0x000058000a127625 */
/* 0x000fcc00078e0003 */
/*02f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1900 */
/*0300*/ FADD R22, R22, -R11 ; /* 0x8000000b16167221 */
/* 0x000fc80000000000 */
/*0310*/ FFMA R27, R25, R22, R27 ; /* 0x00000016191b7223 */
/* 0x000fe4000000001b */
/*0320*/ IMAD.WIDE.U32 R22, R6, R3, c[0x0][0x160] ; /* 0x0000580006167625 */
/* 0x000fcc00078e0003 */
/*0330*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f22000c1e1900 */
/*0340*/ FADD R25, -R11, R18 ; /* 0x000000120b197221 */
/* 0x004fc80000000100 */
/*0350*/ FFMA R11, R25, R29, R11 ; /* 0x0000001d190b7223 */
/* 0x008fe4000000000b */
/*0360*/ LDG.E R29, [R20.64+0x10] ; /* 0x00001004141d7981 */
/* 0x000ea4000c1e1900 */
/*0370*/ FADD R18, R18, -R11 ; /* 0x8000000b12127221 */
/* 0x000fc80000000000 */
/*0380*/ FFMA R27, R25, R18, R27 ; /* 0x00000012191b7223 */
/* 0x000fe4000000001b */
/*0390*/ IMAD.WIDE.U32 R18, R24, R3, c[0x0][0x160] ; /* 0x0000580018127625 */
/* 0x000fc800078e0003 */
/*03a0*/ FADD R25, -R11, R22 ; /* 0x000000160b197221 */
/* 0x010fe40000000100 */
/*03b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1900 */
/*03c0*/ FFMA R11, R25, R29, R11 ; /* 0x0000001d190b7223 */
/* 0x004fe4000000000b */
/*03d0*/ LDG.E R29, [R20.64+0x14] ; /* 0x00001404141d7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FADD R22, R22, -R11 ; /* 0x8000000b16167221 */
/* 0x000fc80000000000 */
/*03f0*/ FFMA R27, R25, R22, R27 ; /* 0x00000016191b7223 */
/* 0x000fe4000000001b */
/*0400*/ FADD R25, -R11, R18 ; /* 0x000000120b197221 */
/* 0x008fe40000000100 */
/*0410*/ IMAD.WIDE.U32 R22, R26, R3, c[0x0][0x160] ; /* 0x000058001a167625 */
/* 0x000fcc00078e0003 */
/*0420*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e8000c1e1900 */
/*0430*/ LDG.E R23, [R20.64+0x1c] ; /* 0x00001c0414177981 */
/* 0x001f22000c1e1900 */
/*0440*/ FFMA R11, R25, R29, R11 ; /* 0x0000001d190b7223 */
/* 0x004fc6000000000b */
/*0450*/ LDG.E R29, [R20.64+0x18] ; /* 0x00001804141d7981 */
/* 0x000ea2000c1e1900 */
/*0460*/ FADD R18, R18, -R11 ; /* 0x8000000b12127221 */
/* 0x000fc80000000000 */
/*0470*/ FFMA R27, R25, R18, R27 ; /* 0x00000012191b7223 */
/* 0x000fe4000000001b */
/*0480*/ IMAD.WIDE.U32 R18, R0, R3, c[0x0][0x160] ; /* 0x0000580000127625 */
/* 0x000fcc00078e0003 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1900 */
/*04a0*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ FADD R25, -R11, R22 ; /* 0x000000160b197221 */
/* 0x008fc60000000100 */
/*04c0*/ ISETP.NE.AND P0, PT, R9, 0x200, PT ; /* 0x000002000900780c */
/* 0x000fe40003f05270 */
/*04d0*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x000fe20007f3e0ff */
/*04e0*/ IMAD R10, R5.reuse, 0x8, R10 ; /* 0x00000008050a7824 */
/* 0x040fe200078e020a */
/*04f0*/ LEA R8, R5.reuse, R8, 0x3 ; /* 0x0000000805087211 */
/* 0x040fe200078e18ff */
/*0500*/ IMAD R26, R5.reuse, 0x8, R26 ; /* 0x00000008051a7824 */
/* 0x040fe200078e021a */
/*0510*/ LEA R2, R5.reuse, R2, 0x3 ; /* 0x0000000205027211 */
/* 0x040fe200078e18ff */
/*0520*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0530*/ LEA R6, R5.reuse, R6, 0x3 ; /* 0x0000000605067211 */
/* 0x040fe400078e18ff */
/*0540*/ LEA R24, R5, R24, 0x3 ; /* 0x0000001805187211 */
/* 0x000fc400078e18ff */
/*0550*/ LEA R28, R5.reuse, R28, 0x3 ; /* 0x0000001c051c7211 */
/* 0x040fe400078e18ff */
/*0560*/ LEA R0, R5, R0, 0x3 ; /* 0x0000000005007211 */
/* 0x000fe200078e18ff */
/*0570*/ FFMA R29, R25, R29, R11 ; /* 0x0000001d191d7223 */
/* 0x004fc8000000000b */
/*0580*/ FADD R22, R22, -R29 ; /* 0x8000001d16167221 */
/* 0x000fe40000000000 */
/*0590*/ FADD R11, -R29, R18 ; /* 0x000000121d0b7221 */
/* 0x010fc80000000100 */
/*05a0*/ FFMA R23, R11, R23, R29 ; /* 0x000000170b177223 */
/* 0x000fe4000000001d */
/*05b0*/ FFMA R22, R25, R22, R27 ; /* 0x0000001619167223 */
/* 0x000fe4000000001b */
/*05c0*/ FADD R25, R18, -R23 ; /* 0x8000001712197221 */
/* 0x000fc80000000000 */
/*05d0*/ FFMA R11, R11, R25, R22 ; /* 0x000000190b0b7223 */
/* 0x000fe20000000016 */
/*05e0*/ @P0 BRA 0x190 ; /* 0xfffffba000000947 */
/* 0x000fea000383ffff */
/*05f0*/ IADD3 R4, R4, 0x200, RZ ; /* 0x0000020004047810 */
/* 0x000fe20007ffe0ff */
/*0600*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e2000c101904 */
/*0610*/ BSSY B0, 0x700 ; /* 0x000000e000007945 */
/* 0x000fe80003800000 */
/*0620*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e640000201400 */
/*0630*/ FADD R2, R4, -1 ; /* 0xbf80000004027421 */
/* 0x002fcc0000000000 */
/*0640*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x000e700000001000 */
/*0650*/ FCHK P0, R11, R2 ; /* 0x000000020b007302 */
/* 0x000ea20000000000 */
/*0660*/ FFMA R0, -R2, R3, 1 ; /* 0x3f80000002007423 */
/* 0x002fc80000000103 */
/*0670*/ FFMA R0, R3, R0, R3 ; /* 0x0000000003007223 */
/* 0x000fc80000000003 */
/*0680*/ FFMA R3, R11, R0, RZ ; /* 0x000000000b037223 */
/* 0x000fc800000000ff */
/*0690*/ FFMA R5, -R2, R3, R11 ; /* 0x0000000302057223 */
/* 0x000fc8000000010b */
/*06a0*/ FFMA R0, R0, R5, R3 ; /* 0x0000000500007223 */
/* 0x000fe20000000003 */
/*06b0*/ @!P0 BRA 0x6f0 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*06c0*/ MOV R0, 0x6e0 ; /* 0x000006e000007802 */
/* 0x001fe40000000f00 */
/*06d0*/ CALL.REL.NOINC 0x970 ; /* 0x0000029000007944 */
/* 0x000fea0003c00000 */
/*06e0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0700*/ IADD3 R2, R0, -0xd000000, RZ ; /* 0xf300000000027810 */
/* 0x000fe20007ffe0ff */
/*0710*/ MUFU.RSQ R5, R0 ; /* 0x0000000000057308 */
/* 0x0000620000001400 */
/*0720*/ BSSY B0, 0x7f0 ; /* 0x000000c000007945 */
/* 0x000fe40003800000 */
/*0730*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*0740*/ @!P0 BRA 0x7a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0750*/ MOV R6, R0 ; /* 0x0000000000067202 */
/* 0x003fe40000000f00 */
/*0760*/ MOV R7, 0x780 ; /* 0x0000078000077802 */
/* 0x000fe40000000f00 */
/*0770*/ CALL.REL.NOINC 0x810 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0000 */
/*0790*/ BRA 0x7e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07a0*/ FMUL.FTZ R3, R5.reuse, R0 ; /* 0x0000000005037220 */
/* 0x043fe40000410000 */
/*07b0*/ FMUL.FTZ R2, R5, 0.5 ; /* 0x3f00000005027820 */
/* 0x000fe40000410000 */
/*07c0*/ FFMA R0, -R3, R3, R0 ; /* 0x0000000303007223 */
/* 0x000fc80000000100 */
/*07d0*/ FFMA R3, R0, R2, R3 ; /* 0x0000000200037223 */
/* 0x000fe40000000003 */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ STG.E [R14.64], R3 ; /* 0x000000030e007986 */
/* 0x000fe2000c101904 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0820*/ @!P0 MOV R0, R6 ; /* 0x0000000600008202 */
/* 0x000fe20000000f00 */
/*0830*/ @!P0 BRA 0x940 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0840*/ FSETP.GEU.FTZ.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fda0003f1e000 */
/*0850*/ @!P0 MOV R0, 0x7fffffff ; /* 0x7fffffff00008802 */
/* 0x000fe20000000f00 */
/*0860*/ @!P0 BRA 0x940 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0870*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1c200 */
/*0880*/ @P0 FADD.FTZ R0, R6, 1 ; /* 0x3f80000006000421 */
/* 0x000fe20000010000 */
/*0890*/ @P0 BRA 0x940 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*08a0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1d200 */
/*08b0*/ @P0 FFMA R2, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006020823 */
/* 0x000fc800000000ff */
/*08c0*/ @P0 MUFU.RSQ R3, R2 ; /* 0x0000000200030308 */
/* 0x000e240000001400 */
/*08d0*/ @P0 FMUL.FTZ R5, R2, R3 ; /* 0x0000000302050220 */
/* 0x001fe40000410000 */
/*08e0*/ @P0 FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003030820 */
/* 0x000fe40000410000 */
/*08f0*/ @P0 FADD.FTZ R0, -R5, -RZ ; /* 0x800000ff05000221 */
/* 0x000fc80000010100 */
/*0900*/ @P0 FFMA R4, R5, R0, R2 ; /* 0x0000000005040223 */
/* 0x000fe40000000002 */
/*0910*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff008224 */
/* 0x000fe400078e0006 */
/*0920*/ @P0 FFMA R3, R4, R3, R5 ; /* 0x0000000304030223 */
/* 0x000fc80000000005 */
/*0930*/ @P0 FMUL.FTZ R0, R3, 2.3283064365386962891e-10 ; /* 0x2f80000003000820 */
/* 0x000fe40000410000 */
/*0940*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0950*/ MOV R2, R7 ; /* 0x0000000700027202 */
/* 0x000fca0000000f00 */
/*0960*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff69002007950 */
/* 0x000fea0003c3ffff */
/*0970*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fe20000011602 */
/*0980*/ BSSY B1, 0xfd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0990*/ SHF.R.U32.HI R3, RZ, 0x17, R11.reuse ; /* 0x00000017ff037819 */
/* 0x100fe4000001160b */
/*09a0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*09b0*/ LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03097812 */
/* 0x000fe200078ec0ff */
/*09c0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000b */
/*09d0*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R8, R9, -0x1, RZ ; /* 0xffffffff09087810 */
/* 0x000fc40007ffe0ff */
/*09f0*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fe40003f04070 */
/*0a00*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*0a10*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*0a20*/ @!P0 MOV R5, RZ ; /* 0x000000ff00058202 */
/* 0x000fe20000000f00 */
/*0a30*/ @!P0 BRA 0xbb0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a40*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*0a50*/ FSETP.GTU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f3c200 */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0a70*/ @P0 BRA 0xfb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c803 */
/*0a90*/ @!P0 BRA 0xf90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ FSETP.NEU.FTZ.AND P2, PT, |R11|.reuse, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x040fe40003f5d200 */
/*0ab0*/ FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f3d200 */
/*0ac0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*0ad0*/ @!P1 BRA !P2, 0xf90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0ae0*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*0af0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b00*/ @P1 BRA 0xf70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b10*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0b20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0b30*/ @P0 BRA 0xf40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0b50*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f26270 */
/*0b60*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe200078e00ff */
/*0b70*/ @!P0 MOV R5, 0xffffffc0 ; /* 0xffffffc000058802 */
/* 0x000fe20000000f00 */
/*0b80*/ @!P0 FFMA R3, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b038823 */
/* 0x000fe400000000ff */
/*0b90*/ @!P1 FFMA R6, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002069823 */
/* 0x000fe200000000ff */
/*0ba0*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0bb0*/ LEA R7, R4, 0xc0800000, 0x17 ; /* 0xc080000004077811 */
/* 0x000fe200078eb8ff */
/*0bc0*/ BSSY B2, 0xf30 ; /* 0x0000036000027945 */
/* 0x000fe60003800000 */
/*0bd0*/ IADD3 R7, -R7, R6, RZ ; /* 0x0000000607077210 */
/* 0x000fe40007ffe1ff */
/*0be0*/ IADD3 R6, R9, -0x7f, RZ ; /* 0xffffff8109067810 */
/* 0x000fc40007ffe0ff */
/*0bf0*/ MUFU.RCP R2, R7 ; /* 0x0000000700027308 */
/* 0x000e220000001000 */
/*0c00*/ FADD.FTZ R8, -R7, -RZ ; /* 0x800000ff07087221 */
/* 0x000fe20000010100 */
/*0c10*/ IADD3 R4, R6.reuse, 0x7f, -R4 ; /* 0x0000007f06047810 */
/* 0x040fe20007ffe804 */
/*0c20*/ IMAD R3, R6, -0x800000, R3 ; /* 0xff80000006037824 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x000fe400078e0205 */
/*0c40*/ FFMA R9, R2, R8, 1 ; /* 0x3f80000002097423 */
/* 0x001fc80000000008 */
/*0c50*/ FFMA R10, R2, R9, R2 ; /* 0x00000009020a7223 */
/* 0x000fc80000000002 */
/*0c60*/ FFMA R2, R3, R10, RZ ; /* 0x0000000a03027223 */
/* 0x000fc800000000ff */
/*0c70*/ FFMA R9, R8, R2, R3 ; /* 0x0000000208097223 */
/* 0x000fc80000000003 */
/*0c80*/ FFMA R9, R10, R9, R2 ; /* 0x000000090a097223 */
/* 0x000fc80000000002 */
/*0c90*/ FFMA R8, R8, R9, R3 ; /* 0x0000000908087223 */
/* 0x000fc80000000003 */
/*0ca0*/ FFMA R2, R10, R8, R9 ; /* 0x000000080a027223 */
/* 0x000fca0000000009 */
/*0cb0*/ SHF.R.U32.HI R3, RZ, 0x17, R2 ; /* 0x00000017ff037819 */
/* 0x000fc80000011602 */
/*0cc0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fc800078ec0ff */
/*0cd0*/ IADD3 R7, R3, R4, RZ ; /* 0x0000000403077210 */
/* 0x000fc80007ffe0ff */
/*0ce0*/ IADD3 R3, R7, -0x1, RZ ; /* 0xffffffff07037810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*0d00*/ @!P0 BRA 0xf10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d10*/ ISETP.GT.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f04270 */
/*0d20*/ @P0 BRA 0xee0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0d30*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f06270 */
/*0d40*/ @P0 BRA 0xf20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0d50*/ ISETP.GE.AND P0, PT, R7, -0x18, PT ; /* 0xffffffe80700780c */
/* 0x000fe40003f06270 */
/*0d60*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fd600078ec0ff */
/*0d70*/ @!P0 BRA 0xf20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0d80*/ FFMA.RZ R3, R10.reuse, R8.reuse, R9.reuse ; /* 0x000000080a037223 */
/* 0x1c0fe2000000c009 */
/*0d90*/ IADD3 R6, R7.reuse, 0x20, RZ ; /* 0x0000002007067810 */
/* 0x040fe20007ffe0ff */
/*0da0*/ FFMA.RM R4, R10.reuse, R8.reuse, R9.reuse ; /* 0x000000080a047223 */
/* 0x1c0fe20000004009 */
/*0db0*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f45270 */
/*0dc0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*0dd0*/ FFMA.RP R3, R10, R8, R9 ; /* 0x000000080a037223 */
/* 0x000fe20000008009 */
/*0de0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*0df0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe400078efcff */
/*0e00*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fc40007ffe1ff */
/*0e10*/ SHF.L.U32 R6, R5, R6, RZ ; /* 0x0000000605067219 */
/* 0x000fe400000006ff */
/*0e20*/ FSETP.NEU.FTZ.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x000fe40003f1d000 */
/*0e30*/ SEL R4, R7, RZ, P2 ; /* 0x000000ff07047207 */
/* 0x000fe40001000000 */
/*0e40*/ ISETP.NE.AND P1, PT, R6, RZ, P1 ; /* 0x000000ff0600720c */
/* 0x000fe40000f25270 */
/*0e50*/ SHF.R.U32.HI R4, RZ, R4, R5 ; /* 0x00000004ff047219 */
/* 0x000fe40000011605 */
/*0e60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0e70*/ SHF.R.U32.HI R6, RZ, 0x1, R4 ; /* 0x00000001ff067819 */
/* 0x000fe40000011604 */
/*0e80*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*0e90*/ LOP3.LUT R3, R3, 0x1, R6, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef806 */
/*0ea0*/ LOP3.LUT R3, R3, R4, RZ, 0xc0, !PT ; /* 0x0000000403037212 */
/* 0x000fc800078ec0ff */
/*0eb0*/ IADD3 R3, R6, R3, RZ ; /* 0x0000000306037210 */
/* 0x000fc80007ffe0ff */
/*0ec0*/ LOP3.LUT R2, R3, R2, RZ, 0xfc, !PT ; /* 0x0000000203027212 */
/* 0x000fe200078efcff */
/*0ed0*/ BRA 0xf20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fc800078ec0ff */
/*0ef0*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0f00*/ BRA 0xf20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f10*/ IMAD R2, R4, 0x800000, R2 ; /* 0x0080000004027824 */
/* 0x000fe400078e0202 */
/*0f20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f30*/ BRA 0xfc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0f40*/ LOP3.LUT R2, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006027812 */
/* 0x000fc800078e4803 */
/*0f50*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0f60*/ BRA 0xfc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0f70*/ LOP3.LUT R2, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006027812 */
/* 0x000fe200078e4803 */
/*0f80*/ BRA 0xfc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0f90*/ MUFU.RSQ R2, -QNAN ; /* 0xffc0000000027908 */
/* 0x000e220000001400 */
/*0fa0*/ BRA 0xfc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ FADD.FTZ R2, R11, R2 ; /* 0x000000020b027221 */
/* 0x000fe40000010000 */
/*0fc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0fd0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0fe0*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x001fe40000000f00 */
/*0ff0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fc80000000f00 */
/*1000*/ RET.REL.NODEC R2 0x0 ; /* 0xffffeff002007950 */
/* 0x000fea0003c3ffff */
/*1010*/ BRA 0x1010; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void GetScaleFactorsKernel(float *indata, float *base, float *stdev, float *factors, int nchans, int processed) {
// NOTE: Filterbank file format coming in
//float mean = indata[threadIdx.x];
float mean = 0.0f;
// NOTE: Depending whether I save STD or VAR at the end of every run
// float estd = stdev[threadIdx.x];
float estd = stdev[threadIdx.x] * stdev[threadIdx.x] * (processed - 1.0f);
float oldmean = base[threadIdx.x];
//float estd = 0.0f;
//float oldmean = 0.0;
float val = 0.0f;
float diff = 0.0;
for (int isamp = 0; isamp < 2 * NACCUMULATE; ++isamp) {
val = indata[isamp * nchans + threadIdx.x];
diff = val - oldmean;
mean = oldmean + diff * factors[processed + isamp + 1];
estd += diff * (val - mean);
oldmean = mean;
}
base[threadIdx.x] = mean;
stdev[threadIdx.x] = sqrtf(estd / (float)(processed + 2 * NACCUMULATE - 1.0f));
// stdev[threadIdx.x] = estd;
} | .file "tmpxft_0008521a_00000000-6_GetScaleFactorsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii
.type _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii, @function
_Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21GetScaleFactorsKernelPfS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii, .-_Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii
.globl _Z21GetScaleFactorsKernelPfS_S_S_ii
.type _Z21GetScaleFactorsKernelPfS_S_S_ii, @function
_Z21GetScaleFactorsKernelPfS_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21GetScaleFactorsKernelPfS_S_S_ii, .-_Z21GetScaleFactorsKernelPfS_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21GetScaleFactorsKernelPfS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21GetScaleFactorsKernelPfS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void GetScaleFactorsKernel(float *indata, float *base, float *stdev, float *factors, int nchans, int processed) {
// NOTE: Filterbank file format coming in
//float mean = indata[threadIdx.x];
float mean = 0.0f;
// NOTE: Depending whether I save STD or VAR at the end of every run
// float estd = stdev[threadIdx.x];
float estd = stdev[threadIdx.x] * stdev[threadIdx.x] * (processed - 1.0f);
float oldmean = base[threadIdx.x];
//float estd = 0.0f;
//float oldmean = 0.0;
float val = 0.0f;
float diff = 0.0;
for (int isamp = 0; isamp < 2 * NACCUMULATE; ++isamp) {
val = indata[isamp * nchans + threadIdx.x];
diff = val - oldmean;
mean = oldmean + diff * factors[processed + isamp + 1];
estd += diff * (val - mean);
oldmean = mean;
}
base[threadIdx.x] = mean;
stdev[threadIdx.x] = sqrtf(estd / (float)(processed + 2 * NACCUMULATE - 1.0f));
// stdev[threadIdx.x] = estd;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void GetScaleFactorsKernel(float *indata, float *base, float *stdev, float *factors, int nchans, int processed) {
// NOTE: Filterbank file format coming in
//float mean = indata[threadIdx.x];
float mean = 0.0f;
// NOTE: Depending whether I save STD or VAR at the end of every run
// float estd = stdev[threadIdx.x];
float estd = stdev[threadIdx.x] * stdev[threadIdx.x] * (processed - 1.0f);
float oldmean = base[threadIdx.x];
//float estd = 0.0f;
//float oldmean = 0.0;
float val = 0.0f;
float diff = 0.0;
for (int isamp = 0; isamp < 2 * NACCUMULATE; ++isamp) {
val = indata[isamp * nchans + threadIdx.x];
diff = val - oldmean;
mean = oldmean + diff * factors[processed + isamp + 1];
estd += diff * (val - mean);
oldmean = mean;
}
base[threadIdx.x] = mean;
stdev[threadIdx.x] = sqrtf(estd / (float)(processed + 2 * NACCUMULATE - 1.0f));
// stdev[threadIdx.x] = estd;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void GetScaleFactorsKernel(float *indata, float *base, float *stdev, float *factors, int nchans, int processed) {
// NOTE: Filterbank file format coming in
//float mean = indata[threadIdx.x];
float mean = 0.0f;
// NOTE: Depending whether I save STD or VAR at the end of every run
// float estd = stdev[threadIdx.x];
float estd = stdev[threadIdx.x] * stdev[threadIdx.x] * (processed - 1.0f);
float oldmean = base[threadIdx.x];
//float estd = 0.0f;
//float oldmean = 0.0;
float val = 0.0f;
float diff = 0.0;
for (int isamp = 0; isamp < 2 * NACCUMULATE; ++isamp) {
val = indata[isamp * nchans + threadIdx.x];
diff = val - oldmean;
mean = oldmean + diff * factors[processed + isamp + 1];
estd += diff * (val - mean);
oldmean = mean;
}
base[threadIdx.x] = mean;
stdev[threadIdx.x] = sqrtf(estd / (float)(processed + 2 * NACCUMULATE - 1.0f));
// stdev[threadIdx.x] = estd;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21GetScaleFactorsKernelPfS_S_S_ii
.globl _Z21GetScaleFactorsKernelPfS_S_S_ii
.p2align 8
.type _Z21GetScaleFactorsKernelPfS_S_S_ii,@function
_Z21GetScaleFactorsKernelPfS_S_S_ii:
s_load_b256 s[4:11], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v5, v4, s[8:9]
global_load_b32 v6, v4, s[6:7]
v_add_co_u32 v2, s8, s8, v4
v_cvt_f32_i32_e32 v7, s1
s_ashr_i32 s3, s1, 31
s_mov_b32 s2, s1
v_add_co_u32 v4, s6, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v7, -1.0, v7
s_lshl_b64 s[2:3], s[2:3], 2
v_add_co_ci_u32_e64 v3, null, s9, 0, s8
s_add_u32 s2, s2, s10
s_addc_u32 s3, s3, s11
s_waitcnt vmcnt(1)
v_mul_f32_e32 v8, v5, v5
v_add_co_ci_u32_e64 v5, null, s7, 0, s6
s_add_u32 s6, s2, 4
s_addc_u32 s7, s3, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_f32_e32 v7, v7, v8
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_1:
v_lshlrev_b64 v[8:9], 2, v[0:1]
s_add_u32 s8, s6, s2
s_addc_u32 s9, s7, s3
s_add_u32 s2, s2, 4
s_load_b32 s8, s[8:9], 0x0
s_addc_u32 s3, s3, 0
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_cmpk_eq_i32 s2, 0x800
v_add_nc_u32_e32 v0, s0, v0
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v9, v8, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, s8, v9
v_sub_f32_e32 v8, v8, v6
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v8
s_cbranch_scc0 .LBB0_1
s_add_i32 s0, s1, 0x200
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, s0
v_add_f32_e32 v0, -1.0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v0, v0, v7
v_div_scale_f32 v10, vcc_lo, v7, v0, v7
v_rcp_f32_e32 v8, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v1, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v1, v9, v10
v_fmac_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v9, v10
v_div_fmas_f32 v1, v1, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v1, v0, v7
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, 1, v1
v_add_nc_u32_e32 v7, -1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v8, v1, v0
v_fma_f32 v9, -v7, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v1, v1, v7, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v10
v_cndmask_b32_e64 v1, v1, v8, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v1
v_cndmask_b32_e32 v1, v1, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v0, v1, v0, vcc_lo
global_store_b32 v[4:5], v6, off
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21GetScaleFactorsKernelPfS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21GetScaleFactorsKernelPfS_S_S_ii, .Lfunc_end0-_Z21GetScaleFactorsKernelPfS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21GetScaleFactorsKernelPfS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z21GetScaleFactorsKernelPfS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void GetScaleFactorsKernel(float *indata, float *base, float *stdev, float *factors, int nchans, int processed) {
// NOTE: Filterbank file format coming in
//float mean = indata[threadIdx.x];
float mean = 0.0f;
// NOTE: Depending whether I save STD or VAR at the end of every run
// float estd = stdev[threadIdx.x];
float estd = stdev[threadIdx.x] * stdev[threadIdx.x] * (processed - 1.0f);
float oldmean = base[threadIdx.x];
//float estd = 0.0f;
//float oldmean = 0.0;
float val = 0.0f;
float diff = 0.0;
for (int isamp = 0; isamp < 2 * NACCUMULATE; ++isamp) {
val = indata[isamp * nchans + threadIdx.x];
diff = val - oldmean;
mean = oldmean + diff * factors[processed + isamp + 1];
estd += diff * (val - mean);
oldmean = mean;
}
base[threadIdx.x] = mean;
stdev[threadIdx.x] = sqrtf(estd / (float)(processed + 2 * NACCUMULATE - 1.0f));
// stdev[threadIdx.x] = estd;
} | .text
.file "GetScaleFactorsKernel.hip"
.globl _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii # -- Begin function _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.p2align 4, 0x90
.type _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii,@function
_Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii: # @_Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21GetScaleFactorsKernelPfS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii, .Lfunc_end0-_Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21GetScaleFactorsKernelPfS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21GetScaleFactorsKernelPfS_S_S_ii,@object # @_Z21GetScaleFactorsKernelPfS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z21GetScaleFactorsKernelPfS_S_S_ii
.p2align 3, 0x0
_Z21GetScaleFactorsKernelPfS_S_S_ii:
.quad _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.size _Z21GetScaleFactorsKernelPfS_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21GetScaleFactorsKernelPfS_S_S_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21GetScaleFactorsKernelPfS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21GetScaleFactorsKernelPfS_S_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R28, SR_TID.X ; /* 0x00000000001c7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R14, R28, R3, c[0x0][0x170] ; /* 0x00005c001c0e7625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R14.64] ; /* 0x000000040e007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE.U32 R16, R28, R3, c[0x0][0x168] ; /* 0x00005a001c107625 */
/* 0x000fca00078e0003 */
/*0070*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000162000c1e1900 */
/*0080*/ I2F R2, c[0x0][0x184] ; /* 0x0000610000027b06 */
/* 0x000e620000201400 */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff057624 */
/* 0x000fe200078e00ff */
/*00a0*/ MOV R4, c[0x0][0x184] ; /* 0x0000610000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R12, c[0x0][0x178] ; /* 0x00005e00000c7a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff0d7624 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R8, R28, c[0x0][0x180], RZ ; /* 0x000060001c087a10 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R10, R5.reuse, 0x3, R28.reuse ; /* 0x00000003050a7824 */
/* 0x140fe200078e021c */
/*0100*/ IADD3 R7, R4, 0x1, RZ ; /* 0x0000000104077810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R6, R5, 0x4, R28 ; /* 0x0000000405067824 */
/* 0x000fc400078e021c */
/*0120*/ IMAD R24, R5.reuse, 0x5, R28.reuse ; /* 0x0000000505187824 */
/* 0x140fe400078e021c */
/*0130*/ IMAD R26, R5.reuse, 0x6, R28 ; /* 0x00000006051a7824 */
/* 0x040fe400078e021c */
/*0140*/ FADD R11, R2, -1 ; /* 0xbf800000020b7421 */
/* 0x002fe20000000000 */
/*0150*/ LEA R2, R5, R28, 0x1 ; /* 0x0000001c05027211 */
/* 0x000fe200078e08ff */
/*0160*/ FMUL R0, R0, R0 ; /* 0x0000000000007220 */
/* 0x004fc80000400000 */
/*0170*/ FMUL R11, R0, R11 ; /* 0x0000000b000b7220 */
/* 0x000fe40000400000 */
/*0180*/ IMAD R0, R5, 0x7, R28 ; /* 0x0000000705007824 */
/* 0x001fe400078e021c */
/*0190*/ IMAD.WIDE.U32 R18, R28, R3, c[0x0][0x160] ; /* 0x000058001c127625 */
/* 0x000fc800078e0003 */
/*01a0*/ IMAD.WIDE R20, R7, 0x4, R12 ; /* 0x0000000407147825 */
/* 0x000fe200078e020c */
/*01b0*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x0000a8000c1e1900 */
/*01c0*/ LDG.E R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000ee2000c1e1900 */
/*01d0*/ IMAD.WIDE.U32 R18, R8, R3, c[0x0][0x160] ; /* 0x0000580008127625 */
/* 0x001fca00078e0003 */
/*01e0*/ LDG.E R25, [R18.64] ; /* 0x0000000412197981 */
/* 0x000128000c1e1900 */
/*01f0*/ LDG.E R18, [R20.64+0x8] ; /* 0x0000080414127981 */
/* 0x001f22000c1e1900 */
/*0200*/ FADD R27, R29, -R23 ; /* 0x800000171d1b7221 */
/* 0x024fc80000000000 */
/*0210*/ FFMA R22, R27, R22, R23 ; /* 0x000000161b167223 */
/* 0x008fe40000000017 */
/*0220*/ LDG.E R23, [R20.64+0x4] ; /* 0x0000040414177981 */
/* 0x000ea4000c1e1900 */
/*0230*/ FADD R29, R29, -R22 ; /* 0x800000161d1d7221 */
/* 0x000fc80000000000 */
/*0240*/ FFMA R27, R27, R29, R11 ; /* 0x0000001d1b1b7223 */
/* 0x000fe4000000000b */
/*0250*/ FADD R29, -R22, R25 ; /* 0x00000019161d7221 */
/* 0x010fc80000000100 */
/*0260*/ FFMA R11, R29, R23, R22 ; /* 0x000000171d0b7223 */
/* 0x004fe40000000016 */
/*0270*/ IMAD.WIDE.U32 R22, R2, R3, c[0x0][0x160] ; /* 0x0000580002167625 */
/* 0x000fcc00078e0003 */
/*0280*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea2000c1e1900 */
/*0290*/ FADD R25, R25, -R11 ; /* 0x8000000b19197221 */
/* 0x000fc80000000000 */
/*02a0*/ FFMA R27, R29, R25, R27 ; /* 0x000000191d1b7223 */
/* 0x000fe4000000001b */
/*02b0*/ LDG.E R29, [R20.64+0xc] ; /* 0x00000c04141d7981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FADD R25, -R11, R22 ; /* 0x000000160b197221 */
/* 0x004fc80000000100 */
/*02d0*/ FFMA R11, R25, R18, R11 ; /* 0x00000012190b7223 */
/* 0x000fe4000000000b */
/*02e0*/ IMAD.WIDE.U32 R18, R10, R3, c[0x0][0x160] ; /* 0x000058000a127625 */
/* 0x000fcc00078e0003 */
/*02f0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1900 */
/*0300*/ FADD R22, R22, -R11 ; /* 0x8000000b16167221 */
/* 0x000fc80000000000 */
/*0310*/ FFMA R27, R25, R22, R27 ; /* 0x00000016191b7223 */
/* 0x000fe4000000001b */
/*0320*/ IMAD.WIDE.U32 R22, R6, R3, c[0x0][0x160] ; /* 0x0000580006167625 */
/* 0x000fcc00078e0003 */
/*0330*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f22000c1e1900 */
/*0340*/ FADD R25, -R11, R18 ; /* 0x000000120b197221 */
/* 0x004fc80000000100 */
/*0350*/ FFMA R11, R25, R29, R11 ; /* 0x0000001d190b7223 */
/* 0x008fe4000000000b */
/*0360*/ LDG.E R29, [R20.64+0x10] ; /* 0x00001004141d7981 */
/* 0x000ea4000c1e1900 */
/*0370*/ FADD R18, R18, -R11 ; /* 0x8000000b12127221 */
/* 0x000fc80000000000 */
/*0380*/ FFMA R27, R25, R18, R27 ; /* 0x00000012191b7223 */
/* 0x000fe4000000001b */
/*0390*/ IMAD.WIDE.U32 R18, R24, R3, c[0x0][0x160] ; /* 0x0000580018127625 */
/* 0x000fc800078e0003 */
/*03a0*/ FADD R25, -R11, R22 ; /* 0x000000160b197221 */
/* 0x010fe40000000100 */
/*03b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1900 */
/*03c0*/ FFMA R11, R25, R29, R11 ; /* 0x0000001d190b7223 */
/* 0x004fe4000000000b */
/*03d0*/ LDG.E R29, [R20.64+0x14] ; /* 0x00001404141d7981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ FADD R22, R22, -R11 ; /* 0x8000000b16167221 */
/* 0x000fc80000000000 */
/*03f0*/ FFMA R27, R25, R22, R27 ; /* 0x00000016191b7223 */
/* 0x000fe4000000001b */
/*0400*/ FADD R25, -R11, R18 ; /* 0x000000120b197221 */
/* 0x008fe40000000100 */
/*0410*/ IMAD.WIDE.U32 R22, R26, R3, c[0x0][0x160] ; /* 0x000058001a167625 */
/* 0x000fcc00078e0003 */
/*0420*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e8000c1e1900 */
/*0430*/ LDG.E R23, [R20.64+0x1c] ; /* 0x00001c0414177981 */
/* 0x001f22000c1e1900 */
/*0440*/ FFMA R11, R25, R29, R11 ; /* 0x0000001d190b7223 */
/* 0x004fc6000000000b */
/*0450*/ LDG.E R29, [R20.64+0x18] ; /* 0x00001804141d7981 */
/* 0x000ea2000c1e1900 */
/*0460*/ FADD R18, R18, -R11 ; /* 0x8000000b12127221 */
/* 0x000fc80000000000 */
/*0470*/ FFMA R27, R25, R18, R27 ; /* 0x00000012191b7223 */
/* 0x000fe4000000001b */
/*0480*/ IMAD.WIDE.U32 R18, R0, R3, c[0x0][0x160] ; /* 0x0000580000127625 */
/* 0x000fcc00078e0003 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1900 */
/*04a0*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ FADD R25, -R11, R22 ; /* 0x000000160b197221 */
/* 0x008fc60000000100 */
/*04c0*/ ISETP.NE.AND P0, PT, R9, 0x200, PT ; /* 0x000002000900780c */
/* 0x000fe40003f05270 */
/*04d0*/ IADD3 R12, P1, R12, 0x20, RZ ; /* 0x000000200c0c7810 */
/* 0x000fe20007f3e0ff */
/*04e0*/ IMAD R10, R5.reuse, 0x8, R10 ; /* 0x00000008050a7824 */
/* 0x040fe200078e020a */
/*04f0*/ LEA R8, R5.reuse, R8, 0x3 ; /* 0x0000000805087211 */
/* 0x040fe200078e18ff */
/*0500*/ IMAD R26, R5.reuse, 0x8, R26 ; /* 0x00000008051a7824 */
/* 0x040fe200078e021a */
/*0510*/ LEA R2, R5.reuse, R2, 0x3 ; /* 0x0000000205027211 */
/* 0x040fe200078e18ff */
/*0520*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0530*/ LEA R6, R5.reuse, R6, 0x3 ; /* 0x0000000605067211 */
/* 0x040fe400078e18ff */
/*0540*/ LEA R24, R5, R24, 0x3 ; /* 0x0000001805187211 */
/* 0x000fc400078e18ff */
/*0550*/ LEA R28, R5.reuse, R28, 0x3 ; /* 0x0000001c051c7211 */
/* 0x040fe400078e18ff */
/*0560*/ LEA R0, R5, R0, 0x3 ; /* 0x0000000005007211 */
/* 0x000fe200078e18ff */
/*0570*/ FFMA R29, R25, R29, R11 ; /* 0x0000001d191d7223 */
/* 0x004fc8000000000b */
/*0580*/ FADD R22, R22, -R29 ; /* 0x8000001d16167221 */
/* 0x000fe40000000000 */
/*0590*/ FADD R11, -R29, R18 ; /* 0x000000121d0b7221 */
/* 0x010fc80000000100 */
/*05a0*/ FFMA R23, R11, R23, R29 ; /* 0x000000170b177223 */
/* 0x000fe4000000001d */
/*05b0*/ FFMA R22, R25, R22, R27 ; /* 0x0000001619167223 */
/* 0x000fe4000000001b */
/*05c0*/ FADD R25, R18, -R23 ; /* 0x8000001712197221 */
/* 0x000fc80000000000 */
/*05d0*/ FFMA R11, R11, R25, R22 ; /* 0x000000190b0b7223 */
/* 0x000fe20000000016 */
/*05e0*/ @P0 BRA 0x190 ; /* 0xfffffba000000947 */
/* 0x000fea000383ffff */
/*05f0*/ IADD3 R4, R4, 0x200, RZ ; /* 0x0000020004047810 */
/* 0x000fe20007ffe0ff */
/*0600*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e2000c101904 */
/*0610*/ BSSY B0, 0x700 ; /* 0x000000e000007945 */
/* 0x000fe80003800000 */
/*0620*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e640000201400 */
/*0630*/ FADD R2, R4, -1 ; /* 0xbf80000004027421 */
/* 0x002fcc0000000000 */
/*0640*/ MUFU.RCP R3, R2 ; /* 0x0000000200037308 */
/* 0x000e700000001000 */
/*0650*/ FCHK P0, R11, R2 ; /* 0x000000020b007302 */
/* 0x000ea20000000000 */
/*0660*/ FFMA R0, -R2, R3, 1 ; /* 0x3f80000002007423 */
/* 0x002fc80000000103 */
/*0670*/ FFMA R0, R3, R0, R3 ; /* 0x0000000003007223 */
/* 0x000fc80000000003 */
/*0680*/ FFMA R3, R11, R0, RZ ; /* 0x000000000b037223 */
/* 0x000fc800000000ff */
/*0690*/ FFMA R5, -R2, R3, R11 ; /* 0x0000000302057223 */
/* 0x000fc8000000010b */
/*06a0*/ FFMA R0, R0, R5, R3 ; /* 0x0000000500007223 */
/* 0x000fe20000000003 */
/*06b0*/ @!P0 BRA 0x6f0 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*06c0*/ MOV R0, 0x6e0 ; /* 0x000006e000007802 */
/* 0x001fe40000000f00 */
/*06d0*/ CALL.REL.NOINC 0x970 ; /* 0x0000029000007944 */
/* 0x000fea0003c00000 */
/*06e0*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0700*/ IADD3 R2, R0, -0xd000000, RZ ; /* 0xf300000000027810 */
/* 0x000fe20007ffe0ff */
/*0710*/ MUFU.RSQ R5, R0 ; /* 0x0000000000057308 */
/* 0x0000620000001400 */
/*0720*/ BSSY B0, 0x7f0 ; /* 0x000000c000007945 */
/* 0x000fe40003800000 */
/*0730*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*0740*/ @!P0 BRA 0x7a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0750*/ MOV R6, R0 ; /* 0x0000000000067202 */
/* 0x003fe40000000f00 */
/*0760*/ MOV R7, 0x780 ; /* 0x0000078000077802 */
/* 0x000fe40000000f00 */
/*0770*/ CALL.REL.NOINC 0x810 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0780*/ IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0000 */
/*0790*/ BRA 0x7e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07a0*/ FMUL.FTZ R3, R5.reuse, R0 ; /* 0x0000000005037220 */
/* 0x043fe40000410000 */
/*07b0*/ FMUL.FTZ R2, R5, 0.5 ; /* 0x3f00000005027820 */
/* 0x000fe40000410000 */
/*07c0*/ FFMA R0, -R3, R3, R0 ; /* 0x0000000303007223 */
/* 0x000fc80000000100 */
/*07d0*/ FFMA R3, R0, R2, R3 ; /* 0x0000000200037223 */
/* 0x000fe40000000003 */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ STG.E [R14.64], R3 ; /* 0x000000030e007986 */
/* 0x000fe2000c101904 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0820*/ @!P0 MOV R0, R6 ; /* 0x0000000600008202 */
/* 0x000fe20000000f00 */
/*0830*/ @!P0 BRA 0x940 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0840*/ FSETP.GEU.FTZ.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x000fda0003f1e000 */
/*0850*/ @!P0 MOV R0, 0x7fffffff ; /* 0x7fffffff00008802 */
/* 0x000fe20000000f00 */
/*0860*/ @!P0 BRA 0x940 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0870*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1c200 */
/*0880*/ @P0 FADD.FTZ R0, R6, 1 ; /* 0x3f80000006000421 */
/* 0x000fe20000010000 */
/*0890*/ @P0 BRA 0x940 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*08a0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fda0003f1d200 */
/*08b0*/ @P0 FFMA R2, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006020823 */
/* 0x000fc800000000ff */
/*08c0*/ @P0 MUFU.RSQ R3, R2 ; /* 0x0000000200030308 */
/* 0x000e240000001400 */
/*08d0*/ @P0 FMUL.FTZ R5, R2, R3 ; /* 0x0000000302050220 */
/* 0x001fe40000410000 */
/*08e0*/ @P0 FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003030820 */
/* 0x000fe40000410000 */
/*08f0*/ @P0 FADD.FTZ R0, -R5, -RZ ; /* 0x800000ff05000221 */
/* 0x000fc80000010100 */
/*0900*/ @P0 FFMA R4, R5, R0, R2 ; /* 0x0000000005040223 */
/* 0x000fe40000000002 */
/*0910*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff008224 */
/* 0x000fe400078e0006 */
/*0920*/ @P0 FFMA R3, R4, R3, R5 ; /* 0x0000000304030223 */
/* 0x000fc80000000005 */
/*0930*/ @P0 FMUL.FTZ R0, R3, 2.3283064365386962891e-10 ; /* 0x2f80000003000820 */
/* 0x000fe40000410000 */
/*0940*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0950*/ MOV R2, R7 ; /* 0x0000000700027202 */
/* 0x000fca0000000f00 */
/*0960*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff69002007950 */
/* 0x000fea0003c3ffff */
/*0970*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fe20000011602 */
/*0980*/ BSSY B1, 0xfd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0990*/ SHF.R.U32.HI R3, RZ, 0x17, R11.reuse ; /* 0x00000017ff037819 */
/* 0x100fe4000001160b */
/*09a0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*09b0*/ LOP3.LUT R9, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03097812 */
/* 0x000fe200078ec0ff */
/*09c0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000b */
/*09d0*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R8, R9, -0x1, RZ ; /* 0xffffffff09087810 */
/* 0x000fc40007ffe0ff */
/*09f0*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fe40003f04070 */
/*0a00*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*0a10*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*0a20*/ @!P0 MOV R5, RZ ; /* 0x000000ff00058202 */
/* 0x000fe20000000f00 */
/*0a30*/ @!P0 BRA 0xbb0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a40*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fe40003f1c200 */
/*0a50*/ FSETP.GTU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f3c200 */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0a70*/ @P0 BRA 0xfb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0a80*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R3, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c803 */
/*0a90*/ @!P0 BRA 0xf90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ FSETP.NEU.FTZ.AND P2, PT, |R11|.reuse, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x040fe40003f5d200 */
/*0ab0*/ FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f3d200 */
/*0ac0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fd60003f1d200 */
/*0ad0*/ @!P1 BRA !P2, 0xf90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0ae0*/ LOP3.LUT P2, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fc8000784c0ff */
/*0af0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0b00*/ @P1 BRA 0xf70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0b10*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0b20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0b30*/ @P0 BRA 0xf40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0b40*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0b50*/ ISETP.GE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f26270 */
/*0b60*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe200078e00ff */
/*0b70*/ @!P0 MOV R5, 0xffffffc0 ; /* 0xffffffc000058802 */
/* 0x000fe20000000f00 */
/*0b80*/ @!P0 FFMA R3, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b038823 */
/* 0x000fe400000000ff */
/*0b90*/ @!P1 FFMA R6, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002069823 */
/* 0x000fe200000000ff */
/*0ba0*/ @!P1 IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005059810 */
/* 0x000fe40007ffe0ff */
/*0bb0*/ LEA R7, R4, 0xc0800000, 0x17 ; /* 0xc080000004077811 */
/* 0x000fe200078eb8ff */
/*0bc0*/ BSSY B2, 0xf30 ; /* 0x0000036000027945 */
/* 0x000fe60003800000 */
/*0bd0*/ IADD3 R7, -R7, R6, RZ ; /* 0x0000000607077210 */
/* 0x000fe40007ffe1ff */
/*0be0*/ IADD3 R6, R9, -0x7f, RZ ; /* 0xffffff8109067810 */
/* 0x000fc40007ffe0ff */
/*0bf0*/ MUFU.RCP R2, R7 ; /* 0x0000000700027308 */
/* 0x000e220000001000 */
/*0c00*/ FADD.FTZ R8, -R7, -RZ ; /* 0x800000ff07087221 */
/* 0x000fe20000010100 */
/*0c10*/ IADD3 R4, R6.reuse, 0x7f, -R4 ; /* 0x0000007f06047810 */
/* 0x040fe20007ffe804 */
/*0c20*/ IMAD R3, R6, -0x800000, R3 ; /* 0xff80000006037824 */
/* 0x000fc800078e0203 */
/*0c30*/ IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104047824 */
/* 0x000fe400078e0205 */
/*0c40*/ FFMA R9, R2, R8, 1 ; /* 0x3f80000002097423 */
/* 0x001fc80000000008 */
/*0c50*/ FFMA R10, R2, R9, R2 ; /* 0x00000009020a7223 */
/* 0x000fc80000000002 */
/*0c60*/ FFMA R2, R3, R10, RZ ; /* 0x0000000a03027223 */
/* 0x000fc800000000ff */
/*0c70*/ FFMA R9, R8, R2, R3 ; /* 0x0000000208097223 */
/* 0x000fc80000000003 */
/*0c80*/ FFMA R9, R10, R9, R2 ; /* 0x000000090a097223 */
/* 0x000fc80000000002 */
/*0c90*/ FFMA R8, R8, R9, R3 ; /* 0x0000000908087223 */
/* 0x000fc80000000003 */
/*0ca0*/ FFMA R2, R10, R8, R9 ; /* 0x000000080a027223 */
/* 0x000fca0000000009 */
/*0cb0*/ SHF.R.U32.HI R3, RZ, 0x17, R2 ; /* 0x00000017ff037819 */
/* 0x000fc80000011602 */
/*0cc0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fc800078ec0ff */
/*0cd0*/ IADD3 R7, R3, R4, RZ ; /* 0x0000000403077210 */
/* 0x000fc80007ffe0ff */
/*0ce0*/ IADD3 R3, R7, -0x1, RZ ; /* 0xffffffff07037810 */
/* 0x000fc80007ffe0ff */
/*0cf0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*0d00*/ @!P0 BRA 0xf10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d10*/ ISETP.GT.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f04270 */
/*0d20*/ @P0 BRA 0xee0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0d30*/ ISETP.GE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f06270 */
/*0d40*/ @P0 BRA 0xf20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0d50*/ ISETP.GE.AND P0, PT, R7, -0x18, PT ; /* 0xffffffe80700780c */
/* 0x000fe40003f06270 */
/*0d60*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fd600078ec0ff */
/*0d70*/ @!P0 BRA 0xf20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0d80*/ FFMA.RZ R3, R10.reuse, R8.reuse, R9.reuse ; /* 0x000000080a037223 */
/* 0x1c0fe2000000c009 */
/*0d90*/ IADD3 R6, R7.reuse, 0x20, RZ ; /* 0x0000002007067810 */
/* 0x040fe20007ffe0ff */
/*0da0*/ FFMA.RM R4, R10.reuse, R8.reuse, R9.reuse ; /* 0x000000080a047223 */
/* 0x1c0fe20000004009 */
/*0db0*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f45270 */
/*0dc0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*0dd0*/ FFMA.RP R3, R10, R8, R9 ; /* 0x000000080a037223 */
/* 0x000fe20000008009 */
/*0de0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*0df0*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe400078efcff */
/*0e00*/ IADD3 R7, -R7, RZ, RZ ; /* 0x000000ff07077210 */
/* 0x000fc40007ffe1ff */
/*0e10*/ SHF.L.U32 R6, R5, R6, RZ ; /* 0x0000000605067219 */
/* 0x000fe400000006ff */
/*0e20*/ FSETP.NEU.FTZ.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x000fe40003f1d000 */
/*0e30*/ SEL R4, R7, RZ, P2 ; /* 0x000000ff07047207 */
/* 0x000fe40001000000 */
/*0e40*/ ISETP.NE.AND P1, PT, R6, RZ, P1 ; /* 0x000000ff0600720c */
/* 0x000fe40000f25270 */
/*0e50*/ SHF.R.U32.HI R4, RZ, R4, R5 ; /* 0x00000004ff047219 */
/* 0x000fe40000011605 */
/*0e60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0e70*/ SHF.R.U32.HI R6, RZ, 0x1, R4 ; /* 0x00000001ff067819 */
/* 0x000fe40000011604 */
/*0e80*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*0e90*/ LOP3.LUT R3, R3, 0x1, R6, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef806 */
/*0ea0*/ LOP3.LUT R3, R3, R4, RZ, 0xc0, !PT ; /* 0x0000000403037212 */
/* 0x000fc800078ec0ff */
/*0eb0*/ IADD3 R3, R6, R3, RZ ; /* 0x0000000306037210 */
/* 0x000fc80007ffe0ff */
/*0ec0*/ LOP3.LUT R2, R3, R2, RZ, 0xfc, !PT ; /* 0x0000000203027212 */
/* 0x000fe200078efcff */
/*0ed0*/ BRA 0xf20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ee0*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fc800078ec0ff */
/*0ef0*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0f00*/ BRA 0xf20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0f10*/ IMAD R2, R4, 0x800000, R2 ; /* 0x0080000004027824 */
/* 0x000fe400078e0202 */
/*0f20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0f30*/ BRA 0xfc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0f40*/ LOP3.LUT R2, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006027812 */
/* 0x000fc800078e4803 */
/*0f50*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0f60*/ BRA 0xfc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0f70*/ LOP3.LUT R2, R6, 0x80000000, R3, 0x48, !PT ; /* 0x8000000006027812 */
/* 0x000fe200078e4803 */
/*0f80*/ BRA 0xfc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0f90*/ MUFU.RSQ R2, -QNAN ; /* 0xffc0000000027908 */
/* 0x000e220000001400 */
/*0fa0*/ BRA 0xfc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ FADD.FTZ R2, R11, R2 ; /* 0x000000020b027221 */
/* 0x000fe40000010000 */
/*0fc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0fd0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0fe0*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x001fe40000000f00 */
/*0ff0*/ MOV R2, R0 ; /* 0x0000000000027202 */
/* 0x000fc80000000f00 */
/*1000*/ RET.REL.NODEC R2 0x0 ; /* 0xffffeff002007950 */
/* 0x000fea0003c3ffff */
/*1010*/ BRA 0x1010; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21GetScaleFactorsKernelPfS_S_S_ii
.globl _Z21GetScaleFactorsKernelPfS_S_S_ii
.p2align 8
.type _Z21GetScaleFactorsKernelPfS_S_S_ii,@function
_Z21GetScaleFactorsKernelPfS_S_S_ii:
s_load_b256 s[4:11], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 2, v0
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v5, v4, s[8:9]
global_load_b32 v6, v4, s[6:7]
v_add_co_u32 v2, s8, s8, v4
v_cvt_f32_i32_e32 v7, s1
s_ashr_i32 s3, s1, 31
s_mov_b32 s2, s1
v_add_co_u32 v4, s6, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_f32_e32 v7, -1.0, v7
s_lshl_b64 s[2:3], s[2:3], 2
v_add_co_ci_u32_e64 v3, null, s9, 0, s8
s_add_u32 s2, s2, s10
s_addc_u32 s3, s3, s11
s_waitcnt vmcnt(1)
v_mul_f32_e32 v8, v5, v5
v_add_co_ci_u32_e64 v5, null, s7, 0, s6
s_add_u32 s6, s2, 4
s_addc_u32 s7, s3, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_f32_e32 v7, v7, v8
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_1:
v_lshlrev_b64 v[8:9], 2, v[0:1]
s_add_u32 s8, s6, s2
s_addc_u32 s9, s7, s3
s_add_u32 s2, s2, 4
s_load_b32 s8, s[8:9], 0x0
s_addc_u32 s3, s3, 0
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_cmpk_eq_i32 s2, 0x800
v_add_nc_u32_e32 v0, s0, v0
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v9, v8, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, s8, v9
v_sub_f32_e32 v8, v8, v6
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v8
s_cbranch_scc0 .LBB0_1
s_add_i32 s0, s1, 0x200
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, s0
v_add_f32_e32 v0, -1.0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v1, null, v0, v0, v7
v_div_scale_f32 v10, vcc_lo, v7, v0, v7
v_rcp_f32_e32 v8, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v1, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v1, v9, v10
v_fmac_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v9, v10
v_div_fmas_f32 v1, v1, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v0, v1, v0, v7
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, 1, v1
v_add_nc_u32_e32 v7, -1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v8, v1, v0
v_fma_f32 v9, -v7, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v1, v1, v7, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v10
v_cndmask_b32_e64 v1, v1, v8, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v1
v_cndmask_b32_e32 v1, v1, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e32 v0, v1, v0, vcc_lo
global_store_b32 v[4:5], v6, off
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21GetScaleFactorsKernelPfS_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21GetScaleFactorsKernelPfS_S_S_ii, .Lfunc_end0-_Z21GetScaleFactorsKernelPfS_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21GetScaleFactorsKernelPfS_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z21GetScaleFactorsKernelPfS_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008521a_00000000-6_GetScaleFactorsKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii
.type _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii, @function
_Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21GetScaleFactorsKernelPfS_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii, .-_Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii
.globl _Z21GetScaleFactorsKernelPfS_S_S_ii
.type _Z21GetScaleFactorsKernelPfS_S_S_ii, @function
_Z21GetScaleFactorsKernelPfS_S_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z21GetScaleFactorsKernelPfS_S_S_iiPfS_S_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21GetScaleFactorsKernelPfS_S_S_ii, .-_Z21GetScaleFactorsKernelPfS_S_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21GetScaleFactorsKernelPfS_S_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21GetScaleFactorsKernelPfS_S_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "GetScaleFactorsKernel.hip"
.globl _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii # -- Begin function _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.p2align 4, 0x90
.type _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii,@function
_Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii: # @_Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21GetScaleFactorsKernelPfS_S_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii, .Lfunc_end0-_Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21GetScaleFactorsKernelPfS_S_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21GetScaleFactorsKernelPfS_S_S_ii,@object # @_Z21GetScaleFactorsKernelPfS_S_S_ii
.section .rodata,"a",@progbits
.globl _Z21GetScaleFactorsKernelPfS_S_S_ii
.p2align 3, 0x0
_Z21GetScaleFactorsKernelPfS_S_S_ii:
.quad _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.size _Z21GetScaleFactorsKernelPfS_S_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21GetScaleFactorsKernelPfS_S_S_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__GetScaleFactorsKernelPfS_S_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21GetScaleFactorsKernelPfS_S_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void detectChanges(float* a, float* b, float* result, int size, float value)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(threadId < size)
{
if(a[threadId] > b[threadId])
{
result[threadId] = value;
}
else if(a[threadId] <b[threadId])
{
result[threadId] = -value;
}
else
{
result[threadId] = 0;
}
}
} | code for sm_80
Function : _Z13detectChangesPfS_S_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ FSETP.GT.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x004fda0003f04000 */
/*0100*/ @P0 BRA 0x170 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0110*/ FSETP.GEU.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x000fda0003f0e000 */
/*0120*/ @P0 STG.E [R6.64], RZ ; /* 0x000000ff06000986 */
/* 0x0001e2000c101904 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ FADD R3, -RZ, -c[0x0][0x17c] ; /* 0x80005f00ff037621 */
/* 0x000fca0000000100 */
/*0150*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*0180*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void detectChanges(float* a, float* b, float* result, int size, float value)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(threadId < size)
{
if(a[threadId] > b[threadId])
{
result[threadId] = value;
}
else if(a[threadId] <b[threadId])
{
result[threadId] = -value;
}
else
{
result[threadId] = 0;
}
}
} | .file "tmpxft_000b231a_00000000-6_detectChanges.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if
.type _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if, @function
_Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13detectChangesPfS_S_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if, .-_Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if
.globl _Z13detectChangesPfS_S_if
.type _Z13detectChangesPfS_S_if, @function
_Z13detectChangesPfS_S_if:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13detectChangesPfS_S_if, .-_Z13detectChangesPfS_S_if
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13detectChangesPfS_S_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13detectChangesPfS_S_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void detectChanges(float* a, float* b, float* result, int size, float value)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(threadId < size)
{
if(a[threadId] > b[threadId])
{
result[threadId] = value;
}
else if(a[threadId] <b[threadId])
{
result[threadId] = -value;
}
else
{
result[threadId] = 0;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void detectChanges(float* a, float* b, float* result, int size, float value)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(threadId < size)
{
if(a[threadId] > b[threadId])
{
result[threadId] = value;
}
else if(a[threadId] <b[threadId])
{
result[threadId] = -value;
}
else
{
result[threadId] = 0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void detectChanges(float* a, float* b, float* result, int size, float value)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(threadId < size)
{
if(a[threadId] > b[threadId])
{
result[threadId] = value;
}
else if(a[threadId] <b[threadId])
{
result[threadId] = -value;
}
else
{
result[threadId] = 0;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13detectChangesPfS_S_if
.globl _Z13detectChangesPfS_S_if
.p2align 8
.type _Z13detectChangesPfS_S_if,@function
_Z13detectChangesPfS_S_if:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x1c
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[2:3], off
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v2, s2
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v3, v4
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_lt_f32_e32 v3, v4
s_xor_b32 s2, s2, 0x80000000
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13detectChangesPfS_S_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13detectChangesPfS_S_if, .Lfunc_end0-_Z13detectChangesPfS_S_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13detectChangesPfS_S_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13detectChangesPfS_S_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void detectChanges(float* a, float* b, float* result, int size, float value)
{
int threadId = blockDim.x*blockIdx.y*gridDim.x
+ blockDim.x*blockIdx.x
+ threadIdx.x;
if(threadId < size)
{
if(a[threadId] > b[threadId])
{
result[threadId] = value;
}
else if(a[threadId] <b[threadId])
{
result[threadId] = -value;
}
else
{
result[threadId] = 0;
}
}
} | .text
.file "detectChanges.hip"
.globl _Z28__device_stub__detectChangesPfS_S_if # -- Begin function _Z28__device_stub__detectChangesPfS_S_if
.p2align 4, 0x90
.type _Z28__device_stub__detectChangesPfS_S_if,@function
_Z28__device_stub__detectChangesPfS_S_if: # @_Z28__device_stub__detectChangesPfS_S_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13detectChangesPfS_S_if, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__detectChangesPfS_S_if, .Lfunc_end0-_Z28__device_stub__detectChangesPfS_S_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13detectChangesPfS_S_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13detectChangesPfS_S_if,@object # @_Z13detectChangesPfS_S_if
.section .rodata,"a",@progbits
.globl _Z13detectChangesPfS_S_if
.p2align 3, 0x0
_Z13detectChangesPfS_S_if:
.quad _Z28__device_stub__detectChangesPfS_S_if
.size _Z13detectChangesPfS_S_if, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13detectChangesPfS_S_if"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__detectChangesPfS_S_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13detectChangesPfS_S_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13detectChangesPfS_S_if
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00a0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00b0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00f0*/ FSETP.GT.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x004fda0003f04000 */
/*0100*/ @P0 BRA 0x170 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0110*/ FSETP.GEU.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x000fda0003f0e000 */
/*0120*/ @P0 STG.E [R6.64], RZ ; /* 0x000000ff06000986 */
/* 0x0001e2000c101904 */
/*0130*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0140*/ FADD R3, -RZ, -c[0x0][0x17c] ; /* 0x80005f00ff037621 */
/* 0x000fca0000000100 */
/*0150*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fca0000000f00 */
/*0180*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13detectChangesPfS_S_if
.globl _Z13detectChangesPfS_S_if
.p2align 8
.type _Z13detectChangesPfS_S_if,@function
_Z13detectChangesPfS_S_if:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x1c
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v3, v[2:3], off
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v2, s2
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e32 v3, v4
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_lt_f32_e32 v3, v4
s_xor_b32 s2, s2, 0x80000000
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13detectChangesPfS_S_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13detectChangesPfS_S_if, .Lfunc_end0-_Z13detectChangesPfS_S_if
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13detectChangesPfS_S_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13detectChangesPfS_S_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b231a_00000000-6_detectChanges.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if
.type _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if, @function
_Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13detectChangesPfS_S_if(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if, .-_Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if
.globl _Z13detectChangesPfS_S_if
.type _Z13detectChangesPfS_S_if, @function
_Z13detectChangesPfS_S_if:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13detectChangesPfS_S_ifPfS_S_if
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13detectChangesPfS_S_if, .-_Z13detectChangesPfS_S_if
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13detectChangesPfS_S_if"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13detectChangesPfS_S_if(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "detectChanges.hip"
.globl _Z28__device_stub__detectChangesPfS_S_if # -- Begin function _Z28__device_stub__detectChangesPfS_S_if
.p2align 4, 0x90
.type _Z28__device_stub__detectChangesPfS_S_if,@function
_Z28__device_stub__detectChangesPfS_S_if: # @_Z28__device_stub__detectChangesPfS_S_if
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movss %xmm0, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13detectChangesPfS_S_if, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__detectChangesPfS_S_if, .Lfunc_end0-_Z28__device_stub__detectChangesPfS_S_if
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13detectChangesPfS_S_if, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13detectChangesPfS_S_if,@object # @_Z13detectChangesPfS_S_if
.section .rodata,"a",@progbits
.globl _Z13detectChangesPfS_S_if
.p2align 3, 0x0
_Z13detectChangesPfS_S_if:
.quad _Z28__device_stub__detectChangesPfS_S_if
.size _Z13detectChangesPfS_S_if, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13detectChangesPfS_S_if"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__detectChangesPfS_S_if
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13detectChangesPfS_S_if
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
/*
* Code to simulate a GPU workload for lab assignment in [A2] Task Mapping on Soft Heterogeneous Systems.
* Workload consists of a the Black-Scholes kernel taken from NVIDIA SDK 10.1
*
* Computation is done on the GPU when the user selects a core attached to a GPU; otherwise the code is run on
* the CPU. GPU version of the code is expected to run faster.
*
* @author: Apan Qasem <apan@txstate.edu>
* @date: 04/02/20
*
* @update: 03/12/21
*/
#include<cstdio>
#include<sys/time.h>
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
static double CND(double d)
{
const double A1 = 0.31938153;
const double A2 = -0.356563782;
const double A3 = 1.781477937;
const double A4 = -1.821255978;
const double A5 = 1.330274429;
const double RSQRT2PI = 0.39894228040143267793994605993438;
double
K = 1.0 / (1.0 + 0.2316419 * fabs(d));
double
cnd = RSQRT2PI * exp(- 0.5 * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0 - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
static void BlackScholesBodyCPU(
float &callResult,
float &putResult,
float Sf, //Stock price
float Xf, //Option strike
float Tf, //Option years
float Rf, //Riskless rate
float Vf //Volatility rate
)
{
double S = Sf, X = Xf, T = Tf, R = Rf, V = Vf;
double sqrtT = sqrt(T);
double d1 = (log(S / X) + (R + 0.5 * V * V) * T) / (V * sqrtT);
double d2 = d1 - V * sqrtT;
double CNDD1 = CND(d1);
double CNDD2 = CND(d2);
//Calculate Call and Put simultaneously
double expRT = exp(- R * T);
callResult = (float)(S * CNDD1 - X * expRT * CNDD2);
putResult = (float)(X * expRT * (1.0 - CNDD2) - S * (1.0 - CNDD1));
}
////////////////////////////////////////////////////////////////////////////////
// Process an array of optN options
////////////////////////////////////////////////////////////////////////////////
void BlackScholesCPU(
float *h_CallResult,
float *h_PutResult,
float *h_StockPrice,
float *h_OptionStrike,
float *h_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
for (int opt = 0; opt < optN; opt++)
BlackScholesBodyCPU(
h_CallResult[opt],
h_PutResult[opt],
h_StockPrice[opt],
h_OptionStrike[opt],
h_OptionYears[opt],
Riskfree,
Volatility
);
}
// extern "C" void BlackScholesCPU(
// float *h_CallResult,
// float *h_PutResult,
// float *h_StockPrice,
// float *h_OptionStrike,
// float *h_OptionYears,
// float Riskfree,
// float Volatility,
// int optN
// );
////////////////////////////////////////////////////////////////////////////////
// Process an array of OptN options on GPU
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
__device__ inline float cndGPU(float d)
{
const float A1 = 0.31938153f;
const float A2 = -0.356563782f;
const float A3 = 1.781477937f;
const float A4 = -1.821255978f;
const float A5 = 1.330274429f;
const float RSQRT2PI = 0.39894228040143267793994605993438f;
float
K = 1.0f / (1.0f + 0.2316419f * fabsf(d));
float
cnd = RSQRT2PI * __expf(- 0.5f * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0f - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
__device__ inline void BlackScholesBodyGPU(
float &CallResult,
float &PutResult,
float S, //Stock price
float X, //Option strike
float T, //Option years
float R, //Riskless rate
float V //Volatility rate
)
{
float sqrtT, expRT;
float d1, d2, CNDD1, CNDD2;
sqrtT = sqrtf(T);
d1 = (__logf(S / X) + (R + 0.5f * V * V) * T) / (V * sqrtT);
d2 = d1 - V * sqrtT;
CNDD1 = cndGPU(d1);
CNDD2 = cndGPU(d2);
//Calculate Call and Put simultaneously
expRT = __expf(- R * T);
CallResult = S * CNDD1 - X * expRT * CNDD2;
PutResult = X * expRT * (1.0f - CNDD2) - S * (1.0f - CNDD1);
}
////////////////////////////////////////////////////////////////////////////////
//Process an array of optN options on GPU
////////////////////////////////////////////////////////////////////////////////
__global__ void BlackScholesGPU(
float *d_CallResult,
float *d_PutResult,
float *d_StockPrice,
float *d_OptionStrike,
float *d_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
////Thread index
//const int tid = blockDim.x * blockIdx.x + threadIdx.x;
////Total number of threads in execution grid
//const int THREAD_N = blockDim.x * gridDim.x;
const int opt = blockDim.x * blockIdx.x + threadIdx.x;
//No matter how small is execution grid or how large OptN is,
//exactly OptN indices will be processed with perfect memory coalescing
//for (int opt = tid; opt < optN; opt += THREAD_N)
if (opt < optN)
BlackScholesBodyGPU(
d_CallResult[opt],
d_PutResult[opt],
d_StockPrice[opt],
d_OptionStrike[opt],
d_OptionYears[opt],
Riskfree,
Volatility
);
}
////////////////////////////////////////////////////////////////////////////////
// Helper function, returning uniformly distributed
// random float in [low, high] range
////////////////////////////////////////////////////////////////////////////////
float RandFloat(float low, float high)
{
float t = (float)rand() / (float)RAND_MAX;
return (1.0f - t) * low + t * high;
}
////////////////////////////////////////////////////////////////////////////////
// Data configuration
////////////////////////////////////////////////////////////////////////////////
const int NUM_ITERATIONS = 512;
const float RISKFREE = 0.02f;
const float VOLATILITY = 0.30f;
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
////////////////////////////////////////////////////////////////////////////////
// Main program
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
if (argc < 3) {
fprintf(stderr, "usage: ./blackscholes options GPU\n");
exit(0);
}
unsigned options = atoi(argv[1]);
int options_size = options * sizeof(float);
unsigned gpu = atoi(argv[2]);
float
*h_CallResultCPU,
*h_PutResultCPU,
*h_CallResultGPU,
*h_PutResultGPU,
*h_StockPrice,
*h_OptionStrike,
*h_OptionYears;
float
*d_CallResult,
*d_PutResult,
*d_StockPrice,
*d_OptionStrike,
*d_OptionYears;
double delta, ref, sum_delta, sum_ref, max_delta, L1norm;
int i;
// CPU memory allocation
h_CallResultCPU = (float *)malloc(options_size);
h_PutResultCPU = (float *)malloc(options_size);
h_CallResultGPU = (float *)malloc(options_size);
h_PutResultGPU = (float *)malloc(options_size);
h_StockPrice = (float *)malloc(options_size);
h_OptionStrike = (float *)malloc(options_size);
h_OptionYears = (float *)malloc(options_size);
// GPU memory allocation
cudaMalloc((void **)&d_CallResult, options_size);
cudaMalloc((void **)&d_PutResult, options_size);
cudaMalloc((void **)&d_StockPrice, options_size);
cudaMalloc((void **)&d_OptionStrike, options_size);
cudaMalloc((void **)&d_OptionYears, options_size);
srand(5347);
// Generate options set
for (i = 0; i < options; i++)
{
h_CallResultCPU[i] = 0.0f;
h_PutResultCPU[i] = -1.0f;
h_StockPrice[i] = RandFloat(5.0f, 30.0f);
h_OptionStrike[i] = RandFloat(1.0f, 100.0f);
h_OptionYears[i] = RandFloat(0.25f, 10.0f);
}
// Copy options data to GPU memory for further processing
cudaMemcpy(d_StockPrice, h_StockPrice, options_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_OptionStrike, h_OptionStrike, options_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_OptionYears, h_OptionYears, options_size, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
timeval starttime, endtime;
double runtime;
if (gpu) {
gettimeofday(&starttime, NULL);
for (i = 0; i < NUM_ITERATIONS; i++) {
BlackScholesGPU<<<DIV_UP(options, 128), 128>>>(
d_CallResult,
d_PutResult,
d_StockPrice,
d_OptionStrike,
d_OptionYears,
RISKFREE,
VOLATILITY,
options
);
}
cudaDeviceSynchronize();
gettimeofday(&endtime, NULL);
}
else {
gettimeofday(&starttime, NULL);
//Calculate options values on CPU
BlackScholesCPU(
h_CallResultCPU,
h_PutResultCPU,
h_StockPrice,
h_OptionStrike,
h_OptionYears,
RISKFREE,
VOLATILITY,
options
);
gettimeofday(&endtime, NULL);
}
// Read back GPU results to compare them to CPU results
cudaMemcpy(h_CallResultGPU, d_CallResult, options_size, cudaMemcpyDeviceToHost);
cudaMemcpy(h_PutResultGPU, d_PutResult, options_size, cudaMemcpyDeviceToHost);
runtime = endtime.tv_sec + endtime.tv_usec / 1000000.0 - (starttime.tv_sec + starttime.tv_usec / 1000000.0);
fprintf(stdout, "\033[1;32m[wk3] compute time = %.3f s\n\033[0m", runtime);
#ifdef VERIFY
printf("%3.5f,%3.5f\n", h_CallResultGPU[2047],h_PutResultGPU[3145]);
#endif
// validation not use; code is running on either GPU or CPU
sum_delta = 0;
sum_ref = 0;
max_delta = 0;
for (i = 0; i < options; i++)
{
ref = h_CallResultCPU[i];
delta = fabs(h_CallResultCPU[i] - h_CallResultGPU[i]);
if (delta > max_delta)
{
max_delta = delta;
}
sum_delta += delta;
sum_ref += fabs(ref);
}
L1norm = sum_delta / sum_ref;
cudaFree(d_OptionYears);
cudaFree(d_OptionStrike);
cudaFree(d_StockPrice);
cudaFree(d_PutResult);
cudaFree(d_CallResult);
free(h_OptionYears);
free(h_OptionStrike);
free(h_StockPrice);
free(h_PutResultGPU);
free(h_CallResultGPU);
free(h_PutResultCPU);
free(h_CallResultCPU);
if (L1norm > 1e-6)
{
exit(EXIT_FAILURE);
}
exit(EXIT_SUCCESS);
} | .file "tmpxft_000b8e25_00000000-6_gpu_wkld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL3CNDd, @function
_ZL3CNDd:
.LFB2057:
.cfi_startproc
subq $24, %rsp
.cfi_def_cfa_offset 32
movapd %xmm0, %xmm3
andpd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
movsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, (%rsp)
movapd %xmm3, %xmm0
mulsd .LC3(%rip), %xmm0
movsd %xmm3, 8(%rsp)
mulsd %xmm3, %xmm0
call exp@PLT
movapd %xmm0, %xmm1
movsd (%rsp), %xmm2
movapd %xmm2, %xmm0
mulsd .LC4(%rip), %xmm0
subsd .LC5(%rip), %xmm0
mulsd %xmm2, %xmm0
addsd .LC6(%rip), %xmm0
mulsd %xmm2, %xmm0
subsd .LC7(%rip), %xmm0
mulsd %xmm2, %xmm0
addsd .LC8(%rip), %xmm0
mulsd %xmm2, %xmm0
mulsd .LC9(%rip), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
movsd 8(%rsp), %xmm3
comisd %xmm1, %xmm3
jbe .L1
movsd .LC2(%rip), %xmm1
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
.L1:
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL3CNDd, .-_ZL3CNDd
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15BlackScholesCPUPfS_S_S_S_ffi
.type _Z15BlackScholesCPUPfS_S_S_S_ffi, @function
_Z15BlackScholesCPUPfS_S_S_S_ffi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 48(%rsp)
testl %r9d, %r9d
jle .L8
movq %rsi, %r15
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movslq %r9d, %r9
leaq 0(,%r9,4), %rbp
movl $0, %ebx
pxor %xmm6, %xmm6
cvtss2sd %xmm0, %xmm6
movsd %xmm6, 56(%rsp)
pxor %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movsd %xmm2, 64(%rsp)
xorpd .LC12(%rip), %xmm6
movsd %xmm6, 72(%rsp)
.L13:
pxor %xmm3, %xmm3
cvtss2sd (%r12,%rbx), %xmm3
movsd %xmm3, 16(%rsp)
pxor %xmm3, %xmm3
cvtss2sd 0(%r13,%rbx), %xmm3
movsd %xmm3, 24(%rsp)
pxor %xmm5, %xmm5
cvtss2sd (%r14,%rbx), %xmm5
movsd %xmm5, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm5, %xmm0
ja .L16
sqrtsd %xmm5, %xmm5
movsd %xmm5, 32(%rsp)
.L12:
movsd 16(%rsp), %xmm0
divsd 24(%rsp), %xmm0
call log@PLT
movapd %xmm0, %xmm2
movsd 32(%rsp), %xmm1
movsd 64(%rsp), %xmm7
mulsd %xmm7, %xmm1
movsd .LC11(%rip), %xmm4
mulsd %xmm7, %xmm4
movapd %xmm4, %xmm0
mulsd %xmm7, %xmm0
addsd 56(%rsp), %xmm0
mulsd 8(%rsp), %xmm0
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
movapd %xmm0, %xmm7
subsd %xmm1, %xmm7
movsd %xmm7, 32(%rsp)
call _ZL3CNDd
movsd %xmm0, 40(%rsp)
movsd 32(%rsp), %xmm0
call _ZL3CNDd
movsd %xmm0, 32(%rsp)
movsd 8(%rsp), %xmm4
mulsd 72(%rsp), %xmm4
movapd %xmm4, %xmm0
call exp@PLT
movsd 24(%rsp), %xmm2
mulsd %xmm0, %xmm2
movsd 16(%rsp), %xmm3
movapd %xmm3, %xmm4
movsd 40(%rsp), %xmm5
mulsd %xmm5, %xmm4
movapd %xmm4, %xmm0
movsd 32(%rsp), %xmm6
movapd %xmm6, %xmm1
mulsd %xmm2, %xmm1
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%rbx)
movsd .LC2(%rip), %xmm1
movapd %xmm1, %xmm0
subsd %xmm6, %xmm0
mulsd %xmm2, %xmm0
subsd %xmm5, %xmm1
mulsd %xmm3, %xmm1
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
.L8:
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
movsd %xmm0, 32(%rsp)
jmp .L12
.cfi_endproc
.LFE2059:
.size _Z15BlackScholesCPUPfS_S_S_S_ffi, .-_Z15BlackScholesCPUPfS_S_S_S_ffi
.globl _Z9RandFloatff
.type _Z9RandFloatff, @function
_Z9RandFloatff:
.LFB2062:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
call rand@PLT
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
mulss .LC13(%rip), %xmm1
movss .LC14(%rip), %xmm0
subss %xmm1, %xmm0
mulss 8(%rsp), %xmm0
mulss 12(%rsp), %xmm1
addss %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9RandFloatff, .-_Z9RandFloatff
.globl _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
.type _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi, @function
_Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi:
.LFB2088:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15BlackScholesGPUPfS_S_S_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi, .-_Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
.globl _Z15BlackScholesGPUPfS_S_S_S_ffi
.type _Z15BlackScholesGPUPfS_S_S_S_ffi, @function
_Z15BlackScholesGPUPfS_S_S_S_ffi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15BlackScholesGPUPfS_S_S_S_ffi, .-_Z15BlackScholesGPUPfS_S_S_S_ffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC15:
.string "usage: ./blackscholes options GPU\n"
.align 8
.LC26:
.string "\033[1;32m[wk3] compute time = %.3f s\n\033[0m"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jg .L29
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L29:
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 48(%rsp)
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 56(%rsp)
leal 0(,%r15,4), %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $5347, %edi
call srand@PLT
testl %r14d, %r14d
je .L30
movl %r14d, %r13d
movl $0, %ebx
movq %r12, 64(%rsp)
movq 16(%rsp), %r12
movl %r14d, 76(%rsp)
movq 24(%rsp), %r14
.L31:
movl $0x00000000, 0(%rbp,%rbx,4)
movq 8(%rsp), %rax
movl $0xbf800000, (%rax,%rbx,4)
movss .LC18(%rip), %xmm1
movss .LC19(%rip), %xmm0
call _Z9RandFloatff
movss %xmm0, (%r15,%rbx,4)
movss .LC20(%rip), %xmm1
movss .LC14(%rip), %xmm0
call _Z9RandFloatff
movss %xmm0, (%r12,%rbx,4)
movss .LC21(%rip), %xmm1
movss .LC22(%rip), %xmm0
call _Z9RandFloatff
movss %xmm0, (%r14,%rbx,4)
addq $1, %rbx
cmpq %r13, %rbx
jne .L31
movq 64(%rsp), %r12
movl 76(%rsp), %r14d
.L30:
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
cmpl $0, 56(%rsp)
je .L32
leaq 144(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 48(%rsp), %eax
leal 127(%rax), %r13d
shrl $7, %r13d
movl $512, %ebx
jmp .L34
.L33:
subl $1, %ebx
je .L50
.L34:
movl $128, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl %r13d, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 132(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %r14d, %r9d
movss .LC23(%rip), %xmm1
movss .LC24(%rip), %xmm0
movq 120(%rsp), %r8
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
jmp .L33
.L50:
call cudaDeviceSynchronize@PLT
leaq 160(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L35:
movl $2, %ecx
movq %r12, %rdx
movq 88(%rsp), %rsi
movq 32(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq 96(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 168(%rsp), %xmm0
movsd .LC25(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 160(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 152(%rsp), %xmm1
divsd %xmm2, %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 144(%rsp), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 48(%rsp), %rax
testl %eax, %eax
je .L42
movl %eax, %edx
movl $0, %eax
pxor %xmm2, %xmm2
movapd %xmm2, %xmm3
movss .LC27(%rip), %xmm5
movq .LC0(%rip), %xmm4
movq %rbx, %rcx
.L38:
movss 0(%rbp,%rax,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
subss (%rcx,%rax,4), %xmm0
andps %xmm5, %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm3
andpd %xmm4, %xmm1
addsd %xmm1, %xmm2
addq $1, %rax
cmpq %rdx, %rax
jne .L38
.L36:
divsd %xmm2, %xmm3
movq %xmm3, %rbx
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %xmm6
comisd .LC28(%rip), %xmm6
jbe .L48
movl $1, %edi
call exit@PLT
.L32:
leaq 144(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 48(%rsp), %r9d
movss .LC23(%rip), %xmm1
movss .LC24(%rip), %xmm0
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call _Z15BlackScholesCPUPfS_S_S_S_ffi
leaq 160(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L35
.L42:
pxor %xmm2, %xmm2
movapd %xmm2, %xmm3
jmp .L36
.L48:
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC29:
.string "_Z15BlackScholesGPUPfS_S_S_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z15BlackScholesGPUPfS_S_S_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 410062862
.long 1070442097
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long -1075838976
.align 8
.LC4:
.long -688641725
.long 1073039565
.align 8
.LC5:
.long 1324513488
.long 1073554397
.align 8
.LC6:
.long 39804520
.long 1073512687
.align 8
.LC7:
.long -441961893
.long 1071043056
.align 8
.LC8:
.long 982710508
.long 1070887103
.align 8
.LC9:
.long 869545553
.long 1071220805
.align 8
.LC11:
.long 0
.long 1071644672
.section .rodata.cst16
.align 16
.LC12:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 805306368
.align 4
.LC14:
.long 1065353216
.align 4
.LC18:
.long 1106247680
.align 4
.LC19:
.long 1084227584
.align 4
.LC20:
.long 1120403456
.align 4
.LC21:
.long 1092616192
.align 4
.LC22:
.long 1048576000
.align 4
.LC23:
.long 1050253722
.align 4
.LC24:
.long 1017370378
.section .rodata.cst8
.align 8
.LC25:
.long 0
.long 1093567616
.section .rodata.cst16
.align 16
.LC27:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC28:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
/*
* Code to simulate a GPU workload for lab assignment in [A2] Task Mapping on Soft Heterogeneous Systems.
* Workload consists of a the Black-Scholes kernel taken from NVIDIA SDK 10.1
*
* Computation is done on the GPU when the user selects a core attached to a GPU; otherwise the code is run on
* the CPU. GPU version of the code is expected to run faster.
*
* @author: Apan Qasem <apan@txstate.edu>
* @date: 04/02/20
*
* @update: 03/12/21
*/
#include<cstdio>
#include<sys/time.h>
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
static double CND(double d)
{
const double A1 = 0.31938153;
const double A2 = -0.356563782;
const double A3 = 1.781477937;
const double A4 = -1.821255978;
const double A5 = 1.330274429;
const double RSQRT2PI = 0.39894228040143267793994605993438;
double
K = 1.0 / (1.0 + 0.2316419 * fabs(d));
double
cnd = RSQRT2PI * exp(- 0.5 * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0 - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
static void BlackScholesBodyCPU(
float &callResult,
float &putResult,
float Sf, //Stock price
float Xf, //Option strike
float Tf, //Option years
float Rf, //Riskless rate
float Vf //Volatility rate
)
{
double S = Sf, X = Xf, T = Tf, R = Rf, V = Vf;
double sqrtT = sqrt(T);
double d1 = (log(S / X) + (R + 0.5 * V * V) * T) / (V * sqrtT);
double d2 = d1 - V * sqrtT;
double CNDD1 = CND(d1);
double CNDD2 = CND(d2);
//Calculate Call and Put simultaneously
double expRT = exp(- R * T);
callResult = (float)(S * CNDD1 - X * expRT * CNDD2);
putResult = (float)(X * expRT * (1.0 - CNDD2) - S * (1.0 - CNDD1));
}
////////////////////////////////////////////////////////////////////////////////
// Process an array of optN options
////////////////////////////////////////////////////////////////////////////////
void BlackScholesCPU(
float *h_CallResult,
float *h_PutResult,
float *h_StockPrice,
float *h_OptionStrike,
float *h_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
for (int opt = 0; opt < optN; opt++)
BlackScholesBodyCPU(
h_CallResult[opt],
h_PutResult[opt],
h_StockPrice[opt],
h_OptionStrike[opt],
h_OptionYears[opt],
Riskfree,
Volatility
);
}
// extern "C" void BlackScholesCPU(
// float *h_CallResult,
// float *h_PutResult,
// float *h_StockPrice,
// float *h_OptionStrike,
// float *h_OptionYears,
// float Riskfree,
// float Volatility,
// int optN
// );
////////////////////////////////////////////////////////////////////////////////
// Process an array of OptN options on GPU
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
__device__ inline float cndGPU(float d)
{
const float A1 = 0.31938153f;
const float A2 = -0.356563782f;
const float A3 = 1.781477937f;
const float A4 = -1.821255978f;
const float A5 = 1.330274429f;
const float RSQRT2PI = 0.39894228040143267793994605993438f;
float
K = 1.0f / (1.0f + 0.2316419f * fabsf(d));
float
cnd = RSQRT2PI * __expf(- 0.5f * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0f - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
__device__ inline void BlackScholesBodyGPU(
float &CallResult,
float &PutResult,
float S, //Stock price
float X, //Option strike
float T, //Option years
float R, //Riskless rate
float V //Volatility rate
)
{
float sqrtT, expRT;
float d1, d2, CNDD1, CNDD2;
sqrtT = sqrtf(T);
d1 = (__logf(S / X) + (R + 0.5f * V * V) * T) / (V * sqrtT);
d2 = d1 - V * sqrtT;
CNDD1 = cndGPU(d1);
CNDD2 = cndGPU(d2);
//Calculate Call and Put simultaneously
expRT = __expf(- R * T);
CallResult = S * CNDD1 - X * expRT * CNDD2;
PutResult = X * expRT * (1.0f - CNDD2) - S * (1.0f - CNDD1);
}
////////////////////////////////////////////////////////////////////////////////
//Process an array of optN options on GPU
////////////////////////////////////////////////////////////////////////////////
__global__ void BlackScholesGPU(
float *d_CallResult,
float *d_PutResult,
float *d_StockPrice,
float *d_OptionStrike,
float *d_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
////Thread index
//const int tid = blockDim.x * blockIdx.x + threadIdx.x;
////Total number of threads in execution grid
//const int THREAD_N = blockDim.x * gridDim.x;
const int opt = blockDim.x * blockIdx.x + threadIdx.x;
//No matter how small is execution grid or how large OptN is,
//exactly OptN indices will be processed with perfect memory coalescing
//for (int opt = tid; opt < optN; opt += THREAD_N)
if (opt < optN)
BlackScholesBodyGPU(
d_CallResult[opt],
d_PutResult[opt],
d_StockPrice[opt],
d_OptionStrike[opt],
d_OptionYears[opt],
Riskfree,
Volatility
);
}
////////////////////////////////////////////////////////////////////////////////
// Helper function, returning uniformly distributed
// random float in [low, high] range
////////////////////////////////////////////////////////////////////////////////
float RandFloat(float low, float high)
{
float t = (float)rand() / (float)RAND_MAX;
return (1.0f - t) * low + t * high;
}
////////////////////////////////////////////////////////////////////////////////
// Data configuration
////////////////////////////////////////////////////////////////////////////////
const int NUM_ITERATIONS = 512;
const float RISKFREE = 0.02f;
const float VOLATILITY = 0.30f;
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
////////////////////////////////////////////////////////////////////////////////
// Main program
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
if (argc < 3) {
fprintf(stderr, "usage: ./blackscholes options GPU\n");
exit(0);
}
unsigned options = atoi(argv[1]);
int options_size = options * sizeof(float);
unsigned gpu = atoi(argv[2]);
float
*h_CallResultCPU,
*h_PutResultCPU,
*h_CallResultGPU,
*h_PutResultGPU,
*h_StockPrice,
*h_OptionStrike,
*h_OptionYears;
float
*d_CallResult,
*d_PutResult,
*d_StockPrice,
*d_OptionStrike,
*d_OptionYears;
double delta, ref, sum_delta, sum_ref, max_delta, L1norm;
int i;
// CPU memory allocation
h_CallResultCPU = (float *)malloc(options_size);
h_PutResultCPU = (float *)malloc(options_size);
h_CallResultGPU = (float *)malloc(options_size);
h_PutResultGPU = (float *)malloc(options_size);
h_StockPrice = (float *)malloc(options_size);
h_OptionStrike = (float *)malloc(options_size);
h_OptionYears = (float *)malloc(options_size);
// GPU memory allocation
cudaMalloc((void **)&d_CallResult, options_size);
cudaMalloc((void **)&d_PutResult, options_size);
cudaMalloc((void **)&d_StockPrice, options_size);
cudaMalloc((void **)&d_OptionStrike, options_size);
cudaMalloc((void **)&d_OptionYears, options_size);
srand(5347);
// Generate options set
for (i = 0; i < options; i++)
{
h_CallResultCPU[i] = 0.0f;
h_PutResultCPU[i] = -1.0f;
h_StockPrice[i] = RandFloat(5.0f, 30.0f);
h_OptionStrike[i] = RandFloat(1.0f, 100.0f);
h_OptionYears[i] = RandFloat(0.25f, 10.0f);
}
// Copy options data to GPU memory for further processing
cudaMemcpy(d_StockPrice, h_StockPrice, options_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_OptionStrike, h_OptionStrike, options_size, cudaMemcpyHostToDevice);
cudaMemcpy(d_OptionYears, h_OptionYears, options_size, cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
timeval starttime, endtime;
double runtime;
if (gpu) {
gettimeofday(&starttime, NULL);
for (i = 0; i < NUM_ITERATIONS; i++) {
BlackScholesGPU<<<DIV_UP(options, 128), 128>>>(
d_CallResult,
d_PutResult,
d_StockPrice,
d_OptionStrike,
d_OptionYears,
RISKFREE,
VOLATILITY,
options
);
}
cudaDeviceSynchronize();
gettimeofday(&endtime, NULL);
}
else {
gettimeofday(&starttime, NULL);
//Calculate options values on CPU
BlackScholesCPU(
h_CallResultCPU,
h_PutResultCPU,
h_StockPrice,
h_OptionStrike,
h_OptionYears,
RISKFREE,
VOLATILITY,
options
);
gettimeofday(&endtime, NULL);
}
// Read back GPU results to compare them to CPU results
cudaMemcpy(h_CallResultGPU, d_CallResult, options_size, cudaMemcpyDeviceToHost);
cudaMemcpy(h_PutResultGPU, d_PutResult, options_size, cudaMemcpyDeviceToHost);
runtime = endtime.tv_sec + endtime.tv_usec / 1000000.0 - (starttime.tv_sec + starttime.tv_usec / 1000000.0);
fprintf(stdout, "\033[1;32m[wk3] compute time = %.3f s\n\033[0m", runtime);
#ifdef VERIFY
printf("%3.5f,%3.5f\n", h_CallResultGPU[2047],h_PutResultGPU[3145]);
#endif
// validation not use; code is running on either GPU or CPU
sum_delta = 0;
sum_ref = 0;
max_delta = 0;
for (i = 0; i < options; i++)
{
ref = h_CallResultCPU[i];
delta = fabs(h_CallResultCPU[i] - h_CallResultGPU[i]);
if (delta > max_delta)
{
max_delta = delta;
}
sum_delta += delta;
sum_ref += fabs(ref);
}
L1norm = sum_delta / sum_ref;
cudaFree(d_OptionYears);
cudaFree(d_OptionStrike);
cudaFree(d_StockPrice);
cudaFree(d_PutResult);
cudaFree(d_CallResult);
free(h_OptionYears);
free(h_OptionStrike);
free(h_StockPrice);
free(h_PutResultGPU);
free(h_CallResultGPU);
free(h_PutResultCPU);
free(h_CallResultCPU);
if (L1norm > 1e-6)
{
exit(EXIT_FAILURE);
}
exit(EXIT_SUCCESS);
} | /*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
/*
* Code to simulate a GPU workload for lab assignment in [A2] Task Mapping on Soft Heterogeneous Systems.
* Workload consists of a the Black-Scholes kernel taken from NVIDIA SDK 10.1
*
* Computation is done on the GPU when the user selects a core attached to a GPU; otherwise the code is run on
* the CPU. GPU version of the code is expected to run faster.
*
* @author: Apan Qasem <apan@txstate.edu>
* @date: 04/02/20
*
* @update: 03/12/21
*/
#include <hip/hip_runtime.h>
#include<cstdio>
#include<sys/time.h>
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
static double CND(double d)
{
const double A1 = 0.31938153;
const double A2 = -0.356563782;
const double A3 = 1.781477937;
const double A4 = -1.821255978;
const double A5 = 1.330274429;
const double RSQRT2PI = 0.39894228040143267793994605993438;
double
K = 1.0 / (1.0 + 0.2316419 * fabs(d));
double
cnd = RSQRT2PI * exp(- 0.5 * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0 - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
static void BlackScholesBodyCPU(
float &callResult,
float &putResult,
float Sf, //Stock price
float Xf, //Option strike
float Tf, //Option years
float Rf, //Riskless rate
float Vf //Volatility rate
)
{
double S = Sf, X = Xf, T = Tf, R = Rf, V = Vf;
double sqrtT = sqrt(T);
double d1 = (log(S / X) + (R + 0.5 * V * V) * T) / (V * sqrtT);
double d2 = d1 - V * sqrtT;
double CNDD1 = CND(d1);
double CNDD2 = CND(d2);
//Calculate Call and Put simultaneously
double expRT = exp(- R * T);
callResult = (float)(S * CNDD1 - X * expRT * CNDD2);
putResult = (float)(X * expRT * (1.0 - CNDD2) - S * (1.0 - CNDD1));
}
////////////////////////////////////////////////////////////////////////////////
// Process an array of optN options
////////////////////////////////////////////////////////////////////////////////
void BlackScholesCPU(
float *h_CallResult,
float *h_PutResult,
float *h_StockPrice,
float *h_OptionStrike,
float *h_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
for (int opt = 0; opt < optN; opt++)
BlackScholesBodyCPU(
h_CallResult[opt],
h_PutResult[opt],
h_StockPrice[opt],
h_OptionStrike[opt],
h_OptionYears[opt],
Riskfree,
Volatility
);
}
// extern "C" void BlackScholesCPU(
// float *h_CallResult,
// float *h_PutResult,
// float *h_StockPrice,
// float *h_OptionStrike,
// float *h_OptionYears,
// float Riskfree,
// float Volatility,
// int optN
// );
////////////////////////////////////////////////////////////////////////////////
// Process an array of OptN options on GPU
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
__device__ inline float cndGPU(float d)
{
const float A1 = 0.31938153f;
const float A2 = -0.356563782f;
const float A3 = 1.781477937f;
const float A4 = -1.821255978f;
const float A5 = 1.330274429f;
const float RSQRT2PI = 0.39894228040143267793994605993438f;
float
K = 1.0f / (1.0f + 0.2316419f * fabsf(d));
float
cnd = RSQRT2PI * __expf(- 0.5f * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0f - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
__device__ inline void BlackScholesBodyGPU(
float &CallResult,
float &PutResult,
float S, //Stock price
float X, //Option strike
float T, //Option years
float R, //Riskless rate
float V //Volatility rate
)
{
float sqrtT, expRT;
float d1, d2, CNDD1, CNDD2;
sqrtT = sqrtf(T);
d1 = (__logf(S / X) + (R + 0.5f * V * V) * T) / (V * sqrtT);
d2 = d1 - V * sqrtT;
CNDD1 = cndGPU(d1);
CNDD2 = cndGPU(d2);
//Calculate Call and Put simultaneously
expRT = __expf(- R * T);
CallResult = S * CNDD1 - X * expRT * CNDD2;
PutResult = X * expRT * (1.0f - CNDD2) - S * (1.0f - CNDD1);
}
////////////////////////////////////////////////////////////////////////////////
//Process an array of optN options on GPU
////////////////////////////////////////////////////////////////////////////////
__global__ void BlackScholesGPU(
float *d_CallResult,
float *d_PutResult,
float *d_StockPrice,
float *d_OptionStrike,
float *d_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
////Thread index
//const int tid = blockDim.x * blockIdx.x + threadIdx.x;
////Total number of threads in execution grid
//const int THREAD_N = blockDim.x * gridDim.x;
const int opt = blockDim.x * blockIdx.x + threadIdx.x;
//No matter how small is execution grid or how large OptN is,
//exactly OptN indices will be processed with perfect memory coalescing
//for (int opt = tid; opt < optN; opt += THREAD_N)
if (opt < optN)
BlackScholesBodyGPU(
d_CallResult[opt],
d_PutResult[opt],
d_StockPrice[opt],
d_OptionStrike[opt],
d_OptionYears[opt],
Riskfree,
Volatility
);
}
////////////////////////////////////////////////////////////////////////////////
// Helper function, returning uniformly distributed
// random float in [low, high] range
////////////////////////////////////////////////////////////////////////////////
float RandFloat(float low, float high)
{
float t = (float)rand() / (float)RAND_MAX;
return (1.0f - t) * low + t * high;
}
////////////////////////////////////////////////////////////////////////////////
// Data configuration
////////////////////////////////////////////////////////////////////////////////
const int NUM_ITERATIONS = 512;
const float RISKFREE = 0.02f;
const float VOLATILITY = 0.30f;
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
////////////////////////////////////////////////////////////////////////////////
// Main program
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
if (argc < 3) {
fprintf(stderr, "usage: ./blackscholes options GPU\n");
exit(0);
}
unsigned options = atoi(argv[1]);
int options_size = options * sizeof(float);
unsigned gpu = atoi(argv[2]);
float
*h_CallResultCPU,
*h_PutResultCPU,
*h_CallResultGPU,
*h_PutResultGPU,
*h_StockPrice,
*h_OptionStrike,
*h_OptionYears;
float
*d_CallResult,
*d_PutResult,
*d_StockPrice,
*d_OptionStrike,
*d_OptionYears;
double delta, ref, sum_delta, sum_ref, max_delta, L1norm;
int i;
// CPU memory allocation
h_CallResultCPU = (float *)malloc(options_size);
h_PutResultCPU = (float *)malloc(options_size);
h_CallResultGPU = (float *)malloc(options_size);
h_PutResultGPU = (float *)malloc(options_size);
h_StockPrice = (float *)malloc(options_size);
h_OptionStrike = (float *)malloc(options_size);
h_OptionYears = (float *)malloc(options_size);
// GPU memory allocation
hipMalloc((void **)&d_CallResult, options_size);
hipMalloc((void **)&d_PutResult, options_size);
hipMalloc((void **)&d_StockPrice, options_size);
hipMalloc((void **)&d_OptionStrike, options_size);
hipMalloc((void **)&d_OptionYears, options_size);
srand(5347);
// Generate options set
for (i = 0; i < options; i++)
{
h_CallResultCPU[i] = 0.0f;
h_PutResultCPU[i] = -1.0f;
h_StockPrice[i] = RandFloat(5.0f, 30.0f);
h_OptionStrike[i] = RandFloat(1.0f, 100.0f);
h_OptionYears[i] = RandFloat(0.25f, 10.0f);
}
// Copy options data to GPU memory for further processing
hipMemcpy(d_StockPrice, h_StockPrice, options_size, hipMemcpyHostToDevice);
hipMemcpy(d_OptionStrike, h_OptionStrike, options_size, hipMemcpyHostToDevice);
hipMemcpy(d_OptionYears, h_OptionYears, options_size, hipMemcpyHostToDevice);
hipDeviceSynchronize();
timeval starttime, endtime;
double runtime;
if (gpu) {
gettimeofday(&starttime, NULL);
for (i = 0; i < NUM_ITERATIONS; i++) {
BlackScholesGPU<<<DIV_UP(options, 128), 128>>>(
d_CallResult,
d_PutResult,
d_StockPrice,
d_OptionStrike,
d_OptionYears,
RISKFREE,
VOLATILITY,
options
);
}
hipDeviceSynchronize();
gettimeofday(&endtime, NULL);
}
else {
gettimeofday(&starttime, NULL);
//Calculate options values on CPU
BlackScholesCPU(
h_CallResultCPU,
h_PutResultCPU,
h_StockPrice,
h_OptionStrike,
h_OptionYears,
RISKFREE,
VOLATILITY,
options
);
gettimeofday(&endtime, NULL);
}
// Read back GPU results to compare them to CPU results
hipMemcpy(h_CallResultGPU, d_CallResult, options_size, hipMemcpyDeviceToHost);
hipMemcpy(h_PutResultGPU, d_PutResult, options_size, hipMemcpyDeviceToHost);
runtime = endtime.tv_sec + endtime.tv_usec / 1000000.0 - (starttime.tv_sec + starttime.tv_usec / 1000000.0);
fprintf(stdout, "\033[1;32m[wk3] compute time = %.3f s\n\033[0m", runtime);
#ifdef VERIFY
printf("%3.5f,%3.5f\n", h_CallResultGPU[2047],h_PutResultGPU[3145]);
#endif
// validation not use; code is running on either GPU or CPU
sum_delta = 0;
sum_ref = 0;
max_delta = 0;
for (i = 0; i < options; i++)
{
ref = h_CallResultCPU[i];
delta = fabs(h_CallResultCPU[i] - h_CallResultGPU[i]);
if (delta > max_delta)
{
max_delta = delta;
}
sum_delta += delta;
sum_ref += fabs(ref);
}
L1norm = sum_delta / sum_ref;
hipFree(d_OptionYears);
hipFree(d_OptionStrike);
hipFree(d_StockPrice);
hipFree(d_PutResult);
hipFree(d_CallResult);
free(h_OptionYears);
free(h_OptionStrike);
free(h_StockPrice);
free(h_PutResultGPU);
free(h_CallResultGPU);
free(h_PutResultCPU);
free(h_CallResultCPU);
if (L1norm > 1e-6)
{
exit(EXIT_FAILURE);
}
exit(EXIT_SUCCESS);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
/*
* Code to simulate a GPU workload for lab assignment in [A2] Task Mapping on Soft Heterogeneous Systems.
* Workload consists of a the Black-Scholes kernel taken from NVIDIA SDK 10.1
*
* Computation is done on the GPU when the user selects a core attached to a GPU; otherwise the code is run on
* the CPU. GPU version of the code is expected to run faster.
*
* @author: Apan Qasem <apan@txstate.edu>
* @date: 04/02/20
*
* @update: 03/12/21
*/
#include <hip/hip_runtime.h>
#include<cstdio>
#include<sys/time.h>
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
static double CND(double d)
{
const double A1 = 0.31938153;
const double A2 = -0.356563782;
const double A3 = 1.781477937;
const double A4 = -1.821255978;
const double A5 = 1.330274429;
const double RSQRT2PI = 0.39894228040143267793994605993438;
double
K = 1.0 / (1.0 + 0.2316419 * fabs(d));
double
cnd = RSQRT2PI * exp(- 0.5 * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0 - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
static void BlackScholesBodyCPU(
float &callResult,
float &putResult,
float Sf, //Stock price
float Xf, //Option strike
float Tf, //Option years
float Rf, //Riskless rate
float Vf //Volatility rate
)
{
double S = Sf, X = Xf, T = Tf, R = Rf, V = Vf;
double sqrtT = sqrt(T);
double d1 = (log(S / X) + (R + 0.5 * V * V) * T) / (V * sqrtT);
double d2 = d1 - V * sqrtT;
double CNDD1 = CND(d1);
double CNDD2 = CND(d2);
//Calculate Call and Put simultaneously
double expRT = exp(- R * T);
callResult = (float)(S * CNDD1 - X * expRT * CNDD2);
putResult = (float)(X * expRT * (1.0 - CNDD2) - S * (1.0 - CNDD1));
}
////////////////////////////////////////////////////////////////////////////////
// Process an array of optN options
////////////////////////////////////////////////////////////////////////////////
void BlackScholesCPU(
float *h_CallResult,
float *h_PutResult,
float *h_StockPrice,
float *h_OptionStrike,
float *h_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
for (int opt = 0; opt < optN; opt++)
BlackScholesBodyCPU(
h_CallResult[opt],
h_PutResult[opt],
h_StockPrice[opt],
h_OptionStrike[opt],
h_OptionYears[opt],
Riskfree,
Volatility
);
}
// extern "C" void BlackScholesCPU(
// float *h_CallResult,
// float *h_PutResult,
// float *h_StockPrice,
// float *h_OptionStrike,
// float *h_OptionYears,
// float Riskfree,
// float Volatility,
// int optN
// );
////////////////////////////////////////////////////////////////////////////////
// Process an array of OptN options on GPU
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
__device__ inline float cndGPU(float d)
{
const float A1 = 0.31938153f;
const float A2 = -0.356563782f;
const float A3 = 1.781477937f;
const float A4 = -1.821255978f;
const float A5 = 1.330274429f;
const float RSQRT2PI = 0.39894228040143267793994605993438f;
float
K = 1.0f / (1.0f + 0.2316419f * fabsf(d));
float
cnd = RSQRT2PI * __expf(- 0.5f * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0f - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
__device__ inline void BlackScholesBodyGPU(
float &CallResult,
float &PutResult,
float S, //Stock price
float X, //Option strike
float T, //Option years
float R, //Riskless rate
float V //Volatility rate
)
{
float sqrtT, expRT;
float d1, d2, CNDD1, CNDD2;
sqrtT = sqrtf(T);
d1 = (__logf(S / X) + (R + 0.5f * V * V) * T) / (V * sqrtT);
d2 = d1 - V * sqrtT;
CNDD1 = cndGPU(d1);
CNDD2 = cndGPU(d2);
//Calculate Call and Put simultaneously
expRT = __expf(- R * T);
CallResult = S * CNDD1 - X * expRT * CNDD2;
PutResult = X * expRT * (1.0f - CNDD2) - S * (1.0f - CNDD1);
}
////////////////////////////////////////////////////////////////////////////////
//Process an array of optN options on GPU
////////////////////////////////////////////////////////////////////////////////
__global__ void BlackScholesGPU(
float *d_CallResult,
float *d_PutResult,
float *d_StockPrice,
float *d_OptionStrike,
float *d_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
////Thread index
//const int tid = blockDim.x * blockIdx.x + threadIdx.x;
////Total number of threads in execution grid
//const int THREAD_N = blockDim.x * gridDim.x;
const int opt = blockDim.x * blockIdx.x + threadIdx.x;
//No matter how small is execution grid or how large OptN is,
//exactly OptN indices will be processed with perfect memory coalescing
//for (int opt = tid; opt < optN; opt += THREAD_N)
if (opt < optN)
BlackScholesBodyGPU(
d_CallResult[opt],
d_PutResult[opt],
d_StockPrice[opt],
d_OptionStrike[opt],
d_OptionYears[opt],
Riskfree,
Volatility
);
}
////////////////////////////////////////////////////////////////////////////////
// Helper function, returning uniformly distributed
// random float in [low, high] range
////////////////////////////////////////////////////////////////////////////////
float RandFloat(float low, float high)
{
float t = (float)rand() / (float)RAND_MAX;
return (1.0f - t) * low + t * high;
}
////////////////////////////////////////////////////////////////////////////////
// Data configuration
////////////////////////////////////////////////////////////////////////////////
const int NUM_ITERATIONS = 512;
const float RISKFREE = 0.02f;
const float VOLATILITY = 0.30f;
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
////////////////////////////////////////////////////////////////////////////////
// Main program
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
if (argc < 3) {
fprintf(stderr, "usage: ./blackscholes options GPU\n");
exit(0);
}
unsigned options = atoi(argv[1]);
int options_size = options * sizeof(float);
unsigned gpu = atoi(argv[2]);
float
*h_CallResultCPU,
*h_PutResultCPU,
*h_CallResultGPU,
*h_PutResultGPU,
*h_StockPrice,
*h_OptionStrike,
*h_OptionYears;
float
*d_CallResult,
*d_PutResult,
*d_StockPrice,
*d_OptionStrike,
*d_OptionYears;
double delta, ref, sum_delta, sum_ref, max_delta, L1norm;
int i;
// CPU memory allocation
h_CallResultCPU = (float *)malloc(options_size);
h_PutResultCPU = (float *)malloc(options_size);
h_CallResultGPU = (float *)malloc(options_size);
h_PutResultGPU = (float *)malloc(options_size);
h_StockPrice = (float *)malloc(options_size);
h_OptionStrike = (float *)malloc(options_size);
h_OptionYears = (float *)malloc(options_size);
// GPU memory allocation
hipMalloc((void **)&d_CallResult, options_size);
hipMalloc((void **)&d_PutResult, options_size);
hipMalloc((void **)&d_StockPrice, options_size);
hipMalloc((void **)&d_OptionStrike, options_size);
hipMalloc((void **)&d_OptionYears, options_size);
srand(5347);
// Generate options set
for (i = 0; i < options; i++)
{
h_CallResultCPU[i] = 0.0f;
h_PutResultCPU[i] = -1.0f;
h_StockPrice[i] = RandFloat(5.0f, 30.0f);
h_OptionStrike[i] = RandFloat(1.0f, 100.0f);
h_OptionYears[i] = RandFloat(0.25f, 10.0f);
}
// Copy options data to GPU memory for further processing
hipMemcpy(d_StockPrice, h_StockPrice, options_size, hipMemcpyHostToDevice);
hipMemcpy(d_OptionStrike, h_OptionStrike, options_size, hipMemcpyHostToDevice);
hipMemcpy(d_OptionYears, h_OptionYears, options_size, hipMemcpyHostToDevice);
hipDeviceSynchronize();
timeval starttime, endtime;
double runtime;
if (gpu) {
gettimeofday(&starttime, NULL);
for (i = 0; i < NUM_ITERATIONS; i++) {
BlackScholesGPU<<<DIV_UP(options, 128), 128>>>(
d_CallResult,
d_PutResult,
d_StockPrice,
d_OptionStrike,
d_OptionYears,
RISKFREE,
VOLATILITY,
options
);
}
hipDeviceSynchronize();
gettimeofday(&endtime, NULL);
}
else {
gettimeofday(&starttime, NULL);
//Calculate options values on CPU
BlackScholesCPU(
h_CallResultCPU,
h_PutResultCPU,
h_StockPrice,
h_OptionStrike,
h_OptionYears,
RISKFREE,
VOLATILITY,
options
);
gettimeofday(&endtime, NULL);
}
// Read back GPU results to compare them to CPU results
hipMemcpy(h_CallResultGPU, d_CallResult, options_size, hipMemcpyDeviceToHost);
hipMemcpy(h_PutResultGPU, d_PutResult, options_size, hipMemcpyDeviceToHost);
runtime = endtime.tv_sec + endtime.tv_usec / 1000000.0 - (starttime.tv_sec + starttime.tv_usec / 1000000.0);
fprintf(stdout, "\033[1;32m[wk3] compute time = %.3f s\n\033[0m", runtime);
#ifdef VERIFY
printf("%3.5f,%3.5f\n", h_CallResultGPU[2047],h_PutResultGPU[3145]);
#endif
// validation not use; code is running on either GPU or CPU
sum_delta = 0;
sum_ref = 0;
max_delta = 0;
for (i = 0; i < options; i++)
{
ref = h_CallResultCPU[i];
delta = fabs(h_CallResultCPU[i] - h_CallResultGPU[i]);
if (delta > max_delta)
{
max_delta = delta;
}
sum_delta += delta;
sum_ref += fabs(ref);
}
L1norm = sum_delta / sum_ref;
hipFree(d_OptionYears);
hipFree(d_OptionStrike);
hipFree(d_StockPrice);
hipFree(d_PutResult);
hipFree(d_CallResult);
free(h_OptionYears);
free(h_OptionStrike);
free(h_StockPrice);
free(h_PutResultGPU);
free(h_CallResultGPU);
free(h_PutResultCPU);
free(h_CallResultCPU);
if (L1norm > 1e-6)
{
exit(EXIT_FAILURE);
}
exit(EXIT_SUCCESS);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15BlackScholesGPUPfS_S_S_S_ffi
.globl _Z15BlackScholesGPUPfS_S_S_S_ffi
.p2align 8
.type _Z15BlackScholesGPUPfS_S_S_S_ffi,@function
_Z15BlackScholesGPUPfS_S_S_S_ffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b128 s[0:3], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_div_scale_f32 v3, null, v4, v4, v6
v_div_scale_f32 v8, vcc_lo, v6, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v3, v5, 1.0
v_fmac_f32_e32 v5, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v5
v_fma_f32 v9, -v3, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v5
v_fma_f32 v3, -v3, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v3, v5, v7
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_div_fixup_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v2, v5, vcc_lo
v_cmp_gt_f32_e64 s0, 0x800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sqrt_f32_e32 v8, v5
v_cndmask_b32_e64 v7, 1.0, 0x4f800000, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, v3, v7
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v8
v_add_nc_u32_e32 v9, 1, v8
v_log_f32_e32 v3, v3
v_fma_f32 v10, -v7, v8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v9, v8, v5
v_cmp_ge_f32_e64 s1, 0, v10
v_mul_f32_e64 v10, s3, 0.5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x3f317217, v3
v_cndmask_b32_e64 v7, v8, v7, s1
v_cmp_lt_f32_e64 s1, 0, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v8, v3, 0x3f317217, -v12
v_cndmask_b32_e64 v7, v7, v9, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v8, v3, 0x3377d1cf, v8
v_mul_f32_e32 v9, 0x37800000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v8, 0x3f317217, v3 :: v_dual_cndmask_b32 v7, v7, v9
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
v_cndmask_b32_e64 v9, 0, 0x41b17218, s0
v_cndmask_b32_e32 v3, v3, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v5, 0x260
v_fma_f32 v8, v10, s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v3, v9
v_cndmask_b32_e32 v5, v7, v5, vcc_lo
v_fmac_f32_e32 v3, v8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v7, s3, v5
v_mul_f32_e64 v2, v2, -s2
v_div_scale_f32 v8, null, v7, v7, v3
v_div_scale_f32 v11, vcc_lo, v3, v7, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v2, 0x3fb8aa3b, v2
v_rcp_f32_e32 v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v8, v9, 1.0
v_dual_mul_f32 v4, v4, v2 :: v_dual_fmac_f32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v11, v9
v_fma_f32 v12, -v8, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v12, v9
v_fma_f32 v8, -v8, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v8, v8, v9, v10
v_div_fixup_f32 v3, v8, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, s3, v3
v_fma_f32 v7, |v3|, 0x3e6d3389, 1.0
v_fma_f32 v8, |v5|, 0x3e6d3389, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v9, null, v7, v7, 1.0
v_div_scale_f32 v15, vcc_lo, 1.0, v7, 1.0
v_div_scale_f32 v10, null, v8, v8, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v9
v_rcp_f32_e32 v12, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v9, v11, 1.0
v_fma_f32 v14, -v10, v12, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v13, v11
v_div_scale_f32 v13, s0, 1.0, v8, 1.0
v_fmac_f32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v14, v15, v11
v_mul_f32_e32 v16, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, -v9, v14, v15
v_fma_f32 v18, -v10, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v17, v11
v_fmac_f32_e32 v16, v18, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v9, v14, v15
v_fma_f32 v10, -v10, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f32 v9, v9, v11, v14
s_mov_b32 vcc_lo, s0
s_mov_b32 s0, 0x3faa466f
v_div_fmas_f32 v10, v10, v12, v16
v_cmp_lt_f32_e32 vcc_lo, 0, v3
v_div_fixup_f32 v7, v9, v7, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v8, v10, v8, 1.0
v_fmaak_f32 v12, s0, v8, 0xbfe91eea
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v12, v8, v12, 0x3fe40778
v_dual_fmaak_f32 v12, v8, v12, 0xbeb68f87 :: v_dual_mul_f32 v11, -0.5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v12, v8, v12, 0x3ea385fa
v_mul_f32_e32 v10, v3, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmaak_f32 v11, s0, v7, 0xbfe91eea :: v_dual_mul_f32 v8, v8, v12
v_mul_f32_e32 v10, 0x3fb8aa3b, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v11, v7, v11, 0x3fe40778
v_exp_f32_e32 v10, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v11, v7, v11, 0xbeb68f87
v_mul_f32_e32 v9, -0.5, v5
v_fmaak_f32 v11, v7, v11, 0x3ea385fa
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v10, 0x3ecc422a, v10 :: v_dual_mul_f32 v7, v7, v11
v_mul_f32_e32 v9, v5, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v10, v7
v_fma_f32 v7, -v10, v7, 1.0
v_cndmask_b32_e32 v7, v11, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, 0x3fb8aa3b, v9
v_cmp_lt_f32_e32 vcc_lo, 0, v5
v_exp_f32_e32 v9, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x3ecc422a, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v8, -v9, v8, 1.0
v_dual_cndmask_b32 v5, v10, v8 :: v_dual_sub_f32 v8, 1.0, v7
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v9, v4, v5
v_dual_sub_f32 v5, 1.0, v5 :: v_dual_mul_f32 v8, v6, v8
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v6, v6, v7, -v9
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_fma_f32 v4, v4, v5, -v8
global_store_b32 v[2:3], v6, off
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15BlackScholesGPUPfS_S_S_S_ffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15BlackScholesGPUPfS_S_S_S_ffi, .Lfunc_end0-_Z15BlackScholesGPUPfS_S_S_S_ffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15BlackScholesGPUPfS_S_S_S_ffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15BlackScholesGPUPfS_S_S_S_ffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 1993-2015 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*
*/
/*
* Code to simulate a GPU workload for lab assignment in [A2] Task Mapping on Soft Heterogeneous Systems.
* Workload consists of a the Black-Scholes kernel taken from NVIDIA SDK 10.1
*
* Computation is done on the GPU when the user selects a core attached to a GPU; otherwise the code is run on
* the CPU. GPU version of the code is expected to run faster.
*
* @author: Apan Qasem <apan@txstate.edu>
* @date: 04/02/20
*
* @update: 03/12/21
*/
#include <hip/hip_runtime.h>
#include<cstdio>
#include<sys/time.h>
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
static double CND(double d)
{
const double A1 = 0.31938153;
const double A2 = -0.356563782;
const double A3 = 1.781477937;
const double A4 = -1.821255978;
const double A5 = 1.330274429;
const double RSQRT2PI = 0.39894228040143267793994605993438;
double
K = 1.0 / (1.0 + 0.2316419 * fabs(d));
double
cnd = RSQRT2PI * exp(- 0.5 * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0 - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
static void BlackScholesBodyCPU(
float &callResult,
float &putResult,
float Sf, //Stock price
float Xf, //Option strike
float Tf, //Option years
float Rf, //Riskless rate
float Vf //Volatility rate
)
{
double S = Sf, X = Xf, T = Tf, R = Rf, V = Vf;
double sqrtT = sqrt(T);
double d1 = (log(S / X) + (R + 0.5 * V * V) * T) / (V * sqrtT);
double d2 = d1 - V * sqrtT;
double CNDD1 = CND(d1);
double CNDD2 = CND(d2);
//Calculate Call and Put simultaneously
double expRT = exp(- R * T);
callResult = (float)(S * CNDD1 - X * expRT * CNDD2);
putResult = (float)(X * expRT * (1.0 - CNDD2) - S * (1.0 - CNDD1));
}
////////////////////////////////////////////////////////////////////////////////
// Process an array of optN options
////////////////////////////////////////////////////////////////////////////////
void BlackScholesCPU(
float *h_CallResult,
float *h_PutResult,
float *h_StockPrice,
float *h_OptionStrike,
float *h_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
for (int opt = 0; opt < optN; opt++)
BlackScholesBodyCPU(
h_CallResult[opt],
h_PutResult[opt],
h_StockPrice[opt],
h_OptionStrike[opt],
h_OptionYears[opt],
Riskfree,
Volatility
);
}
// extern "C" void BlackScholesCPU(
// float *h_CallResult,
// float *h_PutResult,
// float *h_StockPrice,
// float *h_OptionStrike,
// float *h_OptionYears,
// float Riskfree,
// float Volatility,
// int optN
// );
////////////////////////////////////////////////////////////////////////////////
// Process an array of OptN options on GPU
////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Polynomial approximation of cumulative normal distribution function
///////////////////////////////////////////////////////////////////////////////
__device__ inline float cndGPU(float d)
{
const float A1 = 0.31938153f;
const float A2 = -0.356563782f;
const float A3 = 1.781477937f;
const float A4 = -1.821255978f;
const float A5 = 1.330274429f;
const float RSQRT2PI = 0.39894228040143267793994605993438f;
float
K = 1.0f / (1.0f + 0.2316419f * fabsf(d));
float
cnd = RSQRT2PI * __expf(- 0.5f * d * d) *
(K * (A1 + K * (A2 + K * (A3 + K * (A4 + K * A5)))));
if (d > 0)
cnd = 1.0f - cnd;
return cnd;
}
///////////////////////////////////////////////////////////////////////////////
// Black-Scholes formula for both call and put
///////////////////////////////////////////////////////////////////////////////
__device__ inline void BlackScholesBodyGPU(
float &CallResult,
float &PutResult,
float S, //Stock price
float X, //Option strike
float T, //Option years
float R, //Riskless rate
float V //Volatility rate
)
{
float sqrtT, expRT;
float d1, d2, CNDD1, CNDD2;
sqrtT = sqrtf(T);
d1 = (__logf(S / X) + (R + 0.5f * V * V) * T) / (V * sqrtT);
d2 = d1 - V * sqrtT;
CNDD1 = cndGPU(d1);
CNDD2 = cndGPU(d2);
//Calculate Call and Put simultaneously
expRT = __expf(- R * T);
CallResult = S * CNDD1 - X * expRT * CNDD2;
PutResult = X * expRT * (1.0f - CNDD2) - S * (1.0f - CNDD1);
}
////////////////////////////////////////////////////////////////////////////////
//Process an array of optN options on GPU
////////////////////////////////////////////////////////////////////////////////
__global__ void BlackScholesGPU(
float *d_CallResult,
float *d_PutResult,
float *d_StockPrice,
float *d_OptionStrike,
float *d_OptionYears,
float Riskfree,
float Volatility,
int optN
)
{
////Thread index
//const int tid = blockDim.x * blockIdx.x + threadIdx.x;
////Total number of threads in execution grid
//const int THREAD_N = blockDim.x * gridDim.x;
const int opt = blockDim.x * blockIdx.x + threadIdx.x;
//No matter how small is execution grid or how large OptN is,
//exactly OptN indices will be processed with perfect memory coalescing
//for (int opt = tid; opt < optN; opt += THREAD_N)
if (opt < optN)
BlackScholesBodyGPU(
d_CallResult[opt],
d_PutResult[opt],
d_StockPrice[opt],
d_OptionStrike[opt],
d_OptionYears[opt],
Riskfree,
Volatility
);
}
////////////////////////////////////////////////////////////////////////////////
// Helper function, returning uniformly distributed
// random float in [low, high] range
////////////////////////////////////////////////////////////////////////////////
float RandFloat(float low, float high)
{
float t = (float)rand() / (float)RAND_MAX;
return (1.0f - t) * low + t * high;
}
////////////////////////////////////////////////////////////////////////////////
// Data configuration
////////////////////////////////////////////////////////////////////////////////
const int NUM_ITERATIONS = 512;
const float RISKFREE = 0.02f;
const float VOLATILITY = 0.30f;
#define DIV_UP(a, b) ( ((a) + (b) - 1) / (b) )
////////////////////////////////////////////////////////////////////////////////
// Main program
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char **argv) {
if (argc < 3) {
fprintf(stderr, "usage: ./blackscholes options GPU\n");
exit(0);
}
unsigned options = atoi(argv[1]);
int options_size = options * sizeof(float);
unsigned gpu = atoi(argv[2]);
float
*h_CallResultCPU,
*h_PutResultCPU,
*h_CallResultGPU,
*h_PutResultGPU,
*h_StockPrice,
*h_OptionStrike,
*h_OptionYears;
float
*d_CallResult,
*d_PutResult,
*d_StockPrice,
*d_OptionStrike,
*d_OptionYears;
double delta, ref, sum_delta, sum_ref, max_delta, L1norm;
int i;
// CPU memory allocation
h_CallResultCPU = (float *)malloc(options_size);
h_PutResultCPU = (float *)malloc(options_size);
h_CallResultGPU = (float *)malloc(options_size);
h_PutResultGPU = (float *)malloc(options_size);
h_StockPrice = (float *)malloc(options_size);
h_OptionStrike = (float *)malloc(options_size);
h_OptionYears = (float *)malloc(options_size);
// GPU memory allocation
hipMalloc((void **)&d_CallResult, options_size);
hipMalloc((void **)&d_PutResult, options_size);
hipMalloc((void **)&d_StockPrice, options_size);
hipMalloc((void **)&d_OptionStrike, options_size);
hipMalloc((void **)&d_OptionYears, options_size);
srand(5347);
// Generate options set
for (i = 0; i < options; i++)
{
h_CallResultCPU[i] = 0.0f;
h_PutResultCPU[i] = -1.0f;
h_StockPrice[i] = RandFloat(5.0f, 30.0f);
h_OptionStrike[i] = RandFloat(1.0f, 100.0f);
h_OptionYears[i] = RandFloat(0.25f, 10.0f);
}
// Copy options data to GPU memory for further processing
hipMemcpy(d_StockPrice, h_StockPrice, options_size, hipMemcpyHostToDevice);
hipMemcpy(d_OptionStrike, h_OptionStrike, options_size, hipMemcpyHostToDevice);
hipMemcpy(d_OptionYears, h_OptionYears, options_size, hipMemcpyHostToDevice);
hipDeviceSynchronize();
timeval starttime, endtime;
double runtime;
if (gpu) {
gettimeofday(&starttime, NULL);
for (i = 0; i < NUM_ITERATIONS; i++) {
BlackScholesGPU<<<DIV_UP(options, 128), 128>>>(
d_CallResult,
d_PutResult,
d_StockPrice,
d_OptionStrike,
d_OptionYears,
RISKFREE,
VOLATILITY,
options
);
}
hipDeviceSynchronize();
gettimeofday(&endtime, NULL);
}
else {
gettimeofday(&starttime, NULL);
//Calculate options values on CPU
BlackScholesCPU(
h_CallResultCPU,
h_PutResultCPU,
h_StockPrice,
h_OptionStrike,
h_OptionYears,
RISKFREE,
VOLATILITY,
options
);
gettimeofday(&endtime, NULL);
}
// Read back GPU results to compare them to CPU results
hipMemcpy(h_CallResultGPU, d_CallResult, options_size, hipMemcpyDeviceToHost);
hipMemcpy(h_PutResultGPU, d_PutResult, options_size, hipMemcpyDeviceToHost);
runtime = endtime.tv_sec + endtime.tv_usec / 1000000.0 - (starttime.tv_sec + starttime.tv_usec / 1000000.0);
fprintf(stdout, "\033[1;32m[wk3] compute time = %.3f s\n\033[0m", runtime);
#ifdef VERIFY
printf("%3.5f,%3.5f\n", h_CallResultGPU[2047],h_PutResultGPU[3145]);
#endif
// validation not use; code is running on either GPU or CPU
sum_delta = 0;
sum_ref = 0;
max_delta = 0;
for (i = 0; i < options; i++)
{
ref = h_CallResultCPU[i];
delta = fabs(h_CallResultCPU[i] - h_CallResultGPU[i]);
if (delta > max_delta)
{
max_delta = delta;
}
sum_delta += delta;
sum_ref += fabs(ref);
}
L1norm = sum_delta / sum_ref;
hipFree(d_OptionYears);
hipFree(d_OptionStrike);
hipFree(d_StockPrice);
hipFree(d_PutResult);
hipFree(d_CallResult);
free(h_OptionYears);
free(h_OptionStrike);
free(h_StockPrice);
free(h_PutResultGPU);
free(h_CallResultGPU);
free(h_PutResultCPU);
free(h_CallResultCPU);
if (L1norm > 1e-6)
{
exit(EXIT_FAILURE);
}
exit(EXIT_SUCCESS);
} | .text
.file "gpu_wkld.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z15BlackScholesCPUPfS_S_S_S_ffi
.LCPI0_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI0_3:
.quad 0x3fcda6711871100e # double 0.23164190000000001
.LCPI0_4:
.quad 0x3ff0000000000000 # double 1
.LCPI0_5:
.quad 0xbfe0000000000000 # double -0.5
.LCPI0_6:
.quad 0x3fd9884533d43651 # double 0.3989422804014327
.LCPI0_7:
.quad 0x3ff548cdd6f42943 # double 1.3302744289999999
.LCPI0_8:
.quad 0xbffd23dd4ef278d0 # double -1.8212559779999999
.LCPI0_9:
.quad 0x3ffc80ef025f5e68 # double 1.781477937
.LCPI0_10:
.quad 0xbfd6d1f0e5a8325b # double -0.356563782
.LCPI0_11:
.quad 0x3fd470bf3a92f8ec # double 0.31938153000000002
.LCPI0_12:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.LCPI0_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z15BlackScholesCPUPfS_S_S_S_ffi
.p2align 4, 0x90
.type _Z15BlackScholesCPUPfS_S_S_S_ffi,@function
_Z15BlackScholesCPUPfS_S_S_S_ffi: # @_Z15BlackScholesCPUPfS_S_S_S_ffi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 88(%rsp) # 8-byte Spill
testl %r9d, %r9d
jle .LBB0_6
# %bb.1: # %.lr.ph
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm1, %xmm2
movsd %xmm1, 80(%rsp) # 8-byte Spill
mulsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 72(%rsp) # 8-byte Spill
xorps .LCPI0_1(%rip), %xmm0
movaps %xmm0, 96(%rsp) # 16-byte Spill
movl %r9d, %ebp
xorl %ebx, %ebx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
sqrtsd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
.LBB0_5: # %.split
# in Loop: Header=BB0_2 Depth=1
movaps %xmm3, %xmm0
divsd %xmm1, %xmm0
callq log
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd 40(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm0, %xmm2
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd 80(%rsp), %xmm1 # 8-byte Folded Reload
divsd %xmm1, %xmm2
movapd %xmm2, 48(%rsp) # 16-byte Spill
movapd %xmm2, %xmm0
subsd %xmm1, %xmm0
movapd %xmm0, (%rsp) # 16-byte Spill
movapd %xmm2, %xmm0
movapd .LCPI0_2(%rip), %xmm1 # xmm1 = [NaN,NaN]
andpd %xmm1, %xmm0
movsd .LCPI0_3(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI0_4(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
movsd .LCPI0_5(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
callq exp
movsd .LCPI0_6(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd 16(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movapd %xmm3, %xmm1
movsd .LCPI0_7(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
movsd .LCPI0_8(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
movsd .LCPI0_9(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
movsd .LCPI0_10(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
movsd .LCPI0_11(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
mulsd %xmm0, %xmm1
movsd .LCPI0_4(%rip), %xmm4 # xmm4 = mem[0],zero
movapd %xmm4, %xmm0
subsd %xmm1, %xmm0
xorpd %xmm3, %xmm3
cmpltsd 48(%rsp), %xmm3 # 16-byte Folded Reload
movapd %xmm3, %xmm2
andnpd %xmm1, %xmm2
andpd %xmm0, %xmm3
orpd %xmm2, %xmm3
movapd %xmm3, 48(%rsp) # 16-byte Spill
movapd (%rsp), %xmm2 # 16-byte Reload
movapd %xmm2, %xmm0
andpd .LCPI0_2(%rip), %xmm0
mulsd .LCPI0_3(%rip), %xmm0
movapd %xmm4, %xmm1
addsd %xmm4, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
mulsd .LCPI0_5(%rip), %xmm0
mulsd %xmm2, %xmm0
callq exp
mulsd .LCPI0_6(%rip), %xmm0
movsd 16(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movapd %xmm2, %xmm1
mulsd .LCPI0_7(%rip), %xmm1
addsd .LCPI0_8(%rip), %xmm1
mulsd %xmm2, %xmm1
addsd .LCPI0_9(%rip), %xmm1
mulsd %xmm2, %xmm1
addsd .LCPI0_10(%rip), %xmm1
mulsd %xmm2, %xmm1
addsd .LCPI0_11(%rip), %xmm1
mulsd %xmm2, %xmm1
mulsd %xmm0, %xmm1
movsd .LCPI0_4(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm1, %xmm0
xorpd %xmm3, %xmm3
cmpltsd (%rsp), %xmm3 # 16-byte Folded Reload
movapd %xmm3, %xmm2
andnpd %xmm1, %xmm2
andpd %xmm0, %xmm3
orpd %xmm2, %xmm3
movapd %xmm3, (%rsp) # 16-byte Spill
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd 96(%rsp), %xmm0 # 16-byte Folded Reload
callq exp
movsd .LCPI0_4(%rip), %xmm5 # xmm5 = mem[0],zero
movapd %xmm5, %xmm1
movapd 48(%rsp), %xmm2 # 16-byte Reload
subsd %xmm2, %xmm1
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
movapd %xmm2, %xmm4
mulsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movapd %xmm5, %xmm2
movapd (%rsp), %xmm5 # 16-byte Reload
subsd %xmm5, %xmm2
mulsd %xmm0, %xmm2
mulsd %xmm5, %xmm0
subsd %xmm0, %xmm4
xorps %xmm0, %xmm0
cvtsd2ss %xmm4, %xmm0
mulsd %xmm3, %xmm1
subsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
movss %xmm0, (%r13,%rbx,4)
movss %xmm1, (%r12,%rbx,4)
incq %rbx
cmpq %rbx, %rbp
je .LBB0_6
.LBB0_2: # =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq 88(%rsp), %rax # 8-byte Reload
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
xorps %xmm3, %xmm3
cvtss2sd %xmm0, %xmm3
cvtss2sd %xmm1, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
ucomisd .LCPI0_12(%rip), %xmm0
movsd %xmm3, 32(%rsp) # 8-byte Spill
movsd %xmm1, 24(%rsp) # 8-byte Spill
movsd %xmm0, 40(%rsp) # 8-byte Spill
jae .LBB0_3
# %bb.4: # %call.sqrt
# in Loop: Header=BB0_2 Depth=1
callq sqrt
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
jmp .LBB0_5
.LBB0_6: # %._crit_edge
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15BlackScholesCPUPfS_S_S_S_ffi, .Lfunc_end0-_Z15BlackScholesCPUPfS_S_S_S_ffi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi # -- Begin function _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.p2align 4, 0x90
.type _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi,@function
_Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi: # @_Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15BlackScholesGPUPfS_S_S_S_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi, .Lfunc_end1-_Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9RandFloatff
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f800000 # float 1
.text
.globl _Z9RandFloatff
.p2align 4, 0x90
.type _Z9RandFloatff,@function
_Z9RandFloatff: # @_Z9RandFloatff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss (%rsp), %xmm1 # 4-byte Folded Reload
mulss 4(%rsp), %xmm0 # 4-byte Folded Reload
addss %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9RandFloatff, .Lfunc_end2-_Z9RandFloatff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x3f800000 # float 1
.LCPI3_2:
.long 0x40a00000 # float 5
.LCPI3_3:
.long 0x41f00000 # float 30
.LCPI3_4:
.long 0x42c80000 # float 100
.LCPI3_5:
.long 0x3e800000 # float 0.25
.LCPI3_6:
.long 0x41200000 # float 10
.LCPI3_7:
.long 0x3ca3d70a # float 0.0199999996
.LCPI3_8:
.long 0x3e99999a # float 0.300000012
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_9:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_11:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_10:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jg .LBB3_1
# %bb.17:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.LBB3_1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
leal (,%rax,4), %ebp
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 104(%rsp) # 8-byte Spill
movslq %ebp, %r15
movq %r15, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, 128(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %rbp
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, 88(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movl $5347, %edi # imm = 0x14E3
callq srand
movq %r14, 8(%rsp) # 8-byte Spill
testl %r14d, %r14d
je .LBB3_4
# %bb.2: # %.lr.ph.preheader
movl 8(%rsp), %r14d # 4-byte Reload
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movl $0, (%rax,%r15,4)
movl $-1082130432, (%rbx,%r15,4) # imm = 0xBF800000
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss .LCPI3_2(%rip), %xmm1
mulss .LCPI3_3(%rip), %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%r12,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss .LCPI3_4(%rip), %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%r13,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss .LCPI3_5(%rip), %xmm1
mulss .LCPI3_6(%rip), %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%rbp,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_3
.LBB3_4: # %._crit_edge
movq %rbx, 80(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movq %r12, %rsi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leaq 296(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cmpl $0, 104(%rsp) # 4-byte Folded Reload
movq %r12, 120(%rsp) # 8-byte Spill
movq %r13, 112(%rsp) # 8-byte Spill
jne .LBB3_5
# %bb.10:
movq %r12, %rdx
movss .LCPI3_7(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI3_8(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq 16(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r13, %rcx
movq %rbp, %r12
movq %rbp, %r8
movq 8(%rsp), %r13 # 8-byte Reload
movl %r13d, %r9d
callq _Z15BlackScholesCPUPfS_S_S_S_ffi
jmp .LBB3_11
.LBB3_5:
movq %rbp, %r12
movabsq $4294967296, %r14 # imm = 0x100000000
movq 8(%rsp), %rax # 8-byte Reload
leal 127(%rax), %r15d
shrl $7, %r15d
orq %r14, %r15
movl $512, %r13d # imm = 0x200
subq $-128, %r14
leaq 216(%rsp), %rbp
movq 16(%rsp), %rbx # 8-byte Reload
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
decl %r13d
je .LBB3_9
.LBB3_6: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=1
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movq %rsi, 192(%rsp)
movq %rdi, 184(%rsp)
movl $1017370378, 76(%rsp) # imm = 0x3CA3D70A
movl $1050253722, 72(%rsp) # imm = 0x3E99999A
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 68(%rsp)
movq %rbp, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 192(%rsp), %rax
movq %rax, 248(%rsp)
leaq 184(%rsp), %rax
movq %rax, 256(%rsp)
leaq 76(%rsp), %rax
movq %rax, 264(%rsp)
leaq 72(%rsp), %rax
movq %rax, 272(%rsp)
leaq 68(%rsp), %rax
movq %rax, 280(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movl $_Z15BlackScholesGPUPfS_S_S_S_ffi, %edi
leaq 224(%rsp), %r9
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_8
.LBB3_9:
callq hipDeviceSynchronize
movq 8(%rsp), %r13 # 8-byte Reload
.LBB3_11:
xorl %r14d, %r14d
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %rsi
movq 128(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 88(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movq 96(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
cvtsi2sdq 224(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 232(%rsp), %xmm0
movsd .LCPI3_9(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 296(%rsp), %xmm1
cvtsi2sdq 304(%rsp), %xmm3
divsd %xmm2, %xmm3
addsd %xmm1, %xmm3
subsd %xmm3, %xmm0
movq stdout(%rip), %rdi
movl $.L.str.1, %esi
movb $1, %al
callq fprintf
testl %r13d, %r13d
je .LBB3_15
# %bb.12: # %.lr.ph95.preheader
movl %r13d, %eax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
movaps .LCPI3_10(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorpd %xmm2, %xmm2
.p2align 4, 0x90
.LBB3_13: # %.lr.ph95
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm3, %xmm4
subss (%r15,%rcx,4), %xmm4
andps %xmm1, %xmm4
cvtss2sd %xmm4, %xmm4
addsd %xmm4, %xmm0
andps %xmm1, %xmm3
cvtss2sd %xmm3, %xmm3
addsd %xmm3, %xmm2
incq %rcx
cmpq %rcx, %rax
jne .LBB3_13
# %bb.14: # %._crit_edge96.loopexit
divsd %xmm2, %xmm0
ucomisd .LCPI3_11(%rip), %xmm0
seta %r14b
.LBB3_15: # %._crit_edge96
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq 120(%rsp), %rdi # 8-byte Reload
callq free
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
testb %r14b, %r14b
je .LBB3_16
# %bb.18:
movl $1, %edi
callq exit
.LBB3_16:
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15BlackScholesGPUPfS_S_S_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15BlackScholesGPUPfS_S_S_S_ffi,@object # @_Z15BlackScholesGPUPfS_S_S_S_ffi
.section .rodata,"a",@progbits
.globl _Z15BlackScholesGPUPfS_S_S_S_ffi
.p2align 3, 0x0
_Z15BlackScholesGPUPfS_S_S_S_ffi:
.quad _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.size _Z15BlackScholesGPUPfS_S_S_S_ffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: ./blackscholes options GPU\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\033[1
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15BlackScholesGPUPfS_S_S_S_ffi"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15BlackScholesGPUPfS_S_S_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b8e25_00000000-6_gpu_wkld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL3CNDd, @function
_ZL3CNDd:
.LFB2057:
.cfi_startproc
subq $24, %rsp
.cfi_def_cfa_offset 32
movapd %xmm0, %xmm3
andpd .LC0(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
movsd .LC2(%rip), %xmm1
addsd %xmm1, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, (%rsp)
movapd %xmm3, %xmm0
mulsd .LC3(%rip), %xmm0
movsd %xmm3, 8(%rsp)
mulsd %xmm3, %xmm0
call exp@PLT
movapd %xmm0, %xmm1
movsd (%rsp), %xmm2
movapd %xmm2, %xmm0
mulsd .LC4(%rip), %xmm0
subsd .LC5(%rip), %xmm0
mulsd %xmm2, %xmm0
addsd .LC6(%rip), %xmm0
mulsd %xmm2, %xmm0
subsd .LC7(%rip), %xmm0
mulsd %xmm2, %xmm0
addsd .LC8(%rip), %xmm0
mulsd %xmm2, %xmm0
mulsd .LC9(%rip), %xmm1
mulsd %xmm1, %xmm0
pxor %xmm1, %xmm1
movsd 8(%rsp), %xmm3
comisd %xmm1, %xmm3
jbe .L1
movsd .LC2(%rip), %xmm1
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
.L1:
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL3CNDd, .-_ZL3CNDd
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15BlackScholesCPUPfS_S_S_S_ffi
.type _Z15BlackScholesCPUPfS_S_S_S_ffi, @function
_Z15BlackScholesCPUPfS_S_S_S_ffi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 48(%rsp)
testl %r9d, %r9d
jle .L8
movq %rsi, %r15
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movslq %r9d, %r9
leaq 0(,%r9,4), %rbp
movl $0, %ebx
pxor %xmm6, %xmm6
cvtss2sd %xmm0, %xmm6
movsd %xmm6, 56(%rsp)
pxor %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movsd %xmm2, 64(%rsp)
xorpd .LC12(%rip), %xmm6
movsd %xmm6, 72(%rsp)
.L13:
pxor %xmm3, %xmm3
cvtss2sd (%r12,%rbx), %xmm3
movsd %xmm3, 16(%rsp)
pxor %xmm3, %xmm3
cvtss2sd 0(%r13,%rbx), %xmm3
movsd %xmm3, 24(%rsp)
pxor %xmm5, %xmm5
cvtss2sd (%r14,%rbx), %xmm5
movsd %xmm5, 8(%rsp)
pxor %xmm0, %xmm0
ucomisd %xmm5, %xmm0
ja .L16
sqrtsd %xmm5, %xmm5
movsd %xmm5, 32(%rsp)
.L12:
movsd 16(%rsp), %xmm0
divsd 24(%rsp), %xmm0
call log@PLT
movapd %xmm0, %xmm2
movsd 32(%rsp), %xmm1
movsd 64(%rsp), %xmm7
mulsd %xmm7, %xmm1
movsd .LC11(%rip), %xmm4
mulsd %xmm7, %xmm4
movapd %xmm4, %xmm0
mulsd %xmm7, %xmm0
addsd 56(%rsp), %xmm0
mulsd 8(%rsp), %xmm0
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
movapd %xmm0, %xmm7
subsd %xmm1, %xmm7
movsd %xmm7, 32(%rsp)
call _ZL3CNDd
movsd %xmm0, 40(%rsp)
movsd 32(%rsp), %xmm0
call _ZL3CNDd
movsd %xmm0, 32(%rsp)
movsd 8(%rsp), %xmm4
mulsd 72(%rsp), %xmm4
movapd %xmm4, %xmm0
call exp@PLT
movsd 24(%rsp), %xmm2
mulsd %xmm0, %xmm2
movsd 16(%rsp), %xmm3
movapd %xmm3, %xmm4
movsd 40(%rsp), %xmm5
mulsd %xmm5, %xmm4
movapd %xmm4, %xmm0
movsd 32(%rsp), %xmm6
movapd %xmm6, %xmm1
mulsd %xmm2, %xmm1
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%rbx)
movsd .LC2(%rip), %xmm1
movapd %xmm1, %xmm0
subsd %xmm6, %xmm0
mulsd %xmm2, %xmm0
subsd %xmm5, %xmm1
mulsd %xmm3, %xmm1
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
.L8:
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movsd 8(%rsp), %xmm0
call sqrt@PLT
movsd %xmm0, 32(%rsp)
jmp .L12
.cfi_endproc
.LFE2059:
.size _Z15BlackScholesCPUPfS_S_S_S_ffi, .-_Z15BlackScholesCPUPfS_S_S_S_ffi
.globl _Z9RandFloatff
.type _Z9RandFloatff, @function
_Z9RandFloatff:
.LFB2062:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss %xmm0, 8(%rsp)
movss %xmm1, 12(%rsp)
call rand@PLT
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
mulss .LC13(%rip), %xmm1
movss .LC14(%rip), %xmm0
subss %xmm1, %xmm0
mulss 8(%rsp), %xmm0
mulss 12(%rsp), %xmm1
addss %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9RandFloatff, .-_Z9RandFloatff
.globl _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
.type _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi, @function
_Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi:
.LFB2088:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z15BlackScholesGPUPfS_S_S_S_ffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi, .-_Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
.globl _Z15BlackScholesGPUPfS_S_S_S_ffi
.type _Z15BlackScholesGPUPfS_S_S_S_ffi, @function
_Z15BlackScholesGPUPfS_S_S_S_ffi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z15BlackScholesGPUPfS_S_S_S_ffi, .-_Z15BlackScholesGPUPfS_S_S_S_ffi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC15:
.string "usage: ./blackscholes options GPU\n"
.align 8
.LC26:
.string "\033[1;32m[wk3] compute time = %.3f s\n\033[0m"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $200, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
cmpl $2, %edi
jg .L29
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.L29:
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 48(%rsp)
movl %eax, %r14d
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 56(%rsp)
leal 0(,%r15,4), %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $5347, %edi
call srand@PLT
testl %r14d, %r14d
je .L30
movl %r14d, %r13d
movl $0, %ebx
movq %r12, 64(%rsp)
movq 16(%rsp), %r12
movl %r14d, 76(%rsp)
movq 24(%rsp), %r14
.L31:
movl $0x00000000, 0(%rbp,%rbx,4)
movq 8(%rsp), %rax
movl $0xbf800000, (%rax,%rbx,4)
movss .LC18(%rip), %xmm1
movss .LC19(%rip), %xmm0
call _Z9RandFloatff
movss %xmm0, (%r15,%rbx,4)
movss .LC20(%rip), %xmm1
movss .LC14(%rip), %xmm0
call _Z9RandFloatff
movss %xmm0, (%r12,%rbx,4)
movss .LC21(%rip), %xmm1
movss .LC22(%rip), %xmm0
call _Z9RandFloatff
movss %xmm0, (%r14,%rbx,4)
addq $1, %rbx
cmpq %r13, %rbx
jne .L31
movq 64(%rsp), %r12
movl 76(%rsp), %r14d
.L30:
movl $1, %ecx
movq %r12, %rdx
movq %r15, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
cmpl $0, 56(%rsp)
je .L32
leaq 144(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 48(%rsp), %eax
leal 127(%rax), %r13d
shrl $7, %r13d
movl $512, %ebx
jmp .L34
.L33:
subl $1, %ebx
je .L50
.L34:
movl $128, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl %r13d, 132(%rsp)
movl $1, 136(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 132(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %r14d, %r9d
movss .LC23(%rip), %xmm1
movss .LC24(%rip), %xmm0
movq 120(%rsp), %r8
movq 112(%rsp), %rcx
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z46__device_stub__Z15BlackScholesGPUPfS_S_S_S_ffiPfS_S_S_S_ffi
jmp .L33
.L50:
call cudaDeviceSynchronize@PLT
leaq 160(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
.L35:
movl $2, %ecx
movq %r12, %rdx
movq 88(%rsp), %rsi
movq 32(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq 96(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 168(%rsp), %xmm0
movsd .LC25(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 160(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 152(%rsp), %xmm1
divsd %xmm2, %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 144(%rsp), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq 48(%rsp), %rax
testl %eax, %eax
je .L42
movl %eax, %edx
movl $0, %eax
pxor %xmm2, %xmm2
movapd %xmm2, %xmm3
movss .LC27(%rip), %xmm5
movq .LC0(%rip), %xmm4
movq %rbx, %rcx
.L38:
movss 0(%rbp,%rax,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
subss (%rcx,%rax,4), %xmm0
andps %xmm5, %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm3
andpd %xmm4, %xmm1
addsd %xmm1, %xmm2
addq $1, %rax
cmpq %rdx, %rax
jne .L38
.L36:
divsd %xmm2, %xmm3
movq %xmm3, %rbx
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %xmm6
comisd .LC28(%rip), %xmm6
jbe .L48
movl $1, %edi
call exit@PLT
.L32:
leaq 144(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 48(%rsp), %r9d
movss .LC23(%rip), %xmm1
movss .LC24(%rip), %xmm0
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call _Z15BlackScholesCPUPfS_S_S_S_ffi
leaq 160(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
jmp .L35
.L42:
pxor %xmm2, %xmm2
movapd %xmm2, %xmm3
jmp .L36
.L48:
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC29:
.string "_Z15BlackScholesGPUPfS_S_S_S_ffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z15BlackScholesGPUPfS_S_S_S_ffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 410062862
.long 1070442097
.align 8
.LC2:
.long 0
.long 1072693248
.align 8
.LC3:
.long 0
.long -1075838976
.align 8
.LC4:
.long -688641725
.long 1073039565
.align 8
.LC5:
.long 1324513488
.long 1073554397
.align 8
.LC6:
.long 39804520
.long 1073512687
.align 8
.LC7:
.long -441961893
.long 1071043056
.align 8
.LC8:
.long 982710508
.long 1070887103
.align 8
.LC9:
.long 869545553
.long 1071220805
.align 8
.LC11:
.long 0
.long 1071644672
.section .rodata.cst16
.align 16
.LC12:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 805306368
.align 4
.LC14:
.long 1065353216
.align 4
.LC18:
.long 1106247680
.align 4
.LC19:
.long 1084227584
.align 4
.LC20:
.long 1120403456
.align 4
.LC21:
.long 1092616192
.align 4
.LC22:
.long 1048576000
.align 4
.LC23:
.long 1050253722
.align 4
.LC24:
.long 1017370378
.section .rodata.cst8
.align 8
.LC25:
.long 0
.long 1093567616
.section .rodata.cst16
.align 16
.LC27:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC28:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_wkld.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z15BlackScholesCPUPfS_S_S_S_ffi
.LCPI0_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI0_3:
.quad 0x3fcda6711871100e # double 0.23164190000000001
.LCPI0_4:
.quad 0x3ff0000000000000 # double 1
.LCPI0_5:
.quad 0xbfe0000000000000 # double -0.5
.LCPI0_6:
.quad 0x3fd9884533d43651 # double 0.3989422804014327
.LCPI0_7:
.quad 0x3ff548cdd6f42943 # double 1.3302744289999999
.LCPI0_8:
.quad 0xbffd23dd4ef278d0 # double -1.8212559779999999
.LCPI0_9:
.quad 0x3ffc80ef025f5e68 # double 1.781477937
.LCPI0_10:
.quad 0xbfd6d1f0e5a8325b # double -0.356563782
.LCPI0_11:
.quad 0x3fd470bf3a92f8ec # double 0.31938153000000002
.LCPI0_12:
.quad 0x0000000000000000 # double 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.LCPI0_2:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z15BlackScholesCPUPfS_S_S_S_ffi
.p2align 4, 0x90
.type _Z15BlackScholesCPUPfS_S_S_S_ffi,@function
_Z15BlackScholesCPUPfS_S_S_S_ffi: # @_Z15BlackScholesCPUPfS_S_S_S_ffi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 88(%rsp) # 8-byte Spill
testl %r9d, %r9d
jle .LBB0_6
# %bb.1: # %.lr.ph
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm1, %xmm2
movsd %xmm1, 80(%rsp) # 8-byte Spill
mulsd %xmm1, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 72(%rsp) # 8-byte Spill
xorps .LCPI0_1(%rip), %xmm0
movaps %xmm0, 96(%rsp) # 16-byte Spill
movl %r9d, %ebp
xorl %ebx, %ebx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
sqrtsd %xmm0, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
.LBB0_5: # %.split
# in Loop: Header=BB0_2 Depth=1
movaps %xmm3, %xmm0
divsd %xmm1, %xmm0
callq log
movsd 72(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd 40(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm0, %xmm2
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd 80(%rsp), %xmm1 # 8-byte Folded Reload
divsd %xmm1, %xmm2
movapd %xmm2, 48(%rsp) # 16-byte Spill
movapd %xmm2, %xmm0
subsd %xmm1, %xmm0
movapd %xmm0, (%rsp) # 16-byte Spill
movapd %xmm2, %xmm0
movapd .LCPI0_2(%rip), %xmm1 # xmm1 = [NaN,NaN]
andpd %xmm1, %xmm0
movsd .LCPI0_3(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI0_4(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
movsd .LCPI0_5(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
mulsd %xmm2, %xmm0
callq exp
movsd .LCPI0_6(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd 16(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movapd %xmm3, %xmm1
movsd .LCPI0_7(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
movsd .LCPI0_8(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
movsd .LCPI0_9(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
movsd .LCPI0_10(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
movsd .LCPI0_11(%rip), %xmm2 # xmm2 = mem[0],zero
addsd %xmm2, %xmm1
mulsd %xmm3, %xmm1
mulsd %xmm0, %xmm1
movsd .LCPI0_4(%rip), %xmm4 # xmm4 = mem[0],zero
movapd %xmm4, %xmm0
subsd %xmm1, %xmm0
xorpd %xmm3, %xmm3
cmpltsd 48(%rsp), %xmm3 # 16-byte Folded Reload
movapd %xmm3, %xmm2
andnpd %xmm1, %xmm2
andpd %xmm0, %xmm3
orpd %xmm2, %xmm3
movapd %xmm3, 48(%rsp) # 16-byte Spill
movapd (%rsp), %xmm2 # 16-byte Reload
movapd %xmm2, %xmm0
andpd .LCPI0_2(%rip), %xmm0
mulsd .LCPI0_3(%rip), %xmm0
movapd %xmm4, %xmm1
addsd %xmm4, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movapd %xmm2, %xmm0
mulsd .LCPI0_5(%rip), %xmm0
mulsd %xmm2, %xmm0
callq exp
mulsd .LCPI0_6(%rip), %xmm0
movsd 16(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
movapd %xmm2, %xmm1
mulsd .LCPI0_7(%rip), %xmm1
addsd .LCPI0_8(%rip), %xmm1
mulsd %xmm2, %xmm1
addsd .LCPI0_9(%rip), %xmm1
mulsd %xmm2, %xmm1
addsd .LCPI0_10(%rip), %xmm1
mulsd %xmm2, %xmm1
addsd .LCPI0_11(%rip), %xmm1
mulsd %xmm2, %xmm1
mulsd %xmm0, %xmm1
movsd .LCPI0_4(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm1, %xmm0
xorpd %xmm3, %xmm3
cmpltsd (%rsp), %xmm3 # 16-byte Folded Reload
movapd %xmm3, %xmm2
andnpd %xmm1, %xmm2
andpd %xmm0, %xmm3
orpd %xmm2, %xmm3
movapd %xmm3, (%rsp) # 16-byte Spill
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd 96(%rsp), %xmm0 # 16-byte Folded Reload
callq exp
movsd .LCPI0_4(%rip), %xmm5 # xmm5 = mem[0],zero
movapd %xmm5, %xmm1
movapd 48(%rsp), %xmm2 # 16-byte Reload
subsd %xmm2, %xmm1
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
mulsd %xmm3, %xmm2
movapd %xmm2, %xmm4
mulsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movapd %xmm5, %xmm2
movapd (%rsp), %xmm5 # 16-byte Reload
subsd %xmm5, %xmm2
mulsd %xmm0, %xmm2
mulsd %xmm5, %xmm0
subsd %xmm0, %xmm4
xorps %xmm0, %xmm0
cvtsd2ss %xmm4, %xmm0
mulsd %xmm3, %xmm1
subsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
movss %xmm0, (%r13,%rbx,4)
movss %xmm1, (%r12,%rbx,4)
incq %rbx
cmpq %rbx, %rbp
je .LBB0_6
.LBB0_2: # =>This Inner Loop Header: Depth=1
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq 88(%rsp), %rax # 8-byte Reload
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
xorps %xmm3, %xmm3
cvtss2sd %xmm0, %xmm3
cvtss2sd %xmm1, %xmm1
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
ucomisd .LCPI0_12(%rip), %xmm0
movsd %xmm3, 32(%rsp) # 8-byte Spill
movsd %xmm1, 24(%rsp) # 8-byte Spill
movsd %xmm0, 40(%rsp) # 8-byte Spill
jae .LBB0_3
# %bb.4: # %call.sqrt
# in Loop: Header=BB0_2 Depth=1
callq sqrt
movsd 24(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movsd %xmm0, (%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
jmp .LBB0_5
.LBB0_6: # %._crit_edge
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15BlackScholesCPUPfS_S_S_S_ffi, .Lfunc_end0-_Z15BlackScholesCPUPfS_S_S_S_ffi
.cfi_endproc
# -- End function
.globl _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi # -- Begin function _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.p2align 4, 0x90
.type _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi,@function
_Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi: # @_Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15BlackScholesGPUPfS_S_S_S_ffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi, .Lfunc_end1-_Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9RandFloatff
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x3f800000 # float 1
.text
.globl _Z9RandFloatff
.p2align 4, 0x90
.type _Z9RandFloatff,@function
_Z9RandFloatff: # @_Z9RandFloatff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm1, 4(%rsp) # 4-byte Spill
movss %xmm0, (%rsp) # 4-byte Spill
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movss .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss (%rsp), %xmm1 # 4-byte Folded Reload
mulss 4(%rsp), %xmm0 # 4-byte Folded Reload
addss %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9RandFloatff, .Lfunc_end2-_Z9RandFloatff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI3_1:
.long 0x3f800000 # float 1
.LCPI3_2:
.long 0x40a00000 # float 5
.LCPI3_3:
.long 0x41f00000 # float 30
.LCPI3_4:
.long 0x42c80000 # float 100
.LCPI3_5:
.long 0x3e800000 # float 0.25
.LCPI3_6:
.long 0x41200000 # float 10
.LCPI3_7:
.long 0x3ca3d70a # float 0.0199999996
.LCPI3_8:
.long 0x3e99999a # float 0.300000012
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_9:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_11:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_10:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $312, %rsp # imm = 0x138
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jg .LBB3_1
# %bb.17:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.LBB3_1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
leal (,%rax,4), %ebp
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 104(%rsp) # 8-byte Spill
movslq %ebp, %r15
movq %r15, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, 128(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r12
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq %r15, %rdi
callq malloc
movq %rax, %rbp
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, 88(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
movl $5347, %edi # imm = 0x14E3
callq srand
movq %r14, 8(%rsp) # 8-byte Spill
testl %r14d, %r14d
je .LBB3_4
# %bb.2: # %.lr.ph.preheader
movl 8(%rsp), %r14d # 4-byte Reload
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movl $0, (%rax,%r15,4)
movl $-1082130432, (%rbx,%r15,4) # imm = 0xBF800000
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss .LCPI3_2(%rip), %xmm1
mulss .LCPI3_3(%rip), %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%r12,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss .LCPI3_4(%rip), %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%r13,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss .LCPI3_5(%rip), %xmm1
mulss .LCPI3_6(%rip), %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%rbp,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB3_3
.LBB3_4: # %._crit_edge
movq %rbx, 80(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movq %r12, %rsi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %rbp, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
leaq 296(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cmpl $0, 104(%rsp) # 4-byte Folded Reload
movq %r12, 120(%rsp) # 8-byte Spill
movq %r13, 112(%rsp) # 8-byte Spill
jne .LBB3_5
# %bb.10:
movq %r12, %rdx
movss .LCPI3_7(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI3_8(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq 16(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r13, %rcx
movq %rbp, %r12
movq %rbp, %r8
movq 8(%rsp), %r13 # 8-byte Reload
movl %r13d, %r9d
callq _Z15BlackScholesCPUPfS_S_S_S_ffi
jmp .LBB3_11
.LBB3_5:
movq %rbp, %r12
movabsq $4294967296, %r14 # imm = 0x100000000
movq 8(%rsp), %rax # 8-byte Reload
leal 127(%rax), %r15d
shrl $7, %r15d
orq %r14, %r15
movl $512, %r13d # imm = 0x200
subq $-128, %r14
leaq 216(%rsp), %rbp
movq 16(%rsp), %rbx # 8-byte Reload
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
decl %r13d
je .LBB3_9
.LBB3_6: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=1
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
movq %rax, 216(%rsp)
movq %rcx, 208(%rsp)
movq %rdx, 200(%rsp)
movq %rsi, 192(%rsp)
movq %rdi, 184(%rsp)
movl $1017370378, 76(%rsp) # imm = 0x3CA3D70A
movl $1050253722, 72(%rsp) # imm = 0x3E99999A
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, 68(%rsp)
movq %rbp, 224(%rsp)
leaq 208(%rsp), %rax
movq %rax, 232(%rsp)
leaq 200(%rsp), %rax
movq %rax, 240(%rsp)
leaq 192(%rsp), %rax
movq %rax, 248(%rsp)
leaq 184(%rsp), %rax
movq %rax, 256(%rsp)
leaq 76(%rsp), %rax
movq %rax, 264(%rsp)
leaq 72(%rsp), %rax
movq %rax, 272(%rsp)
leaq 68(%rsp), %rax
movq %rax, 280(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movl $_Z15BlackScholesGPUPfS_S_S_S_ffi, %edi
leaq 224(%rsp), %r9
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_8
.LBB3_9:
callq hipDeviceSynchronize
movq 8(%rsp), %r13 # 8-byte Reload
.LBB3_11:
xorl %r14d, %r14d
leaq 224(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 56(%rsp), %rsi
movq 128(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq 88(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rsi
movq 96(%rsp), %rdi # 8-byte Reload
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
cvtsi2sdq 224(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 232(%rsp), %xmm0
movsd .LCPI3_9(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 296(%rsp), %xmm1
cvtsi2sdq 304(%rsp), %xmm3
divsd %xmm2, %xmm3
addsd %xmm1, %xmm3
subsd %xmm3, %xmm0
movq stdout(%rip), %rdi
movl $.L.str.1, %esi
movb $1, %al
callq fprintf
testl %r13d, %r13d
je .LBB3_15
# %bb.12: # %.lr.ph95.preheader
movl %r13d, %eax
xorpd %xmm0, %xmm0
xorl %ecx, %ecx
movaps .LCPI3_10(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorpd %xmm2, %xmm2
.p2align 4, 0x90
.LBB3_13: # %.lr.ph95
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rcx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm3, %xmm4
subss (%r15,%rcx,4), %xmm4
andps %xmm1, %xmm4
cvtss2sd %xmm4, %xmm4
addsd %xmm4, %xmm0
andps %xmm1, %xmm3
cvtss2sd %xmm3, %xmm3
addsd %xmm3, %xmm2
incq %rcx
cmpq %rcx, %rax
jne .LBB3_13
# %bb.14: # %._crit_edge96.loopexit
divsd %xmm2, %xmm0
ucomisd .LCPI3_11(%rip), %xmm0
seta %r14b
.LBB3_15: # %._crit_edge96
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq %r12, %rdi
callq free
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq 120(%rsp), %rdi # 8-byte Reload
callq free
movq 96(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
testb %r14b, %r14b
je .LBB3_16
# %bb.18:
movl $1, %edi
callq exit
.LBB3_16:
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15BlackScholesGPUPfS_S_S_S_ffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15BlackScholesGPUPfS_S_S_S_ffi,@object # @_Z15BlackScholesGPUPfS_S_S_S_ffi
.section .rodata,"a",@progbits
.globl _Z15BlackScholesGPUPfS_S_S_S_ffi
.p2align 3, 0x0
_Z15BlackScholesGPUPfS_S_S_S_ffi:
.quad _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.size _Z15BlackScholesGPUPfS_S_S_S_ffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: ./blackscholes options GPU\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\033[1
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15BlackScholesGPUPfS_S_S_S_ffi"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__BlackScholesGPUPfS_S_S_S_ffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15BlackScholesGPUPfS_S_S_S_ffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
// #include "lodepng.h"
__global__ void square(int *height, int *width, int *result){
*result = *height * *width;
}
int main(void){
int width, height, result;
int *gpuWidth, *gpuHeight, *gpuResult;
cudaMalloc(&gpuWidth, sizeof(int));
cudaMalloc(&gpuHeight, sizeof(int));
cudaMalloc(&gpuResult, sizeof(int));
width = 2;
height = 10;
cudaMemcpy(gpuWidth, &width, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(gpuHeight, &height, sizeof(int), cudaMemcpyHostToDevice);
square<<<height, width>>>(gpuHeight, gpuWidth, gpuResult);
cudaMemcpy(&result, gpuResult, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d\n", result);
return 0;
} | code for sm_80
Function : _Z6squarePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
// #include "lodepng.h"
__global__ void square(int *height, int *width, int *result){
*result = *height * *width;
}
int main(void){
int width, height, result;
int *gpuWidth, *gpuHeight, *gpuResult;
cudaMalloc(&gpuWidth, sizeof(int));
cudaMalloc(&gpuHeight, sizeof(int));
cudaMalloc(&gpuResult, sizeof(int));
width = 2;
height = 10;
cudaMemcpy(gpuWidth, &width, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(gpuHeight, &height, sizeof(int), cudaMemcpyHostToDevice);
square<<<height, width>>>(gpuHeight, gpuWidth, gpuResult);
cudaMemcpy(&result, gpuResult, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d\n", result);
return 0;
} | .file "tmpxft_0016c1d7_00000000-6_HPC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6squarePiS_S_PiS_S_
.type _Z29__device_stub__Z6squarePiS_S_PiS_S_, @function
_Z29__device_stub__Z6squarePiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6squarePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6squarePiS_S_PiS_S_, .-_Z29__device_stub__Z6squarePiS_S_PiS_S_
.globl _Z6squarePiS_S_
.type _Z6squarePiS_S_, @function
_Z6squarePiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6squarePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePiS_S_, .-_Z6squarePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $2, (%rsp)
movl $10, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl (%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 4(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6squarePiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
// #include "lodepng.h"
__global__ void square(int *height, int *width, int *result){
*result = *height * *width;
}
int main(void){
int width, height, result;
int *gpuWidth, *gpuHeight, *gpuResult;
cudaMalloc(&gpuWidth, sizeof(int));
cudaMalloc(&gpuHeight, sizeof(int));
cudaMalloc(&gpuResult, sizeof(int));
width = 2;
height = 10;
cudaMemcpy(gpuWidth, &width, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(gpuHeight, &height, sizeof(int), cudaMemcpyHostToDevice);
square<<<height, width>>>(gpuHeight, gpuWidth, gpuResult);
cudaMemcpy(&result, gpuResult, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d\n", result);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
// #include "lodepng.h"
__global__ void square(int *height, int *width, int *result){
*result = *height * *width;
}
int main(void){
int width, height, result;
int *gpuWidth, *gpuHeight, *gpuResult;
hipMalloc(&gpuWidth, sizeof(int));
hipMalloc(&gpuHeight, sizeof(int));
hipMalloc(&gpuResult, sizeof(int));
width = 2;
height = 10;
hipMemcpy(gpuWidth, &width, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(gpuHeight, &height, sizeof(int), hipMemcpyHostToDevice);
square<<<height, width>>>(gpuHeight, gpuWidth, gpuResult);
hipMemcpy(&result, gpuResult, sizeof(int), hipMemcpyDeviceToHost);
printf("%d\n", result);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
// #include "lodepng.h"
__global__ void square(int *height, int *width, int *result){
*result = *height * *width;
}
int main(void){
int width, height, result;
int *gpuWidth, *gpuHeight, *gpuResult;
hipMalloc(&gpuWidth, sizeof(int));
hipMalloc(&gpuHeight, sizeof(int));
hipMalloc(&gpuResult, sizeof(int));
width = 2;
height = 10;
hipMemcpy(gpuWidth, &width, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(gpuHeight, &height, sizeof(int), hipMemcpyHostToDevice);
square<<<height, width>>>(gpuHeight, gpuWidth, gpuResult);
hipMemcpy(&result, gpuResult, sizeof(int), hipMemcpyDeviceToHost);
printf("%d\n", result);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePiS_S_
.globl _Z6squarePiS_S_
.p2align 8
.type _Z6squarePiS_S_,@function
_Z6squarePiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePiS_S_, .Lfunc_end0-_Z6squarePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6squarePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdio.h>
#include <stdlib.h>
// #include "lodepng.h"
__global__ void square(int *height, int *width, int *result){
*result = *height * *width;
}
int main(void){
int width, height, result;
int *gpuWidth, *gpuHeight, *gpuResult;
hipMalloc(&gpuWidth, sizeof(int));
hipMalloc(&gpuHeight, sizeof(int));
hipMalloc(&gpuResult, sizeof(int));
width = 2;
height = 10;
hipMemcpy(gpuWidth, &width, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(gpuHeight, &height, sizeof(int), hipMemcpyHostToDevice);
square<<<height, width>>>(gpuHeight, gpuWidth, gpuResult);
hipMemcpy(&result, gpuResult, sizeof(int), hipMemcpyDeviceToHost);
printf("%d\n", result);
return 0;
} | .text
.file "HPC.hip"
.globl _Z21__device_stub__squarePiS_S_ # -- Begin function _Z21__device_stub__squarePiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__squarePiS_S_,@function
_Z21__device_stub__squarePiS_S_: # @_Z21__device_stub__squarePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePiS_S_, .Lfunc_end0-_Z21__device_stub__squarePiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $2, 4(%rsp)
movl $10, (%rsp)
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl (%rsp), %edi
movl 4(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6squarePiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePiS_S_,@object # @_Z6squarePiS_S_
.section .rodata,"a",@progbits
.globl _Z6squarePiS_S_
.p2align 3, 0x0
_Z6squarePiS_S_:
.quad _Z21__device_stub__squarePiS_S_
.size _Z6squarePiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePiS_S_
.globl _Z6squarePiS_S_
.p2align 8
.type _Z6squarePiS_S_,@function
_Z6squarePiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePiS_S_, .Lfunc_end0-_Z6squarePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6squarePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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