system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define N 512
__global__ void dot(int *a, int *b, int *c) {
__shared__ int temp[N];
temp[threadIdx.x] = a[threadIdx.x] * b[threadIdx.x];
__syncthreads();
if (0 == threadIdx.x) {
int sum = 0;
for(int i = 0; i < N; i++)
sum += temp[i];
*c = sum;
}
}
void random_ints(int *a, int size) {
for (int i = 0; i < size; i++) {
a[i] = rand() % 10;
}
}
int main( void ) {
srand(10);
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size = N * sizeof(int);
hipMalloc((void**)&dev_a, size);
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, sizeof(int));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
random_ints(a, N);
random_ints(b, N);
// копируем ввод на device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
//запускаем на выполнение dot() kernel с 1 блоком и N тредами
dot<<<1, N>>>(dev_a, dev_b, dev_c);
//копируем результат работы device на host копией c
hipMemcpy(c, dev_c, sizeof(int) , hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++) {
std::cout << a[i] << " " << b[i]<< "\n";
}
std::cout << *c << "\n";
free(a); free(b); free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPiS_S_
.globl _Z3dotPiS_S_
.p2align 8
.type _Z3dotPiS_S_,@function
_Z3dotPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v2, v1, s[4:5]
global_load_b32 v3, v1, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
.LBB0_2:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s2, 0x800
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPiS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPiS_S_, .Lfunc_end0-_Z3dotPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3dotPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#define N 512
__global__ void dot(int *a, int *b, int *c) {
__shared__ int temp[N];
temp[threadIdx.x] = a[threadIdx.x] * b[threadIdx.x];
__syncthreads();
if (0 == threadIdx.x) {
int sum = 0;
for(int i = 0; i < N; i++)
sum += temp[i];
*c = sum;
}
}
void random_ints(int *a, int size) {
for (int i = 0; i < size; i++) {
a[i] = rand() % 10;
}
}
int main( void ) {
srand(10);
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size = N * sizeof(int);
hipMalloc((void**)&dev_a, size);
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, sizeof(int));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
random_ints(a, N);
random_ints(b, N);
// копируем ввод на device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
//запускаем на выполнение dot() kernel с 1 блоком и N тредами
dot<<<1, N>>>(dev_a, dev_b, dev_c);
//копируем результат работы device на host копией c
hipMemcpy(c, dev_c, sizeof(int) , hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++) {
std::cout << a[i] << " " << b[i]<< "\n";
}
std::cout << *c << "\n";
free(a); free(b); free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "task6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPiS_S_ # -- Begin function _Z18__device_stub__dotPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPiS_S_,@function
_Z18__device_stub__dotPiS_S_: # @_Z18__device_stub__dotPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPiS_S_, .Lfunc_end0-_Z18__device_stub__dotPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10, %edi
callq srand
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_1
# %bb.2: # %.lr.ph.i22.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit26
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r14,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
cmpq $512, %r13 # imm = 0x200
jne .LBB2_7
# %bb.8:
movl (%r15), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPiS_S_,@object # @_Z3dotPiS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPiS_S_
.p2align 3, 0x0
_Z3dotPiS_S_:
.quad _Z18__device_stub__dotPiS_S_
.size _Z3dotPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00076b95_00000000-6_task6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3dotPiS_S_PiS_S_
.type _Z26__device_stub__Z3dotPiS_S_PiS_S_, @function
_Z26__device_stub__Z3dotPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3dotPiS_S_PiS_S_, .-_Z26__device_stub__Z3dotPiS_S_PiS_S_
.globl _Z3dotPiS_S_
.type _Z3dotPiS_S_, @function
_Z3dotPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3dotPiS_S_, .-_Z3dotPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $10, %edi
call srand@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $512, %esi
movq %r13, %rdi
call _Z11random_intsPii
movl $512, %esi
movq %r12, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $2048, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r15
leaq .LC0(%rip), %r14
.L21:
movl 0(%r13,%rbx), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq $2048, %rbx
jne .L21
movq 8(%rsp), %rbx
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3dotPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPiS_S_ # -- Begin function _Z18__device_stub__dotPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPiS_S_,@function
_Z18__device_stub__dotPiS_S_: # @_Z18__device_stub__dotPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPiS_S_, .Lfunc_end0-_Z18__device_stub__dotPiS_S_
.cfi_endproc
# -- End function
.globl _Z11random_intsPii # -- Begin function _Z11random_intsPii
.p2align 4, 0x90
.type _Z11random_intsPii,@function
_Z11random_intsPii: # @_Z11random_intsPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11random_intsPii, .Lfunc_end1-_Z11random_intsPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10, %edi
callq srand
leaq 16(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_1
# %bb.2: # %.lr.ph.i22.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i22
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $512, %r12 # imm = 0x200
jne .LBB2_3
# %bb.4: # %_Z11random_intsPii.exit26
movq 16(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 511(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%r14,%r13,4), %esi
movq %r12, %rdi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r13
cmpq $512, %r13 # imm = 0x200
jne .LBB2_7
# %bb.8:
movl (%r15), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPiS_S_,@object # @_Z3dotPiS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPiS_S_
.p2align 3, 0x0
_Z3dotPiS_S_:
.quad _Z18__device_stub__dotPiS_S_
.size _Z3dotPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void DragRealGrad(float2 *ORIGIN , float *DEST , float *VEC) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
DEST[idx] = ORIGIN[idx].x/sqV - VEC[idx];
} | code for sm_80
Function : _Z12DragRealGradP6float2PfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a036115 ; /* 0x3a036115ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ BSSY B1, 0x160 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x44f96a56 ; /* 0x44f96a56ff047424 */
/* 0x000fc800078e00ff */
/*00b0*/ FFMA R4, R5, -R4, 1 ; /* 0x3f80000005047423 */
/* 0x000fc80000000804 */
/*00c0*/ FFMA R4, R4, R5, 0.00050117197679355740547 ; /* 0x3a03611504047423 */
/* 0x000fe20000000005 */
/*00d0*/ FCHK P0, R3, 1995.322998046875 ; /* 0x44f96a5603007902 */
/* 0x004e260000000000 */
/*00e0*/ FFMA R5, R3, R4, RZ ; /* 0x0000000403057223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, R5, -1995.322998046875, R3 ; /* 0xc4f96a5605067823 */
/* 0x000fc80000000003 */
/*0100*/ FFMA R6, R4, R6, R5 ; /* 0x0000000604067223 */
/* 0x000fe20000000005 */
/*0110*/ @!P0 BRA 0x150 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x1d0 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0005 */
/*0150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0190*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0205 */
/*01a0*/ FADD R7, -R3, R6 ; /* 0x0000000603077221 */
/* 0x004fca0000000100 */
/*01b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011603 */
/*01e0*/ BSSY B0, 0x7b0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*01f0*/ BSSY B2, 0x3a0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*0210*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fc800078ec0ff */
/*0220*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GT.U32.OR P0, PT, R7, 0xfd, !PT ; /* 0x000000fd0700780c */
/* 0x000fda0007f04470 */
/*0240*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0250*/ @!P0 BRA 0x390 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0270*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0280*/ @P0 BRA 0x790 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, 0x44f96a56 ; /* 0x44f96a56ff067424 */
/* 0x000fca00078e00ff */
/*02a0*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*02b0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*02c0*/ @!P0 BRA 0x770 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*02e0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*02f0*/ @!P0 BRA 0x750 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*0310*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0320*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0330*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0340*/ @P0 BRA 0x720 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*0360*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0370*/ @!P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003058823 */
/* 0x000fe400000000ff */
/*0380*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0390*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*03a0*/ UMOV UR4, 0x44f96a56 ; /* 0x44f96a5600047882 */
/* 0x000fe20000000000 */
/*03b0*/ IADD3 R4, R4, -0x7f, RZ ; /* 0xffffff8104047810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ UIADD3 UR4, UR4, -0x5000000, URZ ; /* 0xfb00000004047890 */
/* 0x000fe2000fffe03f */
/*03d0*/ BSSY B2, 0x710 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*03e0*/ IADD3 R6, R6, -0xa, R4 ; /* 0xfffffff606067810 */
/* 0x000fe20007ffe004 */
/*03f0*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fc400078e0205 */
/*0400*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*0410*/ MUFU.RCP R3, UR4 ; /* 0x0000000400037d08 */
/* 0x000e240008001000 */
/*0420*/ FFMA R10, R3, R8, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000008 */
/*0430*/ FFMA R10, R3, R10, R3 ; /* 0x0000000a030a7223 */
/* 0x000fc80000000003 */
/*0440*/ FFMA R3, R5, R10, RZ ; /* 0x0000000a05037223 */
/* 0x000fc800000000ff */
/*0450*/ FFMA R7, R8, R3, R5 ; /* 0x0000000308077223 */
/* 0x000fc80000000005 */
/*0460*/ FFMA R7, R10, R7, R3 ; /* 0x000000070a077223 */
/* 0x000fc80000000003 */
/*0470*/ FFMA R8, R8, R7, R5 ; /* 0x0000000708087223 */
/* 0x000fc80000000005 */
/*0480*/ FFMA R5, R10, R8, R7 ; /* 0x000000080a057223 */
/* 0x000fca0000000007 */
/*0490*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fc80000011605 */
/*04a0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*04b0*/ IMAD.IADD R9, R3, 0x1, R6 ; /* 0x0000000103097824 */
/* 0x000fca00078e0206 */
/*04c0*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*04e0*/ @!P0 BRA 0x6f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0500*/ @P0 BRA 0x6c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0510*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0520*/ @P0 BRA 0x700 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0540*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0550*/ @!P0 BRA 0x700 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0560*/ FFMA.RZ R3, R10.reuse, R8.reuse, R7 ; /* 0x000000080a037223 */
/* 0x0c0fe2000000c007 */
/*0570*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0580*/ IMAD.MOV R6, RZ, RZ, -R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a09 */
/*0590*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*05a0*/ LOP3.LUT R4, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03047812 */
/* 0x000fe200078ec0ff */
/*05b0*/ FFMA.RP R3, R10.reuse, R8.reuse, R7.reuse ; /* 0x000000080a037223 */
/* 0x1c0fe40000008007 */
/*05c0*/ FFMA.RM R10, R10, R8, R7 ; /* 0x000000080a0a7223 */
/* 0x000fe20000004007 */
/*05d0*/ IADD3 R7, R9, 0x20, RZ ; /* 0x0000002009077810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fc400078efcff */
/*05f0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720b */
/* 0x000fe40003f1d000 */
/*0600*/ SHF.L.U32 R7, R4, R7, RZ ; /* 0x0000000704077219 */
/* 0x000fe400000006ff */
/*0610*/ SEL R3, R6, RZ, P2 ; /* 0x000000ff06037207 */
/* 0x000fe40001000000 */
/*0620*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0630*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*0640*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0650*/ SHF.R.U32.HI R7, RZ, 0x1, R3 ; /* 0x00000001ff077819 */
/* 0x000fe40000011603 */
/*0660*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0670*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0680*/ LOP3.LUT R4, R4, R3, RZ, 0xc0, !PT ; /* 0x0000000304047212 */
/* 0x000fca00078ec0ff */
/*0690*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*06a0*/ LOP3.LUT R5, R4, R5, RZ, 0xfc, !PT ; /* 0x0000000504057212 */
/* 0x000fe200078efcff */
/*06b0*/ BRA 0x700 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*06c0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*06d0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*06e0*/ BRA 0x700 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD R5, R6, 0x800000, R5 ; /* 0x0080000006057824 */
/* 0x000fe400078e0205 */
/*0700*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x7a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0720*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fc800078e4805 */
/*0730*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x7a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078e4805 */
/*0760*/ BRA 0x7a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0770*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0780*/ BRA 0x7a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0790*/ FADD.FTZ R5, R3, 1995.322998046875 ; /* 0x44f96a5603057421 */
/* 0x000fe40000010000 */
/*07a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*07c0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff83002007950 */
/* 0x000fea0003c3ffff */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void DragRealGrad(float2 *ORIGIN , float *DEST , float *VEC) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
DEST[idx] = ORIGIN[idx].x/sqV - VEC[idx];
} | .file "tmpxft_000877b3_00000000-6_DragRealGrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_
.type _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_, @function
_Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12DragRealGradP6float2PfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_, .-_Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_
.globl _Z12DragRealGradP6float2PfS1_
.type _Z12DragRealGradP6float2PfS1_, @function
_Z12DragRealGradP6float2PfS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12DragRealGradP6float2PfS1_, .-_Z12DragRealGradP6float2PfS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12DragRealGradP6float2PfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12DragRealGradP6float2PfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void DragRealGrad(float2 *ORIGIN , float *DEST , float *VEC) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
DEST[idx] = ORIGIN[idx].x/sqV - VEC[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DragRealGrad(float2 *ORIGIN , float *DEST , float *VEC) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
DEST[idx] = ORIGIN[idx].x/sqV - VEC[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DragRealGrad(float2 *ORIGIN , float *DEST , float *VEC) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
DEST[idx] = ORIGIN[idx].x/sqV - VEC[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.globl _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.p2align 8
.type _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_,@function
_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v0
global_load_b32 v4, v[3:4], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_div_scale_f32 v3, null, 0x44f96a56, 0x44f96a56, v4
v_div_scale_f32 v7, vcc_lo, v4, 0x44f96a56, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v3, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v3, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v3, -v3, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v3, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v3, v3, 0x44f96a56, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, .Lfunc_end0-_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DragRealGrad(float2 *ORIGIN , float *DEST , float *VEC) {
int idx = threadIdx.x + blockIdx.x*blockDim.x;
DEST[idx] = ORIGIN[idx].x/sqV - VEC[idx];
} | .text
.file "DragRealGrad.hip"
.globl _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_ # -- Begin function _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.p2align 4, 0x90
.type _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_,@function
_Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_: # @_Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, .Lfunc_end0-_Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_,@object # @_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.section .rodata,"a",@progbits
.globl _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.p2align 3, 0x0
_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_:
.quad _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.size _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12DragRealGradP6float2PfS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3a036115 ; /* 0x3a036115ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ BSSY B1, 0x160 ; /* 0x000000c000017945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x44f96a56 ; /* 0x44f96a56ff047424 */
/* 0x000fc800078e00ff */
/*00b0*/ FFMA R4, R5, -R4, 1 ; /* 0x3f80000005047423 */
/* 0x000fc80000000804 */
/*00c0*/ FFMA R4, R4, R5, 0.00050117197679355740547 ; /* 0x3a03611504047423 */
/* 0x000fe20000000005 */
/*00d0*/ FCHK P0, R3, 1995.322998046875 ; /* 0x44f96a5603007902 */
/* 0x004e260000000000 */
/*00e0*/ FFMA R5, R3, R4, RZ ; /* 0x0000000403057223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, R5, -1995.322998046875, R3 ; /* 0xc4f96a5605067823 */
/* 0x000fc80000000003 */
/*0100*/ FFMA R6, R4, R6, R5 ; /* 0x0000000604067223 */
/* 0x000fe20000000005 */
/*0110*/ @!P0 BRA 0x150 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x1d0 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0005 */
/*0150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0190*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0205 */
/*01a0*/ FADD R7, -R3, R6 ; /* 0x0000000603077221 */
/* 0x004fca0000000100 */
/*01b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ SHF.R.U32.HI R4, RZ, 0x17, R3.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011603 */
/*01e0*/ BSSY B0, 0x7b0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*01f0*/ BSSY B2, 0x3a0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*0210*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fc800078ec0ff */
/*0220*/ IADD3 R7, R4, -0x1, RZ ; /* 0xffffffff04077810 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GT.U32.OR P0, PT, R7, 0xfd, !PT ; /* 0x000000fd0700780c */
/* 0x000fda0007f04470 */
/*0240*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0250*/ @!P0 BRA 0x390 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0260*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fda0003f1c200 */
/*0270*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0280*/ @P0 BRA 0x790 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, 0x44f96a56 ; /* 0x44f96a56ff067424 */
/* 0x000fca00078e00ff */
/*02a0*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*02b0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*02c0*/ @!P0 BRA 0x770 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fda000780c0ff */
/*02e0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*02f0*/ @!P0 BRA 0x750 ; /* 0x0000045000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1d200 */
/*0310*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*0320*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0330*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0340*/ @P0 BRA 0x720 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f06270 */
/*0360*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0370*/ @!P0 FFMA R5, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003058823 */
/* 0x000fe400000000ff */
/*0380*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0390*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*03a0*/ UMOV UR4, 0x44f96a56 ; /* 0x44f96a5600047882 */
/* 0x000fe20000000000 */
/*03b0*/ IADD3 R4, R4, -0x7f, RZ ; /* 0xffffff8104047810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ UIADD3 UR4, UR4, -0x5000000, URZ ; /* 0xfb00000004047890 */
/* 0x000fe2000fffe03f */
/*03d0*/ BSSY B2, 0x710 ; /* 0x0000033000027945 */
/* 0x000fe40003800000 */
/*03e0*/ IADD3 R6, R6, -0xa, R4 ; /* 0xfffffff606067810 */
/* 0x000fe20007ffe004 */
/*03f0*/ IMAD R5, R4, -0x800000, R5 ; /* 0xff80000004057824 */
/* 0x000fc400078e0205 */
/*0400*/ FADD.FTZ R8, -RZ, -UR4 ; /* 0x80000004ff087e21 */
/* 0x000fc60008010100 */
/*0410*/ MUFU.RCP R3, UR4 ; /* 0x0000000400037d08 */
/* 0x000e240008001000 */
/*0420*/ FFMA R10, R3, R8, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000008 */
/*0430*/ FFMA R10, R3, R10, R3 ; /* 0x0000000a030a7223 */
/* 0x000fc80000000003 */
/*0440*/ FFMA R3, R5, R10, RZ ; /* 0x0000000a05037223 */
/* 0x000fc800000000ff */
/*0450*/ FFMA R7, R8, R3, R5 ; /* 0x0000000308077223 */
/* 0x000fc80000000005 */
/*0460*/ FFMA R7, R10, R7, R3 ; /* 0x000000070a077223 */
/* 0x000fc80000000003 */
/*0470*/ FFMA R8, R8, R7, R5 ; /* 0x0000000708087223 */
/* 0x000fc80000000005 */
/*0480*/ FFMA R5, R10, R8, R7 ; /* 0x000000080a057223 */
/* 0x000fca0000000007 */
/*0490*/ SHF.R.U32.HI R3, RZ, 0x17, R5 ; /* 0x00000017ff037819 */
/* 0x000fc80000011605 */
/*04a0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fca00078ec0ff */
/*04b0*/ IMAD.IADD R9, R3, 0x1, R6 ; /* 0x0000000103097824 */
/* 0x000fca00078e0206 */
/*04c0*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GE.U32.AND P0, PT, R3, 0xfe, PT ; /* 0x000000fe0300780c */
/* 0x000fda0003f06070 */
/*04e0*/ @!P0 BRA 0x6f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0500*/ @P0 BRA 0x6c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0510*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0520*/ @P0 BRA 0x700 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0540*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0550*/ @!P0 BRA 0x700 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0560*/ FFMA.RZ R3, R10.reuse, R8.reuse, R7 ; /* 0x000000080a037223 */
/* 0x0c0fe2000000c007 */
/*0570*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0580*/ IMAD.MOV R6, RZ, RZ, -R9 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a09 */
/*0590*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*05a0*/ LOP3.LUT R4, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03047812 */
/* 0x000fe200078ec0ff */
/*05b0*/ FFMA.RP R3, R10.reuse, R8.reuse, R7.reuse ; /* 0x000000080a037223 */
/* 0x1c0fe40000008007 */
/*05c0*/ FFMA.RM R10, R10, R8, R7 ; /* 0x000000080a0a7223 */
/* 0x000fe20000004007 */
/*05d0*/ IADD3 R7, R9, 0x20, RZ ; /* 0x0000002009077810 */
/* 0x000fe40007ffe0ff */
/*05e0*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fc400078efcff */
/*05f0*/ FSETP.NEU.FTZ.AND P0, PT, R3, R10, PT ; /* 0x0000000a0300720b */
/* 0x000fe40003f1d000 */
/*0600*/ SHF.L.U32 R7, R4, R7, RZ ; /* 0x0000000704077219 */
/* 0x000fe400000006ff */
/*0610*/ SEL R3, R6, RZ, P2 ; /* 0x000000ff06037207 */
/* 0x000fe40001000000 */
/*0620*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0630*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fe40000011604 */
/*0640*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0650*/ SHF.R.U32.HI R7, RZ, 0x1, R3 ; /* 0x00000001ff077819 */
/* 0x000fe40000011603 */
/*0660*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0670*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0680*/ LOP3.LUT R4, R4, R3, RZ, 0xc0, !PT ; /* 0x0000000304047212 */
/* 0x000fca00078ec0ff */
/*0690*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*06a0*/ LOP3.LUT R5, R4, R5, RZ, 0xfc, !PT ; /* 0x0000000504057212 */
/* 0x000fe200078efcff */
/*06b0*/ BRA 0x700 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*06c0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*06d0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*06e0*/ BRA 0x700 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06f0*/ IMAD R5, R6, 0x800000, R5 ; /* 0x0080000006057824 */
/* 0x000fe400078e0205 */
/*0700*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0710*/ BRA 0x7a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0720*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fc800078e4805 */
/*0730*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0740*/ BRA 0x7a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0750*/ LOP3.LUT R5, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078e4805 */
/*0760*/ BRA 0x7a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0770*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0780*/ BRA 0x7a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0790*/ FADD.FTZ R5, R3, 1995.322998046875 ; /* 0x44f96a5603057421 */
/* 0x000fe40000010000 */
/*07a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*07c0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff83002007950 */
/* 0x000fea0003c3ffff */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.globl _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.p2align 8
.type _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_,@function
_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v0
global_load_b32 v4, v[3:4], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_div_scale_f32 v3, null, 0x44f96a56, 0x44f96a56, v4
v_div_scale_f32 v7, vcc_lo, v4, 0x44f96a56, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v3, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v3, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v3, -v3, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v3, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v3, v3, 0x44f96a56, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_sub_f32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, .Lfunc_end0-_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000877b3_00000000-6_DragRealGrad.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_
.type _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_, @function
_Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12DragRealGradP6float2PfS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_, .-_Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_
.globl _Z12DragRealGradP6float2PfS1_
.type _Z12DragRealGradP6float2PfS1_, @function
_Z12DragRealGradP6float2PfS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z12DragRealGradP6float2PfS1_P6float2PfS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12DragRealGradP6float2PfS1_, .-_Z12DragRealGradP6float2PfS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12DragRealGradP6float2PfS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12DragRealGradP6float2PfS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DragRealGrad.hip"
.globl _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_ # -- Begin function _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.p2align 4, 0x90
.type _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_,@function
_Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_: # @_Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, .Lfunc_end0-_Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_,@object # @_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.section .rodata,"a",@progbits
.globl _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.p2align 3, 0x0
_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_:
.quad _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.size _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_"
.size .L__unnamed_1, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12DragRealGradP15HIP_vector_typeIfLj2EEPfS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // update the velocities
__global__ void update_vel(int npart, float qom, float dx, float dt, float *Epx, float *u){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while ( tid < npart) {
u[tid] = u[tid] + float(qom)*Epx[tid]*float(dt);
tid += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z10update_velifffPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R4, R0, R3, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ FMUL R6, R4, c[0x0][0x164] ; /* 0x0000590004067a20 */
/* 0x004fc80000400000 */
/*0100*/ FFMA R7, R6, c[0x0][0x16c], R7 ; /* 0x00005b0006077a23 */
/* 0x008fca0000000007 */
/*0110*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e6000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // update the velocities
__global__ void update_vel(int npart, float qom, float dx, float dt, float *Epx, float *u){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while ( tid < npart) {
u[tid] = u[tid] + float(qom)*Epx[tid]*float(dt);
tid += blockDim.x * gridDim.x;
}
} | .file "tmpxft_000a384f_00000000-6_update_vel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10update_velifffPfS_ifffPfS_
.type _Z36__device_stub__Z10update_velifffPfS_ifffPfS_, @function
_Z36__device_stub__Z10update_velifffPfS_ifffPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10update_velifffPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10update_velifffPfS_ifffPfS_, .-_Z36__device_stub__Z10update_velifffPfS_ifffPfS_
.globl _Z10update_velifffPfS_
.type _Z10update_velifffPfS_, @function
_Z10update_velifffPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10update_velifffPfS_ifffPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10update_velifffPfS_, .-_Z10update_velifffPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10update_velifffPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10update_velifffPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // update the velocities
__global__ void update_vel(int npart, float qom, float dx, float dt, float *Epx, float *u){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while ( tid < npart) {
u[tid] = u[tid] + float(qom)*Epx[tid]*float(dt);
tid += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
// update the velocities
__global__ void update_vel(int npart, float qom, float dx, float dt, float *Epx, float *u){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while ( tid < npart) {
u[tid] = u[tid] + float(qom)*Epx[tid]*float(dt);
tid += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// update the velocities
__global__ void update_vel(int npart, float qom, float dx, float dt, float *Epx, float *u){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while ( tid < npart) {
u[tid] = u[tid] + float(qom)*Epx[tid]*float(dt);
tid += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10update_velifffPfS_
.globl _Z10update_velifffPfS_
.p2align 8
.type _Z10update_velifffPfS_,@function
_Z10update_velifffPfS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[2:3], 0x0
s_clause 0x2
s_load_b32 s5, s[0:1], 0x4
s_load_b32 s6, s[0:1], 0xc
s_load_b128 s[0:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s8, s7
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(1)
v_dual_mul_f32 v0, s5, v0 :: v_dual_add_nc_u32 v1, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s6, v0
s_or_b32 s8, vcc_lo, s8
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10update_velifffPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10update_velifffPfS_, .Lfunc_end0-_Z10update_velifffPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10update_velifffPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10update_velifffPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// update the velocities
__global__ void update_vel(int npart, float qom, float dx, float dt, float *Epx, float *u){
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while ( tid < npart) {
u[tid] = u[tid] + float(qom)*Epx[tid]*float(dt);
tid += blockDim.x * gridDim.x;
}
} | .text
.file "update_vel.hip"
.globl _Z25__device_stub__update_velifffPfS_ # -- Begin function _Z25__device_stub__update_velifffPfS_
.p2align 4, 0x90
.type _Z25__device_stub__update_velifffPfS_,@function
_Z25__device_stub__update_velifffPfS_: # @_Z25__device_stub__update_velifffPfS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10update_velifffPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__update_velifffPfS_, .Lfunc_end0-_Z25__device_stub__update_velifffPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10update_velifffPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10update_velifffPfS_,@object # @_Z10update_velifffPfS_
.section .rodata,"a",@progbits
.globl _Z10update_velifffPfS_
.p2align 3, 0x0
_Z10update_velifffPfS_:
.quad _Z25__device_stub__update_velifffPfS_
.size _Z10update_velifffPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10update_velifffPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__update_velifffPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10update_velifffPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10update_velifffPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R4, R0, R3, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0203 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fe400078e0203 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fca0000000f00 */
/*00d0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ FMUL R6, R4, c[0x0][0x164] ; /* 0x0000590004067a20 */
/* 0x004fc80000400000 */
/*0100*/ FFMA R7, R6, c[0x0][0x16c], R7 ; /* 0x00005b0006077a23 */
/* 0x008fca0000000007 */
/*0110*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e6000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10update_velifffPfS_
.globl _Z10update_velifffPfS_
.p2align 8
.type _Z10update_velifffPfS_,@function
_Z10update_velifffPfS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_mov_b32 s5, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[2:3], 0x0
s_clause 0x2
s_load_b32 s5, s[0:1], 0x4
s_load_b32 s6, s[0:1], 0xc
s_load_b128 s[0:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s8, s7
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(1)
v_dual_mul_f32 v0, s5, v0 :: v_dual_add_nc_u32 v1, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s6, v0
s_or_b32 s8, vcc_lo, s8
global_store_b32 v[2:3], v4, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10update_velifffPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10update_velifffPfS_, .Lfunc_end0-_Z10update_velifffPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10update_velifffPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10update_velifffPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a384f_00000000-6_update_vel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z10update_velifffPfS_ifffPfS_
.type _Z36__device_stub__Z10update_velifffPfS_ifffPfS_, @function
_Z36__device_stub__Z10update_velifffPfS_ifffPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10update_velifffPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z10update_velifffPfS_ifffPfS_, .-_Z36__device_stub__Z10update_velifffPfS_ifffPfS_
.globl _Z10update_velifffPfS_
.type _Z10update_velifffPfS_, @function
_Z10update_velifffPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z10update_velifffPfS_ifffPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10update_velifffPfS_, .-_Z10update_velifffPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10update_velifffPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10update_velifffPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_vel.hip"
.globl _Z25__device_stub__update_velifffPfS_ # -- Begin function _Z25__device_stub__update_velifffPfS_
.p2align 4, 0x90
.type _Z25__device_stub__update_velifffPfS_,@function
_Z25__device_stub__update_velifffPfS_: # @_Z25__device_stub__update_velifffPfS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, (%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10update_velifffPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__update_velifffPfS_, .Lfunc_end0-_Z25__device_stub__update_velifffPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10update_velifffPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10update_velifffPfS_,@object # @_Z10update_velifffPfS_
.section .rodata,"a",@progbits
.globl _Z10update_velifffPfS_
.p2align 3, 0x0
_Z10update_velifffPfS_:
.quad _Z25__device_stub__update_velifffPfS_
.size _Z10update_velifffPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10update_velifffPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__update_velifffPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10update_velifffPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW(int B);
int ceil(int a, int b);
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist; // n * n, on device
int streamSize;
vector<cudaStream_t> streams;
inline cudaStream_t getIdleStream ()
{
if(streams.size() == streamSize)
{
cudaStream_t stm;
cudaStreamCreate(&stm);
streams.push_back(stm);
streamSize++;
return stm;
}
else
return streams[streamSize++];
}
inline void syncAllStreams ()
{
cudaThreadSynchronize();
streamSize = 0;
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
// if(B > n)
// {
// B = n;
// cerr << "Warning: B > n. Set B = n.";
// }
block_FW(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
Dist = new int[n * n];
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
delete[] Dist;
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
inline int ceil(int a, int b)
{
return (a + b -1)/b;
}
inline __device__
void updateMin (int &x, int a)
{
if(a < x) x = a;
}
__global__
void UpdateIKJ32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int i = r * 32 + tx;
int j = r * 32 + ty;
__shared__ int S[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S[tx][ty], S[tx][k] + S[k][ty]);
__syncthreads();
}
D(i, j) = S[tx][ty];
#undef D
}
__global__
void UpdateIK32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int by = blockIdx.x;
if(by >= r) by++;
int i = r * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r*32 + ty);
S1[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S1[tx][ty], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S1[tx][ty];
#undef D
}
__global__
void UpdateKJ32 (int r, int* dDist, int n)
// 0 --update--> 1
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
if(bx >= r) bx++;
int i = bx * 32 + tx;
int j = r * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, j);
S1[tx][ty] = D(r*32 + tx, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S0[ty][tx], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S0[ty][tx];
#undef D
}
__global__
void Update32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= r) bx++;
if(by >= r) by++;
int i = bx * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r * 32 + ty);
S1[tx][ty] = D(r * 32 + tx, j);
__syncthreads();
int Dij = D(i, j);
for(int k=0; k<32; ++k)
{
updateMin(Dij, S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = Dij;
#undef D
}
void block_FW(int B)
{
int *dPivot;
cudaMalloc(&dDist, sizeof(int) * n * n);
cudaMalloc(&dPivot, sizeof(int) * B * B);
cudaMemcpy(dDist, Dist, sizeof(int) * n * n, cudaMemcpyHostToDevice);
int round = ceil(n, B);
if(B == 32)
{
for (int r = 0; r < round; ++r)
{
/* Phase 1*/
UpdateIKJ32 <<< 1, dim3(32,32) >>> (r, dDist, n);
/* Phase 2*/
UpdateIK32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
UpdateKJ32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
syncAllStreams();
/* Phase 3*/
Update32 <<< dim3(round-1, round-1), dim3(32,32) >>> (r, dDist, n);
}
}
else
for (int r = 0; r < round; ++r) {
/* Phase 1*/
calAsync(B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(B, r, r, 0, r, 1);
calAsync(B, r, r, r +1, round - r -1, 1);
calAsync(B, r, 0, r, 1, r);
calAsync(B, r, r +1, r, 1, round - r -1);
syncAllStreams();
/* Phase 3*/
calAsync(B, r, 0, 0, r, r);
calAsync(B, r, 0, r +1, round -r -1, r);
calAsync(B, r, r +1, 0, r, round - r -1);
calAsync(B, r, r +1, r +1, round -r -1, round - r -1);
syncAllStreams();
}
cudaMemcpy(Dist, dDist, sizeof(int) * n * n, cudaMemcpyDeviceToHost);
cudaFree(dDist);
cudaFree(dPivot);
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
updateMin(D(i, j), D(i, k) + D(k, j));
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
updateMin(Dij, Dik + Dkj);
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
int block_total = block_width * block_height;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
cudaStream_t stm = getIdleStream();
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, dDist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, dDist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} | .file "tmpxft_0002c1fd_00000000-6_HW4_x1054037_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4054:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZNSt6vectorIP11CUstream_stSaIS1_EED2Ev,"axG",@progbits,_ZNSt6vectorIP11CUstream_stSaIS1_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIP11CUstream_stSaIS1_EED2Ev
.type _ZNSt6vectorIP11CUstream_stSaIS1_EED2Ev, @function
_ZNSt6vectorIP11CUstream_stSaIS1_EED2Ev:
.LFB4775:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L6
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L6:
ret
.cfi_endproc
.LFE4775:
.size _ZNSt6vectorIP11CUstream_stSaIS1_EED2Ev, .-_ZNSt6vectorIP11CUstream_stSaIS1_EED2Ev
.weak _ZNSt6vectorIP11CUstream_stSaIS1_EED1Ev
.set _ZNSt6vectorIP11CUstream_stSaIS1_EED1Ev,_ZNSt6vectorIP11CUstream_stSaIS1_EED2Ev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d %d"
.LC2:
.string "%d %d %d"
.text
.globl _Z5inputPci
.type _Z5inputPci, @function
_Z5inputPci:
.LFB4045:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbx
leaq m(%rip), %rcx
leaq realn(%rip), %rdx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl %ebp, %eax
addl realn(%rip), %eax
subl $1, %eax
cltd
idivl %ebp
imull %ebp, %eax
movl %eax, n(%rip)
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, Dist(%rip)
movl $0, %edi
movl $0, %ecx
cmpl $0, n(%rip)
jg .L10
.L11:
movl m(%rip), %eax
subl $1, %eax
movl %eax, m(%rip)
js .L9
leaq .LC2(%rip), %rbp
.L18:
leaq 16(%rsp), %rcx
leaq 12(%rsp), %rdx
leaq 20(%rsp), %r8
movq %rbp, %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %eax
subl $1, %eax
imull n(%rip), %eax
movl 16(%rsp), %edx
leal -1(%rax,%rdx), %eax
cltq
movl 20(%rsp), %ecx
movq Dist(%rip), %rdx
movl %ecx, (%rdx,%rax,4)
movl m(%rip), %eax
subl $1, %eax
movl %eax, m(%rip)
jns .L18
.L9:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq Dist(%rip), %rsi
movl $10000000, (%rsi,%rdx)
.L13:
addl $1, %eax
addq $4, %rdx
cmpl %eax, n(%rip)
jle .L27
.L14:
cmpl %eax, %ecx
jne .L12
movq Dist(%rip), %rsi
movl $0, (%rsi,%rdx)
jmp .L13
.L27:
addl %eax, %edi
.L16:
addl $1, %ecx
cmpl %ecx, n(%rip)
jle .L11
.L10:
movslq %edi, %rdx
salq $2, %rdx
movl $0, %eax
cmpl $0, n(%rip)
jg .L14
jmp .L16
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4045:
.size _Z5inputPci, .-_Z5inputPci
.section .rodata.str1.1
.LC3:
.string "w"
.LC4:
.string "INF "
.LC5:
.string "%d "
.LC6:
.string "\n"
.text
.globl _Z6outputPc
.type _Z6outputPc, @function
_Z6outputPc:
.LFB4046:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC3(%rip), %rsi
call fopen@PLT
movq %rax, %r12
movl $0, %ebp
leaq .LC5(%rip), %r14
leaq .LC4(%rip), %r13
leaq .LC6(%rip), %r15
cmpl $0, realn(%rip)
jg .L29
.L30:
movq Dist(%rip), %rdi
testq %rdi, %rdi
je .L28
call _ZdaPv@PLT
.L28:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L32:
addl $1, %ebx
cmpl %ebx, realn(%rip)
jle .L34
.L33:
movl %ebp, %eax
imull n(%rip), %eax
addl %ebx, %eax
cltq
movq Dist(%rip), %rdx
movl (%rdx,%rax,4), %ecx
cmpl $9999999, %ecx
jle .L31
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L32
.L34:
movq %r15, %rdx
movl $2, %esi
movq %r12, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl %ebp, realn(%rip)
jle .L30
.L29:
movl $0, %ebx
cmpl $0, realn(%rip)
jg .L33
jmp .L34
.cfi_endproc
.LFE4046:
.size _Z6outputPc, .-_Z6outputPc
.globl _Z5printv
.type _Z5printv, @function
_Z5printv:
.LFB4047:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $0, %ebp
leaq .LC5(%rip), %r13
leaq .LC4(%rip), %r12
leaq .LC6(%rip), %r14
cmpl $0, realn(%rip)
jg .L43
.L44:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq %r13, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L46:
addl $1, %ebx
cmpl %ebx, realn(%rip)
jle .L48
.L47:
movl %ebp, %eax
imull n(%rip), %eax
addl %ebx, %eax
cltq
movq Dist(%rip), %rdx
movl (%rdx,%rax,4), %ecx
cmpl $9999999, %ecx
jle .L45
movq %r12, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L46
.L48:
movq %r14, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addl $1, %ebp
cmpl %ebp, realn(%rip)
jle .L44
.L43:
movl $0, %ebx
cmpl $0, realn(%rip)
jg .L47
jmp .L48
.cfi_endproc
.LFE4047:
.size _Z5printv, .-_Z5printv
.globl _Z33__device_stub__Z11UpdateIKJ32iPiiiPii
.type _Z33__device_stub__Z11UpdateIKJ32iPiiiPii, @function
_Z33__device_stub__Z11UpdateIKJ32iPiiiPii:
.LFB4076:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11UpdateIKJ32iPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4076:
.size _Z33__device_stub__Z11UpdateIKJ32iPiiiPii, .-_Z33__device_stub__Z11UpdateIKJ32iPiiiPii
.globl _Z11UpdateIKJ32iPii
.type _Z11UpdateIKJ32iPii, @function
_Z11UpdateIKJ32iPii:
.LFB4077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11UpdateIKJ32iPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4077:
.size _Z11UpdateIKJ32iPii, .-_Z11UpdateIKJ32iPii
.globl _Z32__device_stub__Z10UpdateIK32iPiiiPii
.type _Z32__device_stub__Z10UpdateIK32iPiiiPii, @function
_Z32__device_stub__Z10UpdateIK32iPiiiPii:
.LFB4078:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L67
.L63:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10UpdateIK32iPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L63
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4078:
.size _Z32__device_stub__Z10UpdateIK32iPiiiPii, .-_Z32__device_stub__Z10UpdateIK32iPiiiPii
.globl _Z10UpdateIK32iPii
.type _Z10UpdateIK32iPii, @function
_Z10UpdateIK32iPii:
.LFB4079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10UpdateIK32iPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4079:
.size _Z10UpdateIK32iPii, .-_Z10UpdateIK32iPii
.globl _Z32__device_stub__Z10UpdateKJ32iPiiiPii
.type _Z32__device_stub__Z10UpdateKJ32iPiiiPii, @function
_Z32__device_stub__Z10UpdateKJ32iPiiiPii:
.LFB4080:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10UpdateKJ32iPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4080:
.size _Z32__device_stub__Z10UpdateKJ32iPiiiPii, .-_Z32__device_stub__Z10UpdateKJ32iPiiiPii
.globl _Z10UpdateKJ32iPii
.type _Z10UpdateKJ32iPii, @function
_Z10UpdateKJ32iPii:
.LFB4081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10UpdateKJ32iPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4081:
.size _Z10UpdateKJ32iPii, .-_Z10UpdateKJ32iPii
.globl _Z29__device_stub__Z8Update32iPiiiPii
.type _Z29__device_stub__Z8Update32iPiiiPii, @function
_Z29__device_stub__Z8Update32iPiiiPii:
.LFB4082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L83
.L79:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L84
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L83:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8Update32iPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L79
.L84:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4082:
.size _Z29__device_stub__Z8Update32iPiiiPii, .-_Z29__device_stub__Z8Update32iPiiiPii
.globl _Z8Update32iPii
.type _Z8Update32iPii, @function
_Z8Update32iPii:
.LFB4083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8Update32iPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4083:
.size _Z8Update32iPii, .-_Z8Update32iPii
.globl _Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
.type _Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii, @function
_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii:
.LFB4084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L91
.L87:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L92
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L91:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6UpdateiiiiiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L87
.L92:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4084:
.size _Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii, .-_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
.globl _Z6UpdateiiiiiPii
.type _Z6UpdateiiiiiPii, @function
_Z6UpdateiiiiiPii:
.LFB4085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4085:
.size _Z6UpdateiiiiiPii, .-_Z6UpdateiiiiiPii
.globl _Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
.type _Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii, @function
_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii:
.LFB4086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L99
.L95:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L100
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L99:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17UpdateIndependentiiiiiiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L95
.L100:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4086:
.size _Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii, .-_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
.globl _Z17UpdateIndependentiiiiiiPii
.type _Z17UpdateIndependentiiiiiiPii, @function
_Z17UpdateIndependentiiiiiiPii:
.LFB4087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4087:
.size _Z17UpdateIndependentiiiiiiPii, .-_Z17UpdateIndependentiiiiiiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z17UpdateIndependentiiiiiiPii"
.section .rodata.str1.1
.LC8:
.string "_Z6UpdateiiiiiPii"
.LC9:
.string "_Z8Update32iPii"
.LC10:
.string "_Z10UpdateKJ32iPii"
.LC11:
.string "_Z10UpdateIK32iPii"
.LC12:
.string "_Z11UpdateIKJ32iPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z17UpdateIndependentiiiiiiPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6UpdateiiiiiPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z8Update32iPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10UpdateKJ32iPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10UpdateIK32iPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11UpdateIKJ32iPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.str1.1,"aMS",@progbits,1
.LC13:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,"axG",@progbits,_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.type _ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, @function
_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_:
.LFB4555:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L122
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L108
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L109
jmp .L116
.L122:
leaq .LC13(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L123:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L111
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L115
.L108:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L116:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L109:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L123
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L113
.L111:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L113:
addq %rbp, %r15
testq %r13, %r13
je .L114
movq 16(%rbx), %rsi
subq %r13, %rsi
.L115:
movq %r13, %rdi
call _ZdlPvm@PLT
.L114:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4555:
.size _ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, .-_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.text
.globl _Z8calAsynciiiiii
.type _Z8calAsynciiiiii, @function
_Z8calAsynciiiiii:
.LFB4051:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %esi, %eax
movl %edx, %r13d
movq %fs:40, %rdx
movq %rdx, 120(%rsp)
xorl %edx, %edx
addl %r13d, %r9d
leal (%rcx,%r8), %esi
movl %esi, 32(%rsp)
cmpl %r9d, %r13d
jge .L124
movl %edi, %esi
imull %eax, %esi
movl %esi, 20(%rsp)
addl $1, %eax
imull %edi, %eax
movl %eax, 44(%rsp)
leal 62(%rdi), %eax
movl %edi, %edx
addl $31, %edx
cmovns %edx, %eax
sarl $5, %eax
movl %eax, 48(%rsp)
movl %r13d, %eax
imull %edi, %eax
movl %ecx, %ebp
imull %edi, %ebp
leaq 88(%rsp), %rsi
movq %rsi, 64(%rsp)
movl %r9d, 72(%rsp)
movl %eax, %edx
movl %ebp, 76(%rsp)
movl %r13d, %eax
movl %ecx, 52(%rsp)
jmp .L126
.L145:
movq 64(%rsp), %rdi
call cudaStreamCreate@PLT
movq 8+streams(%rip), %rsi
cmpq 16+streams(%rip), %rsi
je .L128
movq 88(%rsp), %rax
movq %rax, (%rsi)
addq $8, 8+streams(%rip)
.L129:
addl $1, streamSize(%rip)
movq 88(%rsp), %r13
jmp .L130
.L128:
movq 64(%rsp), %rdx
leaq streams(%rip), %rdi
call _ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
jmp .L129
.L140:
movl 20(%rsp), %ebp
cmpl %ebx, %ebp
jl .L135
.L133:
movl 32(%rsp), %eax
cmpl %eax, %r15d
je .L144
.L136:
movl n(%rip), %ebx
movl 36(%rsp), %eax
cmpl %eax, %ebx
movl %eax, %r14d
cmovle %ebx, %r14d
movl %r12d, %edi
movl %r12d, 12(%rsp)
addl $1, %r15d
movl 28(%rsp), %eax
addl %eax, %r12d
cmpl %ebx, %r12d
movl %ebx, %eax
cmovle %r12d, %eax
movl %eax, 16(%rsp)
movl 44(%rsp), %eax
cmpl %eax, %ebx
cmovg %eax, %ebx
movl 20(%rsp), %eax
cmpl %eax, %edi
sete %bpl
movl 48(%rsp), %eax
movl %eax, 96(%rsp)
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $32, 108(%rsp)
movl $32, 112(%rsp)
movl $1, 116(%rsp)
movq streams(%rip), %rcx
movl streamSize(%rip), %edx
movslq %edx, %rsi
movq 8+streams(%rip), %rax
subq %rcx, %rax
sarq $3, %rax
cmpq %rsi, %rax
je .L145
addl $1, %edx
movl %edx, streamSize(%rip)
movq (%rcx,%rsi,8), %r13
.L130:
cmpb $0, 43(%rsp)
jne .L140
testb %bpl, %bpl
jne .L140
movl 116(%rsp), %ecx
movq %r13, %r9
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L133
movl n(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 200
pushq dDist(%rip)
.cfi_def_cfa_offset 208
movl 32(%rsp), %r9d
movl %r14d, %r8d
movl 28(%rsp), %ecx
movl 40(%rsp), %edx
movl %ebx, %esi
movl 36(%rsp), %edi
call _Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L133
.L134:
addl $1, %ebp
cmpl %ebp, %ebx
je .L133
.L135:
movl 116(%rsp), %ecx
movq %r13, %r9
movl $0, %r8d
movq 108(%rsp), %rdx
movq 96(%rsp), %rdi
movl 104(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L134
subq $8, %rsp
.cfi_def_cfa_offset 200
movl n(%rip), %eax
pushq %rax
.cfi_def_cfa_offset 208
movq dDist(%rip), %r9
movl 32(%rsp), %r8d
movl %r14d, %ecx
movl 28(%rsp), %edx
movl 40(%rsp), %esi
movl %ebp, %edi
call _Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L134
.L144:
movl 56(%rsp), %edx
movl 28(%rsp), %edi
movl 60(%rsp), %eax
.L138:
addl $1, %eax
addl %edi, %edx
cmpl %eax, 72(%rsp)
je .L124
.L126:
movl 32(%rsp), %ebx
cmpl %ebx, 52(%rsp)
jge .L138
movl %edx, 24(%rsp)
leal (%rdi,%rdx), %esi
movl %esi, 36(%rsp)
movl 20(%rsp), %esi
cmpl %esi, %edx
sete 43(%rsp)
movl 76(%rsp), %r12d
movl 52(%rsp), %r14d
movl %r14d, %r15d
movl %edx, 56(%rsp)
movl %edi, 28(%rsp)
movl %eax, 60(%rsp)
jmp .L136
.L124:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L146
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L146:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4051:
.size _Z8calAsynciiiiii, .-_Z8calAsynciiiiii
.globl _Z8block_FWi
.type _Z8block_FWi, @function
_Z8block_FWi:
.LFB4050:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq n(%rip), %rsi
imulq %rsi, %rsi
salq $2, %rsi
leaq dDist(%rip), %rdi
call cudaMalloc@PLT
movslq %r12d, %rsi
imulq %rsi, %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movslq n(%rip), %rdx
imulq %rdx, %rdx
salq $2, %rdx
movl $1, %ecx
movq Dist(%rip), %rsi
movq dDist(%rip), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
addl n(%rip), %eax
subl $1, %eax
cltd
idivl %r12d
movl %eax, %r14d
cmpl $32, %r12d
je .L148
movl $0, %ebx
leal -1(%rax), %r15d
testl %eax, %eax
jle .L150
.L149:
movl $1, %r9d
movl $1, %r8d
movl %ebx, %ecx
movl %ebx, %edx
movl %ebx, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
call cudaThreadSynchronize@PLT
movl $0, streamSize(%rip)
movl $1, %r9d
movl %ebx, %r8d
movl $0, %ecx
movl %ebx, %edx
movl %ebx, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
movl %r15d, %r13d
subl %ebx, %r13d
movl %ebx, %ebp
addl $1, %ebx
movl $1, %r9d
movl %r13d, %r8d
movl %ebx, %ecx
movl %ebp, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
movl %ebp, %r9d
movl $1, %r8d
movl %ebp, %ecx
movl $0, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
movl %r13d, %r9d
movl $1, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
call cudaThreadSynchronize@PLT
movl $0, streamSize(%rip)
movl %ebp, %r9d
movl %ebp, %r8d
movl $0, %ecx
movl $0, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
movl %ebp, %r9d
movl %r13d, %r8d
movl %ebx, %ecx
movl $0, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
movl %r13d, %r9d
movl %ebp, %r8d
movl $0, %ecx
movl %ebx, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
movl %r13d, %r9d
movl %r13d, %r8d
movl %ebx, %ecx
movl %ebx, %edx
movl %ebp, %esi
movl %r12d, %edi
call _Z8calAsynciiiiii
call cudaThreadSynchronize@PLT
movl $0, streamSize(%rip)
cmpl %r14d, %ebx
jne .L149
.L150:
movslq n(%rip), %rdx
imulq %rdx, %rdx
salq $2, %rdx
movl $2, %ecx
movq dDist(%rip), %rsi
movq Dist(%rip), %rdi
call cudaMemcpy@PLT
movq dDist(%rip), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L170
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L148:
.cfi_restore_state
testl %eax, %eax
jle .L150
movl $0, %ebx
leaq 24(%rsp), %rbp
jmp .L163
.L171:
movl n(%rip), %edx
movq dDist(%rip), %rsi
movl %ebx, %edi
call _Z33__device_stub__Z11UpdateIKJ32iPiiiPii
jmp .L151
.L172:
movq %rbp, %rdi
call cudaStreamCreate@PLT
movq 8+streams(%rip), %rsi
cmpq 16+streams(%rip), %rsi
je .L153
movq 24(%rsp), %rax
movq %rax, (%rsi)
addq $8, 8+streams(%rip)
.L154:
addl $1, streamSize(%rip)
movq 24(%rsp), %r9
jmp .L155
.L153:
leaq 24(%rsp), %rdx
leaq streams(%rip), %rdi
call _ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
jmp .L154
.L173:
movl n(%rip), %edx
movq dDist(%rip), %rsi
movl %ebx, %edi
call _Z32__device_stub__Z10UpdateIK32iPiiiPii
jmp .L156
.L174:
movq %rbp, %rdi
call cudaStreamCreate@PLT
movq 8+streams(%rip), %rsi
cmpq 16+streams(%rip), %rsi
je .L158
movq 24(%rsp), %rax
movq %rax, (%rsi)
addq $8, 8+streams(%rip)
.L159:
addl $1, streamSize(%rip)
movq 24(%rsp), %r9
jmp .L160
.L158:
leaq 24(%rsp), %rdx
leaq streams(%rip), %rdi
call _ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
jmp .L159
.L175:
movl n(%rip), %edx
movq dDist(%rip), %rsi
movl %ebx, %edi
call _Z32__device_stub__Z10UpdateKJ32iPiiiPii
jmp .L161
.L162:
addl $1, %ebx
cmpl %r14d, %ebx
je .L150
.L163:
movl $32, 12(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L171
.L151:
movq streams(%rip), %rcx
movl streamSize(%rip), %edx
movslq %edx, %rsi
movq 8+streams(%rip), %rax
subq %rcx, %rax
sarq $3, %rax
cmpq %rsi, %rax
je .L172
addl $1, %edx
movl %edx, streamSize(%rip)
movq (%rcx,%rsi,8), %r9
.L155:
movl $32, 12(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
leal -1(%r14), %r12d
movl %r12d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L173
.L156:
movq streams(%rip), %rcx
movl streamSize(%rip), %edx
movslq %edx, %rsi
movq 8+streams(%rip), %rax
subq %rcx, %rax
sarq $3, %rax
cmpq %rax, %rsi
je .L174
addl $1, %edx
movl %edx, streamSize(%rip)
movq (%rcx,%rsi,8), %r9
.L160:
movl $32, 12(%rsp)
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl %r12d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L175
.L161:
call cudaThreadSynchronize@PLT
movl $0, streamSize(%rip)
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl %r12d, 12(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 12(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L162
movl n(%rip), %edx
movq dDist(%rip), %rsi
movl %ebx, %edi
call _Z29__device_stub__Z8Update32iPiiiPii
jmp .L162
.L170:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4050:
.size _Z8block_FWi, .-_Z8block_FWi
.globl main
.type main, @function
main:
.LFB4044:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movq 24(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movq 8(%rbx), %rdi
movl %eax, %esi
call _Z5inputPci
movl %ebp, %edi
call _Z8block_FWi
movq 16(%rbx), %rdi
call _Z6outputPc
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4044:
.size main, .-main
.type _GLOBAL__sub_I_realn, @function
_GLOBAL__sub_I_realn:
.LFB4777:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq $0, streams(%rip)
movq $0, 8+streams(%rip)
movq $0, 16+streams(%rip)
leaq __dso_handle(%rip), %rdx
leaq streams(%rip), %rsi
leaq _ZNSt6vectorIP11CUstream_stSaIS1_EED1Ev(%rip), %rdi
call __cxa_atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4777:
.size _GLOBAL__sub_I_realn, .-_GLOBAL__sub_I_realn
.section .init_array
.align 8
.quad _GLOBAL__sub_I_realn
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl streams
.bss
.align 16
.type streams, @object
.size streams, 24
streams:
.zero 24
.globl streamSize
.align 4
.type streamSize, @object
.size streamSize, 4
streamSize:
.zero 4
.globl dDist
.align 8
.type dDist, @object
.size dDist, 8
dDist:
.zero 8
.globl Dist
.align 8
.type Dist, @object
.size Dist, 8
Dist:
.zero 8
.globl m
.align 4
.type m, @object
.size m, 4
m:
.zero 4
.globl n
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl realn
.align 4
.type realn, @object
.size realn, 4
realn:
.zero 4
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW(int B);
int ceil(int a, int b);
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist; // n * n, on device
int streamSize;
vector<cudaStream_t> streams;
inline cudaStream_t getIdleStream ()
{
if(streams.size() == streamSize)
{
cudaStream_t stm;
cudaStreamCreate(&stm);
streams.push_back(stm);
streamSize++;
return stm;
}
else
return streams[streamSize++];
}
inline void syncAllStreams ()
{
cudaThreadSynchronize();
streamSize = 0;
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
// if(B > n)
// {
// B = n;
// cerr << "Warning: B > n. Set B = n.";
// }
block_FW(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
Dist = new int[n * n];
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
delete[] Dist;
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
inline int ceil(int a, int b)
{
return (a + b -1)/b;
}
inline __device__
void updateMin (int &x, int a)
{
if(a < x) x = a;
}
__global__
void UpdateIKJ32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int i = r * 32 + tx;
int j = r * 32 + ty;
__shared__ int S[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S[tx][ty], S[tx][k] + S[k][ty]);
__syncthreads();
}
D(i, j) = S[tx][ty];
#undef D
}
__global__
void UpdateIK32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int by = blockIdx.x;
if(by >= r) by++;
int i = r * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r*32 + ty);
S1[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S1[tx][ty], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S1[tx][ty];
#undef D
}
__global__
void UpdateKJ32 (int r, int* dDist, int n)
// 0 --update--> 1
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
if(bx >= r) bx++;
int i = bx * 32 + tx;
int j = r * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, j);
S1[tx][ty] = D(r*32 + tx, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S0[ty][tx], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S0[ty][tx];
#undef D
}
__global__
void Update32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= r) bx++;
if(by >= r) by++;
int i = bx * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r * 32 + ty);
S1[tx][ty] = D(r * 32 + tx, j);
__syncthreads();
int Dij = D(i, j);
for(int k=0; k<32; ++k)
{
updateMin(Dij, S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = Dij;
#undef D
}
void block_FW(int B)
{
int *dPivot;
cudaMalloc(&dDist, sizeof(int) * n * n);
cudaMalloc(&dPivot, sizeof(int) * B * B);
cudaMemcpy(dDist, Dist, sizeof(int) * n * n, cudaMemcpyHostToDevice);
int round = ceil(n, B);
if(B == 32)
{
for (int r = 0; r < round; ++r)
{
/* Phase 1*/
UpdateIKJ32 <<< 1, dim3(32,32) >>> (r, dDist, n);
/* Phase 2*/
UpdateIK32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
UpdateKJ32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
syncAllStreams();
/* Phase 3*/
Update32 <<< dim3(round-1, round-1), dim3(32,32) >>> (r, dDist, n);
}
}
else
for (int r = 0; r < round; ++r) {
/* Phase 1*/
calAsync(B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(B, r, r, 0, r, 1);
calAsync(B, r, r, r +1, round - r -1, 1);
calAsync(B, r, 0, r, 1, r);
calAsync(B, r, r +1, r, 1, round - r -1);
syncAllStreams();
/* Phase 3*/
calAsync(B, r, 0, 0, r, r);
calAsync(B, r, 0, r +1, round -r -1, r);
calAsync(B, r, r +1, 0, r, round - r -1);
calAsync(B, r, r +1, r +1, round -r -1, round - r -1);
syncAllStreams();
}
cudaMemcpy(Dist, dDist, sizeof(int) * n * n, cudaMemcpyDeviceToHost);
cudaFree(dDist);
cudaFree(dPivot);
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
updateMin(D(i, j), D(i, k) + D(k, j));
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
updateMin(Dij, Dik + Dkj);
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
int block_total = block_width * block_height;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
cudaStream_t stm = getIdleStream();
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, dDist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, dDist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW(int B);
int ceil(int a, int b);
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist; // n * n, on device
int streamSize;
vector<hipStream_t> streams;
inline hipStream_t getIdleStream ()
{
if(streams.size() == streamSize)
{
hipStream_t stm;
hipStreamCreate(&stm);
streams.push_back(stm);
streamSize++;
return stm;
}
else
return streams[streamSize++];
}
inline void syncAllStreams ()
{
hipDeviceSynchronize();
streamSize = 0;
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
// if(B > n)
// {
// B = n;
// cerr << "Warning: B > n. Set B = n.";
// }
block_FW(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
Dist = new int[n * n];
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
delete[] Dist;
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
inline int ceil(int a, int b)
{
return (a + b -1)/b;
}
inline __device__
void updateMin (int &x, int a)
{
if(a < x) x = a;
}
__global__
void UpdateIKJ32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int i = r * 32 + tx;
int j = r * 32 + ty;
__shared__ int S[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S[tx][ty], S[tx][k] + S[k][ty]);
__syncthreads();
}
D(i, j) = S[tx][ty];
#undef D
}
__global__
void UpdateIK32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int by = blockIdx.x;
if(by >= r) by++;
int i = r * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r*32 + ty);
S1[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S1[tx][ty], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S1[tx][ty];
#undef D
}
__global__
void UpdateKJ32 (int r, int* dDist, int n)
// 0 --update--> 1
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
if(bx >= r) bx++;
int i = bx * 32 + tx;
int j = r * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, j);
S1[tx][ty] = D(r*32 + tx, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S0[ty][tx], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S0[ty][tx];
#undef D
}
__global__
void Update32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= r) bx++;
if(by >= r) by++;
int i = bx * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r * 32 + ty);
S1[tx][ty] = D(r * 32 + tx, j);
__syncthreads();
int Dij = D(i, j);
for(int k=0; k<32; ++k)
{
updateMin(Dij, S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = Dij;
#undef D
}
void block_FW(int B)
{
int *dPivot;
hipMalloc(&dDist, sizeof(int) * n * n);
hipMalloc(&dPivot, sizeof(int) * B * B);
hipMemcpy(dDist, Dist, sizeof(int) * n * n, hipMemcpyHostToDevice);
int round = ceil(n, B);
if(B == 32)
{
for (int r = 0; r < round; ++r)
{
/* Phase 1*/
UpdateIKJ32 <<< 1, dim3(32,32) >>> (r, dDist, n);
/* Phase 2*/
UpdateIK32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
UpdateKJ32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
syncAllStreams();
/* Phase 3*/
Update32 <<< dim3(round-1, round-1), dim3(32,32) >>> (r, dDist, n);
}
}
else
for (int r = 0; r < round; ++r) {
/* Phase 1*/
calAsync(B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(B, r, r, 0, r, 1);
calAsync(B, r, r, r +1, round - r -1, 1);
calAsync(B, r, 0, r, 1, r);
calAsync(B, r, r +1, r, 1, round - r -1);
syncAllStreams();
/* Phase 3*/
calAsync(B, r, 0, 0, r, r);
calAsync(B, r, 0, r +1, round -r -1, r);
calAsync(B, r, r +1, 0, r, round - r -1);
calAsync(B, r, r +1, r +1, round -r -1, round - r -1);
syncAllStreams();
}
hipMemcpy(Dist, dDist, sizeof(int) * n * n, hipMemcpyDeviceToHost);
hipFree(dDist);
hipFree(dPivot);
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
updateMin(D(i, j), D(i, k) + D(k, j));
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
updateMin(Dij, Dik + Dkj);
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
int block_total = block_width * block_height;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
hipStream_t stm = getIdleStream();
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, dDist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, dDist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW(int B);
int ceil(int a, int b);
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist; // n * n, on device
int streamSize;
vector<hipStream_t> streams;
inline hipStream_t getIdleStream ()
{
if(streams.size() == streamSize)
{
hipStream_t stm;
hipStreamCreate(&stm);
streams.push_back(stm);
streamSize++;
return stm;
}
else
return streams[streamSize++];
}
inline void syncAllStreams ()
{
hipDeviceSynchronize();
streamSize = 0;
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
// if(B > n)
// {
// B = n;
// cerr << "Warning: B > n. Set B = n.";
// }
block_FW(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
Dist = new int[n * n];
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
delete[] Dist;
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
inline int ceil(int a, int b)
{
return (a + b -1)/b;
}
inline __device__
void updateMin (int &x, int a)
{
if(a < x) x = a;
}
__global__
void UpdateIKJ32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int i = r * 32 + tx;
int j = r * 32 + ty;
__shared__ int S[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S[tx][ty], S[tx][k] + S[k][ty]);
__syncthreads();
}
D(i, j) = S[tx][ty];
#undef D
}
__global__
void UpdateIK32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int by = blockIdx.x;
if(by >= r) by++;
int i = r * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r*32 + ty);
S1[tx][ty] = D(i, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S1[tx][ty], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S1[tx][ty];
#undef D
}
__global__
void UpdateKJ32 (int r, int* dDist, int n)
// 0 --update--> 1
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
if(bx >= r) bx++;
int i = bx * 32 + tx;
int j = r * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, j);
S1[tx][ty] = D(r*32 + tx, j);
__syncthreads();
for(int k=0; k<32; ++k)
{
updateMin(S0[ty][tx], S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = S0[ty][tx];
#undef D
}
__global__
void Update32 (int r, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int bx = blockIdx.x;
int by = blockIdx.y;
if(bx >= r) bx++;
if(by >= r) by++;
int i = bx * 32 + tx;
int j = by * 32 + ty;
__shared__ int S0[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int S1[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
S0[ty][tx] = D(i, r * 32 + ty);
S1[tx][ty] = D(r * 32 + tx, j);
__syncthreads();
int Dij = D(i, j);
for(int k=0; k<32; ++k)
{
updateMin(Dij, S0[k][tx] + S1[k][ty]);
__syncthreads();
}
D(i, j) = Dij;
#undef D
}
void block_FW(int B)
{
int *dPivot;
hipMalloc(&dDist, sizeof(int) * n * n);
hipMalloc(&dPivot, sizeof(int) * B * B);
hipMemcpy(dDist, Dist, sizeof(int) * n * n, hipMemcpyHostToDevice);
int round = ceil(n, B);
if(B == 32)
{
for (int r = 0; r < round; ++r)
{
/* Phase 1*/
UpdateIKJ32 <<< 1, dim3(32,32) >>> (r, dDist, n);
/* Phase 2*/
UpdateIK32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
UpdateKJ32 <<< round-1, dim3(32,32), 0, getIdleStream() >>> (r, dDist, n);
syncAllStreams();
/* Phase 3*/
Update32 <<< dim3(round-1, round-1), dim3(32,32) >>> (r, dDist, n);
}
}
else
for (int r = 0; r < round; ++r) {
/* Phase 1*/
calAsync(B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(B, r, r, 0, r, 1);
calAsync(B, r, r, r +1, round - r -1, 1);
calAsync(B, r, 0, r, 1, r);
calAsync(B, r, r +1, r, 1, round - r -1);
syncAllStreams();
/* Phase 3*/
calAsync(B, r, 0, 0, r, r);
calAsync(B, r, 0, r +1, round -r -1, r);
calAsync(B, r, r +1, 0, r, round - r -1);
calAsync(B, r, r +1, r +1, round -r -1, round - r -1);
syncAllStreams();
}
hipMemcpy(Dist, dDist, sizeof(int) * n * n, hipMemcpyDeviceToHost);
hipFree(dDist);
hipFree(dPivot);
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
updateMin(D(i, j), D(i, k) + D(k, j));
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
updateMin(Dij, Dik + Dkj);
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
int block_total = block_width * block_height;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
hipStream_t stm = getIdleStream();
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, dDist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, dDist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11UpdateIKJ32iPii
.globl _Z11UpdateIKJ32iPii
.p2align 8
.type _Z11UpdateIKJ32iPii,@function
_Z11UpdateIKJ32iPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v4, 7, v3
s_waitcnt lgkmcnt(0)
s_lshl_b32 s2, s2, 5
v_add_nc_u32_e32 v1, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s3
v_add3_u32 v0, s2, v2, v1
v_lshlrev_b32_e32 v2, 2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v3, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v2, 0x80, v2
s_add_i32 s0, s0, 4
s_waitcnt lgkmcnt(0)
s_cmpk_eq_i32 s0, 0x80
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_4
.LBB0_2:
v_add_nc_u32_e32 v5, s0, v4
s_mov_b32 s1, exec_lo
ds_load_b32 v6, v2
ds_load_b32 v5, v5
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v6, v5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v7, v5
s_cbranch_execz .LBB0_1
ds_store_b32 v3, v5
s_branch .LBB0_1
.LBB0_4:
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11UpdateIKJ32iPii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11UpdateIKJ32iPii, .Lfunc_end0-_Z11UpdateIKJ32iPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10UpdateIK32iPii
.globl _Z10UpdateIK32iPii
.p2align 8
.type _Z10UpdateIK32iPii,@function
_Z10UpdateIK32iPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
v_and_b32_e32 v7, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s4, s15, 0
s_lshl_b32 s2, s2, 5
v_add_nc_u32_e32 v2, s2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v2, s3, v[4:5]
v_add_nc_u32_e32 v1, s2, v0
v_lshl_add_u32 v5, s4, 5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[0:1], off
v_lshlrev_b32_e32 v2, 2, v7
v_lshl_or_b32 v3, v4, 2, 0x1000
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v8, v4, 7, v2
v_lshl_add_u32 v4, v7, 7, v3
s_waitcnt vmcnt(1)
ds_store_b32 v8, v5
s_waitcnt vmcnt(0)
ds_store_b32 v4, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s1
s_addk_i32 s0, 0x80
s_waitcnt lgkmcnt(0)
s_cmpk_eq_i32 s0, 0x1000
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_4
.LBB1_2:
v_add_nc_u32_e32 v5, s0, v3
v_add_nc_u32_e32 v6, s0, v2
s_mov_b32 s1, exec_lo
ds_load_b32 v5, v5
ds_load_b32 v6, v6
ds_load_b32 v7, v4
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v5, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v7, v5
s_cbranch_execz .LBB1_1
ds_store_b32 v4, v5
s_branch .LBB1_1
.LBB1_4:
ds_load_b32 v2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10UpdateIK32iPii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10UpdateIK32iPii, .Lfunc_end1-_Z10UpdateIK32iPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10UpdateKJ32iPii
.globl _Z10UpdateKJ32iPii
.p2align 8
.type _Z10UpdateKJ32iPii,@function
_Z10UpdateKJ32iPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
v_and_b32_e32 v5, 0x3ff, v0
v_bfe_u32 v6, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s4, s15, 0
s_lshl_b32 s2, s2, 5
v_lshl_add_u32 v3, s4, 5, v5
v_add_nc_u32_e32 v0, s2, v6
v_add_nc_u32_e32 v7, s2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v3, s3, v[0:1]
v_mad_u64_u32 v[3:4], null, v7, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_lshl_or_b32 v4, v6, 2, 0x1000
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_b32 v7, v[0:1], off
global_load_b32 v8, v[2:3], off
v_lshlrev_b32_e32 v2, 2, v5
v_lshl_add_u32 v5, v5, 7, v4
s_mov_b32 s0, 0
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v3, v6, 7, v2
s_waitcnt vmcnt(1)
ds_store_b32 v3, v7
s_waitcnt vmcnt(0)
ds_store_b32 v5, v8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s1
s_addk_i32 s0, 0x80
s_waitcnt lgkmcnt(0)
s_cmpk_eq_i32 s0, 0x1000
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_4
.LBB2_2:
v_add_nc_u32_e32 v5, s0, v4
v_add_nc_u32_e32 v6, s0, v2
s_mov_b32 s1, exec_lo
ds_load_b32 v5, v5
ds_load_b32 v6, v6
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v5, v5, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 v7, v5
s_cbranch_execz .LBB2_1
ds_store_b32 v3, v5
s_branch .LBB2_1
.LBB2_4:
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10UpdateKJ32iPii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10UpdateKJ32iPii, .Lfunc_end2-_Z10UpdateKJ32iPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8Update32iPii
.globl _Z8Update32iPii
.p2align 8
.type _Z8Update32iPii,@function
_Z8Update32iPii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x8
v_and_b32_e32 v5, 0x3ff, v0
v_bfe_u32 v6, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s2
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s4, 0
s_addc_u32 s4, s14, 0
s_cmp_ge_i32 s15, s2
v_lshl_add_u32 v1, s4, 5, v5
s_cselect_b32 s4, -1, 0
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mul_lo_u32 v7, v1, s3
s_addc_u32 s4, s15, 0
s_lshl_b32 s2, s2, 5
v_lshl_add_u32 v0, s4, 5, v6
v_add_nc_u32_e32 v2, s2, v5
v_add3_u32 v1, s2, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, v7, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v8, v[1:2], off
global_load_b32 v4, v[3:4], off
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b32_e32 v2, 2, v5
v_lshl_or_b32 v3, v6, 2, 0x1000
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshl_add_u32 v6, v6, 7, v2
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v5, v5, 7, v3
s_waitcnt vmcnt(1)
ds_store_b32 v6, v8
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v4, v[0:1], off
s_mov_b32 s0, 0
.LBB3_1:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s0, v2
v_add_nc_u32_e32 v6, s0, v3
s_addk_i32 s0, 0x80
ds_load_b32 v5, v5
ds_load_b32 v6, v6
s_cmpk_eq_i32 s0, 0x1000
s_waitcnt vmcnt(0) lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v4, v4, v5
s_cbranch_scc0 .LBB3_1
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8Update32iPii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z8Update32iPii, .Lfunc_end3-_Z8Update32iPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6UpdateiiiiiPii
.globl _Z6UpdateiiiiiPii
.p2align 8
.type _Z6UpdateiiiiiPii,@function
_Z6UpdateiiiiiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add3_u32 v1, s14, s4, v1
v_add3_u32 v0, s15, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v1
v_cmp_gt_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB4_3
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s2
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, v4, v0
v_add_nc_u32_e32 v5, s3, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_clause 0x2
global_load_b32 v2, v[4:5], off
global_load_b32 v3, v[6:7], off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, v4, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_3
global_store_b32 v[0:1], v2, off
.LBB4_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6UpdateiiiiiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z6UpdateiiiiiPii, .Lfunc_end4-_Z6UpdateiiiiiPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17UpdateIndependentiiiiiiPii
.globl _Z17UpdateIndependentiiiiiiPii
.p2align 8
.type _Z17UpdateIndependentiiiiiiPii,@function
_Z17UpdateIndependentiiiiiiPii:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x20
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v7, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add3_u32 v5, s14, s8, v7
v_add3_u32 v0, s15, s9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v5
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s2
s_and_saveexec_b32 s4, s8
s_cbranch_execz .LBB5_2
v_mad_u64_u32 v[2:3], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s3, s6, v2
v_add_co_ci_u32_e64 v3, s3, s7, v3, s3
global_load_b32 v6, v[2:3], off
.LBB5_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s5
s_cbranch_scc1 .LBB5_15
v_add_nc_u32_e32 v2, s4, v7
v_lshlrev_b32_e32 v4, 2, v7
v_lshlrev_b32_e32 v9, 2, v1
v_lshlrev_b32_e32 v11, 7, v7
v_add_nc_u32_e32 v12, s9, v1
v_mul_lo_u32 v10, s10, v2
v_mad_u64_u32 v[2:3], null, v5, s10, v[1:2]
v_lshl_add_u32 v8, v1, 7, v4
v_add3_u32 v9, v11, v9, 0x1000
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_4)
v_add3_u32 v3, v12, v10, s15
s_branch .LBB5_5
.LBB5_4:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s0, s1, 1
v_add_nc_u32_e32 v3, s10, v3
s_ashr_i32 s1, s0, 31
s_add_i32 s4, s4, 1
s_lshr_b32 s1, s1, 27
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s0, s1
s_and_not1_b32 s1, s1, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s1, s0, s1
s_cmp_ge_i32 s4, s5
s_cbranch_scc1 .LBB5_15
.LBB5_5:
s_cmp_lg_u32 s1, 0
s_cbranch_scc0 .LBB5_7
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB5_4
s_branch .LBB5_14
.LBB5_7:
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB5_10
v_add_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s5, v4
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB5_10
v_add_nc_u32_e32 v10, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s6, v10
v_add_co_ci_u32_e64 v11, s0, s7, v11, s0
global_load_b32 v4, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB5_10:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB5_13
v_add_nc_u32_e32 v4, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s5, v4
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB5_13
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[3:4]
v_add_co_u32 v10, s0, s6, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s7, v11, s0
global_load_b32 v4, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v4
.LBB5_13:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB5_4
.LBB5_14:
s_lshl_b32 s3, s1, 7
s_delay_alu instid0(SALU_CYCLE_1)
v_lshl_add_u32 v4, v7, 2, s3
v_lshl_add_u32 v10, v1, 2, s3
ds_load_b32 v4, v4
ds_load_b32 v10, v10 offset:4096
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v10, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v6, v6, v4
s_branch .LBB5_4
.LBB5_15:
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB5_17
v_mad_u64_u32 v[1:2], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v6, off
.LBB5_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17UpdateIndependentiiiiiiPii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size _Z17UpdateIndependentiiiiiiPii, .Lfunc_end5-_Z17UpdateIndependentiiiiiiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11UpdateIKJ32iPii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11UpdateIKJ32iPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10UpdateIK32iPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10UpdateIK32iPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10UpdateKJ32iPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10UpdateKJ32iPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8Update32iPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8Update32iPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6UpdateiiiiiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6UpdateiiiiiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17UpdateIndependentiiiiiiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17UpdateIndependentiiiiiiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <iostream>
int main(){
const int N = 108000000;
const int M = 70000000;
thrust :: device_vector <int> D(N, 0);
thrust :: fill(D.begin(), D.end(), 1);
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
thrust::host_vector <int> H(M);
for(int i=0;i<1000;i++){
thrust::sequence(H.begin(), H.begin()+10);
thrust::copy(H.begin(), H.end(), D.begin());
}
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <iostream>
int main(){
const int N = 108000000;
const int M = 70000000;
thrust :: device_vector <int> D(N, 0);
thrust :: fill(D.begin(), D.end(), 1);
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
thrust::host_vector <int> H(M);
for(int i=0;i<1000;i++){
thrust::sequence(H.begin(), H.begin()+10);
thrust::copy(H.begin(), H.end(), D.begin());
}
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <iostream>
int main(){
const int N = 108000000;
const int M = 70000000;
thrust :: device_vector <int> D(N, 0);
thrust :: fill(D.begin(), D.end(), 1);
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
thrust::host_vector <int> H(M);
for(int i=0;i<1000;i++){
thrust::sequence(H.begin(), H.begin()+10);
thrust::copy(H.begin(), H.end(), D.begin());
}
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <iostream>
int main(){
const int N = 108000000;
const int M = 70000000;
thrust :: device_vector <int> D(N, 0);
thrust :: fill(D.begin(), D.end(), 1);
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
thrust::host_vector <int> H(M);
for(int i=0;i<1000;i++){
thrust::sequence(H.begin(), H.begin()+10);
thrust::copy(H.begin(), H.end(), D.begin());
}
for(int i=0;i<10;i++){
std::cout<<"D["<<i<<"]="<<D[i]<<std::endl;
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub6__fill7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04300 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_:
s_load_b128 s[4:7], s[0:1], 0x18
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s6, s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform17unary_transform_fINS_17counting_iteratorIlNS_11use_defaultES6_S6_EENS_6detail15normal_iteratorINS_10device_ptrIiEEEENS3_14no_stencil_tagEZNS0_6fill_nINS0_3tagESC_liEET0_RNS0_16execution_policyIT_EESG_T1_RKT2_EUllE_NS3_21always_true_predicateEEElLj1EEEvSG_SL_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void initvectors(double4 *acc3, float4 *apred){
int i = blockIdx.x*blockDim.x + threadIdx.x;
acc3[i].x = acc3[i].y = acc3[i].z = 0.0;
apred[i].x = apred[i].y = apred[i].z = 0.0f;
} | code for sm_80
Function : _Z11initvectorsP7double4P6float4
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x10 ; /* 0x0000001000077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0207 */
/*0090*/ STG.E.64 [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101b04 */
/*00a0*/ STG.E.128 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101d04 */
/*00b0*/ STG.E [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101904 */
/*00c0*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void initvectors(double4 *acc3, float4 *apred){
int i = blockIdx.x*blockDim.x + threadIdx.x;
acc3[i].x = acc3[i].y = acc3[i].z = 0.0;
apred[i].x = apred[i].y = apred[i].z = 0.0f;
} | .file "tmpxft_000476ae_00000000-6_initvectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4
.type _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4, @function
_Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11initvectorsP7double4P6float4(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4, .-_Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4
.globl _Z11initvectorsP7double4P6float4
.type _Z11initvectorsP7double4P6float4, @function
_Z11initvectorsP7double4P6float4:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11initvectorsP7double4P6float4, .-_Z11initvectorsP7double4P6float4
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11initvectorsP7double4P6float4"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11initvectorsP7double4P6float4(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void initvectors(double4 *acc3, float4 *apred){
int i = blockIdx.x*blockDim.x + threadIdx.x;
acc3[i].x = acc3[i].y = acc3[i].z = 0.0;
apred[i].x = apred[i].y = apred[i].z = 0.0f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initvectors(double4 *acc3, float4 *apred){
int i = blockIdx.x*blockDim.x + threadIdx.x;
acc3[i].x = acc3[i].y = acc3[i].z = 0.0;
apred[i].x = apred[i].y = apred[i].z = 0.0f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initvectors(double4 *acc3, float4 *apred){
int i = blockIdx.x*blockDim.x + threadIdx.x;
acc3[i].x = acc3[i].y = acc3[i].z = 0.0;
apred[i].x = apred[i].y = apred[i].z = 0.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.globl _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.p2align 8
.type _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE,@function
_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 5, v[2:3]
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v3, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_store_b64 v[4:5], v[0:1], off offset:16
global_store_b128 v[4:5], v[0:3], off
global_store_b96 v[6:7], v[0:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, .Lfunc_end0-_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initvectors(double4 *acc3, float4 *apred){
int i = blockIdx.x*blockDim.x + threadIdx.x;
acc3[i].x = acc3[i].y = acc3[i].z = 0.0;
apred[i].x = apred[i].y = apred[i].z = 0.0f;
} | .text
.file "initvectors.hip"
.globl _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE # -- Begin function _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.p2align 4, 0x90
.type _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE,@function
_Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE: # @_Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, .Lfunc_end0-_Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE,@object # @_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.section .rodata,"a",@progbits
.globl _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.p2align 3, 0x0
_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE:
.quad _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.size _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11initvectorsP7double4P6float4
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.9073486328125e-06 ; /* 0x00000020ff057435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R7, 0x10 ; /* 0x0000001000077802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0080*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0207 */
/*0090*/ STG.E.64 [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101b04 */
/*00a0*/ STG.E.128 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101d04 */
/*00b0*/ STG.E [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101904 */
/*00c0*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.globl _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.p2align 8
.type _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE,@function
_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 5, v[2:3]
v_lshlrev_b64 v[6:7], 4, v[2:3]
v_mov_b32_e32 v2, v0
v_mov_b32_e32 v3, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_store_b64 v[4:5], v[0:1], off offset:16
global_store_b128 v[4:5], v[0:3], off
global_store_b96 v[6:7], v[0:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, .Lfunc_end0-_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000476ae_00000000-6_initvectors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4
.type _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4, @function
_Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11initvectorsP7double4P6float4(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4, .-_Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4
.globl _Z11initvectorsP7double4P6float4
.type _Z11initvectorsP7double4P6float4, @function
_Z11initvectorsP7double4P6float4:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z11initvectorsP7double4P6float4P7double4P6float4
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11initvectorsP7double4P6float4, .-_Z11initvectorsP7double4P6float4
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11initvectorsP7double4P6float4"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11initvectorsP7double4P6float4(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "initvectors.hip"
.globl _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE # -- Begin function _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.p2align 4, 0x90
.type _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE,@function
_Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE: # @_Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, .Lfunc_end0-_Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE,@object # @_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.section .rodata,"a",@progbits
.globl _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.p2align 3, 0x0
_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE:
.quad _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.size _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE"
.size .L__unnamed_1, 51
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11initvectorsP15HIP_vector_typeIdLj4EEPS_IfLj4EE
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/host_vector.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/remove.h>
#include <thrust/count.h>
#include <iostream>
// Given a set of vectors (all of same size), remove the entries corresponding
// to indexes tagged as 'false' in a vector of flags.
int main(void)
{
const bool active[] = { false, true, false, true, false, false };
const float a[] = {0.3f, 0.5f, 0.4f, 0.1f, 0.2f, 0.7f};
const int b[] = {3, 5, 4, 1, 2, 7};
const double c[] = {13, 15, 14, 11, 12, 17 };
thrust::host_vector<bool> h_active(active, active + 6);
thrust::host_vector<float> h_a(a, a + 6);
thrust::host_vector<int> h_b(b, b + 6);
thrust::host_vector<double> h_c(c, c + 6);
// define a tuple of the three vector's iterators
typedef thrust::tuple<thrust::host_vector<float>::iterator, thrust::host_vector<int>::iterator, thrust::host_vector<double>::iterator> IteratorTuple;
// define a zip iterator
typedef thrust::zip_iterator<IteratorTuple> ZipIterator;
ZipIterator zip_begin = thrust::make_zip_iterator(thrust::make_tuple(h_a.begin(), h_b.begin(), h_c.begin()));
ZipIterator zip_end = zip_begin + 6;
// call remove if on the zipped ranges (logical_not predicate: remove entries tagged with 'false')
ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::logical_not<bool>());
// call remove if on the zipped ranges (identity predicate: remove entries tagged with 'true')
//ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::identity<bool>());
// Count number of flags set to 'true'
int num_flags = thrust::count_if(h_active.begin(), h_active.end(), thrust::identity<bool>());
std::cout << "Keep " << num_flags << " elements" << std::endl;
// erase the removed elements
//h_a.erase(thrust::get<0>(new_end.get_iterator_tuple()), h_a.end());
//h_b.erase(thrust::get<1>(new_end.get_iterator_tuple()), h_b.end());
//h_c.erase(thrust::get<2>(new_end.get_iterator_tuple()), h_c.end());
h_a.resize(num_flags);
h_b.resize(num_flags);
h_c.resize(num_flags);
// print out the contents of the vectors
std::cout << "New a: " << std::endl;
for(int i = 0; i < h_a.size(); ++i)
{
std::cout << h_a[i] << " ";
}
std::cout << std::endl;
std::cout << "New b: " << std::endl;
for(int i = 0; i < h_b.size(); ++i)
{
std::cout << h_b[i] << " ";
}
std::cout << std::endl;
std::cout << "New c: " << std::endl;
for (int i = 0; i < h_c.size(); ++i)
{
std::cout << h_c[i] << " ";
}
std::cout << std::endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/remove.h>
#include <thrust/count.h>
#include <iostream>
// Given a set of vectors (all of same size), remove the entries corresponding
// to indexes tagged as 'false' in a vector of flags.
int main(void)
{
const bool active[] = { false, true, false, true, false, false };
const float a[] = {0.3f, 0.5f, 0.4f, 0.1f, 0.2f, 0.7f};
const int b[] = {3, 5, 4, 1, 2, 7};
const double c[] = {13, 15, 14, 11, 12, 17 };
thrust::host_vector<bool> h_active(active, active + 6);
thrust::host_vector<float> h_a(a, a + 6);
thrust::host_vector<int> h_b(b, b + 6);
thrust::host_vector<double> h_c(c, c + 6);
// define a tuple of the three vector's iterators
typedef thrust::tuple<thrust::host_vector<float>::iterator, thrust::host_vector<int>::iterator, thrust::host_vector<double>::iterator> IteratorTuple;
// define a zip iterator
typedef thrust::zip_iterator<IteratorTuple> ZipIterator;
ZipIterator zip_begin = thrust::make_zip_iterator(thrust::make_tuple(h_a.begin(), h_b.begin(), h_c.begin()));
ZipIterator zip_end = zip_begin + 6;
// call remove if on the zipped ranges (logical_not predicate: remove entries tagged with 'false')
ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::logical_not<bool>());
// call remove if on the zipped ranges (identity predicate: remove entries tagged with 'true')
//ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::identity<bool>());
// Count number of flags set to 'true'
int num_flags = thrust::count_if(h_active.begin(), h_active.end(), thrust::identity<bool>());
std::cout << "Keep " << num_flags << " elements" << std::endl;
// erase the removed elements
//h_a.erase(thrust::get<0>(new_end.get_iterator_tuple()), h_a.end());
//h_b.erase(thrust::get<1>(new_end.get_iterator_tuple()), h_b.end());
//h_c.erase(thrust::get<2>(new_end.get_iterator_tuple()), h_c.end());
h_a.resize(num_flags);
h_b.resize(num_flags);
h_c.resize(num_flags);
// print out the contents of the vectors
std::cout << "New a: " << std::endl;
for(int i = 0; i < h_a.size(); ++i)
{
std::cout << h_a[i] << " ";
}
std::cout << std::endl;
std::cout << "New b: " << std::endl;
for(int i = 0; i < h_b.size(); ++i)
{
std::cout << h_b[i] << " ";
}
std::cout << std::endl;
std::cout << "New c: " << std::endl;
for (int i = 0; i < h_c.size(); ++i)
{
std::cout << h_c[i] << " ";
}
std::cout << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/remove.h>
#include <thrust/count.h>
#include <iostream>
// Given a set of vectors (all of same size), remove the entries corresponding
// to indexes tagged as 'false' in a vector of flags.
int main(void)
{
const bool active[] = { false, true, false, true, false, false };
const float a[] = {0.3f, 0.5f, 0.4f, 0.1f, 0.2f, 0.7f};
const int b[] = {3, 5, 4, 1, 2, 7};
const double c[] = {13, 15, 14, 11, 12, 17 };
thrust::host_vector<bool> h_active(active, active + 6);
thrust::host_vector<float> h_a(a, a + 6);
thrust::host_vector<int> h_b(b, b + 6);
thrust::host_vector<double> h_c(c, c + 6);
// define a tuple of the three vector's iterators
typedef thrust::tuple<thrust::host_vector<float>::iterator, thrust::host_vector<int>::iterator, thrust::host_vector<double>::iterator> IteratorTuple;
// define a zip iterator
typedef thrust::zip_iterator<IteratorTuple> ZipIterator;
ZipIterator zip_begin = thrust::make_zip_iterator(thrust::make_tuple(h_a.begin(), h_b.begin(), h_c.begin()));
ZipIterator zip_end = zip_begin + 6;
// call remove if on the zipped ranges (logical_not predicate: remove entries tagged with 'false')
ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::logical_not<bool>());
// call remove if on the zipped ranges (identity predicate: remove entries tagged with 'true')
//ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::identity<bool>());
// Count number of flags set to 'true'
int num_flags = thrust::count_if(h_active.begin(), h_active.end(), thrust::identity<bool>());
std::cout << "Keep " << num_flags << " elements" << std::endl;
// erase the removed elements
//h_a.erase(thrust::get<0>(new_end.get_iterator_tuple()), h_a.end());
//h_b.erase(thrust::get<1>(new_end.get_iterator_tuple()), h_b.end());
//h_c.erase(thrust::get<2>(new_end.get_iterator_tuple()), h_c.end());
h_a.resize(num_flags);
h_b.resize(num_flags);
h_c.resize(num_flags);
// print out the contents of the vectors
std::cout << "New a: " << std::endl;
for(int i = 0; i < h_a.size(); ++i)
{
std::cout << h_a[i] << " ";
}
std::cout << std::endl;
std::cout << "New b: " << std::endl;
for(int i = 0; i < h_b.size(); ++i)
{
std::cout << h_b[i] << " ";
}
std::cout << std::endl;
std::cout << "New c: " << std::endl;
for (int i = 0; i < h_c.size(); ++i)
{
std::cout << h_c[i] << " ";
}
std::cout << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/remove.h>
#include <thrust/count.h>
#include <iostream>
// Given a set of vectors (all of same size), remove the entries corresponding
// to indexes tagged as 'false' in a vector of flags.
int main(void)
{
const bool active[] = { false, true, false, true, false, false };
const float a[] = {0.3f, 0.5f, 0.4f, 0.1f, 0.2f, 0.7f};
const int b[] = {3, 5, 4, 1, 2, 7};
const double c[] = {13, 15, 14, 11, 12, 17 };
thrust::host_vector<bool> h_active(active, active + 6);
thrust::host_vector<float> h_a(a, a + 6);
thrust::host_vector<int> h_b(b, b + 6);
thrust::host_vector<double> h_c(c, c + 6);
// define a tuple of the three vector's iterators
typedef thrust::tuple<thrust::host_vector<float>::iterator, thrust::host_vector<int>::iterator, thrust::host_vector<double>::iterator> IteratorTuple;
// define a zip iterator
typedef thrust::zip_iterator<IteratorTuple> ZipIterator;
ZipIterator zip_begin = thrust::make_zip_iterator(thrust::make_tuple(h_a.begin(), h_b.begin(), h_c.begin()));
ZipIterator zip_end = zip_begin + 6;
// call remove if on the zipped ranges (logical_not predicate: remove entries tagged with 'false')
ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::logical_not<bool>());
// call remove if on the zipped ranges (identity predicate: remove entries tagged with 'true')
//ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::identity<bool>());
// Count number of flags set to 'true'
int num_flags = thrust::count_if(h_active.begin(), h_active.end(), thrust::identity<bool>());
std::cout << "Keep " << num_flags << " elements" << std::endl;
// erase the removed elements
//h_a.erase(thrust::get<0>(new_end.get_iterator_tuple()), h_a.end());
//h_b.erase(thrust::get<1>(new_end.get_iterator_tuple()), h_b.end());
//h_c.erase(thrust::get<2>(new_end.get_iterator_tuple()), h_c.end());
h_a.resize(num_flags);
h_b.resize(num_flags);
h_c.resize(num_flags);
// print out the contents of the vectors
std::cout << "New a: " << std::endl;
for(int i = 0; i < h_a.size(); ++i)
{
std::cout << h_a[i] << " ";
}
std::cout << std::endl;
std::cout << "New b: " << std::endl;
for(int i = 0; i < h_b.size(); ++i)
{
std::cout << h_b[i] << " ";
}
std::cout << std::endl;
std::cout << "New c: " << std::endl;
for (int i = 0; i < h_c.size(); ++i)
{
std::cout << h_c[i] << " ";
}
std::cout << std::endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/remove.h>
#include <thrust/count.h>
#include <iostream>
// Given a set of vectors (all of same size), remove the entries corresponding
// to indexes tagged as 'false' in a vector of flags.
int main(void)
{
const bool active[] = { false, true, false, true, false, false };
const float a[] = {0.3f, 0.5f, 0.4f, 0.1f, 0.2f, 0.7f};
const int b[] = {3, 5, 4, 1, 2, 7};
const double c[] = {13, 15, 14, 11, 12, 17 };
thrust::host_vector<bool> h_active(active, active + 6);
thrust::host_vector<float> h_a(a, a + 6);
thrust::host_vector<int> h_b(b, b + 6);
thrust::host_vector<double> h_c(c, c + 6);
// define a tuple of the three vector's iterators
typedef thrust::tuple<thrust::host_vector<float>::iterator, thrust::host_vector<int>::iterator, thrust::host_vector<double>::iterator> IteratorTuple;
// define a zip iterator
typedef thrust::zip_iterator<IteratorTuple> ZipIterator;
ZipIterator zip_begin = thrust::make_zip_iterator(thrust::make_tuple(h_a.begin(), h_b.begin(), h_c.begin()));
ZipIterator zip_end = zip_begin + 6;
// call remove if on the zipped ranges (logical_not predicate: remove entries tagged with 'false')
ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::logical_not<bool>());
// call remove if on the zipped ranges (identity predicate: remove entries tagged with 'true')
//ZipIterator new_end = thrust::remove_if(zip_begin, zip_end, h_active.begin(), thrust::identity<bool>());
// Count number of flags set to 'true'
int num_flags = thrust::count_if(h_active.begin(), h_active.end(), thrust::identity<bool>());
std::cout << "Keep " << num_flags << " elements" << std::endl;
// erase the removed elements
//h_a.erase(thrust::get<0>(new_end.get_iterator_tuple()), h_a.end());
//h_b.erase(thrust::get<1>(new_end.get_iterator_tuple()), h_b.end());
//h_c.erase(thrust::get<2>(new_end.get_iterator_tuple()), h_c.end());
h_a.resize(num_flags);
h_b.resize(num_flags);
h_c.resize(num_flags);
// print out the contents of the vectors
std::cout << "New a: " << std::endl;
for(int i = 0; i < h_a.size(); ++i)
{
std::cout << h_a[i] << " ";
}
std::cout << std::endl;
std::cout << "New b: " << std::endl;
for(int i = 0; i < h_b.size(); ++i)
{
std::cout << h_b[i] << " ";
}
std::cout << std::endl;
std::cout << "New c: " << std::endl;
for (int i = 0; i < h_c.size(); ++i)
{
std::cout << h_c[i] << " ";
}
std::cout << std::endl;
return 0;
} | .text
.file "remove_if.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3e99999a # float 0.300000012
.long 0x3f000000 # float 0.5
.long 0x3ecccccd # float 0.400000006
.long 0x3dcccccd # float 0.100000001
.LCPI0_1:
.long 3 # 0x3
.long 5 # 0x5
.long 4 # 0x4
.long 1 # 0x1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZN6thrust6detail16allocator_traitsISaIbEE8allocateERS2_m.exit.i.i.i.i.i.i.i
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $6, %edi
callq _Znwm
movl $16777472, (%rax) # imm = 0x1000100
movq %rax, 32(%rsp) # 8-byte Spill
movw $0, 4(%rax)
.Ltmp0:
movl $24, %edi
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZN6thrust6detail11vector_baseIfSaIfEE17allocate_and_copyIPKfEEvmT_S7_RNS0_18contiguous_storageIfS2_EE.exit
movq %rax, %r14
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [3.00000012E-1,5.0E-1,4.00000006E-1,1.00000001E-1]
movups %xmm0, (%rax)
movabsq $4554039943383272653, %rax # imm = 0x3F3333333E4CCCCD
movq %rax, 16(%r14)
.Ltmp3:
movl $24, %edi
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZN6thrust6detail11vector_baseIiSaIiEE17allocate_and_copyIPKiEEvmT_S7_RNS0_18contiguous_storageIiS2_EE.exit
movq %rax, %r12
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [3,5,4,1]
movups %xmm0, (%rax)
movabsq $30064771074, %rax # imm = 0x700000002
movq %rax, 16(%r12)
.Ltmp6:
movl $48, %edi
callq _Znwm
.Ltmp7:
# %bb.3: # %_ZN6thrust6detail11vector_baseIdSaIdEE17allocate_and_copyIPKdEEvmT_S7_RNS0_18contiguous_storageIdS2_EE.exit
movabsq $4623507967449235456, %rcx # imm = 0x402A000000000000
movq %rcx, (%rax)
movabsq $4624633867356078080, %rcx # imm = 0x402E000000000000
movq %rcx, 8(%rax)
movabsq $4624070917402656768, %rcx # imm = 0x402C000000000000
movq %rcx, 16(%rax)
movabsq $4622382067542392832, %rcx # imm = 0x4026000000000000
movq %rcx, 24(%rax)
movabsq $4622945017495814144, %rcx # imm = 0x4028000000000000
movq %rcx, 32(%rax)
movabsq $4625478292286210048, %rcx # imm = 0x4031000000000000
movq %rcx, 40(%rax)
movq %rax, %r15
addq $48, %r15
leaq 24(%r12), %rcx
movq 32(%rsp), %rsi # 8-byte Reload
movq %rsi, %rdx
addq $6, %rdx
xorl %r8d, %r8d
movq %rax, %rdi
.p2align 4, 0x90
.LBB0_4: # %.lr.ph.i.i.i
# =>This Inner Loop Header: Depth=1
cmpb $0, (%rsi)
je .LBB0_7
# %bb.5: # in Loop: Header=BB0_4 Depth=1
addq $4, %r8
addq $8, %rdi
incq %rsi
cmpq $24, %r8
jne .LBB0_4
# %bb.6:
movl $24, %r8d
cmpq $24, %r8
jne .LBB0_9
jmp .LBB0_14
.LBB0_7: # %.lr.ph.i.i.i..critedge.i.i.i_crit_edge
movq %r12, %rcx
addq %r8, %rcx
movq %rdi, %r15
movq %rsi, %rdx
cmpq $24, %r8
je .LBB0_14
.LBB0_9: # %.critedge.i.i.i
leaq 4(%r8), %rsi
cmpq $24, %rsi
je .LBB0_14
# %bb.10: # %.lr.ph52.i.i.i.preheader
leaq (%r14,%r8), %rdi
incq %rdx
addq %r14, %rsi
movl $20, %r9d
subq %r8, %r9
xorl %r8d, %r8d
movq %r15, %r10
movq %rcx, %r11
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_11 Depth=1
incq %rdx
addq $4, %r8
cmpq %r8, %r9
je .LBB0_14
.LBB0_11: # %.lr.ph52.i.i.i
# =>This Inner Loop Header: Depth=1
cmpb $0, (%rdx)
je .LBB0_13
# %bb.12: # in Loop: Header=BB0_11 Depth=1
movss (%rsi,%r8), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdi)
movl 4(%rcx,%r8), %ebx
movl %ebx, (%r11)
movsd 8(%r15,%r8,2), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r10)
addq $4, %rdi
addq $4, %r11
addq $8, %r10
jmp .LBB0_13
.LBB0_14: # %.lr.ph.i.i.i.i.i.i.i.preheader
movq %rax, 8(%rsp) # 8-byte Spill
movq %r12, 16(%rsp) # 8-byte Spill
movq %r14, 24(%rsp) # 8-byte Spill
xorl %eax, %eax
xorl %r13d, %r13d
movq 32(%rsp), %rdx # 8-byte Reload
.p2align 4, 0x90
.LBB0_15: # %.lr.ph.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movzbl (%rdx,%rax), %ecx
addq %rcx, %r13
incq %rax
cmpq $6, %rax
jne .LBB0_15
# %bb.16: # %_ZN6thrust8count_ifINS_6detail15normal_iteratorIPbEENS_8identityIbEEEENS_15iterator_traitsIT_E15difference_typeES8_S8_T0_.exit
.Ltmp9:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.17: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
.Ltmp11:
movl $_ZSt4cout, %edi
movl %r13d, %esi
callq _ZNSolsEi
.Ltmp12:
# %bb.18:
.Ltmp13:
movq %rax, %rbp
movl $.L.str.1, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp14:
# %bb.19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit48
movq (%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .LBB0_20
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_24
# %bb.23:
movzbl 67(%r14), %eax
jmp .LBB0_26
.LBB0_24:
.Ltmp15:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp16:
# %bb.25: # %.noexc104
movq (%r14), %rax
.Ltmp17:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp18:
.LBB0_26: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp19:
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
.Ltmp20:
# %bb.27: # %.noexc106
.Ltmp21:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp22:
# %bb.28: # %_ZNSolsEPFRSoS_E.exit
movslq %r13d, %rbx
cmpq $6, %rbx
jae .LBB0_30
# %bb.29:
movq %rbx, %r12
movq 24(%rsp), %r14 # 8-byte Reload
jmp .LBB0_37
.LBB0_30:
movq %rbx, %r13
addq $-6, %r13
movq 24(%rsp), %r14 # 8-byte Reload
je .LBB0_31
# %bb.32:
cmpq $7, %r13
movl $6, %eax
cmovaeq %r13, %rax
addq $6, %rax
movq %rax, %rcx
shrq $61, %rcx
jne .LBB0_33
# %bb.35: # %_ZN6thrust6detail16allocator_traitsISaIfEE8allocateERS2_m.exit.i.i.i
cmpq $13, %rax
movl $12, %edi
cmovaeq %rax, %rdi
shlq $2, %rdi
.Ltmp23:
callq _Znwm
.Ltmp24:
# %bb.36: # %_ZN6thrust6detail18contiguous_storageIfSaIfEEC2ENS0_16copy_allocator_tERKS3_m.exit.i
movq %rax, %r14
movq 24(%rsp), %r15 # 8-byte Reload
movq 16(%r15), %rax
movq %rax, 16(%r14)
movups (%r15), %xmm0
movups %xmm0, (%r14)
movq %r14, %rdi
addq $24, %rdi
shlq $2, %r13
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq %r15, %rdi
callq _ZdlPv
movq %rbx, %r12
jmp .LBB0_37
.LBB0_31:
movl $6, %r12d
.LBB0_37: # %_ZN6thrust6detail11vector_baseIfSaIfEE6resizeEm.exit
cmpq $6, %rbx
movq %r14, 24(%rsp) # 8-byte Spill
jae .LBB0_39
# %bb.38:
movq %rbx, %r15
cmpq $6, %rbx
jae .LBB0_47
jmp .LBB0_54
.LBB0_39:
movq %rbx, %r13
addq $-6, %r13
je .LBB0_40
# %bb.41:
cmpq $7, %r13
movl $6, %eax
cmovaeq %r13, %rax
addq $6, %rax
movq %rax, %rcx
shrq $61, %rcx
jne .LBB0_42
# %bb.44: # %_ZN6thrust6detail16allocator_traitsISaIiEE8allocateERS2_m.exit.i.i.i
cmpq $13, %rax
movl $12, %edi
cmovaeq %rax, %rdi
shlq $2, %rdi
.Ltmp27:
callq _Znwm
.Ltmp28:
# %bb.45: # %_ZN6thrust6detail18contiguous_storageIiSaIiEEC2ENS0_16copy_allocator_tERKS3_m.exit.i
movq %rax, %r14
movq 16(%rsp), %r15 # 8-byte Reload
movq 16(%r15), %rax
movq %rax, 16(%r14)
movups (%r15), %xmm0
movups %xmm0, (%r14)
movq %r14, %rdi
addq $24, %rdi
shlq $2, %r13
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq %r15, %rdi
callq _ZdlPv
movq %rbx, %r15
movq %r14, 16(%rsp) # 8-byte Spill
cmpq $6, %rbx
jae .LBB0_47
jmp .LBB0_54
.LBB0_40:
movl $6, %r15d
cmpq $6, %rbx
jb .LBB0_54
.LBB0_47:
movq %rbx, %r13
addq $-6, %r13
je .LBB0_48
# %bb.49:
cmpq $7, %r13
movl $6, %eax
cmovaeq %r13, %rax
addq $6, %rax
movq %rax, %rcx
shrq $60, %rcx
jne .LBB0_50
# %bb.52: # %_ZN6thrust6detail16allocator_traitsISaIdEE8allocateERS2_m.exit.i.i.i
cmpq $13, %rax
movl $12, %edi
cmovaeq %rax, %rdi
shlq $3, %rdi
.Ltmp31:
callq _Znwm
.Ltmp32:
# %bb.53: # %_ZN6thrust6detail18contiguous_storageIdSaIdEEC2ENS0_16copy_allocator_tERKS3_m.exit.i
movq %rax, %rbp
movq 8(%rsp), %r14 # 8-byte Reload
movups (%r14), %xmm0
movups 16(%r14), %xmm1
movups 32(%r14), %xmm2
movups %xmm2, 32(%rax)
movups %xmm1, 16(%rax)
movups %xmm0, (%rax)
movq %rax, %rdi
addq $48, %rdi
shlq $3, %r13
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
movq %r14, %rdi
callq _ZdlPv
movq %rbp, 8(%rsp) # 8-byte Spill
jmp .LBB0_54
.LBB0_48:
movl $6, %ebx
.LBB0_54: # %_ZN6thrust6detail11vector_baseIdSaIdEE6resizeEm.exit
.Ltmp35:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp36:
# %bb.55: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit52
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_112
# %bb.56: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i149
cmpb $0, 56(%r14)
je .LBB0_58
# %bb.57:
movzbl 67(%r14), %eax
jmp .LBB0_60
.LBB0_58:
.Ltmp37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp38:
# %bb.59: # %.noexc154
movq (%r14), %rax
.Ltmp39:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp40:
.LBB0_60: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i151
.Ltmp41:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp42:
# %bb.61: # %.noexc156
.Ltmp43:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp44:
# %bb.62: # %_ZNSolsEPFRSoS_E.exit54.preheader
testq %r12, %r12
je .LBB0_67
# %bb.63: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_64: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax # 8-byte Reload
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.Ltmp45:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp46:
# %bb.65: # %_ZNSolsEf.exit
# in Loop: Header=BB0_64 Depth=1
.Ltmp47:
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp48:
# %bb.66: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit59
# in Loop: Header=BB0_64 Depth=1
incq %r14
cmpq %r14, %r12
jne .LBB0_64
.LBB0_67: # %_ZNSolsEPFRSoS_E.exit54._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_112
# %bb.68: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i160
cmpb $0, 56(%r14)
je .LBB0_70
# %bb.69:
movzbl 67(%r14), %eax
jmp .LBB0_72
.LBB0_70:
.Ltmp50:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp51:
# %bb.71: # %.noexc165
movq (%r14), %rax
.Ltmp52:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp53:
.LBB0_72: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i162
.Ltmp54:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp55:
# %bb.73: # %.noexc167
.Ltmp56:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp57:
# %bb.74: # %_ZNSolsEPFRSoS_E.exit56
.Ltmp58:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp59:
# %bb.75: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit61
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_112
# %bb.76: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i171
cmpb $0, 56(%r14)
je .LBB0_82
# %bb.77:
movzbl 67(%r14), %eax
jmp .LBB0_84
.LBB0_82:
.Ltmp60:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp61:
# %bb.83: # %.noexc176
movq (%r14), %rax
.Ltmp62:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp63:
.LBB0_84: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i173
.Ltmp64:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp65:
# %bb.85: # %.noexc178
.Ltmp66:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp67:
# %bb.86: # %_ZNSolsEPFRSoS_E.exit63.preheader
testq %r15, %r15
movq 16(%rsp), %r12 # 8-byte Reload
je .LBB0_91
# %bb.87: # %.lr.ph326.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_88: # %.lr.ph326
# =>This Inner Loop Header: Depth=1
movl (%r12,%r14,4), %esi
.Ltmp68:
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp69:
# %bb.89: # in Loop: Header=BB0_88 Depth=1
.Ltmp70:
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp71:
# %bb.90: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit67
# in Loop: Header=BB0_88 Depth=1
incq %r14
cmpq %r14, %r15
jne .LBB0_88
.LBB0_91: # %_ZNSolsEPFRSoS_E.exit63._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_112
# %bb.92: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i182
cmpb $0, 56(%r14)
je .LBB0_94
# %bb.93:
movzbl 67(%r14), %eax
jmp .LBB0_96
.LBB0_94:
.Ltmp73:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp74:
# %bb.95: # %.noexc187
movq (%r14), %rax
.Ltmp75:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp76:
.LBB0_96: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i184
.Ltmp77:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp78:
# %bb.97: # %.noexc189
.Ltmp79:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp80:
# %bb.98: # %_ZNSolsEPFRSoS_E.exit65
.Ltmp81:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp82:
# %bb.99: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit69
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_112
# %bb.100: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i193
cmpb $0, 56(%r14)
je .LBB0_102
# %bb.101:
movzbl 67(%r14), %eax
jmp .LBB0_104
.LBB0_102:
.Ltmp83:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp84:
# %bb.103: # %.noexc198
movq (%r14), %rax
.Ltmp85:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp86:
.LBB0_104: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i195
.Ltmp87:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp88:
# %bb.105: # %.noexc200
.Ltmp89:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp90:
# %bb.106: # %_ZNSolsEPFRSoS_E.exit71.preheader
testq %rbx, %rbx
movq 8(%rsp), %r15 # 8-byte Reload
je .LBB0_111
# %bb.107: # %.lr.ph328.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_108: # %.lr.ph328
# =>This Inner Loop Header: Depth=1
movsd (%r15,%r14,8), %xmm0 # xmm0 = mem[0],zero
.Ltmp91:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp92:
# %bb.109: # %_ZNSolsEd.exit
# in Loop: Header=BB0_108 Depth=1
.Ltmp93:
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp94:
# %bb.110: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit76
# in Loop: Header=BB0_108 Depth=1
incq %r14
cmpq %r14, %rbx
jne .LBB0_108
.LBB0_111: # %_ZNSolsEPFRSoS_E.exit71._crit_edge
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB0_112
# %bb.114: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i204
cmpb $0, 56(%r14)
je .LBB0_116
# %bb.115:
movzbl 67(%r14), %eax
jmp .LBB0_118
.LBB0_116:
.Ltmp96:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp97:
# %bb.117: # %.noexc209
movq (%r14), %rax
.Ltmp98:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp99:
.LBB0_118: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i206
.Ltmp100:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp101:
# %bb.119: # %.noexc211
.Ltmp102:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp103:
# %bb.120: # %_ZNSolsEPFRSoS_E.exit73
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
movq 16(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
movq 24(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
movq 32(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_33: # %.noexc4.i.i
.cfi_def_cfa_offset 96
.Ltmp25:
callq _ZSt17__throw_bad_allocv
.Ltmp26:
# %bb.34: # %.noexc112
.LBB0_42: # %.noexc4.i.i128
.Ltmp29:
callq _ZSt17__throw_bad_allocv
.Ltmp30:
# %bb.43: # %.noexc129
.LBB0_50: # %.noexc4.i.i145
.Ltmp33:
callq _ZSt17__throw_bad_allocv
.Ltmp34:
# %bb.51: # %.noexc146
.LBB0_112: # %.invoke
.Ltmp104:
callq _ZSt16__throw_bad_castv
.Ltmp105:
# %bb.113: # %.cont
.LBB0_20:
.Ltmp107:
callq _ZSt16__throw_bad_castv
.Ltmp108:
# %bb.21: # %.noexc103
.LBB0_78:
.Ltmp109:
jmp .LBB0_79
.LBB0_130: # %_ZN6thrust6detail18contiguous_storageIdSaIdEED2Ev.exit.i.i
.Ltmp8:
movq %rax, %r13
jmp .LBB0_125
.LBB0_129: # %_ZN6thrust6detail18contiguous_storageIiSaIiEED2Ev.exit.i.i
.Ltmp5:
movq %rax, %r13
jmp .LBB0_126
.LBB0_128: # %_ZN6thrust6detail18contiguous_storageIfSaIfEED2Ev.exit.i.i
.Ltmp2:
movq %rax, %r13
jmp .LBB0_127
.LBB0_121:
.Ltmp95:
movq %rax, %r13
movq 16(%rsp), %r12 # 8-byte Reload
jmp .LBB0_124
.LBB0_122:
.Ltmp72:
movq %rax, %r13
jmp .LBB0_123
.LBB0_81:
.Ltmp49:
jmp .LBB0_79
.LBB0_80:
.Ltmp106:
.LBB0_79:
movq %rax, %r13
movq 16(%rsp), %r12 # 8-byte Reload
.LBB0_123:
movq 8(%rsp), %r15 # 8-byte Reload
.LBB0_124:
movq %r15, %rdi
callq _ZdlPv
movq 24(%rsp), %r14 # 8-byte Reload
.LBB0_125: # %_ZN6thrust6detail11vector_baseIdSaIdEED2Ev.exit82
movq %r12, %rdi
callq _ZdlPv
.LBB0_126: # %_ZN6thrust6detail11vector_baseIiSaIiEED2Ev.exit84
movq %r14, %rdi
callq _ZdlPv
.LBB0_127: # %_ZN6thrust6detail11vector_baseIfSaIfEED2Ev.exit86
movq 32(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
movq %r13, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp24-.Ltmp9 # Call between .Ltmp9 and .Ltmp24
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp27-.Ltmp24 # Call between .Ltmp24 and .Ltmp27
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp31-.Ltmp28 # Call between .Ltmp28 and .Ltmp31
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp32-.Ltmp31 # Call between .Ltmp31 and .Ltmp32
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp35-.Ltmp32 # Call between .Ltmp32 and .Ltmp35
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp44-.Ltmp35 # Call between .Ltmp35 and .Ltmp44
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp48-.Ltmp45 # Call between .Ltmp45 and .Ltmp48
.uleb128 .Ltmp49-.Lfunc_begin0 # jumps to .Ltmp49
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp67-.Ltmp50 # Call between .Ltmp50 and .Ltmp67
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp68-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp71-.Ltmp68 # Call between .Ltmp68 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp73-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp90-.Ltmp73 # Call between .Ltmp73 and .Ltmp90
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp91-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp94-.Ltmp91 # Call between .Ltmp91 and .Ltmp94
.uleb128 .Ltmp95-.Lfunc_begin0 # jumps to .Ltmp95
.byte 0 # On action: cleanup
.uleb128 .Ltmp96-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp105-.Ltmp96 # Call between .Ltmp96 and .Ltmp105
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp107-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp108-.Ltmp107 # Call between .Ltmp107 and .Ltmp108
.uleb128 .Ltmp109-.Lfunc_begin0 # jumps to .Ltmp109
.byte 0 # On action: cleanup
.uleb128 .Ltmp108-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Lfunc_end0-.Ltmp108 # Call between .Ltmp108 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Keep "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " elements"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "New a: "
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " "
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "New b: "
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "New c: "
.size .L.str.5, 8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/sort.h>
#include <thrust/reduce.h>
#include <stdlib.h>
#include <ctime>
int main ()
{
srand(time(NULL));
thrust::device_vector<int> dv(0);
thrust::host_vector<int> hv(0);
for (int i = 0; i < 5; ++i) {
hv.push_back(rand() % 101);
}
dv = hv;
thrust::sort(dv.begin(), dv.end());
float sum = thrust::reduce(dv.begin(), dv.end());
std::cout << "Average is " << sum / 5.0f << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/sort.h>
#include <thrust/reduce.h>
#include <stdlib.h>
#include <ctime>
int main ()
{
srand(time(NULL));
thrust::device_vector<int> dv(0);
thrust::host_vector<int> hv(0);
for (int i = 0; i < 5; ++i) {
hv.push_back(rand() % 101);
}
dv = hv;
thrust::sort(dv.begin(), dv.end());
float sum = thrust::reduce(dv.begin(), dv.end());
std::cout << "Average is " << sum / 5.0f << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
#include <cuComplex.h>
__global__ void rsub_strided_double(int n,int xOffset,int yOffset, double *dx, double *dy,int incx,int incy,double *result) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
if(i >= xOffset && i >= yOffset && i % incx == 0 && i % incy == 0)
result[i] = dx[i] / dy[i];
}
} | code for sm_80
Function : _Z19rsub_strided_doubleiiiPdS_iiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ISETP.GE.AND P0, PT, R10.reuse, c[0x0][0x164], PT ; /* 0x000059000a007a0c */
/* 0x040fe20003f06270 */
/*0080*/ BSSY B0, 0x540 ; /* 0x000004b000007945 */
/* 0x000fe60003800000 */
/*0090*/ ISETP.LT.OR P0, PT, R10, c[0x0][0x168], !P0 ; /* 0x00005a000a007a0c */
/* 0x000fda0004701670 */
/*00a0*/ @P0 BRA 0x530 ; /* 0x0000048000000947 */
/* 0x003fea0003800000 */
/*00b0*/ IABS R5, c[0x0][0x180] ; /* 0x0000600000057a13 */
/* 0x000fe40000000000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*00d0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R4, R10 ; /* 0x0000000a00047213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0180*/ IMAD R0, R5, R3, R4 ; /* 0x0000000305007224 */
/* 0x000fca00078e0204 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100008824 */
/* 0x000fe200078e0a05 */
/*01b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f06270 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fc800078e0a05 */
/*01e0*/ @!P0 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff008224 */
/* 0x000fe200078e0a00 */
/*01f0*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff009a12 */
/* 0x000fc800078e33ff */
/*0200*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*0210*/ @P1 BRA 0x530 ; /* 0x0000031000001947 */
/* 0x000fea0003800000 */
/*0220*/ IABS R6, c[0x0][0x184] ; /* 0x0000610000067a13 */
/* 0x000fc80000000000 */
/*0230*/ I2F.RP R0, R6 ; /* 0x0000000600007306 */
/* 0x000e300000209400 */
/*0240*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0250*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0260*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0270*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0280*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0290*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fc800078e02ff */
/*02a0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*02b0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*02d0*/ IMAD R3, R6, R3, R4 ; /* 0x0000000306037224 */
/* 0x000fca00078e0204 */
/*02e0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*02f0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a06 */
/*0300*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fc80003f25270 */
/*0310*/ ISETP.GT.U32.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f44070 */
/*0320*/ @!P2 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x000000010303a824 */
/* 0x000fc800078e0a06 */
/*0330*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fe200078e0a03 */
/*0340*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff039a12 */
/* 0x000fc800078e33ff */
/*0350*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0360*/ @P0 BRA 0x530 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.WIDE R6, R10, R5, c[0x0][0x178] ; /* 0x00005e000a067625 */
/* 0x000fcc00078e0205 */
/*0390*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fcc00078e0205 */
/*03b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*03c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*03d0*/ BSSY B1, 0x500 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*03e0*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x004e220000001800 */
/*03f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fc60003f2e200 */
/*0400*/ DFMA R8, -R6, R2, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000102 */
/*0410*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0420*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0430*/ DFMA R2, -R6, R8, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000108 */
/*0440*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*0450*/ DMUL R8, R4, R2 ; /* 0x0000000204087228 */
/* 0x001e0c0000000000 */
/*0460*/ DFMA R12, -R6, R8, R4 ; /* 0x00000008060c722b */
/* 0x001e0c0000000104 */
/*0470*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*0480*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*0490*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*04a0*/ @P0 BRA P1, 0x4f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*04b0*/ MOV R0, 0x4d0 ; /* 0x000004d000007802 */
/* 0x000fe40000000f00 */
/*04c0*/ CALL.REL.NOINC 0x590 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*04d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*04f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD.WIDE R4, R10, R5, c[0x0][0x188] ; /* 0x000062000a047625 */
/* 0x000fca00078e0205 */
/*0520*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0005e4000c101b04 */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x004fc800078e00ff */
/*0550*/ IMAD R10, R3, c[0x0][0xc], R10 ; /* 0x00000300030a7a24 */
/* 0x000fca00078e020a */
/*0560*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0570*/ @!P0 BRA 0x70 ; /* 0xfffffaf000008947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*05a0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*05b0*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*05d0*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*05e0*/ BSSY B2, 0xb20 ; /* 0x0000053000027945 */
/* 0x000fe20003800000 */
/*05f0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0600*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0610*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*0620*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*0630*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*0640*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*0650*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0660*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0670*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0680*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0690*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*06a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*06b0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*06c0*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*06d0*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*06e0*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*06f0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*0700*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0710*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*0720*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*0730*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*0740*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0750*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0760*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0770*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0780*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0790*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*07a0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*07b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*07c0*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*07d0*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*07e0*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*07f0*/ @P0 BRA 0x9c0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0810*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*0820*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*0830*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*0840*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0850*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0860*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*0870*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0880*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0890*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*08a0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*08b0*/ @P0 BRA 0xb10 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*08c0*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*08d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*08e0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*08f0*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0900*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0910*/ @!P0 BRA 0xb10 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0920*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0930*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0940*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0950*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0960*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fc600078e3cff */
/*0970*/ IADD3 R2, -R11, -0x43300000, RZ ; /* 0xbcd000000b027810 */
/* 0x004fc80007ffe1ff */
/*0980*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0990*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*09a0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*09b0*/ BRA 0xb10 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*09c0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*09d0*/ @P0 BRA 0xaf0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*09e0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*09f0*/ @P0 BRA 0xac0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0a00*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0a10*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0a20*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0a30*/ @!P0 BRA 0xb10 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a40*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0a50*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0a60*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0a70*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0a80*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0a90*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0aa0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0ab0*/ BRA 0xb10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ac0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0ad0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0ae0*/ BRA 0xb10 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0af0*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0b00*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0b10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b20*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0b30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0b40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff4b002007950 */
/* 0x000fea0003c3ffff */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
#include <cuComplex.h>
__global__ void rsub_strided_double(int n,int xOffset,int yOffset, double *dx, double *dy,int incx,int incy,double *result) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
if(i >= xOffset && i >= yOffset && i % incx == 0 && i % incy == 0)
result[i] = dx[i] / dy[i];
}
} | .file "tmpxft_000e1fb6_00000000-6_rsub_strided.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_
.type _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_, @function
_Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_:
.LFB2074:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 32(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19rsub_strided_doubleiiiPdS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_, .-_Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_
.globl _Z19rsub_strided_doubleiiiPdS_iiS_
.type _Z19rsub_strided_doubleiiiPdS_iiS_, @function
_Z19rsub_strided_doubleiiiPdS_iiS_:
.LFB2075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z19rsub_strided_doubleiiiPdS_iiS_, .-_Z19rsub_strided_doubleiiiPdS_iiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19rsub_strided_doubleiiiPdS_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19rsub_strided_doubleiiiPdS_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
#include <cuComplex.h>
__global__ void rsub_strided_double(int n,int xOffset,int yOffset, double *dx, double *dy,int incx,int incy,double *result) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
if(i >= xOffset && i >= yOffset && i % incx == 0 && i % incy == 0)
result[i] = dx[i] / dy[i];
}
} | extern "C"
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
__global__ void rsub_strided_double(int n,int xOffset,int yOffset, double *dx, double *dy,int incx,int incy,double *result) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
if(i >= xOffset && i >= yOffset && i % incx == 0 && i % incy == 0)
result[i] = dx[i] / dy[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | extern "C"
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
__global__ void rsub_strided_double(int n,int xOffset,int yOffset, double *dx, double *dy,int incx,int incy,double *result) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
if(i >= xOffset && i >= yOffset && i % incx == 0 && i % incy == 0)
result[i] = dx[i] / dy[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19rsub_strided_doubleiiiPdS_iiS_
.globl _Z19rsub_strided_doubleiiiPdS_iiS_
.p2align 8
.type _Z19rsub_strided_doubleiiiPdS_iiS_,@function
_Z19rsub_strided_doubleiiiPdS_iiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_7
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s14, s8, 31
s_ashr_i32 s15, s9, 31
s_add_i32 s8, s8, s14
s_add_i32 s9, s9, s15
s_xor_b32 s8, s8, s14
s_xor_b32 s9, s9, s15
v_cvt_f32_u32_e32 v0, s8
v_cvt_f32_u32_e32 v2, s9
s_sub_i32 s3, 0, s8
s_sub_i32 s14, 0, s9
s_max_i32 s0, s0, s1
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v2, v2
s_mul_i32 s1, s2, s13
s_mov_b32 s2, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s3, v0
v_mul_lo_u32 v4, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v3, v2, v4
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_le_i32_e64 s0, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v0
v_mul_lo_u32 v5, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v4, v5
v_subrev_nc_u32_e32 v6, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_xor_b32_e32 v5, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_mul_hi_u32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s9
v_sub_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s9, v4
v_cmp_le_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s9, v4
v_cmp_le_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v2
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[14:15], v[12:13]
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_div_fixup_f64 v[6:7], v[10:11], v[8:9], v[6:7]
global_store_b64 v[4:5], v[6:7], off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19rsub_strided_doubleiiiPdS_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19rsub_strided_doubleiiiPdS_iiS_, .Lfunc_end0-_Z19rsub_strided_doubleiiiPdS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19rsub_strided_doubleiiiPdS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19rsub_strided_doubleiiiPdS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | extern "C"
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
__global__ void rsub_strided_double(int n,int xOffset,int yOffset, double *dx, double *dy,int incx,int incy,double *result) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < n; i += blockDim.x * gridDim.x) {
if(i >= xOffset && i >= yOffset && i % incx == 0 && i % incy == 0)
result[i] = dx[i] / dy[i];
}
} | .text
.file "rsub_strided.hip"
.globl _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_ # -- Begin function _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.p2align 4, 0x90
.type _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_,@function
_Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_: # @_Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19rsub_strided_doubleiiiPdS_iiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_, .Lfunc_end0-_Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19rsub_strided_doubleiiiPdS_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19rsub_strided_doubleiiiPdS_iiS_,@object # @_Z19rsub_strided_doubleiiiPdS_iiS_
.section .rodata,"a",@progbits
.globl _Z19rsub_strided_doubleiiiPdS_iiS_
.p2align 3, 0x0
_Z19rsub_strided_doubleiiiPdS_iiS_:
.quad _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.size _Z19rsub_strided_doubleiiiPdS_iiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19rsub_strided_doubleiiiPdS_iiS_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19rsub_strided_doubleiiiPdS_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19rsub_strided_doubleiiiPdS_iiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ ISETP.GE.AND P0, PT, R10.reuse, c[0x0][0x164], PT ; /* 0x000059000a007a0c */
/* 0x040fe20003f06270 */
/*0080*/ BSSY B0, 0x540 ; /* 0x000004b000007945 */
/* 0x000fe60003800000 */
/*0090*/ ISETP.LT.OR P0, PT, R10, c[0x0][0x168], !P0 ; /* 0x00005a000a007a0c */
/* 0x000fda0004701670 */
/*00a0*/ @P0 BRA 0x530 ; /* 0x0000048000000947 */
/* 0x003fea0003800000 */
/*00b0*/ IABS R5, c[0x0][0x180] ; /* 0x0000600000057a13 */
/* 0x000fe40000000000 */
/*00c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*00d0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*0140*/ IABS R4, R10 ; /* 0x0000000a00047213 */
/* 0x000fc60000000000 */
/*0150*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*0180*/ IMAD R0, R5, R3, R4 ; /* 0x0000000305007224 */
/* 0x000fca00078e0204 */
/*0190*/ ISETP.GT.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f04070 */
/*01a0*/ @!P0 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100008824 */
/* 0x000fe200078e0a05 */
/*01b0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f06270 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fc800078e0a05 */
/*01e0*/ @!P0 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff008224 */
/* 0x000fe200078e0a00 */
/*01f0*/ @!P1 LOP3.LUT R0, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff009a12 */
/* 0x000fc800078e33ff */
/*0200*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*0210*/ @P1 BRA 0x530 ; /* 0x0000031000001947 */
/* 0x000fea0003800000 */
/*0220*/ IABS R6, c[0x0][0x184] ; /* 0x0000610000067a13 */
/* 0x000fc80000000000 */
/*0230*/ I2F.RP R0, R6 ; /* 0x0000000600007306 */
/* 0x000e300000209400 */
/*0240*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0250*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0260*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0270*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0280*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0290*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fc800078e02ff */
/*02a0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*02b0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*02d0*/ IMAD R3, R6, R3, R4 ; /* 0x0000000306037224 */
/* 0x000fca00078e0204 */
/*02e0*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*02f0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a06 */
/*0300*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fc80003f25270 */
/*0310*/ ISETP.GT.U32.AND P2, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f44070 */
/*0320*/ @!P2 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x000000010303a824 */
/* 0x000fc800078e0a06 */
/*0330*/ @!P0 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff038224 */
/* 0x000fe200078e0a03 */
/*0340*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff039a12 */
/* 0x000fc800078e33ff */
/*0350*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0360*/ @P0 BRA 0x530 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.WIDE R6, R10, R5, c[0x0][0x178] ; /* 0x00005e000a067625 */
/* 0x000fcc00078e0205 */
/*0390*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*03a0*/ IMAD.WIDE R4, R10, R5, c[0x0][0x170] ; /* 0x00005c000a047625 */
/* 0x000fcc00078e0205 */
/*03b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1b00 */
/*03c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*03d0*/ BSSY B1, 0x500 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*03e0*/ MUFU.RCP64H R3, R7 ; /* 0x0000000700037308 */
/* 0x004e220000001800 */
/*03f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fc60003f2e200 */
/*0400*/ DFMA R8, -R6, R2, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000102 */
/*0410*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0420*/ DFMA R8, R2, R8, R2 ; /* 0x000000080208722b */
/* 0x001e0c0000000002 */
/*0430*/ DFMA R2, -R6, R8, 1 ; /* 0x3ff000000602742b */
/* 0x001e0c0000000108 */
/*0440*/ DFMA R2, R8, R2, R8 ; /* 0x000000020802722b */
/* 0x001e0c0000000008 */
/*0450*/ DMUL R8, R4, R2 ; /* 0x0000000204087228 */
/* 0x001e0c0000000000 */
/*0460*/ DFMA R12, -R6, R8, R4 ; /* 0x00000008060c722b */
/* 0x001e0c0000000104 */
/*0470*/ DFMA R2, R2, R12, R8 ; /* 0x0000000c0202722b */
/* 0x001e140000000008 */
/*0480*/ FFMA R0, RZ, R7, R3 ; /* 0x00000007ff007223 */
/* 0x001fca0000000003 */
/*0490*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*04a0*/ @P0 BRA P1, 0x4f0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*04b0*/ MOV R0, 0x4d0 ; /* 0x000004d000007802 */
/* 0x000fe40000000f00 */
/*04c0*/ CALL.REL.NOINC 0x590 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*04d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*04f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0510*/ IMAD.WIDE R4, R10, R5, c[0x0][0x188] ; /* 0x000062000a047625 */
/* 0x000fca00078e0205 */
/*0520*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0005e4000c101b04 */
/*0530*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x004fc800078e00ff */
/*0550*/ IMAD R10, R3, c[0x0][0xc], R10 ; /* 0x00000300030a7a24 */
/* 0x000fca00078e020a */
/*0560*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0570*/ @!P0 BRA 0x70 ; /* 0xfffffaf000008947 */
/* 0x000fea000383ffff */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*05a0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*05b0*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*05d0*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*05e0*/ BSSY B2, 0xb20 ; /* 0x0000053000027945 */
/* 0x000fe20003800000 */
/*05f0*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0600*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0610*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*0620*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*0630*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*0640*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*0650*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0660*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0670*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0680*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0690*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*06a0*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*06b0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*06c0*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*06d0*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*06e0*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*06f0*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*0700*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0710*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*0720*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*0730*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*0740*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0750*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0760*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0770*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0780*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0790*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*07a0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*07b0*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*07c0*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*07d0*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*07e0*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*07f0*/ @P0 BRA 0x9c0 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0800*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0810*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*0820*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*0830*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*0840*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*0850*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0860*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*0870*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0880*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0890*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*08a0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*08b0*/ @P0 BRA 0xb10 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*08c0*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*08d0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*08e0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*08f0*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0900*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0910*/ @!P0 BRA 0xb10 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0920*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0930*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0940*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0950*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0960*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fc600078e3cff */
/*0970*/ IADD3 R2, -R11, -0x43300000, RZ ; /* 0xbcd000000b027810 */
/* 0x004fc80007ffe1ff */
/*0980*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0990*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*09a0*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*09b0*/ BRA 0xb10 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*09c0*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*09d0*/ @P0 BRA 0xaf0 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*09e0*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*09f0*/ @P0 BRA 0xac0 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0a00*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0a10*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0a20*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0a30*/ @!P0 BRA 0xb10 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a40*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0a50*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0a60*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0a70*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0a80*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0a90*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0aa0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0ab0*/ BRA 0xb10 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0ac0*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0ad0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0ae0*/ BRA 0xb10 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0af0*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0b00*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0b10*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b20*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0b30*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0b40*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff4b002007950 */
/* 0x000fea0003c3ffff */
/*0b50*/ BRA 0xb50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19rsub_strided_doubleiiiPdS_iiS_
.globl _Z19rsub_strided_doubleiiiPdS_iiS_
.p2align 8
.type _Z19rsub_strided_doubleiiiPdS_iiS_,@function
_Z19rsub_strided_doubleiiiPdS_iiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_7
s_load_b256 s[4:11], s[0:1], 0x10
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_ashr_i32 s14, s8, 31
s_ashr_i32 s15, s9, 31
s_add_i32 s8, s8, s14
s_add_i32 s9, s9, s15
s_xor_b32 s8, s8, s14
s_xor_b32 s9, s9, s15
v_cvt_f32_u32_e32 v0, s8
v_cvt_f32_u32_e32 v2, s9
s_sub_i32 s3, 0, s8
s_sub_i32 s14, 0, s9
s_max_i32 s0, s0, s1
v_rcp_iflag_f32_e32 v0, v0
v_rcp_iflag_f32_e32 v2, v2
s_mul_i32 s1, s2, s13
s_mov_b32 s2, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s3, v0
v_mul_lo_u32 v4, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v0, v3
v_add_nc_u32_e32 v3, v2, v4
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_7
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_le_i32_e64 s0, v1
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v0
v_mul_lo_u32 v5, v5, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v4, v5
v_subrev_nc_u32_e32 v6, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_xor_b32_e32 v5, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v2
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_mul_hi_u32 v5, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s9
v_sub_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s9, v4
v_cmp_le_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s9, v4
v_cmp_le_u32_e32 vcc_lo, s9, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v2
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_add_co_u32 v6, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v5, vcc_lo
global_load_b64 v[6:7], v[6:7], off
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[14:15], v[12:13]
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
v_div_fixup_f64 v[6:7], v[10:11], v[8:9], v[6:7]
global_store_b64 v[4:5], v[6:7], off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19rsub_strided_doubleiiiPdS_iiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19rsub_strided_doubleiiiPdS_iiS_, .Lfunc_end0-_Z19rsub_strided_doubleiiiPdS_iiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19rsub_strided_doubleiiiPdS_iiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19rsub_strided_doubleiiiPdS_iiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e1fb6_00000000-6_rsub_strided.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_
.type _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_, @function
_Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_:
.LFB2074:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 32(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19rsub_strided_doubleiiiPdS_iiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_, .-_Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_
.globl _Z19rsub_strided_doubleiiiPdS_iiS_
.type _Z19rsub_strided_doubleiiiPdS_iiS_, @function
_Z19rsub_strided_doubleiiiPdS_iiS_:
.LFB2075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z19rsub_strided_doubleiiiPdS_iiS_iiiPdS_iiS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z19rsub_strided_doubleiiiPdS_iiS_, .-_Z19rsub_strided_doubleiiiPdS_iiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19rsub_strided_doubleiiiPdS_iiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19rsub_strided_doubleiiiPdS_iiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rsub_strided.hip"
.globl _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_ # -- Begin function _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.p2align 4, 0x90
.type _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_,@function
_Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_: # @_Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19rsub_strided_doubleiiiPdS_iiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_, .Lfunc_end0-_Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19rsub_strided_doubleiiiPdS_iiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19rsub_strided_doubleiiiPdS_iiS_,@object # @_Z19rsub_strided_doubleiiiPdS_iiS_
.section .rodata,"a",@progbits
.globl _Z19rsub_strided_doubleiiiPdS_iiS_
.p2align 3, 0x0
_Z19rsub_strided_doubleiiiPdS_iiS_:
.quad _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.size _Z19rsub_strided_doubleiiiPdS_iiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19rsub_strided_doubleiiiPdS_iiS_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__rsub_strided_doubleiiiPdS_iiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19rsub_strided_doubleiiiPdS_iiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void reduction(bool *B,int *number,int order){
int num = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//if(idx==0) printf("ORDER%d\n",order);
//printf("IDX%d\n",idx);
if(idx<order){
for(int i = 0 ; i<order; i++)
if(B[idx*order+i]==1)
num ++; //= B[idx*order + i];
//if(B[idx]==1)
//printf("CUDANUM%d\n",num);
number[idx] = num;
//atomicAdd(number,num);
//printf("NUMBER%d\n",number);//<<endl;
}
} | code for sm_80
Function : _Z9reductionPbPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xb00 ; /* 0x00000a5000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0xa10 ; /* 0x0000090000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD R3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000037a24 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0150*/ IADD3 R2, P1, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f3e0ff */
/*0160*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P1 ; /* 0x0000590003037a11 */
/* 0x000fce00008f0eff */
/*0170*/ @!P0 BRA 0x8b0 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P1 BRA 0x620 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E.U8 R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000ea8000c1e1100 */
/*01d0*/ LDG.E.U8 R16, [R2.64+0x1] ; /* 0x0000010402107981 */
/* 0x000ee8000c1e1100 */
/*01e0*/ LDG.E.U8 R17, [R2.64+0x2] ; /* 0x0000020402117981 */
/* 0x000f28000c1e1100 */
/*01f0*/ LDG.E.U8 R18, [R2.64+0x3] ; /* 0x0000030402127981 */
/* 0x000f68000c1e1100 */
/*0200*/ LDG.E.U8 R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x000f68000c1e1100 */
/*0210*/ LDG.E.U8 R20, [R2.64+0x5] ; /* 0x0000050402147981 */
/* 0x000f68000c1e1100 */
/*0220*/ LDG.E.U8 R21, [R2.64+0x6] ; /* 0x0000060402157981 */
/* 0x000f68000c1e1100 */
/*0230*/ LDG.E.U8 R22, [R2.64+0x7] ; /* 0x0000070402167981 */
/* 0x000f68000c1e1100 */
/*0240*/ LDG.E.U8 R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000f68000c1e1100 */
/*0250*/ LDG.E.U8 R14, [R2.64+0x9] ; /* 0x00000904020e7981 */
/* 0x000f68000c1e1100 */
/*0260*/ LDG.E.U8 R13, [R2.64+0xa] ; /* 0x00000a04020d7981 */
/* 0x000f68000c1e1100 */
/*0270*/ LDG.E.U8 R12, [R2.64+0xb] ; /* 0x00000b04020c7981 */
/* 0x000f68000c1e1100 */
/*0280*/ LDG.E.U8 R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f68000c1e1100 */
/*0290*/ LDG.E.U8 R10, [R2.64+0xd] ; /* 0x00000d04020a7981 */
/* 0x000f68000c1e1100 */
/*02a0*/ LDG.E.U8 R9, [R2.64+0xe] ; /* 0x00000e0402097981 */
/* 0x000f68000c1e1100 */
/*02b0*/ LDG.E.U8 R8, [R2.64+0xf] ; /* 0x00000f0402087981 */
/* 0x000f62000c1e1100 */
/*02c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.NE.AND P1, PT, R23, 0x1, PT ; /* 0x000000011700780c */
/* 0x004fe40003f25270 */
/*02f0*/ ISETP.NE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x008fe40003f45270 */
/*0300*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fd20007ffe0ff */
/*0310*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*0320*/ ISETP.NE.AND P1, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x010fc80003f25270 */
/*0330*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*0340*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*0350*/ ISETP.NE.AND P2, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x020fc80003f45270 */
/*0360*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fc60007ffe0ff */
/*0370*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*0380*/ ISETP.NE.AND P1, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fc80003f25270 */
/*0390*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*03b0*/ ISETP.NE.AND P2, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fc80003f45270 */
/*03c0*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fc60007ffe0ff */
/*03d0*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*03e0*/ ISETP.NE.AND P1, PT, R21, 0x1, PT ; /* 0x000000011500780c */
/* 0x000fc80003f25270 */
/*03f0*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*0400*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*0410*/ ISETP.NE.AND P2, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fc80003f45270 */
/*0420*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fc60007ffe0ff */
/*0430*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*0440*/ ISETP.NE.AND P1, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe40003f25270 */
/*0450*/ ISETP.NE.AND P3, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f65270 */
/*0460*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*0470*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*0480*/ ISETP.NE.AND P2, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc80003f45270 */
/*0490*/ IADD3 R14, R5, 0x1, RZ ; /* 0x00000001050e7810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ @P1 IMAD.MOV R14, RZ, RZ, R5 ; /* 0x000000ffff0e1224 */
/* 0x000fe200078e0205 */
/*04b0*/ ISETP.NE.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fc80003f25270 */
/*04c0*/ IADD3 R5, R14, 0x1, RZ ; /* 0x000000010e057810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ @P2 IMAD.MOV R5, RZ, RZ, R14 ; /* 0x000000ffff052224 */
/* 0x000fe200078e020e */
/*04e0*/ ISETP.NE.AND P2, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f45270 */
/*04f0*/ IADD3 R12, R5, 0x1, RZ ; /* 0x00000001050c7810 */
/* 0x000fc60007ffe0ff */
/*0500*/ @P1 IMAD.MOV R12, RZ, RZ, R5 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0205 */
/*0510*/ ISETP.NE.AND P1, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc80003f25270 */
/*0520*/ IADD3 R5, R12, 0x1, RZ ; /* 0x000000010c057810 */
/* 0x000fe20007ffe0ff */
/*0530*/ @P2 IMAD.MOV R5, RZ, RZ, R12 ; /* 0x000000ffff052224 */
/* 0x000fe200078e020c */
/*0540*/ ISETP.NE.AND P2, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f45270 */
/*0550*/ IADD3 R10, R5, 0x1, RZ ; /* 0x00000001050a7810 */
/* 0x000fc60007ffe0ff */
/*0560*/ @P1 IMAD.MOV R10, RZ, RZ, R5 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e0205 */
/*0570*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f25270 */
/*0580*/ IADD3 R5, R10, 0x1, RZ ; /* 0x000000010a057810 */
/* 0x000fe20007ffe0ff */
/*0590*/ @P2 IMAD.MOV R5, RZ, RZ, R10 ; /* 0x000000ffff052224 */
/* 0x000fe200078e020a */
/*05a0*/ ISETP.GT.AND P2, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc80003f44270 */
/*05b0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ @P3 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff083224 */
/* 0x000fe200078e0205 */
/*05d0*/ IADD3 R2, P3, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc80007f7e0ff */
/*05e0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*0600*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*0610*/ @P2 BRA 0x1c0 ; /* 0xfffffba000002947 */
/* 0x000fea000383ffff */
/*0620*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0630*/ @!P1 BRA 0x890 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*0640*/ LDG.E.U8 R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000a8000c1e1100 */
/*0650*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */
/* 0x0000e8000c1e1100 */
/*0660*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000128000c1e1100 */
/*0670*/ LDG.E.U8 R10, [R2.64+0x3] ; /* 0x00000304020a7981 */
/* 0x000168000c1e1100 */
/*0680*/ LDG.E.U8 R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000168000c1e1100 */
/*0690*/ LDG.E.U8 R12, [R2.64+0x5] ; /* 0x00000504020c7981 */
/* 0x000168000c1e1100 */
/*06a0*/ LDG.E.U8 R13, [R2.64+0x6] ; /* 0x00000604020d7981 */
/* 0x000168000c1e1100 */
/*06b0*/ LDG.E.U8 R14, [R2.64+0x7] ; /* 0x00000704020e7981 */
/* 0x000162000c1e1100 */
/*06c0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ IADD3 R2, P2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x001fca0007f5e0ff */
/*06f0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0700*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x004fe40003f05270 */
/*0710*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x008fe40003f25270 */
/*0720*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fd20007ffe0ff */
/*0730*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0740*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x010fc80003f05270 */
/*0750*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0760*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*0770*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fc80003f25270 */
/*0780*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0790*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*07a0*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc80003f05270 */
/*07b0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*07d0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f25270 */
/*07e0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0800*/ ISETP.NE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fc80003f05270 */
/*0810*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0820*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*0830*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc80003f25270 */
/*0840*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0850*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0860*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0870*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0880*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe400078e0208 */
/*0890*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08a0*/ @!P0 BRA 0xa10 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*08b0*/ LDG.E.U8 R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000a8000c1e1100 */
/*08c0*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */
/* 0x0000e8000c1e1100 */
/*08d0*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000128000c1e1100 */
/*08e0*/ LDG.E.U8 R10, [R2.64+0x3] ; /* 0x00000304020a7981 */
/* 0x000162000c1e1100 */
/*08f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc40007ffe0ff */
/*0900*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0910*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*0920*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0930*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x004fe40003f05270 */
/*0940*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x008fe40003f25270 */
/*0950*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fd20007ffe0ff */
/*0960*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0970*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x010fc80003f05270 */
/*0980*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0990*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*09a0*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fc80003f25270 */
/*09b0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*09c0*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*09d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*09e0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fd000078e0208 */
/*0a00*/ @P0 BRA 0x8b0 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0a10*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0a20*/ @!P0 BRA 0xb00 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a30*/ IMAD R7, R0, c[0x0][0x170], R7 ; /* 0x00005c0000077a24 */
/* 0x000fca00078e0207 */
/*0a40*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0a50*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0a60*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x0000a2000c1e1100 */
/*0a70*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0a80*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0a90*/ IADD3 R2, P2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x001fca0007f5e0ff */
/*0aa0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0ab0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fe40003f05270 */
/*0ac0*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fd60007ffe0ff */
/*0ad0*/ @P0 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff060224 */
/* 0x000fc800078e0205 */
/*0ae0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0af0*/ @P1 BRA 0xa60 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0b00*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0b10*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0b20*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void reduction(bool *B,int *number,int order){
int num = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//if(idx==0) printf("ORDER%d\n",order);
//printf("IDX%d\n",idx);
if(idx<order){
for(int i = 0 ; i<order; i++)
if(B[idx*order+i]==1)
num ++; //= B[idx*order + i];
//if(B[idx]==1)
//printf("CUDANUM%d\n",num);
number[idx] = num;
//atomicAdd(number,num);
//printf("NUMBER%d\n",number);//<<endl;
}
} | .file "tmpxft_000b2b76_00000000-6_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPbPiiPbPii
.type _Z31__device_stub__Z9reductionPbPiiPbPii, @function
_Z31__device_stub__Z9reductionPbPiiPbPii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPbPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPbPiiPbPii, .-_Z31__device_stub__Z9reductionPbPiiPbPii
.globl _Z9reductionPbPii
.type _Z9reductionPbPii, @function
_Z9reductionPbPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPbPiiPbPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPbPii, .-_Z9reductionPbPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPbPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPbPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void reduction(bool *B,int *number,int order){
int num = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//if(idx==0) printf("ORDER%d\n",order);
//printf("IDX%d\n",idx);
if(idx<order){
for(int i = 0 ; i<order; i++)
if(B[idx*order+i]==1)
num ++; //= B[idx*order + i];
//if(B[idx]==1)
//printf("CUDANUM%d\n",num);
number[idx] = num;
//atomicAdd(number,num);
//printf("NUMBER%d\n",number);//<<endl;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduction(bool *B,int *number,int order){
int num = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//if(idx==0) printf("ORDER%d\n",order);
//printf("IDX%d\n",idx);
if(idx<order){
for(int i = 0 ; i<order; i++)
if(B[idx*order+i]==1)
num ++; //= B[idx*order + i];
//if(B[idx]==1)
//printf("CUDANUM%d\n",num);
number[idx] = num;
//atomicAdd(number,num);
//printf("NUMBER%d\n",number);//<<endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduction(bool *B,int *number,int order){
int num = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//if(idx==0) printf("ORDER%d\n",order);
//printf("IDX%d\n",idx);
if(idx<order){
for(int i = 0 ; i<order; i++)
if(B[idx*order+i]==1)
num ++; //= B[idx*order + i];
//if(B[idx]==1)
//printf("CUDANUM%d\n",num);
number[idx] = num;
//atomicAdd(number,num);
//printf("NUMBER%d\n",number);//<<endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPbPii
.globl _Z9reductionPbPii
.p2align 8
.type _Z9reductionPbPii,@function
_Z9reductionPbPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v0, 0
.LBB0_3:
global_load_u8 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPbPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPbPii, .Lfunc_end0-_Z9reductionPbPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPbPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPbPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void reduction(bool *B,int *number,int order){
int num = 0;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
//if(idx==0) printf("ORDER%d\n",order);
//printf("IDX%d\n",idx);
if(idx<order){
for(int i = 0 ; i<order; i++)
if(B[idx*order+i]==1)
num ++; //= B[idx*order + i];
//if(B[idx]==1)
//printf("CUDANUM%d\n",num);
number[idx] = num;
//atomicAdd(number,num);
//printf("NUMBER%d\n",number);//<<endl;
}
} | .text
.file "reduction.hip"
.globl _Z24__device_stub__reductionPbPii # -- Begin function _Z24__device_stub__reductionPbPii
.p2align 4, 0x90
.type _Z24__device_stub__reductionPbPii,@function
_Z24__device_stub__reductionPbPii: # @_Z24__device_stub__reductionPbPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPbPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPbPii, .Lfunc_end0-_Z24__device_stub__reductionPbPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPbPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPbPii,@object # @_Z9reductionPbPii
.section .rodata,"a",@progbits
.globl _Z9reductionPbPii
.p2align 3, 0x0
_Z9reductionPbPii:
.quad _Z24__device_stub__reductionPbPii
.size _Z9reductionPbPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPbPii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPbPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPbPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9reductionPbPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xb00 ; /* 0x00000a5000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00d0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0xa10 ; /* 0x0000090000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004067a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD R3, R0, c[0x0][0x170], RZ ; /* 0x00005c0000037a24 */
/* 0x000fe400078e02ff */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0140*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0150*/ IADD3 R2, P1, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f3e0ff */
/*0160*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P1 ; /* 0x0000590003037a11 */
/* 0x000fce00008f0eff */
/*0170*/ @!P0 BRA 0x8b0 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P1 BRA 0x620 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ LDG.E.U8 R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x000ea8000c1e1100 */
/*01d0*/ LDG.E.U8 R16, [R2.64+0x1] ; /* 0x0000010402107981 */
/* 0x000ee8000c1e1100 */
/*01e0*/ LDG.E.U8 R17, [R2.64+0x2] ; /* 0x0000020402117981 */
/* 0x000f28000c1e1100 */
/*01f0*/ LDG.E.U8 R18, [R2.64+0x3] ; /* 0x0000030402127981 */
/* 0x000f68000c1e1100 */
/*0200*/ LDG.E.U8 R19, [R2.64+0x4] ; /* 0x0000040402137981 */
/* 0x000f68000c1e1100 */
/*0210*/ LDG.E.U8 R20, [R2.64+0x5] ; /* 0x0000050402147981 */
/* 0x000f68000c1e1100 */
/*0220*/ LDG.E.U8 R21, [R2.64+0x6] ; /* 0x0000060402157981 */
/* 0x000f68000c1e1100 */
/*0230*/ LDG.E.U8 R22, [R2.64+0x7] ; /* 0x0000070402167981 */
/* 0x000f68000c1e1100 */
/*0240*/ LDG.E.U8 R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000f68000c1e1100 */
/*0250*/ LDG.E.U8 R14, [R2.64+0x9] ; /* 0x00000904020e7981 */
/* 0x000f68000c1e1100 */
/*0260*/ LDG.E.U8 R13, [R2.64+0xa] ; /* 0x00000a04020d7981 */
/* 0x000f68000c1e1100 */
/*0270*/ LDG.E.U8 R12, [R2.64+0xb] ; /* 0x00000b04020c7981 */
/* 0x000f68000c1e1100 */
/*0280*/ LDG.E.U8 R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000f68000c1e1100 */
/*0290*/ LDG.E.U8 R10, [R2.64+0xd] ; /* 0x00000d04020a7981 */
/* 0x000f68000c1e1100 */
/*02a0*/ LDG.E.U8 R9, [R2.64+0xe] ; /* 0x00000e0402097981 */
/* 0x000f68000c1e1100 */
/*02b0*/ LDG.E.U8 R8, [R2.64+0xf] ; /* 0x00000f0402087981 */
/* 0x000f62000c1e1100 */
/*02c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.NE.AND P1, PT, R23, 0x1, PT ; /* 0x000000011700780c */
/* 0x004fe40003f25270 */
/*02f0*/ ISETP.NE.AND P2, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x008fe40003f45270 */
/*0300*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fd20007ffe0ff */
/*0310*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*0320*/ ISETP.NE.AND P1, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x010fc80003f25270 */
/*0330*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*0340*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*0350*/ ISETP.NE.AND P2, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x020fc80003f45270 */
/*0360*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fc60007ffe0ff */
/*0370*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*0380*/ ISETP.NE.AND P1, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fc80003f25270 */
/*0390*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*03b0*/ ISETP.NE.AND P2, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fc80003f45270 */
/*03c0*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fc60007ffe0ff */
/*03d0*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*03e0*/ ISETP.NE.AND P1, PT, R21, 0x1, PT ; /* 0x000000011500780c */
/* 0x000fc80003f25270 */
/*03f0*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*0400*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*0410*/ ISETP.NE.AND P2, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fc80003f45270 */
/*0420*/ IADD3 R16, R5, 0x1, RZ ; /* 0x0000000105107810 */
/* 0x000fc60007ffe0ff */
/*0430*/ @P1 IMAD.MOV R16, RZ, RZ, R5 ; /* 0x000000ffff101224 */
/* 0x000fe200078e0205 */
/*0440*/ ISETP.NE.AND P1, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe40003f25270 */
/*0450*/ ISETP.NE.AND P3, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f65270 */
/*0460*/ IADD3 R5, R16, 0x1, RZ ; /* 0x0000000110057810 */
/* 0x000fe20007ffe0ff */
/*0470*/ @P2 IMAD.MOV R5, RZ, RZ, R16 ; /* 0x000000ffff052224 */
/* 0x000fe200078e0210 */
/*0480*/ ISETP.NE.AND P2, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc80003f45270 */
/*0490*/ IADD3 R14, R5, 0x1, RZ ; /* 0x00000001050e7810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ @P1 IMAD.MOV R14, RZ, RZ, R5 ; /* 0x000000ffff0e1224 */
/* 0x000fe200078e0205 */
/*04b0*/ ISETP.NE.AND P1, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fc80003f25270 */
/*04c0*/ IADD3 R5, R14, 0x1, RZ ; /* 0x000000010e057810 */
/* 0x000fe20007ffe0ff */
/*04d0*/ @P2 IMAD.MOV R5, RZ, RZ, R14 ; /* 0x000000ffff052224 */
/* 0x000fe200078e020e */
/*04e0*/ ISETP.NE.AND P2, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f45270 */
/*04f0*/ IADD3 R12, R5, 0x1, RZ ; /* 0x00000001050c7810 */
/* 0x000fc60007ffe0ff */
/*0500*/ @P1 IMAD.MOV R12, RZ, RZ, R5 ; /* 0x000000ffff0c1224 */
/* 0x000fe200078e0205 */
/*0510*/ ISETP.NE.AND P1, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc80003f25270 */
/*0520*/ IADD3 R5, R12, 0x1, RZ ; /* 0x000000010c057810 */
/* 0x000fe20007ffe0ff */
/*0530*/ @P2 IMAD.MOV R5, RZ, RZ, R12 ; /* 0x000000ffff052224 */
/* 0x000fe200078e020c */
/*0540*/ ISETP.NE.AND P2, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc80003f45270 */
/*0550*/ IADD3 R10, R5, 0x1, RZ ; /* 0x00000001050a7810 */
/* 0x000fc60007ffe0ff */
/*0560*/ @P1 IMAD.MOV R10, RZ, RZ, R5 ; /* 0x000000ffff0a1224 */
/* 0x000fe200078e0205 */
/*0570*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fc80003f25270 */
/*0580*/ IADD3 R5, R10, 0x1, RZ ; /* 0x000000010a057810 */
/* 0x000fe20007ffe0ff */
/*0590*/ @P2 IMAD.MOV R5, RZ, RZ, R10 ; /* 0x000000ffff052224 */
/* 0x000fe200078e020a */
/*05a0*/ ISETP.GT.AND P2, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc80003f44270 */
/*05b0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ @P3 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff083224 */
/* 0x000fe200078e0205 */
/*05d0*/ IADD3 R2, P3, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc80007f7e0ff */
/*05e0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*05f0*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*0600*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*0610*/ @P2 BRA 0x1c0 ; /* 0xfffffba000002947 */
/* 0x000fea000383ffff */
/*0620*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0630*/ @!P1 BRA 0x890 ; /* 0x0000025000009947 */
/* 0x000fea0003800000 */
/*0640*/ LDG.E.U8 R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x0000a8000c1e1100 */
/*0650*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */
/* 0x0000e8000c1e1100 */
/*0660*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000128000c1e1100 */
/*0670*/ LDG.E.U8 R10, [R2.64+0x3] ; /* 0x00000304020a7981 */
/* 0x000168000c1e1100 */
/*0680*/ LDG.E.U8 R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000168000c1e1100 */
/*0690*/ LDG.E.U8 R12, [R2.64+0x5] ; /* 0x00000504020c7981 */
/* 0x000168000c1e1100 */
/*06a0*/ LDG.E.U8 R13, [R2.64+0x6] ; /* 0x00000604020d7981 */
/* 0x000168000c1e1100 */
/*06b0*/ LDG.E.U8 R14, [R2.64+0x7] ; /* 0x00000704020e7981 */
/* 0x000162000c1e1100 */
/*06c0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fc40007ffe0ff */
/*06d0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ IADD3 R2, P2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x001fca0007f5e0ff */
/*06f0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0700*/ ISETP.NE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x004fe40003f05270 */
/*0710*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x008fe40003f25270 */
/*0720*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fd20007ffe0ff */
/*0730*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0740*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x010fc80003f05270 */
/*0750*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0760*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*0770*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fc80003f25270 */
/*0780*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0790*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*07a0*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fc80003f05270 */
/*07b0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*07d0*/ ISETP.NE.AND P1, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fc80003f25270 */
/*07e0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*07f0*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0800*/ ISETP.NE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fc80003f05270 */
/*0810*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0820*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*0830*/ ISETP.NE.AND P1, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fc80003f25270 */
/*0840*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*0850*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0860*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*0870*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0880*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe400078e0208 */
/*0890*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08a0*/ @!P0 BRA 0xa10 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*08b0*/ LDG.E.U8 R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0000a8000c1e1100 */
/*08c0*/ LDG.E.U8 R8, [R2.64+0x1] ; /* 0x0000010402087981 */
/* 0x0000e8000c1e1100 */
/*08d0*/ LDG.E.U8 R9, [R2.64+0x2] ; /* 0x0000020402097981 */
/* 0x000128000c1e1100 */
/*08e0*/ LDG.E.U8 R10, [R2.64+0x3] ; /* 0x00000304020a7981 */
/* 0x000162000c1e1100 */
/*08f0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc40007ffe0ff */
/*0900*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0910*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*0920*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0930*/ ISETP.NE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x004fe40003f05270 */
/*0940*/ ISETP.NE.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x008fe40003f25270 */
/*0950*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fd20007ffe0ff */
/*0960*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*0970*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x010fc80003f05270 */
/*0980*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*0990*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fe200078e0208 */
/*09a0*/ ISETP.NE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x020fc80003f25270 */
/*09b0*/ IADD3 R8, R5, 0x1, RZ ; /* 0x0000000105087810 */
/* 0x000fc60007ffe0ff */
/*09c0*/ @P0 IMAD.MOV R8, RZ, RZ, R5 ; /* 0x000000ffff080224 */
/* 0x000fe200078e0205 */
/*09d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*09e0*/ IADD3 R5, R8, 0x1, RZ ; /* 0x0000000108057810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ @P1 IMAD.MOV R5, RZ, RZ, R8 ; /* 0x000000ffff051224 */
/* 0x000fd000078e0208 */
/*0a00*/ @P0 BRA 0x8b0 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0a10*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0a20*/ @!P0 BRA 0xb00 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0a30*/ IMAD R7, R0, c[0x0][0x170], R7 ; /* 0x00005c0000077a24 */
/* 0x000fca00078e0207 */
/*0a40*/ IADD3 R2, P0, R7, c[0x0][0x160], RZ ; /* 0x0000580007027a10 */
/* 0x000fc80007f1e0ff */
/*0a50*/ LEA.HI.X.SX32 R3, R7, c[0x0][0x164], 0x1, P0 ; /* 0x0000590007037a11 */
/* 0x000fca00000f0eff */
/*0a60*/ LDG.E.U8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x0000a2000c1e1100 */
/*0a70*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0a80*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0a90*/ IADD3 R2, P2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x001fca0007f5e0ff */
/*0aa0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0ab0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x004fe40003f05270 */
/*0ac0*/ IADD3 R6, R5, 0x1, RZ ; /* 0x0000000105067810 */
/* 0x000fd60007ffe0ff */
/*0ad0*/ @P0 IMAD.MOV R6, RZ, RZ, R5 ; /* 0x000000ffff060224 */
/* 0x000fc800078e0205 */
/*0ae0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0006 */
/*0af0*/ @P1 BRA 0xa60 ; /* 0xffffff6000001947 */
/* 0x000fea000383ffff */
/*0b00*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0b10*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0b20*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9reductionPbPii
.globl _Z9reductionPbPii
.p2align 8
.type _Z9reductionPbPii,@function
_Z9reductionPbPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v0, 0
.LBB0_3:
global_load_u8 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9reductionPbPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9reductionPbPii, .Lfunc_end0-_Z9reductionPbPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9reductionPbPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9reductionPbPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b2b76_00000000-6_reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9reductionPbPiiPbPii
.type _Z31__device_stub__Z9reductionPbPiiPbPii, @function
_Z31__device_stub__Z9reductionPbPiiPbPii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9reductionPbPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9reductionPbPiiPbPii, .-_Z31__device_stub__Z9reductionPbPiiPbPii
.globl _Z9reductionPbPii
.type _Z9reductionPbPii, @function
_Z9reductionPbPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9reductionPbPiiPbPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9reductionPbPii, .-_Z9reductionPbPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9reductionPbPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9reductionPbPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduction.hip"
.globl _Z24__device_stub__reductionPbPii # -- Begin function _Z24__device_stub__reductionPbPii
.p2align 4, 0x90
.type _Z24__device_stub__reductionPbPii,@function
_Z24__device_stub__reductionPbPii: # @_Z24__device_stub__reductionPbPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9reductionPbPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__reductionPbPii, .Lfunc_end0-_Z24__device_stub__reductionPbPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9reductionPbPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9reductionPbPii,@object # @_Z9reductionPbPii
.section .rodata,"a",@progbits
.globl _Z9reductionPbPii
.p2align 3, 0x0
_Z9reductionPbPii:
.quad _Z24__device_stub__reductionPbPii
.size _Z9reductionPbPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9reductionPbPii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__reductionPbPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9reductionPbPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void evaluateSymbolRegression(float* resultScore, float* result, float* programArray, float* evaluateBuffer, int* stackCountArray, int* programLength, int *maxProgramLengthFromMain, int *targetFunction, float* targetValueArray){
// allocate buffer for processing
const unsigned int maxProgramLength = maxProgramLengthFromMain[0];
// extern __shared__ float copyBuffer[];
const int index = threadIdx.x;
int posCounter = programLength[index] - 1;
// Copy a program array(individual) into buffer for processing
while(posCounter >= 0){
evaluateBuffer[index*maxProgramLength + posCounter] =
programArray[index*maxProgramLength + posCounter];
posCounter--;
}
unsigned int currentProgramLength = programLength[index];
while(currentProgramLength > 1){
unsigned int currentProgramNode = 0;
for(int i=currentProgramLength-1; i>=0; i--){
// Remainder with 1.0 equals 0.0 (means integer),
// stack count is less than zero,
// detected as function node
if(fmod((double)evaluateBuffer[index*maxProgramLength + i], 1.0) == 0.0 &&
(int)evaluateBuffer[index*maxProgramLength + i] > 65535 &&
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + i] - 65535] <= 0){
// Search Last Function Node
currentProgramNode = i;
break;
}
}
int currentStackCount =
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] -65535];
unsigned int subTreeRange = 1;
while(currentStackCount < 1){
currentStackCount += 1;
subTreeRange++;
}
float resultFromFunctionNode = 0.0;
unsigned int functionLabel =
(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] - 65535;
switch(functionLabel){
case 0: //add
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
+
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 1: //sub
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
-
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 2: //mul
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
*
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 3: //div
if(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1] != 0.0 &&
evaluateBuffer[index*maxProgramLength + currentProgramNode + 2] != 0.0){
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
/
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
}
else
resultFromFunctionNode = 1.0;
break;
case 4: //IfLessThenElse
if(evaluateBuffer[index*maxProgramLength + currentProgramNode +1] >
evaluateBuffer[index*maxProgramLength + currentProgramNode +2])
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 3];
else
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 4];
break;
case 5: //cos
resultFromFunctionNode =
cos(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
case 6: //sin
resultFromFunctionNode =
sin(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
default:
resultFromFunctionNode = 0.0;
break;
}
// Replace current function node with result of calc subtree
evaluateBuffer[index*maxProgramLength + currentProgramNode] =
resultFromFunctionNode;
// Copy node array after current subtree.
for(int i=0; i<subTreeRange; i++)
evaluateBuffer[index*maxProgramLength + currentProgramNode + 1 + i] =
evaluateBuffer[index*maxProgramLength + currentProgramNode + subTreeRange + i];
// new currentProgramLength
currentProgramLength = currentProgramLength - subTreeRange + 1;
// Fill zero after currentProgramLength
for(int i=index*maxProgramLength + currentProgramLength;
i<(index+1)*maxProgramLength;
i++)
evaluateBuffer[i] = 0.0;
}
result[index] = (float)evaluateBuffer[index*maxProgramLength] - targetValueArray[index] * evaluateBuffer[index*maxProgramLength] - targetValueArray[index];
__syncthreads(); // Waiting Finish All Threads
resultScore[0] = 0.0;
if(index == 0){ // If thread ID == 0 then calc score from RSS array
float sum = 0;
for(unsigned int j=0; j<blockDim.x; j++){
sum += result[j];
}
if(targetFunction[0] == 0){ //MSE: Mean Square Error
resultScore[0] = (sum / blockDim.x);
}
else if(targetFunction[0] == 1){ //MDL: Minimum Description Length
resultScore[0] = (sum / blockDim.x) + (programLength[0] * logf(blockDim.x));
}
else{
resultScore[0] = 0.0;
}
}
} | .file "tmpxft_0018f88b_00000000-6_evaluateSymbolRegression.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
.type _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_, @function
_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_, .-_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
.globl _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.type _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, @function
_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, .-_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void evaluateSymbolRegression(float* resultScore, float* result, float* programArray, float* evaluateBuffer, int* stackCountArray, int* programLength, int *maxProgramLengthFromMain, int *targetFunction, float* targetValueArray){
// allocate buffer for processing
const unsigned int maxProgramLength = maxProgramLengthFromMain[0];
// extern __shared__ float copyBuffer[];
const int index = threadIdx.x;
int posCounter = programLength[index] - 1;
// Copy a program array(individual) into buffer for processing
while(posCounter >= 0){
evaluateBuffer[index*maxProgramLength + posCounter] =
programArray[index*maxProgramLength + posCounter];
posCounter--;
}
unsigned int currentProgramLength = programLength[index];
while(currentProgramLength > 1){
unsigned int currentProgramNode = 0;
for(int i=currentProgramLength-1; i>=0; i--){
// Remainder with 1.0 equals 0.0 (means integer),
// stack count is less than zero,
// detected as function node
if(fmod((double)evaluateBuffer[index*maxProgramLength + i], 1.0) == 0.0 &&
(int)evaluateBuffer[index*maxProgramLength + i] > 65535 &&
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + i] - 65535] <= 0){
// Search Last Function Node
currentProgramNode = i;
break;
}
}
int currentStackCount =
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] -65535];
unsigned int subTreeRange = 1;
while(currentStackCount < 1){
currentStackCount += 1;
subTreeRange++;
}
float resultFromFunctionNode = 0.0;
unsigned int functionLabel =
(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] - 65535;
switch(functionLabel){
case 0: //add
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
+
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 1: //sub
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
-
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 2: //mul
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
*
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 3: //div
if(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1] != 0.0 &&
evaluateBuffer[index*maxProgramLength + currentProgramNode + 2] != 0.0){
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
/
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
}
else
resultFromFunctionNode = 1.0;
break;
case 4: //IfLessThenElse
if(evaluateBuffer[index*maxProgramLength + currentProgramNode +1] >
evaluateBuffer[index*maxProgramLength + currentProgramNode +2])
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 3];
else
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 4];
break;
case 5: //cos
resultFromFunctionNode =
cos(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
case 6: //sin
resultFromFunctionNode =
sin(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
default:
resultFromFunctionNode = 0.0;
break;
}
// Replace current function node with result of calc subtree
evaluateBuffer[index*maxProgramLength + currentProgramNode] =
resultFromFunctionNode;
// Copy node array after current subtree.
for(int i=0; i<subTreeRange; i++)
evaluateBuffer[index*maxProgramLength + currentProgramNode + 1 + i] =
evaluateBuffer[index*maxProgramLength + currentProgramNode + subTreeRange + i];
// new currentProgramLength
currentProgramLength = currentProgramLength - subTreeRange + 1;
// Fill zero after currentProgramLength
for(int i=index*maxProgramLength + currentProgramLength;
i<(index+1)*maxProgramLength;
i++)
evaluateBuffer[i] = 0.0;
}
result[index] = (float)evaluateBuffer[index*maxProgramLength] - targetValueArray[index] * evaluateBuffer[index*maxProgramLength] - targetValueArray[index];
__syncthreads(); // Waiting Finish All Threads
resultScore[0] = 0.0;
if(index == 0){ // If thread ID == 0 then calc score from RSS array
float sum = 0;
for(unsigned int j=0; j<blockDim.x; j++){
sum += result[j];
}
if(targetFunction[0] == 0){ //MSE: Mean Square Error
resultScore[0] = (sum / blockDim.x);
}
else if(targetFunction[0] == 1){ //MDL: Minimum Description Length
resultScore[0] = (sum / blockDim.x) + (programLength[0] * logf(blockDim.x));
}
else{
resultScore[0] = 0.0;
}
}
} | #include <hip/hip_runtime.h>
__global__ void evaluateSymbolRegression(float* resultScore, float* result, float* programArray, float* evaluateBuffer, int* stackCountArray, int* programLength, int *maxProgramLengthFromMain, int *targetFunction, float* targetValueArray){
// allocate buffer for processing
const unsigned int maxProgramLength = maxProgramLengthFromMain[0];
// extern __shared__ float copyBuffer[];
const int index = threadIdx.x;
int posCounter = programLength[index] - 1;
// Copy a program array(individual) into buffer for processing
while(posCounter >= 0){
evaluateBuffer[index*maxProgramLength + posCounter] =
programArray[index*maxProgramLength + posCounter];
posCounter--;
}
unsigned int currentProgramLength = programLength[index];
while(currentProgramLength > 1){
unsigned int currentProgramNode = 0;
for(int i=currentProgramLength-1; i>=0; i--){
// Remainder with 1.0 equals 0.0 (means integer),
// stack count is less than zero,
// detected as function node
if(fmod((double)evaluateBuffer[index*maxProgramLength + i], 1.0) == 0.0 &&
(int)evaluateBuffer[index*maxProgramLength + i] > 65535 &&
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + i] - 65535] <= 0){
// Search Last Function Node
currentProgramNode = i;
break;
}
}
int currentStackCount =
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] -65535];
unsigned int subTreeRange = 1;
while(currentStackCount < 1){
currentStackCount += 1;
subTreeRange++;
}
float resultFromFunctionNode = 0.0;
unsigned int functionLabel =
(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] - 65535;
switch(functionLabel){
case 0: //add
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
+
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 1: //sub
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
-
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 2: //mul
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
*
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 3: //div
if(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1] != 0.0 &&
evaluateBuffer[index*maxProgramLength + currentProgramNode + 2] != 0.0){
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
/
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
}
else
resultFromFunctionNode = 1.0;
break;
case 4: //IfLessThenElse
if(evaluateBuffer[index*maxProgramLength + currentProgramNode +1] >
evaluateBuffer[index*maxProgramLength + currentProgramNode +2])
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 3];
else
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 4];
break;
case 5: //cos
resultFromFunctionNode =
cos(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
case 6: //sin
resultFromFunctionNode =
sin(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
default:
resultFromFunctionNode = 0.0;
break;
}
// Replace current function node with result of calc subtree
evaluateBuffer[index*maxProgramLength + currentProgramNode] =
resultFromFunctionNode;
// Copy node array after current subtree.
for(int i=0; i<subTreeRange; i++)
evaluateBuffer[index*maxProgramLength + currentProgramNode + 1 + i] =
evaluateBuffer[index*maxProgramLength + currentProgramNode + subTreeRange + i];
// new currentProgramLength
currentProgramLength = currentProgramLength - subTreeRange + 1;
// Fill zero after currentProgramLength
for(int i=index*maxProgramLength + currentProgramLength;
i<(index+1)*maxProgramLength;
i++)
evaluateBuffer[i] = 0.0;
}
result[index] = (float)evaluateBuffer[index*maxProgramLength] - targetValueArray[index] * evaluateBuffer[index*maxProgramLength] - targetValueArray[index];
__syncthreads(); // Waiting Finish All Threads
resultScore[0] = 0.0;
if(index == 0){ // If thread ID == 0 then calc score from RSS array
float sum = 0;
for(unsigned int j=0; j<blockDim.x; j++){
sum += result[j];
}
if(targetFunction[0] == 0){ //MSE: Mean Square Error
resultScore[0] = (sum / blockDim.x);
}
else if(targetFunction[0] == 1){ //MDL: Minimum Description Length
resultScore[0] = (sum / blockDim.x) + (programLength[0] * logf(blockDim.x));
}
else{
resultScore[0] = 0.0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void evaluateSymbolRegression(float* resultScore, float* result, float* programArray, float* evaluateBuffer, int* stackCountArray, int* programLength, int *maxProgramLengthFromMain, int *targetFunction, float* targetValueArray){
// allocate buffer for processing
const unsigned int maxProgramLength = maxProgramLengthFromMain[0];
// extern __shared__ float copyBuffer[];
const int index = threadIdx.x;
int posCounter = programLength[index] - 1;
// Copy a program array(individual) into buffer for processing
while(posCounter >= 0){
evaluateBuffer[index*maxProgramLength + posCounter] =
programArray[index*maxProgramLength + posCounter];
posCounter--;
}
unsigned int currentProgramLength = programLength[index];
while(currentProgramLength > 1){
unsigned int currentProgramNode = 0;
for(int i=currentProgramLength-1; i>=0; i--){
// Remainder with 1.0 equals 0.0 (means integer),
// stack count is less than zero,
// detected as function node
if(fmod((double)evaluateBuffer[index*maxProgramLength + i], 1.0) == 0.0 &&
(int)evaluateBuffer[index*maxProgramLength + i] > 65535 &&
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + i] - 65535] <= 0){
// Search Last Function Node
currentProgramNode = i;
break;
}
}
int currentStackCount =
stackCountArray[(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] -65535];
unsigned int subTreeRange = 1;
while(currentStackCount < 1){
currentStackCount += 1;
subTreeRange++;
}
float resultFromFunctionNode = 0.0;
unsigned int functionLabel =
(int)evaluateBuffer[index*maxProgramLength + currentProgramNode] - 65535;
switch(functionLabel){
case 0: //add
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
+
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 1: //sub
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
-
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 2: //mul
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
*
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
break;
case 3: //div
if(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1] != 0.0 &&
evaluateBuffer[index*maxProgramLength + currentProgramNode + 2] != 0.0){
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode +1]
/
evaluateBuffer[index*maxProgramLength + currentProgramNode +2];
}
else
resultFromFunctionNode = 1.0;
break;
case 4: //IfLessThenElse
if(evaluateBuffer[index*maxProgramLength + currentProgramNode +1] >
evaluateBuffer[index*maxProgramLength + currentProgramNode +2])
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 3];
else
resultFromFunctionNode =
evaluateBuffer[index*maxProgramLength + currentProgramNode + 4];
break;
case 5: //cos
resultFromFunctionNode =
cos(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
case 6: //sin
resultFromFunctionNode =
sin(evaluateBuffer[index*maxProgramLength + currentProgramNode + 1]);
break;
default:
resultFromFunctionNode = 0.0;
break;
}
// Replace current function node with result of calc subtree
evaluateBuffer[index*maxProgramLength + currentProgramNode] =
resultFromFunctionNode;
// Copy node array after current subtree.
for(int i=0; i<subTreeRange; i++)
evaluateBuffer[index*maxProgramLength + currentProgramNode + 1 + i] =
evaluateBuffer[index*maxProgramLength + currentProgramNode + subTreeRange + i];
// new currentProgramLength
currentProgramLength = currentProgramLength - subTreeRange + 1;
// Fill zero after currentProgramLength
for(int i=index*maxProgramLength + currentProgramLength;
i<(index+1)*maxProgramLength;
i++)
evaluateBuffer[i] = 0.0;
}
result[index] = (float)evaluateBuffer[index*maxProgramLength] - targetValueArray[index] * evaluateBuffer[index*maxProgramLength] - targetValueArray[index];
__syncthreads(); // Waiting Finish All Threads
resultScore[0] = 0.0;
if(index == 0){ // If thread ID == 0 then calc score from RSS array
float sum = 0;
for(unsigned int j=0; j<blockDim.x; j++){
sum += result[j];
}
if(targetFunction[0] == 0){ //MSE: Mean Square Error
resultScore[0] = (sum / blockDim.x);
}
else if(targetFunction[0] == 1){ //MDL: Minimum Description Length
resultScore[0] = (sum / blockDim.x) + (programLength[0] * logf(blockDim.x));
}
else{
resultScore[0] = 0.0;
}
}
} | .text
.file "evaluateSymbolRegression.hip"
.globl _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_ # -- Begin function _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.p2align 4, 0x90
.type _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_,@function
_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_: # @_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, .Lfunc_end0-_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_,@object # @_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.section .rodata,"a",@progbits
.globl _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.p2align 3, 0x0
_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_:
.quad _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.size _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f88b_00000000-6_evaluateSymbolRegression.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
.type _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_, @function
_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movq %r8, 40(%rsp)
movq %r9, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 24(%rsp)
movq 248(%rsp), %rax
movq %rax, 16(%rsp)
movq 256(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 248
pushq 88(%rsp)
.cfi_def_cfa_offset 256
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_, .-_Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
.globl _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.type _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, @function
_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z63__device_stub__Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_PfS_S_S_PiS0_S0_S0_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, .-_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "evaluateSymbolRegression.hip"
.globl _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_ # -- Begin function _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.p2align 4, 0x90
.type _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_,@function
_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_: # @_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, .Lfunc_end0-_Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_,@object # @_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.section .rodata,"a",@progbits
.globl _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.p2align 3, 0x0
_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_:
.quad _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.size _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24evaluateSymbolRegressionPfS_S_S_PiS0_S0_S0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void hello() {
printf("Hello world! I\'m a thread in block %d\n", blockIdx.x);
}
int main(int argc, char** argv) {
hello<<<16, 1>>>();
// this statement will make the printfs() to flush to stdout
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void hello() {
printf("Hello world! I\'m a thread in block %d\n", blockIdx.x);
}
int main(int argc, char** argv) {
hello<<<16, 1>>>();
// this statement will make the printfs() to flush to stdout
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0002628a_00000000-6_order.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void hello() {
printf("Hello world! I\'m a thread in block %d\n", blockIdx.x);
}
int main(int argc, char** argv) {
hello<<<16, 1>>>();
// this statement will make the printfs() to flush to stdout
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello() {
printf("Hello world! I\'m a thread in block %d\n", blockIdx.x);
}
int main(int argc, char** argv) {
hello<<<16, 1>>>();
// this statement will make the printfs() to flush to stdout
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void hello() {
printf("Hello world! I\'m a thread in block %d\n", blockIdx.x);
}
int main(int argc, char** argv) {
hello<<<16, 1>>>();
// this statement will make the printfs() to flush to stdout
hipDeviceSynchronize();
return 0;
} | .text
.file "order.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 15(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002628a_00000000-6_order.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5hellov, .-_Z5hellov
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $16, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z23__device_stub__Z5hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "order.hip"
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z20__device_stub__hellov, .Lfunc_end0-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 15(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5hellov,@object # @_Z5hellov
.section .rodata,"a",@progbits
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5hellov"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // From CUDA for Engineer
// Listing D.5
#include <iostream>
#include <cuda_runtime.h>
using namespace std;
int main()
{
int numDevices = 0;
cudaGetDeviceCount(&numDevices);
cout << "Number of devices = " << numDevices << "\n";
for (int i = 0; i < numDevices; i++) {
struct cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
cout << "Device Number: " << i << "\n"
<< "Device name: " << prop.name << "\n"
<< "Compute capability: " << prop.major << "." << prop.minor << "\n"
<< "MultiProcessor count: " << prop.multiProcessorCount << "\n"
<< "Maximum threads/block: " << prop.maxThreadsPerBlock << "\n"
<< "Shared memory/block: " << prop.sharedMemPerBlock/1024.0 << " KBytes\n"
<< "Total global memory: " << prop.totalGlobalMem/1e9 << " Gbs\n"
<< "Total constant memory: " << prop.totalConstMem/1024.0 << " KBytes\n";
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // From CUDA for Engineer
// Listing D.5
#include <iostream>
#include <cuda_runtime.h>
using namespace std;
int main()
{
int numDevices = 0;
cudaGetDeviceCount(&numDevices);
cout << "Number of devices = " << numDevices << "\n";
for (int i = 0; i < numDevices; i++) {
struct cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
cout << "Device Number: " << i << "\n"
<< "Device name: " << prop.name << "\n"
<< "Compute capability: " << prop.major << "." << prop.minor << "\n"
<< "MultiProcessor count: " << prop.multiProcessorCount << "\n"
<< "Maximum threads/block: " << prop.maxThreadsPerBlock << "\n"
<< "Shared memory/block: " << prop.sharedMemPerBlock/1024.0 << " KBytes\n"
<< "Total global memory: " << prop.totalGlobalMem/1e9 << " Gbs\n"
<< "Total constant memory: " << prop.totalConstMem/1024.0 << " KBytes\n";
}
return 0;
} | .file "tmpxft_0009a82c_00000000-6_device_property.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of devices = "
.LC1:
.string "\n"
.LC2:
.string "Device Number: "
.LC3:
.string "Device name: "
.LC4:
.string "Compute capability: "
.LC5:
.string "."
.LC6:
.string "MultiProcessor count: "
.LC7:
.string "Maximum threads/block: "
.LC8:
.string "Shared memory/block: "
.LC10:
.string " KBytes\n"
.LC11:
.string "Total global memory: "
.LC13:
.string " Gbs\n"
.LC14:
.string "Total constant memory: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC10(%rip), %r12
jmp .L11
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L6
.L7:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L8
.L9:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L10:
mulsd .LC9(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $8, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L11:
leaq 16(%rsp), %r14
movl %ebp, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $15, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $13, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $20, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $22, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 404(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $23, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 336(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $21, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L6:
mulsd .LC9(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $8, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $21, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rax
testq %rax, %rax
js .L7
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L8:
divsd .LC12(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $5, %edx
leaq .LC13(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $23, %edx
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 368(%rsp), %rax
testq %rax, %rax
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L10
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1062207488
.align 8
.LC12:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // From CUDA for Engineer
// Listing D.5
#include <iostream>
#include <cuda_runtime.h>
using namespace std;
int main()
{
int numDevices = 0;
cudaGetDeviceCount(&numDevices);
cout << "Number of devices = " << numDevices << "\n";
for (int i = 0; i < numDevices; i++) {
struct cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, i);
cout << "Device Number: " << i << "\n"
<< "Device name: " << prop.name << "\n"
<< "Compute capability: " << prop.major << "." << prop.minor << "\n"
<< "MultiProcessor count: " << prop.multiProcessorCount << "\n"
<< "Maximum threads/block: " << prop.maxThreadsPerBlock << "\n"
<< "Shared memory/block: " << prop.sharedMemPerBlock/1024.0 << " KBytes\n"
<< "Total global memory: " << prop.totalGlobalMem/1e9 << " Gbs\n"
<< "Total constant memory: " << prop.totalConstMem/1024.0 << " KBytes\n";
}
return 0;
} | // From CUDA for Engineer
// Listing D.5
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
int main()
{
int numDevices = 0;
hipGetDeviceCount(&numDevices);
cout << "Number of devices = " << numDevices << "\n";
for (int i = 0; i < numDevices; i++) {
struct hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
cout << "Device Number: " << i << "\n"
<< "Device name: " << prop.name << "\n"
<< "Compute capability: " << prop.major << "." << prop.minor << "\n"
<< "MultiProcessor count: " << prop.multiProcessorCount << "\n"
<< "Maximum threads/block: " << prop.maxThreadsPerBlock << "\n"
<< "Shared memory/block: " << prop.sharedMemPerBlock/1024.0 << " KBytes\n"
<< "Total global memory: " << prop.totalGlobalMem/1e9 << " Gbs\n"
<< "Total constant memory: " << prop.totalConstMem/1024.0 << " KBytes\n";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // From CUDA for Engineer
// Listing D.5
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
int main()
{
int numDevices = 0;
hipGetDeviceCount(&numDevices);
cout << "Number of devices = " << numDevices << "\n";
for (int i = 0; i < numDevices; i++) {
struct hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
cout << "Device Number: " << i << "\n"
<< "Device name: " << prop.name << "\n"
<< "Compute capability: " << prop.major << "." << prop.minor << "\n"
<< "MultiProcessor count: " << prop.multiProcessorCount << "\n"
<< "Maximum threads/block: " << prop.maxThreadsPerBlock << "\n"
<< "Shared memory/block: " << prop.sharedMemPerBlock/1024.0 << " KBytes\n"
<< "Total global memory: " << prop.totalGlobalMem/1e9 << " Gbs\n"
<< "Total constant memory: " << prop.totalConstMem/1024.0 << " KBytes\n";
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // From CUDA for Engineer
// Listing D.5
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
int main()
{
int numDevices = 0;
hipGetDeviceCount(&numDevices);
cout << "Number of devices = " << numDevices << "\n";
for (int i = 0; i < numDevices; i++) {
struct hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, i);
cout << "Device Number: " << i << "\n"
<< "Device name: " << prop.name << "\n"
<< "Compute capability: " << prop.major << "." << prop.minor << "\n"
<< "MultiProcessor count: " << prop.multiProcessorCount << "\n"
<< "Maximum threads/block: " << prop.maxThreadsPerBlock << "\n"
<< "Shared memory/block: " << prop.sharedMemPerBlock/1024.0 << " KBytes\n"
<< "Total global memory: " << prop.totalGlobalMem/1e9 << " Gbs\n"
<< "Total constant memory: " << prop.totalConstMem/1024.0 << " KBytes\n";
}
return 0;
} | .text
.file "device_property.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI0_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
xorl %ebx, %ebx
leaq 16(%rsp), %r14
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.3, %esi
movl $13, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.1, %esi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.4, %esi
movl $20, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 376(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 380(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.6, %esi
movl $22, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 404(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.7, %esi
movl $23, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.8, %esi
movl $21, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 312(%rsp), %xmm1 # xmm1 = mem[0],zero
movapd .LCPI0_0(%rip), %xmm0 # xmm0 = [1127219200,1160773632,0,0]
unpcklps %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movapd .LCPI0_1(%rip), %xmm0 # xmm0 = [4.503599627370496E+15,1.9342813113834067E+25]
subpd %xmm0, %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.9, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.10, %esi
movl $21, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 304(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI0_3(%rip), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.11, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.12, %esi
movl $23, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 368(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.9, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebx
cmpl 12(%rsp), %ebx
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of devices = "
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device Number: "
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device name: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute capability: "
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "."
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "MultiProcessor count: "
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum threads/block: "
.size .L.str.7, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Shared memory/block: "
.size .L.str.8, 22
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " KBytes\n"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Total global memory: "
.size .L.str.10, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Gbs\n"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total constant memory: "
.size .L.str.12, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009a82c_00000000-6_device_property.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of devices = "
.LC1:
.string "\n"
.LC2:
.string "Device Number: "
.LC3:
.string "Device name: "
.LC4:
.string "Compute capability: "
.LC5:
.string "."
.LC6:
.string "MultiProcessor count: "
.LC7:
.string "Maximum threads/block: "
.LC8:
.string "Shared memory/block: "
.LC10:
.string " KBytes\n"
.LC11:
.string "Total global memory: "
.LC13:
.string " Gbs\n"
.LC14:
.string "Total constant memory: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 12(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC10(%rip), %r12
jmp .L11
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L6
.L7:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L8
.L9:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L10:
mulsd .LC9(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $8, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L11:
leaq 16(%rsp), %r14
movl %ebp, %esi
movq %r14, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $15, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC1(%rip), %r13
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $13, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r14, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $20, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC5(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $22, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 404(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $23, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 336(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $21, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L6:
mulsd .LC9(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $8, %edx
movq %r12, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $21, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rax
testq %rax, %rax
js .L7
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L8:
divsd .LC12(%rip), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $5, %edx
leaq .LC13(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $23, %edx
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 368(%rsp), %rax
testq %rax, %rax
js .L9
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L10
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long 0
.long 1062207488
.align 8
.LC12:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "device_property.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3f50000000000000 # double 9.765625E-4
.LCPI0_3:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 12(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, 12(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
xorl %ebx, %ebx
leaq 16(%rsp), %r14
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.3, %esi
movl $13, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.1, %esi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.4, %esi
movl $20, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 376(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 380(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.6, %esi
movl $22, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 404(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.7, %esi
movl $23, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.8, %esi
movl $21, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 312(%rsp), %xmm1 # xmm1 = mem[0],zero
movapd .LCPI0_0(%rip), %xmm0 # xmm0 = [1127219200,1160773632,0,0]
unpcklps %xmm0, %xmm1 # xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
movapd .LCPI0_1(%rip), %xmm0 # xmm0 = [4.503599627370496E+15,1.9342813113834067E+25]
subpd %xmm0, %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movsd .LCPI0_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.9, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.10, %esi
movl $21, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 304(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI0_3(%rip), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.11, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.12, %esi
movl $23, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 368(%rsp), %xmm1 # xmm1 = mem[0],zero
unpcklps .LCPI0_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI0_2(%rip), %xmm0
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.9, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebx
cmpl 12(%rsp), %ebx
jl .LBB0_2
.LBB0_3: # %._crit_edge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of devices = "
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device Number: "
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device name: "
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute capability: "
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "."
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "MultiProcessor count: "
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Maximum threads/block: "
.size .L.str.7, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Shared memory/block: "
.size .L.str.8, 22
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " KBytes\n"
.size .L.str.9, 9
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Total global memory: "
.size .L.str.10, 22
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Gbs\n"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Total constant memory: "
.size .L.str.12, 24
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda.h>
#include<stdio.h>
#include<math.h>
#include<ctime>
__global__
void vecMulMatrixKernel(float* A, float* B, float* C, int n){
// clock_t start = clock();
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
//printf("%d ",blockDim.x);
if(row<n && column <n){
float val = 0.0;
int i;
for(i=0;i<n;i++){
val += A[row*n+i] * B[i*n+column];
}
C[row*n+column]=val;
}
// clock_t end =clock();
// printf("time:%lld\n",(int)(end-start));
} | code for sm_80
Function : _Z18vecMulMatrixKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda.h>
#include<stdio.h>
#include<math.h>
#include<ctime>
__global__
void vecMulMatrixKernel(float* A, float* B, float* C, int n){
// clock_t start = clock();
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
//printf("%d ",blockDim.x);
if(row<n && column <n){
float val = 0.0;
int i;
for(i=0;i<n;i++){
val += A[row*n+i] * B[i*n+column];
}
C[row*n+column]=val;
}
// clock_t end =clock();
// printf("time:%lld\n",(int)(end-start));
} | .file "tmpxft_0015df54_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i
.type _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i, @function
_Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vecMulMatrixKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i, .-_Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i
.globl _Z18vecMulMatrixKernelPfS_S_i
.type _Z18vecMulMatrixKernelPfS_S_i, @function
_Z18vecMulMatrixKernelPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z18vecMulMatrixKernelPfS_S_i, .-_Z18vecMulMatrixKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18vecMulMatrixKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vecMulMatrixKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda.h>
#include<stdio.h>
#include<math.h>
#include<ctime>
__global__
void vecMulMatrixKernel(float* A, float* B, float* C, int n){
// clock_t start = clock();
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
//printf("%d ",blockDim.x);
if(row<n && column <n){
float val = 0.0;
int i;
for(i=0;i<n;i++){
val += A[row*n+i] * B[i*n+column];
}
C[row*n+column]=val;
}
// clock_t end =clock();
// printf("time:%lld\n",(int)(end-start));
} | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<ctime>
__global__
void vecMulMatrixKernel(float* A, float* B, float* C, int n){
// clock_t start = clock();
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
//printf("%d ",blockDim.x);
if(row<n && column <n){
float val = 0.0;
int i;
for(i=0;i<n;i++){
val += A[row*n+i] * B[i*n+column];
}
C[row*n+column]=val;
}
// clock_t end =clock();
// printf("time:%lld\n",(int)(end-start));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<ctime>
__global__
void vecMulMatrixKernel(float* A, float* B, float* C, int n){
// clock_t start = clock();
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
//printf("%d ",blockDim.x);
if(row<n && column <n){
float val = 0.0;
int i;
for(i=0;i<n;i++){
val += A[row*n+i] * B[i*n+column];
}
C[row*n+column]=val;
}
// clock_t end =clock();
// printf("time:%lld\n",(int)(end-start));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vecMulMatrixKernelPfS_S_i
.globl _Z18vecMulMatrixKernelPfS_S_i
.p2align 8
.type _Z18vecMulMatrixKernelPfS_S_i,@function
_Z18vecMulMatrixKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vecMulMatrixKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vecMulMatrixKernelPfS_S_i, .Lfunc_end0-_Z18vecMulMatrixKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vecMulMatrixKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vecMulMatrixKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<ctime>
__global__
void vecMulMatrixKernel(float* A, float* B, float* C, int n){
// clock_t start = clock();
int column = threadIdx.x + blockDim.x * blockIdx.x;
int row = threadIdx.y + blockDim.y * blockIdx.y;
//printf("%d ",blockDim.x);
if(row<n && column <n){
float val = 0.0;
int i;
for(i=0;i<n;i++){
val += A[row*n+i] * B[i*n+column];
}
C[row*n+column]=val;
}
// clock_t end =clock();
// printf("time:%lld\n",(int)(end-start));
} | .text
.file "test.hip"
.globl _Z33__device_stub__vecMulMatrixKernelPfS_S_i # -- Begin function _Z33__device_stub__vecMulMatrixKernelPfS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__vecMulMatrixKernelPfS_S_i,@function
_Z33__device_stub__vecMulMatrixKernelPfS_S_i: # @_Z33__device_stub__vecMulMatrixKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vecMulMatrixKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__vecMulMatrixKernelPfS_S_i, .Lfunc_end0-_Z33__device_stub__vecMulMatrixKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vecMulMatrixKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vecMulMatrixKernelPfS_S_i,@object # @_Z18vecMulMatrixKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z18vecMulMatrixKernelPfS_S_i
.p2align 3, 0x0
_Z18vecMulMatrixKernelPfS_S_i:
.quad _Z33__device_stub__vecMulMatrixKernelPfS_S_i
.size _Z18vecMulMatrixKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18vecMulMatrixKernelPfS_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vecMulMatrixKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vecMulMatrixKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18vecMulMatrixKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vecMulMatrixKernelPfS_S_i
.globl _Z18vecMulMatrixKernelPfS_S_i
.p2align 8
.type _Z18vecMulMatrixKernelPfS_S_i,@function
_Z18vecMulMatrixKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vecMulMatrixKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vecMulMatrixKernelPfS_S_i, .Lfunc_end0-_Z18vecMulMatrixKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vecMulMatrixKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vecMulMatrixKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015df54_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i
.type _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i, @function
_Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vecMulMatrixKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i, .-_Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i
.globl _Z18vecMulMatrixKernelPfS_S_i
.type _Z18vecMulMatrixKernelPfS_S_i, @function
_Z18vecMulMatrixKernelPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18vecMulMatrixKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z18vecMulMatrixKernelPfS_S_i, .-_Z18vecMulMatrixKernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18vecMulMatrixKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vecMulMatrixKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z33__device_stub__vecMulMatrixKernelPfS_S_i # -- Begin function _Z33__device_stub__vecMulMatrixKernelPfS_S_i
.p2align 4, 0x90
.type _Z33__device_stub__vecMulMatrixKernelPfS_S_i,@function
_Z33__device_stub__vecMulMatrixKernelPfS_S_i: # @_Z33__device_stub__vecMulMatrixKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vecMulMatrixKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__vecMulMatrixKernelPfS_S_i, .Lfunc_end0-_Z33__device_stub__vecMulMatrixKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vecMulMatrixKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vecMulMatrixKernelPfS_S_i,@object # @_Z18vecMulMatrixKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z18vecMulMatrixKernelPfS_S_i
.p2align 3, 0x0
_Z18vecMulMatrixKernelPfS_S_i:
.quad _Z33__device_stub__vecMulMatrixKernelPfS_S_i
.size _Z18vecMulMatrixKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18vecMulMatrixKernelPfS_S_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vecMulMatrixKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vecMulMatrixKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void _mat_sum_row_fast(float *m, float *target,int nrow, int ncol, int agg_col){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float accum[NUM_THREAD_PER_ROW];
if(tx < ncol){
accum[threadIdx.x] = m[blockIdx.y*ncol+tx];
}else{
accum[threadIdx.x] = 0.0f;
}
__syncthreads();
if(NUM_THREAD_PER_ROW >= 512){
if(threadIdx.x < 256)
accum[threadIdx.x] += accum[threadIdx.x+256];
__syncthreads();
}
if(NUM_THREAD_PER_ROW >= 256){
if(threadIdx.x < 128)
accum[threadIdx.x] += accum[threadIdx.x+128];
__syncthreads();
}
//NUM_THREAD_PER_ROW at least 128
if(threadIdx.x < 64)
accum[threadIdx.x] += accum[threadIdx.x+64];
__syncthreads();
if(threadIdx.x < 32){
accum[threadIdx.x] += accum[threadIdx.x+32];
accum[threadIdx.x] += accum[threadIdx.x+16];
accum[threadIdx.x] += accum[threadIdx.x+8];
accum[threadIdx.x] += accum[threadIdx.x+4];
accum[threadIdx.x] += accum[threadIdx.x+2];
accum[threadIdx.x] += accum[threadIdx.x+1];
}
target[blockIdx.y*agg_col+blockIdx.x] = accum[0];
} | code for sm_80
Function : _Z17_mat_sum_row_fastPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R4, c[0x0][0x0], R15 ; /* 0x0000000004007a24 */
/* 0x001fe200078e020f */
/*0060*/ ISETP.GT.U32.AND P0, PT, R15, 0x3f, PT ; /* 0x0000003f0f00780c */
/* 0x000fc80003f04070 */
/*0070*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f26270 */
/*0080*/ @P1 STS [R15.X4], RZ ; /* 0x000000ff0f001388 */
/* 0x0001e20000004800 */
/*0090*/ @P1 BRA 0x100 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*00a0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R3, c[0x0][0x174], R0 ; /* 0x00005d0003027a24 */
/* 0x002fd200078e0200 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R15.X4], R2 ; /* 0x000000020f007388 */
/* 0x0043e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ ISETP.GT.U32.AND P1, PT, R15, 0x1f, PT ; /* 0x0000001f0f00780c */
/* 0x000fca0003f24070 */
/*0130*/ BSSY B0, 0x290 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0140*/ @!P0 LDS R0, [R15.X4] ; /* 0x000000000f008984 */
/* 0x000fe80000004800 */
/*0150*/ @!P0 LDS R3, [R15.X4+0x100] ; /* 0x000100000f038984 */
/* 0x000ea40000004800 */
/*0160*/ @!P0 FADD R0, R0, R3 ; /* 0x0000000300008221 */
/* 0x004fca0000000000 */
/*0170*/ @!P0 STS [R15.X4], R0 ; /* 0x000000000f008388 */
/* 0x0005e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P1 BRA 0x280 ; /* 0x000000e000001947 */
/* 0x000fea0003800000 */
/*01a0*/ LDS R0, [R15.X4] ; /* 0x000000000f007984 */
/* 0x004fe80000004800 */
/*01b0*/ LDS R3, [R15.X4+0x80] ; /* 0x000080000f037984 */
/* 0x000ea80000004800 */
/*01c0*/ LDS R5, [R15.X4+0x40] ; /* 0x000040000f057984 */
/* 0x000ee80000004800 */
/*01d0*/ LDS R7, [R15.X4+0x20] ; /* 0x000020000f077984 */
/* 0x000f280000004800 */
/*01e0*/ LDS R9, [R15.X4+0x10] ; /* 0x000010000f097984 */
/* 0x000f680000004800 */
/*01f0*/ LDS R11, [R15.X4+0x8] ; /* 0x000008000f0b7984 */
/* 0x000e280000004800 */
/*0200*/ LDS R13, [R15.X4+0x4] ; /* 0x000004000f0d7984 */
/* 0x000e620000004800 */
/*0210*/ FADD R0, R0, R3 ; /* 0x0000000300007221 */
/* 0x004fc80000000000 */
/*0220*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x008fc80000000000 */
/*0230*/ FADD R0, R0, R7 ; /* 0x0000000700007221 */
/* 0x010fc80000000000 */
/*0240*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x020fc80000000000 */
/*0250*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x001fc80000000000 */
/*0260*/ FADD R0, R0, R13 ; /* 0x0000000d00007221 */
/* 0x002fca0000000000 */
/*0270*/ STS [R15.X4], R0 ; /* 0x000000000f007388 */
/* 0x0001e40000004800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0290*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000ea20000000800 */
/*02a0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fc60000000f00 */
/*02b0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ee40000002600 */
/*02c0*/ IMAD R2, R3, c[0x0][0x178], R4 ; /* 0x00005e0003027a24 */
/* 0x00afc800078e0204 */
/*02d0*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0007 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void _mat_sum_row_fast(float *m, float *target,int nrow, int ncol, int agg_col){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float accum[NUM_THREAD_PER_ROW];
if(tx < ncol){
accum[threadIdx.x] = m[blockIdx.y*ncol+tx];
}else{
accum[threadIdx.x] = 0.0f;
}
__syncthreads();
if(NUM_THREAD_PER_ROW >= 512){
if(threadIdx.x < 256)
accum[threadIdx.x] += accum[threadIdx.x+256];
__syncthreads();
}
if(NUM_THREAD_PER_ROW >= 256){
if(threadIdx.x < 128)
accum[threadIdx.x] += accum[threadIdx.x+128];
__syncthreads();
}
//NUM_THREAD_PER_ROW at least 128
if(threadIdx.x < 64)
accum[threadIdx.x] += accum[threadIdx.x+64];
__syncthreads();
if(threadIdx.x < 32){
accum[threadIdx.x] += accum[threadIdx.x+32];
accum[threadIdx.x] += accum[threadIdx.x+16];
accum[threadIdx.x] += accum[threadIdx.x+8];
accum[threadIdx.x] += accum[threadIdx.x+4];
accum[threadIdx.x] += accum[threadIdx.x+2];
accum[threadIdx.x] += accum[threadIdx.x+1];
}
target[blockIdx.y*agg_col+blockIdx.x] = accum[0];
} | .file "tmpxft_00078f57_00000000-6__mat_sum_row_fast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii
.type _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii, @function
_Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17_mat_sum_row_fastPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii, .-_Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii
.globl _Z17_mat_sum_row_fastPfS_iii
.type _Z17_mat_sum_row_fastPfS_iii, @function
_Z17_mat_sum_row_fastPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17_mat_sum_row_fastPfS_iii, .-_Z17_mat_sum_row_fastPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17_mat_sum_row_fastPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17_mat_sum_row_fastPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void _mat_sum_row_fast(float *m, float *target,int nrow, int ncol, int agg_col){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float accum[NUM_THREAD_PER_ROW];
if(tx < ncol){
accum[threadIdx.x] = m[blockIdx.y*ncol+tx];
}else{
accum[threadIdx.x] = 0.0f;
}
__syncthreads();
if(NUM_THREAD_PER_ROW >= 512){
if(threadIdx.x < 256)
accum[threadIdx.x] += accum[threadIdx.x+256];
__syncthreads();
}
if(NUM_THREAD_PER_ROW >= 256){
if(threadIdx.x < 128)
accum[threadIdx.x] += accum[threadIdx.x+128];
__syncthreads();
}
//NUM_THREAD_PER_ROW at least 128
if(threadIdx.x < 64)
accum[threadIdx.x] += accum[threadIdx.x+64];
__syncthreads();
if(threadIdx.x < 32){
accum[threadIdx.x] += accum[threadIdx.x+32];
accum[threadIdx.x] += accum[threadIdx.x+16];
accum[threadIdx.x] += accum[threadIdx.x+8];
accum[threadIdx.x] += accum[threadIdx.x+4];
accum[threadIdx.x] += accum[threadIdx.x+2];
accum[threadIdx.x] += accum[threadIdx.x+1];
}
target[blockIdx.y*agg_col+blockIdx.x] = accum[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _mat_sum_row_fast(float *m, float *target,int nrow, int ncol, int agg_col){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float accum[NUM_THREAD_PER_ROW];
if(tx < ncol){
accum[threadIdx.x] = m[blockIdx.y*ncol+tx];
}else{
accum[threadIdx.x] = 0.0f;
}
__syncthreads();
if(NUM_THREAD_PER_ROW >= 512){
if(threadIdx.x < 256)
accum[threadIdx.x] += accum[threadIdx.x+256];
__syncthreads();
}
if(NUM_THREAD_PER_ROW >= 256){
if(threadIdx.x < 128)
accum[threadIdx.x] += accum[threadIdx.x+128];
__syncthreads();
}
//NUM_THREAD_PER_ROW at least 128
if(threadIdx.x < 64)
accum[threadIdx.x] += accum[threadIdx.x+64];
__syncthreads();
if(threadIdx.x < 32){
accum[threadIdx.x] += accum[threadIdx.x+32];
accum[threadIdx.x] += accum[threadIdx.x+16];
accum[threadIdx.x] += accum[threadIdx.x+8];
accum[threadIdx.x] += accum[threadIdx.x+4];
accum[threadIdx.x] += accum[threadIdx.x+2];
accum[threadIdx.x] += accum[threadIdx.x+1];
}
target[blockIdx.y*agg_col+blockIdx.x] = accum[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _mat_sum_row_fast(float *m, float *target,int nrow, int ncol, int agg_col){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float accum[NUM_THREAD_PER_ROW];
if(tx < ncol){
accum[threadIdx.x] = m[blockIdx.y*ncol+tx];
}else{
accum[threadIdx.x] = 0.0f;
}
__syncthreads();
if(NUM_THREAD_PER_ROW >= 512){
if(threadIdx.x < 256)
accum[threadIdx.x] += accum[threadIdx.x+256];
__syncthreads();
}
if(NUM_THREAD_PER_ROW >= 256){
if(threadIdx.x < 128)
accum[threadIdx.x] += accum[threadIdx.x+128];
__syncthreads();
}
//NUM_THREAD_PER_ROW at least 128
if(threadIdx.x < 64)
accum[threadIdx.x] += accum[threadIdx.x+64];
__syncthreads();
if(threadIdx.x < 32){
accum[threadIdx.x] += accum[threadIdx.x+32];
accum[threadIdx.x] += accum[threadIdx.x+16];
accum[threadIdx.x] += accum[threadIdx.x+8];
accum[threadIdx.x] += accum[threadIdx.x+4];
accum[threadIdx.x] += accum[threadIdx.x+2];
accum[threadIdx.x] += accum[threadIdx.x+1];
}
target[blockIdx.y*agg_col+blockIdx.x] = accum[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17_mat_sum_row_fastPfS_iii
.globl _Z17_mat_sum_row_fastPfS_iii
.p2align 8
.type _Z17_mat_sum_row_fastPfS_iii,@function
_Z17_mat_sum_row_fastPfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_4
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v6, 2, v0
ds_load_b32 v7, v6 offset:128
ds_load_2addr_b32 v[0:1], v6 offset1:1
ds_load_2addr_b32 v[2:3], v6 offset0:8 offset1:16
ds_load_2addr_b32 v[4:5], v6 offset0:2 offset1:4
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v0, v7, v0
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v3
v_add_f32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v5
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v1
ds_store_b32 v6, v0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s2, s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17_mat_sum_row_fastPfS_iii
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17_mat_sum_row_fastPfS_iii, .Lfunc_end0-_Z17_mat_sum_row_fastPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17_mat_sum_row_fastPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17_mat_sum_row_fastPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _mat_sum_row_fast(float *m, float *target,int nrow, int ncol, int agg_col){
int tx = blockIdx.x * blockDim.x + threadIdx.x;
__shared__ float accum[NUM_THREAD_PER_ROW];
if(tx < ncol){
accum[threadIdx.x] = m[blockIdx.y*ncol+tx];
}else{
accum[threadIdx.x] = 0.0f;
}
__syncthreads();
if(NUM_THREAD_PER_ROW >= 512){
if(threadIdx.x < 256)
accum[threadIdx.x] += accum[threadIdx.x+256];
__syncthreads();
}
if(NUM_THREAD_PER_ROW >= 256){
if(threadIdx.x < 128)
accum[threadIdx.x] += accum[threadIdx.x+128];
__syncthreads();
}
//NUM_THREAD_PER_ROW at least 128
if(threadIdx.x < 64)
accum[threadIdx.x] += accum[threadIdx.x+64];
__syncthreads();
if(threadIdx.x < 32){
accum[threadIdx.x] += accum[threadIdx.x+32];
accum[threadIdx.x] += accum[threadIdx.x+16];
accum[threadIdx.x] += accum[threadIdx.x+8];
accum[threadIdx.x] += accum[threadIdx.x+4];
accum[threadIdx.x] += accum[threadIdx.x+2];
accum[threadIdx.x] += accum[threadIdx.x+1];
}
target[blockIdx.y*agg_col+blockIdx.x] = accum[0];
} | .text
.file "_mat_sum_row_fast.hip"
.globl _Z32__device_stub___mat_sum_row_fastPfS_iii # -- Begin function _Z32__device_stub___mat_sum_row_fastPfS_iii
.p2align 4, 0x90
.type _Z32__device_stub___mat_sum_row_fastPfS_iii,@function
_Z32__device_stub___mat_sum_row_fastPfS_iii: # @_Z32__device_stub___mat_sum_row_fastPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17_mat_sum_row_fastPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub___mat_sum_row_fastPfS_iii, .Lfunc_end0-_Z32__device_stub___mat_sum_row_fastPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17_mat_sum_row_fastPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17_mat_sum_row_fastPfS_iii,@object # @_Z17_mat_sum_row_fastPfS_iii
.section .rodata,"a",@progbits
.globl _Z17_mat_sum_row_fastPfS_iii
.p2align 3, 0x0
_Z17_mat_sum_row_fastPfS_iii:
.quad _Z32__device_stub___mat_sum_row_fastPfS_iii
.size _Z17_mat_sum_row_fastPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17_mat_sum_row_fastPfS_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub___mat_sum_row_fastPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17_mat_sum_row_fastPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17_mat_sum_row_fastPfS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R4, c[0x0][0x0], R15 ; /* 0x0000000004007a24 */
/* 0x001fe200078e020f */
/*0060*/ ISETP.GT.U32.AND P0, PT, R15, 0x3f, PT ; /* 0x0000003f0f00780c */
/* 0x000fc80003f04070 */
/*0070*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f26270 */
/*0080*/ @P1 STS [R15.X4], RZ ; /* 0x000000ff0f001388 */
/* 0x0001e20000004800 */
/*0090*/ @P1 BRA 0x100 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*00a0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*00b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R3, c[0x0][0x174], R0 ; /* 0x00005d0003027a24 */
/* 0x002fd200078e0200 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0005 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STS [R15.X4], R2 ; /* 0x000000020f007388 */
/* 0x0043e40000004800 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ ISETP.GT.U32.AND P1, PT, R15, 0x1f, PT ; /* 0x0000001f0f00780c */
/* 0x000fca0003f24070 */
/*0130*/ BSSY B0, 0x290 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0140*/ @!P0 LDS R0, [R15.X4] ; /* 0x000000000f008984 */
/* 0x000fe80000004800 */
/*0150*/ @!P0 LDS R3, [R15.X4+0x100] ; /* 0x000100000f038984 */
/* 0x000ea40000004800 */
/*0160*/ @!P0 FADD R0, R0, R3 ; /* 0x0000000300008221 */
/* 0x004fca0000000000 */
/*0170*/ @!P0 STS [R15.X4], R0 ; /* 0x000000000f008388 */
/* 0x0005e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P1 BRA 0x280 ; /* 0x000000e000001947 */
/* 0x000fea0003800000 */
/*01a0*/ LDS R0, [R15.X4] ; /* 0x000000000f007984 */
/* 0x004fe80000004800 */
/*01b0*/ LDS R3, [R15.X4+0x80] ; /* 0x000080000f037984 */
/* 0x000ea80000004800 */
/*01c0*/ LDS R5, [R15.X4+0x40] ; /* 0x000040000f057984 */
/* 0x000ee80000004800 */
/*01d0*/ LDS R7, [R15.X4+0x20] ; /* 0x000020000f077984 */
/* 0x000f280000004800 */
/*01e0*/ LDS R9, [R15.X4+0x10] ; /* 0x000010000f097984 */
/* 0x000f680000004800 */
/*01f0*/ LDS R11, [R15.X4+0x8] ; /* 0x000008000f0b7984 */
/* 0x000e280000004800 */
/*0200*/ LDS R13, [R15.X4+0x4] ; /* 0x000004000f0d7984 */
/* 0x000e620000004800 */
/*0210*/ FADD R0, R0, R3 ; /* 0x0000000300007221 */
/* 0x004fc80000000000 */
/*0220*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x008fc80000000000 */
/*0230*/ FADD R0, R0, R7 ; /* 0x0000000700007221 */
/* 0x010fc80000000000 */
/*0240*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x020fc80000000000 */
/*0250*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x001fc80000000000 */
/*0260*/ FADD R0, R0, R13 ; /* 0x0000000d00007221 */
/* 0x002fca0000000000 */
/*0270*/ STS [R15.X4], R0 ; /* 0x000000000f007388 */
/* 0x0001e40000004800 */
/*0280*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x004fea0003800000 */
/*0290*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000ea20000000800 */
/*02a0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fc60000000f00 */
/*02b0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000ee40000002600 */
/*02c0*/ IMAD R2, R3, c[0x0][0x178], R4 ; /* 0x00005e0003027a24 */
/* 0x00afc800078e0204 */
/*02d0*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0007 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17_mat_sum_row_fastPfS_iii
.globl _Z17_mat_sum_row_fastPfS_iii
.p2align 8
.type _Z17_mat_sum_row_fastPfS_iii,@function
_Z17_mat_sum_row_fastPfS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 64, v0
s_cbranch_execz .LBB0_4
ds_load_2addr_stride64_b32 v[2:3], v1 offset1:1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 32, v0
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v6, 2, v0
ds_load_b32 v7, v6 offset:128
ds_load_2addr_b32 v[0:1], v6 offset1:1
ds_load_2addr_b32 v[2:3], v6 offset0:8 offset1:16
ds_load_2addr_b32 v[4:5], v6 offset0:2 offset1:4
s_waitcnt lgkmcnt(2)
v_add_f32_e32 v0, v7, v0
s_waitcnt lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v3
v_add_f32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v5
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v1
ds_store_b32 v6, v0
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s2, s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17_mat_sum_row_fastPfS_iii
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17_mat_sum_row_fastPfS_iii, .Lfunc_end0-_Z17_mat_sum_row_fastPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17_mat_sum_row_fastPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17_mat_sum_row_fastPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00078f57_00000000-6__mat_sum_row_fast.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii
.type _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii, @function
_Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17_mat_sum_row_fastPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii, .-_Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii
.globl _Z17_mat_sum_row_fastPfS_iii
.type _Z17_mat_sum_row_fastPfS_iii, @function
_Z17_mat_sum_row_fastPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17_mat_sum_row_fastPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17_mat_sum_row_fastPfS_iii, .-_Z17_mat_sum_row_fastPfS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17_mat_sum_row_fastPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17_mat_sum_row_fastPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "_mat_sum_row_fast.hip"
.globl _Z32__device_stub___mat_sum_row_fastPfS_iii # -- Begin function _Z32__device_stub___mat_sum_row_fastPfS_iii
.p2align 4, 0x90
.type _Z32__device_stub___mat_sum_row_fastPfS_iii,@function
_Z32__device_stub___mat_sum_row_fastPfS_iii: # @_Z32__device_stub___mat_sum_row_fastPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17_mat_sum_row_fastPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub___mat_sum_row_fastPfS_iii, .Lfunc_end0-_Z32__device_stub___mat_sum_row_fastPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17_mat_sum_row_fastPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17_mat_sum_row_fastPfS_iii,@object # @_Z17_mat_sum_row_fastPfS_iii
.section .rodata,"a",@progbits
.globl _Z17_mat_sum_row_fastPfS_iii
.p2align 3, 0x0
_Z17_mat_sum_row_fastPfS_iii:
.quad _Z32__device_stub___mat_sum_row_fastPfS_iii
.size _Z17_mat_sum_row_fastPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17_mat_sum_row_fastPfS_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub___mat_sum_row_fastPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17_mat_sum_row_fastPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <chrono>
#include <iostream>
#include <string>
//Testing Structs, easiest way to define datatypes of size
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
}testingStruct_1;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
}testingStruct_2;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
}testingStruct_4;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
}testingStruct_8;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
char p9;
char p10;
char p11;
char p12;
char p13;
char p14;
char p15;
char p16;
}testingStruct_16;
//Kernel definition
template<typename T>
__global__
void copyKernel(T* out, T* in, int stride) {
unsigned id = threadIdx.x + blockIdx.x * blockDim.x;
// if (id*stride < sizeof(out)) {
out[id*stride] = in[id*stride];
// }
}
int main () {
using namespace std::chrono;
//output strings so that they may be pasted directly into python
//std::string keyString;
//std::string valueString;
std::cout<<"np.array((";
for (int i = 0; i <= 6; i++) {//we are looping the numbers of blocks now
int stride = 1 << i;
int* out;
int* in;
int accessSize = sizeof (int);
// TODO check total memory consumtpion and cout total size in GB
cudaMalloc(&out , 16384 * 1024 * accessSize * stride );
auto err = cudaMalloc(&in , 16384 * 1024 * accessSize *stride ) ;
if (err != cudaSuccess) {
std::cout << "ERROR: could not alloc!" << std::endl;
}
copyKernel<<<16384, 1024>>>(out, in, stride);
cudaDeviceSynchronize();
//Time Measururement Point 1
high_resolution_clock::time_point timeBefore = high_resolution_clock::now();
for (int j = 1; j <= 10; j++){
copyKernel<<<16384, 1024>>>(out, in, stride);
cudaDeviceSynchronize();
}
//Time Measurement Point 2
high_resolution_clock::time_point timeAfter = high_resolution_clock::now();
//Output Time Measurement Result
duration<double> time_span = duration_cast<duration<double>>(timeAfter - timeBefore);
//std::cout << "Time for 10x stride = " << stride << " is " << time_span.count() << " seconds";
//std::cout << std:: endl;
std::cout << time_span.count();
cudaFree(out);
cudaFree(in);
if(i != 6)
{
std::cout<<",";
}
}
std::cout << "))" << std::endl;
return 0;
} | code for sm_80
Function : _Z10copyKernelIiEvPT_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fc800078e02ff */
/*0070*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0005 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <chrono>
#include <iostream>
#include <string>
//Testing Structs, easiest way to define datatypes of size
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
}testingStruct_1;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
}testingStruct_2;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
}testingStruct_4;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
}testingStruct_8;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
char p9;
char p10;
char p11;
char p12;
char p13;
char p14;
char p15;
char p16;
}testingStruct_16;
//Kernel definition
template<typename T>
__global__
void copyKernel(T* out, T* in, int stride) {
unsigned id = threadIdx.x + blockIdx.x * blockDim.x;
// if (id*stride < sizeof(out)) {
out[id*stride] = in[id*stride];
// }
}
int main () {
using namespace std::chrono;
//output strings so that they may be pasted directly into python
//std::string keyString;
//std::string valueString;
std::cout<<"np.array((";
for (int i = 0; i <= 6; i++) {//we are looping the numbers of blocks now
int stride = 1 << i;
int* out;
int* in;
int accessSize = sizeof (int);
// TODO check total memory consumtpion and cout total size in GB
cudaMalloc(&out , 16384 * 1024 * accessSize * stride );
auto err = cudaMalloc(&in , 16384 * 1024 * accessSize *stride ) ;
if (err != cudaSuccess) {
std::cout << "ERROR: could not alloc!" << std::endl;
}
copyKernel<<<16384, 1024>>>(out, in, stride);
cudaDeviceSynchronize();
//Time Measururement Point 1
high_resolution_clock::time_point timeBefore = high_resolution_clock::now();
for (int j = 1; j <= 10; j++){
copyKernel<<<16384, 1024>>>(out, in, stride);
cudaDeviceSynchronize();
}
//Time Measurement Point 2
high_resolution_clock::time_point timeAfter = high_resolution_clock::now();
//Output Time Measurement Result
duration<double> time_span = duration_cast<duration<double>>(timeAfter - timeBefore);
//std::cout << "Time for 10x stride = " << stride << " is " << time_span.count() << " seconds";
//std::cout << std:: endl;
std::cout << time_span.count();
cudaFree(out);
cudaFree(in);
if(i != 6)
{
std::cout<<",";
}
}
std::cout << "))" << std::endl;
return 0;
} | .file "tmpxft_000ebbc3_00000000-6_stridedaccess_rev2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i, @function
_ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i:
.LFB3798:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10copyKernelIiEvPT_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3798:
.size _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i, .-_ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
.section .text._Z10copyKernelIiEvPT_S1_i,"axG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.weak _Z10copyKernelIiEvPT_S1_i
.type _Z10copyKernelIiEvPT_S1_i, @function
_Z10copyKernelIiEvPT_S1_i:
.LFB4132:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4132:
.size _Z10copyKernelIiEvPT_S1_i, .-_Z10copyKernelIiEvPT_S1_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3776:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3776:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "np.array(("
.LC1:
.string "ERROR: could not alloc!"
.LC3:
.string ","
.LC4:
.string "))"
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC3(%rip), %r15
jmp .L21
.L28:
movl $23, %edx
leaq .LC1(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %esi
.L16:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L12
.L25:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
call _ZSt16__throw_bad_castv@PLT
.L26:
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L29:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
jmp .L17
.L18:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L27
.L19:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
jmp .L18
.L27:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
cmpl $6, %r12d
je .L20
movl $1, %edx
movq %r15, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %r12d
.L21:
movl $1, %ebp
movl %r12d, %ecx
sall %cl, %ebp
movl $67108864, %ebx
sall %cl, %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
.L12:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl $10, %ebx
jmp .L19
.L20:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10copyKernelIiEvPT_S1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10copyKernelIiEvPT_S1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <chrono>
#include <iostream>
#include <string>
//Testing Structs, easiest way to define datatypes of size
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
}testingStruct_1;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
}testingStruct_2;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
}testingStruct_4;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
}testingStruct_8;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
char p9;
char p10;
char p11;
char p12;
char p13;
char p14;
char p15;
char p16;
}testingStruct_16;
//Kernel definition
template<typename T>
__global__
void copyKernel(T* out, T* in, int stride) {
unsigned id = threadIdx.x + blockIdx.x * blockDim.x;
// if (id*stride < sizeof(out)) {
out[id*stride] = in[id*stride];
// }
}
int main () {
using namespace std::chrono;
//output strings so that they may be pasted directly into python
//std::string keyString;
//std::string valueString;
std::cout<<"np.array((";
for (int i = 0; i <= 6; i++) {//we are looping the numbers of blocks now
int stride = 1 << i;
int* out;
int* in;
int accessSize = sizeof (int);
// TODO check total memory consumtpion and cout total size in GB
cudaMalloc(&out , 16384 * 1024 * accessSize * stride );
auto err = cudaMalloc(&in , 16384 * 1024 * accessSize *stride ) ;
if (err != cudaSuccess) {
std::cout << "ERROR: could not alloc!" << std::endl;
}
copyKernel<<<16384, 1024>>>(out, in, stride);
cudaDeviceSynchronize();
//Time Measururement Point 1
high_resolution_clock::time_point timeBefore = high_resolution_clock::now();
for (int j = 1; j <= 10; j++){
copyKernel<<<16384, 1024>>>(out, in, stride);
cudaDeviceSynchronize();
}
//Time Measurement Point 2
high_resolution_clock::time_point timeAfter = high_resolution_clock::now();
//Output Time Measurement Result
duration<double> time_span = duration_cast<duration<double>>(timeAfter - timeBefore);
//std::cout << "Time for 10x stride = " << stride << " is " << time_span.count() << " seconds";
//std::cout << std:: endl;
std::cout << time_span.count();
cudaFree(out);
cudaFree(in);
if(i != 6)
{
std::cout<<",";
}
}
std::cout << "))" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <chrono>
#include <iostream>
#include <string>
//Testing Structs, easiest way to define datatypes of size
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
}testingStruct_1;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
}testingStruct_2;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
}testingStruct_4;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
}testingStruct_8;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
char p9;
char p10;
char p11;
char p12;
char p13;
char p14;
char p15;
char p16;
}testingStruct_16;
//Kernel definition
template<typename T>
__global__
void copyKernel(T* out, T* in, int stride) {
unsigned id = threadIdx.x + blockIdx.x * blockDim.x;
// if (id*stride < sizeof(out)) {
out[id*stride] = in[id*stride];
// }
}
int main () {
using namespace std::chrono;
//output strings so that they may be pasted directly into python
//std::string keyString;
//std::string valueString;
std::cout<<"np.array((";
for (int i = 0; i <= 6; i++) {//we are looping the numbers of blocks now
int stride = 1 << i;
int* out;
int* in;
int accessSize = sizeof (int);
// TODO check total memory consumtpion and cout total size in GB
hipMalloc(&out , 16384 * 1024 * accessSize * stride );
auto err = hipMalloc(&in , 16384 * 1024 * accessSize *stride ) ;
if (err != hipSuccess) {
std::cout << "ERROR: could not alloc!" << std::endl;
}
copyKernel<<<16384, 1024>>>(out, in, stride);
hipDeviceSynchronize();
//Time Measururement Point 1
high_resolution_clock::time_point timeBefore = high_resolution_clock::now();
for (int j = 1; j <= 10; j++){
copyKernel<<<16384, 1024>>>(out, in, stride);
hipDeviceSynchronize();
}
//Time Measurement Point 2
high_resolution_clock::time_point timeAfter = high_resolution_clock::now();
//Output Time Measurement Result
duration<double> time_span = duration_cast<duration<double>>(timeAfter - timeBefore);
//std::cout << "Time for 10x stride = " << stride << " is " << time_span.count() << " seconds";
//std::cout << std:: endl;
std::cout << time_span.count();
hipFree(out);
hipFree(in);
if(i != 6)
{
std::cout<<",";
}
}
std::cout << "))" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <chrono>
#include <iostream>
#include <string>
//Testing Structs, easiest way to define datatypes of size
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
}testingStruct_1;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
}testingStruct_2;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
}testingStruct_4;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
}testingStruct_8;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
char p9;
char p10;
char p11;
char p12;
char p13;
char p14;
char p15;
char p16;
}testingStruct_16;
//Kernel definition
template<typename T>
__global__
void copyKernel(T* out, T* in, int stride) {
unsigned id = threadIdx.x + blockIdx.x * blockDim.x;
// if (id*stride < sizeof(out)) {
out[id*stride] = in[id*stride];
// }
}
int main () {
using namespace std::chrono;
//output strings so that they may be pasted directly into python
//std::string keyString;
//std::string valueString;
std::cout<<"np.array((";
for (int i = 0; i <= 6; i++) {//we are looping the numbers of blocks now
int stride = 1 << i;
int* out;
int* in;
int accessSize = sizeof (int);
// TODO check total memory consumtpion and cout total size in GB
hipMalloc(&out , 16384 * 1024 * accessSize * stride );
auto err = hipMalloc(&in , 16384 * 1024 * accessSize *stride ) ;
if (err != hipSuccess) {
std::cout << "ERROR: could not alloc!" << std::endl;
}
copyKernel<<<16384, 1024>>>(out, in, stride);
hipDeviceSynchronize();
//Time Measururement Point 1
high_resolution_clock::time_point timeBefore = high_resolution_clock::now();
for (int j = 1; j <= 10; j++){
copyKernel<<<16384, 1024>>>(out, in, stride);
hipDeviceSynchronize();
}
//Time Measurement Point 2
high_resolution_clock::time_point timeAfter = high_resolution_clock::now();
//Output Time Measurement Result
duration<double> time_span = duration_cast<duration<double>>(timeAfter - timeBefore);
//std::cout << "Time for 10x stride = " << stride << " is " << time_span.count() << " seconds";
//std::cout << std:: endl;
std::cout << time_span.count();
hipFree(out);
hipFree(in);
if(i != 6)
{
std::cout<<",";
}
}
std::cout << "))" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10copyKernelIiEvPT_S1_i,"axG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.protected _Z10copyKernelIiEvPT_S1_i
.globl _Z10copyKernelIiEvPT_S1_i
.p2align 8
.type _Z10copyKernelIiEvPT_S1_i,@function
_Z10copyKernelIiEvPT_S1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s4
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10copyKernelIiEvPT_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10copyKernelIiEvPT_S1_i,"axG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.Lfunc_end0:
.size _Z10copyKernelIiEvPT_S1_i, .Lfunc_end0-_Z10copyKernelIiEvPT_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10copyKernelIiEvPT_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10copyKernelIiEvPT_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <chrono>
#include <iostream>
#include <string>
//Testing Structs, easiest way to define datatypes of size
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
}testingStruct_1;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
}testingStruct_2;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
}testingStruct_4;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
}testingStruct_8;
typedef struct
{//just define an amount of chars in the struct that is equal to the desired size
char p1;
char p2;
char p3;
char p4;
char p5;
char p6;
char p7;
char p8;
char p9;
char p10;
char p11;
char p12;
char p13;
char p14;
char p15;
char p16;
}testingStruct_16;
//Kernel definition
template<typename T>
__global__
void copyKernel(T* out, T* in, int stride) {
unsigned id = threadIdx.x + blockIdx.x * blockDim.x;
// if (id*stride < sizeof(out)) {
out[id*stride] = in[id*stride];
// }
}
int main () {
using namespace std::chrono;
//output strings so that they may be pasted directly into python
//std::string keyString;
//std::string valueString;
std::cout<<"np.array((";
for (int i = 0; i <= 6; i++) {//we are looping the numbers of blocks now
int stride = 1 << i;
int* out;
int* in;
int accessSize = sizeof (int);
// TODO check total memory consumtpion and cout total size in GB
hipMalloc(&out , 16384 * 1024 * accessSize * stride );
auto err = hipMalloc(&in , 16384 * 1024 * accessSize *stride ) ;
if (err != hipSuccess) {
std::cout << "ERROR: could not alloc!" << std::endl;
}
copyKernel<<<16384, 1024>>>(out, in, stride);
hipDeviceSynchronize();
//Time Measururement Point 1
high_resolution_clock::time_point timeBefore = high_resolution_clock::now();
for (int j = 1; j <= 10; j++){
copyKernel<<<16384, 1024>>>(out, in, stride);
hipDeviceSynchronize();
}
//Time Measurement Point 2
high_resolution_clock::time_point timeAfter = high_resolution_clock::now();
//Output Time Measurement Result
duration<double> time_span = duration_cast<duration<double>>(timeAfter - timeBefore);
//std::cout << "Time for 10x stride = " << stride << " is " << time_span.count() << " seconds";
//std::cout << std:: endl;
std::cout << time_span.count();
hipFree(out);
hipFree(in);
if(i != 6)
{
std::cout<<",";
}
}
std::cout << "))" << std::endl;
return 0;
} | .text
.file "stridedaccess_rev2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r14d, %r14d
leaq 15360(%rbx), %r13
leaq 96(%rsp), %r15
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_1 Depth=1
incl %r14d
cmpl $7, %r14d
je .LBB0_5
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_15 Depth 2
movl $1, %ebp
movl %r14d, %ecx
shll %cl, %ebp
movl $67108864, %eax # imm = 0x4000000
shll %cl, %eax
movslq %eax, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB0_12
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB0_21
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB0_1 Depth=1
cmpb $0, 56(%r12)
je .LBB0_10
# %bb.4: # in Loop: Header=BB0_1 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_1 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB0_1 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_12: # in Loop: Header=BB0_1 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_14
# %bb.13: # in Loop: Header=BB0_1 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10copyKernelIiEvPT_S1_i, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_14: # in Loop: Header=BB0_1 Depth=1
callq hipDeviceSynchronize
movl $10, %r12d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 128(%rsp) # 8-byte Spill
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_15 Depth=2
callq hipDeviceSynchronize
decl %r12d
je .LBB0_18
.LBB0_15: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16: # in Loop: Header=BB0_15 Depth=2
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10copyKernelIiEvPT_S1_i, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_1 Depth=1
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 128(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
cmpl $6, %r14d
je .LBB0_20
# %bb.19: # in Loop: Header=BB0_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_20
.LBB0_5:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB0_9
.LBB0_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_21:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__copyKernelIiEvPT_S1_i,"axG",@progbits,_Z25__device_stub__copyKernelIiEvPT_S1_i,comdat
.weak _Z25__device_stub__copyKernelIiEvPT_S1_i # -- Begin function _Z25__device_stub__copyKernelIiEvPT_S1_i
.p2align 4, 0x90
.type _Z25__device_stub__copyKernelIiEvPT_S1_i,@function
_Z25__device_stub__copyKernelIiEvPT_S1_i: # @_Z25__device_stub__copyKernelIiEvPT_S1_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10copyKernelIiEvPT_S1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__copyKernelIiEvPT_S1_i, .Lfunc_end1-_Z25__device_stub__copyKernelIiEvPT_S1_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10copyKernelIiEvPT_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "np.array(("
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: could not alloc!"
.size .L.str.1, 24
.type _Z10copyKernelIiEvPT_S1_i,@object # @_Z10copyKernelIiEvPT_S1_i
.section .rodata._Z10copyKernelIiEvPT_S1_i,"aG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.weak _Z10copyKernelIiEvPT_S1_i
.p2align 3, 0x0
_Z10copyKernelIiEvPT_S1_i:
.quad _Z25__device_stub__copyKernelIiEvPT_S1_i
.size _Z10copyKernelIiEvPT_S1_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz ","
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "))"
.size .L.str.3, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10copyKernelIiEvPT_S1_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__copyKernelIiEvPT_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10copyKernelIiEvPT_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10copyKernelIiEvPT_S1_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fc800078e02ff */
/*0070*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0005 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fca00078e0005 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z10copyKernelIiEvPT_S1_i,"axG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.protected _Z10copyKernelIiEvPT_S1_i
.globl _Z10copyKernelIiEvPT_S1_i
.p2align 8
.type _Z10copyKernelIiEvPT_S1_i,@function
_Z10copyKernelIiEvPT_S1_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v0, v1, s4
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10copyKernelIiEvPT_S1_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z10copyKernelIiEvPT_S1_i,"axG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.Lfunc_end0:
.size _Z10copyKernelIiEvPT_S1_i, .Lfunc_end0-_Z10copyKernelIiEvPT_S1_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10copyKernelIiEvPT_S1_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10copyKernelIiEvPT_S1_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ebbc3_00000000-6_stridedaccess_rev2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i, @function
_ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i:
.LFB3798:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10copyKernelIiEvPT_S1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3798:
.size _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i, .-_ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
.section .text._Z10copyKernelIiEvPT_S1_i,"axG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.weak _Z10copyKernelIiEvPT_S1_i
.type _Z10copyKernelIiEvPT_S1_i, @function
_Z10copyKernelIiEvPT_S1_i:
.LFB4132:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4132:
.size _Z10copyKernelIiEvPT_S1_i, .-_Z10copyKernelIiEvPT_S1_i
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3776:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3776:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "np.array(("
.LC1:
.string "ERROR: could not alloc!"
.LC3:
.string ","
.LC4:
.string "))"
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC3(%rip), %r15
jmp .L21
.L28:
movl $23, %edx
leaq .LC1(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %esi
.L16:
movsbl %sil, %esi
movq %r14, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L12
.L25:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
call _ZSt16__throw_bad_castv@PLT
.L26:
call __stack_chk_fail@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L29:
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
jmp .L17
.L18:
call cudaDeviceSynchronize@PLT
subl $1, %ebx
je .L27
.L19:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _ZL39__device_stub__Z10copyKernelIiEvPT_S1_iPiS_i
jmp .L18
.L27:
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
cmpl $6, %r12d
je .L20
movl $1, %edx
movq %r15, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %r12d
.L21:
movl $1, %ebp
movl %r12d, %ecx
sall %cl, %ebp
movl $67108864, %ebx
sall %cl, %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L28
.L12:
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16384, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L17:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
movl $10, %ebx
jmp .L19
.L20:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10copyKernelIiEvPT_S1_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10copyKernelIiEvPT_S1_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stridedaccess_rev2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294968320, %rbx # imm = 0x100000400
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r14d, %r14d
leaq 15360(%rbx), %r13
leaq 96(%rsp), %r15
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_20: # in Loop: Header=BB0_1 Depth=1
incl %r14d
cmpl $7, %r14d
je .LBB0_5
.LBB0_1: # =>This Loop Header: Depth=1
# Child Loop BB0_15 Depth 2
movl $1, %ebp
movl %r14d, %ecx
shll %cl, %ebp
movl $67108864, %eax # imm = 0x4000000
shll %cl, %eax
movslq %eax, %r12
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB0_12
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB0_21
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB0_1 Depth=1
cmpb $0, 56(%r12)
je .LBB0_10
# %bb.4: # in Loop: Header=BB0_1 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_1 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB0_1 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB0_12: # in Loop: Header=BB0_1 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_14
# %bb.13: # in Loop: Header=BB0_1 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10copyKernelIiEvPT_S1_i, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_14: # in Loop: Header=BB0_1 Depth=1
callq hipDeviceSynchronize
movl $10, %r12d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, 128(%rsp) # 8-byte Spill
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_17: # in Loop: Header=BB0_15 Depth=2
callq hipDeviceSynchronize
decl %r12d
je .LBB0_18
.LBB0_15: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r13, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16: # in Loop: Header=BB0_15 Depth=2
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z10copyKernelIiEvPT_S1_i, %edi
movq %r15, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_18: # in Loop: Header=BB0_1 Depth=1
callq _ZNSt6chrono3_V212system_clock3nowEv
subq 128(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
cmpl $6, %r14d
je .LBB0_20
# %bb.19: # in Loop: Header=BB0_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_20
.LBB0_5:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_8
# %bb.7:
movzbl 67(%rbx), %eax
jmp .LBB0_9
.LBB0_8:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_21:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z25__device_stub__copyKernelIiEvPT_S1_i,"axG",@progbits,_Z25__device_stub__copyKernelIiEvPT_S1_i,comdat
.weak _Z25__device_stub__copyKernelIiEvPT_S1_i # -- Begin function _Z25__device_stub__copyKernelIiEvPT_S1_i
.p2align 4, 0x90
.type _Z25__device_stub__copyKernelIiEvPT_S1_i,@function
_Z25__device_stub__copyKernelIiEvPT_S1_i: # @_Z25__device_stub__copyKernelIiEvPT_S1_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10copyKernelIiEvPT_S1_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__copyKernelIiEvPT_S1_i, .Lfunc_end1-_Z25__device_stub__copyKernelIiEvPT_S1_i
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10copyKernelIiEvPT_S1_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "np.array(("
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ERROR: could not alloc!"
.size .L.str.1, 24
.type _Z10copyKernelIiEvPT_S1_i,@object # @_Z10copyKernelIiEvPT_S1_i
.section .rodata._Z10copyKernelIiEvPT_S1_i,"aG",@progbits,_Z10copyKernelIiEvPT_S1_i,comdat
.weak _Z10copyKernelIiEvPT_S1_i
.p2align 3, 0x0
_Z10copyKernelIiEvPT_S1_i:
.quad _Z25__device_stub__copyKernelIiEvPT_S1_i
.size _Z10copyKernelIiEvPT_S1_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz ","
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "))"
.size .L.str.3, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10copyKernelIiEvPT_S1_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__copyKernelIiEvPT_S1_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z10copyKernelIiEvPT_S1_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#define dT 0.2f
#define G 0.6f
#define BLOCK_SIZE 32
// Global variables
int num_planets;
int num_timesteps;
// Host arrays
float2* velocities;
float4* planets;
// Device arrays
float2* velocities_d;
float4* planets_d;
// Parse command line arguments
void parse_args(int argc, char** argv){
if(argc != 2){
printf("Useage: nbody num_timesteps\n");
exit(-1);
}
num_timesteps = strtol(argv[1], 0, 10);
}
double walltime ( void ) {
static struct timeval t;
gettimeofday ( &t, NULL );
return ( t.tv_sec + 1e-6 * t.tv_usec );
}
// Reads planets from planets.txt
void read_planets(){
FILE* file = fopen("planets.txt", "r");
if(file == NULL){
printf("'planets.txt' not found. Exiting\n");
exit(-1);
}
char line[200];
fgets(line, 200, file);
sscanf(line, "%d", &num_planets);
planets = (float4*)malloc(sizeof(float4)*num_planets);
velocities = (float2*)malloc(sizeof(float2)*num_planets);
for(int p = 0; p < num_planets; p++){
fgets(line, 200, file);
sscanf(line, "%f %f %f %f %f",
&planets[p].x,
&planets[p].y,
&velocities[p].x,
&velocities[p].y,
&planets[p].z);
}
fclose(file);
}
// Writes planets to file
void write_planets(int timestep){
char name[20];
int n = sprintf(name, "planets_out.txt");
FILE* file = fopen(name, "wr+");
for(int p = 0; p < num_planets; p++){
fprintf(file, "%f %f %f %f %f\n",
planets[p].x,
planets[p].y,
velocities[p].x,
velocities[p].y,
planets[p].z);
}
fclose(file);
}
// TODO 7. Calculate the change in velocity for p, caused by the interaction with q
__device__ float2 calculate_velocity_change_planet(float4 p, float4 q){
float2 dv;
float2 dist;
dist.x = q.x - p.x;
dist.y = q.y - p.y;
float abs_dist = sqrt(dist.x*dist.x + dist.y*dist.y);
float dist_cubed = abs_dist*abs_dist*abs_dist;
//printf("%f %f\n", abs_dist, dist_cubed);
dv.x = dT*G*q.z/dist_cubed * dist.x;
dv.y = dT*G*q.z/dist_cubed * dist.y;
return dv;
}
// TODO 5. Calculate the change in velocity for my_planet, caused by the interactions with a block of planets
__device__ float2 calculate_velocity_change_block(float4 my_planet, float4* shared_planets){
float2 velocityChange;
velocityChange.x = 0;
velocityChange.y = 0;
for (int i = 0; i < BLOCK_SIZE; i++)
{
if (my_planet.x == shared_planets[i].x && my_planet.y == shared_planets[i].y) continue;
float2 newChange = calculate_velocity_change_planet(my_planet, shared_planets[i]);
velocityChange.x += newChange.x;
velocityChange.y += newChange.y;
}
return velocityChange;
}
// TODO 4. Update the velocities by calculating the planet interactions
__global__ void update_velocities(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
__shared__ float4 shared[BLOCK_SIZE];
float4 planet = planets[tid];
float2 velocityChange;
velocityChange.x = velocities[tid].x;
velocityChange.y = velocities[tid].y;
for (int i = 0; i < num_planets; i+=BLOCK_SIZE)
{
shared[threadIdx.x] = planets[threadIdx.x + i];
__syncthreads();
float2 vc = calculate_velocity_change_block(planet, shared);
velocityChange.x += vc.x;
velocityChange.y += vc.y;
__syncthreads();
}
velocities[tid].x = velocityChange.x;
velocities[tid].y = velocityChange.y;
}
// TODO 7. Update the positions of the planets using the new velocities
__global__ void update_positions(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
planets[tid].x += velocities[tid].x * dT;
planets[tid].y += velocities[tid].y * dT;
}
int main(int argc, char** argv){
parse_args(argc, argv);
read_planets();
// TODO 1. Allocate device memory, and transfer data to device
int error;
double start=walltime();
/* Allocate device memory, and point to it from local variable */
error = cudaMalloc((void**)&planets_d, sizeof(float4)*num_planets);
/* Everything OK? */
if (error != cudaSuccess)
printf("Malloc: %d\n", error);
error = cudaMalloc((void**)&velocities_d, sizeof(float2)*num_planets);
/* Everything OK? */
if (error != cudaSuccess)
printf("Malloc: %d\n", error);
double mallocTime=walltime();
/* We transfer memory like this */
error = cudaMemcpy(planets_d, planets, sizeof(float4)*num_planets, cudaMemcpyHostToDevice);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy planets to device: %d\n", error);
error = cudaMemcpy(velocities_d, velocities, sizeof(float2)*num_planets, cudaMemcpyHostToDevice);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy to velocities to device: %d\n", error);
double memTime = walltime();
// Calculating the number of blocks
int num_blocks = num_planets/BLOCK_SIZE + ((num_planets%BLOCK_SIZE == 0) ? 0 : 1);
// Main loop
for(int t = 0; t < num_timesteps; t++){
// TODO 2. Call kernels
update_velocities<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = cudaGetLastError();
if (error != cudaSuccess)
printf("update_velocities error - Step: %d CUDA Code: %d\n", t, error);
cudaThreadSynchronize();
update_positions<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = cudaGetLastError();
if (error != cudaSuccess)
printf("update_positions errror - Step: %d CUDA Code: %d\n", t, error);
cudaThreadSynchronize();
}
double calcTime = walltime();
// TODO 3. Transfer data back to host
error = cudaMemcpy(planets, planets_d, sizeof(float4)*num_planets, cudaMemcpyDeviceToHost);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy to planets back to host: %d\n", error);
error = cudaMemcpy(velocities, velocities_d, sizeof(float2)*num_planets, cudaMemcpyDeviceToHost);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy velocities back to host: %d\n", error);
cudaFree(planets_d);
cudaFree(velocities_d);
double tranferBackTime = walltime();
cudaDeviceSynchronize();
printf("Malloc device time: %f\n", mallocTime - start);
printf("Copy to device time: %f\n", memTime - mallocTime);
printf("Calc time: %f\n", calcTime - memTime);
printf("Copy to host time: %f\n", tranferBackTime - calcTime);
printf("Total time: %f\n", walltime() - start);
// Output
write_planets(num_timesteps);
} | .file "tmpxft_001432aa_00000000-6_nbody_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Useage: nbody num_timesteps\n"
.text
.globl _Z10parse_argsiPPc
.type _Z10parse_argsiPPc, @function
_Z10parse_argsiPPc:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cmpl $2, %edi
jne .L6
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, num_timesteps(%rip)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10parse_argsiPPc, .-_Z10parse_argsiPPc
.globl _Z8walltimev
.type _Z8walltimev, @function
_Z8walltimev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZZ8walltimevE1t(%rip), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8+_ZZ8walltimevE1t(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8walltimev, .-_Z8walltimev
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "planets.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "'planets.txt' not found. Exiting\n"
.section .rodata.str1.1
.LC5:
.string "%d"
.LC6:
.string "%f %f %f %f %f"
.text
.globl _Z12read_planetsv
.type _Z12read_planetsv, @function
_Z12read_planetsv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $216, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L16
movq %rax, %r12
movq %rsp, %rbx
movq %rax, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
leaq num_planets(%rip), %rdx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
movl num_planets(%rip), %ebp
movslq %ebp, %rbx
movq %rbx, %rdi
salq $4, %rdi
call malloc@PLT
movq %rax, planets(%rip)
leaq 0(,%rbx,8), %rdi
call malloc@PLT
movq %rax, velocities(%rip)
testl %ebp, %ebp
jle .L11
movl $0, %ebx
leaq .LC6(%rip), %r13
.L12:
movq %rsp, %rbp
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbp, %rdi
call __fgets_chk@PLT
movq %rbx, %rdx
salq $4, %rdx
addq planets(%rip), %rdx
movq velocities(%rip), %rax
leaq (%rax,%rbx,8), %r8
leaq 4(%rdx), %rcx
subq $8, %rsp
.cfi_def_cfa_offset 264
leaq 8(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 272
leaq 4(%r8), %r9
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
addq $1, %rbx
movq %rbp, %rsp
.cfi_def_cfa_offset 256
cmpl %ebx, num_planets(%rip)
jg .L12
.L11:
movq %r12, %rdi
call fclose@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z12read_planetsv, .-_Z12read_planetsv
.section .rodata.str1.1
.LC7:
.string "wr+"
.LC8:
.string "%f %f %f %f %f\n"
.text
.globl _Z13write_planetsi
.type _Z13write_planetsi, @function
_Z13write_planetsi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movabsq $6877969034917276784, %rax
movabsq $32783537689359727, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
cmpl $0, num_planets(%rip)
jle .L19
movl $0, %ebx
leaq .LC8(%rip), %r12
.L20:
movq %rbx, %rax
salq $4, %rax
addq planets(%rip), %rax
movq velocities(%rip), %rdx
leaq (%rdx,%rbx,8), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
pxor %xmm4, %xmm4
cvtss2sd 8(%rax), %xmm4
pxor %xmm3, %xmm3
cvtss2sd 4(%rdx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd (%rdx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rax), %xmm1
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $5, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, num_planets(%rip)
jg .L20
.L19:
movq %rbp, %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z13write_planetsi, .-_Z13write_planetsi
.globl _Z32calculate_velocity_change_planet6float4S_
.type _Z32calculate_velocity_change_planet6float4S_, @function
_Z32calculate_velocity_change_planet6float4S_:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z32calculate_velocity_change_planet6float4S_, .-_Z32calculate_velocity_change_planet6float4S_
.globl _Z31calculate_velocity_change_block6float4PS_
.type _Z31calculate_velocity_change_block6float4PS_, @function
_Z31calculate_velocity_change_block6float4PS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z31calculate_velocity_change_block6float4PS_, .-_Z31calculate_velocity_change_block6float4PS_
.globl _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
.type _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i, @function
_Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17update_velocitiesP6float4P6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i, .-_Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
.globl _Z17update_velocitiesP6float4P6float2i
.type _Z17update_velocitiesP6float4P6float2i, @function
_Z17update_velocitiesP6float4P6float2i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z17update_velocitiesP6float4P6float2i, .-_Z17update_velocitiesP6float4P6float2i
.globl _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
.type _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i, @function
_Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16update_positionsP6float4P6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i, .-_Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
.globl _Z16update_positionsP6float4P6float2i
.type _Z16update_positionsP6float4P6float2i, @function
_Z16update_positionsP6float4P6float2i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z16update_positionsP6float4P6float2i, .-_Z16update_positionsP6float4P6float2i
.section .rodata.str1.1
.LC9:
.string "Malloc: %d\n"
.LC10:
.string "Copy planets to device: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Copy to velocities to device: %d\n"
.align 8
.LC12:
.string "update_velocities error - Step: %d CUDA Code: %d\n"
.align 8
.LC13:
.string "update_positions errror - Step: %d CUDA Code: %d\n"
.align 8
.LC14:
.string "Copy to planets back to host: %d\n"
.align 8
.LC15:
.string "Copy velocities back to host: %d\n"
.section .rodata.str1.1
.LC16:
.string "Malloc device time: %f\n"
.LC17:
.string "Copy to device time: %f\n"
.LC18:
.string "Calc time: %f\n"
.LC19:
.string "Copy to host time: %f\n"
.LC20:
.string "Total time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
call _Z10parse_argsiPPc
call _Z12read_planetsv
call _Z8walltimev
movsd %xmm0, 8(%rsp)
movslq num_planets(%rip), %rsi
salq $4, %rsi
leaq planets_d(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
.L46:
movslq num_planets(%rip), %rsi
salq $3, %rsi
leaq velocities_d(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L61
.L47:
call _Z8walltimev
movsd %xmm0, 16(%rsp)
movslq num_planets(%rip), %rdx
salq $4, %rdx
movl $1, %ecx
movq planets(%rip), %rsi
movq planets_d(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L62
.L48:
movslq num_planets(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq velocities(%rip), %rsi
movq velocities_d(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
.L49:
call _Z8walltimev
movsd %xmm0, 24(%rsp)
movl num_planets(%rip), %edx
testb $31, %dl
setne %bpl
movzbl %bpl, %ebp
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl %eax, %ebp
cmpl $0, num_timesteps(%rip)
jle .L50
movl $0, %ebx
leaq .LC12(%rip), %r13
leaq .LC13(%rip), %r12
jmp .L55
.L60:
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L61:
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L62:
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L63:
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L64:
movl num_planets(%rip), %edx
movq velocities_d(%rip), %rsi
movq planets_d(%rip), %rdi
call _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
jmp .L51
.L65:
movl %eax, %ecx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L52
.L66:
movl num_planets(%rip), %edx
movq velocities_d(%rip), %rsi
movq planets_d(%rip), %rdi
call _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
jmp .L53
.L54:
call cudaThreadSynchronize@PLT
addl $1, %ebx
cmpl %ebx, num_timesteps(%rip)
jle .L50
.L55:
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L51:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L65
.L52:
call cudaThreadSynchronize@PLT
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L53:
call cudaGetLastError@PLT
testl %eax, %eax
je .L54
movl %eax, %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L50:
call _Z8walltimev
movsd %xmm0, 32(%rsp)
movslq num_planets(%rip), %rdx
salq $4, %rdx
movl $2, %ecx
movq planets_d(%rip), %rsi
movq planets(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L67
.L56:
movslq num_planets(%rip), %rdx
salq $3, %rdx
movl $2, %ecx
movq velocities_d(%rip), %rsi
movq velocities(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L68
.L57:
movq planets_d(%rip), %rdi
call cudaFree@PLT
movq velocities_d(%rip), %rdi
call cudaFree@PLT
call _Z8walltimev
movsd %xmm0, 40(%rsp)
call cudaDeviceSynchronize@PLT
movsd 16(%rsp), %xmm1
subsd 8(%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm2
subsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 32(%rsp), %xmm3
subsd 24(%rsp), %xmm3
movapd %xmm3, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 40(%rsp), %xmm0
subsd 32(%rsp), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z8walltimev
subsd 8(%rsp), %xmm0
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl num_timesteps(%rip), %edi
call _Z13write_planetsi
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl %eax, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L68:
movl %eax, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L57
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC21:
.string "_Z16update_positionsP6float4P6float2i"
.align 8
.LC22:
.string "_Z17update_velocitiesP6float4P6float2i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z16update_positionsP6float4P6float2i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z17update_velocitiesP6float4P6float2i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ8walltimevE1t
.comm _ZZ8walltimevE1t,16,16
.globl planets_d
.bss
.align 8
.type planets_d, @object
.size planets_d, 8
planets_d:
.zero 8
.globl velocities_d
.align 8
.type velocities_d, @object
.size velocities_d, 8
velocities_d:
.zero 8
.globl planets
.align 8
.type planets, @object
.size planets, 8
planets:
.zero 8
.globl velocities
.align 8
.type velocities, @object
.size velocities, 8
velocities:
.zero 8
.globl num_timesteps
.align 4
.type num_timesteps, @object
.size num_timesteps, 4
num_timesteps:
.zero 4
.globl num_planets
.align 4
.type num_planets, @object
.size num_planets, 4
num_planets:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <sys/time.h>
#define dT 0.2f
#define G 0.6f
#define BLOCK_SIZE 32
// Global variables
int num_planets;
int num_timesteps;
// Host arrays
float2* velocities;
float4* planets;
// Device arrays
float2* velocities_d;
float4* planets_d;
// Parse command line arguments
void parse_args(int argc, char** argv){
if(argc != 2){
printf("Useage: nbody num_timesteps\n");
exit(-1);
}
num_timesteps = strtol(argv[1], 0, 10);
}
double walltime ( void ) {
static struct timeval t;
gettimeofday ( &t, NULL );
return ( t.tv_sec + 1e-6 * t.tv_usec );
}
// Reads planets from planets.txt
void read_planets(){
FILE* file = fopen("planets.txt", "r");
if(file == NULL){
printf("'planets.txt' not found. Exiting\n");
exit(-1);
}
char line[200];
fgets(line, 200, file);
sscanf(line, "%d", &num_planets);
planets = (float4*)malloc(sizeof(float4)*num_planets);
velocities = (float2*)malloc(sizeof(float2)*num_planets);
for(int p = 0; p < num_planets; p++){
fgets(line, 200, file);
sscanf(line, "%f %f %f %f %f",
&planets[p].x,
&planets[p].y,
&velocities[p].x,
&velocities[p].y,
&planets[p].z);
}
fclose(file);
}
// Writes planets to file
void write_planets(int timestep){
char name[20];
int n = sprintf(name, "planets_out.txt");
FILE* file = fopen(name, "wr+");
for(int p = 0; p < num_planets; p++){
fprintf(file, "%f %f %f %f %f\n",
planets[p].x,
planets[p].y,
velocities[p].x,
velocities[p].y,
planets[p].z);
}
fclose(file);
}
// TODO 7. Calculate the change in velocity for p, caused by the interaction with q
__device__ float2 calculate_velocity_change_planet(float4 p, float4 q){
float2 dv;
float2 dist;
dist.x = q.x - p.x;
dist.y = q.y - p.y;
float abs_dist = sqrt(dist.x*dist.x + dist.y*dist.y);
float dist_cubed = abs_dist*abs_dist*abs_dist;
//printf("%f %f\n", abs_dist, dist_cubed);
dv.x = dT*G*q.z/dist_cubed * dist.x;
dv.y = dT*G*q.z/dist_cubed * dist.y;
return dv;
}
// TODO 5. Calculate the change in velocity for my_planet, caused by the interactions with a block of planets
__device__ float2 calculate_velocity_change_block(float4 my_planet, float4* shared_planets){
float2 velocityChange;
velocityChange.x = 0;
velocityChange.y = 0;
for (int i = 0; i < BLOCK_SIZE; i++)
{
if (my_planet.x == shared_planets[i].x && my_planet.y == shared_planets[i].y) continue;
float2 newChange = calculate_velocity_change_planet(my_planet, shared_planets[i]);
velocityChange.x += newChange.x;
velocityChange.y += newChange.y;
}
return velocityChange;
}
// TODO 4. Update the velocities by calculating the planet interactions
__global__ void update_velocities(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
__shared__ float4 shared[BLOCK_SIZE];
float4 planet = planets[tid];
float2 velocityChange;
velocityChange.x = velocities[tid].x;
velocityChange.y = velocities[tid].y;
for (int i = 0; i < num_planets; i+=BLOCK_SIZE)
{
shared[threadIdx.x] = planets[threadIdx.x + i];
__syncthreads();
float2 vc = calculate_velocity_change_block(planet, shared);
velocityChange.x += vc.x;
velocityChange.y += vc.y;
__syncthreads();
}
velocities[tid].x = velocityChange.x;
velocities[tid].y = velocityChange.y;
}
// TODO 7. Update the positions of the planets using the new velocities
__global__ void update_positions(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
planets[tid].x += velocities[tid].x * dT;
planets[tid].y += velocities[tid].y * dT;
}
int main(int argc, char** argv){
parse_args(argc, argv);
read_planets();
// TODO 1. Allocate device memory, and transfer data to device
int error;
double start=walltime();
/* Allocate device memory, and point to it from local variable */
error = cudaMalloc((void**)&planets_d, sizeof(float4)*num_planets);
/* Everything OK? */
if (error != cudaSuccess)
printf("Malloc: %d\n", error);
error = cudaMalloc((void**)&velocities_d, sizeof(float2)*num_planets);
/* Everything OK? */
if (error != cudaSuccess)
printf("Malloc: %d\n", error);
double mallocTime=walltime();
/* We transfer memory like this */
error = cudaMemcpy(planets_d, planets, sizeof(float4)*num_planets, cudaMemcpyHostToDevice);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy planets to device: %d\n", error);
error = cudaMemcpy(velocities_d, velocities, sizeof(float2)*num_planets, cudaMemcpyHostToDevice);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy to velocities to device: %d\n", error);
double memTime = walltime();
// Calculating the number of blocks
int num_blocks = num_planets/BLOCK_SIZE + ((num_planets%BLOCK_SIZE == 0) ? 0 : 1);
// Main loop
for(int t = 0; t < num_timesteps; t++){
// TODO 2. Call kernels
update_velocities<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = cudaGetLastError();
if (error != cudaSuccess)
printf("update_velocities error - Step: %d CUDA Code: %d\n", t, error);
cudaThreadSynchronize();
update_positions<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = cudaGetLastError();
if (error != cudaSuccess)
printf("update_positions errror - Step: %d CUDA Code: %d\n", t, error);
cudaThreadSynchronize();
}
double calcTime = walltime();
// TODO 3. Transfer data back to host
error = cudaMemcpy(planets, planets_d, sizeof(float4)*num_planets, cudaMemcpyDeviceToHost);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy to planets back to host: %d\n", error);
error = cudaMemcpy(velocities, velocities_d, sizeof(float2)*num_planets, cudaMemcpyDeviceToHost);
/* and check for errors */
if (error != cudaSuccess)
printf("Copy velocities back to host: %d\n", error);
cudaFree(planets_d);
cudaFree(velocities_d);
double tranferBackTime = walltime();
cudaDeviceSynchronize();
printf("Malloc device time: %f\n", mallocTime - start);
printf("Copy to device time: %f\n", memTime - mallocTime);
printf("Calc time: %f\n", calcTime - memTime);
printf("Copy to host time: %f\n", tranferBackTime - calcTime);
printf("Total time: %f\n", walltime() - start);
// Output
write_planets(num_timesteps);
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define dT 0.2f
#define G 0.6f
#define BLOCK_SIZE 32
// Global variables
int num_planets;
int num_timesteps;
// Host arrays
float2* velocities;
float4* planets;
// Device arrays
float2* velocities_d;
float4* planets_d;
// Parse command line arguments
void parse_args(int argc, char** argv){
if(argc != 2){
printf("Useage: nbody num_timesteps\n");
exit(-1);
}
num_timesteps = strtol(argv[1], 0, 10);
}
double walltime ( void ) {
static struct timeval t;
gettimeofday ( &t, NULL );
return ( t.tv_sec + 1e-6 * t.tv_usec );
}
// Reads planets from planets.txt
void read_planets(){
FILE* file = fopen("planets.txt", "r");
if(file == NULL){
printf("'planets.txt' not found. Exiting\n");
exit(-1);
}
char line[200];
fgets(line, 200, file);
sscanf(line, "%d", &num_planets);
planets = (float4*)malloc(sizeof(float4)*num_planets);
velocities = (float2*)malloc(sizeof(float2)*num_planets);
for(int p = 0; p < num_planets; p++){
fgets(line, 200, file);
sscanf(line, "%f %f %f %f %f",
&planets[p].x,
&planets[p].y,
&velocities[p].x,
&velocities[p].y,
&planets[p].z);
}
fclose(file);
}
// Writes planets to file
void write_planets(int timestep){
char name[20];
int n = sprintf(name, "planets_out.txt");
FILE* file = fopen(name, "wr+");
for(int p = 0; p < num_planets; p++){
fprintf(file, "%f %f %f %f %f\n",
planets[p].x,
planets[p].y,
velocities[p].x,
velocities[p].y,
planets[p].z);
}
fclose(file);
}
// TODO 7. Calculate the change in velocity for p, caused by the interaction with q
__device__ float2 calculate_velocity_change_planet(float4 p, float4 q){
float2 dv;
float2 dist;
dist.x = q.x - p.x;
dist.y = q.y - p.y;
float abs_dist = sqrt(dist.x*dist.x + dist.y*dist.y);
float dist_cubed = abs_dist*abs_dist*abs_dist;
//printf("%f %f\n", abs_dist, dist_cubed);
dv.x = dT*G*q.z/dist_cubed * dist.x;
dv.y = dT*G*q.z/dist_cubed * dist.y;
return dv;
}
// TODO 5. Calculate the change in velocity for my_planet, caused by the interactions with a block of planets
__device__ float2 calculate_velocity_change_block(float4 my_planet, float4* shared_planets){
float2 velocityChange;
velocityChange.x = 0;
velocityChange.y = 0;
for (int i = 0; i < BLOCK_SIZE; i++)
{
if (my_planet.x == shared_planets[i].x && my_planet.y == shared_planets[i].y) continue;
float2 newChange = calculate_velocity_change_planet(my_planet, shared_planets[i]);
velocityChange.x += newChange.x;
velocityChange.y += newChange.y;
}
return velocityChange;
}
// TODO 4. Update the velocities by calculating the planet interactions
__global__ void update_velocities(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
__shared__ float4 shared[BLOCK_SIZE];
float4 planet = planets[tid];
float2 velocityChange;
velocityChange.x = velocities[tid].x;
velocityChange.y = velocities[tid].y;
for (int i = 0; i < num_planets; i+=BLOCK_SIZE)
{
shared[threadIdx.x] = planets[threadIdx.x + i];
__syncthreads();
float2 vc = calculate_velocity_change_block(planet, shared);
velocityChange.x += vc.x;
velocityChange.y += vc.y;
__syncthreads();
}
velocities[tid].x = velocityChange.x;
velocities[tid].y = velocityChange.y;
}
// TODO 7. Update the positions of the planets using the new velocities
__global__ void update_positions(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
planets[tid].x += velocities[tid].x * dT;
planets[tid].y += velocities[tid].y * dT;
}
int main(int argc, char** argv){
parse_args(argc, argv);
read_planets();
// TODO 1. Allocate device memory, and transfer data to device
int error;
double start=walltime();
/* Allocate device memory, and point to it from local variable */
error = hipMalloc((void**)&planets_d, sizeof(float4)*num_planets);
/* Everything OK? */
if (error != hipSuccess)
printf("Malloc: %d\n", error);
error = hipMalloc((void**)&velocities_d, sizeof(float2)*num_planets);
/* Everything OK? */
if (error != hipSuccess)
printf("Malloc: %d\n", error);
double mallocTime=walltime();
/* We transfer memory like this */
error = hipMemcpy(planets_d, planets, sizeof(float4)*num_planets, hipMemcpyHostToDevice);
/* and check for errors */
if (error != hipSuccess)
printf("Copy planets to device: %d\n", error);
error = hipMemcpy(velocities_d, velocities, sizeof(float2)*num_planets, hipMemcpyHostToDevice);
/* and check for errors */
if (error != hipSuccess)
printf("Copy to velocities to device: %d\n", error);
double memTime = walltime();
// Calculating the number of blocks
int num_blocks = num_planets/BLOCK_SIZE + ((num_planets%BLOCK_SIZE == 0) ? 0 : 1);
// Main loop
for(int t = 0; t < num_timesteps; t++){
// TODO 2. Call kernels
update_velocities<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = hipGetLastError();
if (error != hipSuccess)
printf("update_velocities error - Step: %d CUDA Code: %d\n", t, error);
hipDeviceSynchronize();
update_positions<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = hipGetLastError();
if (error != hipSuccess)
printf("update_positions errror - Step: %d CUDA Code: %d\n", t, error);
hipDeviceSynchronize();
}
double calcTime = walltime();
// TODO 3. Transfer data back to host
error = hipMemcpy(planets, planets_d, sizeof(float4)*num_planets, hipMemcpyDeviceToHost);
/* and check for errors */
if (error != hipSuccess)
printf("Copy to planets back to host: %d\n", error);
error = hipMemcpy(velocities, velocities_d, sizeof(float2)*num_planets, hipMemcpyDeviceToHost);
/* and check for errors */
if (error != hipSuccess)
printf("Copy velocities back to host: %d\n", error);
hipFree(planets_d);
hipFree(velocities_d);
double tranferBackTime = walltime();
hipDeviceSynchronize();
printf("Malloc device time: %f\n", mallocTime - start);
printf("Copy to device time: %f\n", memTime - mallocTime);
printf("Calc time: %f\n", calcTime - memTime);
printf("Copy to host time: %f\n", tranferBackTime - calcTime);
printf("Total time: %f\n", walltime() - start);
// Output
write_planets(num_timesteps);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define dT 0.2f
#define G 0.6f
#define BLOCK_SIZE 32
// Global variables
int num_planets;
int num_timesteps;
// Host arrays
float2* velocities;
float4* planets;
// Device arrays
float2* velocities_d;
float4* planets_d;
// Parse command line arguments
void parse_args(int argc, char** argv){
if(argc != 2){
printf("Useage: nbody num_timesteps\n");
exit(-1);
}
num_timesteps = strtol(argv[1], 0, 10);
}
double walltime ( void ) {
static struct timeval t;
gettimeofday ( &t, NULL );
return ( t.tv_sec + 1e-6 * t.tv_usec );
}
// Reads planets from planets.txt
void read_planets(){
FILE* file = fopen("planets.txt", "r");
if(file == NULL){
printf("'planets.txt' not found. Exiting\n");
exit(-1);
}
char line[200];
fgets(line, 200, file);
sscanf(line, "%d", &num_planets);
planets = (float4*)malloc(sizeof(float4)*num_planets);
velocities = (float2*)malloc(sizeof(float2)*num_planets);
for(int p = 0; p < num_planets; p++){
fgets(line, 200, file);
sscanf(line, "%f %f %f %f %f",
&planets[p].x,
&planets[p].y,
&velocities[p].x,
&velocities[p].y,
&planets[p].z);
}
fclose(file);
}
// Writes planets to file
void write_planets(int timestep){
char name[20];
int n = sprintf(name, "planets_out.txt");
FILE* file = fopen(name, "wr+");
for(int p = 0; p < num_planets; p++){
fprintf(file, "%f %f %f %f %f\n",
planets[p].x,
planets[p].y,
velocities[p].x,
velocities[p].y,
planets[p].z);
}
fclose(file);
}
// TODO 7. Calculate the change in velocity for p, caused by the interaction with q
__device__ float2 calculate_velocity_change_planet(float4 p, float4 q){
float2 dv;
float2 dist;
dist.x = q.x - p.x;
dist.y = q.y - p.y;
float abs_dist = sqrt(dist.x*dist.x + dist.y*dist.y);
float dist_cubed = abs_dist*abs_dist*abs_dist;
//printf("%f %f\n", abs_dist, dist_cubed);
dv.x = dT*G*q.z/dist_cubed * dist.x;
dv.y = dT*G*q.z/dist_cubed * dist.y;
return dv;
}
// TODO 5. Calculate the change in velocity for my_planet, caused by the interactions with a block of planets
__device__ float2 calculate_velocity_change_block(float4 my_planet, float4* shared_planets){
float2 velocityChange;
velocityChange.x = 0;
velocityChange.y = 0;
for (int i = 0; i < BLOCK_SIZE; i++)
{
if (my_planet.x == shared_planets[i].x && my_planet.y == shared_planets[i].y) continue;
float2 newChange = calculate_velocity_change_planet(my_planet, shared_planets[i]);
velocityChange.x += newChange.x;
velocityChange.y += newChange.y;
}
return velocityChange;
}
// TODO 4. Update the velocities by calculating the planet interactions
__global__ void update_velocities(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
__shared__ float4 shared[BLOCK_SIZE];
float4 planet = planets[tid];
float2 velocityChange;
velocityChange.x = velocities[tid].x;
velocityChange.y = velocities[tid].y;
for (int i = 0; i < num_planets; i+=BLOCK_SIZE)
{
shared[threadIdx.x] = planets[threadIdx.x + i];
__syncthreads();
float2 vc = calculate_velocity_change_block(planet, shared);
velocityChange.x += vc.x;
velocityChange.y += vc.y;
__syncthreads();
}
velocities[tid].x = velocityChange.x;
velocities[tid].y = velocityChange.y;
}
// TODO 7. Update the positions of the planets using the new velocities
__global__ void update_positions(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
planets[tid].x += velocities[tid].x * dT;
planets[tid].y += velocities[tid].y * dT;
}
int main(int argc, char** argv){
parse_args(argc, argv);
read_planets();
// TODO 1. Allocate device memory, and transfer data to device
int error;
double start=walltime();
/* Allocate device memory, and point to it from local variable */
error = hipMalloc((void**)&planets_d, sizeof(float4)*num_planets);
/* Everything OK? */
if (error != hipSuccess)
printf("Malloc: %d\n", error);
error = hipMalloc((void**)&velocities_d, sizeof(float2)*num_planets);
/* Everything OK? */
if (error != hipSuccess)
printf("Malloc: %d\n", error);
double mallocTime=walltime();
/* We transfer memory like this */
error = hipMemcpy(planets_d, planets, sizeof(float4)*num_planets, hipMemcpyHostToDevice);
/* and check for errors */
if (error != hipSuccess)
printf("Copy planets to device: %d\n", error);
error = hipMemcpy(velocities_d, velocities, sizeof(float2)*num_planets, hipMemcpyHostToDevice);
/* and check for errors */
if (error != hipSuccess)
printf("Copy to velocities to device: %d\n", error);
double memTime = walltime();
// Calculating the number of blocks
int num_blocks = num_planets/BLOCK_SIZE + ((num_planets%BLOCK_SIZE == 0) ? 0 : 1);
// Main loop
for(int t = 0; t < num_timesteps; t++){
// TODO 2. Call kernels
update_velocities<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = hipGetLastError();
if (error != hipSuccess)
printf("update_velocities error - Step: %d CUDA Code: %d\n", t, error);
hipDeviceSynchronize();
update_positions<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = hipGetLastError();
if (error != hipSuccess)
printf("update_positions errror - Step: %d CUDA Code: %d\n", t, error);
hipDeviceSynchronize();
}
double calcTime = walltime();
// TODO 3. Transfer data back to host
error = hipMemcpy(planets, planets_d, sizeof(float4)*num_planets, hipMemcpyDeviceToHost);
/* and check for errors */
if (error != hipSuccess)
printf("Copy to planets back to host: %d\n", error);
error = hipMemcpy(velocities, velocities_d, sizeof(float2)*num_planets, hipMemcpyDeviceToHost);
/* and check for errors */
if (error != hipSuccess)
printf("Copy velocities back to host: %d\n", error);
hipFree(planets_d);
hipFree(velocities_d);
double tranferBackTime = walltime();
hipDeviceSynchronize();
printf("Malloc device time: %f\n", mallocTime - start);
printf("Copy to device time: %f\n", memTime - mallocTime);
printf("Calc time: %f\n", calcTime - memTime);
printf("Copy to host time: %f\n", tranferBackTime - calcTime);
printf("Total time: %f\n", walltime() - start);
// Output
write_planets(num_timesteps);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.globl _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 8
.type _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@function
_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
s_cmp_lt_i32 s4, 1
global_load_b64 v[7:8], v[5:6], off
s_cbranch_scc1 .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 4, v[1:2]
v_lshlrev_b32_e32 v9, 4, v0
s_mov_b32 s1, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b128 v[1:4], v[1:2], off
s_waitcnt vmcnt(0)
v_mov_b32_e32 v4, 0
s_branch .LBB0_3
.LBB0_2:
v_dual_add_f32 v7, v7, v10 :: v_dual_add_f32 v8, v8, v3
s_add_i32 s1, s1, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s1, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_add_nc_u32_e32 v3, s1, v0
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 4, v[3:4]
v_mov_b32_e32 v3, 0
v_add_co_u32 v10, vcc_lo, s2, v10
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
global_load_b128 v[11:14], v[10:11], off
v_mov_b32_e32 v10, 0
s_waitcnt vmcnt(0)
ds_store_b128 v9, v[11:14]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s5, s5, 16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s5, 0x200
s_cbranch_scc0 .LBB0_2
.LBB0_5:
v_mov_b32_e32 v11, s5
s_mov_b32 s6, exec_lo
ds_load_b32 v11, v11
s_waitcnt lgkmcnt(0)
v_cmp_neq_f32_e64 s0, v1, v11
v_cmpx_eq_f32_e32 v1, v11
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v11, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s0, s0, exec_lo
ds_load_b32 v11, v11 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_neq_f32_e32 vcc_lo, v2, v11
s_and_b32 s7, vcc_lo, exec_lo
s_or_b32 s0, s0, s7
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v11, s5
ds_load_b128 v[11:14], v11
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v12, v12, v2 :: v_dual_sub_f32 v11, v11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v13, 0x3df5c290, v13 :: v_dual_mul_f32 v14, v12, v12
v_fmac_f32_e32 v14, v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v15, 0x4f800000, v14
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v14
v_cndmask_b32_e32 v14, v14, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v15, v14
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v16, -1, v15
v_add_nc_u32_e32 v17, 1, v15
v_fma_f32 v18, -v16, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v19, -v17, v15, v14
v_cmp_ge_f32_e64 s0, 0, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, v15, v16, s0
v_cmp_lt_f32_e64 s0, 0, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v15, v15, v17, s0
v_mul_f32_e32 v16, 0x37800000, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v15, v15, v16, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v14, 0x260
v_cndmask_b32_e32 v14, v15, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v14, v14
v_mul_f32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v15, null, v14, v14, v13
v_div_scale_f32 v18, vcc_lo, v13, v14, v13
v_rcp_f32_e32 v16, v15
s_waitcnt_depctr 0xfff
v_fma_f32 v17, -v15, v16, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v17, v16
v_mul_f32_e32 v17, v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v19, -v15, v17, v18
v_fmac_f32_e32 v17, v19, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v15, -v15, v17, v18
v_div_fmas_f32 v15, v15, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v13, v15, v14, v13
v_fmac_f32_e32 v10, v11, v13
v_fmac_f32_e32 v3, v12, v13
s_branch .LBB0_4
.LBB0_9:
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[7:8], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, .Lfunc_end0-_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.globl _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 8
.type _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@function
_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_lshlrev_b64 v[0:1], 4, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_fmamk_f32 v4, v6, 0x3e4ccccd, v4
global_store_b32 v[0:1], v4, off
global_load_b32 v2, v[2:3], off offset:4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v5, 0x3e4ccccd, v2
global_store_b32 v[0:1], v5, off offset:4
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, .Lfunc_end1-_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define dT 0.2f
#define G 0.6f
#define BLOCK_SIZE 32
// Global variables
int num_planets;
int num_timesteps;
// Host arrays
float2* velocities;
float4* planets;
// Device arrays
float2* velocities_d;
float4* planets_d;
// Parse command line arguments
void parse_args(int argc, char** argv){
if(argc != 2){
printf("Useage: nbody num_timesteps\n");
exit(-1);
}
num_timesteps = strtol(argv[1], 0, 10);
}
double walltime ( void ) {
static struct timeval t;
gettimeofday ( &t, NULL );
return ( t.tv_sec + 1e-6 * t.tv_usec );
}
// Reads planets from planets.txt
void read_planets(){
FILE* file = fopen("planets.txt", "r");
if(file == NULL){
printf("'planets.txt' not found. Exiting\n");
exit(-1);
}
char line[200];
fgets(line, 200, file);
sscanf(line, "%d", &num_planets);
planets = (float4*)malloc(sizeof(float4)*num_planets);
velocities = (float2*)malloc(sizeof(float2)*num_planets);
for(int p = 0; p < num_planets; p++){
fgets(line, 200, file);
sscanf(line, "%f %f %f %f %f",
&planets[p].x,
&planets[p].y,
&velocities[p].x,
&velocities[p].y,
&planets[p].z);
}
fclose(file);
}
// Writes planets to file
void write_planets(int timestep){
char name[20];
int n = sprintf(name, "planets_out.txt");
FILE* file = fopen(name, "wr+");
for(int p = 0; p < num_planets; p++){
fprintf(file, "%f %f %f %f %f\n",
planets[p].x,
planets[p].y,
velocities[p].x,
velocities[p].y,
planets[p].z);
}
fclose(file);
}
// TODO 7. Calculate the change in velocity for p, caused by the interaction with q
__device__ float2 calculate_velocity_change_planet(float4 p, float4 q){
float2 dv;
float2 dist;
dist.x = q.x - p.x;
dist.y = q.y - p.y;
float abs_dist = sqrt(dist.x*dist.x + dist.y*dist.y);
float dist_cubed = abs_dist*abs_dist*abs_dist;
//printf("%f %f\n", abs_dist, dist_cubed);
dv.x = dT*G*q.z/dist_cubed * dist.x;
dv.y = dT*G*q.z/dist_cubed * dist.y;
return dv;
}
// TODO 5. Calculate the change in velocity for my_planet, caused by the interactions with a block of planets
__device__ float2 calculate_velocity_change_block(float4 my_planet, float4* shared_planets){
float2 velocityChange;
velocityChange.x = 0;
velocityChange.y = 0;
for (int i = 0; i < BLOCK_SIZE; i++)
{
if (my_planet.x == shared_planets[i].x && my_planet.y == shared_planets[i].y) continue;
float2 newChange = calculate_velocity_change_planet(my_planet, shared_planets[i]);
velocityChange.x += newChange.x;
velocityChange.y += newChange.y;
}
return velocityChange;
}
// TODO 4. Update the velocities by calculating the planet interactions
__global__ void update_velocities(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
__shared__ float4 shared[BLOCK_SIZE];
float4 planet = planets[tid];
float2 velocityChange;
velocityChange.x = velocities[tid].x;
velocityChange.y = velocities[tid].y;
for (int i = 0; i < num_planets; i+=BLOCK_SIZE)
{
shared[threadIdx.x] = planets[threadIdx.x + i];
__syncthreads();
float2 vc = calculate_velocity_change_block(planet, shared);
velocityChange.x += vc.x;
velocityChange.y += vc.y;
__syncthreads();
}
velocities[tid].x = velocityChange.x;
velocities[tid].y = velocityChange.y;
}
// TODO 7. Update the positions of the planets using the new velocities
__global__ void update_positions(float4* planets, float2* velocities, int num_planets){
int tid = threadIdx.x + blockIdx.x*blockDim.x;
planets[tid].x += velocities[tid].x * dT;
planets[tid].y += velocities[tid].y * dT;
}
int main(int argc, char** argv){
parse_args(argc, argv);
read_planets();
// TODO 1. Allocate device memory, and transfer data to device
int error;
double start=walltime();
/* Allocate device memory, and point to it from local variable */
error = hipMalloc((void**)&planets_d, sizeof(float4)*num_planets);
/* Everything OK? */
if (error != hipSuccess)
printf("Malloc: %d\n", error);
error = hipMalloc((void**)&velocities_d, sizeof(float2)*num_planets);
/* Everything OK? */
if (error != hipSuccess)
printf("Malloc: %d\n", error);
double mallocTime=walltime();
/* We transfer memory like this */
error = hipMemcpy(planets_d, planets, sizeof(float4)*num_planets, hipMemcpyHostToDevice);
/* and check for errors */
if (error != hipSuccess)
printf("Copy planets to device: %d\n", error);
error = hipMemcpy(velocities_d, velocities, sizeof(float2)*num_planets, hipMemcpyHostToDevice);
/* and check for errors */
if (error != hipSuccess)
printf("Copy to velocities to device: %d\n", error);
double memTime = walltime();
// Calculating the number of blocks
int num_blocks = num_planets/BLOCK_SIZE + ((num_planets%BLOCK_SIZE == 0) ? 0 : 1);
// Main loop
for(int t = 0; t < num_timesteps; t++){
// TODO 2. Call kernels
update_velocities<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = hipGetLastError();
if (error != hipSuccess)
printf("update_velocities error - Step: %d CUDA Code: %d\n", t, error);
hipDeviceSynchronize();
update_positions<<<num_blocks,BLOCK_SIZE>>>(planets_d, velocities_d, num_planets);
// We print the error code from last call if things went bad
error = hipGetLastError();
if (error != hipSuccess)
printf("update_positions errror - Step: %d CUDA Code: %d\n", t, error);
hipDeviceSynchronize();
}
double calcTime = walltime();
// TODO 3. Transfer data back to host
error = hipMemcpy(planets, planets_d, sizeof(float4)*num_planets, hipMemcpyDeviceToHost);
/* and check for errors */
if (error != hipSuccess)
printf("Copy to planets back to host: %d\n", error);
error = hipMemcpy(velocities, velocities_d, sizeof(float2)*num_planets, hipMemcpyDeviceToHost);
/* and check for errors */
if (error != hipSuccess)
printf("Copy velocities back to host: %d\n", error);
hipFree(planets_d);
hipFree(velocities_d);
double tranferBackTime = walltime();
hipDeviceSynchronize();
printf("Malloc device time: %f\n", mallocTime - start);
printf("Copy to device time: %f\n", memTime - mallocTime);
printf("Calc time: %f\n", calcTime - memTime);
printf("Copy to host time: %f\n", tranferBackTime - calcTime);
printf("Total time: %f\n", walltime() - start);
// Output
write_planets(num_timesteps);
} | .text
.file "nbody_cuda.hip"
.globl _Z10parse_argsiPPc # -- Begin function _Z10parse_argsiPPc
.p2align 4, 0x90
.type _Z10parse_argsiPPc,@function
_Z10parse_argsiPPc: # @_Z10parse_argsiPPc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $2, %edi
jne .LBB0_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, num_timesteps(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z10parse_argsiPPc, .Lfunc_end0-_Z10parse_argsiPPc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8walltimev
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z8walltimev
.p2align 4, 0x90
.type _Z8walltimev,@function
_Z8walltimev: # @_Z8walltimev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm1
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8walltimev, .Lfunc_end1-_Z8walltimev
.cfi_endproc
# -- End function
.globl _Z12read_planetsv # -- Begin function _Z12read_planetsv
.p2align 4, 0x90
.type _Z12read_planetsv,@function
_Z12read_planetsv: # @_Z12read_planetsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $224, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_5
# %bb.1:
movq %rax, %rbx
leaq 16(%rsp), %r14
movq %r14, %rdi
movl $200, %esi
movq %rax, %rdx
callq fgets
movl $.L.str.4, %esi
movl $num_planets, %edx
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_sscanf
movslq num_planets(%rip), %r14
movq %r14, %rdi
shlq $4, %rdi
callq malloc
movq %rax, planets(%rip)
shlq $3, %r14
movq %r14, %rdi
callq malloc
movq %rax, velocities(%rip)
cmpl $0, num_planets(%rip)
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl $4, %r15d
movl $8, %r12d
leaq 16(%rsp), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq planets(%rip), %rax
leaq (%rax,%r12), %rsi
leaq (%rax,%r12), %rdx
addq $-8, %rdx
leaq (%rax,%r12), %rcx
addq $-4, %rcx
movq velocities(%rip), %r9
leaq (%r9,%r15), %r8
addq $-4, %r8
addq %r15, %r9
movq %rsi, (%rsp)
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_sscanf
incq %r13
movslq num_planets(%rip), %rax
addq $8, %r15
addq $16, %r12
cmpq %rax, %r13
jl .LBB2_3
.LBB2_4: # %._crit_edge
movq %rbx, %rdi
callq fclose
addq $224, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 272
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z12read_planetsv, .Lfunc_end2-_Z12read_planetsv
.cfi_endproc
# -- End function
.globl _Z13write_planetsi # -- Begin function _Z13write_planetsi
.p2align 4, 0x90
.type _Z13write_planetsi,@function
_Z13write_planetsi: # @_Z13write_planetsi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .L.str.6(%rip), %xmm0
movaps %xmm0, (%rsp)
movq %rsp, %rdi
movl $.L.str.7, %esi
callq fopen
movq %rax, %rbx
cmpl $0, num_planets(%rip)
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl $4, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq planets(%rip), %rax
movss -8(%rax,%r14,2), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss -4(%rax,%r14,2), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq velocities(%rip), %rcx
movss -4(%rcx,%r14), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rcx,%r14), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movss (%rax,%r14,2), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
movl $.L.str.8, %esi
movq %rbx, %rdi
movb $5, %al
callq fprintf
incq %r15
movslq num_planets(%rip), %rax
addq $8, %r14
cmpq %rax, %r15
jl .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rdi
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z13write_planetsi, .Lfunc_end3-_Z13write_planetsi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi # -- Begin function _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 4, 0x90
.type _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@function
_Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi: # @_Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, .Lfunc_end4-_Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi # -- Begin function _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 4, 0x90
.type _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@function
_Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi: # @_Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, .Lfunc_end5-_Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB6_28
# %bb.1: # %_Z10parse_argsiPPc.exit
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, num_timesteps(%rip)
callq _Z12read_planetsv
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movslq num_planets(%rip), %rsi
shlq $4, %rsi
movl $planets_d, %edi
callq hipMalloc
testl %eax, %eax
je .LBB6_3
# %bb.2:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_3:
movslq num_planets(%rip), %rsi
shlq $3, %rsi
movl $velocities_d, %edi
callq hipMalloc
testl %eax, %eax
je .LBB6_5
# %bb.4:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_5:
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq planets_d(%rip), %rdi
movq planets(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $4, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_7
# %bb.6:
movl $.L.str.10, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_7:
movq velocities_d(%rip), %rdi
movq velocities(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_9
# %bb.8:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_9:
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
cmpl $0, num_timesteps(%rip)
jle .LBB6_20
# %bb.10: # %.lr.ph
movabsq $4294967328, %rbx # imm = 0x100000020
movl num_planets(%rip), %eax
movl %eax, %ecx
andl $31, %ecx
leal 31(%rax), %edx
testl %eax, %eax
cmovnsl %eax, %edx
sarl $5, %edx
cmpl $1, %ecx
sbbl $-1, %edx
leaq (%rdx,%rbx), %r14
addq $-32, %r14
leaq 136(%rsp), %r13
leaq 128(%rsp), %rbp
leaq 96(%rsp), %r15
xorl %r12d, %r12d
jmp .LBB6_11
.p2align 4, 0x90
.LBB6_19: # in Loop: Header=BB6_11 Depth=1
callq hipDeviceSynchronize
incl %r12d
cmpl num_timesteps(%rip), %r12d
jge .LBB6_20
.LBB6_11: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_13
# %bb.12: # in Loop: Header=BB6_11 Depth=1
movq planets_d(%rip), %rax
movq velocities_d(%rip), %rcx
movl num_planets(%rip), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
movq %r15, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_13: # in Loop: Header=BB6_11 Depth=1
callq hipGetLastError
testl %eax, %eax
je .LBB6_15
# %bb.14: # in Loop: Header=BB6_11 Depth=1
movl $.L.str.12, %edi
movl %r12d, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
.LBB6_15: # in Loop: Header=BB6_11 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_17
# %bb.16: # in Loop: Header=BB6_11 Depth=1
movq planets_d(%rip), %rax
movq velocities_d(%rip), %rcx
movl num_planets(%rip), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
movq %r15, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_17: # in Loop: Header=BB6_11 Depth=1
callq hipGetLastError
testl %eax, %eax
je .LBB6_19
# %bb.18: # in Loop: Header=BB6_11 Depth=1
movl $.L.str.13, %edi
movl %r12d, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
jmp .LBB6_19
.LBB6_20: # %._crit_edge
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 144(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq planets(%rip), %rdi
movq planets_d(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $4, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_22
# %bb.21:
movl $.L.str.14, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_22:
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 160(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 152(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 144(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq velocities(%rip), %rdi
movq velocities_d(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $3, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_24
# %bb.23:
movl $.L.str.15, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_24:
movq planets_d(%rip), %rdi
callq hipFree
movq velocities_d(%rip), %rdi
callq hipFree
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.16, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.17, %edi
movb $1, %al
callq printf
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.18, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.19, %edi
movb $1, %al
callq printf
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.20, %edi
movb $1, %al
callq printf
movaps .L.str.6(%rip), %xmm0
movaps %xmm0, 96(%rsp)
leaq 96(%rsp), %rdi
movl $.L.str.7, %esi
callq fopen
movq %rax, %rbx
cmpl $0, num_planets(%rip)
jle .LBB6_27
# %bb.25: # %.lr.ph.i.preheader
movl $8, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_26: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq planets(%rip), %rax
movss -8(%rax,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss -4(%rax,%r14), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq velocities(%rip), %rcx
movss (%rcx,%r15,8), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 4(%rcx,%r15,8), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movss (%rax,%r14), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
movl $.L.str.8, %esi
movq %rbx, %rdi
movb $5, %al
callq fprintf
incq %r15
movslq num_planets(%rip), %rax
addq $16, %r14
cmpq %rax, %r15
jl .LBB6_26
.LBB6_27: # %_Z13write_planetsi.exit
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_28:
.cfi_def_cfa_offset 224
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type num_planets,@object # @num_planets
.bss
.globl num_planets
.p2align 2, 0x0
num_planets:
.long 0 # 0x0
.size num_planets, 4
.type num_timesteps,@object # @num_timesteps
.globl num_timesteps
.p2align 2, 0x0
num_timesteps:
.long 0 # 0x0
.size num_timesteps, 4
.type velocities,@object # @velocities
.globl velocities
.p2align 3, 0x0
velocities:
.quad 0
.size velocities, 8
.type planets,@object # @planets
.globl planets
.p2align 3, 0x0
planets:
.quad 0
.size planets, 8
.type velocities_d,@object # @velocities_d
.globl velocities_d
.p2align 3, 0x0
velocities_d:
.quad 0
.size velocities_d, 8
.type planets_d,@object # @planets_d
.globl planets_d
.p2align 3, 0x0
planets_d:
.quad 0
.size planets_d, 8
.type _ZZ8walltimevE1t,@object # @_ZZ8walltimevE1t
.local _ZZ8walltimevE1t
.comm _ZZ8walltimevE1t,16,8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "planets.txt"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f %f %f %f %f"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L.str.6:
.asciz "planets_out.txt"
.size .L.str.6, 16
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "wr+"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f %f %f %f %f\n"
.size .L.str.8, 16
.type _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@object # @_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.section .rodata,"a",@progbits
.globl _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 3, 0x0
_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi:
.quad _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.size _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, 8
.type _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@object # @_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.globl _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 3, 0x0
_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi:
.quad _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.size _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "Malloc: %d\n"
.size .L.str.9, 12
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Copy planets to device: %d\n"
.size .L.str.10, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Copy to velocities to device: %d\n"
.size .L.str.11, 34
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "update_velocities error - Step: %d CUDA Code: %d\n"
.size .L.str.12, 50
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "update_positions errror - Step: %d CUDA Code: %d\n"
.size .L.str.13, 50
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Copy to planets back to host: %d\n"
.size .L.str.14, 34
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Copy velocities back to host: %d\n"
.size .L.str.15, 34
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Malloc device time: %f\n"
.size .L.str.16, 24
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Copy to device time: %f\n"
.size .L.str.17, 25
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Calc time: %f\n"
.size .L.str.18, 15
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Copy to host time: %f\n"
.size .L.str.19, 23
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Total time: %f\n"
.size .L.str.20, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi"
.size .L__unnamed_1, 58
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi"
.size .L__unnamed_2, 57
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Useage: nbody num_timesteps"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "'planets.txt' not found. Exiting"
.size .Lstr.1, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym num_planets
.addrsig_sym velocities_d
.addrsig_sym planets_d
.addrsig_sym _ZZ8walltimevE1t
.addrsig_sym _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001432aa_00000000-6_nbody_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Useage: nbody num_timesteps\n"
.text
.globl _Z10parse_argsiPPc
.type _Z10parse_argsiPPc, @function
_Z10parse_argsiPPc:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cmpl $2, %edi
jne .L6
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, num_timesteps(%rip)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10parse_argsiPPc, .-_Z10parse_argsiPPc
.globl _Z8walltimev
.type _Z8walltimev, @function
_Z8walltimev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZZ8walltimevE1t(%rip), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8+_ZZ8walltimevE1t(%rip), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm1
addsd %xmm1, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8walltimev, .-_Z8walltimev
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "planets.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "'planets.txt' not found. Exiting\n"
.section .rodata.str1.1
.LC5:
.string "%d"
.LC6:
.string "%f %f %f %f %f"
.text
.globl _Z12read_planetsv
.type _Z12read_planetsv, @function
_Z12read_planetsv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $216, %rsp
.cfi_def_cfa_offset 256
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
testq %rax, %rax
je .L16
movq %rax, %r12
movq %rsp, %rbx
movq %rax, %rcx
movl $200, %edx
movl $200, %esi
movq %rbx, %rdi
call __fgets_chk@PLT
leaq num_planets(%rip), %rdx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
movl num_planets(%rip), %ebp
movslq %ebp, %rbx
movq %rbx, %rdi
salq $4, %rdi
call malloc@PLT
movq %rax, planets(%rip)
leaq 0(,%rbx,8), %rdi
call malloc@PLT
movq %rax, velocities(%rip)
testl %ebp, %ebp
jle .L11
movl $0, %ebx
leaq .LC6(%rip), %r13
.L12:
movq %rsp, %rbp
movq %r12, %rcx
movl $200, %edx
movl $200, %esi
movq %rbp, %rdi
call __fgets_chk@PLT
movq %rbx, %rdx
salq $4, %rdx
addq planets(%rip), %rdx
movq velocities(%rip), %rax
leaq (%rax,%rbx,8), %r8
leaq 4(%rdx), %rcx
subq $8, %rsp
.cfi_def_cfa_offset 264
leaq 8(%rdx), %rax
pushq %rax
.cfi_def_cfa_offset 272
leaq 4(%r8), %r9
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_sscanf@PLT
addq $1, %rbx
movq %rbp, %rsp
.cfi_def_cfa_offset 256
cmpl %ebx, num_planets(%rip)
jg .L12
.L11:
movq %r12, %rdi
call fclose@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z12read_planetsv, .-_Z12read_planetsv
.section .rodata.str1.1
.LC7:
.string "wr+"
.LC8:
.string "%f %f %f %f %f\n"
.text
.globl _Z13write_planetsi
.type _Z13write_planetsi, @function
_Z13write_planetsi:
.LFB2060:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movabsq $6877969034917276784, %rax
movabsq $32783537689359727, %rdx
movq %rax, (%rsp)
movq %rdx, 8(%rsp)
leaq .LC7(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
cmpl $0, num_planets(%rip)
jle .L19
movl $0, %ebx
leaq .LC8(%rip), %r12
.L20:
movq %rbx, %rax
salq $4, %rax
addq planets(%rip), %rax
movq velocities(%rip), %rdx
leaq (%rdx,%rbx,8), %rdx
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
pxor %xmm4, %xmm4
cvtss2sd 8(%rax), %xmm4
pxor %xmm3, %xmm3
cvtss2sd 4(%rdx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd (%rdx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rax), %xmm1
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $5, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, num_planets(%rip)
jg .L20
.L19:
movq %rbp, %rdi
call fclose@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z13write_planetsi, .-_Z13write_planetsi
.globl _Z32calculate_velocity_change_planet6float4S_
.type _Z32calculate_velocity_change_planet6float4S_, @function
_Z32calculate_velocity_change_planet6float4S_:
.LFB2061:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2061:
.size _Z32calculate_velocity_change_planet6float4S_, .-_Z32calculate_velocity_change_planet6float4S_
.globl _Z31calculate_velocity_change_block6float4PS_
.type _Z31calculate_velocity_change_block6float4PS_, @function
_Z31calculate_velocity_change_block6float4PS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z31calculate_velocity_change_block6float4PS_, .-_Z31calculate_velocity_change_block6float4PS_
.globl _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
.type _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i, @function
_Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17update_velocitiesP6float4P6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i, .-_Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
.globl _Z17update_velocitiesP6float4P6float2i
.type _Z17update_velocitiesP6float4P6float2i, @function
_Z17update_velocitiesP6float4P6float2i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z17update_velocitiesP6float4P6float2i, .-_Z17update_velocitiesP6float4P6float2i
.globl _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
.type _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i, @function
_Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16update_positionsP6float4P6float2i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i, .-_Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
.globl _Z16update_positionsP6float4P6float2i
.type _Z16update_positionsP6float4P6float2i, @function
_Z16update_positionsP6float4P6float2i:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z16update_positionsP6float4P6float2i, .-_Z16update_positionsP6float4P6float2i
.section .rodata.str1.1
.LC9:
.string "Malloc: %d\n"
.LC10:
.string "Copy planets to device: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Copy to velocities to device: %d\n"
.align 8
.LC12:
.string "update_velocities error - Step: %d CUDA Code: %d\n"
.align 8
.LC13:
.string "update_positions errror - Step: %d CUDA Code: %d\n"
.align 8
.LC14:
.string "Copy to planets back to host: %d\n"
.align 8
.LC15:
.string "Copy velocities back to host: %d\n"
.section .rodata.str1.1
.LC16:
.string "Malloc device time: %f\n"
.LC17:
.string "Copy to device time: %f\n"
.LC18:
.string "Calc time: %f\n"
.LC19:
.string "Copy to host time: %f\n"
.LC20:
.string "Total time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
call _Z10parse_argsiPPc
call _Z12read_planetsv
call _Z8walltimev
movsd %xmm0, 8(%rsp)
movslq num_planets(%rip), %rsi
salq $4, %rsi
leaq planets_d(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L60
.L46:
movslq num_planets(%rip), %rsi
salq $3, %rsi
leaq velocities_d(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L61
.L47:
call _Z8walltimev
movsd %xmm0, 16(%rsp)
movslq num_planets(%rip), %rdx
salq $4, %rdx
movl $1, %ecx
movq planets(%rip), %rsi
movq planets_d(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L62
.L48:
movslq num_planets(%rip), %rdx
salq $3, %rdx
movl $1, %ecx
movq velocities(%rip), %rsi
movq velocities_d(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L63
.L49:
call _Z8walltimev
movsd %xmm0, 24(%rsp)
movl num_planets(%rip), %edx
testb $31, %dl
setne %bpl
movzbl %bpl, %ebp
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl %eax, %ebp
cmpl $0, num_timesteps(%rip)
jle .L50
movl $0, %ebx
leaq .LC12(%rip), %r13
leaq .LC13(%rip), %r12
jmp .L55
.L60:
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L46
.L61:
movl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L62:
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L48
.L63:
movl %eax, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L49
.L64:
movl num_planets(%rip), %edx
movq velocities_d(%rip), %rsi
movq planets_d(%rip), %rdi
call _Z52__device_stub__Z17update_velocitiesP6float4P6float2iP6float4P6float2i
jmp .L51
.L65:
movl %eax, %ecx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L52
.L66:
movl num_planets(%rip), %edx
movq velocities_d(%rip), %rsi
movq planets_d(%rip), %rdi
call _Z51__device_stub__Z16update_positionsP6float4P6float2iP6float4P6float2i
jmp .L53
.L54:
call cudaThreadSynchronize@PLT
addl $1, %ebx
cmpl %ebx, num_timesteps(%rip)
jle .L50
.L55:
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L51:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L65
.L52:
call cudaThreadSynchronize@PLT
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L53:
call cudaGetLastError@PLT
testl %eax, %eax
je .L54
movl %eax, %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L50:
call _Z8walltimev
movsd %xmm0, 32(%rsp)
movslq num_planets(%rip), %rdx
salq $4, %rdx
movl $2, %ecx
movq planets_d(%rip), %rsi
movq planets(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L67
.L56:
movslq num_planets(%rip), %rdx
salq $3, %rdx
movl $2, %ecx
movq velocities_d(%rip), %rsi
movq velocities(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L68
.L57:
movq planets_d(%rip), %rdi
call cudaFree@PLT
movq velocities_d(%rip), %rdi
call cudaFree@PLT
call _Z8walltimev
movsd %xmm0, 40(%rsp)
call cudaDeviceSynchronize@PLT
movsd 16(%rsp), %xmm1
subsd 8(%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm2
subsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 32(%rsp), %xmm3
subsd 24(%rsp), %xmm3
movapd %xmm3, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 40(%rsp), %xmm0
subsd 32(%rsp), %xmm0
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z8walltimev
subsd 8(%rsp), %xmm0
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl num_timesteps(%rip), %edi
call _Z13write_planetsi
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl %eax, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L56
.L68:
movl %eax, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L57
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC21:
.string "_Z16update_positionsP6float4P6float2i"
.align 8
.LC22:
.string "_Z17update_velocitiesP6float4P6float2i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z16update_positionsP6float4P6float2i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z17update_velocitiesP6float4P6float2i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ8walltimevE1t
.comm _ZZ8walltimevE1t,16,16
.globl planets_d
.bss
.align 8
.type planets_d, @object
.size planets_d, 8
planets_d:
.zero 8
.globl velocities_d
.align 8
.type velocities_d, @object
.size velocities_d, 8
velocities_d:
.zero 8
.globl planets
.align 8
.type planets, @object
.size planets, 8
planets:
.zero 8
.globl velocities
.align 8
.type velocities, @object
.size velocities, 8
velocities:
.zero 8
.globl num_timesteps
.align 4
.type num_timesteps, @object
.size num_timesteps, 4
num_timesteps:
.zero 4
.globl num_planets
.align 4
.type num_planets, @object
.size num_planets, 4
num_planets:
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nbody_cuda.hip"
.globl _Z10parse_argsiPPc # -- Begin function _Z10parse_argsiPPc
.p2align 4, 0x90
.type _Z10parse_argsiPPc,@function
_Z10parse_argsiPPc: # @_Z10parse_argsiPPc
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpl $2, %edi
jne .LBB0_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, num_timesteps(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z10parse_argsiPPc, .Lfunc_end0-_Z10parse_argsiPPc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8walltimev
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z8walltimev
.p2align 4, 0x90
.type _Z8walltimev,@function
_Z8walltimev: # @_Z8walltimev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm1
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8walltimev, .Lfunc_end1-_Z8walltimev
.cfi_endproc
# -- End function
.globl _Z12read_planetsv # -- Begin function _Z12read_planetsv
.p2align 4, 0x90
.type _Z12read_planetsv,@function
_Z12read_planetsv: # @_Z12read_planetsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $224, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
testq %rax, %rax
je .LBB2_5
# %bb.1:
movq %rax, %rbx
leaq 16(%rsp), %r14
movq %r14, %rdi
movl $200, %esi
movq %rax, %rdx
callq fgets
movl $.L.str.4, %esi
movl $num_planets, %edx
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_sscanf
movslq num_planets(%rip), %r14
movq %r14, %rdi
shlq $4, %rdi
callq malloc
movq %rax, planets(%rip)
shlq $3, %r14
movq %r14, %rdi
callq malloc
movq %rax, velocities(%rip)
cmpl $0, num_planets(%rip)
jle .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl $4, %r15d
movl $8, %r12d
leaq 16(%rsp), %r14
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $200, %esi
movq %rbx, %rdx
callq fgets
movq planets(%rip), %rax
leaq (%rax,%r12), %rsi
leaq (%rax,%r12), %rdx
addq $-8, %rdx
leaq (%rax,%r12), %rcx
addq $-4, %rcx
movq velocities(%rip), %r9
leaq (%r9,%r15), %r8
addq $-4, %r8
addq %r15, %r9
movq %rsi, (%rsp)
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_sscanf
incq %r13
movslq num_planets(%rip), %rax
addq $8, %r15
addq $16, %r12
cmpq %rax, %r13
jl .LBB2_3
.LBB2_4: # %._crit_edge
movq %rbx, %rdi
callq fclose
addq $224, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_5:
.cfi_def_cfa_offset 272
movl $.Lstr.1, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z12read_planetsv, .Lfunc_end2-_Z12read_planetsv
.cfi_endproc
# -- End function
.globl _Z13write_planetsi # -- Begin function _Z13write_planetsi
.p2align 4, 0x90
.type _Z13write_planetsi,@function
_Z13write_planetsi: # @_Z13write_planetsi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movaps .L.str.6(%rip), %xmm0
movaps %xmm0, (%rsp)
movq %rsp, %rdi
movl $.L.str.7, %esi
callq fopen
movq %rax, %rbx
cmpl $0, num_planets(%rip)
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl $4, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq planets(%rip), %rax
movss -8(%rax,%r14,2), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss -4(%rax,%r14,2), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq velocities(%rip), %rcx
movss -4(%rcx,%r14), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%rcx,%r14), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movss (%rax,%r14,2), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
movl $.L.str.8, %esi
movq %rbx, %rdi
movb $5, %al
callq fprintf
incq %r15
movslq num_planets(%rip), %rax
addq $8, %r14
cmpq %rax, %r15
jl .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rdi
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end3:
.size _Z13write_planetsi, .Lfunc_end3-_Z13write_planetsi
.cfi_endproc
# -- End function
.globl _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi # -- Begin function _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 4, 0x90
.type _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@function
_Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi: # @_Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, .Lfunc_end4-_Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi # -- Begin function _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 4, 0x90
.type _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@function
_Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi: # @_Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, .Lfunc_end5-_Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB6_28
# %bb.1: # %_Z10parse_argsiPPc.exit
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, num_timesteps(%rip)
callq _Z12read_planetsv
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movslq num_planets(%rip), %rsi
shlq $4, %rsi
movl $planets_d, %edi
callq hipMalloc
testl %eax, %eax
je .LBB6_3
# %bb.2:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_3:
movslq num_planets(%rip), %rsi
shlq $3, %rsi
movl $velocities_d, %edi
callq hipMalloc
testl %eax, %eax
je .LBB6_5
# %bb.4:
movl $.L.str.9, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_5:
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq planets_d(%rip), %rdi
movq planets(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $4, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_7
# %bb.6:
movl $.L.str.10, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_7:
movq velocities_d(%rip), %rdi
movq velocities(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $3, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_9
# %bb.8:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_9:
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
cmpl $0, num_timesteps(%rip)
jle .LBB6_20
# %bb.10: # %.lr.ph
movabsq $4294967328, %rbx # imm = 0x100000020
movl num_planets(%rip), %eax
movl %eax, %ecx
andl $31, %ecx
leal 31(%rax), %edx
testl %eax, %eax
cmovnsl %eax, %edx
sarl $5, %edx
cmpl $1, %ecx
sbbl $-1, %edx
leaq (%rdx,%rbx), %r14
addq $-32, %r14
leaq 136(%rsp), %r13
leaq 128(%rsp), %rbp
leaq 96(%rsp), %r15
xorl %r12d, %r12d
jmp .LBB6_11
.p2align 4, 0x90
.LBB6_19: # in Loop: Header=BB6_11 Depth=1
callq hipDeviceSynchronize
incl %r12d
cmpl num_timesteps(%rip), %r12d
jge .LBB6_20
.LBB6_11: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_13
# %bb.12: # in Loop: Header=BB6_11 Depth=1
movq planets_d(%rip), %rax
movq velocities_d(%rip), %rcx
movl num_planets(%rip), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
movq %r15, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_13: # in Loop: Header=BB6_11 Depth=1
callq hipGetLastError
testl %eax, %eax
je .LBB6_15
# %bb.14: # in Loop: Header=BB6_11 Depth=1
movl $.L.str.12, %edi
movl %r12d, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
.LBB6_15: # in Loop: Header=BB6_11 Depth=1
callq hipDeviceSynchronize
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_17
# %bb.16: # in Loop: Header=BB6_11 Depth=1
movq planets_d(%rip), %rax
movq velocities_d(%rip), %rcx
movl num_planets(%rip), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %edi
movq %r15, %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_17: # in Loop: Header=BB6_11 Depth=1
callq hipGetLastError
testl %eax, %eax
je .LBB6_19
# %bb.18: # in Loop: Header=BB6_11 Depth=1
movl $.L.str.13, %edi
movl %r12d, %esi
movl %eax, %edx
xorl %eax, %eax
callq printf
jmp .LBB6_19
.LBB6_20: # %._crit_edge
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
movsd %xmm0, 144(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq planets(%rip), %rdi
movq planets_d(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $4, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_22
# %bb.21:
movl $.L.str.14, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_22:
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 160(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 152(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 144(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq velocities(%rip), %rdi
movq velocities_d(%rip), %rsi
movslq num_planets(%rip), %rdx
shlq $3, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB6_24
# %bb.23:
movl $.L.str.15, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB6_24:
movq planets_d(%rip), %rdi
callq hipFree
movq velocities_d(%rip), %rdi
callq hipFree
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.16, %edi
movb $1, %al
callq printf
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.17, %edi
movb $1, %al
callq printf
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.18, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.19, %edi
movb $1, %al
callq printf
movl $_ZZ8walltimevE1t, %edi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq _ZZ8walltimevE1t(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq _ZZ8walltimevE1t+8(%rip), %xmm0
mulsd .LCPI6_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.20, %edi
movb $1, %al
callq printf
movaps .L.str.6(%rip), %xmm0
movaps %xmm0, 96(%rsp)
leaq 96(%rsp), %rdi
movl $.L.str.7, %esi
callq fopen
movq %rax, %rbx
cmpl $0, num_planets(%rip)
jle .LBB6_27
# %bb.25: # %.lr.ph.i.preheader
movl $8, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_26: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq planets(%rip), %rax
movss -8(%rax,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss -4(%rax,%r14), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movq velocities(%rip), %rcx
movss (%rcx,%r15,8), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 4(%rcx,%r15,8), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movss (%rax,%r14), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
movl $.L.str.8, %esi
movq %rbx, %rdi
movb $5, %al
callq fprintf
incq %r15
movslq num_planets(%rip), %rax
addq $16, %r14
cmpq %rax, %r15
jl .LBB6_26
.LBB6_27: # %_Z13write_planetsi.exit
movq %rbx, %rdi
callq fclose
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_28:
.cfi_def_cfa_offset 224
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type num_planets,@object # @num_planets
.bss
.globl num_planets
.p2align 2, 0x0
num_planets:
.long 0 # 0x0
.size num_planets, 4
.type num_timesteps,@object # @num_timesteps
.globl num_timesteps
.p2align 2, 0x0
num_timesteps:
.long 0 # 0x0
.size num_timesteps, 4
.type velocities,@object # @velocities
.globl velocities
.p2align 3, 0x0
velocities:
.quad 0
.size velocities, 8
.type planets,@object # @planets
.globl planets
.p2align 3, 0x0
planets:
.quad 0
.size planets, 8
.type velocities_d,@object # @velocities_d
.globl velocities_d
.p2align 3, 0x0
velocities_d:
.quad 0
.size velocities_d, 8
.type planets_d,@object # @planets_d
.globl planets_d
.p2align 3, 0x0
planets_d:
.quad 0
.size planets_d, 8
.type _ZZ8walltimevE1t,@object # @_ZZ8walltimevE1t
.local _ZZ8walltimevE1t
.comm _ZZ8walltimevE1t,16,8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "planets.txt"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f %f %f %f %f"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.section .rodata.str1.16,"aMS",@progbits,1
.p2align 4, 0x0
.L.str.6:
.asciz "planets_out.txt"
.size .L.str.6, 16
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "wr+"
.size .L.str.7, 4
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%f %f %f %f %f\n"
.size .L.str.8, 16
.type _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@object # @_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.section .rodata,"a",@progbits
.globl _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 3, 0x0
_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi:
.quad _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.size _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, 8
.type _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi,@object # @_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.globl _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.p2align 3, 0x0
_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi:
.quad _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.size _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "Malloc: %d\n"
.size .L.str.9, 12
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Copy planets to device: %d\n"
.size .L.str.10, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Copy to velocities to device: %d\n"
.size .L.str.11, 34
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "update_velocities error - Step: %d CUDA Code: %d\n"
.size .L.str.12, 50
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "update_positions errror - Step: %d CUDA Code: %d\n"
.size .L.str.13, 50
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Copy to planets back to host: %d\n"
.size .L.str.14, 34
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Copy velocities back to host: %d\n"
.size .L.str.15, 34
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Malloc device time: %f\n"
.size .L.str.16, 24
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Copy to device time: %f\n"
.size .L.str.17, 25
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Calc time: %f\n"
.size .L.str.18, 15
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "Copy to host time: %f\n"
.size .L.str.19, 23
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "Total time: %f\n"
.size .L.str.20, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi"
.size .L__unnamed_1, 58
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi"
.size .L__unnamed_2, 57
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Useage: nbody num_timesteps"
.size .Lstr, 28
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "'planets.txt' not found. Exiting"
.size .Lstr.1, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym _Z31__device_stub__update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym num_planets
.addrsig_sym velocities_d
.addrsig_sym planets_d
.addrsig_sym _ZZ8walltimevE1t
.addrsig_sym _Z17update_velocitiesP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym _Z16update_positionsP15HIP_vector_typeIfLj4EEPS_IfLj2EEi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void rotate(int *a, int size) {
/*@ ghost int a0[];
requires size == blockDim.x;
requires \forall i; a[i] == a0[i];
ensures \forall i; 0 < i && i < size - 1 -> a[i] == a0[i - 1];
ensures a[0] == a0[size - 1] */
int tmp = a[threadIdx.x];
int t = threadIdx.x + 1;
if (t == size) t = 0;
__syncthreads();
a[t] = tmp;
} | code for sm_80
Function : _Z6rotatePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0005 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc60007ffe0ff */
/*0070*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0080*/ ISETP.NE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f05270 */
/*0090*/ SEL R4, R0, RZ, P0 ; /* 0x000000ff00047207 */
/* 0x000fca0000000000 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void rotate(int *a, int size) {
/*@ ghost int a0[];
requires size == blockDim.x;
requires \forall i; a[i] == a0[i];
ensures \forall i; 0 < i && i < size - 1 -> a[i] == a0[i - 1];
ensures a[0] == a0[size - 1] */
int tmp = a[threadIdx.x];
int t = threadIdx.x + 1;
if (t == size) t = 0;
__syncthreads();
a[t] = tmp;
} | .file "tmpxft_00114ad1_00000000-6_rotate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6rotatePiiPii
.type _Z26__device_stub__Z6rotatePiiPii, @function
_Z26__device_stub__Z6rotatePiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6rotatePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6rotatePiiPii, .-_Z26__device_stub__Z6rotatePiiPii
.globl _Z6rotatePii
.type _Z6rotatePii, @function
_Z6rotatePii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6rotatePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6rotatePii, .-_Z6rotatePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6rotatePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rotatePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void rotate(int *a, int size) {
/*@ ghost int a0[];
requires size == blockDim.x;
requires \forall i; a[i] == a0[i];
ensures \forall i; 0 < i && i < size - 1 -> a[i] == a0[i - 1];
ensures a[0] == a0[size - 1] */
int tmp = a[threadIdx.x];
int t = threadIdx.x + 1;
if (t == size) t = 0;
__syncthreads();
a[t] = tmp;
} | #include <hip/hip_runtime.h>
__global__ void rotate(int *a, int size) {
/*@ ghost int a0[];
requires size == blockDim.x;
requires \forall i; a[i] == a0[i];
ensures \forall i; 0 < i && i < size - 1 -> a[i] == a0[i - 1];
ensures a[0] == a0[size - 1] */
int tmp = a[threadIdx.x];
int t = threadIdx.x + 1;
if (t == size) t = 0;
__syncthreads();
a[t] = tmp;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void rotate(int *a, int size) {
/*@ ghost int a0[];
requires size == blockDim.x;
requires \forall i; a[i] == a0[i];
ensures \forall i; 0 < i && i < size - 1 -> a[i] == a0[i - 1];
ensures a[0] == a0[size - 1] */
int tmp = a[threadIdx.x];
int t = threadIdx.x + 1;
if (t == size) t = 0;
__syncthreads();
a[t] = tmp;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6rotatePii
.globl _Z6rotatePii
.p2align 8
.type _Z6rotatePii,@function
_Z6rotatePii:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x8
v_add_nc_u32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s0, v0
s_barrier
buffer_gl0_inv
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6rotatePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6rotatePii, .Lfunc_end0-_Z6rotatePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6rotatePii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6rotatePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void rotate(int *a, int size) {
/*@ ghost int a0[];
requires size == blockDim.x;
requires \forall i; a[i] == a0[i];
ensures \forall i; 0 < i && i < size - 1 -> a[i] == a0[i - 1];
ensures a[0] == a0[size - 1] */
int tmp = a[threadIdx.x];
int t = threadIdx.x + 1;
if (t == size) t = 0;
__syncthreads();
a[t] = tmp;
} | .text
.file "rotate.hip"
.globl _Z21__device_stub__rotatePii # -- Begin function _Z21__device_stub__rotatePii
.p2align 4, 0x90
.type _Z21__device_stub__rotatePii,@function
_Z21__device_stub__rotatePii: # @_Z21__device_stub__rotatePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6rotatePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__rotatePii, .Lfunc_end0-_Z21__device_stub__rotatePii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rotatePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6rotatePii,@object # @_Z6rotatePii
.section .rodata,"a",@progbits
.globl _Z6rotatePii
.p2align 3, 0x0
_Z6rotatePii:
.quad _Z21__device_stub__rotatePii
.size _Z6rotatePii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6rotatePii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__rotatePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6rotatePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6rotatePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fcc00078e0005 */
/*0050*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc60007ffe0ff */
/*0070*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0080*/ ISETP.NE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f05270 */
/*0090*/ SEL R4, R0, RZ, P0 ; /* 0x000000ff00047207 */
/* 0x000fca0000000000 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6rotatePii
.globl _Z6rotatePii
.p2align 8
.type _Z6rotatePii,@function
_Z6rotatePii:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x8
v_add_nc_u32_e32 v0, 1, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, s0, v0
s_barrier
buffer_gl0_inv
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6rotatePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6rotatePii, .Lfunc_end0-_Z6rotatePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6rotatePii
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z6rotatePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00114ad1_00000000-6_rotate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6rotatePiiPii
.type _Z26__device_stub__Z6rotatePiiPii, @function
_Z26__device_stub__Z6rotatePiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6rotatePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6rotatePiiPii, .-_Z26__device_stub__Z6rotatePiiPii
.globl _Z6rotatePii
.type _Z6rotatePii, @function
_Z6rotatePii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6rotatePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6rotatePii, .-_Z6rotatePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6rotatePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6rotatePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rotate.hip"
.globl _Z21__device_stub__rotatePii # -- Begin function _Z21__device_stub__rotatePii
.p2align 4, 0x90
.type _Z21__device_stub__rotatePii,@function
_Z21__device_stub__rotatePii: # @_Z21__device_stub__rotatePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6rotatePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__rotatePii, .Lfunc_end0-_Z21__device_stub__rotatePii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6rotatePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6rotatePii,@object # @_Z6rotatePii
.section .rodata,"a",@progbits
.globl _Z6rotatePii
.p2align 3, 0x0
_Z6rotatePii:
.quad _Z21__device_stub__rotatePii
.size _Z6rotatePii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6rotatePii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__rotatePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6rotatePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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