system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016c1d7_00000000-6_HPC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6squarePiS_S_PiS_S_
.type _Z29__device_stub__Z6squarePiS_S_PiS_S_, @function
_Z29__device_stub__Z6squarePiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6squarePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6squarePiS_S_PiS_S_, .-_Z29__device_stub__Z6squarePiS_S_PiS_S_
.globl _Z6squarePiS_S_
.type _Z6squarePiS_S_, @function
_Z6squarePiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6squarePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePiS_S_, .-_Z6squarePiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $2, (%rsp)
movl $10, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl (%rsp), %eax
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl 4(%rsp), %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6squarePiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "HPC.hip"
.globl _Z21__device_stub__squarePiS_S_ # -- Begin function _Z21__device_stub__squarePiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__squarePiS_S_,@function
_Z21__device_stub__squarePiS_S_: # @_Z21__device_stub__squarePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePiS_S_, .Lfunc_end0-_Z21__device_stub__squarePiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $2, 4(%rsp)
movl $10, (%rsp)
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl (%rsp), %edi
movl 4(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6squarePiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePiS_S_,@object # @_Z6squarePiS_S_
.section .rodata,"a",@progbits
.globl _Z6squarePiS_S_
.p2align 3, 0x0
_Z6squarePiS_S_:
.quad _Z21__device_stub__squarePiS_S_
.size _Z6squarePiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cudaDRectifier_propagate_kernel(double* x, double* y, unsigned int size, double leakSlope, int shifting, double clipping)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride) {
double value = x[i];
if (shifting > 0)
value /= (1 << shifting);
else if (shifting < 0)
value *= (1 << (-shifting));
if (clipping > 0.0)
y[i] = (value > 0.0) ? min(value, clipping) : leakSlope * value;
else
y[i] = (value > 0.0) ? value : leakSlope * value;
}
} | code for sm_80
Function : _Z31cudaDRectifier_propagate_kernelPdS_jdid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f01270 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @P0 BRA 0x510 ; /* 0x0000048000000947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fda0003f05270 */
/*00a0*/ @!P0 BRA 0x360 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*00b0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ DSETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff00762a */
/* 0x000e220003f01000 */
/*00d0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe4000fffe13f */
/*00e0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00f0*/ USHF.L.U32 UR4, UR5, UR4, URZ ; /* 0x0000000405047299 */
/* 0x000fd2000800063f */
/*0100*/ I2F.F64 R2, UR4 ; /* 0x0000000400027d12 */
/* 0x000e620008201c00 */
/*0110*/ @P0 BRA 0x210 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.WIDE.U32 R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e000b */
/*0140*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1b00 */
/*0150*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x006e0c0000000000 */
/*0160*/ DMUL R8, R6, c[0x0][0x178] ; /* 0x00005e0006087a28 */
/* 0x001fc80000000000 */
/*0170*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e0c0003f04000 */
/*0180*/ FSEL R8, R6, R8, P0 ; /* 0x0000000806087208 */
/* 0x001fe40000000000 */
/*0190*/ FSEL R9, R7, R9, P0 ; /* 0x0000000907097208 */
/* 0x000fe20000000000 */
/*01a0*/ IMAD.WIDE.U32 R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e000b */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*01c0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001e6000c101b06 */
/*01d0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*01f0*/ @!P0 BRA 0x120 ; /* 0xffffff2000008947 */
/* 0x001fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0005 */
/*0230*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*0240*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0c7624 */
/* 0x000fe200078e00ff */
/*0250*/ LEA R8, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000087a11 */
/* 0x001fe200078218ff */
/*0260*/ DMUL R10, R4, R2 ; /* 0x00000002040a7228 */
/* 0x0060640000000000 */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x001fc800078e00ff */
/*0280*/ DSETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x002e1c0003f04000 */
/*0290*/ @P0 DSETP.MIN.AND P2, P3, R10, c[0x0][0x188], PT ; /* 0x000062000a00062a */
/* 0x001e220003b40000 */
/*02a0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff060224 */
/* 0x000fe200078e000b */
/*02b0*/ @P0 LOP3.LUT R12, R12, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000c0c0812 */
/* 0x000fc800078efcff */
/*02c0*/ @P0 FSEL R9, R6, c[0x0][0x18c], P2 ; /* 0x0000630006090a08 */
/* 0x001fe20001000000 */
/*02d0*/ @!P0 DMUL R6, R10, c[0x0][0x178] ; /* 0x00005e000a068a28 */
/* 0x000e0c0000000000 */
/*02e0*/ @P0 SEL R7, R12, R9, P3 ; /* 0x000000090c070207 */
/* 0x000fe40001800000 */
/*02f0*/ LEA.HI.X R9, R0, c[0x0][0x16c], RZ, 0x3, P1 ; /* 0x00005b0000097a11 */
/* 0x000fe200008f1cff */
/*0300*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*0310*/ @P0 SEL R6, R10, c[0x0][0x188], P2 ; /* 0x000062000a060a07 */
/* 0x000fc80001000000 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0330*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011d8000c101b06 */
/*0340*/ @!P0 BRA 0x210 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ DSETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff00762a */
/* 0x000e080003f01000 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0007 */
/*0390*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000362000c1e1b00 */
/*03a0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e0007 */
/*03b0*/ @P0 BRA 0x420 ; /* 0x0000006000000947 */
/* 0x001fea0003800000 */
/*03c0*/ DMUL R2, R4, c[0x0][0x178] ; /* 0x00005e0004027a28 */
/* 0x022fc80000000000 */
/*03d0*/ DSETP.GT.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e0c0003f24000 */
/*03e0*/ FSEL R2, R4, R2, P1 ; /* 0x0000000204027208 */
/* 0x001fe40000800000 */
/*03f0*/ FSEL R3, R5, R3, P1 ; /* 0x0000000305037208 */
/* 0x000fca0000800000 */
/*0400*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0001e2000c101b06 */
/*0410*/ BRA 0x4c0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0420*/ DSETP.GT.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x020e220003f24000 */
/*0430*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff097624 */
/* 0x000fda00078e00ff */
/*0440*/ @P1 DSETP.MIN.AND P2, P3, R4.reuse, c[0x0][0x188], PT ; /* 0x000062000400162a */
/* 0x041e220003b40000 */
/*0450*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0005 */
/*0460*/ @P1 LOP3.LUT R9, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009091812 */
/* 0x000fe400078efcff */
/*0470*/ @!P1 DMUL R2, R4, c[0x0][0x178] ; /* 0x00005e0004029a28 */
/* 0x002e640000000000 */
/*0480*/ @P1 FSEL R8, R8, c[0x0][0x18c], P2 ; /* 0x0000630008081a08 */
/* 0x001fc80001000000 */
/*0490*/ @P1 SEL R2, R4, c[0x0][0x188], P2 ; /* 0x0000620004021a07 */
/* 0x000fe40001000000 */
/*04a0*/ @P1 SEL R3, R9, R8, P3 ; /* 0x0000000809031207 */
/* 0x000fca0001800000 */
/*04b0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0021e4000c101b06 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*04d0*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*04e0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f26070 */
/*04f0*/ @!P1 BRA 0x370 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ DSETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff00762a */
/* 0x000e220003f01000 */
/*0520*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0530*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe40000000800 */
/*0540*/ USHF.L.U32 UR4, UR4, UR5, URZ ; /* 0x0000000504047299 */
/* 0x000fd2000800063f */
/*0550*/ I2F.F64 R4, UR4 ; /* 0x0000000400047d12 */
/* 0x000e620008201c00 */
/*0560*/ @P0 BRA 0x7a0 ; /* 0x0000023000000947 */
/* 0x001fea0003800000 */
/*0570*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0590*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e220000001800 */
/*05b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*05c0*/ BSSY B0, 0x6e0 ; /* 0x0000011000007945 */
/* 0x000fea0003800000 */
/*05d0*/ DFMA R8, R6, -R4, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000804 */
/*05e0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*05f0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0600*/ DFMA R6, R8, -R4, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000804 */
/*0610*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e8c0000000008 */
/*0620*/ DMUL R8, R2, R6 ; /* 0x0000000602087228 */
/* 0x004e220000000000 */
/*0630*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fca0003f2e200 */
/*0640*/ DFMA R10, R8, -R4, R2 ; /* 0x80000004080a722b */
/* 0x001e0c0000000002 */
/*0650*/ DFMA R6, R6, R10, R8 ; /* 0x0000000a0606722b */
/* 0x001e140000000008 */
/*0660*/ FFMA R8, RZ, R5, R7 ; /* 0x00000005ff087223 */
/* 0x001fca0000000007 */
/*0670*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*0680*/ @P0 BRA P1, 0x6d0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*06a0*/ MOV R12, 0x6d0 ; /* 0x000006d0000c7802 */
/* 0x000fe20000000f00 */
/*06b0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*06c0*/ CALL.REL.NOINC 0xa20 ; /* 0x0000035000007944 */
/* 0x000fea0003c00000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ DMUL R2, R6, c[0x0][0x178] ; /* 0x00005e0006027a28 */
/* 0x000fe20000000000 */
/*06f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc600078e00ff */
/*0700*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e0c0003f04000 */
/*0710*/ FSEL R6, R6, R2, P0 ; /* 0x0000000206067208 */
/* 0x001fe40000000000 */
/*0720*/ FSEL R7, R7, R3, P0 ; /* 0x0000000307077208 */
/* 0x000fe20000000000 */
/*0730*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0009 */
/*0740*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0750*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0001e6000c101b06 */
/*0760*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0780*/ @!P0 BRA 0x570 ; /* 0xfffffde000008947 */
/* 0x001fea000383ffff */
/*0790*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x001fc800078e00ff */
/*07b0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*07c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*07d0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e220000001800 */
/*07e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*07f0*/ BSSY B0, 0x910 ; /* 0x0000011000007945 */
/* 0x000fea0003800000 */
/*0800*/ DFMA R8, R6, -R4, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000804 */
/*0810*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0820*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0830*/ DFMA R6, R8, -R4, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000804 */
/*0840*/ DFMA R10, R8, R6, R8 ; /* 0x00000006080a722b */
/* 0x001e8c0000000008 */
/*0850*/ DMUL R6, R2, R10 ; /* 0x0000000a02067228 */
/* 0x004e220000000000 */
/*0860*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fca0003f2e200 */
/*0870*/ DFMA R8, R6, -R4, R2 ; /* 0x800000040608722b */
/* 0x001e0c0000000002 */
/*0880*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */
/* 0x001e140000000006 */
/*0890*/ FFMA R8, RZ, R5, R7 ; /* 0x00000005ff087223 */
/* 0x001fca0000000007 */
/*08a0*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*08b0*/ @P0 BRA P1, 0x900 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*08c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*08d0*/ MOV R12, 0x900 ; /* 0x00000900000c7802 */
/* 0x000fe20000000f00 */
/*08e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*08f0*/ CALL.REL.NOINC 0xa20 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e220003f04000 */
/*0920*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0a7624 */
/* 0x000fe200078e00ff */
/*0930*/ LEA R8, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000087a11 */
/* 0x000fd800078218ff */
/*0940*/ @P0 DSETP.MIN.AND P2, P3, R6, c[0x0][0x188], PT ; /* 0x000062000600062a */
/* 0x001e220003b40000 */
/*0950*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff020224 */
/* 0x000fe200078e0007 */
/*0960*/ @P0 LOP3.LUT R10, R10, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000a0a0812 */
/* 0x000fc800078efcff */
/*0970*/ @P0 FSEL R9, R2, c[0x0][0x18c], P2 ; /* 0x0000630002090a08 */
/* 0x001fe20001000000 */
/*0980*/ @!P0 DMUL R2, R6, c[0x0][0x178] ; /* 0x00005e0006028a28 */
/* 0x0000640000000000 */
/*0990*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x001fc800078e00ff */
/*09a0*/ @P0 SEL R3, R10, R9, P3 ; /* 0x000000090a030207 */
/* 0x000fe40001800000 */
/*09b0*/ LEA.HI.X R9, R0, c[0x0][0x16c], RZ, 0x3, P1 ; /* 0x00005b0000097a11 */
/* 0x000fe200008f1cff */
/*09c0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*09d0*/ @P0 SEL R2, R6, c[0x0][0x188], P2 ; /* 0x0000620006020a07 */
/* 0x000fc80001000000 */
/*09e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*09f0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0021d8000c101b06 */
/*0a00*/ @!P0 BRA 0x7a0 ; /* 0xfffffd9000008947 */
/* 0x000fea000383ffff */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0a40*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe200078ec0ff */
/*0a50*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0a60*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x000fe200078ec0ff */
/*0a70*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0a80*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0a90*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0aa0*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*0ab0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0ac0*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x000fe200078ec0ff */
/*0ad0*/ BSSY B1, 0xfe0 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*0ae0*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e220000000000 */
/*0af0*/ ISETP.GE.U32.AND P1, PT, R13, R16, PT ; /* 0x000000100d00720c */
/* 0x000fc80003f26070 */
/*0b00*/ SEL R3, R14, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x000fe20004800000 */
/*0b10*/ MUFU.RCP64H R19, R7 ; /* 0x0000000700137308 */
/* 0x001e240000001800 */
/*0b20*/ @!P2 LOP3.LUT R2, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000902a812 */
/* 0x000fe200078ec0ff */
/*0b30*/ @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff16a224 */
/* 0x000fe200078e00ff */
/*0b40*/ LOP3.LUT R3, R3, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80b */
/*0b50*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0b60*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000a */
/*0b70*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0b80*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fe200078ef80b */
/*0b90*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x001e060000000806 */
/*0ba0*/ @!P2 LOP3.LUT R23, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f17a812 */
/* 0x000fe200078efcff */
/*0bb0*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000d */
/*0bc0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*0bd0*/ @!P2 DFMA R2, R2, 2, -R22 ; /* 0x400000000202a82b */
/* 0x0003e40000000816 */
/*0be0*/ IMAD.MOV.U32 R22, RZ, RZ, R16 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0010 */
/*0bf0*/ @!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007168812 */
/* 0x000fe200078ec0ff */
/*0c00*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x001e060000000012 */
/*0c10*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fc60007ffe0ff */
/*0c20*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x001e220000000806 */
/*0c30*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fca00078ec0ff */
/*0c40*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*0c50*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x001fc80007ffe0ff */
/*0c60*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0c70*/ DMUL R16, R18, R2 ; /* 0x0000000212107228 */
/* 0x002e060000000000 */
/*0c80*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fc60000704470 */
/*0c90*/ DFMA R20, R16, -R6, R2 ; /* 0x800000061014722b */
/* 0x001e0c0000000002 */
/*0ca0*/ DFMA R16, R18, R20, R16 ; /* 0x000000141210722b */
/* 0x0010480000000010 */
/*0cb0*/ @P0 BRA 0xe80 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x003fc800078ec0ff */
/*0cd0*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0ce0*/ IMAD.IADD R10, R13, 0x1, -R18 ; /* 0x000000010d0a7824 */
/* 0x000fc600078e0a12 */
/*0cf0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0d00*/ IMNMX R10, R10, -0x46a00000, !PT ; /* 0xb96000000a0a7817 */
/* 0x000fc80007800200 */
/*0d10*/ IMNMX R10, R10, 0x46a00000, PT ; /* 0x46a000000a0a7817 */
/* 0x000fca0003800200 */
/*0d20*/ IMAD.IADD R13, R10, 0x1, -R13 ; /* 0x000000010a0d7824 */
/* 0x000fe400078e0a0d */
/*0d30*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*0d40*/ IADD3 R11, R13, 0x7fe00000, RZ ; /* 0x7fe000000d0b7810 */
/* 0x000fcc0007ffe0ff */
/*0d50*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x000e140000000000 */
/*0d60*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0d70*/ @P0 BRA 0xfd0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0d80*/ DFMA R2, R16, -R6, R2 ; /* 0x800000061002722b */
/* 0x000e220000000002 */
/*0d90*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*0da0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0db0*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0dc0*/ LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ; /* 0x0000000b090b7212 */
/* 0x000fce00078efcff */
/*0dd0*/ @!P0 BRA 0xfd0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0de0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0df0*/ DMUL.RP R10, R16, R10 ; /* 0x0000000a100a7228 */
/* 0x000e220000008000 */
/*0e00*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0e10*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0e20*/ LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ; /* 0x000000090b097212 */
/* 0x001fc600078e3cff */
/*0e30*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0e40*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0e50*/ FSEL R18, R10, R18, !P0 ; /* 0x000000120a127208 */
/* 0x000fe40004000000 */
/*0e60*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0e70*/ BRA 0xfd0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0e80*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x003e1c0003f08000 */
/*0e90*/ @P0 BRA 0xfb0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0ea0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0eb0*/ @P0 BRA 0xf80 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0ec0*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0ed0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x000fe400078e00ff */
/*0ee0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0ef0*/ @!P0 BRA 0xfd0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0f00*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0f10*/ LOP3.LUT R19, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b137812 */
/* 0x000fe400078e4809 */
/*0f20*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0f30*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0f40*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0f50*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0f60*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0f70*/ BRA 0xfd0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0f80*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x000fe200078efcff */
/*0f90*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0fa0*/ BRA 0xfd0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b137812 */
/* 0x000fe200078efcff */
/*0fc0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000a */
/*0fd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0fe0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0ff0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*1000*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*1010*/ RET.REL.NODEC R12 0x0 ; /* 0xffffefe00c007950 */
/* 0x000fec0003c3ffff */
/*1020*/ BRA 0x1020; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cudaDRectifier_propagate_kernel(double* x, double* y, unsigned int size, double leakSlope, int shifting, double clipping)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride) {
double value = x[i];
if (shifting > 0)
value /= (1 << shifting);
else if (shifting < 0)
value *= (1 << (-shifting));
if (clipping > 0.0)
y[i] = (value > 0.0) ? min(value, clipping) : leakSlope * value;
else
y[i] = (value > 0.0) ? value : leakSlope * value;
}
} | .file "tmpxft_000c19a3_00000000-6_cudaDRectifier_propagate_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid
.type _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid, @function
_Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 24(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31cudaDRectifier_propagate_kernelPdS_jdid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid, .-_Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid
.globl _Z31cudaDRectifier_propagate_kernelPdS_jdid
.type _Z31cudaDRectifier_propagate_kernelPdS_jdid, @function
_Z31cudaDRectifier_propagate_kernelPdS_jdid:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31cudaDRectifier_propagate_kernelPdS_jdid, .-_Z31cudaDRectifier_propagate_kernelPdS_jdid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31cudaDRectifier_propagate_kernelPdS_jdid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31cudaDRectifier_propagate_kernelPdS_jdid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cudaDRectifier_propagate_kernel(double* x, double* y, unsigned int size, double leakSlope, int shifting, double clipping)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride) {
double value = x[i];
if (shifting > 0)
value /= (1 << shifting);
else if (shifting < 0)
value *= (1 << (-shifting));
if (clipping > 0.0)
y[i] = (value > 0.0) ? min(value, clipping) : leakSlope * value;
else
y[i] = (value > 0.0) ? value : leakSlope * value;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaDRectifier_propagate_kernel(double* x, double* y, unsigned int size, double leakSlope, int shifting, double clipping)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride) {
double value = x[i];
if (shifting > 0)
value /= (1 << shifting);
else if (shifting < 0)
value *= (1 << (-shifting));
if (clipping > 0.0)
y[i] = (value > 0.0) ? min(value, clipping) : leakSlope * value;
else
y[i] = (value > 0.0) ? value : leakSlope * value;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaDRectifier_propagate_kernel(double* x, double* y, unsigned int size, double leakSlope, int shifting, double clipping)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride) {
double value = x[i];
if (shifting > 0)
value /= (1 << shifting);
else if (shifting < 0)
value *= (1 << (-shifting));
if (clipping > 0.0)
y[i] = (value > 0.0) ? min(value, clipping) : leakSlope * value;
else
y[i] = (value > 0.0) ? value : leakSlope * value;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31cudaDRectifier_propagate_kernelPdS_jdid
.globl _Z31cudaDRectifier_propagate_kernelPdS_jdid
.p2align 8
.type _Z31cudaDRectifier_propagate_kernelPdS_jdid,@function
_Z31cudaDRectifier_propagate_kernelPdS_jdid:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_17
s_clause 0x1
s_load_b32 s6, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x28
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
v_cmp_ngt_f64_e64 s10, s[4:5], 0
s_cselect_b32 s9, -1, 0
s_cmp_lt_i32 s6, 0
v_max_f64 v[7:8], s[4:5], s[4:5]
s_cselect_b32 s11, -1, 0
s_sub_i32 s7, 0, s6
s_lshl_b32 s6, 1, s6
s_lshl_b32 s7, 1, s7
v_cvt_f64_i32_e32 v[3:4], s6
v_cvt_f64_i32_e32 v[5:6], s7
s_load_b32 s13, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_3:
v_add_nc_u32_e32 v1, s12, v1
v_add_co_u32 v9, s0, s6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_waitcnt vmcnt(0)
global_store_b64 v[9:10], v[13:14], off
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_17
.LBB0_4:
v_lshlrev_b64 v[9:10], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v10, vcc_lo
s_and_b32 vcc_lo, exec_lo, s9
global_load_b64 v[13:14], v[11:12], off
s_cbranch_vccz .LBB0_8
s_waitcnt vmcnt(0)
v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_7
v_mul_f64 v[11:12], v[13:14], v[5:6]
.LBB0_7:
s_cbranch_execz .LBB0_9
s_branch .LBB0_10
.LBB0_8:
.LBB0_9:
s_waitcnt vmcnt(0)
v_div_scale_f64 v[11:12], null, v[3:4], v[3:4], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[11:12], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[11:12], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_div_scale_f64 v[17:18], vcc_lo, v[13:14], v[3:4], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[17:18], v[15:16]
v_fma_f64 v[11:12], -v[11:12], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[19:20]
v_div_fixup_f64 v[11:12], v[11:12], v[3:4], v[13:14]
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e64 s1, 0, v[11:12]
v_cmp_nlt_f64_e64 s0, 0, v[11:12]
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccz .LBB0_12
v_mov_b32_e32 v0, 0x3ff00000
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, s2, 0, s1
v_cndmask_b32_e64 v14, s3, v0, s1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[13:14]
s_cbranch_execnz .LBB0_3
s_branch .LBB0_13
.LBB0_12:
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_15
s_waitcnt vmcnt(0)
v_mul_f64 v[13:14], v[11:12], s[2:3]
.LBB0_15:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
v_max_f64 v[11:12], v[11:12], v[11:12]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_f64 v[13:14], v[11:12], v[7:8]
s_branch .LBB0_2
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31cudaDRectifier_propagate_kernelPdS_jdid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31cudaDRectifier_propagate_kernelPdS_jdid, .Lfunc_end0-_Z31cudaDRectifier_propagate_kernelPdS_jdid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31cudaDRectifier_propagate_kernelPdS_jdid
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31cudaDRectifier_propagate_kernelPdS_jdid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaDRectifier_propagate_kernel(double* x, double* y, unsigned int size, double leakSlope, int shifting, double clipping)
{
const unsigned int index = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int stride = blockDim.x * gridDim.x;
for (unsigned int i = index; i < size; i += stride) {
double value = x[i];
if (shifting > 0)
value /= (1 << shifting);
else if (shifting < 0)
value *= (1 << (-shifting));
if (clipping > 0.0)
y[i] = (value > 0.0) ? min(value, clipping) : leakSlope * value;
else
y[i] = (value > 0.0) ? value : leakSlope * value;
}
} | .text
.file "cudaDRectifier_propagate_kernel.hip"
.globl _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid # -- Begin function _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.p2align 4, 0x90
.type _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid,@function
_Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid: # @_Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 72(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm1, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31cudaDRectifier_propagate_kernelPdS_jdid, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid, .Lfunc_end0-_Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31cudaDRectifier_propagate_kernelPdS_jdid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31cudaDRectifier_propagate_kernelPdS_jdid,@object # @_Z31cudaDRectifier_propagate_kernelPdS_jdid
.section .rodata,"a",@progbits
.globl _Z31cudaDRectifier_propagate_kernelPdS_jdid
.p2align 3, 0x0
_Z31cudaDRectifier_propagate_kernelPdS_jdid:
.quad _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.size _Z31cudaDRectifier_propagate_kernelPdS_jdid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31cudaDRectifier_propagate_kernelPdS_jdid"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31cudaDRectifier_propagate_kernelPdS_jdid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31cudaDRectifier_propagate_kernelPdS_jdid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f01270 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @P0 BRA 0x510 ; /* 0x0000048000000947 */
/* 0x000fea0003800000 */
/*0090*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fda0003f05270 */
/*00a0*/ @!P0 BRA 0x360 ; /* 0x000002b000008947 */
/* 0x000fea0003800000 */
/*00b0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ DSETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff00762a */
/* 0x000e220003f01000 */
/*00d0*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe4000fffe13f */
/*00e0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00f0*/ USHF.L.U32 UR4, UR5, UR4, URZ ; /* 0x0000000405047299 */
/* 0x000fd2000800063f */
/*0100*/ I2F.F64 R2, UR4 ; /* 0x0000000400027d12 */
/* 0x000e620008201c00 */
/*0110*/ @P0 BRA 0x210 ; /* 0x000000f000000947 */
/* 0x001fea0003800000 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.WIDE.U32 R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e000b */
/*0140*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea4000c1e1b00 */
/*0150*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x006e0c0000000000 */
/*0160*/ DMUL R8, R6, c[0x0][0x178] ; /* 0x00005e0006087a28 */
/* 0x001fc80000000000 */
/*0170*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e0c0003f04000 */
/*0180*/ FSEL R8, R6, R8, P0 ; /* 0x0000000806087208 */
/* 0x001fe40000000000 */
/*0190*/ FSEL R9, R7, R9, P0 ; /* 0x0000000907097208 */
/* 0x000fe20000000000 */
/*01a0*/ IMAD.WIDE.U32 R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e000b */
/*01b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0b7624 */
/* 0x000fe200078e00ff */
/*01c0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0001e6000c101b06 */
/*01d0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*01f0*/ @!P0 BRA 0x120 ; /* 0xffffff2000008947 */
/* 0x001fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0005 */
/*0230*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*0240*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0c7624 */
/* 0x000fe200078e00ff */
/*0250*/ LEA R8, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000087a11 */
/* 0x001fe200078218ff */
/*0260*/ DMUL R10, R4, R2 ; /* 0x00000002040a7228 */
/* 0x0060640000000000 */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x001fc800078e00ff */
/*0280*/ DSETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00722a */
/* 0x002e1c0003f04000 */
/*0290*/ @P0 DSETP.MIN.AND P2, P3, R10, c[0x0][0x188], PT ; /* 0x000062000a00062a */
/* 0x001e220003b40000 */
/*02a0*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff060224 */
/* 0x000fe200078e000b */
/*02b0*/ @P0 LOP3.LUT R12, R12, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000c0c0812 */
/* 0x000fc800078efcff */
/*02c0*/ @P0 FSEL R9, R6, c[0x0][0x18c], P2 ; /* 0x0000630006090a08 */
/* 0x001fe20001000000 */
/*02d0*/ @!P0 DMUL R6, R10, c[0x0][0x178] ; /* 0x00005e000a068a28 */
/* 0x000e0c0000000000 */
/*02e0*/ @P0 SEL R7, R12, R9, P3 ; /* 0x000000090c070207 */
/* 0x000fe40001800000 */
/*02f0*/ LEA.HI.X R9, R0, c[0x0][0x16c], RZ, 0x3, P1 ; /* 0x00005b0000097a11 */
/* 0x000fe200008f1cff */
/*0300*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*0310*/ @P0 SEL R6, R10, c[0x0][0x188], P2 ; /* 0x000062000a060a07 */
/* 0x000fc80001000000 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0330*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011d8000c101b06 */
/*0340*/ @!P0 BRA 0x210 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ DSETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff00762a */
/* 0x000e080003f01000 */
/*0370*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc800078e00ff */
/*0380*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0007 */
/*0390*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000362000c1e1b00 */
/*03a0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fe200078e0007 */
/*03b0*/ @P0 BRA 0x420 ; /* 0x0000006000000947 */
/* 0x001fea0003800000 */
/*03c0*/ DMUL R2, R4, c[0x0][0x178] ; /* 0x00005e0004027a28 */
/* 0x022fc80000000000 */
/*03d0*/ DSETP.GT.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x000e0c0003f24000 */
/*03e0*/ FSEL R2, R4, R2, P1 ; /* 0x0000000204027208 */
/* 0x001fe40000800000 */
/*03f0*/ FSEL R3, R5, R3, P1 ; /* 0x0000000305037208 */
/* 0x000fca0000800000 */
/*0400*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0001e2000c101b06 */
/*0410*/ BRA 0x4c0 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0420*/ DSETP.GT.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400722a */
/* 0x020e220003f24000 */
/*0430*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff097624 */
/* 0x000fda00078e00ff */
/*0440*/ @P1 DSETP.MIN.AND P2, P3, R4.reuse, c[0x0][0x188], PT ; /* 0x000062000400162a */
/* 0x041e220003b40000 */
/*0450*/ @P1 IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff081224 */
/* 0x000fe200078e0005 */
/*0460*/ @P1 LOP3.LUT R9, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009091812 */
/* 0x000fe400078efcff */
/*0470*/ @!P1 DMUL R2, R4, c[0x0][0x178] ; /* 0x00005e0004029a28 */
/* 0x002e640000000000 */
/*0480*/ @P1 FSEL R8, R8, c[0x0][0x18c], P2 ; /* 0x0000630008081a08 */
/* 0x001fc80001000000 */
/*0490*/ @P1 SEL R2, R4, c[0x0][0x188], P2 ; /* 0x0000620004021a07 */
/* 0x000fe40001000000 */
/*04a0*/ @P1 SEL R3, R9, R8, P3 ; /* 0x0000000809031207 */
/* 0x000fca0001800000 */
/*04b0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x0021e4000c101b06 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*04d0*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x000fca00078e0200 */
/*04e0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f26070 */
/*04f0*/ @!P1 BRA 0x370 ; /* 0xfffffe7000009947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ DSETP.LT.AND P0, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff00762a */
/* 0x000e220003f01000 */
/*0520*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0530*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe40000000800 */
/*0540*/ USHF.L.U32 UR4, UR4, UR5, URZ ; /* 0x0000000504047299 */
/* 0x000fd2000800063f */
/*0550*/ I2F.F64 R4, UR4 ; /* 0x0000000400047d12 */
/* 0x000e620008201c00 */
/*0560*/ @P0 BRA 0x7a0 ; /* 0x0000023000000947 */
/* 0x001fea0003800000 */
/*0570*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0580*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0590*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*05a0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e220000001800 */
/*05b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*05c0*/ BSSY B0, 0x6e0 ; /* 0x0000011000007945 */
/* 0x000fea0003800000 */
/*05d0*/ DFMA R8, R6, -R4, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000804 */
/*05e0*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*05f0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0600*/ DFMA R6, R8, -R4, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000804 */
/*0610*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x001e8c0000000008 */
/*0620*/ DMUL R8, R2, R6 ; /* 0x0000000602087228 */
/* 0x004e220000000000 */
/*0630*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fca0003f2e200 */
/*0640*/ DFMA R10, R8, -R4, R2 ; /* 0x80000004080a722b */
/* 0x001e0c0000000002 */
/*0650*/ DFMA R6, R6, R10, R8 ; /* 0x0000000a0606722b */
/* 0x001e140000000008 */
/*0660*/ FFMA R8, RZ, R5, R7 ; /* 0x00000005ff087223 */
/* 0x001fca0000000007 */
/*0670*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*0680*/ @P0 BRA P1, 0x6d0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0690*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*06a0*/ MOV R12, 0x6d0 ; /* 0x000006d0000c7802 */
/* 0x000fe20000000f00 */
/*06b0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*06c0*/ CALL.REL.NOINC 0xa20 ; /* 0x0000035000007944 */
/* 0x000fea0003c00000 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ DMUL R2, R6, c[0x0][0x178] ; /* 0x00005e0006027a28 */
/* 0x000fe20000000000 */
/*06f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc600078e00ff */
/*0700*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e0c0003f04000 */
/*0710*/ FSEL R6, R6, R2, P0 ; /* 0x0000000206067208 */
/* 0x001fe40000000000 */
/*0720*/ FSEL R7, R7, R3, P0 ; /* 0x0000000307077208 */
/* 0x000fe20000000000 */
/*0730*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0009 */
/*0740*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0750*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0001e6000c101b06 */
/*0760*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0780*/ @!P0 BRA 0x570 ; /* 0xfffffde000008947 */
/* 0x001fea000383ffff */
/*0790*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x001fc800078e00ff */
/*07b0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*07c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1b00 */
/*07d0*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x002e220000001800 */
/*07e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*07f0*/ BSSY B0, 0x910 ; /* 0x0000011000007945 */
/* 0x000fea0003800000 */
/*0800*/ DFMA R8, R6, -R4, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c0000000804 */
/*0810*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0820*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x001e0c0000000006 */
/*0830*/ DFMA R6, R8, -R4, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000804 */
/*0840*/ DFMA R10, R8, R6, R8 ; /* 0x00000006080a722b */
/* 0x001e8c0000000008 */
/*0850*/ DMUL R6, R2, R10 ; /* 0x0000000a02067228 */
/* 0x004e220000000000 */
/*0860*/ FSETP.GEU.AND P1, PT, |R3|, 6.5827683646048100446e-37, PT ; /* 0x036000000300780b */
/* 0x000fca0003f2e200 */
/*0870*/ DFMA R8, R6, -R4, R2 ; /* 0x800000040608722b */
/* 0x001e0c0000000002 */
/*0880*/ DFMA R6, R8, R10, R6 ; /* 0x0000000a0806722b */
/* 0x001e140000000006 */
/*0890*/ FFMA R8, RZ, R5, R7 ; /* 0x00000005ff087223 */
/* 0x001fca0000000007 */
/*08a0*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*08b0*/ @P0 BRA P1, 0x900 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*08c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*08d0*/ MOV R12, 0x900 ; /* 0x00000900000c7802 */
/* 0x000fe20000000f00 */
/*08e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*08f0*/ CALL.REL.NOINC 0xa20 ; /* 0x0000012000007944 */
/* 0x000fea0003c00000 */
/*0900*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0910*/ DSETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e220003f04000 */
/*0920*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0a7624 */
/* 0x000fe200078e00ff */
/*0930*/ LEA R8, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000087a11 */
/* 0x000fd800078218ff */
/*0940*/ @P0 DSETP.MIN.AND P2, P3, R6, c[0x0][0x188], PT ; /* 0x000062000600062a */
/* 0x001e220003b40000 */
/*0950*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff020224 */
/* 0x000fe200078e0007 */
/*0960*/ @P0 LOP3.LUT R10, R10, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000a0a0812 */
/* 0x000fc800078efcff */
/*0970*/ @P0 FSEL R9, R2, c[0x0][0x18c], P2 ; /* 0x0000630002090a08 */
/* 0x001fe20001000000 */
/*0980*/ @!P0 DMUL R2, R6, c[0x0][0x178] ; /* 0x00005e0006028a28 */
/* 0x0000640000000000 */
/*0990*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x001fc800078e00ff */
/*09a0*/ @P0 SEL R3, R10, R9, P3 ; /* 0x000000090a030207 */
/* 0x000fe40001800000 */
/*09b0*/ LEA.HI.X R9, R0, c[0x0][0x16c], RZ, 0x3, P1 ; /* 0x00005b0000097a11 */
/* 0x000fe200008f1cff */
/*09c0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*09d0*/ @P0 SEL R2, R6, c[0x0][0x188], P2 ; /* 0x0000620006020a07 */
/* 0x000fc80001000000 */
/*09e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*09f0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0021d8000c101b06 */
/*0a00*/ @!P0 BRA 0x7a0 ; /* 0xfffffd9000008947 */
/* 0x000fea000383ffff */
/*0a10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a20*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0003 */
/*0a40*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe200078ec0ff */
/*0a50*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0002 */
/*0a60*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x000fe200078ec0ff */
/*0a70*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0a80*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0a90*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0008 */
/*0aa0*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*0ab0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0ac0*/ LOP3.LUT R13, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0d7812 */
/* 0x000fe200078ec0ff */
/*0ad0*/ BSSY B1, 0xfe0 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*0ae0*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e220000000000 */
/*0af0*/ ISETP.GE.U32.AND P1, PT, R13, R16, PT ; /* 0x000000100d00720c */
/* 0x000fc80003f26070 */
/*0b00*/ SEL R3, R14, 0x63400000, !P1 ; /* 0x634000000e037807 */
/* 0x000fe20004800000 */
/*0b10*/ MUFU.RCP64H R19, R7 ; /* 0x0000000700137308 */
/* 0x001e240000001800 */
/*0b20*/ @!P2 LOP3.LUT R2, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000902a812 */
/* 0x000fe200078ec0ff */
/*0b30*/ @!P2 IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff16a224 */
/* 0x000fe200078e00ff */
/*0b40*/ LOP3.LUT R3, R3, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe400078ef80b */
/*0b50*/ @!P2 ISETP.GE.U32.AND P3, PT, R13, R2, PT ; /* 0x000000020d00a20c */
/* 0x000fe20003f66070 */
/*0b60*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000a */
/*0b70*/ @!P2 SEL R15, R14, 0x63400000, !P3 ; /* 0x634000000e0fa807 */
/* 0x000fc80005800000 */
/*0b80*/ @!P2 LOP3.LUT R15, R15, 0x80000000, R11, 0xf8, !PT ; /* 0x800000000f0fa812 */
/* 0x000fe200078ef80b */
/*0b90*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x001e060000000806 */
/*0ba0*/ @!P2 LOP3.LUT R23, R15, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000f17a812 */
/* 0x000fe200078efcff */
/*0bb0*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000d */
/*0bc0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*0bd0*/ @!P2 DFMA R2, R2, 2, -R22 ; /* 0x400000000202a82b */
/* 0x0003e40000000816 */
/*0be0*/ IMAD.MOV.U32 R22, RZ, RZ, R16 ; /* 0x000000ffff167224 */
/* 0x002fe200078e0010 */
/*0bf0*/ @!P0 LOP3.LUT R22, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007168812 */
/* 0x000fe200078ec0ff */
/*0c00*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x001e060000000012 */
/*0c10*/ IADD3 R23, R22, -0x1, RZ ; /* 0xffffffff16177810 */
/* 0x000fc60007ffe0ff */
/*0c20*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x001e220000000806 */
/*0c30*/ @!P2 LOP3.LUT R15, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000030fa812 */
/* 0x000fca00078ec0ff */
/*0c40*/ DFMA R18, R18, R20, R18 ; /* 0x000000141212722b */
/* 0x0010640000000012 */
/*0c50*/ IADD3 R20, R15, -0x1, RZ ; /* 0xffffffff0f147810 */
/* 0x001fc80007ffe0ff */
/*0c60*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fe20003f04070 */
/*0c70*/ DMUL R16, R18, R2 ; /* 0x0000000212107228 */
/* 0x002e060000000000 */
/*0c80*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fc60000704470 */
/*0c90*/ DFMA R20, R16, -R6, R2 ; /* 0x800000061014722b */
/* 0x001e0c0000000002 */
/*0ca0*/ DFMA R16, R18, R20, R16 ; /* 0x000000141210722b */
/* 0x0010480000000010 */
/*0cb0*/ @P0 BRA 0xe80 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x003fc800078ec0ff */
/*0cd0*/ ISETP.GE.U32.AND P0, PT, R13.reuse, R18, PT ; /* 0x000000120d00720c */
/* 0x040fe20003f06070 */
/*0ce0*/ IMAD.IADD R10, R13, 0x1, -R18 ; /* 0x000000010d0a7824 */
/* 0x000fc600078e0a12 */
/*0cf0*/ SEL R13, R14, 0x63400000, !P0 ; /* 0x634000000e0d7807 */
/* 0x000fe40004000000 */
/*0d00*/ IMNMX R10, R10, -0x46a00000, !PT ; /* 0xb96000000a0a7817 */
/* 0x000fc80007800200 */
/*0d10*/ IMNMX R10, R10, 0x46a00000, PT ; /* 0x46a000000a0a7817 */
/* 0x000fca0003800200 */
/*0d20*/ IMAD.IADD R13, R10, 0x1, -R13 ; /* 0x000000010a0d7824 */
/* 0x000fe400078e0a0d */
/*0d30*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*0d40*/ IADD3 R11, R13, 0x7fe00000, RZ ; /* 0x7fe000000d0b7810 */
/* 0x000fcc0007ffe0ff */
/*0d50*/ DMUL R18, R16, R10 ; /* 0x0000000a10127228 */
/* 0x000e140000000000 */
/*0d60*/ FSETP.GTU.AND P0, PT, |R19|, 1.469367938527859385e-39, PT ; /* 0x001000001300780b */
/* 0x001fda0003f0c200 */
/*0d70*/ @P0 BRA 0xfd0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0d80*/ DFMA R2, R16, -R6, R2 ; /* 0x800000061002722b */
/* 0x000e220000000002 */
/*0d90*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*0da0*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0db0*/ LOP3.LUT R9, R3, 0x80000000, R9, 0x48, !PT ; /* 0x8000000003097812 */
/* 0x000fc800078e4809 */
/*0dc0*/ LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ; /* 0x0000000b090b7212 */
/* 0x000fce00078efcff */
/*0dd0*/ @!P0 BRA 0xfd0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0de0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0d */
/*0df0*/ DMUL.RP R10, R16, R10 ; /* 0x0000000a100a7228 */
/* 0x000e220000008000 */
/*0e00*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0e10*/ DFMA R2, R18, -R2, R16 ; /* 0x800000021202722b */
/* 0x000e460000000010 */
/*0e20*/ LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ; /* 0x000000090b097212 */
/* 0x001fc600078e3cff */
/*0e30*/ IADD3 R2, -R13, -0x43300000, RZ ; /* 0xbcd000000d027810 */
/* 0x002fc80007ffe1ff */
/*0e40*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0e50*/ FSEL R18, R10, R18, !P0 ; /* 0x000000120a127208 */
/* 0x000fe40004000000 */
/*0e60*/ FSEL R19, R9, R19, !P0 ; /* 0x0000001309137208 */
/* 0x000fe20004000000 */
/*0e70*/ BRA 0xfd0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0e80*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x003e1c0003f08000 */
/*0e90*/ @P0 BRA 0xfb0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0ea0*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0eb0*/ @P0 BRA 0xf80 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0ec0*/ ISETP.NE.AND P0, PT, R15, R22, PT ; /* 0x000000160f00720c */
/* 0x000fe20003f05270 */
/*0ed0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x0 ; /* 0x00000000ff127424 */
/* 0x000fe400078e00ff */
/*0ee0*/ IMAD.MOV.U32 R19, RZ, RZ, -0x80000 ; /* 0xfff80000ff137424 */
/* 0x000fd400078e00ff */
/*0ef0*/ @!P0 BRA 0xfd0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0f00*/ ISETP.NE.AND P0, PT, R15, 0x7ff00000, PT ; /* 0x7ff000000f00780c */
/* 0x000fe40003f05270 */
/*0f10*/ LOP3.LUT R19, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b137812 */
/* 0x000fe400078e4809 */
/*0f20*/ ISETP.EQ.OR P0, PT, R22, RZ, !P0 ; /* 0x000000ff1600720c */
/* 0x000fda0004702670 */
/*0f30*/ @P0 LOP3.LUT R2, R19, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000013020812 */
/* 0x000fe200078efcff */
/*0f40*/ @!P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff128224 */
/* 0x000fe400078e00ff */
/*0f50*/ @P0 IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff120224 */
/* 0x000fe400078e00ff */
/*0f60*/ @P0 IMAD.MOV.U32 R19, RZ, RZ, R2 ; /* 0x000000ffff130224 */
/* 0x000fe200078e0002 */
/*0f70*/ BRA 0xfd0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0f80*/ LOP3.LUT R19, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000009137812 */
/* 0x000fe200078efcff */
/*0f90*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0008 */
/*0fa0*/ BRA 0xfd0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0fb0*/ LOP3.LUT R19, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b137812 */
/* 0x000fe200078efcff */
/*0fc0*/ IMAD.MOV.U32 R18, RZ, RZ, R10 ; /* 0x000000ffff127224 */
/* 0x000fe400078e000a */
/*0fd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0fe0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*0ff0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0012 */
/*1000*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0013 */
/*1010*/ RET.REL.NODEC R12 0x0 ; /* 0xffffefe00c007950 */
/* 0x000fec0003c3ffff */
/*1020*/ BRA 0x1020; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31cudaDRectifier_propagate_kernelPdS_jdid
.globl _Z31cudaDRectifier_propagate_kernelPdS_jdid
.p2align 8
.type _Z31cudaDRectifier_propagate_kernelPdS_jdid,@function
_Z31cudaDRectifier_propagate_kernelPdS_jdid:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_17
s_clause 0x1
s_load_b32 s6, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x28
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 1
v_cmp_ngt_f64_e64 s10, s[4:5], 0
s_cselect_b32 s9, -1, 0
s_cmp_lt_i32 s6, 0
v_max_f64 v[7:8], s[4:5], s[4:5]
s_cselect_b32 s11, -1, 0
s_sub_i32 s7, 0, s6
s_lshl_b32 s6, 1, s6
s_lshl_b32 s7, 1, s7
v_cvt_f64_i32_e32 v[3:4], s6
v_cvt_f64_i32_e32 v[5:6], s7
s_load_b32 s13, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_3:
v_add_nc_u32_e32 v1, s12, v1
v_add_co_u32 v9, s0, s6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v10, s0, s7, v10, s0
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_waitcnt vmcnt(0)
global_store_b64 v[9:10], v[13:14], off
s_or_b32 s13, vcc_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_17
.LBB0_4:
v_lshlrev_b64 v[9:10], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v10, vcc_lo
s_and_b32 vcc_lo, exec_lo, s9
global_load_b64 v[13:14], v[11:12], off
s_cbranch_vccz .LBB0_8
s_waitcnt vmcnt(0)
v_dual_mov_b32 v11, v13 :: v_dual_mov_b32 v12, v14
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_7
v_mul_f64 v[11:12], v[13:14], v[5:6]
.LBB0_7:
s_cbranch_execz .LBB0_9
s_branch .LBB0_10
.LBB0_8:
.LBB0_9:
s_waitcnt vmcnt(0)
v_div_scale_f64 v[11:12], null, v[3:4], v[3:4], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[11:12], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[11:12], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_div_scale_f64 v[17:18], vcc_lo, v[13:14], v[3:4], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[17:18], v[15:16]
v_fma_f64 v[11:12], -v[11:12], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[19:20]
v_div_fixup_f64 v[11:12], v[11:12], v[3:4], v[13:14]
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e64 s1, 0, v[11:12]
v_cmp_nlt_f64_e64 s0, 0, v[11:12]
s_and_b32 vcc_lo, exec_lo, s10
s_cbranch_vccz .LBB0_12
v_mov_b32_e32 v0, 0x3ff00000
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, s2, 0, s1
v_cndmask_b32_e64 v14, s3, v0, s1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[13:14]
s_cbranch_execnz .LBB0_3
s_branch .LBB0_13
.LBB0_12:
.LBB0_13:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s0, exec_lo, s1
s_cbranch_execz .LBB0_15
s_waitcnt vmcnt(0)
v_mul_f64 v[13:14], v[11:12], s[2:3]
.LBB0_15:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
v_max_f64 v[11:12], v[11:12], v[11:12]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_f64 v[13:14], v[11:12], v[7:8]
s_branch .LBB0_2
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31cudaDRectifier_propagate_kernelPdS_jdid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31cudaDRectifier_propagate_kernelPdS_jdid, .Lfunc_end0-_Z31cudaDRectifier_propagate_kernelPdS_jdid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31cudaDRectifier_propagate_kernelPdS_jdid
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31cudaDRectifier_propagate_kernelPdS_jdid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c19a3_00000000-6_cudaDRectifier_propagate_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid
.type _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid, @function
_Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movsd %xmm0, 16(%rsp)
movl %ecx, 24(%rsp)
movsd %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31cudaDRectifier_propagate_kernelPdS_jdid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid, .-_Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid
.globl _Z31cudaDRectifier_propagate_kernelPdS_jdid
.type _Z31cudaDRectifier_propagate_kernelPdS_jdid, @function
_Z31cudaDRectifier_propagate_kernelPdS_jdid:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z31cudaDRectifier_propagate_kernelPdS_jdidPdS_jdid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31cudaDRectifier_propagate_kernelPdS_jdid, .-_Z31cudaDRectifier_propagate_kernelPdS_jdid
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31cudaDRectifier_propagate_kernelPdS_jdid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31cudaDRectifier_propagate_kernelPdS_jdid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaDRectifier_propagate_kernel.hip"
.globl _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid # -- Begin function _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.p2align 4, 0x90
.type _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid,@function
_Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid: # @_Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movsd %xmm0, 72(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm1, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31cudaDRectifier_propagate_kernelPdS_jdid, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid, .Lfunc_end0-_Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31cudaDRectifier_propagate_kernelPdS_jdid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31cudaDRectifier_propagate_kernelPdS_jdid,@object # @_Z31cudaDRectifier_propagate_kernelPdS_jdid
.section .rodata,"a",@progbits
.globl _Z31cudaDRectifier_propagate_kernelPdS_jdid
.p2align 3, 0x0
_Z31cudaDRectifier_propagate_kernelPdS_jdid:
.quad _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.size _Z31cudaDRectifier_propagate_kernelPdS_jdid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31cudaDRectifier_propagate_kernelPdS_jdid"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__cudaDRectifier_propagate_kernelPdS_jdid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31cudaDRectifier_propagate_kernelPdS_jdid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrix_multiply_kernel(double *matrix, double *vector_in, double *vector_out, long dim_mn){
double out;
long i, j;
i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<dim_mn){
out = 0.;
for (j=0; j<dim_mn; j++){
out += matrix[i*dim_mn+j] * vector_in[j];
}
vector_out[i] = out;
}
} | code for sm_80
Function : _Z22matrix_multiply_kernelPdS_S_l
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06300 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff187624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*00a0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fc80003f06070 */
/*00c0*/ ISETP.GE.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06300 */
/*00d0*/ @!P0 BRA 0x590 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, P0, R24.reuse, -0x1, RZ ; /* 0xffffffff18037810 */
/* 0x040fe20007f1e0ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ; /* 0x0000000318187812 */
/* 0x000fe200078ec0ff */
/*0110*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0130*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0140*/ IADD3.X R2, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02027810 */
/* 0x000fe400007fe4ff */
/*0150*/ ISETP.NE.U32.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe40003f05070 */
/*0160*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fc40003f26110 */
/*0170*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0180*/ @!P1 BRA 0x3d0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a25 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R25, P1, R24, -c[0x0][0x178], RZ ; /* 0x80005e0018197a10 */
/* 0x000fe20007f3e0ff */
/*01b0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01d0*/ IMAD R5, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000057a24 */
/* 0x000fe200078e0203 */
/*01e0*/ LEA R3, P2, R2.reuse, c[0x0][0x160], 0x3 ; /* 0x0000580002037a11 */
/* 0x040fe200078418ff */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0200*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0210*/ IMAD.X R26, RZ, RZ, ~c[0x0][0x17c], P1 ; /* 0x80005f00ff1a7624 */
/* 0x000fe200008e06ff */
/*0220*/ LEA.HI.X R6, R2, c[0x0][0x164], R5, 0x3, P2 ; /* 0x0000590002067a11 */
/* 0x000fe200010f1c05 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R2, P2, R3, 0x10, RZ ; /* 0x0000001003027810 */
/* 0x000fca0007f5e0ff */
/*0250*/ IMAD.X R3, RZ, RZ, R6, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0606 */
/*0260*/ LDG.E.64 R20, [R4.64] ; /* 0x0000000804147981 */
/* 0x0000a8000c1e1b00 */
/*0270*/ LDG.E.64 R22, [R2.64+-0x10] ; /* 0xfffff00802167981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R6, [R4.64+0x8] ; /* 0x0000080804067981 */
/* 0x0000e8000c1e1b00 */
/*0290*/ LDG.E.64 R8, [R2.64+-0x8] ; /* 0xfffff80802087981 */
/* 0x000ee8000c1e1b00 */
/*02a0*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001008040a7981 */
/* 0x000128000c1e1b00 */
/*02b0*/ LDG.E.64 R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000328000c1e1b00 */
/*02c0*/ LDG.E.64 R14, [R4.64+0x18] ; /* 0x00001808040e7981 */
/* 0x000168000c1e1b00 */
/*02d0*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080802107981 */
/* 0x000362000c1e1b00 */
/*02e0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*02f0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0300*/ IADD3 R4, P3, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f7e0ff */
/*0310*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0320*/ DFMA R20, R20, R22, R18 ; /* 0x000000161414722b */
/* 0x0040e40000000012 */
/*0330*/ IADD3 R18, P2, R25, UR4, RZ ; /* 0x0000000419127c10 */
/* 0x001fc8000ff5e0ff */
/*0340*/ ISETP.NE.U32.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f25070 */
/*0350*/ DFMA R6, R6, R8, R20 ; /* 0x000000080606722b */
/* 0x0081240000000014 */
/*0360*/ IADD3.X R8, R26, UR5, RZ, P2, !PT ; /* 0x000000051a087c10 */
/* 0x001fe400097fe4ff */
/*0370*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x002fe40007f5e0ff */
/*0380*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fe20003f25310 */
/*0390*/ DFMA R6, R10, R12, R6 ; /* 0x0000000c0a06722b */
/* 0x010f640000000006 */
/*03a0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fc800010e0603 */
/*03b0*/ DFMA R18, R14, R16, R6 ; /* 0x000000100e12722b */
/* 0x02004c0000000006 */
/*03c0*/ @P1 BRA 0x260 ; /* 0xfffffe9000001947 */
/* 0x003fea000383ffff */
/*03d0*/ @!P0 BRA 0x590 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*03f0*/ IADD3 R24, P1, RZ, -R24, RZ ; /* 0x80000018ff187210 */
/* 0x000fe20007f3e0ff */
/*0400*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*0410*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0420*/ ULEA UR6, UP0, UR4, UR6, 0x3 ; /* 0x0000000604067291 */
/* 0x000fe2000f80183f */
/*0430*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x178], R2 ; /* 0x00005e0000027a25 */
/* 0x000fc600078e0002 */
/*0440*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ; /* 0x0000000704047291 */
/* 0x000fe200080f1c05 */
/*0450*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fe200078e0203 */
/*0460*/ LEA R7, P0, R2, c[0x0][0x160], 0x3 ; /* 0x0000580002077a11 */
/* 0x000fe200078018ff */
/*0470*/ IMAD.X R6, RZ, RZ, -0x1, P1 ; /* 0xffffffffff067424 */
/* 0x000fc600008e06ff */
/*0480*/ LEA.HI.X R8, R2, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590002087a11 */
/* 0x000fe400000f1c03 */
/*0490*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x001fe4000f8e00ff */
/*04a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe4000f8e00ff */
/*04b0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0007 */
/*04c0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0008 */
/*04d0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea8000c1e1b00 */
/*04e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1b00 */
/*04f0*/ IADD3 R24, P0, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fca0007f1e0ff */
/*0500*/ IMAD.X R6, RZ, RZ, R6, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e0606 */
/*0510*/ ISETP.NE.U32.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fc80003f05070 */
/*0520*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fe20003f05300 */
/*0530*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000ff1e03f */
/*0540*/ IADD3 R7, P1, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fc60007f3e0ff */
/*0550*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe400087fe43f */
/*0560*/ IMAD.X R8, RZ, RZ, R8, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0608 */
/*0570*/ DFMA R18, R2, R4, R18 ; /* 0x000000040212722b */
/* 0x00604a0000000012 */
/*0580*/ @P0 BRA 0x490 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0590*/ LEA R2, P0, R0, c[0x0][0x170], 0x3 ; /* 0x00005c0000027a11 */
/* 0x001fc800078018ff */
/*05a0*/ LEA.HI.X R3, R0, c[0x0][0x174], RZ, 0x3, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1cff */
/*05b0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b08 */
/*05c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05d0*/ BRA 0x5d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrix_multiply_kernel(double *matrix, double *vector_in, double *vector_out, long dim_mn){
double out;
long i, j;
i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<dim_mn){
out = 0.;
for (j=0; j<dim_mn; j++){
out += matrix[i*dim_mn+j] * vector_in[j];
}
vector_out[i] = out;
}
} | .file "tmpxft_000857be_00000000-6_matrix_multiply_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l
.type _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l, @function
_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22matrix_multiply_kernelPdS_S_l(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l, .-_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l
.globl _Z22matrix_multiply_kernelPdS_S_l
.type _Z22matrix_multiply_kernelPdS_S_l, @function
_Z22matrix_multiply_kernelPdS_S_l:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22matrix_multiply_kernelPdS_S_l, .-_Z22matrix_multiply_kernelPdS_S_l
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22matrix_multiply_kernelPdS_S_l"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrix_multiply_kernelPdS_S_l(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrix_multiply_kernel(double *matrix, double *vector_in, double *vector_out, long dim_mn){
double out;
long i, j;
i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<dim_mn){
out = 0.;
for (j=0; j<dim_mn; j++){
out += matrix[i*dim_mn+j] * vector_in[j];
}
vector_out[i] = out;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_multiply_kernel(double *matrix, double *vector_in, double *vector_out, long dim_mn){
double out;
long i, j;
i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<dim_mn){
out = 0.;
for (j=0; j<dim_mn; j++){
out += matrix[i*dim_mn+j] * vector_in[j];
}
vector_out[i] = out;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_multiply_kernel(double *matrix, double *vector_in, double *vector_out, long dim_mn){
double out;
long i, j;
i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<dim_mn){
out = 0.;
for (j=0; j<dim_mn; j++){
out += matrix[i*dim_mn+j] * vector_in[j];
}
vector_out[i] = out;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22matrix_multiply_kernelPdS_S_l
.globl _Z22matrix_multiply_kernelPdS_S_l
.p2align 8
.type _Z22matrix_multiply_kernelPdS_S_l,@function
_Z22matrix_multiply_kernelPdS_S_l:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_6
v_cmp_lt_i64_e64 s4, s[2:3], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_4
v_mad_u64_u32 v[3:4], null, v1, s2, 0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v4
v_mad_u64_u32 v[4:5], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[3:4]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.LBB0_3:
global_load_b64 v[7:8], v[5:6], off
s_load_b64 s[4:5], s[6:7], 0x0
v_add_co_u32 v5, vcc_lo, v5, 8
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_addc_u32 s3, s3, -1
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[7:8], s[4:5], v[3:4]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22matrix_multiply_kernelPdS_S_l
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22matrix_multiply_kernelPdS_S_l, .Lfunc_end0-_Z22matrix_multiply_kernelPdS_S_l
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22matrix_multiply_kernelPdS_S_l
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22matrix_multiply_kernelPdS_S_l.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrix_multiply_kernel(double *matrix, double *vector_in, double *vector_out, long dim_mn){
double out;
long i, j;
i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<dim_mn){
out = 0.;
for (j=0; j<dim_mn; j++){
out += matrix[i*dim_mn+j] * vector_in[j];
}
vector_out[i] = out;
}
} | .text
.file "matrix_multiply_kernel.hip"
.globl _Z37__device_stub__matrix_multiply_kernelPdS_S_l # -- Begin function _Z37__device_stub__matrix_multiply_kernelPdS_S_l
.p2align 4, 0x90
.type _Z37__device_stub__matrix_multiply_kernelPdS_S_l,@function
_Z37__device_stub__matrix_multiply_kernelPdS_S_l: # @_Z37__device_stub__matrix_multiply_kernelPdS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22matrix_multiply_kernelPdS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__matrix_multiply_kernelPdS_S_l, .Lfunc_end0-_Z37__device_stub__matrix_multiply_kernelPdS_S_l
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22matrix_multiply_kernelPdS_S_l, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22matrix_multiply_kernelPdS_S_l,@object # @_Z22matrix_multiply_kernelPdS_S_l
.section .rodata,"a",@progbits
.globl _Z22matrix_multiply_kernelPdS_S_l
.p2align 3, 0x0
_Z22matrix_multiply_kernelPdS_S_l:
.quad _Z37__device_stub__matrix_multiply_kernelPdS_S_l
.size _Z22matrix_multiply_kernelPdS_S_l, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22matrix_multiply_kernelPdS_S_l"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__matrix_multiply_kernelPdS_S_l
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22matrix_multiply_kernelPdS_S_l
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22matrix_multiply_kernelPdS_S_l
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x17c], PT, P0 ; /* 0x00005f00ff007a0c */
/* 0x000fda0003f06300 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R24, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff187624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*00a0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fc80003f06070 */
/*00c0*/ ISETP.GE.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f06300 */
/*00d0*/ @!P0 BRA 0x590 ; /* 0x000004b000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R3, P0, R24.reuse, -0x1, RZ ; /* 0xffffffff18037810 */
/* 0x040fe20007f1e0ff */
/*00f0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0100*/ LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ; /* 0x0000000318187812 */
/* 0x000fe200078ec0ff */
/*0110*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0130*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0140*/ IADD3.X R2, R2, -0x1, RZ, P0, !PT ; /* 0xffffffff02027810 */
/* 0x000fe400007fe4ff */
/*0150*/ ISETP.NE.U32.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe40003f05070 */
/*0160*/ ISETP.GE.U32.AND.EX P1, PT, R2, RZ, PT, P1 ; /* 0x000000ff0200720c */
/* 0x000fc40003f26110 */
/*0170*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*0180*/ @!P1 BRA 0x3d0 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a25 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R25, P1, R24, -c[0x0][0x178], RZ ; /* 0x80005e0018197a10 */
/* 0x000fe20007f3e0ff */
/*01b0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*01c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*01d0*/ IMAD R5, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000057a24 */
/* 0x000fe200078e0203 */
/*01e0*/ LEA R3, P2, R2.reuse, c[0x0][0x160], 0x3 ; /* 0x0000580002037a11 */
/* 0x040fe200078418ff */
/*01f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0200*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0210*/ IMAD.X R26, RZ, RZ, ~c[0x0][0x17c], P1 ; /* 0x80005f00ff1a7624 */
/* 0x000fe200008e06ff */
/*0220*/ LEA.HI.X R6, R2, c[0x0][0x164], R5, 0x3, P2 ; /* 0x0000590002067a11 */
/* 0x000fe200010f1c05 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0240*/ IADD3 R2, P2, R3, 0x10, RZ ; /* 0x0000001003027810 */
/* 0x000fca0007f5e0ff */
/*0250*/ IMAD.X R3, RZ, RZ, R6, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0606 */
/*0260*/ LDG.E.64 R20, [R4.64] ; /* 0x0000000804147981 */
/* 0x0000a8000c1e1b00 */
/*0270*/ LDG.E.64 R22, [R2.64+-0x10] ; /* 0xfffff00802167981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R6, [R4.64+0x8] ; /* 0x0000080804067981 */
/* 0x0000e8000c1e1b00 */
/*0290*/ LDG.E.64 R8, [R2.64+-0x8] ; /* 0xfffff80802087981 */
/* 0x000ee8000c1e1b00 */
/*02a0*/ LDG.E.64 R10, [R4.64+0x10] ; /* 0x00001008040a7981 */
/* 0x000128000c1e1b00 */
/*02b0*/ LDG.E.64 R12, [R2.64] ; /* 0x00000008020c7981 */
/* 0x000328000c1e1b00 */
/*02c0*/ LDG.E.64 R14, [R4.64+0x18] ; /* 0x00001808040e7981 */
/* 0x000168000c1e1b00 */
/*02d0*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080802107981 */
/* 0x000362000c1e1b00 */
/*02e0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*02f0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0300*/ IADD3 R4, P3, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fca0007f7e0ff */
/*0310*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe200018e0605 */
/*0320*/ DFMA R20, R20, R22, R18 ; /* 0x000000161414722b */
/* 0x0040e40000000012 */
/*0330*/ IADD3 R18, P2, R25, UR4, RZ ; /* 0x0000000419127c10 */
/* 0x001fc8000ff5e0ff */
/*0340*/ ISETP.NE.U32.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f25070 */
/*0350*/ DFMA R6, R6, R8, R20 ; /* 0x000000080606722b */
/* 0x0081240000000014 */
/*0360*/ IADD3.X R8, R26, UR5, RZ, P2, !PT ; /* 0x000000051a087c10 */
/* 0x001fe400097fe4ff */
/*0370*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x002fe40007f5e0ff */
/*0380*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fe20003f25310 */
/*0390*/ DFMA R6, R10, R12, R6 ; /* 0x0000000c0a06722b */
/* 0x010f640000000006 */
/*03a0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fc800010e0603 */
/*03b0*/ DFMA R18, R14, R16, R6 ; /* 0x000000100e12722b */
/* 0x02004c0000000006 */
/*03c0*/ @P1 BRA 0x260 ; /* 0xfffffe9000001947 */
/* 0x003fea000383ffff */
/*03d0*/ @!P0 BRA 0x590 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x000fe2000f8e00ff */
/*03f0*/ IADD3 R24, P1, RZ, -R24, RZ ; /* 0x80000018ff187210 */
/* 0x000fe20007f3e0ff */
/*0400*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fe2000f8e00ff */
/*0410*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0420*/ ULEA UR6, UP0, UR4, UR6, 0x3 ; /* 0x0000000604067291 */
/* 0x000fe2000f80183f */
/*0430*/ IMAD.WIDE.U32 R2, R0, c[0x0][0x178], R2 ; /* 0x00005e0000027a25 */
/* 0x000fc600078e0002 */
/*0440*/ ULEA.HI.X UR4, UR4, UR7, UR5, 0x3, UP0 ; /* 0x0000000704047291 */
/* 0x000fe200080f1c05 */
/*0450*/ IMAD R3, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000037a24 */
/* 0x000fe200078e0203 */
/*0460*/ LEA R7, P0, R2, c[0x0][0x160], 0x3 ; /* 0x0000580002077a11 */
/* 0x000fe200078018ff */
/*0470*/ IMAD.X R6, RZ, RZ, -0x1, P1 ; /* 0xffffffffff067424 */
/* 0x000fc600008e06ff */
/*0480*/ LEA.HI.X R8, R2, c[0x0][0x164], R3, 0x3, P0 ; /* 0x0000590002087a11 */
/* 0x000fe400000f1c03 */
/*0490*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x001fe4000f8e00ff */
/*04a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe4000f8e00ff */
/*04b0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0007 */
/*04c0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0008 */
/*04d0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea8000c1e1b00 */
/*04e0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000804047981 */
/* 0x000ea2000c1e1b00 */
/*04f0*/ IADD3 R24, P0, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fca0007f1e0ff */
/*0500*/ IMAD.X R6, RZ, RZ, R6, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e0606 */
/*0510*/ ISETP.NE.U32.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fc80003f05070 */
/*0520*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fe20003f05300 */
/*0530*/ UIADD3 UR6, UP0, UR6, 0x8, URZ ; /* 0x0000000806067890 */
/* 0x000fe2000ff1e03f */
/*0540*/ IADD3 R7, P1, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fc60007f3e0ff */
/*0550*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe400087fe43f */
/*0560*/ IMAD.X R8, RZ, RZ, R8, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0608 */
/*0570*/ DFMA R18, R2, R4, R18 ; /* 0x000000040212722b */
/* 0x00604a0000000012 */
/*0580*/ @P0 BRA 0x490 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0590*/ LEA R2, P0, R0, c[0x0][0x170], 0x3 ; /* 0x00005c0000027a11 */
/* 0x001fc800078018ff */
/*05a0*/ LEA.HI.X R3, R0, c[0x0][0x174], RZ, 0x3, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1cff */
/*05b0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b08 */
/*05c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05d0*/ BRA 0x5d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22matrix_multiply_kernelPdS_S_l
.globl _Z22matrix_multiply_kernelPdS_S_l
.p2align 8
.type _Z22matrix_multiply_kernelPdS_S_l,@function
_Z22matrix_multiply_kernelPdS_S_l:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_6
v_cmp_lt_i64_e64 s4, s[2:3], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_4
v_mad_u64_u32 v[3:4], null, v1, s2, 0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v4
v_mad_u64_u32 v[4:5], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[3:4]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.LBB0_3:
global_load_b64 v[7:8], v[5:6], off
s_load_b64 s[4:5], s[6:7], 0x0
v_add_co_u32 v5, vcc_lo, v5, 8
s_add_u32 s2, s2, -1
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_addc_u32 s3, s3, -1
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_lg_u64 s[2:3], 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[3:4], v[7:8], s[4:5], v[3:4]
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22matrix_multiply_kernelPdS_S_l
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22matrix_multiply_kernelPdS_S_l, .Lfunc_end0-_Z22matrix_multiply_kernelPdS_S_l
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22matrix_multiply_kernelPdS_S_l
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22matrix_multiply_kernelPdS_S_l.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000857be_00000000-6_matrix_multiply_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l
.type _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l, @function
_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22matrix_multiply_kernelPdS_S_l(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l, .-_Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l
.globl _Z22matrix_multiply_kernelPdS_S_l
.type _Z22matrix_multiply_kernelPdS_S_l, @function
_Z22matrix_multiply_kernelPdS_S_l:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z22matrix_multiply_kernelPdS_S_lPdS_S_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22matrix_multiply_kernelPdS_S_l, .-_Z22matrix_multiply_kernelPdS_S_l
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22matrix_multiply_kernelPdS_S_l"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matrix_multiply_kernelPdS_S_l(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_multiply_kernel.hip"
.globl _Z37__device_stub__matrix_multiply_kernelPdS_S_l # -- Begin function _Z37__device_stub__matrix_multiply_kernelPdS_S_l
.p2align 4, 0x90
.type _Z37__device_stub__matrix_multiply_kernelPdS_S_l,@function
_Z37__device_stub__matrix_multiply_kernelPdS_S_l: # @_Z37__device_stub__matrix_multiply_kernelPdS_S_l
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22matrix_multiply_kernelPdS_S_l, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__matrix_multiply_kernelPdS_S_l, .Lfunc_end0-_Z37__device_stub__matrix_multiply_kernelPdS_S_l
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22matrix_multiply_kernelPdS_S_l, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22matrix_multiply_kernelPdS_S_l,@object # @_Z22matrix_multiply_kernelPdS_S_l
.section .rodata,"a",@progbits
.globl _Z22matrix_multiply_kernelPdS_S_l
.p2align 3, 0x0
_Z22matrix_multiply_kernelPdS_S_l:
.quad _Z37__device_stub__matrix_multiply_kernelPdS_S_l
.size _Z22matrix_multiply_kernelPdS_S_l, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22matrix_multiply_kernelPdS_S_l"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__matrix_multiply_kernelPdS_S_l
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22matrix_multiply_kernelPdS_S_l
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <assert.h>
#include <cstdlib>
#include <cuda.h>
#include <cuda_runtime.h>
const int SIZE = 1024;
__global__ void transpose(int *V, int n) {
int Idx = blockDim.x * blockIdx.x + threadIdx.x;
if (Idx <= n/2) {
int tmp = V[Idx];
V[Idx] = V[n-Idx-1];
V[n-Idx-1] = tmp;
}
}
__global__ void static_trans(int *Vec, int N) {
__shared__ int array[SIZE];
int Idx = threadIdx.x; //we have only one block - condition
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
__global__ void dynamic_trans(int *Vec, int N) {
extern __shared__ int array[];
int Idx = threadIdx.x;
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
int main(int argc, char **argv) {
assert(argc==2);
int n = atoi(argv[1]);
size_t size = n * sizeof(int);
int *V = (int*)malloc(size);
int *V_t = (int*)malloc(size);
for (int i = 0; i < n; i++) {
V[i] = i;
}
int block = 1024;
int grid = 1;
// int grid = (n / 2 - 1) / block + 1;
int *V_dev;
cudaMalloc(&V_dev, size);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
transpose<<<grid, block>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Common time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//STATIC SHARED
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
static_trans<<<grid, block, n>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Static sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//DYNAMIC SHARED
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
dynamic_trans<<<grid, block, n>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Dynamic sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
free(V);
cudaFree(V_t);
return 0;
} | code for sm_80
Function : _Z13dynamic_transPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff047212 */
/* 0x000fc800078e33ff */
/*0070*/ IADD3 R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12static_transPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff047212 */
/* 0x000fc800078e33ff */
/*0070*/ IADD3 R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GT.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ LOP3.LUT R0, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff007212 */
/* 0x000fe200078e33ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IADD3 R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD.WIDE R4, R0, R3, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0203 */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1900 */
/*0110*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <assert.h>
#include <cstdlib>
#include <cuda.h>
#include <cuda_runtime.h>
const int SIZE = 1024;
__global__ void transpose(int *V, int n) {
int Idx = blockDim.x * blockIdx.x + threadIdx.x;
if (Idx <= n/2) {
int tmp = V[Idx];
V[Idx] = V[n-Idx-1];
V[n-Idx-1] = tmp;
}
}
__global__ void static_trans(int *Vec, int N) {
__shared__ int array[SIZE];
int Idx = threadIdx.x; //we have only one block - condition
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
__global__ void dynamic_trans(int *Vec, int N) {
extern __shared__ int array[];
int Idx = threadIdx.x;
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
int main(int argc, char **argv) {
assert(argc==2);
int n = atoi(argv[1]);
size_t size = n * sizeof(int);
int *V = (int*)malloc(size);
int *V_t = (int*)malloc(size);
for (int i = 0; i < n; i++) {
V[i] = i;
}
int block = 1024;
int grid = 1;
// int grid = (n / 2 - 1) / block + 1;
int *V_dev;
cudaMalloc(&V_dev, size);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
transpose<<<grid, block>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Common time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//STATIC SHARED
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
static_trans<<<grid, block, n>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Static sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//DYNAMIC SHARED
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
dynamic_trans<<<grid, block, n>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Dynamic sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
free(V);
cudaFree(V_t);
return 0;
} | .file "tmpxft_00134794_00000000-6_vec_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9transposePiiPii
.type _Z29__device_stub__Z9transposePiiPii, @function
_Z29__device_stub__Z9transposePiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z9transposePiiPii, .-_Z29__device_stub__Z9transposePiiPii
.globl _Z9transposePii
.type _Z9transposePii, @function
_Z9transposePii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9transposePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9transposePii, .-_Z9transposePii
.globl _Z33__device_stub__Z12static_transPiiPii
.type _Z33__device_stub__Z12static_transPiiPii, @function
_Z33__device_stub__Z12static_transPiiPii:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12static_transPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z33__device_stub__Z12static_transPiiPii, .-_Z33__device_stub__Z12static_transPiiPii
.globl _Z12static_transPii
.type _Z12static_transPii, @function
_Z12static_transPii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12static_transPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z12static_transPii, .-_Z12static_transPii
.globl _Z34__device_stub__Z13dynamic_transPiiPii
.type _Z34__device_stub__Z13dynamic_transPiiPii, @function
_Z34__device_stub__Z13dynamic_transPiiPii:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13dynamic_transPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z34__device_stub__Z13dynamic_transPiiPii, .-_Z34__device_stub__Z13dynamic_transPiiPii
.globl _Z13dynamic_transPii
.type _Z13dynamic_transPii, @function
_Z13dynamic_transPii:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13dynamic_transPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z13dynamic_transPii, .-_Z13dynamic_transPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Common time is: "
.LC2:
.string " "
.LC3:
.string "Static sh m time is: "
.LC4:
.string "Dynamic sh m time is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 12(%rsp)
cltq
movq %rax, (%rsp)
leaq 0(,%rax,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
testl %r12d, %r12d
jle .L28
leal -1(%r12), %ecx
movl $0, %eax
.L29:
movl %eax, 0(%rbp,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L29
.L28:
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L30:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L31
movq %r13, %rbx
leal -1(%r12), %eax
leaq 4(%r13,%rax,4), %r15
.L32:
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L32
.L31:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movq (%rsp), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L33:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L34
movq %r13, %rbx
leal -1(%r12), %eax
leaq 4(%r13,%rax,4), %r15
.L35:
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L35
.L34:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movq (%rsp), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L36:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L37
movq %r13, %rbx
leal -1(%r12), %eax
leaq 4(%r13,%rax,4), %r15
leaq _ZSt4cout(%rip), %r14
leaq .LC2(%rip), %r12
.L38:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L38
.L37:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z9transposePiiPii
jmp .L30
.L46:
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z12static_transPiiPii
jmp .L33
.L47:
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z13dynamic_transPiiPii
jmp .L36
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z13dynamic_transPii"
.LC6:
.string "_Z12static_transPii"
.LC7:
.string "_Z9transposePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dynamic_transPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12static_transPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <assert.h>
#include <cstdlib>
#include <cuda.h>
#include <cuda_runtime.h>
const int SIZE = 1024;
__global__ void transpose(int *V, int n) {
int Idx = blockDim.x * blockIdx.x + threadIdx.x;
if (Idx <= n/2) {
int tmp = V[Idx];
V[Idx] = V[n-Idx-1];
V[n-Idx-1] = tmp;
}
}
__global__ void static_trans(int *Vec, int N) {
__shared__ int array[SIZE];
int Idx = threadIdx.x; //we have only one block - condition
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
__global__ void dynamic_trans(int *Vec, int N) {
extern __shared__ int array[];
int Idx = threadIdx.x;
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
int main(int argc, char **argv) {
assert(argc==2);
int n = atoi(argv[1]);
size_t size = n * sizeof(int);
int *V = (int*)malloc(size);
int *V_t = (int*)malloc(size);
for (int i = 0; i < n; i++) {
V[i] = i;
}
int block = 1024;
int grid = 1;
// int grid = (n / 2 - 1) / block + 1;
int *V_dev;
cudaMalloc(&V_dev, size);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
transpose<<<grid, block>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Common time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//STATIC SHARED
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
static_trans<<<grid, block, n>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Static sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//DYNAMIC SHARED
cudaEventRecord(start);
cudaMemcpy(V_dev, V, size, cudaMemcpyHostToDevice);
dynamic_trans<<<grid, block, n>>>(V_dev, n);
cudaDeviceSynchronize();
cudaEventRecord(stop);
cudaMemcpy(V_t, V_dev, size, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
ms = 0;
cudaEventElapsedTime(&ms, start, stop);
std::cout << "Dynamic sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
free(V);
cudaFree(V_t);
return 0;
} | #include <iostream>
#include <assert.h>
#include <cstdlib>
#include <hip/hip_runtime.h>
const int SIZE = 1024;
__global__ void transpose(int *V, int n) {
int Idx = blockDim.x * blockIdx.x + threadIdx.x;
if (Idx <= n/2) {
int tmp = V[Idx];
V[Idx] = V[n-Idx-1];
V[n-Idx-1] = tmp;
}
}
__global__ void static_trans(int *Vec, int N) {
__shared__ int array[SIZE];
int Idx = threadIdx.x; //we have only one block - condition
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
__global__ void dynamic_trans(int *Vec, int N) {
extern __shared__ int array[];
int Idx = threadIdx.x;
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
int main(int argc, char **argv) {
assert(argc==2);
int n = atoi(argv[1]);
size_t size = n * sizeof(int);
int *V = (int*)malloc(size);
int *V_t = (int*)malloc(size);
for (int i = 0; i < n; i++) {
V[i] = i;
}
int block = 1024;
int grid = 1;
// int grid = (n / 2 - 1) / block + 1;
int *V_dev;
hipMalloc(&V_dev, size);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
transpose<<<grid, block>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Common time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//STATIC SHARED
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
static_trans<<<grid, block, n>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Static sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//DYNAMIC SHARED
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
dynamic_trans<<<grid, block, n>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Dynamic sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
free(V);
hipFree(V_t);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <assert.h>
#include <cstdlib>
#include <hip/hip_runtime.h>
const int SIZE = 1024;
__global__ void transpose(int *V, int n) {
int Idx = blockDim.x * blockIdx.x + threadIdx.x;
if (Idx <= n/2) {
int tmp = V[Idx];
V[Idx] = V[n-Idx-1];
V[n-Idx-1] = tmp;
}
}
__global__ void static_trans(int *Vec, int N) {
__shared__ int array[SIZE];
int Idx = threadIdx.x; //we have only one block - condition
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
__global__ void dynamic_trans(int *Vec, int N) {
extern __shared__ int array[];
int Idx = threadIdx.x;
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
int main(int argc, char **argv) {
assert(argc==2);
int n = atoi(argv[1]);
size_t size = n * sizeof(int);
int *V = (int*)malloc(size);
int *V_t = (int*)malloc(size);
for (int i = 0; i < n; i++) {
V[i] = i;
}
int block = 1024;
int grid = 1;
// int grid = (n / 2 - 1) / block + 1;
int *V_dev;
hipMalloc(&V_dev, size);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
transpose<<<grid, block>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Common time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//STATIC SHARED
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
static_trans<<<grid, block, n>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Static sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//DYNAMIC SHARED
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
dynamic_trans<<<grid, block, n>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Dynamic sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
free(V);
hipFree(V_t);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePii
.globl _Z9transposePii
.p2align 8
.type _Z9transposePii,@function
_Z9transposePii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshr_b32 s3, s2, 31
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_xad_u32 v3, v1, -1, s2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePii, .Lfunc_end0-_Z9transposePii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12static_transPii
.globl _Z12static_transPii
.p2align 8
.type _Z12static_transPii,@function
_Z12static_transPii:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x8
v_not_b32_e32 v0, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
v_add_lshl_u32 v0, v0, s0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12static_transPii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12static_transPii, .Lfunc_end1-_Z12static_transPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13dynamic_transPii
.globl _Z13dynamic_transPii
.p2align 8
.type _Z13dynamic_transPii,@function
_Z13dynamic_transPii:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0, v1
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
v_xad_u32 v0, v0, -1, s0
v_lshl_add_u32 v0, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13dynamic_transPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13dynamic_transPii, .Lfunc_end2-_Z13dynamic_transPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12static_transPii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z12static_transPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13dynamic_transPii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z13dynamic_transPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <assert.h>
#include <cstdlib>
#include <hip/hip_runtime.h>
const int SIZE = 1024;
__global__ void transpose(int *V, int n) {
int Idx = blockDim.x * blockIdx.x + threadIdx.x;
if (Idx <= n/2) {
int tmp = V[Idx];
V[Idx] = V[n-Idx-1];
V[n-Idx-1] = tmp;
}
}
__global__ void static_trans(int *Vec, int N) {
__shared__ int array[SIZE];
int Idx = threadIdx.x; //we have only one block - condition
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
__global__ void dynamic_trans(int *Vec, int N) {
extern __shared__ int array[];
int Idx = threadIdx.x;
array[Idx] = Vec[Idx];
__syncthreads();
Vec[Idx] = array[N-Idx-1];
}
int main(int argc, char **argv) {
assert(argc==2);
int n = atoi(argv[1]);
size_t size = n * sizeof(int);
int *V = (int*)malloc(size);
int *V_t = (int*)malloc(size);
for (int i = 0; i < n; i++) {
V[i] = i;
}
int block = 1024;
int grid = 1;
// int grid = (n / 2 - 1) / block + 1;
int *V_dev;
hipMalloc(&V_dev, size);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
transpose<<<grid, block>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Common time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//STATIC SHARED
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
static_trans<<<grid, block, n>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Static sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
/////////////////////////////////////////////////
//DYNAMIC SHARED
hipEventRecord(start);
hipMemcpy(V_dev, V, size, hipMemcpyHostToDevice);
dynamic_trans<<<grid, block, n>>>(V_dev, n);
hipDeviceSynchronize();
hipEventRecord(stop);
hipMemcpy(V_t, V_dev, size, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
ms = 0;
hipEventElapsedTime(&ms, start, stop);
std::cout << "Dynamic sh m time is: " << ms << std::endl;
for (int i = 0; i < n; i++) {
std::cout << V_t[i] << " ";
}
std::cout << std::endl;
free(V);
hipFree(V_t);
return 0;
} | .text
.file "vec_transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__transposePii # -- Begin function _Z24__device_stub__transposePii
.p2align 4, 0x90
.type _Z24__device_stub__transposePii,@function
_Z24__device_stub__transposePii: # @_Z24__device_stub__transposePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePii, .Lfunc_end0-_Z24__device_stub__transposePii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__static_transPii # -- Begin function _Z27__device_stub__static_transPii
.p2align 4, 0x90
.type _Z27__device_stub__static_transPii,@function
_Z27__device_stub__static_transPii: # @_Z27__device_stub__static_transPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12static_transPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__static_transPii, .Lfunc_end1-_Z27__device_stub__static_transPii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__dynamic_transPii # -- Begin function _Z28__device_stub__dynamic_transPii
.p2align 4, 0x90
.type _Z28__device_stub__dynamic_transPii,@function
_Z28__device_stub__dynamic_transPii: # @_Z28__device_stub__dynamic_transPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13dynamic_transPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__dynamic_transPii, .Lfunc_end2-_Z28__device_stub__dynamic_transPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movslq %r15d, %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r13, 128(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
movabsq $4294967297, %r13 # imm = 0x100000001
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 1023(%r13), %rdx
movq %r13, %rdi
movl $1, %esi
movq %rdx, 120(%rsp) # 8-byte Spill
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9transposePii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB3_8
# %bb.7:
movzbl 67(%r13), %eax
jmp .LBB3_9
.LBB3_8:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_12
# %bb.10: # %.lr.ph120.preheader
movl %r15d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_11: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r13
jne .LBB3_11
.LBB3_12: # %._crit_edge121
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i79
cmpb $0, 56(%r13)
je .LBB3_15
# %bb.14:
movzbl 67(%r13), %eax
jmp .LBB3_16
.LBB3_15:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit82
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
movq 128(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.17:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12static_transPii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_18:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB3_43
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
cmpb $0, 56(%r13)
je .LBB3_21
# %bb.20:
movzbl 67(%r13), %ecx
jmp .LBB3_22
.LBB3_21:
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit87
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_25
# %bb.23: # %.lr.ph123.preheader
movl %r15d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_24: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r13
jne .LBB3_24
.LBB3_25: # %._crit_edge124
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r13)
je .LBB3_28
# %bb.27:
movzbl 67(%r13), %eax
jmp .LBB3_29
.LBB3_28:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
movq 128(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_31
# %bb.30:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13dynamic_transPii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_31:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB3_43
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r12)
je .LBB3_34
# %bb.33:
movzbl 67(%r12), %ecx
jmp .LBB3_35
.LBB3_34:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB3_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_38
# %bb.36: # %.lr.ph126.preheader
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_37: # %.lr.ph126
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB3_37
.LBB3_38: # %._crit_edge127
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_43
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
cmpb $0, 56(%r15)
je .LBB3_41
# %bb.40:
movzbl 67(%r15), %eax
jmp .LBB3_42
.LBB3_41:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_43:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12static_transPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dynamic_transPii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePii,@object # @_Z9transposePii
.section .rodata,"a",@progbits
.globl _Z9transposePii
.p2align 3, 0x0
_Z9transposePii:
.quad _Z24__device_stub__transposePii
.size _Z9transposePii, 8
.type _Z12static_transPii,@object # @_Z12static_transPii
.globl _Z12static_transPii
.p2align 3, 0x0
_Z12static_transPii:
.quad _Z27__device_stub__static_transPii
.size _Z12static_transPii, 8
.type _Z13dynamic_transPii,@object # @_Z13dynamic_transPii
.globl _Z13dynamic_transPii
.p2align 3, 0x0
_Z13dynamic_transPii:
.quad _Z28__device_stub__dynamic_transPii
.size _Z13dynamic_transPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Common time is: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Static sh m time is: "
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Dynamic sh m time is: "
.size .L.str.3, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12static_transPii"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13dynamic_transPii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePii
.addrsig_sym _Z27__device_stub__static_transPii
.addrsig_sym _Z28__device_stub__dynamic_transPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePii
.addrsig_sym _Z12static_transPii
.addrsig_sym _Z13dynamic_transPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13dynamic_transPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff047212 */
/* 0x000fc800078e33ff */
/*0070*/ IADD3 R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12static_transPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff047212 */
/* 0x000fc800078e33ff */
/*0070*/ IADD3 R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0060*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GT.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fda000bf04270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ LOP3.LUT R0, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff007212 */
/* 0x000fe200078e33ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IADD3 R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD.WIDE R4, R0, R3, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0203 */
/*00e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*00f0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1900 */
/*0110*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101904 */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePii
.globl _Z9transposePii
.p2align 8
.type _Z9transposePii,@function
_Z9transposePii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshr_b32 s3, s2, 31
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_xad_u32 v3, v1, -1, s2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePii, .Lfunc_end0-_Z9transposePii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12static_transPii
.globl _Z12static_transPii
.p2align 8
.type _Z12static_transPii,@function
_Z12static_transPii:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x8
v_not_b32_e32 v0, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
v_add_lshl_u32 v0, v0, s0, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12static_transPii
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12static_transPii, .Lfunc_end1-_Z12static_transPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13dynamic_transPii
.globl _Z13dynamic_transPii
.p2align 8
.type _Z13dynamic_transPii,@function
_Z13dynamic_transPii:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0, v1
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
v_xad_u32 v0, v0, -1, s0
v_lshl_add_u32 v0, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13dynamic_transPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13dynamic_transPii, .Lfunc_end2-_Z13dynamic_transPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12static_transPii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z12static_transPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13dynamic_transPii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z13dynamic_transPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00134794_00000000-6_vec_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9transposePiiPii
.type _Z29__device_stub__Z9transposePiiPii, @function
_Z29__device_stub__Z9transposePiiPii:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z9transposePiiPii, .-_Z29__device_stub__Z9transposePiiPii
.globl _Z9transposePii
.type _Z9transposePii, @function
_Z9transposePii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9transposePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9transposePii, .-_Z9transposePii
.globl _Z33__device_stub__Z12static_transPiiPii
.type _Z33__device_stub__Z12static_transPiiPii, @function
_Z33__device_stub__Z12static_transPiiPii:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12static_transPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z33__device_stub__Z12static_transPiiPii, .-_Z33__device_stub__Z12static_transPiiPii
.globl _Z12static_transPii
.type _Z12static_transPii, @function
_Z12static_transPii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z12static_transPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z12static_transPii, .-_Z12static_transPii
.globl _Z34__device_stub__Z13dynamic_transPiiPii
.type _Z34__device_stub__Z13dynamic_transPiiPii, @function
_Z34__device_stub__Z13dynamic_transPiiPii:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13dynamic_transPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z34__device_stub__Z13dynamic_transPiiPii, .-_Z34__device_stub__Z13dynamic_transPiiPii
.globl _Z13dynamic_transPii
.type _Z13dynamic_transPii, @function
_Z13dynamic_transPii:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z13dynamic_transPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z13dynamic_transPii, .-_Z13dynamic_transPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Common time is: "
.LC2:
.string " "
.LC3:
.string "Static sh m time is: "
.LC4:
.string "Dynamic sh m time is: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, 12(%rsp)
cltq
movq %rax, (%rsp)
leaq 0(,%rax,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r14, %rdi
call malloc@PLT
movq %rax, %r13
testl %r12d, %r12d
jle .L28
leal -1(%r12), %ecx
movl $0, %eax
.L29:
movl %eax, 0(%rbp,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L29
.L28:
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L30:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L31
movq %r13, %rbx
leal -1(%r12), %eax
leaq 4(%r13,%rax,4), %r15
.L32:
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L32
.L31:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movq (%rsp), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L33:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L34
movq %r13, %rbx
leal -1(%r12), %eax
leaq 4(%r13,%rax,4), %r15
.L35:
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L35
.L34:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movq (%rsp), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L47
.L36:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
testl %r12d, %r12d
jle .L37
movq %r13, %rbx
leal -1(%r12), %eax
leaq 4(%r13,%rax,4), %r15
leaq _ZSt4cout(%rip), %r14
leaq .LC2(%rip), %r12
.L38:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbx, %r15
jne .L38
.L37:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z9transposePiiPii
jmp .L30
.L46:
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z33__device_stub__Z12static_transPiiPii
jmp .L33
.L47:
movl 12(%rsp), %esi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z13dynamic_transPiiPii
jmp .L36
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z13dynamic_transPii"
.LC6:
.string "_Z12static_transPii"
.LC7:
.string "_Z9transposePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dynamic_transPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z12static_transPii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__transposePii # -- Begin function _Z24__device_stub__transposePii
.p2align 4, 0x90
.type _Z24__device_stub__transposePii,@function
_Z24__device_stub__transposePii: # @_Z24__device_stub__transposePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePii, .Lfunc_end0-_Z24__device_stub__transposePii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__static_transPii # -- Begin function _Z27__device_stub__static_transPii
.p2align 4, 0x90
.type _Z27__device_stub__static_transPii,@function
_Z27__device_stub__static_transPii: # @_Z27__device_stub__static_transPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12static_transPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z27__device_stub__static_transPii, .Lfunc_end1-_Z27__device_stub__static_transPii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__dynamic_transPii # -- Begin function _Z28__device_stub__dynamic_transPii
.p2align 4, 0x90
.type _Z28__device_stub__dynamic_transPii,@function
_Z28__device_stub__dynamic_transPii: # @_Z28__device_stub__dynamic_transPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13dynamic_transPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z28__device_stub__dynamic_transPii, .Lfunc_end2-_Z28__device_stub__dynamic_transPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movslq %r15d, %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r13, 128(%rsp) # 8-byte Spill
testl %r13d, %r13d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
movabsq $4294967297, %r13 # imm = 0x100000001
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 1023(%r13), %rdx
movq %r13, %rdi
movl $1, %esi
movq %rdx, 120(%rsp) # 8-byte Spill
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9transposePii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB3_8
# %bb.7:
movzbl 67(%r13), %eax
jmp .LBB3_9
.LBB3_8:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_12
# %bb.10: # %.lr.ph120.preheader
movl %r15d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_11: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r13
jne .LBB3_11
.LBB3_12: # %._crit_edge121
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i79
cmpb $0, 56(%r13)
je .LBB3_15
# %bb.14:
movzbl 67(%r13), %eax
jmp .LBB3_16
.LBB3_15:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit82
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
movq 128(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_18
# %bb.17:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12static_transPii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_18:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r13
testq %r13, %r13
je .LBB3_43
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
cmpb $0, 56(%r13)
je .LBB3_21
# %bb.20:
movzbl 67(%r13), %ecx
jmp .LBB3_22
.LBB3_21:
movq %r13, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit87
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_25
# %bb.23: # %.lr.ph123.preheader
movl %r15d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_24: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbp,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbp
cmpq %rbp, %r13
jne .LBB3_24
.LBB3_25: # %._crit_edge124
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r13)
je .LBB3_28
# %bb.27:
movzbl 67(%r13), %eax
jmp .LBB3_29
.LBB3_28:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq 120(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
movq 128(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_31
# %bb.30:
movq 24(%rsp), %rax
movq %rax, 88(%rsp)
movl %r15d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13dynamic_transPii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_31:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB3_43
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r12)
je .LBB3_34
# %bb.33:
movzbl 67(%r12), %ecx
jmp .LBB3_35
.LBB3_34:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB3_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
testl %r15d, %r15d
jle .LBB3_38
# %bb.36: # %.lr.ph126.preheader
movl %r15d, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_37: # %.lr.ph126
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB3_37
.LBB3_38: # %._crit_edge127
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB3_43
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
cmpb $0, 56(%r15)
je .LBB3_41
# %bb.40:
movzbl 67(%r15), %eax
jmp .LBB3_42
.LBB3_41:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_43:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12static_transPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dynamic_transPii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePii,@object # @_Z9transposePii
.section .rodata,"a",@progbits
.globl _Z9transposePii
.p2align 3, 0x0
_Z9transposePii:
.quad _Z24__device_stub__transposePii
.size _Z9transposePii, 8
.type _Z12static_transPii,@object # @_Z12static_transPii
.globl _Z12static_transPii
.p2align 3, 0x0
_Z12static_transPii:
.quad _Z27__device_stub__static_transPii
.size _Z12static_transPii, 8
.type _Z13dynamic_transPii,@object # @_Z13dynamic_transPii
.globl _Z13dynamic_transPii
.p2align 3, 0x0
_Z13dynamic_transPii:
.quad _Z28__device_stub__dynamic_transPii
.size _Z13dynamic_transPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Common time is: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Static sh m time is: "
.size .L.str.2, 22
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Dynamic sh m time is: "
.size .L.str.3, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePii"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12static_transPii"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13dynamic_transPii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePii
.addrsig_sym _Z27__device_stub__static_transPii
.addrsig_sym _Z28__device_stub__dynamic_transPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePii
.addrsig_sym _Z12static_transPii
.addrsig_sym _Z13dynamic_transPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
using namespace std;
__global__ void mul(int *d_in1,int *d_in2,int *d_out){
int idx = threadIdx.x;
d_out[idx] = d_in1[idx]*d_in2[idx];
}
__global__ void reduce_section(int *d_in,int &d_out,const int start,const int end){
int idx = threadIdx.x;
extern __shared__ int s_out[];
s_out[idx] = d_in[start+idx];
__syncthreads();
int out;
for(int step=1;step<end-start;step*=2){
if(idx-step>=0){
out = s_out[idx]+s_out[idx-1];
}
__syncthreads();
if(idx-step>=0)
s_out[idx] = out;
__syncthreads();
}
if(idx == end-start-1)
d_out = s_out[idx];
}
int main(){
const int size = 6;
int value[size] = {1,2,3,4,5,6};
int cols[size] = {0,2,1,0,1,0};
int rows[5] = {0,2,3,5,size};//最后一个元素记录非零元素个数
int mul_val[3] = {1,2,3};
int mul_valn[size];//非零元素相乘的对应元素
printf("左矩阵:\n");
int flag = 0;
for(int i=0;i<4;i++){
for(int i=0;i<3;i++){
if(i == cols[flag])
printf("%d ",value[flag++]);
else
printf("0 ");
}
printf("\n");
}
printf("\n右矩阵:\n");
for(int i=0;i<3;i++){
printf("%d\n",mul_val[i]);
}
printf("\n");
for(int i=0;i<size;i++){
mul_valn[i] = mul_val[cols[i]];
}
int *h_in1 = value;
int *h_in2 = mul_valn;
int *h_out;
int *d_in1;
int *d_in2;
int *d_out_mid;
int *d_out;
h_out = (int *)malloc(4*sizeof(int));
cudaMalloc((int **)&d_in1,size*sizeof(int));
cudaMalloc((int **)&d_in2,size*sizeof(int));
cudaMalloc((int **)&d_out,4*sizeof(int));
cudaMalloc((int **)&d_out_mid,size*sizeof(int));
cudaMemcpy(d_in1,h_in1,size*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_in2,h_in2,size*sizeof(int),cudaMemcpyHostToDevice);
dim3 thread(size);
mul<<<1,thread>>>(d_in1,d_in2,d_out_mid);
for(int i=1;i<5;i++){
int sizenew = rows[i]-rows[i-1];
dim3 threadnew(sizenew);
reduce_section<<<1,threadnew,sizenew>>>(d_out_mid,d_out[i-1],rows[i-1],rows[i]);
}
cudaMemcpy(h_out,d_out,4*sizeof(int),cudaMemcpyDeviceToHost);
printf("结果:\n");
for(int i=0;i<4;i++){
printf("%d\n",h_out[i]);
}
printf("\n");
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out_mid);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z14reduce_sectionPiRiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R2, R5, c[0x0][0x170], RZ ; /* 0x00005c0005027a10 */
/* 0x001fca0007ffe0ff */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fca00078e00ff */
/*0080*/ IADD3 R0, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*00a0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00c0*/ @!P0 BRA 0x180 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*00d0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x001fe40000000000 */
/*00e0*/ ISETP.GE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf06270 */
/*00f0*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fd8000800063f */
/*0100*/ @P0 LDS R2, [R5.X4] ; /* 0x0000000005020984 */
/* 0x000fe80000004800 */
/*0110*/ @P0 LDS R3, [R5.X4+-0x4] ; /* 0xfffffc0005030984 */
/* 0x000e240000004800 */
/*0120*/ @P0 IADD3 R4, R2, R3, RZ ; /* 0x0000000302040210 */
/* 0x001fe40007ffe0ff */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @P0 STS [R5.X4], R4 ; /* 0x0000000405000388 */
/* 0x0001e80000004800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0160*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf03270 */
/*0170*/ @!P0 BRA 0xe0 ; /* 0xffffff6000008947 */
/* 0x001fea000383ffff */
/*0180*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x001fe40000000a00 */
/*0190*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fc8000f8e333f */
/*01a0*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fcc000fffe03f */
/*01b0*/ ISETP.NE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf05270 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e220000004800 */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*01f0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
using namespace std;
__global__ void mul(int *d_in1,int *d_in2,int *d_out){
int idx = threadIdx.x;
d_out[idx] = d_in1[idx]*d_in2[idx];
}
__global__ void reduce_section(int *d_in,int &d_out,const int start,const int end){
int idx = threadIdx.x;
extern __shared__ int s_out[];
s_out[idx] = d_in[start+idx];
__syncthreads();
int out;
for(int step=1;step<end-start;step*=2){
if(idx-step>=0){
out = s_out[idx]+s_out[idx-1];
}
__syncthreads();
if(idx-step>=0)
s_out[idx] = out;
__syncthreads();
}
if(idx == end-start-1)
d_out = s_out[idx];
}
int main(){
const int size = 6;
int value[size] = {1,2,3,4,5,6};
int cols[size] = {0,2,1,0,1,0};
int rows[5] = {0,2,3,5,size};//最后一个元素记录非零元素个数
int mul_val[3] = {1,2,3};
int mul_valn[size];//非零元素相乘的对应元素
printf("左矩阵:\n");
int flag = 0;
for(int i=0;i<4;i++){
for(int i=0;i<3;i++){
if(i == cols[flag])
printf("%d ",value[flag++]);
else
printf("0 ");
}
printf("\n");
}
printf("\n右矩阵:\n");
for(int i=0;i<3;i++){
printf("%d\n",mul_val[i]);
}
printf("\n");
for(int i=0;i<size;i++){
mul_valn[i] = mul_val[cols[i]];
}
int *h_in1 = value;
int *h_in2 = mul_valn;
int *h_out;
int *d_in1;
int *d_in2;
int *d_out_mid;
int *d_out;
h_out = (int *)malloc(4*sizeof(int));
cudaMalloc((int **)&d_in1,size*sizeof(int));
cudaMalloc((int **)&d_in2,size*sizeof(int));
cudaMalloc((int **)&d_out,4*sizeof(int));
cudaMalloc((int **)&d_out_mid,size*sizeof(int));
cudaMemcpy(d_in1,h_in1,size*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_in2,h_in2,size*sizeof(int),cudaMemcpyHostToDevice);
dim3 thread(size);
mul<<<1,thread>>>(d_in1,d_in2,d_out_mid);
for(int i=1;i<5;i++){
int sizenew = rows[i]-rows[i-1];
dim3 threadnew(sizenew);
reduce_section<<<1,threadnew,sizenew>>>(d_out_mid,d_out[i-1],rows[i-1],rows[i]);
}
cudaMemcpy(h_out,d_out,4*sizeof(int),cudaMemcpyDeviceToHost);
printf("结果:\n");
for(int i=0;i<4;i++){
printf("%d\n",h_out[i]);
}
printf("\n");
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out_mid);
cudaFree(d_out);
return 0;
} | .file "tmpxft_0004a52e_00000000-6_scan_section.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3mulPiS_S_PiS_S_
.type _Z26__device_stub__Z3mulPiS_S_PiS_S_, @function
_Z26__device_stub__Z3mulPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3mulPiS_S_PiS_S_, .-_Z26__device_stub__Z3mulPiS_S_PiS_S_
.globl _Z3mulPiS_S_
.type _Z3mulPiS_S_, @function
_Z3mulPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3mulPiS_S_, .-_Z3mulPiS_S_
.globl _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
.type _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii, @function
_Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14reduce_sectionPiRiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii, .-_Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
.globl _Z14reduce_sectionPiRiii
.type _Z14reduce_sectionPiRiii, @function
_Z14reduce_sectionPiRiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14reduce_sectionPiRiii, .-_Z14reduce_sectionPiRiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\345\267\246\347\237\251\351\230\265:\n"
.LC1:
.string "%d "
.LC2:
.string "0 "
.LC3:
.string "\n"
.LC4:
.string "\n\345\217\263\347\237\251\351\230\265:\n"
.LC5:
.string "%d\n"
.LC6:
.string "\347\273\223\346\236\234:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl $1, 112(%rsp)
movl $2, 116(%rsp)
movl $3, 120(%rsp)
movl $4, 124(%rsp)
movl $5, 128(%rsp)
movl $6, 132(%rsp)
movl $0, 144(%rsp)
movl $2, 148(%rsp)
movl $1, 152(%rsp)
movl $0, 156(%rsp)
movl $1, 160(%rsp)
movl $0, 164(%rsp)
movl $0, 80(%rsp)
movl $2, 84(%rsp)
movl $3, 88(%rsp)
movl $5, 92(%rsp)
movl $6, 96(%rsp)
movl $1, 68(%rsp)
movl $2, 72(%rsp)
movl $3, 76(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %r12d
movl $0, %ebp
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L20
.L39:
leal 1(%rbp), %r14d
movl 112(%rsp,%rax,4), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %ebp
.L22:
addl $1, %ebx
cmpl $3, %ebx
je .L38
.L23:
movslq %ebp, %rax
cmpl %ebx, 144(%rsp,%rax,4)
je .L39
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L38:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl $1, %r12d
je .L24
.L20:
movl $0, %ebx
jmp .L23
.L24:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 68(%rsp), %rbx
leaq 80(%rsp), %r12
leaq .LC5(%rip), %rbp
.L25:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L25
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L26:
movslq 144(%rsp,%rax), %rdx
movl 68(%rsp,%rdx,4), %edx
movl %edx, 176(%rsp,%rax)
addq $4, %rax
cmpq $24, %rax
jne .L26
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L27:
movl $0, %ebx
leaq 84(%rsp), %r14
jmp .L29
.L40:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
jmp .L27
.L28:
addq $4, %rbx
cmpq $16, %rbx
je .L41
.L29:
movl (%r14,%rbx), %r12d
movl 80(%rsp,%rbx), %ebp
movl %r12d, %r8d
subl %ebp, %r8d
movl %r8d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
movq %rbx, %rsi
addq 24(%rsp), %rsi
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rdi
call _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
jmp .L28
.L41:
movl $2, %ecx
movl $16, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 16(%r13), %r12
leaq .LC5(%rip), %rbp
.L30:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L30
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z14reduce_sectionPiRiii"
.LC8:
.string "_Z3mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14reduce_sectionPiRiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
using namespace std;
__global__ void mul(int *d_in1,int *d_in2,int *d_out){
int idx = threadIdx.x;
d_out[idx] = d_in1[idx]*d_in2[idx];
}
__global__ void reduce_section(int *d_in,int &d_out,const int start,const int end){
int idx = threadIdx.x;
extern __shared__ int s_out[];
s_out[idx] = d_in[start+idx];
__syncthreads();
int out;
for(int step=1;step<end-start;step*=2){
if(idx-step>=0){
out = s_out[idx]+s_out[idx-1];
}
__syncthreads();
if(idx-step>=0)
s_out[idx] = out;
__syncthreads();
}
if(idx == end-start-1)
d_out = s_out[idx];
}
int main(){
const int size = 6;
int value[size] = {1,2,3,4,5,6};
int cols[size] = {0,2,1,0,1,0};
int rows[5] = {0,2,3,5,size};//最后一个元素记录非零元素个数
int mul_val[3] = {1,2,3};
int mul_valn[size];//非零元素相乘的对应元素
printf("左矩阵:\n");
int flag = 0;
for(int i=0;i<4;i++){
for(int i=0;i<3;i++){
if(i == cols[flag])
printf("%d ",value[flag++]);
else
printf("0 ");
}
printf("\n");
}
printf("\n右矩阵:\n");
for(int i=0;i<3;i++){
printf("%d\n",mul_val[i]);
}
printf("\n");
for(int i=0;i<size;i++){
mul_valn[i] = mul_val[cols[i]];
}
int *h_in1 = value;
int *h_in2 = mul_valn;
int *h_out;
int *d_in1;
int *d_in2;
int *d_out_mid;
int *d_out;
h_out = (int *)malloc(4*sizeof(int));
cudaMalloc((int **)&d_in1,size*sizeof(int));
cudaMalloc((int **)&d_in2,size*sizeof(int));
cudaMalloc((int **)&d_out,4*sizeof(int));
cudaMalloc((int **)&d_out_mid,size*sizeof(int));
cudaMemcpy(d_in1,h_in1,size*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_in2,h_in2,size*sizeof(int),cudaMemcpyHostToDevice);
dim3 thread(size);
mul<<<1,thread>>>(d_in1,d_in2,d_out_mid);
for(int i=1;i<5;i++){
int sizenew = rows[i]-rows[i-1];
dim3 threadnew(sizenew);
reduce_section<<<1,threadnew,sizenew>>>(d_out_mid,d_out[i-1],rows[i-1],rows[i]);
}
cudaMemcpy(h_out,d_out,4*sizeof(int),cudaMemcpyDeviceToHost);
printf("结果:\n");
for(int i=0;i<4;i++){
printf("%d\n",h_out[i]);
}
printf("\n");
free(h_out);
cudaFree(d_in1);
cudaFree(d_in2);
cudaFree(d_out_mid);
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
using namespace std;
__global__ void mul(int *d_in1,int *d_in2,int *d_out){
int idx = threadIdx.x;
d_out[idx] = d_in1[idx]*d_in2[idx];
}
__global__ void reduce_section(int *d_in,int &d_out,const int start,const int end){
int idx = threadIdx.x;
extern __shared__ int s_out[];
s_out[idx] = d_in[start+idx];
__syncthreads();
int out;
for(int step=1;step<end-start;step*=2){
if(idx-step>=0){
out = s_out[idx]+s_out[idx-1];
}
__syncthreads();
if(idx-step>=0)
s_out[idx] = out;
__syncthreads();
}
if(idx == end-start-1)
d_out = s_out[idx];
}
int main(){
const int size = 6;
int value[size] = {1,2,3,4,5,6};
int cols[size] = {0,2,1,0,1,0};
int rows[5] = {0,2,3,5,size};//最后一个元素记录非零元素个数
int mul_val[3] = {1,2,3};
int mul_valn[size];//非零元素相乘的对应元素
printf("左矩阵:\n");
int flag = 0;
for(int i=0;i<4;i++){
for(int i=0;i<3;i++){
if(i == cols[flag])
printf("%d ",value[flag++]);
else
printf("0 ");
}
printf("\n");
}
printf("\n右矩阵:\n");
for(int i=0;i<3;i++){
printf("%d\n",mul_val[i]);
}
printf("\n");
for(int i=0;i<size;i++){
mul_valn[i] = mul_val[cols[i]];
}
int *h_in1 = value;
int *h_in2 = mul_valn;
int *h_out;
int *d_in1;
int *d_in2;
int *d_out_mid;
int *d_out;
h_out = (int *)malloc(4*sizeof(int));
hipMalloc((int **)&d_in1,size*sizeof(int));
hipMalloc((int **)&d_in2,size*sizeof(int));
hipMalloc((int **)&d_out,4*sizeof(int));
hipMalloc((int **)&d_out_mid,size*sizeof(int));
hipMemcpy(d_in1,h_in1,size*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_in2,h_in2,size*sizeof(int),hipMemcpyHostToDevice);
dim3 thread(size);
mul<<<1,thread>>>(d_in1,d_in2,d_out_mid);
for(int i=1;i<5;i++){
int sizenew = rows[i]-rows[i-1];
dim3 threadnew(sizenew);
reduce_section<<<1,threadnew,sizenew>>>(d_out_mid,d_out[i-1],rows[i-1],rows[i]);
}
hipMemcpy(h_out,d_out,4*sizeof(int),hipMemcpyDeviceToHost);
printf("结果:\n");
for(int i=0;i<4;i++){
printf("%d\n",h_out[i]);
}
printf("\n");
free(h_out);
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out_mid);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
using namespace std;
__global__ void mul(int *d_in1,int *d_in2,int *d_out){
int idx = threadIdx.x;
d_out[idx] = d_in1[idx]*d_in2[idx];
}
__global__ void reduce_section(int *d_in,int &d_out,const int start,const int end){
int idx = threadIdx.x;
extern __shared__ int s_out[];
s_out[idx] = d_in[start+idx];
__syncthreads();
int out;
for(int step=1;step<end-start;step*=2){
if(idx-step>=0){
out = s_out[idx]+s_out[idx-1];
}
__syncthreads();
if(idx-step>=0)
s_out[idx] = out;
__syncthreads();
}
if(idx == end-start-1)
d_out = s_out[idx];
}
int main(){
const int size = 6;
int value[size] = {1,2,3,4,5,6};
int cols[size] = {0,2,1,0,1,0};
int rows[5] = {0,2,3,5,size};//最后一个元素记录非零元素个数
int mul_val[3] = {1,2,3};
int mul_valn[size];//非零元素相乘的对应元素
printf("左矩阵:\n");
int flag = 0;
for(int i=0;i<4;i++){
for(int i=0;i<3;i++){
if(i == cols[flag])
printf("%d ",value[flag++]);
else
printf("0 ");
}
printf("\n");
}
printf("\n右矩阵:\n");
for(int i=0;i<3;i++){
printf("%d\n",mul_val[i]);
}
printf("\n");
for(int i=0;i<size;i++){
mul_valn[i] = mul_val[cols[i]];
}
int *h_in1 = value;
int *h_in2 = mul_valn;
int *h_out;
int *d_in1;
int *d_in2;
int *d_out_mid;
int *d_out;
h_out = (int *)malloc(4*sizeof(int));
hipMalloc((int **)&d_in1,size*sizeof(int));
hipMalloc((int **)&d_in2,size*sizeof(int));
hipMalloc((int **)&d_out,4*sizeof(int));
hipMalloc((int **)&d_out_mid,size*sizeof(int));
hipMemcpy(d_in1,h_in1,size*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_in2,h_in2,size*sizeof(int),hipMemcpyHostToDevice);
dim3 thread(size);
mul<<<1,thread>>>(d_in1,d_in2,d_out_mid);
for(int i=1;i<5;i++){
int sizenew = rows[i]-rows[i-1];
dim3 threadnew(sizenew);
reduce_section<<<1,threadnew,sizenew>>>(d_out_mid,d_out[i-1],rows[i-1],rows[i]);
}
hipMemcpy(h_out,d_out,4*sizeof(int),hipMemcpyDeviceToHost);
printf("结果:\n");
for(int i=0;i<4;i++){
printf("%d\n",h_out[i]);
}
printf("\n");
free(h_out);
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out_mid);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPiS_S_
.globl _Z3mulPiS_S_
.p2align 8
.type _Z3mulPiS_S_,@function
_Z3mulPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPiS_S_, .Lfunc_end0-_Z3mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14reduce_sectionPiRiii
.globl _Z14reduce_sectionPiRiii
.p2align 8
.type _Z14reduce_sectionPiRiii,@function
_Z14reduce_sectionPiRiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s2, v0
s_sub_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lt_i32 s2, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s3, 1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v2, 0, -4
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
.LBB1_3:
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_5
ds_load_b32 v3, v1
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s4
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_2
ds_store_b32 v1, v3
s_branch .LBB1_2
.LBB1_7:
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_9
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14reduce_sectionPiRiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14reduce_sectionPiRiii, .Lfunc_end1-_Z14reduce_sectionPiRiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14reduce_sectionPiRiii
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14reduce_sectionPiRiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
using namespace std;
__global__ void mul(int *d_in1,int *d_in2,int *d_out){
int idx = threadIdx.x;
d_out[idx] = d_in1[idx]*d_in2[idx];
}
__global__ void reduce_section(int *d_in,int &d_out,const int start,const int end){
int idx = threadIdx.x;
extern __shared__ int s_out[];
s_out[idx] = d_in[start+idx];
__syncthreads();
int out;
for(int step=1;step<end-start;step*=2){
if(idx-step>=0){
out = s_out[idx]+s_out[idx-1];
}
__syncthreads();
if(idx-step>=0)
s_out[idx] = out;
__syncthreads();
}
if(idx == end-start-1)
d_out = s_out[idx];
}
int main(){
const int size = 6;
int value[size] = {1,2,3,4,5,6};
int cols[size] = {0,2,1,0,1,0};
int rows[5] = {0,2,3,5,size};//最后一个元素记录非零元素个数
int mul_val[3] = {1,2,3};
int mul_valn[size];//非零元素相乘的对应元素
printf("左矩阵:\n");
int flag = 0;
for(int i=0;i<4;i++){
for(int i=0;i<3;i++){
if(i == cols[flag])
printf("%d ",value[flag++]);
else
printf("0 ");
}
printf("\n");
}
printf("\n右矩阵:\n");
for(int i=0;i<3;i++){
printf("%d\n",mul_val[i]);
}
printf("\n");
for(int i=0;i<size;i++){
mul_valn[i] = mul_val[cols[i]];
}
int *h_in1 = value;
int *h_in2 = mul_valn;
int *h_out;
int *d_in1;
int *d_in2;
int *d_out_mid;
int *d_out;
h_out = (int *)malloc(4*sizeof(int));
hipMalloc((int **)&d_in1,size*sizeof(int));
hipMalloc((int **)&d_in2,size*sizeof(int));
hipMalloc((int **)&d_out,4*sizeof(int));
hipMalloc((int **)&d_out_mid,size*sizeof(int));
hipMemcpy(d_in1,h_in1,size*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_in2,h_in2,size*sizeof(int),hipMemcpyHostToDevice);
dim3 thread(size);
mul<<<1,thread>>>(d_in1,d_in2,d_out_mid);
for(int i=1;i<5;i++){
int sizenew = rows[i]-rows[i-1];
dim3 threadnew(sizenew);
reduce_section<<<1,threadnew,sizenew>>>(d_out_mid,d_out[i-1],rows[i-1],rows[i]);
}
hipMemcpy(h_out,d_out,4*sizeof(int),hipMemcpyDeviceToHost);
printf("结果:\n");
for(int i=0;i<4;i++){
printf("%d\n",h_out[i]);
}
printf("\n");
free(h_out);
hipFree(d_in1);
hipFree(d_in2);
hipFree(d_out_mid);
hipFree(d_out);
return 0;
} | .text
.file "scan_section.hip"
.globl _Z18__device_stub__mulPiS_S_ # -- Begin function _Z18__device_stub__mulPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__mulPiS_S_,@function
_Z18__device_stub__mulPiS_S_: # @_Z18__device_stub__mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPiS_S_, .Lfunc_end0-_Z18__device_stub__mulPiS_S_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__reduce_sectionPiRiii # -- Begin function _Z29__device_stub__reduce_sectionPiRiii
.p2align 4, 0x90
.type _Z29__device_stub__reduce_sectionPiRiii,@function
_Z29__device_stub__reduce_sectionPiRiii: # @_Z29__device_stub__reduce_sectionPiRiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14reduce_sectionPiRiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__reduce_sectionPiRiii, .Lfunc_end1-_Z29__device_stub__reduce_sectionPiRiii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI2_1:
.long 0 # 0x0
.long 2 # 0x2
.long 1 # 0x1
.long 0 # 0x0
.LCPI2_2:
.long 0 # 0x0
.long 2 # 0x2
.long 3 # 0x3
.long 5 # 0x5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 224(%rsp)
movabsq $25769803781, %rax # imm = 0x600000005
movq %rax, 240(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [0,2,1,0]
movaps %xmm0, 192(%rsp)
movq $1, 208(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [0,2,3,5]
movaps %xmm0, 160(%rsp)
movl $6, 176(%rsp)
movabsq $8589934593, %rax # imm = 0x200000001
movq %rax, 116(%rsp)
movl $3, 124(%rsp)
movl $.Lstr, %edi
callq puts@PLT
xorl %ebp, %ebp
xorl %ebx, %ebx
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
cmpl $4, %ebx
je .LBB2_5
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_2 Depth=2
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB2_19: # in Loop: Header=BB2_2 Depth=2
incl %r14d
cmpl $3, %r14d
je .LBB2_4
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movslq %ebp, %rax
cmpl 192(%rsp,%rax,4), %r14d
jne .LBB2_18
# %bb.3: # in Loop: Header=BB2_2 Depth=2
leal 1(%rax), %ebp
movl 224(%rsp,%rax,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_19
.LBB2_5:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl 116(%rsp,%rbx,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $3, %rbx
jne .LBB2_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movslq 192(%rsp,%rax,4), %rcx
movl 116(%rsp,%rcx,4), %ecx
movl %ecx, 256(%rsp,%rax,4)
incq %rax
cmpq $6, %rax
jne .LBB2_8
# %bb.9:
movabsq $4294967297, %r14 # imm = 0x100000001
movl $16, %edi
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $24, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $24, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 256(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
leaq 5(%r14), %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
xorl %r12d, %r12d
leaq 128(%rsp), %r15
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_12 Depth=1
addq $4, %r12
cmpq $16, %r12
je .LBB2_15
.LBB2_12: # =>This Inner Loop Header: Depth=1
movl 160(%rsp,%r12), %ebp
movl 164(%rsp,%r12), %r13d
movl %r13d, %eax
subl %ebp, %eax
leaq (%r14,%rax), %rdx
decq %rdx
movslq %eax, %r8
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_12 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
addq %r12, %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %ebp, 40(%rsp)
movl %r13d, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z14reduce_sectionPiRiii, %edi
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_14
.LBB2_15:
movq 8(%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_16: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
jne .LBB2_16
# %bb.17:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14reduce_sectionPiRiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPiS_S_,@object # @_Z3mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z3mulPiS_S_
.p2align 3, 0x0
_Z3mulPiS_S_:
.quad _Z18__device_stub__mulPiS_S_
.size _Z3mulPiS_S_, 8
.type _Z14reduce_sectionPiRiii,@object # @_Z14reduce_sectionPiRiii
.globl _Z14reduce_sectionPiRiii
.p2align 3, 0x0
_Z14reduce_sectionPiRiii:
.quad _Z29__device_stub__reduce_sectionPiRiii
.size _Z14reduce_sectionPiRiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "0 "
.size .L.str.2, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPiS_S_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14reduce_sectionPiRiii"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\345\267\246\347\237\251\351\230\265:"
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\345\217\263\347\237\251\351\230\265:"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\347\273\223\346\236\234:"
.size .Lstr.2, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPiS_S_
.addrsig_sym _Z29__device_stub__reduce_sectionPiRiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPiS_S_
.addrsig_sym _Z14reduce_sectionPiRiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14reduce_sectionPiRiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R2, R5, c[0x0][0x170], RZ ; /* 0x00005c0005027a10 */
/* 0x001fca0007ffe0ff */
/*0050*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fca00078e00ff */
/*0080*/ IADD3 R0, R0, -c[0x0][0x170], RZ ; /* 0x80005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*00a0*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0041e80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00c0*/ @!P0 BRA 0x180 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*00d0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x001fe40000000000 */
/*00e0*/ ISETP.GE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe2000bf06270 */
/*00f0*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fd8000800063f */
/*0100*/ @P0 LDS R2, [R5.X4] ; /* 0x0000000005020984 */
/* 0x000fe80000004800 */
/*0110*/ @P0 LDS R3, [R5.X4+-0x4] ; /* 0xfffffc0005030984 */
/* 0x000e240000004800 */
/*0120*/ @P0 IADD3 R4, R2, R3, RZ ; /* 0x0000000302040210 */
/* 0x001fe40007ffe0ff */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0140*/ @P0 STS [R5.X4], R4 ; /* 0x0000000405000388 */
/* 0x0001e80000004800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0160*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf03270 */
/*0170*/ @!P0 BRA 0xe0 ; /* 0xffffff6000008947 */
/* 0x001fea000383ffff */
/*0180*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x001fe40000000a00 */
/*0190*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fc8000f8e333f */
/*01a0*/ UIADD3 UR4, UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fcc000fffe03f */
/*01b0*/ ISETP.NE.AND P0, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fda000bf05270 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e220000004800 */
/*01e0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*01f0*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mulPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPiS_S_
.globl _Z3mulPiS_S_
.p2align 8
.type _Z3mulPiS_S_,@function
_Z3mulPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPiS_S_, .Lfunc_end0-_Z3mulPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14reduce_sectionPiRiii
.globl _Z14reduce_sectionPiRiii
.p2align 8
.type _Z14reduce_sectionPiRiii,@function
_Z14reduce_sectionPiRiii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s2, v0
s_sub_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lt_i32 s2, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
v_lshlrev_b32_e32 v2, 2, v0
s_mov_b32 s3, 1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v2, 0, -4
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_7
.LBB1_3:
v_cmp_le_u32_e32 vcc_lo, s3, v0
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_5
ds_load_b32 v3, v1
ds_load_b32 v4, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s4
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_2
ds_store_b32 v1, v3
s_branch .LBB1_2
.LBB1_7:
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_9
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v0, v1
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14reduce_sectionPiRiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14reduce_sectionPiRiii, .Lfunc_end1-_Z14reduce_sectionPiRiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3mulPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14reduce_sectionPiRiii
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14reduce_sectionPiRiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004a52e_00000000-6_scan_section.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3mulPiS_S_PiS_S_
.type _Z26__device_stub__Z3mulPiS_S_PiS_S_, @function
_Z26__device_stub__Z3mulPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3mulPiS_S_PiS_S_, .-_Z26__device_stub__Z3mulPiS_S_PiS_S_
.globl _Z3mulPiS_S_
.type _Z3mulPiS_S_, @function
_Z3mulPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3mulPiS_S_, .-_Z3mulPiS_S_
.globl _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
.type _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii, @function
_Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14reduce_sectionPiRiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii, .-_Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
.globl _Z14reduce_sectionPiRiii
.type _Z14reduce_sectionPiRiii, @function
_Z14reduce_sectionPiRiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14reduce_sectionPiRiii, .-_Z14reduce_sectionPiRiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\345\267\246\347\237\251\351\230\265:\n"
.LC1:
.string "%d "
.LC2:
.string "0 "
.LC3:
.string "\n"
.LC4:
.string "\n\345\217\263\347\237\251\351\230\265:\n"
.LC5:
.string "%d\n"
.LC6:
.string "\347\273\223\346\236\234:\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl $1, 112(%rsp)
movl $2, 116(%rsp)
movl $3, 120(%rsp)
movl $4, 124(%rsp)
movl $5, 128(%rsp)
movl $6, 132(%rsp)
movl $0, 144(%rsp)
movl $2, 148(%rsp)
movl $1, 152(%rsp)
movl $0, 156(%rsp)
movl $1, 160(%rsp)
movl $0, 164(%rsp)
movl $0, 80(%rsp)
movl $2, 84(%rsp)
movl $3, 88(%rsp)
movl $5, 92(%rsp)
movl $6, 96(%rsp)
movl $1, 68(%rsp)
movl $2, 72(%rsp)
movl $3, 76(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $4, %r12d
movl $0, %ebp
leaq .LC2(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L20
.L39:
leal 1(%rbp), %r14d
movl 112(%rsp,%rax,4), %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %ebp
.L22:
addl $1, %ebx
cmpl $3, %ebx
je .L38
.L23:
movslq %ebp, %rax
cmpl %ebx, 144(%rsp,%rax,4)
je .L39
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L38:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subl $1, %r12d
je .L24
.L20:
movl $0, %ebx
jmp .L23
.L24:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 68(%rsp), %rbx
leaq 80(%rsp), %r12
leaq .LC5(%rip), %rbp
.L25:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L25
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L26:
movslq 144(%rsp,%rax), %rdx
movl 68(%rsp,%rdx,4), %edx
movl %edx, 176(%rsp,%rax)
addq $4, %rax
cmpq $24, %rax
jne .L26
movl $16, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $24, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $24, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $6, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L27:
movl $0, %ebx
leaq 84(%rsp), %r14
jmp .L29
.L40:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3mulPiS_S_PiS_S_
jmp .L27
.L28:
addq $4, %rbx
cmpq $16, %rbx
je .L41
.L29:
movl (%r14,%rbx), %r12d
movl 80(%rsp,%rbx), %ebp
movl %r12d, %r8d
subl %ebp, %r8d
movl %r8d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movslq %r8d, %r8
movq 44(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
movq %rbx, %rsi
addq 24(%rsp), %rsi
movl %r12d, %ecx
movl %ebp, %edx
movq 16(%rsp), %rdi
call _Z38__device_stub__Z14reduce_sectionPiRiiiPiS_ii
jmp .L28
.L41:
movl $2, %ecx
movl $16, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rbx
leaq 16(%r13), %r12
leaq .LC5(%rip), %rbp
.L30:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbx, %r12
jne .L30
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z14reduce_sectionPiRiii"
.LC8:
.string "_Z3mulPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14reduce_sectionPiRiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan_section.hip"
.globl _Z18__device_stub__mulPiS_S_ # -- Begin function _Z18__device_stub__mulPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__mulPiS_S_,@function
_Z18__device_stub__mulPiS_S_: # @_Z18__device_stub__mulPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__mulPiS_S_, .Lfunc_end0-_Z18__device_stub__mulPiS_S_
.cfi_endproc
# -- End function
.globl _Z29__device_stub__reduce_sectionPiRiii # -- Begin function _Z29__device_stub__reduce_sectionPiRiii
.p2align 4, 0x90
.type _Z29__device_stub__reduce_sectionPiRiii,@function
_Z29__device_stub__reduce_sectionPiRiii: # @_Z29__device_stub__reduce_sectionPiRiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14reduce_sectionPiRiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__reduce_sectionPiRiii, .Lfunc_end1-_Z29__device_stub__reduce_sectionPiRiii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.long 4 # 0x4
.LCPI2_1:
.long 0 # 0x0
.long 2 # 0x2
.long 1 # 0x1
.long 0 # 0x0
.LCPI2_2:
.long 0 # 0x0
.long 2 # 0x2
.long 3 # 0x3
.long 5 # 0x5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [1,2,3,4]
movaps %xmm0, 224(%rsp)
movabsq $25769803781, %rax # imm = 0x600000005
movq %rax, 240(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [0,2,1,0]
movaps %xmm0, 192(%rsp)
movq $1, 208(%rsp)
movaps .LCPI2_2(%rip), %xmm0 # xmm0 = [0,2,3,5]
movaps %xmm0, 160(%rsp)
movl $6, 176(%rsp)
movabsq $8589934593, %rax # imm = 0x200000001
movq %rax, 116(%rsp)
movl $3, 124(%rsp)
movl $.Lstr, %edi
callq puts@PLT
xorl %ebp, %ebp
xorl %ebx, %ebx
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
cmpl $4, %ebx
je .LBB2_5
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_18: # in Loop: Header=BB2_2 Depth=2
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB2_19: # in Loop: Header=BB2_2 Depth=2
incl %r14d
cmpl $3, %r14d
je .LBB2_4
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movslq %ebp, %rax
cmpl 192(%rsp,%rax,4), %r14d
jne .LBB2_18
# %bb.3: # in Loop: Header=BB2_2 Depth=2
leal 1(%rax), %ebp
movl 224(%rsp,%rax,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
jmp .LBB2_19
.LBB2_5:
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
movl 116(%rsp,%rbx,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $3, %rbx
jne .LBB2_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_8: # =>This Inner Loop Header: Depth=1
movslq 192(%rsp,%rax,4), %rcx
movl 116(%rsp,%rcx,4), %ecx
movl %ecx, 256(%rsp,%rax,4)
incq %rax
cmpq $6, %rax
jne .LBB2_8
# %bb.9:
movabsq $4294967297, %r14 # imm = 0x100000001
movl $16, %edi
callq malloc
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $24, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $24, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $24, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 256(%rsp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
leaq 5(%r14), %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 56(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3mulPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
xorl %r12d, %r12d
leaq 128(%rsp), %r15
jmp .LBB2_12
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_12 Depth=1
addq $4, %r12
cmpq $16, %r12
je .LBB2_15
.LBB2_12: # =>This Inner Loop Header: Depth=1
movl 160(%rsp,%r12), %ebp
movl 164(%rsp,%r12), %r13d
movl %r13d, %eax
subl %ebp, %eax
leaq (%r14,%rax), %rdx
decq %rdx
movslq %eax, %r8
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_12 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
addq %r12, %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %ebp, 40(%rsp)
movl %r13d, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z14reduce_sectionPiRiii, %edi
movq %r15, %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_14
.LBB2_15:
movq 8(%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_16: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
jne .LBB2_16
# %bb.17:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14reduce_sectionPiRiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3mulPiS_S_,@object # @_Z3mulPiS_S_
.section .rodata,"a",@progbits
.globl _Z3mulPiS_S_
.p2align 3, 0x0
_Z3mulPiS_S_:
.quad _Z18__device_stub__mulPiS_S_
.size _Z3mulPiS_S_, 8
.type _Z14reduce_sectionPiRiii,@object # @_Z14reduce_sectionPiRiii
.globl _Z14reduce_sectionPiRiii
.p2align 3, 0x0
_Z14reduce_sectionPiRiii:
.quad _Z29__device_stub__reduce_sectionPiRiii
.size _Z14reduce_sectionPiRiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "0 "
.size .L.str.2, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n"
.size .L.str.5, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPiS_S_"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14reduce_sectionPiRiii"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\345\267\246\347\237\251\351\230\265:"
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\345\217\263\347\237\251\351\230\265:"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\347\273\223\346\236\234:"
.size .Lstr.2, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPiS_S_
.addrsig_sym _Z29__device_stub__reduce_sectionPiRiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPiS_S_
.addrsig_sym _Z14reduce_sectionPiRiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// richu shaji abraham richursa
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
if(bitset == 1 )
{
if((value & bit) != 0)
{
return 1;
}
else
return 0;
}
else
{
if((value & bit) == 0)
{
return 1;
}
else
{
return 0;
}
}
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index < d_numberOfElements)
{
d_predicateArrry[index] = function(d_array[index],bit,bitset);
}
} | code for sm_80
Function : _Z15predicateDevicePiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*00c0*/ ISETP.NE.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f25270 */
/*00d0*/ LOP3.LUT P0, RZ, R2, c[0x0][0x174], RZ, 0xc0, !PT ; /* 0x00005d0002ff7a12 */
/* 0x004fc8000780c0ff */
/*00e0*/ SEL R0, RZ, 0xffffffff, P0 ; /* 0xffffffffff007807 */
/* 0x000fce0000000000 */
/*00f0*/ @!P1 SEL R0, RZ, 0xffffffff, !P0 ; /* 0xffffffffff009807 */
/* 0x000fc80004000000 */
/*0100*/ LOP3.LUT R7, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100077812 */
/* 0x000fca00078ec0ff */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// richu shaji abraham richursa
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
if(bitset == 1 )
{
if((value & bit) != 0)
{
return 1;
}
else
return 0;
}
else
{
if((value & bit) == 0)
{
return 1;
}
else
{
return 0;
}
}
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index < d_numberOfElements)
{
d_predicateArrry[index] = function(d_array[index],bit,bitset);
}
} | .file "tmpxft_000e68eb_00000000-6_predicateDevice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8functioniii
.type _Z8functioniii, @function
_Z8functioniii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8functioniii, .-_Z8functioniii
.globl _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
.type _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii, @function
_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15predicateDevicePiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii, .-_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
.globl _Z15predicateDevicePiS_iii
.type _Z15predicateDevicePiS_iii, @function
_Z15predicateDevicePiS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15predicateDevicePiS_iii, .-_Z15predicateDevicePiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15predicateDevicePiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15predicateDevicePiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// richu shaji abraham richursa
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
if(bitset == 1 )
{
if((value & bit) != 0)
{
return 1;
}
else
return 0;
}
else
{
if((value & bit) == 0)
{
return 1;
}
else
{
return 0;
}
}
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index < d_numberOfElements)
{
d_predicateArrry[index] = function(d_array[index],bit,bitset);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// richu shaji abraham richursa
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
if(bitset == 1 )
{
if((value & bit) != 0)
{
return 1;
}
else
return 0;
}
else
{
if((value & bit) == 0)
{
return 1;
}
else
{
return 0;
}
}
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index < d_numberOfElements)
{
d_predicateArrry[index] = function(d_array[index],bit,bitset);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// richu shaji abraham richursa
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
if(bitset == 1 )
{
if((value & bit) != 0)
{
return 1;
}
else
return 0;
}
else
{
if((value & bit) == 0)
{
return 1;
}
else
{
return 0;
}
}
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index < d_numberOfElements)
{
d_predicateArrry[index] = function(d_array[index],bit,bitset);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15predicateDevicePiS_iii
.globl _Z15predicateDevicePiS_iii
.p2align 8
.type _Z15predicateDevicePiS_iii,@function
_Z15predicateDevicePiS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_cmp_eq_u32 s1, 1
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, s0, v2
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_and_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15predicateDevicePiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15predicateDevicePiS_iii, .Lfunc_end0-_Z15predicateDevicePiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15predicateDevicePiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15predicateDevicePiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// richu shaji abraham richursa
using namespace std;
__device__ int function(int value , int bit ,int bitset)
{
if(bitset == 1 )
{
if((value & bit) != 0)
{
return 1;
}
else
return 0;
}
else
{
if((value & bit) == 0)
{
return 1;
}
else
{
return 0;
}
}
}
__global__ void predicateDevice(int *d_array , int *d_predicateArrry , int d_numberOfElements,int bit,int bitset)
{
int index = threadIdx.x + blockIdx.x*blockDim.x;
if(index < d_numberOfElements)
{
d_predicateArrry[index] = function(d_array[index],bit,bitset);
}
} | .text
.file "predicateDevice.hip"
.globl _Z30__device_stub__predicateDevicePiS_iii # -- Begin function _Z30__device_stub__predicateDevicePiS_iii
.p2align 4, 0x90
.type _Z30__device_stub__predicateDevicePiS_iii,@function
_Z30__device_stub__predicateDevicePiS_iii: # @_Z30__device_stub__predicateDevicePiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15predicateDevicePiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__predicateDevicePiS_iii, .Lfunc_end0-_Z30__device_stub__predicateDevicePiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15predicateDevicePiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15predicateDevicePiS_iii,@object # @_Z15predicateDevicePiS_iii
.section .rodata,"a",@progbits
.globl _Z15predicateDevicePiS_iii
.p2align 3, 0x0
_Z15predicateDevicePiS_iii:
.quad _Z30__device_stub__predicateDevicePiS_iii
.size _Z15predicateDevicePiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15predicateDevicePiS_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__predicateDevicePiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15predicateDevicePiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15predicateDevicePiS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*00c0*/ ISETP.NE.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f25270 */
/*00d0*/ LOP3.LUT P0, RZ, R2, c[0x0][0x174], RZ, 0xc0, !PT ; /* 0x00005d0002ff7a12 */
/* 0x004fc8000780c0ff */
/*00e0*/ SEL R0, RZ, 0xffffffff, P0 ; /* 0xffffffffff007807 */
/* 0x000fce0000000000 */
/*00f0*/ @!P1 SEL R0, RZ, 0xffffffff, !P0 ; /* 0xffffffffff009807 */
/* 0x000fc80004000000 */
/*0100*/ LOP3.LUT R7, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100077812 */
/* 0x000fca00078ec0ff */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15predicateDevicePiS_iii
.globl _Z15predicateDevicePiS_iii
.p2align 8
.type _Z15predicateDevicePiS_iii,@function
_Z15predicateDevicePiS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_cmp_eq_u32 s1, 1
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, s0, v2
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_and_b32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15predicateDevicePiS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15predicateDevicePiS_iii, .Lfunc_end0-_Z15predicateDevicePiS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15predicateDevicePiS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15predicateDevicePiS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e68eb_00000000-6_predicateDevice.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8functioniii
.type _Z8functioniii, @function
_Z8functioniii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z8functioniii, .-_Z8functioniii
.globl _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
.type _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii, @function
_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15predicateDevicePiS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii, .-_Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
.globl _Z15predicateDevicePiS_iii
.type _Z15predicateDevicePiS_iii, @function
_Z15predicateDevicePiS_iii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15predicateDevicePiS_iiiPiS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z15predicateDevicePiS_iii, .-_Z15predicateDevicePiS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15predicateDevicePiS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15predicateDevicePiS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "predicateDevice.hip"
.globl _Z30__device_stub__predicateDevicePiS_iii # -- Begin function _Z30__device_stub__predicateDevicePiS_iii
.p2align 4, 0x90
.type _Z30__device_stub__predicateDevicePiS_iii,@function
_Z30__device_stub__predicateDevicePiS_iii: # @_Z30__device_stub__predicateDevicePiS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15predicateDevicePiS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__predicateDevicePiS_iii, .Lfunc_end0-_Z30__device_stub__predicateDevicePiS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15predicateDevicePiS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15predicateDevicePiS_iii,@object # @_Z15predicateDevicePiS_iii
.section .rodata,"a",@progbits
.globl _Z15predicateDevicePiS_iii
.p2align 3, 0x0
_Z15predicateDevicePiS_iii:
.quad _Z30__device_stub__predicateDevicePiS_iii
.size _Z15predicateDevicePiS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15predicateDevicePiS_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__predicateDevicePiS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15predicateDevicePiS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
struct compressed_sparse_column {
int* data;
int* row;
int* column;
int* index_column;
int* index_row_start;
int* index_row_end;
};
struct graph {
compressed_sparse_column* dataset;
bool* roots;
bool* leaves;
bool* singletons;
int vertices;
int edges;
};
__global__ void pre_post_order(int* depth, int* zeta, int* zeta_tilde, graph* dataset_graph) {
int* pre = new int[dataset_graph->vertices];
int* post = new int[dataset_graph->vertices];
memset(pre, 0, dataset_graph->vertices * sizeof(int));
memset(post, 0, dataset_graph->vertices * sizeof(int));
bool* incoming_edges = new bool[dataset_graph->edges];
memset(incoming_edges, false, dataset_graph->edges * sizeof(bool));
bool* q = new bool[dataset_graph->vertices];
memcpy(q, dataset_graph->roots, sizeof(int) * dataset_graph->vertices);
while(true) {
bool* p = new bool[dataset_graph->vertices];
memset(p, false, dataset_graph->vertices * sizeof(bool));
bool global_check = false;
for(int i = 0; i < dataset_graph->vertices; i++) {
if( q[i] ) {
int pre_node = pre[i];
int post_node = post[i];
for(int j = dataset_graph->dataset->index_column[i]; dataset_graph->dataset->column[j] == i; j++) {
int neighbor_vertex = dataset_graph->dataset->row[j];
// zeta[i] = undefined!
pre[neighbor_vertex] = pre_node + zeta_tilde[neighbor_vertex];
post[neighbor_vertex] = post_node + zeta_tilde[neighbor_vertex];
incoming_edges[j] = true;
bool flag = true;
for(int k = 0; k < dataset_graph->edges; k++) {
if( dataset_graph->dataset->row[k] == neighbor_vertex && !incoming_edges[k] ) {
flag = false;
break;
}
}
if( flag ) {
global_check = true;
p[neighbor_vertex] = true;
}
}
pre[i] = pre_node + depth[i];
post[i] = post_node + (zeta[i] - 1);
}
}
q = p;
if( !global_check ) {
break;
}
}
} | .file "tmpxft_0017eea5_00000000-6_pre_post_order.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph
.type _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph, @function
_Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14pre_post_orderPiS_S_P5graph(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph, .-_Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph
.globl _Z14pre_post_orderPiS_S_P5graph
.type _Z14pre_post_orderPiS_S_P5graph, @function
_Z14pre_post_orderPiS_S_P5graph:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14pre_post_orderPiS_S_P5graph, .-_Z14pre_post_orderPiS_S_P5graph
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14pre_post_orderPiS_S_P5graph"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14pre_post_orderPiS_S_P5graph(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
struct compressed_sparse_column {
int* data;
int* row;
int* column;
int* index_column;
int* index_row_start;
int* index_row_end;
};
struct graph {
compressed_sparse_column* dataset;
bool* roots;
bool* leaves;
bool* singletons;
int vertices;
int edges;
};
__global__ void pre_post_order(int* depth, int* zeta, int* zeta_tilde, graph* dataset_graph) {
int* pre = new int[dataset_graph->vertices];
int* post = new int[dataset_graph->vertices];
memset(pre, 0, dataset_graph->vertices * sizeof(int));
memset(post, 0, dataset_graph->vertices * sizeof(int));
bool* incoming_edges = new bool[dataset_graph->edges];
memset(incoming_edges, false, dataset_graph->edges * sizeof(bool));
bool* q = new bool[dataset_graph->vertices];
memcpy(q, dataset_graph->roots, sizeof(int) * dataset_graph->vertices);
while(true) {
bool* p = new bool[dataset_graph->vertices];
memset(p, false, dataset_graph->vertices * sizeof(bool));
bool global_check = false;
for(int i = 0; i < dataset_graph->vertices; i++) {
if( q[i] ) {
int pre_node = pre[i];
int post_node = post[i];
for(int j = dataset_graph->dataset->index_column[i]; dataset_graph->dataset->column[j] == i; j++) {
int neighbor_vertex = dataset_graph->dataset->row[j];
// zeta[i] = undefined!
pre[neighbor_vertex] = pre_node + zeta_tilde[neighbor_vertex];
post[neighbor_vertex] = post_node + zeta_tilde[neighbor_vertex];
incoming_edges[j] = true;
bool flag = true;
for(int k = 0; k < dataset_graph->edges; k++) {
if( dataset_graph->dataset->row[k] == neighbor_vertex && !incoming_edges[k] ) {
flag = false;
break;
}
}
if( flag ) {
global_check = true;
p[neighbor_vertex] = true;
}
}
pre[i] = pre_node + depth[i];
post[i] = post_node + (zeta[i] - 1);
}
}
q = p;
if( !global_check ) {
break;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
struct compressed_sparse_column {
int* data;
int* row;
int* column;
int* index_column;
int* index_row_start;
int* index_row_end;
};
struct graph {
compressed_sparse_column* dataset;
bool* roots;
bool* leaves;
bool* singletons;
int vertices;
int edges;
};
__global__ void pre_post_order(int* depth, int* zeta, int* zeta_tilde, graph* dataset_graph) {
int* pre = new int[dataset_graph->vertices];
int* post = new int[dataset_graph->vertices];
memset(pre, 0, dataset_graph->vertices * sizeof(int));
memset(post, 0, dataset_graph->vertices * sizeof(int));
bool* incoming_edges = new bool[dataset_graph->edges];
memset(incoming_edges, false, dataset_graph->edges * sizeof(bool));
bool* q = new bool[dataset_graph->vertices];
memcpy(q, dataset_graph->roots, sizeof(int) * dataset_graph->vertices);
while(true) {
bool* p = new bool[dataset_graph->vertices];
memset(p, false, dataset_graph->vertices * sizeof(bool));
bool global_check = false;
for(int i = 0; i < dataset_graph->vertices; i++) {
if( q[i] ) {
int pre_node = pre[i];
int post_node = post[i];
for(int j = dataset_graph->dataset->index_column[i]; dataset_graph->dataset->column[j] == i; j++) {
int neighbor_vertex = dataset_graph->dataset->row[j];
// zeta[i] = undefined!
pre[neighbor_vertex] = pre_node + zeta_tilde[neighbor_vertex];
post[neighbor_vertex] = post_node + zeta_tilde[neighbor_vertex];
incoming_edges[j] = true;
bool flag = true;
for(int k = 0; k < dataset_graph->edges; k++) {
if( dataset_graph->dataset->row[k] == neighbor_vertex && !incoming_edges[k] ) {
flag = false;
break;
}
}
if( flag ) {
global_check = true;
p[neighbor_vertex] = true;
}
}
pre[i] = pre_node + depth[i];
post[i] = post_node + (zeta[i] - 1);
}
}
q = p;
if( !global_check ) {
break;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
struct compressed_sparse_column {
int* data;
int* row;
int* column;
int* index_column;
int* index_row_start;
int* index_row_end;
};
struct graph {
compressed_sparse_column* dataset;
bool* roots;
bool* leaves;
bool* singletons;
int vertices;
int edges;
};
__global__ void pre_post_order(int* depth, int* zeta, int* zeta_tilde, graph* dataset_graph) {
int* pre = new int[dataset_graph->vertices];
int* post = new int[dataset_graph->vertices];
memset(pre, 0, dataset_graph->vertices * sizeof(int));
memset(post, 0, dataset_graph->vertices * sizeof(int));
bool* incoming_edges = new bool[dataset_graph->edges];
memset(incoming_edges, false, dataset_graph->edges * sizeof(bool));
bool* q = new bool[dataset_graph->vertices];
memcpy(q, dataset_graph->roots, sizeof(int) * dataset_graph->vertices);
while(true) {
bool* p = new bool[dataset_graph->vertices];
memset(p, false, dataset_graph->vertices * sizeof(bool));
bool global_check = false;
for(int i = 0; i < dataset_graph->vertices; i++) {
if( q[i] ) {
int pre_node = pre[i];
int post_node = post[i];
for(int j = dataset_graph->dataset->index_column[i]; dataset_graph->dataset->column[j] == i; j++) {
int neighbor_vertex = dataset_graph->dataset->row[j];
// zeta[i] = undefined!
pre[neighbor_vertex] = pre_node + zeta_tilde[neighbor_vertex];
post[neighbor_vertex] = post_node + zeta_tilde[neighbor_vertex];
incoming_edges[j] = true;
bool flag = true;
for(int k = 0; k < dataset_graph->edges; k++) {
if( dataset_graph->dataset->row[k] == neighbor_vertex && !incoming_edges[k] ) {
flag = false;
break;
}
}
if( flag ) {
global_check = true;
p[neighbor_vertex] = true;
}
}
pre[i] = pre_node + depth[i];
post[i] = post_node + (zeta[i] - 1);
}
}
q = p;
if( !global_check ) {
break;
}
}
} | .text
.file "pre_post_order.hip"
.globl _Z29__device_stub__pre_post_orderPiS_S_P5graph # -- Begin function _Z29__device_stub__pre_post_orderPiS_S_P5graph
.p2align 4, 0x90
.type _Z29__device_stub__pre_post_orderPiS_S_P5graph,@function
_Z29__device_stub__pre_post_orderPiS_S_P5graph: # @_Z29__device_stub__pre_post_orderPiS_S_P5graph
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14pre_post_orderPiS_S_P5graph, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__pre_post_orderPiS_S_P5graph, .Lfunc_end0-_Z29__device_stub__pre_post_orderPiS_S_P5graph
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14pre_post_orderPiS_S_P5graph, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14pre_post_orderPiS_S_P5graph,@object # @_Z14pre_post_orderPiS_S_P5graph
.section .rodata,"a",@progbits
.globl _Z14pre_post_orderPiS_S_P5graph
.p2align 3, 0x0
_Z14pre_post_orderPiS_S_P5graph:
.quad _Z29__device_stub__pre_post_orderPiS_S_P5graph
.size _Z14pre_post_orderPiS_S_P5graph, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14pre_post_orderPiS_S_P5graph"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__pre_post_orderPiS_S_P5graph
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14pre_post_orderPiS_S_P5graph
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017eea5_00000000-6_pre_post_order.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph
.type _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph, @function
_Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14pre_post_orderPiS_S_P5graph(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph, .-_Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph
.globl _Z14pre_post_orderPiS_S_P5graph
.type _Z14pre_post_orderPiS_S_P5graph, @function
_Z14pre_post_orderPiS_S_P5graph:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z14pre_post_orderPiS_S_P5graphPiS_S_P5graph
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14pre_post_orderPiS_S_P5graph, .-_Z14pre_post_orderPiS_S_P5graph
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14pre_post_orderPiS_S_P5graph"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14pre_post_orderPiS_S_P5graph(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pre_post_order.hip"
.globl _Z29__device_stub__pre_post_orderPiS_S_P5graph # -- Begin function _Z29__device_stub__pre_post_orderPiS_S_P5graph
.p2align 4, 0x90
.type _Z29__device_stub__pre_post_orderPiS_S_P5graph,@function
_Z29__device_stub__pre_post_orderPiS_S_P5graph: # @_Z29__device_stub__pre_post_orderPiS_S_P5graph
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14pre_post_orderPiS_S_P5graph, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__pre_post_orderPiS_S_P5graph, .Lfunc_end0-_Z29__device_stub__pre_post_orderPiS_S_P5graph
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14pre_post_orderPiS_S_P5graph, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14pre_post_orderPiS_S_P5graph,@object # @_Z14pre_post_orderPiS_S_P5graph
.section .rodata,"a",@progbits
.globl _Z14pre_post_orderPiS_S_P5graph
.p2align 3, 0x0
_Z14pre_post_orderPiS_S_P5graph:
.quad _Z29__device_stub__pre_post_orderPiS_S_P5graph
.size _Z14pre_post_orderPiS_S_P5graph, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14pre_post_orderPiS_S_P5graph"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__pre_post_orderPiS_S_P5graph
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14pre_post_orderPiS_S_P5graph
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#define FILENAME "./dblp-co-authors.txt"
#define NumAuthor 317080
#define DataLen 1049866
#define BlockSize 1024
#define GridSize int(DataLen/BlockSize) + 1
#define MAX 343
#define newGridSize int(NumAuthor/BlockSize) + 1
int dataset[DataLen * 2];// array to store the raw dataset
void dataset_read(int * dataset);
__global__ void dataset_parse(int * dataset, int * output, int * full_output);
//int dataset_maxCoAuthor(int * output, int lenght);
//void dataset_plot(int * output, int lenght, int max);
__global__ void output_parse(int * full_output, int * output, int * num_author_array);
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len);
__device__ void count_diff_auth(int * pair_array, int * new_array,int pair_len, int * pure_len, int indx);
int main(int argc, char * argv[])
{
int output[NumAuthor] = {0};
int full_output[MAX * NumAuthor] = { 0 };
int * cu_output;//array to store the co-authors number of each author
int * cu_full_output;
dataset_read(dataset);
// Set device that we will use for our cuda code
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
float time;
int * cu_dataset;
cudaEventRecord(start,0);
cudaMalloc((void**)&cu_output, NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_full_output, MAX * NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_dataset, DataLen * 2 * sizeof(int));
cudaMemcpy(cu_dataset, dataset, DataLen * 2 * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(cu_full_output, full_output, MAX * NumAuthor * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(cu_output, output, NumAuthor * sizeof(int), cudaMemcpyHostToDevice);
dataset_parse<<<GridSize, BlockSize>>>(cu_dataset, cu_output, cu_full_output);
cudaDeviceSynchronize();
cudaMemcpy(output, cu_output, NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(full_output, cu_full_output, MAX * NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
//int max = dataset_maxCoAuthor(output, NumAuthor);
//printf("Time elapsed: %f\n", time);
int * cu_num_author_array;
int * num_author_array = (int*)malloc(NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_num_author_array, NumAuthor * sizeof(int));
cudaMemset(cu_num_author_array, 0, NumAuthor * sizeof(int));
cudaEventRecord(start,0);
output_parse<<<newGridSize, BlockSize>>>(cu_full_output, cu_output, cu_num_author_array);
cudaDeviceSynchronize();
printf("Error in Kernel output_parse:%s\n",cudaGetErrorString(cudaGetLastError()));
cudaDeviceSynchronize();
cudaMemcpy(num_author_array, cu_num_author_array, NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time in Kernel output_parse: %f\n", time);
int total_number = 0;
for (int i = 0; i < NumAuthor; i++)
total_number += num_author_array[i];
printf("Total number of authors is %d\n", total_number/2);
return 0;
}
void dataset_read( int * dataset)
{
FILE * datafile;
datafile = fopen( FILENAME, "r");
char line[255];
while (true)
{
fscanf(datafile, "%s", line);
if (atoi(line) == 1)
{
dataset[0] = 1;
break;
}
}
for(int i = 1; i < 2 * DataLen; i++){
fscanf(datafile, "%d", &dataset[i]);
}
fclose(datafile);
}
__global__ void dataset_parse(int * dataset, int * output, int * full_output)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
int i, j;
if(indx < DataLen){
i = atomicAdd(&(output[dataset[2*indx]-1]), 1);
full_output[(dataset[2*indx]-1) * MAX + i] = dataset[2*indx+1];
j = atomicAdd(&(output[dataset[2*indx+1]-1]), 1);
full_output[(dataset[2*indx + 1]-1) * MAX + j] = dataset[2*indx];
}
}
/*
int dataset_maxCoAuthor(int * output, int lenght)
{
int max =0;
int max_num = 0;
int max_ind[1000] = { 0 };
//memset(max_ind, 0, 1000);
for(int i = 0; i < lenght; i++)
{
//printf("output:%d, %d", i, output[i]);
if(max < output[i])
{
// printf("Max right now:%d, %d\n", i, output[i]);
max = output[i];
max_num = 0;
memset(max_ind, 0, 1000);
max_ind[max_num] = i;
}
else if(max == output[i])
{
max_num++;
max_ind[max_num] = i;
}
//else{
//printf("max is:%d, %d\n", max, max_ind[0]);
//}
}
printf("The list of authors with most co-authors:\n");
for(int i = 0; i <= max_num; i++)
{
printf("Author: %6d has %6d co-authors.\n", max_ind[i] + 1, output[max_ind[i]]);
}
return output[max_ind[0]];
}
void dataset_plot(int * output, int lenght, int max)
{
//int* numCoAuthorList;
int* numCoAuthorList = (int*)malloc(max * sizeof(int));
memset(numCoAuthorList, 0, max);
for(int i = 0; i < lenght; i++)
{
if(output[i] <= max)
{
numCoAuthorList[output[i] - 1]++;
}
else{
printf("\nError in Finding MAX!!!\n");
}
}
FILE *fp;
fp = fopen("./output.txt", "wb");
fwrite(numCoAuthorList, sizeof(int), max, fp);
fclose(fp);
}
*/
__global__ void output_parse(int * full_output, int * output, int * num_author_array)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
if(indx < NumAuthor){
int pair_array[10000] = { 0 };
int pair_len = 0;
int coauthor, coauthor_co_len, possible_pair;
for(int i = 0; i < output[indx]; i++){
coauthor = full_output[indx * MAX + i];
coauthor_co_len = output[coauthor-1];
for(int j = 0; j < coauthor_co_len; j++){
possible_pair = full_output[(coauthor - 1) * MAX + j];
check_pair(full_output, indx * MAX, output[indx], possible_pair, pair_array, &pair_len);
}
}
//int * new_array = (int*)malloc(pair_len * sizeof(int));
//memset(new_array, 0, pair_len );
int new_array[10000] = {0};
int num_authors = 0;
count_diff_auth(pair_array, new_array, pair_len, &num_authors, indx);
num_author_array[indx] = num_authors;
}
}
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len){
for(int i = 0; i < len; i++){
if(full_output[start + i] == possible_pair){
pair_array[*pair_len] = possible_pair;
(*pair_len)++;
break;
}
}
}
__device__ void count_diff_auth(int * pair_array,int * new_array, int pair_len, int * pure_len, int indx){
//int * new_array;
//cudaMalloc((void**)&new_array, pair_len * sizeof(int));
//cudaMemset(new_array, 0, pair_len * sizeof(int));
//printf("pair_array[0]:%d, pair_len:%d, %d\n",pair_array[0], pair_len, indx);
new_array[0] = pair_array[0];
*pure_len = 1;
for(int i = 1; i < pair_len; i++){
int j;
for(j = 0; j< *pure_len; j++){
if(pair_array[i] == new_array[j]){
break;
}
}
if (j == *pure_len){
new_array[*pure_len] = pair_array[i];
(*pure_len)++;
}
}
} | code for sm_80
Function : _Z12output_parsePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x13880, RZ ; /* 0xfffec78001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0050*/ ISETP.GT.AND P0, PT, R5, 0x4d697, PT ; /* 0x0004d6970500780c */
/* 0x000fda0003f04270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ STL.128 [R1], RZ ; /* 0x000000ff01007387 */
/* 0x0001e20000100c00 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0001 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*00c0*/ IMAD.U32 R3, R4, 0x4, R1 ; /* 0x0000000404037824 */
/* 0x002fe200078e0001 */
/*00d0*/ IADD3 R2, R2, 0x54, RZ ; /* 0x0000005402027810 */
/* 0x000fe40007ffe0ff */
/*00e0*/ IADD3 R4, R4, 0x54, RZ ; /* 0x0000005404047810 */
/* 0x000fe40007ffe0ff */
/*00f0*/ STL.128 [R3], RZ ; /* 0x000000ff03007387 */
/* 0x0003e20000100c00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x2710, PT ; /* 0x000027100200780c */
/* 0x000fc60003f06070 */
/*0110*/ STL.128 [R3+0x10], RZ ; /* 0x000010ff03007387 */
/* 0x0003e80000100c00 */
/*0120*/ STL.128 [R3+0x20], RZ ; /* 0x000020ff03007387 */
/* 0x0003e80000100c00 */
/*0130*/ STL.128 [R3+0x30], RZ ; /* 0x000030ff03007387 */
/* 0x0003e80000100c00 */
/*0140*/ STL.128 [R3+0x40], RZ ; /* 0x000040ff03007387 */
/* 0x0003e80000100c00 */
/*0150*/ STL.128 [R3+0x50], RZ ; /* 0x000050ff03007387 */
/* 0x0003e80000100c00 */
/*0160*/ STL.128 [R3+0x60], RZ ; /* 0x000060ff03007387 */
/* 0x0003e80000100c00 */
/*0170*/ STL.128 [R3+0x70], RZ ; /* 0x000070ff03007387 */
/* 0x0003e80000100c00 */
/*0180*/ STL.128 [R3+0x80], RZ ; /* 0x000080ff03007387 */
/* 0x0003e80000100c00 */
/*0190*/ STL.128 [R3+0x90], RZ ; /* 0x000090ff03007387 */
/* 0x0003e80000100c00 */
/*01a0*/ STL.128 [R3+0xa0], RZ ; /* 0x0000a0ff03007387 */
/* 0x0003e80000100c00 */
/*01b0*/ STL.128 [R3+0xb0], RZ ; /* 0x0000b0ff03007387 */
/* 0x0003e80000100c00 */
/*01c0*/ STL.128 [R3+0xc0], RZ ; /* 0x0000c0ff03007387 */
/* 0x0003e80000100c00 */
/*01d0*/ STL.128 [R3+0xd0], RZ ; /* 0x0000d0ff03007387 */
/* 0x0003e80000100c00 */
/*01e0*/ STL.128 [R3+0xe0], RZ ; /* 0x0000e0ff03007387 */
/* 0x0003e80000100c00 */
/*01f0*/ STL.128 [R3+0xf0], RZ ; /* 0x0000f0ff03007387 */
/* 0x0003e80000100c00 */
/*0200*/ STL.128 [R3+0x100], RZ ; /* 0x000100ff03007387 */
/* 0x0003e80000100c00 */
/*0210*/ STL.128 [R3+0x110], RZ ; /* 0x000110ff03007387 */
/* 0x0003e80000100c00 */
/*0220*/ STL.128 [R3+0x120], RZ ; /* 0x000120ff03007387 */
/* 0x0003e80000100c00 */
/*0230*/ STL.128 [R3+0x130], RZ ; /* 0x000130ff03007387 */
/* 0x0003e80000100c00 */
/*0240*/ STL.128 [R3+0x140], RZ ; /* 0x000140ff03007387 */
/* 0x0003e20000100c00 */
/*0250*/ @!P0 BRA 0xc0 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*0260*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fc800078e00ff */
/*0270*/ IMAD.WIDE R2, R5, R10, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x002fca00078e020a */
/*0280*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0290*/ BSSY B0, 0x5f0 ; /* 0x0000035000007945 */
/* 0x000fe20003800000 */
/*02a0*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fe20000011405 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*02c0*/ IADD3 R8, R1, 0x9c40, RZ ; /* 0x00009c4001087810 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x004fda0003f06270 */
/*02e0*/ @!P0 BRA 0x5e0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD R9, R5, 0x157, RZ ; /* 0x0000015705097824 */
/* 0x000fe200078e02ff */
/*0300*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*0320*/ IMAD.WIDE R2, R9, R10, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x000fc800078e020a */
/*0330*/ IMAD.IADD R12, R9, 0x1, R4 ; /* 0x00000001090c7824 */
/* 0x002fe400078e0204 */
/*0340*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc800078e00ff */
/*0350*/ IMAD.WIDE R12, R12, R15, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fcc00078e020f */
/*0360*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea4000c1e1900 */
/*0370*/ IADD3 R14, R13, -0x1, RZ ; /* 0xffffffff0d0e7810 */
/* 0x004fca0007ffe0ff */
/*0380*/ IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fca00078e020f */
/*0390*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x000ea2000c1e1900 */
/*03a0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ BSSY B1, 0x5d0 ; /* 0x0000021000017945 */
/* 0x000fe60003800000 */
/*03c0*/ ISETP.GE.AND P0, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe40003f06270 */
/*03d0*/ ISETP.GE.AND P1, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x004fda0003f26270 */
/*03e0*/ @!P1 BRA 0x5c0 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x157 ; /* 0x00000157ff0c7424 */
/* 0x000fe400078e00ff */
/*0400*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0410*/ IMAD R19, R13, R12, -0x157 ; /* 0xfffffea90d137424 */
/* 0x000fc800078e020c */
/*0420*/ IMAD.IADD R12, R19, 0x1, R10 ; /* 0x00000001130c7824 */
/* 0x002fe400078e020a */
/*0430*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0440*/ IMAD.WIDE R12, R12, R13, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fca00078e020d */
/*0450*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000362000c1e1900 */
/*0460*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe20007ffe0ff */
/*0470*/ BSSY B2, 0x5b0 ; /* 0x0000013000027945 */
/* 0x000fe20003800000 */
/*0480*/ MOV R15, R2 ; /* 0x00000002000f7202 */
/* 0x000fe20000000f00 */
/*0490*/ IMAD.MOV.U32 R16, RZ, RZ, R3 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0003 */
/*04a0*/ ISETP.GE.AND P1, PT, R10, R17, PT ; /* 0x000000110a00720c */
/* 0x000fe20003f26270 */
/*04b0*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*04c0*/ IMAD.MOV.U32 R12, RZ, RZ, R15 ; /* 0x000000ffff0c7224 */
/* 0x002fe400078e000f */
/*04d0*/ IMAD.MOV.U32 R13, RZ, RZ, R16 ; /* 0x000000ffff0d7224 */
/* 0x000fca00078e0010 */
/*04e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ ISETP.NE.AND P2, PT, R12, R21, PT ; /* 0x000000150c00720c */
/* 0x024fda0003f45270 */
/*0500*/ @!P2 BRA 0x570 ; /* 0x000000600000a947 */
/* 0x000fea0003800000 */
/*0510*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe40007ffe0ff */
/*0520*/ IADD3 R15, P3, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe40007f7e0ff */
/*0530*/ ISETP.GE.AND P2, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fc60003f46270 */
/*0540*/ IMAD.X R16, RZ, RZ, R16, P3 ; /* 0x000000ffff107224 */
/* 0x000fd400018e0610 */
/*0550*/ @!P2 BRA 0x4c0 ; /* 0xffffff600000a947 */
/* 0x000fea000383ffff */
/*0560*/ BRA 0x5a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD R12, R7.reuse, 0x4, R0 ; /* 0x00000004070c7824 */
/* 0x040fe200078e0200 */
/*0580*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fc80007ffe0ff */
/*0590*/ STL [R12], R21 ; /* 0x000000150c007387 */
/* 0x0003e60000100800 */
/*05a0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05b0*/ @!P1 BRA 0x420 ; /* 0xfffffe6000009947 */
/* 0x000fea000383ffff */
/*05c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05d0*/ @!P0 BRA 0x330 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ STL.128 [R1+0x9c40], RZ ; /* 0x009c40ff01007387 */
/* 0x0005e20000100c00 */
/*0600*/ HFMA2.MMA R3, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff037435 */
/* 0x000fe200000001ff */
/*0610*/ IADD3 R2, R1, 0x9c80, RZ ; /* 0x00009c8001027810 */
/* 0x000fe20007ffe0ff */
/*0620*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe200078e00ff */
/*0630*/ STL.128 [R1+0x9c50], RZ ; /* 0x009c50ff01007387 */
/* 0x0005e80000100c00 */
/*0640*/ STL.128 [R1+0x9c60], RZ ; /* 0x009c60ff01007387 */
/* 0x0005e80000100c00 */
/*0650*/ STL.128 [R1+0x9c70], RZ ; /* 0x009c70ff01007387 */
/* 0x0005e40000100c00 */
/*0660*/ IADD3 R3, P0, R3, 0x9c, RZ ; /* 0x0000009c03037810 */
/* 0x000fe20007f1e0ff */
/*0670*/ STL.128 [R2], RZ ; /* 0x000000ff02007387 */
/* 0x000fe80000100c00 */
/*0680*/ IMAD.X R4, RZ, RZ, R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0604 */
/*0690*/ ISETP.GE.U32.AND P0, PT, R3, 0x2710, PT ; /* 0x000027100300780c */
/* 0x000fe20003f06070 */
/*06a0*/ STL.128 [R2+0x10], RZ ; /* 0x000010ff02007387 */
/* 0x000fe60000100c00 */
/*06b0*/ ISETP.GE.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fe20003f06100 */
/*06c0*/ STL.128 [R2+0x20], RZ ; /* 0x000020ff02007387 */
/* 0x000fe80000100c00 */
/*06d0*/ STL.128 [R2+0x30], RZ ; /* 0x000030ff02007387 */
/* 0x000fe80000100c00 */
/*06e0*/ STL.128 [R2+0x40], RZ ; /* 0x000040ff02007387 */
/* 0x000fe80000100c00 */
/*06f0*/ STL.128 [R2+0x50], RZ ; /* 0x000050ff02007387 */
/* 0x000fe80000100c00 */
/*0700*/ STL.128 [R2+0x60], RZ ; /* 0x000060ff02007387 */
/* 0x000fe80000100c00 */
/*0710*/ STL.128 [R2+0x70], RZ ; /* 0x000070ff02007387 */
/* 0x000fe80000100c00 */
/*0720*/ STL.128 [R2+0x80], RZ ; /* 0x000080ff02007387 */
/* 0x000fe80000100c00 */
/*0730*/ STL.128 [R2+0x90], RZ ; /* 0x000090ff02007387 */
/* 0x000fe80000100c00 */
/*0740*/ STL.128 [R2+0xa0], RZ ; /* 0x0000a0ff02007387 */
/* 0x000fe80000100c00 */
/*0750*/ STL.128 [R2+0xb0], RZ ; /* 0x0000b0ff02007387 */
/* 0x000fe80000100c00 */
/*0760*/ STL.128 [R2+0xc0], RZ ; /* 0x0000c0ff02007387 */
/* 0x000fe80000100c00 */
/*0770*/ STL.128 [R2+0xd0], RZ ; /* 0x0000d0ff02007387 */
/* 0x000fe80000100c00 */
/*0780*/ STL.128 [R2+0xe0], RZ ; /* 0x0000e0ff02007387 */
/* 0x000fe80000100c00 */
/*0790*/ STL.128 [R2+0xf0], RZ ; /* 0x0000f0ff02007387 */
/* 0x000fe80000100c00 */
/*07a0*/ STL.128 [R2+0x100], RZ ; /* 0x000100ff02007387 */
/* 0x000fe80000100c00 */
/*07b0*/ STL.128 [R2+0x110], RZ ; /* 0x000110ff02007387 */
/* 0x000fe80000100c00 */
/*07c0*/ STL.128 [R2+0x120], RZ ; /* 0x000120ff02007387 */
/* 0x000fe80000100c00 */
/*07d0*/ STL.128 [R2+0x130], RZ ; /* 0x000130ff02007387 */
/* 0x000fe80000100c00 */
/*07e0*/ STL.128 [R2+0x140], RZ ; /* 0x000140ff02007387 */
/* 0x000fe80000100c00 */
/*07f0*/ STL.128 [R2+0x150], RZ ; /* 0x000150ff02007387 */
/* 0x000fe80000100c00 */
/*0800*/ STL.128 [R2+0x160], RZ ; /* 0x000160ff02007387 */
/* 0x000fe80000100c00 */
/*0810*/ STL.128 [R2+0x170], RZ ; /* 0x000170ff02007387 */
/* 0x000fe80000100c00 */
/*0820*/ STL.128 [R2+0x180], RZ ; /* 0x000180ff02007387 */
/* 0x000fe80000100c00 */
/*0830*/ STL.128 [R2+0x190], RZ ; /* 0x000190ff02007387 */
/* 0x000fe80000100c00 */
/*0840*/ STL.128 [R2+0x1a0], RZ ; /* 0x0001a0ff02007387 */
/* 0x000fe80000100c00 */
/*0850*/ STL.128 [R2+0x1b0], RZ ; /* 0x0001b0ff02007387 */
/* 0x000fe80000100c00 */
/*0860*/ STL.128 [R2+0x1c0], RZ ; /* 0x0001c0ff02007387 */
/* 0x000fe80000100c00 */
/*0870*/ STL.128 [R2+0x1d0], RZ ; /* 0x0001d0ff02007387 */
/* 0x000fe80000100c00 */
/*0880*/ STL.128 [R2+0x1e0], RZ ; /* 0x0001e0ff02007387 */
/* 0x000fe80000100c00 */
/*0890*/ STL.128 [R2+0x1f0], RZ ; /* 0x0001f0ff02007387 */
/* 0x000fe80000100c00 */
/*08a0*/ STL.128 [R2+0x200], RZ ; /* 0x000200ff02007387 */
/* 0x000fe80000100c00 */
/*08b0*/ STL.128 [R2+0x210], RZ ; /* 0x000210ff02007387 */
/* 0x000fe80000100c00 */
/*08c0*/ STL.128 [R2+0x220], RZ ; /* 0x000220ff02007387 */
/* 0x000fe80000100c00 */
/*08d0*/ STL.128 [R2+0x230], RZ ; /* 0x000230ff02007387 */
/* 0x000fe80000100c00 */
/*08e0*/ STL.128 [R2+0x240], RZ ; /* 0x000240ff02007387 */
/* 0x000fe80000100c00 */
/*08f0*/ STL.128 [R2+0x250], RZ ; /* 0x000250ff02007387 */
/* 0x000fe80000100c00 */
/*0900*/ STL.128 [R2+0x260], RZ ; /* 0x000260ff02007387 */
/* 0x0007e40000100c00 */
/*0910*/ IADD3 R2, R2, 0x270, RZ ; /* 0x0000027002027810 */
/* 0x008fe20007ffe0ff */
/*0920*/ @!P0 BRA 0x660 ; /* 0xfffffd3000008947 */
/* 0x000fea000383ffff */
/*0930*/ LDL R2, [R1] ; /* 0x0000000001027983 */
/* 0x000ee20000100800 */
/*0940*/ ISETP.GE.AND P0, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe20003f06270 */
/*0950*/ BSSY B0, 0xb60 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*0970*/ STL [R1+0x9c40], R2 ; /* 0x009c400201007387 */
/* 0x0087f40000100800 */
/*0980*/ @!P0 BRA 0xb50 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0990*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x008fe400078e00ff */
/*09a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fca00078e00ff */
/*09b0*/ ISETP.GE.AND P1, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fe20003f26270 */
/*09c0*/ BSSY B1, 0xac0 ; /* 0x000000f000017945 */
/* 0x000fe20003800000 */
/*09d0*/ LEA R4, R2.reuse, R0, 0x2 ; /* 0x0000000002047211 */
/* 0x042fe200078e10ff */
/*09e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*09f0*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*0a00*/ ISETP.GE.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fca0003f06270 */
/*0a10*/ @!P1 BRA 0xab0 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*0a20*/ LDL R12, [R4] ; /* 0x00000000040c7983 */
/* 0x0023620000100800 */
/*0a30*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e00ff */
/*0a40*/ IMAD R9, R10, 0x4, R8 ; /* 0x000000040a097824 */
/* 0x000fcc00078e0208 */
/*0a50*/ LDL R9, [R9] ; /* 0x0000000009097983 */
/* 0x000ee40000100800 */
/*0a60*/ ISETP.NE.AND P1, PT, R12, R9, PT ; /* 0x000000090c00720c */
/* 0x028fda0003f25270 */
/*0a70*/ @!P1 BRA 0xab0 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0a80*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.GE.AND P1, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f26270 */
/*0aa0*/ @!P1 BRA 0xa40 ; /* 0xffffff9000009947 */
/* 0x000fea000383ffff */
/*0ab0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ac0*/ ISETP.NE.AND P1, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fe20003f25270 */
/*0ad0*/ BSSY B1, 0xb40 ; /* 0x0000006000017945 */
/* 0x000fd80003800000 */
/*0ae0*/ @P1 BRA 0xb30 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0af0*/ LDL R4, [R4] ; /* 0x0000000004047983 */
/* 0x002ee20000100800 */
/*0b00*/ IMAD R9, R3.reuse, 0x4, R8 ; /* 0x0000000403097824 */
/* 0x040fe200078e0208 */
/*0b10*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0b20*/ STL [R9], R4 ; /* 0x0000000409007387 */
/* 0x0083e60000100800 */
/*0b30*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0b40*/ @!P0 BRA 0x9b0 ; /* 0xfffffe6000008947 */
/* 0x000fea000383ffff */
/*0b50*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b60*/ LEA R4, P0, R5, c[0x0][0x170], 0x2 ; /* 0x00005c0005047a11 */
/* 0x002fc800078010ff */
/*0b70*/ LEA.HI.X R5, R5, c[0x0][0x174], R6, 0x2, P0 ; /* 0x00005d0005057a11 */
/* 0x000fca00000f1406 */
/*0b80*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13dataset_parsePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x100509, PT ; /* 0x001005090000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*0070*/ SHF.L.U32 R2, R0, 0x1, RZ ; /* 0x0000000100027819 */
/* 0x000fe200000006ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R15, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e020f */
/*00a0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ HFMA2.MMA R17, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff117435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x004fca0007ffe0ff */
/*00d0*/ IMAD.WIDE R4, R0, R15, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e020f */
/*00e0*/ ATOMG.E.ADD.STRONG.GPU PT, R4, [R4.64], R17 ; /* 0x00000011040479a8 */
/* 0x000ea800081ee1c4 */
/*00f0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee2000c1e1900 */
/*0110*/ IMAD R7, R7, 0x157, R4 ; /* 0x0000015707077824 */
/* 0x004fca00078e0204 */
/*0120*/ IADD3 R7, R7, -0x157, RZ ; /* 0xfffffea907077810 */
/* 0x000fca0007ffe0ff */
/*0130*/ IMAD.WIDE R6, R7, R15, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fca00078e020f */
/*0140*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x008fe8000c101904 */
/*0150*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0160*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x004fca0007ffe0ff */
/*0170*/ IMAD.WIDE R8, R0, R15, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e020f */
/*0180*/ ATOMG.E.ADD.STRONG.GPU PT, R8, [R8.64], R17 ; /* 0x00000011080879a8 */
/* 0x000ea800081ee1c4 */
/*0190*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ee2000c1e1900 */
/*01b0*/ IMAD R5, R5, 0x157, R8 ; /* 0x0000015705057824 */
/* 0x004fca00078e0208 */
/*01c0*/ IADD3 R5, R5, -0x157, RZ ; /* 0xfffffea905057810 */
/* 0x000fca0007ffe0ff */
/*01d0*/ IMAD.WIDE R4, R5, R15, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e020f */
/*01e0*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x008fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#define FILENAME "./dblp-co-authors.txt"
#define NumAuthor 317080
#define DataLen 1049866
#define BlockSize 1024
#define GridSize int(DataLen/BlockSize) + 1
#define MAX 343
#define newGridSize int(NumAuthor/BlockSize) + 1
int dataset[DataLen * 2];// array to store the raw dataset
void dataset_read(int * dataset);
__global__ void dataset_parse(int * dataset, int * output, int * full_output);
//int dataset_maxCoAuthor(int * output, int lenght);
//void dataset_plot(int * output, int lenght, int max);
__global__ void output_parse(int * full_output, int * output, int * num_author_array);
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len);
__device__ void count_diff_auth(int * pair_array, int * new_array,int pair_len, int * pure_len, int indx);
int main(int argc, char * argv[])
{
int output[NumAuthor] = {0};
int full_output[MAX * NumAuthor] = { 0 };
int * cu_output;//array to store the co-authors number of each author
int * cu_full_output;
dataset_read(dataset);
// Set device that we will use for our cuda code
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
float time;
int * cu_dataset;
cudaEventRecord(start,0);
cudaMalloc((void**)&cu_output, NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_full_output, MAX * NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_dataset, DataLen * 2 * sizeof(int));
cudaMemcpy(cu_dataset, dataset, DataLen * 2 * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(cu_full_output, full_output, MAX * NumAuthor * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(cu_output, output, NumAuthor * sizeof(int), cudaMemcpyHostToDevice);
dataset_parse<<<GridSize, BlockSize>>>(cu_dataset, cu_output, cu_full_output);
cudaDeviceSynchronize();
cudaMemcpy(output, cu_output, NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(full_output, cu_full_output, MAX * NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
//int max = dataset_maxCoAuthor(output, NumAuthor);
//printf("Time elapsed: %f\n", time);
int * cu_num_author_array;
int * num_author_array = (int*)malloc(NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_num_author_array, NumAuthor * sizeof(int));
cudaMemset(cu_num_author_array, 0, NumAuthor * sizeof(int));
cudaEventRecord(start,0);
output_parse<<<newGridSize, BlockSize>>>(cu_full_output, cu_output, cu_num_author_array);
cudaDeviceSynchronize();
printf("Error in Kernel output_parse:%s\n",cudaGetErrorString(cudaGetLastError()));
cudaDeviceSynchronize();
cudaMemcpy(num_author_array, cu_num_author_array, NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time in Kernel output_parse: %f\n", time);
int total_number = 0;
for (int i = 0; i < NumAuthor; i++)
total_number += num_author_array[i];
printf("Total number of authors is %d\n", total_number/2);
return 0;
}
void dataset_read( int * dataset)
{
FILE * datafile;
datafile = fopen( FILENAME, "r");
char line[255];
while (true)
{
fscanf(datafile, "%s", line);
if (atoi(line) == 1)
{
dataset[0] = 1;
break;
}
}
for(int i = 1; i < 2 * DataLen; i++){
fscanf(datafile, "%d", &dataset[i]);
}
fclose(datafile);
}
__global__ void dataset_parse(int * dataset, int * output, int * full_output)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
int i, j;
if(indx < DataLen){
i = atomicAdd(&(output[dataset[2*indx]-1]), 1);
full_output[(dataset[2*indx]-1) * MAX + i] = dataset[2*indx+1];
j = atomicAdd(&(output[dataset[2*indx+1]-1]), 1);
full_output[(dataset[2*indx + 1]-1) * MAX + j] = dataset[2*indx];
}
}
/*
int dataset_maxCoAuthor(int * output, int lenght)
{
int max =0;
int max_num = 0;
int max_ind[1000] = { 0 };
//memset(max_ind, 0, 1000);
for(int i = 0; i < lenght; i++)
{
//printf("output:%d, %d", i, output[i]);
if(max < output[i])
{
// printf("Max right now:%d, %d\n", i, output[i]);
max = output[i];
max_num = 0;
memset(max_ind, 0, 1000);
max_ind[max_num] = i;
}
else if(max == output[i])
{
max_num++;
max_ind[max_num] = i;
}
//else{
//printf("max is:%d, %d\n", max, max_ind[0]);
//}
}
printf("The list of authors with most co-authors:\n");
for(int i = 0; i <= max_num; i++)
{
printf("Author: %6d has %6d co-authors.\n", max_ind[i] + 1, output[max_ind[i]]);
}
return output[max_ind[0]];
}
void dataset_plot(int * output, int lenght, int max)
{
//int* numCoAuthorList;
int* numCoAuthorList = (int*)malloc(max * sizeof(int));
memset(numCoAuthorList, 0, max);
for(int i = 0; i < lenght; i++)
{
if(output[i] <= max)
{
numCoAuthorList[output[i] - 1]++;
}
else{
printf("\nError in Finding MAX!!!\n");
}
}
FILE *fp;
fp = fopen("./output.txt", "wb");
fwrite(numCoAuthorList, sizeof(int), max, fp);
fclose(fp);
}
*/
__global__ void output_parse(int * full_output, int * output, int * num_author_array)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
if(indx < NumAuthor){
int pair_array[10000] = { 0 };
int pair_len = 0;
int coauthor, coauthor_co_len, possible_pair;
for(int i = 0; i < output[indx]; i++){
coauthor = full_output[indx * MAX + i];
coauthor_co_len = output[coauthor-1];
for(int j = 0; j < coauthor_co_len; j++){
possible_pair = full_output[(coauthor - 1) * MAX + j];
check_pair(full_output, indx * MAX, output[indx], possible_pair, pair_array, &pair_len);
}
}
//int * new_array = (int*)malloc(pair_len * sizeof(int));
//memset(new_array, 0, pair_len );
int new_array[10000] = {0};
int num_authors = 0;
count_diff_auth(pair_array, new_array, pair_len, &num_authors, indx);
num_author_array[indx] = num_authors;
}
}
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len){
for(int i = 0; i < len; i++){
if(full_output[start + i] == possible_pair){
pair_array[*pair_len] = possible_pair;
(*pair_len)++;
break;
}
}
}
__device__ void count_diff_auth(int * pair_array,int * new_array, int pair_len, int * pure_len, int indx){
//int * new_array;
//cudaMalloc((void**)&new_array, pair_len * sizeof(int));
//cudaMemset(new_array, 0, pair_len * sizeof(int));
//printf("pair_array[0]:%d, pair_len:%d, %d\n",pair_array[0], pair_len, indx);
new_array[0] = pair_array[0];
*pure_len = 1;
for(int i = 1; i < pair_len; i++){
int j;
for(j = 0; j< *pure_len; j++){
if(pair_array[i] == new_array[j]){
break;
}
}
if (j == *pure_len){
new_array[*pure_len] = pair_array[i];
(*pure_len)++;
}
}
} | .file "tmpxft_000d3a5c_00000000-6_Q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./dblp-co-authors.txt"
.LC2:
.string "%s"
.LC3:
.string "%d"
.text
.globl _Z12dataset_readPi
.type _Z12dataset_readPi, @function
_Z12dataset_readPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $280, %rsp
.cfi_def_cfa_offset 320
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %r13
.L4:
movq %rsp, %rbx
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
cmpl $1, %eax
jne .L4
movl $1, (%r12)
leaq 4(%r12), %rbx
addq $8398928, %r12
leaq .LC3(%rip), %r13
.L5:
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
movq %rbp, %rdi
call fclose@PLT
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12dataset_readPi, .-_Z12dataset_readPi
.globl _Z10check_pairPiiiiS_S_
.type _Z10check_pairPiiiiS_S_, @function
_Z10check_pairPiiiiS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10check_pairPiiiiS_S_, .-_Z10check_pairPiiiiS_S_
.globl _Z15count_diff_authPiS_iS_i
.type _Z15count_diff_authPiS_iS_i, @function
_Z15count_diff_authPiS_iS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z15count_diff_authPiS_iS_i, .-_Z15count_diff_authPiS_iS_i
.globl _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
.type _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_, @function
_Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13dataset_parsePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_, .-_Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
.globl _Z13dataset_parsePiS_S_
.type _Z13dataset_parsePiS_S_, @function
_Z13dataset_parsePiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13dataset_parsePiS_S_, .-_Z13dataset_parsePiS_S_
.globl _Z36__device_stub__Z12output_parsePiS_S_PiS_S_
.type _Z36__device_stub__Z12output_parsePiS_S_PiS_S_, @function
_Z36__device_stub__Z12output_parsePiS_S_PiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12output_parsePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z36__device_stub__Z12output_parsePiS_S_PiS_S_, .-_Z36__device_stub__Z12output_parsePiS_S_PiS_S_
.globl _Z12output_parsePiS_S_
.type _Z12output_parsePiS_S_, @function
_Z12output_parsePiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12output_parsePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12output_parsePiS_S_, .-_Z12output_parsePiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error in Kernel output_parse:%s\n"
.align 8
.LC5:
.string "Elapsed time in Kernel output_parse: %f\n"
.align 8
.LC6:
.string "Total number of authors is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -436301824(%rsp), %r11
.cfi_def_cfa 11, 436301856
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $352, %rsp
.cfi_def_cfa_offset 436302208
movq %fs:40, %rax
movq %rax, 436302168(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbx
movl $1268320, %edx
movl $0, %esi
movq %rbx, %rdi
call memset@PLT
leaq 1268400(%rsp), %rbp
movl $435033760, %edx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
leaq dataset(%rip), %r12
movq %r12, %rdi
call _Z12dataset_readPi
movl $0, %edi
call cudaSetDevice@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8(%rsp), %rdi
movl $1268320, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $435033760, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8398928, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8398928, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $435033760, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1268320, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1026, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L32:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $1268320, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq 1268400(%rsp), %rdi
movl $2, %ecx
movl $435033760, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $1268320, %edi
call malloc@PLT
movq %rax, %rbx
leaq 48(%rsp), %rdi
movl $1268320, %esi
call cudaMalloc@PLT
movl $1268320, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $310, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $1268320, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rax
leaq 1268320(%rbx), %rsi
movl $0, %ecx
.L34:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L34
movl %ecx, %eax
shrl $31, %eax
addl %eax, %edx
sarl %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 436302168(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $436302176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
jmp .L32
.L39:
movq 48(%rsp), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z12output_parsePiS_S_PiS_S_
jmp .L33
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12output_parsePiS_S_"
.LC8:
.string "_Z13dataset_parsePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12output_parsePiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dataset_parsePiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dataset
.bss
.align 32
.type dataset, @object
.size dataset, 8398928
dataset:
.zero 8398928
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#define FILENAME "./dblp-co-authors.txt"
#define NumAuthor 317080
#define DataLen 1049866
#define BlockSize 1024
#define GridSize int(DataLen/BlockSize) + 1
#define MAX 343
#define newGridSize int(NumAuthor/BlockSize) + 1
int dataset[DataLen * 2];// array to store the raw dataset
void dataset_read(int * dataset);
__global__ void dataset_parse(int * dataset, int * output, int * full_output);
//int dataset_maxCoAuthor(int * output, int lenght);
//void dataset_plot(int * output, int lenght, int max);
__global__ void output_parse(int * full_output, int * output, int * num_author_array);
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len);
__device__ void count_diff_auth(int * pair_array, int * new_array,int pair_len, int * pure_len, int indx);
int main(int argc, char * argv[])
{
int output[NumAuthor] = {0};
int full_output[MAX * NumAuthor] = { 0 };
int * cu_output;//array to store the co-authors number of each author
int * cu_full_output;
dataset_read(dataset);
// Set device that we will use for our cuda code
cudaSetDevice(0);
// Time Variables
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
float time;
int * cu_dataset;
cudaEventRecord(start,0);
cudaMalloc((void**)&cu_output, NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_full_output, MAX * NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_dataset, DataLen * 2 * sizeof(int));
cudaMemcpy(cu_dataset, dataset, DataLen * 2 * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(cu_full_output, full_output, MAX * NumAuthor * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(cu_output, output, NumAuthor * sizeof(int), cudaMemcpyHostToDevice);
dataset_parse<<<GridSize, BlockSize>>>(cu_dataset, cu_output, cu_full_output);
cudaDeviceSynchronize();
cudaMemcpy(output, cu_output, NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(full_output, cu_full_output, MAX * NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
//int max = dataset_maxCoAuthor(output, NumAuthor);
//printf("Time elapsed: %f\n", time);
int * cu_num_author_array;
int * num_author_array = (int*)malloc(NumAuthor * sizeof(int));
cudaMalloc((void**)&cu_num_author_array, NumAuthor * sizeof(int));
cudaMemset(cu_num_author_array, 0, NumAuthor * sizeof(int));
cudaEventRecord(start,0);
output_parse<<<newGridSize, BlockSize>>>(cu_full_output, cu_output, cu_num_author_array);
cudaDeviceSynchronize();
printf("Error in Kernel output_parse:%s\n",cudaGetErrorString(cudaGetLastError()));
cudaDeviceSynchronize();
cudaMemcpy(num_author_array, cu_num_author_array, NumAuthor * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time in Kernel output_parse: %f\n", time);
int total_number = 0;
for (int i = 0; i < NumAuthor; i++)
total_number += num_author_array[i];
printf("Total number of authors is %d\n", total_number/2);
return 0;
}
void dataset_read( int * dataset)
{
FILE * datafile;
datafile = fopen( FILENAME, "r");
char line[255];
while (true)
{
fscanf(datafile, "%s", line);
if (atoi(line) == 1)
{
dataset[0] = 1;
break;
}
}
for(int i = 1; i < 2 * DataLen; i++){
fscanf(datafile, "%d", &dataset[i]);
}
fclose(datafile);
}
__global__ void dataset_parse(int * dataset, int * output, int * full_output)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
int i, j;
if(indx < DataLen){
i = atomicAdd(&(output[dataset[2*indx]-1]), 1);
full_output[(dataset[2*indx]-1) * MAX + i] = dataset[2*indx+1];
j = atomicAdd(&(output[dataset[2*indx+1]-1]), 1);
full_output[(dataset[2*indx + 1]-1) * MAX + j] = dataset[2*indx];
}
}
/*
int dataset_maxCoAuthor(int * output, int lenght)
{
int max =0;
int max_num = 0;
int max_ind[1000] = { 0 };
//memset(max_ind, 0, 1000);
for(int i = 0; i < lenght; i++)
{
//printf("output:%d, %d", i, output[i]);
if(max < output[i])
{
// printf("Max right now:%d, %d\n", i, output[i]);
max = output[i];
max_num = 0;
memset(max_ind, 0, 1000);
max_ind[max_num] = i;
}
else if(max == output[i])
{
max_num++;
max_ind[max_num] = i;
}
//else{
//printf("max is:%d, %d\n", max, max_ind[0]);
//}
}
printf("The list of authors with most co-authors:\n");
for(int i = 0; i <= max_num; i++)
{
printf("Author: %6d has %6d co-authors.\n", max_ind[i] + 1, output[max_ind[i]]);
}
return output[max_ind[0]];
}
void dataset_plot(int * output, int lenght, int max)
{
//int* numCoAuthorList;
int* numCoAuthorList = (int*)malloc(max * sizeof(int));
memset(numCoAuthorList, 0, max);
for(int i = 0; i < lenght; i++)
{
if(output[i] <= max)
{
numCoAuthorList[output[i] - 1]++;
}
else{
printf("\nError in Finding MAX!!!\n");
}
}
FILE *fp;
fp = fopen("./output.txt", "wb");
fwrite(numCoAuthorList, sizeof(int), max, fp);
fclose(fp);
}
*/
__global__ void output_parse(int * full_output, int * output, int * num_author_array)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
if(indx < NumAuthor){
int pair_array[10000] = { 0 };
int pair_len = 0;
int coauthor, coauthor_co_len, possible_pair;
for(int i = 0; i < output[indx]; i++){
coauthor = full_output[indx * MAX + i];
coauthor_co_len = output[coauthor-1];
for(int j = 0; j < coauthor_co_len; j++){
possible_pair = full_output[(coauthor - 1) * MAX + j];
check_pair(full_output, indx * MAX, output[indx], possible_pair, pair_array, &pair_len);
}
}
//int * new_array = (int*)malloc(pair_len * sizeof(int));
//memset(new_array, 0, pair_len );
int new_array[10000] = {0};
int num_authors = 0;
count_diff_auth(pair_array, new_array, pair_len, &num_authors, indx);
num_author_array[indx] = num_authors;
}
}
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len){
for(int i = 0; i < len; i++){
if(full_output[start + i] == possible_pair){
pair_array[*pair_len] = possible_pair;
(*pair_len)++;
break;
}
}
}
__device__ void count_diff_auth(int * pair_array,int * new_array, int pair_len, int * pure_len, int indx){
//int * new_array;
//cudaMalloc((void**)&new_array, pair_len * sizeof(int));
//cudaMemset(new_array, 0, pair_len * sizeof(int));
//printf("pair_array[0]:%d, pair_len:%d, %d\n",pair_array[0], pair_len, indx);
new_array[0] = pair_array[0];
*pure_len = 1;
for(int i = 1; i < pair_len; i++){
int j;
for(j = 0; j< *pure_len; j++){
if(pair_array[i] == new_array[j]){
break;
}
}
if (j == *pure_len){
new_array[*pure_len] = pair_array[i];
(*pure_len)++;
}
}
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define FILENAME "./dblp-co-authors.txt"
#define NumAuthor 317080
#define DataLen 1049866
#define BlockSize 1024
#define GridSize int(DataLen/BlockSize) + 1
#define MAX 343
#define newGridSize int(NumAuthor/BlockSize) + 1
int dataset[DataLen * 2];// array to store the raw dataset
void dataset_read(int * dataset);
__global__ void dataset_parse(int * dataset, int * output, int * full_output);
//int dataset_maxCoAuthor(int * output, int lenght);
//void dataset_plot(int * output, int lenght, int max);
__global__ void output_parse(int * full_output, int * output, int * num_author_array);
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len);
__device__ void count_diff_auth(int * pair_array, int * new_array,int pair_len, int * pure_len, int indx);
int main(int argc, char * argv[])
{
int output[NumAuthor] = {0};
int full_output[MAX * NumAuthor] = { 0 };
int * cu_output;//array to store the co-authors number of each author
int * cu_full_output;
dataset_read(dataset);
// Set device that we will use for our cuda code
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
float time;
int * cu_dataset;
hipEventRecord(start,0);
hipMalloc((void**)&cu_output, NumAuthor * sizeof(int));
hipMalloc((void**)&cu_full_output, MAX * NumAuthor * sizeof(int));
hipMalloc((void**)&cu_dataset, DataLen * 2 * sizeof(int));
hipMemcpy(cu_dataset, dataset, DataLen * 2 * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(cu_full_output, full_output, MAX * NumAuthor * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(cu_output, output, NumAuthor * sizeof(int), hipMemcpyHostToDevice);
dataset_parse<<<GridSize, BlockSize>>>(cu_dataset, cu_output, cu_full_output);
hipDeviceSynchronize();
hipMemcpy(output, cu_output, NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(full_output, cu_full_output, MAX * NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
//int max = dataset_maxCoAuthor(output, NumAuthor);
//printf("Time elapsed: %f\n", time);
int * cu_num_author_array;
int * num_author_array = (int*)malloc(NumAuthor * sizeof(int));
hipMalloc((void**)&cu_num_author_array, NumAuthor * sizeof(int));
hipMemset(cu_num_author_array, 0, NumAuthor * sizeof(int));
hipEventRecord(start,0);
output_parse<<<newGridSize, BlockSize>>>(cu_full_output, cu_output, cu_num_author_array);
hipDeviceSynchronize();
printf("Error in Kernel output_parse:%s\n",hipGetErrorString(hipGetLastError()));
hipDeviceSynchronize();
hipMemcpy(num_author_array, cu_num_author_array, NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time in Kernel output_parse: %f\n", time);
int total_number = 0;
for (int i = 0; i < NumAuthor; i++)
total_number += num_author_array[i];
printf("Total number of authors is %d\n", total_number/2);
return 0;
}
void dataset_read( int * dataset)
{
FILE * datafile;
datafile = fopen( FILENAME, "r");
char line[255];
while (true)
{
fscanf(datafile, "%s", line);
if (atoi(line) == 1)
{
dataset[0] = 1;
break;
}
}
for(int i = 1; i < 2 * DataLen; i++){
fscanf(datafile, "%d", &dataset[i]);
}
fclose(datafile);
}
__global__ void dataset_parse(int * dataset, int * output, int * full_output)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
int i, j;
if(indx < DataLen){
i = atomicAdd(&(output[dataset[2*indx]-1]), 1);
full_output[(dataset[2*indx]-1) * MAX + i] = dataset[2*indx+1];
j = atomicAdd(&(output[dataset[2*indx+1]-1]), 1);
full_output[(dataset[2*indx + 1]-1) * MAX + j] = dataset[2*indx];
}
}
/*
int dataset_maxCoAuthor(int * output, int lenght)
{
int max =0;
int max_num = 0;
int max_ind[1000] = { 0 };
//memset(max_ind, 0, 1000);
for(int i = 0; i < lenght; i++)
{
//printf("output:%d, %d", i, output[i]);
if(max < output[i])
{
// printf("Max right now:%d, %d\n", i, output[i]);
max = output[i];
max_num = 0;
memset(max_ind, 0, 1000);
max_ind[max_num] = i;
}
else if(max == output[i])
{
max_num++;
max_ind[max_num] = i;
}
//else{
//printf("max is:%d, %d\n", max, max_ind[0]);
//}
}
printf("The list of authors with most co-authors:\n");
for(int i = 0; i <= max_num; i++)
{
printf("Author: %6d has %6d co-authors.\n", max_ind[i] + 1, output[max_ind[i]]);
}
return output[max_ind[0]];
}
void dataset_plot(int * output, int lenght, int max)
{
//int* numCoAuthorList;
int* numCoAuthorList = (int*)malloc(max * sizeof(int));
memset(numCoAuthorList, 0, max);
for(int i = 0; i < lenght; i++)
{
if(output[i] <= max)
{
numCoAuthorList[output[i] - 1]++;
}
else{
printf("\nError in Finding MAX!!!\n");
}
}
FILE *fp;
fp = fopen("./output.txt", "wb");
fwrite(numCoAuthorList, sizeof(int), max, fp);
fclose(fp);
}
*/
__global__ void output_parse(int * full_output, int * output, int * num_author_array)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
if(indx < NumAuthor){
int pair_array[10000] = { 0 };
int pair_len = 0;
int coauthor, coauthor_co_len, possible_pair;
for(int i = 0; i < output[indx]; i++){
coauthor = full_output[indx * MAX + i];
coauthor_co_len = output[coauthor-1];
for(int j = 0; j < coauthor_co_len; j++){
possible_pair = full_output[(coauthor - 1) * MAX + j];
check_pair(full_output, indx * MAX, output[indx], possible_pair, pair_array, &pair_len);
}
}
//int * new_array = (int*)malloc(pair_len * sizeof(int));
//memset(new_array, 0, pair_len );
int new_array[10000] = {0};
int num_authors = 0;
count_diff_auth(pair_array, new_array, pair_len, &num_authors, indx);
num_author_array[indx] = num_authors;
}
}
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len){
for(int i = 0; i < len; i++){
if(full_output[start + i] == possible_pair){
pair_array[*pair_len] = possible_pair;
(*pair_len)++;
break;
}
}
}
__device__ void count_diff_auth(int * pair_array,int * new_array, int pair_len, int * pure_len, int indx){
//int * new_array;
//cudaMalloc((void**)&new_array, pair_len * sizeof(int));
//cudaMemset(new_array, 0, pair_len * sizeof(int));
//printf("pair_array[0]:%d, pair_len:%d, %d\n",pair_array[0], pair_len, indx);
new_array[0] = pair_array[0];
*pure_len = 1;
for(int i = 1; i < pair_len; i++){
int j;
for(j = 0; j< *pure_len; j++){
if(pair_array[i] == new_array[j]){
break;
}
}
if (j == *pure_len){
new_array[*pure_len] = pair_array[i];
(*pure_len)++;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define FILENAME "./dblp-co-authors.txt"
#define NumAuthor 317080
#define DataLen 1049866
#define BlockSize 1024
#define GridSize int(DataLen/BlockSize) + 1
#define MAX 343
#define newGridSize int(NumAuthor/BlockSize) + 1
int dataset[DataLen * 2];// array to store the raw dataset
void dataset_read(int * dataset);
__global__ void dataset_parse(int * dataset, int * output, int * full_output);
//int dataset_maxCoAuthor(int * output, int lenght);
//void dataset_plot(int * output, int lenght, int max);
__global__ void output_parse(int * full_output, int * output, int * num_author_array);
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len);
__device__ void count_diff_auth(int * pair_array, int * new_array,int pair_len, int * pure_len, int indx);
int main(int argc, char * argv[])
{
int output[NumAuthor] = {0};
int full_output[MAX * NumAuthor] = { 0 };
int * cu_output;//array to store the co-authors number of each author
int * cu_full_output;
dataset_read(dataset);
// Set device that we will use for our cuda code
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
float time;
int * cu_dataset;
hipEventRecord(start,0);
hipMalloc((void**)&cu_output, NumAuthor * sizeof(int));
hipMalloc((void**)&cu_full_output, MAX * NumAuthor * sizeof(int));
hipMalloc((void**)&cu_dataset, DataLen * 2 * sizeof(int));
hipMemcpy(cu_dataset, dataset, DataLen * 2 * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(cu_full_output, full_output, MAX * NumAuthor * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(cu_output, output, NumAuthor * sizeof(int), hipMemcpyHostToDevice);
dataset_parse<<<GridSize, BlockSize>>>(cu_dataset, cu_output, cu_full_output);
hipDeviceSynchronize();
hipMemcpy(output, cu_output, NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(full_output, cu_full_output, MAX * NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
//int max = dataset_maxCoAuthor(output, NumAuthor);
//printf("Time elapsed: %f\n", time);
int * cu_num_author_array;
int * num_author_array = (int*)malloc(NumAuthor * sizeof(int));
hipMalloc((void**)&cu_num_author_array, NumAuthor * sizeof(int));
hipMemset(cu_num_author_array, 0, NumAuthor * sizeof(int));
hipEventRecord(start,0);
output_parse<<<newGridSize, BlockSize>>>(cu_full_output, cu_output, cu_num_author_array);
hipDeviceSynchronize();
printf("Error in Kernel output_parse:%s\n",hipGetErrorString(hipGetLastError()));
hipDeviceSynchronize();
hipMemcpy(num_author_array, cu_num_author_array, NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time in Kernel output_parse: %f\n", time);
int total_number = 0;
for (int i = 0; i < NumAuthor; i++)
total_number += num_author_array[i];
printf("Total number of authors is %d\n", total_number/2);
return 0;
}
void dataset_read( int * dataset)
{
FILE * datafile;
datafile = fopen( FILENAME, "r");
char line[255];
while (true)
{
fscanf(datafile, "%s", line);
if (atoi(line) == 1)
{
dataset[0] = 1;
break;
}
}
for(int i = 1; i < 2 * DataLen; i++){
fscanf(datafile, "%d", &dataset[i]);
}
fclose(datafile);
}
__global__ void dataset_parse(int * dataset, int * output, int * full_output)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
int i, j;
if(indx < DataLen){
i = atomicAdd(&(output[dataset[2*indx]-1]), 1);
full_output[(dataset[2*indx]-1) * MAX + i] = dataset[2*indx+1];
j = atomicAdd(&(output[dataset[2*indx+1]-1]), 1);
full_output[(dataset[2*indx + 1]-1) * MAX + j] = dataset[2*indx];
}
}
/*
int dataset_maxCoAuthor(int * output, int lenght)
{
int max =0;
int max_num = 0;
int max_ind[1000] = { 0 };
//memset(max_ind, 0, 1000);
for(int i = 0; i < lenght; i++)
{
//printf("output:%d, %d", i, output[i]);
if(max < output[i])
{
// printf("Max right now:%d, %d\n", i, output[i]);
max = output[i];
max_num = 0;
memset(max_ind, 0, 1000);
max_ind[max_num] = i;
}
else if(max == output[i])
{
max_num++;
max_ind[max_num] = i;
}
//else{
//printf("max is:%d, %d\n", max, max_ind[0]);
//}
}
printf("The list of authors with most co-authors:\n");
for(int i = 0; i <= max_num; i++)
{
printf("Author: %6d has %6d co-authors.\n", max_ind[i] + 1, output[max_ind[i]]);
}
return output[max_ind[0]];
}
void dataset_plot(int * output, int lenght, int max)
{
//int* numCoAuthorList;
int* numCoAuthorList = (int*)malloc(max * sizeof(int));
memset(numCoAuthorList, 0, max);
for(int i = 0; i < lenght; i++)
{
if(output[i] <= max)
{
numCoAuthorList[output[i] - 1]++;
}
else{
printf("\nError in Finding MAX!!!\n");
}
}
FILE *fp;
fp = fopen("./output.txt", "wb");
fwrite(numCoAuthorList, sizeof(int), max, fp);
fclose(fp);
}
*/
__global__ void output_parse(int * full_output, int * output, int * num_author_array)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
if(indx < NumAuthor){
int pair_array[10000] = { 0 };
int pair_len = 0;
int coauthor, coauthor_co_len, possible_pair;
for(int i = 0; i < output[indx]; i++){
coauthor = full_output[indx * MAX + i];
coauthor_co_len = output[coauthor-1];
for(int j = 0; j < coauthor_co_len; j++){
possible_pair = full_output[(coauthor - 1) * MAX + j];
check_pair(full_output, indx * MAX, output[indx], possible_pair, pair_array, &pair_len);
}
}
//int * new_array = (int*)malloc(pair_len * sizeof(int));
//memset(new_array, 0, pair_len );
int new_array[10000] = {0};
int num_authors = 0;
count_diff_auth(pair_array, new_array, pair_len, &num_authors, indx);
num_author_array[indx] = num_authors;
}
}
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len){
for(int i = 0; i < len; i++){
if(full_output[start + i] == possible_pair){
pair_array[*pair_len] = possible_pair;
(*pair_len)++;
break;
}
}
}
__device__ void count_diff_auth(int * pair_array,int * new_array, int pair_len, int * pure_len, int indx){
//int * new_array;
//cudaMalloc((void**)&new_array, pair_len * sizeof(int));
//cudaMemset(new_array, 0, pair_len * sizeof(int));
//printf("pair_array[0]:%d, pair_len:%d, %d\n",pair_array[0], pair_len, indx);
new_array[0] = pair_array[0];
*pure_len = 1;
for(int i = 1; i < pair_len; i++){
int j;
for(j = 0; j< *pure_len; j++){
if(pair_array[i] == new_array[j]){
break;
}
}
if (j == *pure_len){
new_array[*pure_len] = pair_array[i];
(*pure_len)++;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13dataset_parsePiS_S_
.globl _Z13dataset_parsePiS_S_
.p2align 8
.type _Z13dataset_parsePiS_S_,@function
_Z13dataset_parsePiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x10050a, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v7, 1 :: v_dual_lshlrev_b32 v0, 1, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_atomic_add_u32 v5, v[3:4], v7, off offset:-4 glc
global_load_b32 v6, v[1:2], off
v_or_b32_e32 v3, 1, v0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(1)
v_mul_lo_u32 v6, v6, 0x157
v_add3_u32 v5, v5, v6, 0xfffffea9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[5:6], v0, off
global_load_b32 v5, v[3:4], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_atomic_add_u32 v0, v[5:6], v7, off offset:-4 glc
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v2, v[1:2], off
s_waitcnt vmcnt(1)
v_mul_lo_u32 v1, v3, 0x157
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v0, v1, 0xfffffea9
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13dataset_parsePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13dataset_parsePiS_S_, .Lfunc_end0-_Z13dataset_parsePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12output_parsePiS_S_
.globl _Z12output_parsePiS_S_
.p2align 8
.type _Z12output_parsePiS_S_,@function
_Z12output_parsePiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x4d698, v1
s_cbranch_execz .LBB1_32
v_mov_b32_e32 v0, 16
v_mov_b32_e32 v2, 0
s_mov_b64 s[2:3], 0
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
scratch_store_b8 v0, v2, off
v_cmp_gt_u64_e64 s4, 0x9c40, s[2:3]
v_add_nc_u32_e32 v0, 1, v0
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_2
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 0
s_mov_b32 s8, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v8
s_cbranch_execz .LBB1_17
s_load_b64 s[6:7], s[0:1], 0x0
v_mul_lo_u32 v3, v1, 0x157
v_mov_b32_e32 v0, 0
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_branch .LBB1_7
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s11
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s9, s9, 1
v_cmp_eq_u32_e32 vcc_lo, s9, v8
s_or_b32 s8, vcc_lo, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB1_16
.LBB1_7:
v_add_nc_u32_e32 v6, s9, v3
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, -1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[9:10], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v9
s_cbranch_execz .LBB1_6
v_mul_lo_u32 v10, v6, 0x157
s_mov_b32 s11, 0
s_mov_b32 s12, 0
s_branch .LBB1_10
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s12, v9
s_or_b32 s11, vcc_lo, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB1_5
.LBB1_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, s12, v10
v_mov_b32_e32 v12, v8
s_mov_b32 s13, 0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v11, v[6:7], off
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_12
.p2align 6
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s16
s_or_b32 s13, s2, s13
s_and_not1_b32 s2, s14, exec_lo
s_and_b32 s14, s15, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s14, s2, s14
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB1_14
.LBB1_12:
global_load_b32 v13, v[6:7], off
s_or_b32 s15, s15, exec_lo
s_or_b32 s16, s16, exec_lo
s_mov_b32 s17, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v13, v11
s_cbranch_execz .LBB1_11
v_add_nc_u32_e32 v12, -1, v12
v_add_co_u32 v6, s2, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s2, 0, v7, s2
v_cmp_eq_u32_e32 vcc_lo, 0, v12
s_and_not1_b32 s2, s16, exec_lo
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s16, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s16, s2, s16
s_branch .LBB1_11
.LBB1_14:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB1_9
v_lshl_add_u32 v6, v0, 2, 16
v_add_nc_u32_e32 v0, 1, v0
scratch_store_b32 v6, v11, off
s_branch .LBB1_9
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s8
.LBB1_17:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
v_dual_mov_b32 v3, 0x9c50 :: v_dual_mov_b32 v4, 0
s_mov_b64 s[2:3], 0
.LBB1_18:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
scratch_store_b8 v3, v4, off
v_cmp_gt_u64_e64 s4, 0x9c40, s[2:3]
v_add_nc_u32_e32 v3, 1, v3
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB1_18
scratch_load_b32 v4, off, off offset:16
v_mov_b32_e32 v3, 1
s_mov_b32 s2, 0x9c50
s_mov_b32 s3, 1
s_waitcnt vmcnt(0)
scratch_store_b32 off, v4, s2
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 1, v0
s_cbranch_execz .LBB1_31
v_mov_b32_e32 v3, 1
s_mov_b32 s4, 0
s_branch .LBB1_22
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s3, v0
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB1_30
.LBB1_22:
v_mov_b32_e32 v6, 0
s_mov_b32 s5, exec_lo
v_cmpx_lt_i32_e32 0, v3
s_cbranch_execz .LBB1_28
s_lshl_b32 s6, s3, 2
v_mov_b32_e32 v5, 0x9c50
s_add_i32 s6, s6, 16
s_mov_b32 s7, 0
scratch_load_b32 v4, off, s6
s_mov_b32 s6, 0
s_branch .LBB1_25
.p2align 6
.LBB1_24:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, exec_lo, s8
s_or_b32 s6, s9, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB1_27
.LBB1_25:
scratch_load_b32 v6, v5, off
s_or_b32 s8, s8, exec_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v4, v6
v_mov_b32_e32 v6, s7
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_24
s_add_i32 s7, s7, 1
v_dual_mov_b32 v6, v3 :: v_dual_add_nc_u32 v5, 4, v5
v_cmp_eq_u32_e32 vcc_lo, s7, v3
s_and_not1_b32 s8, s8, exec_lo
s_and_b32 s10, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
s_branch .LBB1_24
.LBB1_27:
s_or_b32 exec_lo, exec_lo, s6
.LBB1_28:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e64 v6, v3
s_cbranch_execz .LBB1_21
s_lshl_b32 s6, s3, 2
v_lshl_add_u32 v5, v3, 2, 0x9c50
s_add_i32 s6, s6, 16
v_add_nc_u32_e32 v3, 1, v3
scratch_load_b32 v4, off, s6
s_waitcnt vmcnt(0)
scratch_store_b32 v5, v4, off
s_branch .LBB1_21
.LBB1_30:
s_or_b32 exec_lo, exec_lo, s4
.LBB1_31:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB1_32:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12output_parsePiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 80016
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12output_parsePiS_S_, .Lfunc_end1-_Z12output_parsePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13dataset_parsePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13dataset_parsePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12output_parsePiS_S_
.private_segment_fixed_size: 80016
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12output_parsePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define FILENAME "./dblp-co-authors.txt"
#define NumAuthor 317080
#define DataLen 1049866
#define BlockSize 1024
#define GridSize int(DataLen/BlockSize) + 1
#define MAX 343
#define newGridSize int(NumAuthor/BlockSize) + 1
int dataset[DataLen * 2];// array to store the raw dataset
void dataset_read(int * dataset);
__global__ void dataset_parse(int * dataset, int * output, int * full_output);
//int dataset_maxCoAuthor(int * output, int lenght);
//void dataset_plot(int * output, int lenght, int max);
__global__ void output_parse(int * full_output, int * output, int * num_author_array);
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len);
__device__ void count_diff_auth(int * pair_array, int * new_array,int pair_len, int * pure_len, int indx);
int main(int argc, char * argv[])
{
int output[NumAuthor] = {0};
int full_output[MAX * NumAuthor] = { 0 };
int * cu_output;//array to store the co-authors number of each author
int * cu_full_output;
dataset_read(dataset);
// Set device that we will use for our cuda code
hipSetDevice(0);
// Time Variables
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
float time;
int * cu_dataset;
hipEventRecord(start,0);
hipMalloc((void**)&cu_output, NumAuthor * sizeof(int));
hipMalloc((void**)&cu_full_output, MAX * NumAuthor * sizeof(int));
hipMalloc((void**)&cu_dataset, DataLen * 2 * sizeof(int));
hipMemcpy(cu_dataset, dataset, DataLen * 2 * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(cu_full_output, full_output, MAX * NumAuthor * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(cu_output, output, NumAuthor * sizeof(int), hipMemcpyHostToDevice);
dataset_parse<<<GridSize, BlockSize>>>(cu_dataset, cu_output, cu_full_output);
hipDeviceSynchronize();
hipMemcpy(output, cu_output, NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(full_output, cu_full_output, MAX * NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
//int max = dataset_maxCoAuthor(output, NumAuthor);
//printf("Time elapsed: %f\n", time);
int * cu_num_author_array;
int * num_author_array = (int*)malloc(NumAuthor * sizeof(int));
hipMalloc((void**)&cu_num_author_array, NumAuthor * sizeof(int));
hipMemset(cu_num_author_array, 0, NumAuthor * sizeof(int));
hipEventRecord(start,0);
output_parse<<<newGridSize, BlockSize>>>(cu_full_output, cu_output, cu_num_author_array);
hipDeviceSynchronize();
printf("Error in Kernel output_parse:%s\n",hipGetErrorString(hipGetLastError()));
hipDeviceSynchronize();
hipMemcpy(num_author_array, cu_num_author_array, NumAuthor * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time in Kernel output_parse: %f\n", time);
int total_number = 0;
for (int i = 0; i < NumAuthor; i++)
total_number += num_author_array[i];
printf("Total number of authors is %d\n", total_number/2);
return 0;
}
void dataset_read( int * dataset)
{
FILE * datafile;
datafile = fopen( FILENAME, "r");
char line[255];
while (true)
{
fscanf(datafile, "%s", line);
if (atoi(line) == 1)
{
dataset[0] = 1;
break;
}
}
for(int i = 1; i < 2 * DataLen; i++){
fscanf(datafile, "%d", &dataset[i]);
}
fclose(datafile);
}
__global__ void dataset_parse(int * dataset, int * output, int * full_output)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
int i, j;
if(indx < DataLen){
i = atomicAdd(&(output[dataset[2*indx]-1]), 1);
full_output[(dataset[2*indx]-1) * MAX + i] = dataset[2*indx+1];
j = atomicAdd(&(output[dataset[2*indx+1]-1]), 1);
full_output[(dataset[2*indx + 1]-1) * MAX + j] = dataset[2*indx];
}
}
/*
int dataset_maxCoAuthor(int * output, int lenght)
{
int max =0;
int max_num = 0;
int max_ind[1000] = { 0 };
//memset(max_ind, 0, 1000);
for(int i = 0; i < lenght; i++)
{
//printf("output:%d, %d", i, output[i]);
if(max < output[i])
{
// printf("Max right now:%d, %d\n", i, output[i]);
max = output[i];
max_num = 0;
memset(max_ind, 0, 1000);
max_ind[max_num] = i;
}
else if(max == output[i])
{
max_num++;
max_ind[max_num] = i;
}
//else{
//printf("max is:%d, %d\n", max, max_ind[0]);
//}
}
printf("The list of authors with most co-authors:\n");
for(int i = 0; i <= max_num; i++)
{
printf("Author: %6d has %6d co-authors.\n", max_ind[i] + 1, output[max_ind[i]]);
}
return output[max_ind[0]];
}
void dataset_plot(int * output, int lenght, int max)
{
//int* numCoAuthorList;
int* numCoAuthorList = (int*)malloc(max * sizeof(int));
memset(numCoAuthorList, 0, max);
for(int i = 0; i < lenght; i++)
{
if(output[i] <= max)
{
numCoAuthorList[output[i] - 1]++;
}
else{
printf("\nError in Finding MAX!!!\n");
}
}
FILE *fp;
fp = fopen("./output.txt", "wb");
fwrite(numCoAuthorList, sizeof(int), max, fp);
fclose(fp);
}
*/
__global__ void output_parse(int * full_output, int * output, int * num_author_array)
{
int indx = threadIdx.x + blockIdx.x * blockDim.x;
if(indx < NumAuthor){
int pair_array[10000] = { 0 };
int pair_len = 0;
int coauthor, coauthor_co_len, possible_pair;
for(int i = 0; i < output[indx]; i++){
coauthor = full_output[indx * MAX + i];
coauthor_co_len = output[coauthor-1];
for(int j = 0; j < coauthor_co_len; j++){
possible_pair = full_output[(coauthor - 1) * MAX + j];
check_pair(full_output, indx * MAX, output[indx], possible_pair, pair_array, &pair_len);
}
}
//int * new_array = (int*)malloc(pair_len * sizeof(int));
//memset(new_array, 0, pair_len );
int new_array[10000] = {0};
int num_authors = 0;
count_diff_auth(pair_array, new_array, pair_len, &num_authors, indx);
num_author_array[indx] = num_authors;
}
}
__device__ void check_pair(int * full_output, int start, int len, int possible_pair, int * pair_array, int * pair_len){
for(int i = 0; i < len; i++){
if(full_output[start + i] == possible_pair){
pair_array[*pair_len] = possible_pair;
(*pair_len)++;
break;
}
}
}
__device__ void count_diff_auth(int * pair_array,int * new_array, int pair_len, int * pure_len, int indx){
//int * new_array;
//cudaMalloc((void**)&new_array, pair_len * sizeof(int));
//cudaMemset(new_array, 0, pair_len * sizeof(int));
//printf("pair_array[0]:%d, pair_len:%d, %d\n",pair_array[0], pair_len, indx);
new_array[0] = pair_array[0];
*pure_len = 1;
for(int i = 1; i < pair_len; i++){
int j;
for(j = 0; j< *pure_len; j++){
if(pair_array[i] == new_array[j]){
break;
}
}
if (j == *pure_len){
new_array[*pure_len] = pair_array[i];
(*pure_len)++;
}
}
} | .text
.file "Q4.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $436302464, %rsp # imm = 0x1A017280
.cfi_def_cfa_offset 436302496
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 384(%rsp), %rdi
movl $1268320, %edx # imm = 0x135A60
xorl %esi, %esi
callq memset@PLT
leaq 1268704(%rsp), %rdi
movl $435033760, %edx # imm = 0x19EE16A0
xorl %esi, %esi
callq memset@PLT
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
leaq 128(%rsp), %rbx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
jne .LBB0_1
# %bb.2:
movl $1, dataset(%rip)
movl $4, %ebx
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
leaq dataset(%rbx), %rdx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbx
cmpq $8398928, %rbx # imm = 0x802850
jne .LBB0_3
# %bb.4: # %_Z12dataset_readPi.exit
movabsq $4294968320, %rbx # imm = 0x100000400
movq %r14, %rdi
callq fclose
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 32(%rsp), %rdi
movl $1268320, %esi # imm = 0x135A60
callq hipMalloc
leaq 24(%rsp), %rdi
movl $435033760, %esi # imm = 0x19EE16A0
callq hipMalloc
leaq 120(%rsp), %rdi
movl $8398928, %esi # imm = 0x802850
callq hipMalloc
movq 120(%rsp), %rdi
movl $dataset, %esi
movl $8398928, %edx # imm = 0x802850
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 1268704(%rsp), %rsi
movl $435033760, %edx # imm = 0x19EE16A0
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 384(%rsp), %rsi
movl $1268320, %edx # imm = 0x135A60
movl $1, %ecx
callq hipMemcpy
leaq 2(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 120(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13dataset_parsePiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
leaq 384(%rsp), %rdi
movl $1268320, %edx # imm = 0x135A60
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
leaq 1268704(%rsp), %rdi
movl $435033760, %edx # imm = 0x19EE16A0
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $1268320, %edi # imm = 0x135A60
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movl $1268320, %esi # imm = 0x135A60
callq hipMalloc
movq 40(%rsp), %rdi
movl $1268320, %edx # imm = 0x135A60
xorl %esi, %esi
callq hipMemset
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq -714(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12output_parsePiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
callq hipDeviceSynchronize
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl $1268320, %edx # imm = 0x135A60
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
addl (%r14,%rax,4), %r15d
incq %rax
cmpq $317080, %rax # imm = 0x4D698
jne .LBB0_9
# %bb.10:
movl %r15d, %esi
shrl $31, %esi
addl %r15d, %esi
sarl %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $436302464, %rsp # imm = 0x1A017280
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z12dataset_readPi # -- Begin function _Z12dataset_readPi
.p2align 4, 0x90
.type _Z12dataset_readPi,@function
_Z12dataset_readPi: # @_Z12dataset_readPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
movq %rsp, %r15
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
jne .LBB1_1
# %bb.2:
movl $1, (%rbx)
movl $4, %r15d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r15), %rdx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
cmpq $8398928, %r15 # imm = 0x802850
jne .LBB1_3
# %bb.4:
movq %r14, %rdi
callq fclose
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12dataset_readPi, .Lfunc_end1-_Z12dataset_readPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__dataset_parsePiS_S_ # -- Begin function _Z28__device_stub__dataset_parsePiS_S_
.p2align 4, 0x90
.type _Z28__device_stub__dataset_parsePiS_S_,@function
_Z28__device_stub__dataset_parsePiS_S_: # @_Z28__device_stub__dataset_parsePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13dataset_parsePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z28__device_stub__dataset_parsePiS_S_, .Lfunc_end2-_Z28__device_stub__dataset_parsePiS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__output_parsePiS_S_ # -- Begin function _Z27__device_stub__output_parsePiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__output_parsePiS_S_,@function
_Z27__device_stub__output_parsePiS_S_: # @_Z27__device_stub__output_parsePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12output_parsePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z27__device_stub__output_parsePiS_S_, .Lfunc_end3-_Z27__device_stub__output_parsePiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dataset_parsePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12output_parsePiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type dataset,@object # @dataset
.bss
.globl dataset
.p2align 4, 0x0
dataset:
.zero 8398928
.size dataset, 8398928
.type _Z13dataset_parsePiS_S_,@object # @_Z13dataset_parsePiS_S_
.section .rodata,"a",@progbits
.globl _Z13dataset_parsePiS_S_
.p2align 3, 0x0
_Z13dataset_parsePiS_S_:
.quad _Z28__device_stub__dataset_parsePiS_S_
.size _Z13dataset_parsePiS_S_, 8
.type _Z12output_parsePiS_S_,@object # @_Z12output_parsePiS_S_
.globl _Z12output_parsePiS_S_
.p2align 3, 0x0
_Z12output_parsePiS_S_:
.quad _Z27__device_stub__output_parsePiS_S_
.size _Z12output_parsePiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error in Kernel output_parse:%s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elapsed time in Kernel output_parse: %f\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total number of authors is %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./dblp-co-authors.txt"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13dataset_parsePiS_S_"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12output_parsePiS_S_"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__dataset_parsePiS_S_
.addrsig_sym _Z27__device_stub__output_parsePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dataset
.addrsig_sym _Z13dataset_parsePiS_S_
.addrsig_sym _Z12output_parsePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d3a5c_00000000-6_Q4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "./dblp-co-authors.txt"
.LC2:
.string "%s"
.LC3:
.string "%d"
.text
.globl _Z12dataset_readPi
.type _Z12dataset_readPi, @function
_Z12dataset_readPi:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $280, %rsp
.cfi_def_cfa_offset 320
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
leaq .LC2(%rip), %r13
.L4:
movq %rsp, %rbx
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $10, %edx
movl $0, %esi
movq %rbx, %rdi
call __isoc23_strtol@PLT
cmpl $1, %eax
jne .L4
movl $1, (%r12)
leaq 4(%r12), %rbx
addq $8398928, %r12
leaq .LC3(%rip), %r13
.L5:
movq %rbx, %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
movq %rbp, %rdi
call fclose@PLT
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z12dataset_readPi, .-_Z12dataset_readPi
.globl _Z10check_pairPiiiiS_S_
.type _Z10check_pairPiiiiS_S_, @function
_Z10check_pairPiiiiS_S_:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10check_pairPiiiiS_S_, .-_Z10check_pairPiiiiS_S_
.globl _Z15count_diff_authPiS_iS_i
.type _Z15count_diff_authPiS_iS_i, @function
_Z15count_diff_authPiS_iS_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2060:
.size _Z15count_diff_authPiS_iS_i, .-_Z15count_diff_authPiS_iS_i
.globl _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
.type _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_, @function
_Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13dataset_parsePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_, .-_Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
.globl _Z13dataset_parsePiS_S_
.type _Z13dataset_parsePiS_S_, @function
_Z13dataset_parsePiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13dataset_parsePiS_S_, .-_Z13dataset_parsePiS_S_
.globl _Z36__device_stub__Z12output_parsePiS_S_PiS_S_
.type _Z36__device_stub__Z12output_parsePiS_S_PiS_S_, @function
_Z36__device_stub__Z12output_parsePiS_S_PiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12output_parsePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z36__device_stub__Z12output_parsePiS_S_PiS_S_, .-_Z36__device_stub__Z12output_parsePiS_S_PiS_S_
.globl _Z12output_parsePiS_S_
.type _Z12output_parsePiS_S_, @function
_Z12output_parsePiS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12output_parsePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12output_parsePiS_S_, .-_Z12output_parsePiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error in Kernel output_parse:%s\n"
.align 8
.LC5:
.string "Elapsed time in Kernel output_parse: %f\n"
.align 8
.LC6:
.string "Total number of authors is %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -436301824(%rsp), %r11
.cfi_def_cfa 11, 436301856
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $352, %rsp
.cfi_def_cfa_offset 436302208
movq %fs:40, %rax
movq %rax, 436302168(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbx
movl $1268320, %edx
movl $0, %esi
movq %rbx, %rdi
call memset@PLT
leaq 1268400(%rsp), %rbp
movl $435033760, %edx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
leaq dataset(%rip), %r12
movq %r12, %rdi
call _Z12dataset_readPi
movl $0, %edi
call cudaSetDevice@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 8(%rsp), %rdi
movl $1268320, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $435033760, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8398928, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8398928, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $435033760, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1268320, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1026, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L32:
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $1268320, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
leaq 1268400(%rsp), %rdi
movl $2, %ecx
movl $435033760, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $1268320, %edi
call malloc@PLT
movq %rax, %rbx
leaq 48(%rsp), %rdi
movl $1268320, %esi
call cudaMalloc@PLT
movl $1268320, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $310, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $1268320, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rax
leaq 1268320(%rbx), %rsi
movl $0, %ecx
.L34:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L34
movl %ecx, %eax
shrl $31, %eax
addl %eax, %edx
sarl %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 436302168(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $436302176, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z37__device_stub__Z13dataset_parsePiS_S_PiS_S_
jmp .L32
.L39:
movq 48(%rsp), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z12output_parsePiS_S_PiS_S_
jmp .L33
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12output_parsePiS_S_"
.LC8:
.string "_Z13dataset_parsePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12output_parsePiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13dataset_parsePiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dataset
.bss
.align 32
.type dataset, @object
.size dataset, 8398928
dataset:
.zero 8398928
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Q4.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $436302464, %rsp # imm = 0x1A017280
.cfi_def_cfa_offset 436302496
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 384(%rsp), %rdi
movl $1268320, %edx # imm = 0x135A60
xorl %esi, %esi
callq memset@PLT
leaq 1268704(%rsp), %rdi
movl $435033760, %edx # imm = 0x19EE16A0
xorl %esi, %esi
callq memset@PLT
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
leaq 128(%rsp), %rbx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %rbx, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
jne .LBB0_1
# %bb.2:
movl $1, dataset(%rip)
movl $4, %ebx
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
leaq dataset(%rbx), %rdx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbx
cmpq $8398928, %rbx # imm = 0x802850
jne .LBB0_3
# %bb.4: # %_Z12dataset_readPi.exit
movabsq $4294968320, %rbx # imm = 0x100000400
movq %r14, %rdi
callq fclose
xorl %edi, %edi
callq hipSetDevice
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 32(%rsp), %rdi
movl $1268320, %esi # imm = 0x135A60
callq hipMalloc
leaq 24(%rsp), %rdi
movl $435033760, %esi # imm = 0x19EE16A0
callq hipMalloc
leaq 120(%rsp), %rdi
movl $8398928, %esi # imm = 0x802850
callq hipMalloc
movq 120(%rsp), %rdi
movl $dataset, %esi
movl $8398928, %edx # imm = 0x802850
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 1268704(%rsp), %rsi
movl $435033760, %edx # imm = 0x19EE16A0
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
leaq 384(%rsp), %rsi
movl $1268320, %edx # imm = 0x135A60
movl $1, %ecx
callq hipMemcpy
leaq 2(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 120(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13dataset_parsePiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
callq hipDeviceSynchronize
movq 32(%rsp), %rsi
leaq 384(%rsp), %rdi
movl $1268320, %edx # imm = 0x135A60
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
leaq 1268704(%rsp), %rdi
movl $435033760, %edx # imm = 0x19EE16A0
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $1268320, %edi # imm = 0x135A60
callq malloc
movq %rax, %r14
leaq 40(%rsp), %rdi
movl $1268320, %esi # imm = 0x135A60
callq hipMalloc
movq 40(%rsp), %rdi
movl $1268320, %edx # imm = 0x135A60
xorl %esi, %esi
callq hipMemset
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq -714(%rbx), %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12output_parsePiS_S_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
callq hipDeviceSynchronize
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movq 40(%rsp), %rsi
movl $1268320, %edx # imm = 0x135A60
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
addl (%r14,%rax,4), %r15d
incq %rax
cmpq $317080, %rax # imm = 0x4D698
jne .LBB0_9
# %bb.10:
movl %r15d, %esi
shrl $31, %esi
addl %r15d, %esi
sarl %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $436302464, %rsp # imm = 0x1A017280
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z12dataset_readPi # -- Begin function _Z12dataset_readPi
.p2align 4, 0x90
.type _Z12dataset_readPi,@function
_Z12dataset_readPi: # @_Z12dataset_readPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.L.str.3, %edi
movl $.L.str.4, %esi
callq fopen
movq %rax, %r14
movq %rsp, %r15
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.5, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq %r15, %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
jne .LBB1_1
# %bb.2:
movl $1, (%rbx)
movl $4, %r15d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
leaq (%rbx,%r15), %rdx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
cmpq $8398928, %r15 # imm = 0x802850
jne .LBB1_3
# %bb.4:
movq %r14, %rdi
callq fclose
addq $256, %rsp # imm = 0x100
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12dataset_readPi, .Lfunc_end1-_Z12dataset_readPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__dataset_parsePiS_S_ # -- Begin function _Z28__device_stub__dataset_parsePiS_S_
.p2align 4, 0x90
.type _Z28__device_stub__dataset_parsePiS_S_,@function
_Z28__device_stub__dataset_parsePiS_S_: # @_Z28__device_stub__dataset_parsePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13dataset_parsePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z28__device_stub__dataset_parsePiS_S_, .Lfunc_end2-_Z28__device_stub__dataset_parsePiS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__output_parsePiS_S_ # -- Begin function _Z27__device_stub__output_parsePiS_S_
.p2align 4, 0x90
.type _Z27__device_stub__output_parsePiS_S_,@function
_Z27__device_stub__output_parsePiS_S_: # @_Z27__device_stub__output_parsePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12output_parsePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z27__device_stub__output_parsePiS_S_, .Lfunc_end3-_Z27__device_stub__output_parsePiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13dataset_parsePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12output_parsePiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type dataset,@object # @dataset
.bss
.globl dataset
.p2align 4, 0x0
dataset:
.zero 8398928
.size dataset, 8398928
.type _Z13dataset_parsePiS_S_,@object # @_Z13dataset_parsePiS_S_
.section .rodata,"a",@progbits
.globl _Z13dataset_parsePiS_S_
.p2align 3, 0x0
_Z13dataset_parsePiS_S_:
.quad _Z28__device_stub__dataset_parsePiS_S_
.size _Z13dataset_parsePiS_S_, 8
.type _Z12output_parsePiS_S_,@object # @_Z12output_parsePiS_S_
.globl _Z12output_parsePiS_S_
.p2align 3, 0x0
_Z12output_parsePiS_S_:
.quad _Z27__device_stub__output_parsePiS_S_
.size _Z12output_parsePiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error in Kernel output_parse:%s\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elapsed time in Kernel output_parse: %f\n"
.size .L.str.1, 41
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Total number of authors is %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "./dblp-co-authors.txt"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "r"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d"
.size .L.str.6, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13dataset_parsePiS_S_"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12output_parsePiS_S_"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__dataset_parsePiS_S_
.addrsig_sym _Z27__device_stub__output_parsePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym dataset
.addrsig_sym _Z13dataset_parsePiS_S_
.addrsig_sym _Z12output_parsePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <iomanip>
using namespace std;
__global__
void convert(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
for(int i = 0; i < step; i += 1){
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
}
extern "C" void rgbConvert(char* input, int size, unsigned char * pBuffer){
int len = size / 3;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + size;
int block = 128;
int thread = 128;
cudaMemcpy(pBuffer, input, size, cudaMemcpyHostToDevice );
cudaMemset(pBuffer + len * 6, 0, len);
cudaDeviceSynchronize();
if(len/block/thread > 0){
convert<<<len/block/thread, thread>>>(cinput, coutput, len, block);
convert<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread*3, coutput + len/block/thread*block*thread, len, 1);
}else{
convert<<<len%(block*thread), 1>>>(cinput , coutput , len, 1);
}
cudaDeviceSynchronize();
}
__global__
void convertBack(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * iR = input + index * step , *iG = iR + len, *iB = iG + len;
char *oPos = output + index * step * 3;
for (int i = 0; i < step; i++){
*(oPos++) = *(iB++);
*(oPos++) = *(iG++);
*(oPos++) = *(iR++);
}
}
extern "C" void rgbConvertBack(int len, unsigned char * pBuffer){
int block = 128;
int thread = 128;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + len * 4;
if(len/block/thread > 0){
convertBack<<<len/block/thread, thread>>>(cinput, coutput, len, thread);
convertBack<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread, coutput + len/block/thread*block*thread*3, len, 1);
}else{
convertBack<<<len%(block*thread), 1>>>(cinput, coutput, len, 1);
}
cudaDeviceSynchronize();
}
__global__
void convert128(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
/*
int main(){
int size = 1811520*3;
char * input = (char*) malloc(size);
memset(input, 2, size);
char* output = rgbConvert(input, size);
cudaFree(output);
return EXIT_SUCCESS;
}
*/ | .file "tmpxft_0006fc7d_00000000-6_rgbConverter.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4052:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7convertPcS_iiPcS_ii
.type _Z30__device_stub__Z7convertPcS_iiPcS_ii, @function
_Z30__device_stub__Z7convertPcS_iiPcS_ii:
.LFB4074:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7convertPcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4074:
.size _Z30__device_stub__Z7convertPcS_iiPcS_ii, .-_Z30__device_stub__Z7convertPcS_iiPcS_ii
.globl _Z7convertPcS_ii
.type _Z7convertPcS_ii, @function
_Z7convertPcS_ii:
.LFB4075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4075:
.size _Z7convertPcS_ii, .-_Z7convertPcS_ii
.globl rgbConvert
.type rgbConvert, @function
rgbConvert:
.LFB4048:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %esi, %r12d
movq %rdx, %rbp
movslq %esi, %rdx
imulq $1431655766, %rdx, %rbx
shrq $32, %rbx
movl %esi, %eax
sarl $31, %eax
subl %eax, %ebx
leaq 0(%rbp,%rdx), %r13
movl $1, %ecx
movq %rdi, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movslq %ebx, %rdx
leal (%rbx,%rbx,2), %edi
addl %edi, %edi
movslq %edi, %rdi
addq %rbp, %rdi
movl $0, %esi
call cudaMemset@PLT
call cudaDeviceSynchronize@PLT
cmpl $49151, %r12d
jle .L12
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 16383(%rbx), %r12d
testl %ebx, %ebx
cmovns %ebx, %r12d
sarl $14, %r12d
movl %r12d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rbx,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $128, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
jmp .L13
.L19:
movl %r12d, %esi
sall $14, %esi
movslq %esi, %rsi
addq %r13, %rsi
leal (%r12,%r12,2), %edi
sall $14, %edi
movslq %edi, %rdi
addq %rbp, %rdi
movl $1, %ecx
movl %ebx, %edx
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
jmp .L15
.L12:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rbx,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl $1, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
jmp .L15
.cfi_endproc
.LFE4048:
.size rgbConvert, .-rgbConvert
.globl _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
.type _Z35__device_stub__Z11convertBackPcS_iiPcS_ii, @function
_Z35__device_stub__Z11convertBackPcS_iiPcS_ii:
.LFB4076:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11convertBackPcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4076:
.size _Z35__device_stub__Z11convertBackPcS_iiPcS_ii, .-_Z35__device_stub__Z11convertBackPcS_iiPcS_ii
.globl _Z11convertBackPcS_ii
.type _Z11convertBackPcS_ii, @function
_Z11convertBackPcS_ii:
.LFB4077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4077:
.size _Z11convertBackPcS_ii, .-_Z11convertBackPcS_ii
.globl rgbConvertBack
.type rgbConvertBack, @function
rgbConvertBack:
.LFB4049:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %r13
leal 0(,%rdi,4), %eax
cltq
leaq (%rsi,%rax), %r12
cmpl $16383, %edi
jle .L29
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 16383(%rdi), %ebp
testl %edi, %edi
cmovns %edi, %ebp
sarl $14, %ebp
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rbx,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $128, %ecx
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
jmp .L30
.L36:
leal 0(%rbp,%rbp,2), %esi
sall $14, %esi
movslq %esi, %rsi
addq %r12, %rsi
sall $14, %ebp
movslq %ebp, %rdi
addq %r13, %rdi
movl $1, %ecx
movl %ebx, %edx
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
jmp .L32
.L29:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %edi, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rdi,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
jmp .L32
.cfi_endproc
.LFE4049:
.size rgbConvertBack, .-rgbConvertBack
.globl _Z34__device_stub__Z10convert128PcS_iiPcS_ii
.type _Z34__device_stub__Z10convert128PcS_iiPcS_ii, @function
_Z34__device_stub__Z10convert128PcS_iiPcS_ii:
.LFB4078:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10convert128PcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4078:
.size _Z34__device_stub__Z10convert128PcS_iiPcS_ii, .-_Z34__device_stub__Z10convert128PcS_iiPcS_ii
.globl _Z10convert128PcS_ii
.type _Z10convert128PcS_ii, @function
_Z10convert128PcS_ii:
.LFB4079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10convert128PcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4079:
.size _Z10convert128PcS_ii, .-_Z10convert128PcS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10convert128PcS_ii"
.LC1:
.string "_Z11convertBackPcS_ii"
.LC2:
.string "_Z7convertPcS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4081:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10convert128PcS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11convertBackPcS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7convertPcS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4081:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <chrono>
#include <iomanip>
using namespace std;
__global__
void convert(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
for(int i = 0; i < step; i += 1){
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
}
extern "C" void rgbConvert(char* input, int size, unsigned char * pBuffer){
int len = size / 3;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + size;
int block = 128;
int thread = 128;
cudaMemcpy(pBuffer, input, size, cudaMemcpyHostToDevice );
cudaMemset(pBuffer + len * 6, 0, len);
cudaDeviceSynchronize();
if(len/block/thread > 0){
convert<<<len/block/thread, thread>>>(cinput, coutput, len, block);
convert<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread*3, coutput + len/block/thread*block*thread, len, 1);
}else{
convert<<<len%(block*thread), 1>>>(cinput , coutput , len, 1);
}
cudaDeviceSynchronize();
}
__global__
void convertBack(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * iR = input + index * step , *iG = iR + len, *iB = iG + len;
char *oPos = output + index * step * 3;
for (int i = 0; i < step; i++){
*(oPos++) = *(iB++);
*(oPos++) = *(iG++);
*(oPos++) = *(iR++);
}
}
extern "C" void rgbConvertBack(int len, unsigned char * pBuffer){
int block = 128;
int thread = 128;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + len * 4;
if(len/block/thread > 0){
convertBack<<<len/block/thread, thread>>>(cinput, coutput, len, thread);
convertBack<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread, coutput + len/block/thread*block*thread*3, len, 1);
}else{
convertBack<<<len%(block*thread), 1>>>(cinput, coutput, len, 1);
}
cudaDeviceSynchronize();
}
__global__
void convert128(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
/*
int main(){
int size = 1811520*3;
char * input = (char*) malloc(size);
memset(input, 2, size);
char* output = rgbConvert(input, size);
cudaFree(output);
return EXIT_SUCCESS;
}
*/ | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <chrono>
#include <iomanip>
using namespace std;
__global__
void convert(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
for(int i = 0; i < step; i += 1){
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
}
extern "C" void rgbConvert(char* input, int size, unsigned char * pBuffer){
int len = size / 3;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + size;
int block = 128;
int thread = 128;
hipMemcpy(pBuffer, input, size, hipMemcpyHostToDevice );
hipMemset(pBuffer + len * 6, 0, len);
hipDeviceSynchronize();
if(len/block/thread > 0){
convert<<<len/block/thread, thread>>>(cinput, coutput, len, block);
convert<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread*3, coutput + len/block/thread*block*thread, len, 1);
}else{
convert<<<len%(block*thread), 1>>>(cinput , coutput , len, 1);
}
hipDeviceSynchronize();
}
__global__
void convertBack(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * iR = input + index * step , *iG = iR + len, *iB = iG + len;
char *oPos = output + index * step * 3;
for (int i = 0; i < step; i++){
*(oPos++) = *(iB++);
*(oPos++) = *(iG++);
*(oPos++) = *(iR++);
}
}
extern "C" void rgbConvertBack(int len, unsigned char * pBuffer){
int block = 128;
int thread = 128;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + len * 4;
if(len/block/thread > 0){
convertBack<<<len/block/thread, thread>>>(cinput, coutput, len, thread);
convertBack<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread, coutput + len/block/thread*block*thread*3, len, 1);
}else{
convertBack<<<len%(block*thread), 1>>>(cinput, coutput, len, 1);
}
hipDeviceSynchronize();
}
__global__
void convert128(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
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*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
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*(oG++) = *(iPos++);
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*(oB++) = *(iPos++);
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*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
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*(oG++) = *(iPos++);
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*(oB++) = *(iPos++);
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*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
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*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
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*(oB++) = *(iPos++);
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*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
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*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
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*(oG++) = *(iPos++);
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*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
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*(oB++) = *(iPos++);
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*(oR++) = *(iPos++);
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*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
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*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
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*(oR++) = *(iPos++);
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*(oB++) = *(iPos++);
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*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
/*
int main(){
int size = 1811520*3;
char * input = (char*) malloc(size);
memset(input, 2, size);
char* output = rgbConvert(input, size);
cudaFree(output);
return EXIT_SUCCESS;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <chrono>
#include <iomanip>
using namespace std;
__global__
void convert(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
for(int i = 0; i < step; i += 1){
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
}
extern "C" void rgbConvert(char* input, int size, unsigned char * pBuffer){
int len = size / 3;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + size;
int block = 128;
int thread = 128;
hipMemcpy(pBuffer, input, size, hipMemcpyHostToDevice );
hipMemset(pBuffer + len * 6, 0, len);
hipDeviceSynchronize();
if(len/block/thread > 0){
convert<<<len/block/thread, thread>>>(cinput, coutput, len, block);
convert<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread*3, coutput + len/block/thread*block*thread, len, 1);
}else{
convert<<<len%(block*thread), 1>>>(cinput , coutput , len, 1);
}
hipDeviceSynchronize();
}
__global__
void convertBack(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * iR = input + index * step , *iG = iR + len, *iB = iG + len;
char *oPos = output + index * step * 3;
for (int i = 0; i < step; i++){
*(oPos++) = *(iB++);
*(oPos++) = *(iG++);
*(oPos++) = *(iR++);
}
}
extern "C" void rgbConvertBack(int len, unsigned char * pBuffer){
int block = 128;
int thread = 128;
char * cinput = (char *) pBuffer;
char * coutput = (char *) pBuffer + len * 4;
if(len/block/thread > 0){
convertBack<<<len/block/thread, thread>>>(cinput, coutput, len, thread);
convertBack<<<len%(block*thread), 1>>>(cinput + len/block/thread*block*thread, coutput + len/block/thread*block*thread*3, len, 1);
}else{
convertBack<<<len%(block*thread), 1>>>(cinput, coutput, len, 1);
}
hipDeviceSynchronize();
}
__global__
void convert128(char *input, char *output, int len, int step)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
//if (index < size) *(output + (2 - index % 3) * len + index / 3) = *(input+index);
char * oR = output + index * step, *oG = oR + len, *oB = oG + len;
const char *iPos = (const char *)input + index * step * 3;
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
*(oB++) = *(iPos++);
*(oG++) = *(iPos++);
*(oR++) = *(iPos++);
}
/*
int main(){
int size = 1811520*3;
char * input = (char*) malloc(size);
memset(input, 2, size);
char* output = rgbConvert(input, size);
cudaFree(output);
return EXIT_SUCCESS;
}
*/ | .text
.file "rgbConverter.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__convertPcS_ii # -- Begin function _Z22__device_stub__convertPcS_ii
.p2align 4, 0x90
.type _Z22__device_stub__convertPcS_ii,@function
_Z22__device_stub__convertPcS_ii: # @_Z22__device_stub__convertPcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__convertPcS_ii, .Lfunc_end0-_Z22__device_stub__convertPcS_ii
.cfi_endproc
# -- End function
.globl rgbConvert # -- Begin function rgbConvert
.p2align 4, 0x90
.type rgbConvert,@function
rgbConvert: # @rgbConvert
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %rax
movabsq $4294967296, %r14 # imm = 0x100000000
movslq %esi, %r15
imulq $1431655766, %r15, %r12 # imm = 0x55555556
movq %r12, %rcx
shrq $63, %rcx
shrq $32, %r12
addl %ecx, %r12d
leaq (%rdx,%r15), %r13
movq %rdx, %rdi
movq %rax, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal (%r12,%r12), %eax
leal (%rax,%rax,2), %eax
movslq %eax, %rdi
addq %rbx, %rdi
movslq %r12d, %rdx
xorl %esi, %esi
callq hipMemset
callq hipDeviceSynchronize
cmpl $49152, %r15d # imm = 0xC000
jl .LBB1_5
# %bb.1:
imulq $715827883, %r15, %r15 # imm = 0x2AAAAAAB
movq %r15, %rax
shrq $63, %rax
sarq $45, %r15
addl %eax, %r15d
movl %r15d, %edi
orq %r14, %rdi
leaq 128(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq %rbx, 72(%rsp)
movq %r13, 64(%rsp)
movl %r12d, 12(%rsp)
movl $128, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movl %r12d, %edi
andl $16383, %edi # imm = 0x3FFF
orq %r14, %rdi
incq %r14
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.4:
shll $14, %r15d
leal (%r15,%r15,2), %eax
addq %rax, %rbx
addq %r15, %r13
jmp .LBB1_6
.LBB1_5:
leal 16383(%r12), %eax
testl %r12d, %r12d
cmovnsl %r12d, %eax
andl $-16384, %eax # imm = 0xC000
movl %r12d, %edi
subl %eax, %edi
orq %r14, %rdi
incq %r14
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
.LBB1_6:
movq %rbx, 72(%rsp)
movq %r13, 64(%rsp)
movl %r12d, 12(%rsp)
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size rgbConvert, .Lfunc_end1-rgbConvert
.cfi_endproc
# -- End function
.globl _Z26__device_stub__convertBackPcS_ii # -- Begin function _Z26__device_stub__convertBackPcS_ii
.p2align 4, 0x90
.type _Z26__device_stub__convertBackPcS_ii,@function
_Z26__device_stub__convertBackPcS_ii: # @_Z26__device_stub__convertBackPcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11convertBackPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__convertBackPcS_ii, .Lfunc_end2-_Z26__device_stub__convertBackPcS_ii
.cfi_endproc
# -- End function
.globl rgbConvertBack # -- Begin function rgbConvertBack
.p2align 4, 0x90
.type rgbConvertBack,@function
rgbConvertBack: # @rgbConvertBack
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movl %edi, %ebx
movabsq $4294967296, %r15 # imm = 0x100000000
leal (,%rbx,4), %eax
movslq %eax, %r12
addq %rsi, %r12
leal 16383(%rbx), %r13d
testl %edi, %edi
cmovnsl %edi, %r13d
cmpl $16384, %edi # imm = 0x4000
jl .LBB3_5
# %bb.1:
sarl $14, %r13d
movl %r13d, %edi
orq %r15, %rdi
leaq 128(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.2:
movq %r14, 72(%rsp)
movq %r12, 64(%rsp)
movl %ebx, 12(%rsp)
movl $128, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11convertBackPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_3:
movl %ebx, %edi
andl $16383, %edi # imm = 0x3FFF
orq %r15, %rdi
incq %r15
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.4:
shll $14, %r13d
addq %r13, %r14
leal (%r13,%r13,2), %eax
addq %rax, %r12
jmp .LBB3_6
.LBB3_5:
andl $-16384, %r13d # imm = 0xC000
movl %ebx, %eax
subl %r13d, %eax
movl %eax, %edi
orq %r15, %rdi
incq %r15
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
.LBB3_6:
movq %r14, 72(%rsp)
movq %r12, 64(%rsp)
movl %ebx, 12(%rsp)
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11convertBackPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size rgbConvertBack, .Lfunc_end3-rgbConvertBack
.cfi_endproc
# -- End function
.globl _Z25__device_stub__convert128PcS_ii # -- Begin function _Z25__device_stub__convert128PcS_ii
.p2align 4, 0x90
.type _Z25__device_stub__convert128PcS_ii,@function
_Z25__device_stub__convert128PcS_ii: # @_Z25__device_stub__convert128PcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10convert128PcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z25__device_stub__convert128PcS_ii, .Lfunc_end4-_Z25__device_stub__convert128PcS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7convertPcS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11convertBackPcS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10convert128PcS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7convertPcS_ii,@object # @_Z7convertPcS_ii
.section .rodata,"a",@progbits
.globl _Z7convertPcS_ii
.p2align 3, 0x0
_Z7convertPcS_ii:
.quad _Z22__device_stub__convertPcS_ii
.size _Z7convertPcS_ii, 8
.type _Z11convertBackPcS_ii,@object # @_Z11convertBackPcS_ii
.globl _Z11convertBackPcS_ii
.p2align 3, 0x0
_Z11convertBackPcS_ii:
.quad _Z26__device_stub__convertBackPcS_ii
.size _Z11convertBackPcS_ii, 8
.type _Z10convert128PcS_ii,@object # @_Z10convert128PcS_ii
.globl _Z10convert128PcS_ii
.p2align 3, 0x0
_Z10convert128PcS_ii:
.quad _Z25__device_stub__convert128PcS_ii
.size _Z10convert128PcS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7convertPcS_ii"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11convertBackPcS_ii"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10convert128PcS_ii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__convertPcS_ii
.addrsig_sym _Z26__device_stub__convertBackPcS_ii
.addrsig_sym _Z25__device_stub__convert128PcS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7convertPcS_ii
.addrsig_sym _Z11convertBackPcS_ii
.addrsig_sym _Z10convert128PcS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006fc7d_00000000-6_rgbConverter.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4052:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7convertPcS_iiPcS_ii
.type _Z30__device_stub__Z7convertPcS_iiPcS_ii, @function
_Z30__device_stub__Z7convertPcS_iiPcS_ii:
.LFB4074:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7convertPcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4074:
.size _Z30__device_stub__Z7convertPcS_iiPcS_ii, .-_Z30__device_stub__Z7convertPcS_iiPcS_ii
.globl _Z7convertPcS_ii
.type _Z7convertPcS_ii, @function
_Z7convertPcS_ii:
.LFB4075:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4075:
.size _Z7convertPcS_ii, .-_Z7convertPcS_ii
.globl rgbConvert
.type rgbConvert, @function
rgbConvert:
.LFB4048:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %esi, %r12d
movq %rdx, %rbp
movslq %esi, %rdx
imulq $1431655766, %rdx, %rbx
shrq $32, %rbx
movl %esi, %eax
sarl $31, %eax
subl %eax, %ebx
leaq 0(%rbp,%rdx), %r13
movl $1, %ecx
movq %rdi, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movslq %ebx, %rdx
leal (%rbx,%rbx,2), %edi
addl %edi, %edi
movslq %edi, %rdi
addq %rbp, %rdi
movl $0, %esi
call cudaMemset@PLT
call cudaDeviceSynchronize@PLT
cmpl $49151, %r12d
jle .L12
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 16383(%rbx), %r12d
testl %ebx, %ebx
cmovns %ebx, %r12d
sarl $14, %r12d
movl %r12d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L13:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rbx,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl $128, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
jmp .L13
.L19:
movl %r12d, %esi
sall $14, %esi
movslq %esi, %rsi
addq %r13, %rsi
leal (%r12,%r12,2), %edi
sall $14, %edi
movslq %edi, %rdi
addq %rbp, %rdi
movl $1, %ecx
movl %ebx, %edx
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
jmp .L15
.L12:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rbx,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movl $1, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %rbp, %rdi
call _Z30__device_stub__Z7convertPcS_iiPcS_ii
jmp .L15
.cfi_endproc
.LFE4048:
.size rgbConvert, .-rgbConvert
.globl _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
.type _Z35__device_stub__Z11convertBackPcS_iiPcS_ii, @function
_Z35__device_stub__Z11convertBackPcS_iiPcS_ii:
.LFB4076:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11convertBackPcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4076:
.size _Z35__device_stub__Z11convertBackPcS_iiPcS_ii, .-_Z35__device_stub__Z11convertBackPcS_iiPcS_ii
.globl _Z11convertBackPcS_ii
.type _Z11convertBackPcS_ii, @function
_Z11convertBackPcS_ii:
.LFB4077:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4077:
.size _Z11convertBackPcS_ii, .-_Z11convertBackPcS_ii
.globl rgbConvertBack
.type rgbConvertBack, @function
rgbConvertBack:
.LFB4049:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %r13
leal 0(,%rdi,4), %eax
cltq
leaq (%rsi,%rax), %r12
cmpl $16383, %edi
jle .L29
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 16383(%rdi), %ebp
testl %edi, %edi
cmovns %edi, %ebp
sarl $14, %ebp
movl %ebp, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rbx,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $128, %ecx
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
jmp .L30
.L36:
leal 0(%rbp,%rbp,2), %esi
sall $14, %esi
movslq %esi, %rsi
addq %r12, %rsi
sall $14, %ebp
movslq %ebp, %rdi
addq %r13, %rdi
movl $1, %ecx
movl %ebx, %edx
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
jmp .L32
.L29:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %edi, %edx
sarl $31, %edx
shrl $18, %edx
leal (%rdi,%rdx), %eax
andl $16383, %eax
subl %edx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z35__device_stub__Z11convertBackPcS_iiPcS_ii
jmp .L32
.cfi_endproc
.LFE4049:
.size rgbConvertBack, .-rgbConvertBack
.globl _Z34__device_stub__Z10convert128PcS_iiPcS_ii
.type _Z34__device_stub__Z10convert128PcS_iiPcS_ii, @function
_Z34__device_stub__Z10convert128PcS_iiPcS_ii:
.LFB4078:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10convert128PcS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4078:
.size _Z34__device_stub__Z10convert128PcS_iiPcS_ii, .-_Z34__device_stub__Z10convert128PcS_iiPcS_ii
.globl _Z10convert128PcS_ii
.type _Z10convert128PcS_ii, @function
_Z10convert128PcS_ii:
.LFB4079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10convert128PcS_iiPcS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4079:
.size _Z10convert128PcS_ii, .-_Z10convert128PcS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10convert128PcS_ii"
.LC1:
.string "_Z11convertBackPcS_ii"
.LC2:
.string "_Z7convertPcS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4081:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10convert128PcS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11convertBackPcS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7convertPcS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4081:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rgbConverter.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__convertPcS_ii # -- Begin function _Z22__device_stub__convertPcS_ii
.p2align 4, 0x90
.type _Z22__device_stub__convertPcS_ii,@function
_Z22__device_stub__convertPcS_ii: # @_Z22__device_stub__convertPcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__convertPcS_ii, .Lfunc_end0-_Z22__device_stub__convertPcS_ii
.cfi_endproc
# -- End function
.globl rgbConvert # -- Begin function rgbConvert
.p2align 4, 0x90
.type rgbConvert,@function
rgbConvert: # @rgbConvert
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %rax
movabsq $4294967296, %r14 # imm = 0x100000000
movslq %esi, %r15
imulq $1431655766, %r15, %r12 # imm = 0x55555556
movq %r12, %rcx
shrq $63, %rcx
shrq $32, %r12
addl %ecx, %r12d
leaq (%rdx,%r15), %r13
movq %rdx, %rdi
movq %rax, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
leal (%r12,%r12), %eax
leal (%rax,%rax,2), %eax
movslq %eax, %rdi
addq %rbx, %rdi
movslq %r12d, %rdx
xorl %esi, %esi
callq hipMemset
callq hipDeviceSynchronize
cmpl $49152, %r15d # imm = 0xC000
jl .LBB1_5
# %bb.1:
imulq $715827883, %r15, %r15 # imm = 0x2AAAAAAB
movq %r15, %rax
shrq $63, %rax
sarq $45, %r15
addl %eax, %r15d
movl %r15d, %edi
orq %r14, %rdi
leaq 128(%r14), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movq %rbx, 72(%rsp)
movq %r13, 64(%rsp)
movl %r12d, 12(%rsp)
movl $128, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
movl %r12d, %edi
andl $16383, %edi # imm = 0x3FFF
orq %r14, %rdi
incq %r14
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.4:
shll $14, %r15d
leal (%r15,%r15,2), %eax
addq %rax, %rbx
addq %r15, %r13
jmp .LBB1_6
.LBB1_5:
leal 16383(%r12), %eax
testl %r12d, %r12d
cmovnsl %r12d, %eax
andl $-16384, %eax # imm = 0xC000
movl %r12d, %edi
subl %eax, %edi
orq %r14, %rdi
incq %r14
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
.LBB1_6:
movq %rbx, 72(%rsp)
movq %r13, 64(%rsp)
movl %r12d, 12(%rsp)
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size rgbConvert, .Lfunc_end1-rgbConvert
.cfi_endproc
# -- End function
.globl _Z26__device_stub__convertBackPcS_ii # -- Begin function _Z26__device_stub__convertBackPcS_ii
.p2align 4, 0x90
.type _Z26__device_stub__convertBackPcS_ii,@function
_Z26__device_stub__convertBackPcS_ii: # @_Z26__device_stub__convertBackPcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11convertBackPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z26__device_stub__convertBackPcS_ii, .Lfunc_end2-_Z26__device_stub__convertBackPcS_ii
.cfi_endproc
# -- End function
.globl rgbConvertBack # -- Begin function rgbConvertBack
.p2align 4, 0x90
.type rgbConvertBack,@function
rgbConvertBack: # @rgbConvertBack
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movl %edi, %ebx
movabsq $4294967296, %r15 # imm = 0x100000000
leal (,%rbx,4), %eax
movslq %eax, %r12
addq %rsi, %r12
leal 16383(%rbx), %r13d
testl %edi, %edi
cmovnsl %edi, %r13d
cmpl $16384, %edi # imm = 0x4000
jl .LBB3_5
# %bb.1:
sarl $14, %r13d
movl %r13d, %edi
orq %r15, %rdi
leaq 128(%r15), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.2:
movq %r14, 72(%rsp)
movq %r12, 64(%rsp)
movl %ebx, 12(%rsp)
movl $128, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11convertBackPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_3:
movl %ebx, %edi
andl $16383, %edi # imm = 0x3FFF
orq %r15, %rdi
incq %r15
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.4:
shll $14, %r13d
addq %r13, %r14
leal (%r13,%r13,2), %eax
addq %rax, %r12
jmp .LBB3_6
.LBB3_5:
andl $-16384, %r13d # imm = 0xC000
movl %ebx, %eax
subl %r13d, %eax
movl %eax, %edi
orq %r15, %rdi
incq %r15
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
.LBB3_6:
movq %r14, 72(%rsp)
movq %r12, 64(%rsp)
movl %ebx, 12(%rsp)
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11convertBackPcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size rgbConvertBack, .Lfunc_end3-rgbConvertBack
.cfi_endproc
# -- End function
.globl _Z25__device_stub__convert128PcS_ii # -- Begin function _Z25__device_stub__convert128PcS_ii
.p2align 4, 0x90
.type _Z25__device_stub__convert128PcS_ii,@function
_Z25__device_stub__convert128PcS_ii: # @_Z25__device_stub__convert128PcS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10convert128PcS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z25__device_stub__convert128PcS_ii, .Lfunc_end4-_Z25__device_stub__convert128PcS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7convertPcS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11convertBackPcS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10convert128PcS_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7convertPcS_ii,@object # @_Z7convertPcS_ii
.section .rodata,"a",@progbits
.globl _Z7convertPcS_ii
.p2align 3, 0x0
_Z7convertPcS_ii:
.quad _Z22__device_stub__convertPcS_ii
.size _Z7convertPcS_ii, 8
.type _Z11convertBackPcS_ii,@object # @_Z11convertBackPcS_ii
.globl _Z11convertBackPcS_ii
.p2align 3, 0x0
_Z11convertBackPcS_ii:
.quad _Z26__device_stub__convertBackPcS_ii
.size _Z11convertBackPcS_ii, 8
.type _Z10convert128PcS_ii,@object # @_Z10convert128PcS_ii
.globl _Z10convert128PcS_ii
.p2align 3, 0x0
_Z10convert128PcS_ii:
.quad _Z25__device_stub__convert128PcS_ii
.size _Z10convert128PcS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7convertPcS_ii"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11convertBackPcS_ii"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10convert128PcS_ii"
.size .L__unnamed_3, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__convertPcS_ii
.addrsig_sym _Z26__device_stub__convertBackPcS_ii
.addrsig_sym _Z25__device_stub__convert128PcS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7convertPcS_ii
.addrsig_sym _Z11convertBackPcS_ii
.addrsig_sym _Z10convert128PcS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* 2DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05
#define GPU_DEVICE 0
/* Problem size */
#define NI 4096
#define NJ 4096
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv2D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
B[i*NJ + j] = c11 * A[(i - 1)*NJ + (j - 1)] + c12 * A[(i + 0)*NJ + (j - 1)] + c13 * A[(i + 1)*NJ + (j - 1)]
+ c21 * A[(i - 1)*NJ + (j + 0)] + c22 * A[(i + 0)*NJ + (j + 0)] + c23 * A[(i + 1)*NJ + (j + 0)]
+ c31 * A[(i - 1)*NJ + (j + 1)] + c32 * A[(i + 0)*NJ + (j + 1)] + c33 * A[(i + 1)*NJ + (j + 1)];
}
}
}
void init(DATA_TYPE* A)
{
int i, j;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
A[i*NJ + j] = (float)rand()/RAND_MAX;
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, fail;
fail = 0;
// Compare a and b
for (i=1; i < (NI-1); i++)
{
for (j=1; j < (NJ-1); j++)
{
if (percentDiff(B[i*NJ + j], B_outputFromGpu[i*NJ + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void Convolution2D_kernel(DATA_TYPE *A, DATA_TYPE *B)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
if ((i < NI-1) && (j < NJ-1) && (i > 0) && (j > 0))
{
B[i * NJ + j] = c11 * A[(i - 1) * NJ + (j - 1)] + c21 * A[(i - 1) * NJ + (j + 0)] + c31 * A[(i - 1) * NJ + (j + 1)]
+ c12 * A[(i + 0) * NJ + (j - 1)] + c22 * A[(i + 0) * NJ + (j + 0)] + c32 * A[(i + 0) * NJ + (j + 1)]
+ c13 * A[(i + 1) * NJ + (j - 1)] + c23 * A[(i + 1) * NJ + (j + 0)] + c33 * A[(i + 1) * NJ + (j + 1)];
}
}
void convolution2DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
cudaMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ);
cudaMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ);
cudaMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ, cudaMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)ceil( ((float)NI) / ((float)block.x) ), (size_t)ceil( ((float)NJ) / ((float)block.y)) );
t_start = rtclock();
Convolution2D_kernel<<<grid,block>>>(A_gpu,B_gpu);
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);//);
cudaMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ, cudaMemcpyDeviceToHost);
cudaFree(A_gpu);
cudaFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
//initialize the arrays
init(A);
GPU_argv_init();
convolution2DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv2D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);//);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | code for sm_80
Function : _Z20Convolution2D_kernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0205 */
/*0080*/ ISETP.GT.U32.AND P0, PT, R2, 0xffd, PT ; /* 0x00000ffd0200780c */
/* 0x000fe40003f04070 */
/*0090*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.GT.U32.OR P0, PT, R4, 0xffd, P0 ; /* 0x00000ffd0400780c */
/* 0x000fda0000704470 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*00d0*/ LEA R0, R3, R0, 0xc ; /* 0x0000000003007211 */
/* 0x000fe200078e60ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IADD3 R2, R0, -0x1001, RZ ; /* 0xffffefff00027810 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE R2, R2, R21, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0215 */
/*0110*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee2000c1e1900 */
/*0130*/ IMAD.WIDE R4, R0, R21, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0215 */
/*0140*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R11, [R2.64+0x4000] ; /* 0x00400004020b7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R13, [R2.64+0x4008] ; /* 0x00400804020d7981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R15, [R2.64+0x8000] ; /* 0x00800004020f7981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R17, [R2.64+0x8004] ; /* 0x0080040402117981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R19, [R2.64+0x8008] ; /* 0x0080080402137981 */
/* 0x000f62000c1e1900 */
/*01b0*/ FMUL R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x004fc80000400000 */
/*01c0*/ FFMA R6, R6, 0.20000000298023223877, R7 ; /* 0x3e4ccccd06067823 */
/* 0x008fc80000000007 */
/*01d0*/ FFMA R6, R9, -0.80000001192092895508, R6 ; /* 0xbf4ccccd09067823 */
/* 0x010fc80000000006 */
/*01e0*/ FFMA R6, R11, -0.30000001192092895508, R6 ; /* 0xbe99999a0b067823 */
/* 0x020fc80000000006 */
/*01f0*/ FFMA R6, R5, 0.60000002384185791016, R6 ; /* 0x3f19999a05067823 */
/* 0x000fe40000000006 */
/*0200*/ IMAD.WIDE R4, R0, R21, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0215 */
/*0210*/ FFMA R6, R13, -0.89999997615814208984, R6 ; /* 0xbf6666660d067823 */
/* 0x000fc80000000006 */
/*0220*/ FFMA R6, R15, 0.40000000596046447754, R6 ; /* 0x3ecccccd0f067823 */
/* 0x000fc80000000006 */
/*0230*/ FFMA R6, R17, 0.69999998807907104492, R6 ; /* 0x3f33333311067823 */
/* 0x000fc80000000006 */
/*0240*/ FFMA R19, R19, 0.10000000149011611938, R6 ; /* 0x3dcccccd13137823 */
/* 0x000fca0000000006 */
/*0250*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* 2DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05
#define GPU_DEVICE 0
/* Problem size */
#define NI 4096
#define NJ 4096
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv2D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
B[i*NJ + j] = c11 * A[(i - 1)*NJ + (j - 1)] + c12 * A[(i + 0)*NJ + (j - 1)] + c13 * A[(i + 1)*NJ + (j - 1)]
+ c21 * A[(i - 1)*NJ + (j + 0)] + c22 * A[(i + 0)*NJ + (j + 0)] + c23 * A[(i + 1)*NJ + (j + 0)]
+ c31 * A[(i - 1)*NJ + (j + 1)] + c32 * A[(i + 0)*NJ + (j + 1)] + c33 * A[(i + 1)*NJ + (j + 1)];
}
}
}
void init(DATA_TYPE* A)
{
int i, j;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
A[i*NJ + j] = (float)rand()/RAND_MAX;
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, fail;
fail = 0;
// Compare a and b
for (i=1; i < (NI-1); i++)
{
for (j=1; j < (NJ-1); j++)
{
if (percentDiff(B[i*NJ + j], B_outputFromGpu[i*NJ + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void Convolution2D_kernel(DATA_TYPE *A, DATA_TYPE *B)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
if ((i < NI-1) && (j < NJ-1) && (i > 0) && (j > 0))
{
B[i * NJ + j] = c11 * A[(i - 1) * NJ + (j - 1)] + c21 * A[(i - 1) * NJ + (j + 0)] + c31 * A[(i - 1) * NJ + (j + 1)]
+ c12 * A[(i + 0) * NJ + (j - 1)] + c22 * A[(i + 0) * NJ + (j + 0)] + c32 * A[(i + 0) * NJ + (j + 1)]
+ c13 * A[(i + 1) * NJ + (j - 1)] + c23 * A[(i + 1) * NJ + (j + 0)] + c33 * A[(i + 1) * NJ + (j + 1)];
}
}
void convolution2DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
cudaMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ);
cudaMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ);
cudaMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ, cudaMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)ceil( ((float)NI) / ((float)block.x) ), (size_t)ceil( ((float)NJ) / ((float)block.y)) );
t_start = rtclock();
Convolution2D_kernel<<<grid,block>>>(A_gpu,B_gpu);
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);//);
cudaMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ, cudaMemcpyDeviceToHost);
cudaFree(A_gpu);
cudaFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
//initialize the arrays
init(A);
GPU_argv_init();
convolution2DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv2D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);//);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | .file "tmpxft_0016357c_00000000-6_2DConvolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2070:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z6absValf
.type _Z6absValf, @function
_Z6absValf:
.LFB2071:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L13
.L10:
ret
.L13:
xorps .LC3(%rip), %xmm0
ret
.cfi_endproc
.LFE2071:
.size _Z6absValf, .-_Z6absValf
.globl _Z11percentDiffdd
.type _Z11percentDiffdd, @function
_Z11percentDiffdd:
.LFB2072:
.cfi_startproc
endbr64
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L35
.L15:
cvtss2sd %xmm2, %xmm2
movsd .LC4(%rip), %xmm3
comisd %xmm2, %xmm3
jbe .L17
pxor %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L36
.L19:
pxor %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
pxor %xmm2, %xmm2
movsd .LC4(%rip), %xmm4
comisd %xmm3, %xmm4
ja .L14
.L17:
movapd %xmm0, %xmm2
subsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
pxor %xmm1, %xmm1
comiss %xmm2, %xmm1
ja .L37
.L22:
addsd .LC5(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
pxor %xmm0, %xmm0
comiss %xmm1, %xmm0
ja .L38
.L24:
movaps %xmm2, %xmm0
divss %xmm1, %xmm0
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L39
.L26:
movaps %xmm0, %xmm2
mulss .LC6(%rip), %xmm2
.L14:
movaps %xmm2, %xmm0
ret
.L35:
xorps .LC3(%rip), %xmm2
jmp .L15
.L36:
xorps .LC3(%rip), %xmm2
jmp .L19
.L37:
xorps .LC3(%rip), %xmm2
jmp .L22
.L38:
xorps .LC3(%rip), %xmm1
jmp .L24
.L39:
xorps .LC3(%rip), %xmm0
jmp .L26
.cfi_endproc
.LFE2072:
.size _Z11percentDiffdd, .-_Z11percentDiffdd
.globl _Z6conv2DPfS_
.type _Z6conv2DPfS_, @function
_Z6conv2DPfS_:
.LFB2073:
.cfi_startproc
endbr64
addq $16388, %rsi
leaq 16376(%rdi), %rcx
movl $0, %edi
movss .LC7(%rip), %xmm9
movss .LC8(%rip), %xmm8
movss .LC9(%rip), %xmm7
movss .LC10(%rip), %xmm6
movss .LC11(%rip), %xmm5
movss .LC12(%rip), %xmm4
movss .LC13(%rip), %xmm3
movss .LC14(%rip), %xmm2
movss .LC15(%rip), %xmm1
.L41:
addl $4096, %edi
leaq -16376(%rcx), %rax
movq %rsi, %rdx
.L42:
movaps %xmm9, %xmm0
mulss (%rax), %xmm0
movaps %xmm8, %xmm10
mulss 16384(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm7, %xmm10
mulss 32768(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm6, %xmm10
mulss 4(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm5, %xmm10
mulss 16388(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm4, %xmm10
mulss 32772(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm3, %xmm10
mulss 8(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm2, %xmm10
mulss 16392(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm1, %xmm10
mulss 32776(%rax), %xmm10
addss %xmm10, %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
addq $4, %rdx
cmpq %rcx, %rax
jne .L42
addq $16384, %rsi
addq $16384, %rcx
cmpl $16769024, %edi
jne .L41
ret
.cfi_endproc
.LFE2073:
.size _Z6conv2DPfS_, .-_Z6conv2DPfS_
.globl _Z4initPf
.type _Z4initPf, @function
_Z4initPf:
.LFB2074:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
leaq 16384(%rdi), %rbp
addq $67125248, %r12
.L46:
leaq -16384(%rbp), %rbx
.L47:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC16(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L47
addq $16384, %rbp
cmpq %r12, %rbp
jne .L46
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _Z4initPf, .-_Z4initPf
.section .rodata.str1.8
.align 8
.LC18:
.string "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.text
.globl _Z14compareResultsPfS_
.type _Z14compareResultsPfS_, @function
_Z14compareResultsPfS_:
.LFB2075:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r14
leaq 16384(%rsi), %r12
leaq 16384(%rdi), %r13
addq $67092480, %r14
movl $0, %ebp
.L52:
movl $1, %ebx
.L55:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
call _Z11percentDiffdd
cvtss2sd %xmm0, %xmm0
comisd .LC17(%rip), %xmm0
seta %al
movzbl %al, %eax
addl %eax, %ebp
addq $1, %rbx
cmpq $4095, %rbx
jne .L55
addq $16384, %r12
addq $16384, %r13
cmpq %r14, %r12
jne .L52
movl %ebp, %edx
movsd .LC17(%rip), %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z14compareResultsPfS_, .-_Z14compareResultsPfS_
.section .rodata.str1.8
.align 8
.LC19:
.string "setting device %d with name %s\n"
.text
.globl _Z13GPU_argv_initv
.type _Z13GPU_argv_initv, @function
_Z13GPU_argv_initv:
.LFB2076:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size _Z13GPU_argv_initv, .-_Z13GPU_argv_initv
.globl _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
.type _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_, @function
_Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_:
.LFB2103:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20Convolution2D_kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_, .-_Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
.globl _Z20Convolution2D_kernelPfS_
.type _Z20Convolution2D_kernelPfS_, @function
_Z20Convolution2D_kernelPfS_:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z20Convolution2D_kernelPfS_, .-_Z20Convolution2D_kernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC20:
.string "GPU Runtime: %0.6lfs\n"
.text
.globl _Z17convolution2DCudaPfS_S_
.type _Z17convolution2DCudaPfS_S_, @function
_Z17convolution2DCudaPfS_S_:
.LFB2077:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $512, 48(%rsp)
movl $1, 52(%rsp)
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl $32, 32(%rsp)
movl $8, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L73:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $2, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
jmp .L73
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z17convolution2DCudaPfS_S_, .-_Z17convolution2DCudaPfS_S_
.section .rodata.str1.1
.LC21:
.string "CPU Runtime: %0.6lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2078:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z4initPf
call _Z13GPU_argv_initv
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z17convolution2DCudaPfS_S_
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6conv2DPfS_
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _Z14compareResultsPfS_
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z20Convolution2D_kernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z20Convolution2D_kernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long 1202590843
.long 1065646817
.align 8
.LC5:
.long -536870912
.long 1044740494
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1120403456
.align 4
.LC7:
.long 1045220557
.align 4
.LC8:
.long -1097229926
.align 4
.LC9:
.long 1053609165
.align 4
.LC10:
.long 1056964608
.align 4
.LC11:
.long 1058642330
.align 4
.LC12:
.long 1060320051
.align 4
.LC13:
.long -1085485875
.align 4
.LC14:
.long -1083808154
.align 4
.LC15:
.long 1036831949
.align 4
.LC16:
.long 805306368
.section .rodata.cst8
.align 8
.LC17:
.long -1717986918
.long 1068079513
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* 2DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05
#define GPU_DEVICE 0
/* Problem size */
#define NI 4096
#define NJ 4096
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv2D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
B[i*NJ + j] = c11 * A[(i - 1)*NJ + (j - 1)] + c12 * A[(i + 0)*NJ + (j - 1)] + c13 * A[(i + 1)*NJ + (j - 1)]
+ c21 * A[(i - 1)*NJ + (j + 0)] + c22 * A[(i + 0)*NJ + (j + 0)] + c23 * A[(i + 1)*NJ + (j + 0)]
+ c31 * A[(i - 1)*NJ + (j + 1)] + c32 * A[(i + 0)*NJ + (j + 1)] + c33 * A[(i + 1)*NJ + (j + 1)];
}
}
}
void init(DATA_TYPE* A)
{
int i, j;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
A[i*NJ + j] = (float)rand()/RAND_MAX;
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, fail;
fail = 0;
// Compare a and b
for (i=1; i < (NI-1); i++)
{
for (j=1; j < (NJ-1); j++)
{
if (percentDiff(B[i*NJ + j], B_outputFromGpu[i*NJ + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void Convolution2D_kernel(DATA_TYPE *A, DATA_TYPE *B)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
if ((i < NI-1) && (j < NJ-1) && (i > 0) && (j > 0))
{
B[i * NJ + j] = c11 * A[(i - 1) * NJ + (j - 1)] + c21 * A[(i - 1) * NJ + (j + 0)] + c31 * A[(i - 1) * NJ + (j + 1)]
+ c12 * A[(i + 0) * NJ + (j - 1)] + c22 * A[(i + 0) * NJ + (j + 0)] + c32 * A[(i + 0) * NJ + (j + 1)]
+ c13 * A[(i + 1) * NJ + (j - 1)] + c23 * A[(i + 1) * NJ + (j + 0)] + c33 * A[(i + 1) * NJ + (j + 1)];
}
}
void convolution2DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
cudaMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ);
cudaMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ);
cudaMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ, cudaMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)ceil( ((float)NI) / ((float)block.x) ), (size_t)ceil( ((float)NJ) / ((float)block.y)) );
t_start = rtclock();
Convolution2D_kernel<<<grid,block>>>(A_gpu,B_gpu);
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);//);
cudaMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ, cudaMemcpyDeviceToHost);
cudaFree(A_gpu);
cudaFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
//initialize the arrays
init(A);
GPU_argv_init();
convolution2DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv2D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);//);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | /**
* 2DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05
#define GPU_DEVICE 0
/* Problem size */
#define NI 4096
#define NJ 4096
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv2D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
B[i*NJ + j] = c11 * A[(i - 1)*NJ + (j - 1)] + c12 * A[(i + 0)*NJ + (j - 1)] + c13 * A[(i + 1)*NJ + (j - 1)]
+ c21 * A[(i - 1)*NJ + (j + 0)] + c22 * A[(i + 0)*NJ + (j + 0)] + c23 * A[(i + 1)*NJ + (j + 0)]
+ c31 * A[(i - 1)*NJ + (j + 1)] + c32 * A[(i + 0)*NJ + (j + 1)] + c33 * A[(i + 1)*NJ + (j + 1)];
}
}
}
void init(DATA_TYPE* A)
{
int i, j;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
A[i*NJ + j] = (float)rand()/RAND_MAX;
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, fail;
fail = 0;
// Compare a and b
for (i=1; i < (NI-1); i++)
{
for (j=1; j < (NJ-1); j++)
{
if (percentDiff(B[i*NJ + j], B_outputFromGpu[i*NJ + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void Convolution2D_kernel(DATA_TYPE *A, DATA_TYPE *B)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
if ((i < NI-1) && (j < NJ-1) && (i > 0) && (j > 0))
{
B[i * NJ + j] = c11 * A[(i - 1) * NJ + (j - 1)] + c21 * A[(i - 1) * NJ + (j + 0)] + c31 * A[(i - 1) * NJ + (j + 1)]
+ c12 * A[(i + 0) * NJ + (j - 1)] + c22 * A[(i + 0) * NJ + (j + 0)] + c32 * A[(i + 0) * NJ + (j + 1)]
+ c13 * A[(i + 1) * NJ + (j - 1)] + c23 * A[(i + 1) * NJ + (j + 0)] + c33 * A[(i + 1) * NJ + (j + 1)];
}
}
void convolution2DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
hipMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ);
hipMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ);
hipMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ, hipMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)ceil( ((float)NI) / ((float)block.x) ), (size_t)ceil( ((float)NJ) / ((float)block.y)) );
t_start = rtclock();
Convolution2D_kernel<<<grid,block>>>(A_gpu,B_gpu);
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);//);
hipMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ, hipMemcpyDeviceToHost);
hipFree(A_gpu);
hipFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
//initialize the arrays
init(A);
GPU_argv_init();
convolution2DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv2D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);//);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* 2DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05
#define GPU_DEVICE 0
/* Problem size */
#define NI 4096
#define NJ 4096
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv2D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
B[i*NJ + j] = c11 * A[(i - 1)*NJ + (j - 1)] + c12 * A[(i + 0)*NJ + (j - 1)] + c13 * A[(i + 1)*NJ + (j - 1)]
+ c21 * A[(i - 1)*NJ + (j + 0)] + c22 * A[(i + 0)*NJ + (j + 0)] + c23 * A[(i + 1)*NJ + (j + 0)]
+ c31 * A[(i - 1)*NJ + (j + 1)] + c32 * A[(i + 0)*NJ + (j + 1)] + c33 * A[(i + 1)*NJ + (j + 1)];
}
}
}
void init(DATA_TYPE* A)
{
int i, j;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
A[i*NJ + j] = (float)rand()/RAND_MAX;
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, fail;
fail = 0;
// Compare a and b
for (i=1; i < (NI-1); i++)
{
for (j=1; j < (NJ-1); j++)
{
if (percentDiff(B[i*NJ + j], B_outputFromGpu[i*NJ + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void Convolution2D_kernel(DATA_TYPE *A, DATA_TYPE *B)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
if ((i < NI-1) && (j < NJ-1) && (i > 0) && (j > 0))
{
B[i * NJ + j] = c11 * A[(i - 1) * NJ + (j - 1)] + c21 * A[(i - 1) * NJ + (j + 0)] + c31 * A[(i - 1) * NJ + (j + 1)]
+ c12 * A[(i + 0) * NJ + (j - 1)] + c22 * A[(i + 0) * NJ + (j + 0)] + c32 * A[(i + 0) * NJ + (j + 1)]
+ c13 * A[(i + 1) * NJ + (j - 1)] + c23 * A[(i + 1) * NJ + (j + 0)] + c33 * A[(i + 1) * NJ + (j + 1)];
}
}
void convolution2DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
hipMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ);
hipMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ);
hipMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ, hipMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)ceil( ((float)NI) / ((float)block.x) ), (size_t)ceil( ((float)NJ) / ((float)block.y)) );
t_start = rtclock();
Convolution2D_kernel<<<grid,block>>>(A_gpu,B_gpu);
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);//);
hipMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ, hipMemcpyDeviceToHost);
hipFree(A_gpu);
hipFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
//initialize the arrays
init(A);
GPU_argv_init();
convolution2DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv2D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);//);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20Convolution2D_kernelPfS_
.globl _Z20Convolution2D_kernelPfS_
.p2align 8
.type _Z20Convolution2D_kernelPfS_,@function
_Z20Convolution2D_kernelPfS_:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v3, -1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, -1, v0
v_max_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0xffe, v3
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v14, 12, v2
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v15, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0xfffff000, v14
v_add_nc_u32_e32 v16, 0x1000, v14
v_add_nc_u32_e32 v2, v8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, v8, v0
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, v8, v15
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, v14, v1
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_add_nc_u32_e32 v2, v14, v0
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_lshlrev_b64 v[12:13], 2, v[2:3]
v_add_nc_u32_e32 v2, v14, v15
s_clause 0x2
global_load_b32 v14, v[4:5], off
global_load_b32 v17, v[6:7], off
global_load_b32 v18, v[8:9], off
v_add_co_u32 v4, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v11, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, v16, v1
v_add_co_u32 v8, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_add_nc_u32_e32 v2, v16, v0
v_add_co_u32 v0, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
s_clause 0x2
global_load_b32 v19, v[4:5], off
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[0:1], off
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s0, v10
v_add_nc_u32_e32 v2, v16, v15
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_clause 0x1
global_load_b32 v6, v[0:1], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(7)
v_mul_f32_e32 v1, 0.5, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v14, 0x3e4ccccd, v1
s_waitcnt vmcnt(6)
v_fmamk_f32 v1, v18, 0xbf4ccccd, v1
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v19, 0xbe99999a, v1
s_waitcnt vmcnt(4)
v_fmamk_f32 v1, v8, 0x3f19999a, v1
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v9, 0xbf666666, v1
s_waitcnt vmcnt(2)
v_fmamk_f32 v1, v6, 0x3ecccccd, v1
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v4, 0x3f333333, v1
s_waitcnt vmcnt(0)
v_fmamk_f32 v2, v0, 0x3dcccccd, v1
v_add_co_u32 v0, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v13, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20Convolution2D_kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20Convolution2D_kernelPfS_, .Lfunc_end0-_Z20Convolution2D_kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20Convolution2D_kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20Convolution2D_kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* 2DConvolution.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <stdlib.h>
#include <stdarg.h>
#include <string.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 0.05
#define GPU_DEVICE 0
/* Problem size */
#define NI 4096
#define NJ 4096
/* Thread block dimensions */
#define DIM_THREAD_BLOCK_X 32
#define DIM_THREAD_BLOCK_Y 8
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void conv2D(DATA_TYPE* A, DATA_TYPE* B)
{
int i, j;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
for (i = 1; i < NI - 1; ++i) // 0
{
for (j = 1; j < NJ - 1; ++j) // 1
{
B[i*NJ + j] = c11 * A[(i - 1)*NJ + (j - 1)] + c12 * A[(i + 0)*NJ + (j - 1)] + c13 * A[(i + 1)*NJ + (j - 1)]
+ c21 * A[(i - 1)*NJ + (j + 0)] + c22 * A[(i + 0)*NJ + (j + 0)] + c23 * A[(i + 1)*NJ + (j + 0)]
+ c31 * A[(i - 1)*NJ + (j + 1)] + c32 * A[(i + 0)*NJ + (j + 1)] + c33 * A[(i + 1)*NJ + (j + 1)];
}
}
}
void init(DATA_TYPE* A)
{
int i, j;
for (i = 0; i < NI; ++i)
{
for (j = 0; j < NJ; ++j)
{
A[i*NJ + j] = (float)rand()/RAND_MAX;
}
}
}
void compareResults(DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
int i, j, fail;
fail = 0;
// Compare a and b
for (i=1; i < (NI-1); i++)
{
for (j=1; j < (NJ-1); j++)
{
if (percentDiff(B[i*NJ + j], B_outputFromGpu[i*NJ + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
}
}
}
// Print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void Convolution2D_kernel(DATA_TYPE *A, DATA_TYPE *B)
{
int j = blockIdx.x * blockDim.x + threadIdx.x;
int i = blockIdx.y * blockDim.y + threadIdx.y;
DATA_TYPE c11, c12, c13, c21, c22, c23, c31, c32, c33;
c11 = +0.2; c21 = +0.5; c31 = -0.8;
c12 = -0.3; c22 = +0.6; c32 = -0.9;
c13 = +0.4; c23 = +0.7; c33 = +0.10;
if ((i < NI-1) && (j < NJ-1) && (i > 0) && (j > 0))
{
B[i * NJ + j] = c11 * A[(i - 1) * NJ + (j - 1)] + c21 * A[(i - 1) * NJ + (j + 0)] + c31 * A[(i - 1) * NJ + (j + 1)]
+ c12 * A[(i + 0) * NJ + (j - 1)] + c22 * A[(i + 0) * NJ + (j + 0)] + c32 * A[(i + 0) * NJ + (j + 1)]
+ c13 * A[(i + 1) * NJ + (j - 1)] + c23 * A[(i + 1) * NJ + (j + 0)] + c33 * A[(i + 1) * NJ + (j + 1)];
}
}
void convolution2DCuda(DATA_TYPE* A, DATA_TYPE* B, DATA_TYPE* B_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *A_gpu;
DATA_TYPE *B_gpu;
hipMalloc((void **)&A_gpu, sizeof(DATA_TYPE) * NI * NJ);
hipMalloc((void **)&B_gpu, sizeof(DATA_TYPE) * NI * NJ);
hipMemcpy(A_gpu, A, sizeof(DATA_TYPE) * NI * NJ, hipMemcpyHostToDevice);
dim3 block(DIM_THREAD_BLOCK_X, DIM_THREAD_BLOCK_Y);
dim3 grid((size_t)ceil( ((float)NI) / ((float)block.x) ), (size_t)ceil( ((float)NJ) / ((float)block.y)) );
t_start = rtclock();
Convolution2D_kernel<<<grid,block>>>(A_gpu,B_gpu);
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);//);
hipMemcpy(B_outputFromGpu, B_gpu, sizeof(DATA_TYPE) * NI * NJ, hipMemcpyDeviceToHost);
hipFree(A_gpu);
hipFree(B_gpu);
}
int main(int argc, char *argv[])
{
double t_start, t_end;
DATA_TYPE* A;
DATA_TYPE* B;
DATA_TYPE* B_outputFromGpu;
A = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
B_outputFromGpu = (DATA_TYPE*)malloc(NI*NJ*sizeof(DATA_TYPE));
//initialize the arrays
init(A);
GPU_argv_init();
convolution2DCuda(A, B, B_outputFromGpu);
t_start = rtclock();
conv2D(A, B);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);//);
compareResults(B, B_outputFromGpu);
free(A);
free(B);
free(B_outputFromGpu);
return 0;
} | .text
.file "2DConvolution.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6absValf
.LCPI1_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z6absValf
.p2align 4, 0x90
.type _Z6absValf,@function
_Z6absValf: # @_Z6absValf
.cfi_startproc
# %bb.0:
movaps .LCPI1_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end1:
.size _Z6absValf, .Lfunc_end1-_Z6absValf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11percentDiffdd
.LCPI2_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI2_2:
.quad 0x3e45798ee0000000 # double 9.9999999392252903E-9
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_3:
.long 0x42c80000 # float 100
.text
.globl _Z11percentDiffdd
.p2align 4, 0x90
.type _Z11percentDiffdd,@function
_Z11percentDiffdd: # @_Z11percentDiffdd
.cfi_startproc
# %bb.0:
cvtsd2ss %xmm0, %xmm2
movaps .LCPI2_0(%rip), %xmm3 # xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm3
maxss %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
ucomisd %xmm2, %xmm3
jbe .LBB2_2
# %bb.1:
xorps %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movaps .LCPI2_0(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm4
maxss %xmm2, %xmm4
cvtss2sd %xmm4, %xmm4
xorps %xmm2, %xmm2
ucomisd %xmm4, %xmm3
ja .LBB2_3
.LBB2_2:
movaps %xmm0, %xmm2
subsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
movaps .LCPI2_0(%rip), %xmm2 # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movaps %xmm1, %xmm3
xorps %xmm2, %xmm3
maxss %xmm1, %xmm3
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm1
xorps %xmm2, %xmm1
maxss %xmm0, %xmm1
divss %xmm1, %xmm3
xorps %xmm3, %xmm2
maxss %xmm3, %xmm2
mulss .LCPI2_3(%rip), %xmm2
.LBB2_3:
movaps %xmm2, %xmm0
retq
.Lfunc_end2:
.size _Z11percentDiffdd, .Lfunc_end2-_Z11percentDiffdd
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6conv2DPfS_
.LCPI3_0:
.long 0x3e4ccccd # float 0.200000003
.LCPI3_1:
.long 0xbe99999a # float -0.300000012
.LCPI3_2:
.long 0x3ecccccd # float 0.400000006
.LCPI3_3:
.long 0x3f000000 # float 0.5
.LCPI3_4:
.long 0x3f19999a # float 0.600000024
.LCPI3_5:
.long 0x3f333333 # float 0.699999988
.LCPI3_6:
.long 0xbf4ccccd # float -0.800000011
.LCPI3_7:
.long 0xbf666666 # float -0.899999976
.LCPI3_8:
.long 0x3dcccccd # float 0.100000001
.text
.globl _Z6conv2DPfS_
.p2align 4, 0x90
.type _Z6conv2DPfS_,@function
_Z6conv2DPfS_: # @_Z6conv2DPfS_
.cfi_startproc
# %bb.0:
addq $32776, %rdi # imm = 0x8008
addq $16388, %rsi # imm = 0x4004
movl $1, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI3_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI3_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI3_4(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI3_5(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI3_6(%rip), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss .LCPI3_7(%rip), %xmm7 # xmm7 = mem[0],zero,zero,zero
movss .LCPI3_8(%rip), %xmm8 # xmm8 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movss -32776(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm0, %xmm9
movss -16392(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm1, %xmm10
addss %xmm9, %xmm10
movss -8(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm2, %xmm9
addss %xmm10, %xmm9
movss -32772(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm3, %xmm10
addss %xmm9, %xmm10
movss -16388(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm4, %xmm9
addss %xmm10, %xmm9
movss -4(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm5, %xmm10
addss %xmm9, %xmm10
movss -32768(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm6, %xmm9
addss %xmm10, %xmm9
movss -16384(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm7, %xmm10
addss %xmm9, %xmm10
movss (%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm8, %xmm9
addss %xmm10, %xmm9
movss %xmm9, (%rsi,%rcx,4)
incq %rcx
cmpq $4094, %rcx # imm = 0xFFE
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rax
addq $16384, %rdi # imm = 0x4000
addq $16384, %rsi # imm = 0x4000
cmpq $4095, %rax # imm = 0xFFF
jne .LBB3_1
# %bb.4:
retq
.Lfunc_end3:
.size _Z6conv2DPfS_, .Lfunc_end3-_Z6conv2DPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4initPf
.LCPI4_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z4initPf
.p2align 4, 0x90
.type _Z4initPf,@function
_Z4initPf: # @_Z4initPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $4096, %r15 # imm = 0x1000
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r14
addq $16384, %rbx # imm = 0x4000
cmpq $4096, %r14 # imm = 0x1000
jne .LBB4_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z4initPf, .Lfunc_end4-_Z4initPf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14compareResultsPfS_
.LCPI5_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI5_4:
.quad 0x3fa999999999999a # double 0.050000000000000003
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_2:
.long 0x322bcc77 # float 9.99999993E-9
.LCPI5_3:
.long 0x42c80000 # float 100
.text
.globl _Z14compareResultsPfS_
.p2align 4, 0x90
.type _Z14compareResultsPfS_,@function
_Z14compareResultsPfS_: # @_Z14compareResultsPfS_
.cfi_startproc
# %bb.0:
addq $16388, %rsi # imm = 0x4004
addq $16388, %rdi # imm = 0x4004
xorl %eax, %eax
movl $1, %ecx
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI5_4(%rip), %xmm2 # xmm2 = mem[0],zero
movss .LCPI5_2(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI5_3(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_1 Depth=1
incq %rcx
addq $16384, %rsi # imm = 0x4000
addq $16384, %rdi # imm = 0x4000
cmpq $4095, %rcx # imm = 0xFFF
je .LBB5_7
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %edx, %edx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_4: # in Loop: Header=BB5_2 Depth=2
movaps %xmm5, %xmm7
subss %xmm6, %xmm7
movaps %xmm7, %xmm6
xorps %xmm0, %xmm6
maxss %xmm7, %xmm6
addss %xmm3, %xmm5
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
divss %xmm7, %xmm6
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
mulss %xmm4, %xmm7
.LBB5_5: # %_Z11percentDiffdd.exit
# in Loop: Header=BB5_2 Depth=2
xorps %xmm5, %xmm5
cvtss2sd %xmm7, %xmm5
xorl %r8d, %r8d
ucomisd %xmm2, %xmm5
seta %r8b
addl %r8d, %eax
incq %rdx
cmpq $4094, %rdx # imm = 0xFFE
je .LBB5_6
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rdx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss (%rsi,%rdx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
cvtss2sd %xmm7, %xmm7
ucomisd %xmm7, %xmm1
jbe .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=2
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
xorps %xmm8, %xmm8
cvtss2sd %xmm7, %xmm8
xorps %xmm7, %xmm7
ucomisd %xmm8, %xmm1
jbe .LBB5_4
jmp .LBB5_5
.LBB5_7:
movsd .LCPI5_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movl %eax, %esi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end5:
.size _Z14compareResultsPfS_, .Lfunc_end5-_Z14compareResultsPfS_
.cfi_endproc
# -- End function
.globl _Z13GPU_argv_initv # -- Begin function _Z13GPU_argv_initv
.p2align 4, 0x90
.type _Z13GPU_argv_initv,@function
_Z13GPU_argv_initv: # @_Z13GPU_argv_initv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z13GPU_argv_initv, .Lfunc_end6-_Z13GPU_argv_initv
.cfi_endproc
# -- End function
.globl _Z35__device_stub__Convolution2D_kernelPfS_ # -- Begin function _Z35__device_stub__Convolution2D_kernelPfS_
.p2align 4, 0x90
.type _Z35__device_stub__Convolution2D_kernelPfS_,@function
_Z35__device_stub__Convolution2D_kernelPfS_: # @_Z35__device_stub__Convolution2D_kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20Convolution2D_kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end7:
.size _Z35__device_stub__Convolution2D_kernelPfS_, .Lfunc_end7-_Z35__device_stub__Convolution2D_kernelPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17convolution2DCudaPfS_S_
.LCPI8_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z17convolution2DCudaPfS_S_
.p2align 4, 0x90
.type _Z17convolution2DCudaPfS_S_,@function
_Z17convolution2DCudaPfS_S_: # @_Z17convolution2DCudaPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %r14
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB8_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB8_2: # %_Z7rtclockv.exit
movq (%rsp), %r14
movq 8(%rsp), %r15
movabsq $2199023255680, %rdi # imm = 0x20000000080
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 8(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rsp, %r9
movl $_Z20Convolution2D_kernelPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_4:
callq hipDeviceSynchronize
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB8_6
# %bb.5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB8_6: # %_Z7rtclockv.exit11
cvtsi2sd %r15, %xmm0
movsd .LCPI8_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsi2sd %r14, %xmm2
addsd %xmm0, %xmm2
cvtsi2sdq (%rsp), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd %xmm1, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movq stdout(%rip), %rdi
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movq 16(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z17convolution2DCudaPfS_S_, .Lfunc_end8-_Z17convolution2DCudaPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI9_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI9_2:
.long 0x3e4ccccd # float 0.200000003
.LCPI9_3:
.long 0xbe99999a # float -0.300000012
.LCPI9_4:
.long 0x3ecccccd # float 0.400000006
.LCPI9_5:
.long 0x3f000000 # float 0.5
.LCPI9_6:
.long 0x3f19999a # float 0.600000024
.LCPI9_7:
.long 0x3f333333 # float 0.699999988
.LCPI9_8:
.long 0xbf4ccccd # float -0.800000011
.LCPI9_9:
.long 0xbf666666 # float -0.899999976
.LCPI9_10:
.long 0x3dcccccd # float 0.100000001
.LCPI9_13:
.long 0x322bcc77 # float 9.99999993E-9
.LCPI9_14:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI9_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI9_12:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI9_15:
.quad 0x3fa999999999999a # double 0.050000000000000003
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI9_11:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB9_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB9_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB9_2: # Parent Loop BB9_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI9_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $4096, %rbp # imm = 0x1000
jne .LBB9_2
# %bb.3: # in Loop: Header=BB9_1 Depth=1
incq %r12
addq $16384, %r13 # imm = 0x4000
cmpq $4096, %r12 # imm = 0x1000
jne .LBB9_1
# %bb.4: # %_Z4initPf.exit
leaq 24(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
xorl %esi, %esi
movq %r12, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movq %rbx, %rdi
movq %r15, %rdx
callq _Z17convolution2DCudaPfS_S_
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB9_6
# %bb.5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB9_6: # %_Z7rtclockv.exit
cvtsi2sdq 32(%rsp), %xmm11
movq 24(%rsp), %rax
mulsd .LCPI9_1(%rip), %xmm11
movq %rbx, %rcx
addq $32776, %rcx # imm = 0x8008
leaq 16388(%r14), %rdx
movl $1, %esi
movss .LCPI9_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI9_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI9_4(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI9_5(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI9_6(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI9_7(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI9_8(%rip), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss .LCPI9_9(%rip), %xmm7 # xmm7 = mem[0],zero,zero,zero
movss .LCPI9_10(%rip), %xmm8 # xmm8 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB9_7: # %.preheader.i13
# =>This Loop Header: Depth=1
# Child Loop BB9_8 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB9_8: # Parent Loop BB9_7 Depth=1
# => This Inner Loop Header: Depth=2
movss -32776(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm0, %xmm9
movss -16392(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm1, %xmm10
addss %xmm9, %xmm10
movss -8(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm2, %xmm9
addss %xmm10, %xmm9
movss -32772(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm3, %xmm10
addss %xmm9, %xmm10
movss -16388(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm4, %xmm9
addss %xmm10, %xmm9
movss -4(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm5, %xmm10
addss %xmm9, %xmm10
movss -32768(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm6, %xmm9
addss %xmm10, %xmm9
movss -16384(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm7, %xmm10
addss %xmm9, %xmm10
movss (%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm8, %xmm9
addss %xmm10, %xmm9
movss %xmm9, (%rdx,%rdi,4)
incq %rdi
cmpq $4094, %rdi # imm = 0xFFE
jne .LBB9_8
# %bb.9: # in Loop: Header=BB9_7 Depth=1
incq %rsi
addq $16384, %rcx # imm = 0x4000
addq $16384, %rdx # imm = 0x4000
cmpq $4095, %rsi # imm = 0xFFF
jne .LBB9_7
# %bb.10: # %_Z6conv2DPfS_.exit
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm0, %xmm11
movsd %xmm11, 8(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB9_12
# %bb.11:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB9_12: # %_Z7rtclockv.exit18
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
mulsd .LCPI9_1(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movq %r15, %rax
addq $16388, %rax # imm = 0x4004
movq %r14, %rcx
addq $16388, %rcx # imm = 0x4004
xorl %esi, %esi
movl $1, %edx
movaps .LCPI9_11(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movsd .LCPI9_12(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI9_15(%rip), %xmm2 # xmm2 = mem[0],zero
movss .LCPI9_13(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI9_14(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB9_13
.p2align 4, 0x90
.LBB9_18: # in Loop: Header=BB9_13 Depth=1
incq %rdx
addq $16384, %rax # imm = 0x4000
addq $16384, %rcx # imm = 0x4000
cmpq $4095, %rdx # imm = 0xFFF
je .LBB9_19
.LBB9_13: # %.preheader.i19
# =>This Loop Header: Depth=1
# Child Loop BB9_14 Depth 2
xorl %edi, %edi
jmp .LBB9_14
.p2align 4, 0x90
.LBB9_16: # in Loop: Header=BB9_14 Depth=2
movaps %xmm5, %xmm7
subss %xmm6, %xmm7
movaps %xmm7, %xmm6
xorps %xmm0, %xmm6
maxss %xmm7, %xmm6
addss %xmm3, %xmm5
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
divss %xmm7, %xmm6
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
mulss %xmm4, %xmm7
.LBB9_17: # %_Z11percentDiffdd.exit.i
# in Loop: Header=BB9_14 Depth=2
xorps %xmm5, %xmm5
cvtss2sd %xmm7, %xmm5
xorl %r8d, %r8d
ucomisd %xmm2, %xmm5
seta %r8b
addl %r8d, %esi
incq %rdi
cmpq $4094, %rdi # imm = 0xFFE
je .LBB9_18
.LBB9_14: # Parent Loop BB9_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss (%rax,%rdi,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
cvtss2sd %xmm7, %xmm7
ucomisd %xmm7, %xmm1
jbe .LBB9_16
# %bb.15: # in Loop: Header=BB9_14 Depth=2
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
xorps %xmm8, %xmm8
cvtss2sd %xmm7, %xmm8
xorps %xmm7, %xmm7
ucomisd %xmm8, %xmm1
jbe .LBB9_16
jmp .LBB9_17
.LBB9_19: # %_Z14compareResultsPfS_.exit
movsd .LCPI9_15(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Convolution2D_kernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.size .L.str.1, 74
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "setting device %d with name %s\n"
.size .L.str.2, 32
.type _Z20Convolution2D_kernelPfS_,@object # @_Z20Convolution2D_kernelPfS_
.section .rodata,"a",@progbits
.globl _Z20Convolution2D_kernelPfS_
.p2align 3, 0x0
_Z20Convolution2D_kernelPfS_:
.quad _Z35__device_stub__Convolution2D_kernelPfS_
.size _Z20Convolution2D_kernelPfS_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "GPU Runtime: %0.6lfs\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU Runtime: %0.6lfs\n"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20Convolution2D_kernelPfS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__Convolution2D_kernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20Convolution2D_kernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20Convolution2D_kernelPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ IADD3 R2, R3, -0x1, RZ ; /* 0xffffffff03027810 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fc600078e0205 */
/*0080*/ ISETP.GT.U32.AND P0, PT, R2, 0xffd, PT ; /* 0x00000ffd0200780c */
/* 0x000fe40003f04070 */
/*0090*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.GT.U32.OR P0, PT, R4, 0xffd, P0 ; /* 0x00000ffd0400780c */
/* 0x000fda0000704470 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*00d0*/ LEA R0, R3, R0, 0xc ; /* 0x0000000003007211 */
/* 0x000fe200078e60ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00f0*/ IADD3 R2, R0, -0x1001, RZ ; /* 0xffffefff00027810 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE R2, R2, R21, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0215 */
/*0110*/ LDG.E R7, [R2.64+0x4] ; /* 0x0000040402077981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ee2000c1e1900 */
/*0130*/ IMAD.WIDE R4, R0, R21, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc600078e0215 */
/*0140*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R11, [R2.64+0x4000] ; /* 0x00400004020b7981 */
/* 0x000f68000c1e1900 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000f68000c1e1900 */
/*0170*/ LDG.E R13, [R2.64+0x4008] ; /* 0x00400804020d7981 */
/* 0x000f68000c1e1900 */
/*0180*/ LDG.E R15, [R2.64+0x8000] ; /* 0x00800004020f7981 */
/* 0x000f68000c1e1900 */
/*0190*/ LDG.E R17, [R2.64+0x8004] ; /* 0x0080040402117981 */
/* 0x000f68000c1e1900 */
/*01a0*/ LDG.E R19, [R2.64+0x8008] ; /* 0x0080080402137981 */
/* 0x000f62000c1e1900 */
/*01b0*/ FMUL R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x004fc80000400000 */
/*01c0*/ FFMA R6, R6, 0.20000000298023223877, R7 ; /* 0x3e4ccccd06067823 */
/* 0x008fc80000000007 */
/*01d0*/ FFMA R6, R9, -0.80000001192092895508, R6 ; /* 0xbf4ccccd09067823 */
/* 0x010fc80000000006 */
/*01e0*/ FFMA R6, R11, -0.30000001192092895508, R6 ; /* 0xbe99999a0b067823 */
/* 0x020fc80000000006 */
/*01f0*/ FFMA R6, R5, 0.60000002384185791016, R6 ; /* 0x3f19999a05067823 */
/* 0x000fe40000000006 */
/*0200*/ IMAD.WIDE R4, R0, R21, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0215 */
/*0210*/ FFMA R6, R13, -0.89999997615814208984, R6 ; /* 0xbf6666660d067823 */
/* 0x000fc80000000006 */
/*0220*/ FFMA R6, R15, 0.40000000596046447754, R6 ; /* 0x3ecccccd0f067823 */
/* 0x000fc80000000006 */
/*0230*/ FFMA R6, R17, 0.69999998807907104492, R6 ; /* 0x3f33333311067823 */
/* 0x000fc80000000006 */
/*0240*/ FFMA R19, R19, 0.10000000149011611938, R6 ; /* 0x3dcccccd13137823 */
/* 0x000fca0000000006 */
/*0250*/ STG.E [R4.64], R19 ; /* 0x0000001304007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20Convolution2D_kernelPfS_
.globl _Z20Convolution2D_kernelPfS_
.p2align 8
.type _Z20Convolution2D_kernelPfS_,@function
_Z20Convolution2D_kernelPfS_:
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v3, -1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, -1, v0
v_max_u32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0xffe, v3
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v14, 12, v2
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v15, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, 0xfffff000, v14
v_add_nc_u32_e32 v16, 0x1000, v14
v_add_nc_u32_e32 v2, v8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add_nc_u32_e32 v2, v8, v0
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, v8, v15
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, v14, v1
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_add_nc_u32_e32 v2, v14, v0
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_lshlrev_b64 v[12:13], 2, v[2:3]
v_add_nc_u32_e32 v2, v14, v15
s_clause 0x2
global_load_b32 v14, v[4:5], off
global_load_b32 v17, v[6:7], off
global_load_b32 v18, v[8:9], off
v_add_co_u32 v4, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v11, vcc_lo
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, v16, v1
v_add_co_u32 v8, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[2:3]
v_add_nc_u32_e32 v2, v16, v0
v_add_co_u32 v0, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v7, vcc_lo
s_clause 0x2
global_load_b32 v19, v[4:5], off
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[0:1], off
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s0, v10
v_add_nc_u32_e32 v2, v16, v15
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_clause 0x1
global_load_b32 v6, v[0:1], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(7)
v_mul_f32_e32 v1, 0.5, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v14, 0x3e4ccccd, v1
s_waitcnt vmcnt(6)
v_fmamk_f32 v1, v18, 0xbf4ccccd, v1
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v19, 0xbe99999a, v1
s_waitcnt vmcnt(4)
v_fmamk_f32 v1, v8, 0x3f19999a, v1
s_waitcnt vmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v9, 0xbf666666, v1
s_waitcnt vmcnt(2)
v_fmamk_f32 v1, v6, 0x3ecccccd, v1
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v4, 0x3f333333, v1
s_waitcnt vmcnt(0)
v_fmamk_f32 v2, v0, 0x3dcccccd, v1
v_add_co_u32 v0, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v13, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20Convolution2D_kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20Convolution2D_kernelPfS_, .Lfunc_end0-_Z20Convolution2D_kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20Convolution2D_kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20Convolution2D_kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016357c_00000000-6_2DConvolution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2070:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z6absValf
.type _Z6absValf, @function
_Z6absValf:
.LFB2071:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L13
.L10:
ret
.L13:
xorps .LC3(%rip), %xmm0
ret
.cfi_endproc
.LFE2071:
.size _Z6absValf, .-_Z6absValf
.globl _Z11percentDiffdd
.type _Z11percentDiffdd, @function
_Z11percentDiffdd:
.LFB2072:
.cfi_startproc
endbr64
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L35
.L15:
cvtss2sd %xmm2, %xmm2
movsd .LC4(%rip), %xmm3
comisd %xmm2, %xmm3
jbe .L17
pxor %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L36
.L19:
pxor %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
pxor %xmm2, %xmm2
movsd .LC4(%rip), %xmm4
comisd %xmm3, %xmm4
ja .L14
.L17:
movapd %xmm0, %xmm2
subsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
pxor %xmm1, %xmm1
comiss %xmm2, %xmm1
ja .L37
.L22:
addsd .LC5(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
pxor %xmm0, %xmm0
comiss %xmm1, %xmm0
ja .L38
.L24:
movaps %xmm2, %xmm0
divss %xmm1, %xmm0
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L39
.L26:
movaps %xmm0, %xmm2
mulss .LC6(%rip), %xmm2
.L14:
movaps %xmm2, %xmm0
ret
.L35:
xorps .LC3(%rip), %xmm2
jmp .L15
.L36:
xorps .LC3(%rip), %xmm2
jmp .L19
.L37:
xorps .LC3(%rip), %xmm2
jmp .L22
.L38:
xorps .LC3(%rip), %xmm1
jmp .L24
.L39:
xorps .LC3(%rip), %xmm0
jmp .L26
.cfi_endproc
.LFE2072:
.size _Z11percentDiffdd, .-_Z11percentDiffdd
.globl _Z6conv2DPfS_
.type _Z6conv2DPfS_, @function
_Z6conv2DPfS_:
.LFB2073:
.cfi_startproc
endbr64
addq $16388, %rsi
leaq 16376(%rdi), %rcx
movl $0, %edi
movss .LC7(%rip), %xmm9
movss .LC8(%rip), %xmm8
movss .LC9(%rip), %xmm7
movss .LC10(%rip), %xmm6
movss .LC11(%rip), %xmm5
movss .LC12(%rip), %xmm4
movss .LC13(%rip), %xmm3
movss .LC14(%rip), %xmm2
movss .LC15(%rip), %xmm1
.L41:
addl $4096, %edi
leaq -16376(%rcx), %rax
movq %rsi, %rdx
.L42:
movaps %xmm9, %xmm0
mulss (%rax), %xmm0
movaps %xmm8, %xmm10
mulss 16384(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm7, %xmm10
mulss 32768(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm6, %xmm10
mulss 4(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm5, %xmm10
mulss 16388(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm4, %xmm10
mulss 32772(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm3, %xmm10
mulss 8(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm2, %xmm10
mulss 16392(%rax), %xmm10
addss %xmm10, %xmm0
movaps %xmm1, %xmm10
mulss 32776(%rax), %xmm10
addss %xmm10, %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
addq $4, %rdx
cmpq %rcx, %rax
jne .L42
addq $16384, %rsi
addq $16384, %rcx
cmpl $16769024, %edi
jne .L41
ret
.cfi_endproc
.LFE2073:
.size _Z6conv2DPfS_, .-_Z6conv2DPfS_
.globl _Z4initPf
.type _Z4initPf, @function
_Z4initPf:
.LFB2074:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
leaq 16384(%rdi), %rbp
addq $67125248, %r12
.L46:
leaq -16384(%rbp), %rbx
.L47:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC16(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L47
addq $16384, %rbp
cmpq %r12, %rbp
jne .L46
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _Z4initPf, .-_Z4initPf
.section .rodata.str1.8
.align 8
.LC18:
.string "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.text
.globl _Z14compareResultsPfS_
.type _Z14compareResultsPfS_, @function
_Z14compareResultsPfS_:
.LFB2075:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r14
leaq 16384(%rsi), %r12
leaq 16384(%rdi), %r13
addq $67092480, %r14
movl $0, %ebp
.L52:
movl $1, %ebx
.L55:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx,4), %xmm1
call _Z11percentDiffdd
cvtss2sd %xmm0, %xmm0
comisd .LC17(%rip), %xmm0
seta %al
movzbl %al, %eax
addl %eax, %ebp
addq $1, %rbx
cmpq $4095, %rbx
jne .L55
addq $16384, %r12
addq $16384, %r13
cmpq %r14, %r12
jne .L52
movl %ebp, %edx
movsd .LC17(%rip), %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z14compareResultsPfS_, .-_Z14compareResultsPfS_
.section .rodata.str1.8
.align 8
.LC19:
.string "setting device %d with name %s\n"
.text
.globl _Z13GPU_argv_initv
.type _Z13GPU_argv_initv, @function
_Z13GPU_argv_initv:
.LFB2076:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2076:
.size _Z13GPU_argv_initv, .-_Z13GPU_argv_initv
.globl _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
.type _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_, @function
_Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_:
.LFB2103:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20Convolution2D_kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_, .-_Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
.globl _Z20Convolution2D_kernelPfS_
.type _Z20Convolution2D_kernelPfS_, @function
_Z20Convolution2D_kernelPfS_:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z20Convolution2D_kernelPfS_, .-_Z20Convolution2D_kernelPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC20:
.string "GPU Runtime: %0.6lfs\n"
.text
.globl _Z17convolution2DCudaPfS_S_
.type _Z17convolution2DCudaPfS_S_, @function
_Z17convolution2DCudaPfS_S_:
.LFB2077:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 40(%rsp)
movl $128, 44(%rsp)
movl $512, 48(%rsp)
movl $1, 52(%rsp)
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl $32, 32(%rsp)
movl $8, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L76
.L73:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC20(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $2, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L77
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L76:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z42__device_stub__Z20Convolution2D_kernelPfS_PfS_
jmp .L73
.L77:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z17convolution2DCudaPfS_S_, .-_Z17convolution2DCudaPfS_S_
.section .rodata.str1.1
.LC21:
.string "CPU Runtime: %0.6lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2078:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z4initPf
call _Z13GPU_argv_initv
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z17convolution2DCudaPfS_S_
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6conv2DPfS_
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _Z14compareResultsPfS_
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z20Convolution2D_kernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z20Convolution2D_kernelPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long 1202590843
.long 1065646817
.align 8
.LC5:
.long -536870912
.long 1044740494
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1120403456
.align 4
.LC7:
.long 1045220557
.align 4
.LC8:
.long -1097229926
.align 4
.LC9:
.long 1053609165
.align 4
.LC10:
.long 1056964608
.align 4
.LC11:
.long 1058642330
.align 4
.LC12:
.long 1060320051
.align 4
.LC13:
.long -1085485875
.align 4
.LC14:
.long -1083808154
.align 4
.LC15:
.long 1036831949
.align 4
.LC16:
.long 805306368
.section .rodata.cst8
.align 8
.LC17:
.long -1717986918
.long 1068079513
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2DConvolution.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB0_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z7rtclockv, .Lfunc_end0-_Z7rtclockv
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6absValf
.LCPI1_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl _Z6absValf
.p2align 4, 0x90
.type _Z6absValf,@function
_Z6absValf: # @_Z6absValf
.cfi_startproc
# %bb.0:
movaps .LCPI1_0(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm0, %xmm1
maxss %xmm0, %xmm1
movaps %xmm1, %xmm0
retq
.Lfunc_end1:
.size _Z6absValf, .Lfunc_end1-_Z6absValf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z11percentDiffdd
.LCPI2_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI2_2:
.quad 0x3e45798ee0000000 # double 9.9999999392252903E-9
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_3:
.long 0x42c80000 # float 100
.text
.globl _Z11percentDiffdd
.p2align 4, 0x90
.type _Z11percentDiffdd,@function
_Z11percentDiffdd: # @_Z11percentDiffdd
.cfi_startproc
# %bb.0:
cvtsd2ss %xmm0, %xmm2
movaps .LCPI2_0(%rip), %xmm3 # xmm3 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm3
maxss %xmm2, %xmm3
xorps %xmm2, %xmm2
cvtss2sd %xmm3, %xmm2
movsd .LCPI2_1(%rip), %xmm3 # xmm3 = mem[0],zero
ucomisd %xmm2, %xmm3
jbe .LBB2_2
# %bb.1:
xorps %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
movaps .LCPI2_0(%rip), %xmm4 # xmm4 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
xorps %xmm2, %xmm4
maxss %xmm2, %xmm4
cvtss2sd %xmm4, %xmm4
xorps %xmm2, %xmm2
ucomisd %xmm4, %xmm3
ja .LBB2_3
.LBB2_2:
movaps %xmm0, %xmm2
subsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsd2ss %xmm2, %xmm1
movaps .LCPI2_0(%rip), %xmm2 # xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movaps %xmm1, %xmm3
xorps %xmm2, %xmm3
maxss %xmm1, %xmm3
addsd .LCPI2_2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm1
xorps %xmm2, %xmm1
maxss %xmm0, %xmm1
divss %xmm1, %xmm3
xorps %xmm3, %xmm2
maxss %xmm3, %xmm2
mulss .LCPI2_3(%rip), %xmm2
.LBB2_3:
movaps %xmm2, %xmm0
retq
.Lfunc_end2:
.size _Z11percentDiffdd, .Lfunc_end2-_Z11percentDiffdd
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6conv2DPfS_
.LCPI3_0:
.long 0x3e4ccccd # float 0.200000003
.LCPI3_1:
.long 0xbe99999a # float -0.300000012
.LCPI3_2:
.long 0x3ecccccd # float 0.400000006
.LCPI3_3:
.long 0x3f000000 # float 0.5
.LCPI3_4:
.long 0x3f19999a # float 0.600000024
.LCPI3_5:
.long 0x3f333333 # float 0.699999988
.LCPI3_6:
.long 0xbf4ccccd # float -0.800000011
.LCPI3_7:
.long 0xbf666666 # float -0.899999976
.LCPI3_8:
.long 0x3dcccccd # float 0.100000001
.text
.globl _Z6conv2DPfS_
.p2align 4, 0x90
.type _Z6conv2DPfS_,@function
_Z6conv2DPfS_: # @_Z6conv2DPfS_
.cfi_startproc
# %bb.0:
addq $32776, %rdi # imm = 0x8008
addq $16388, %rsi # imm = 0x4004
movl $1, %eax
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI3_2(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI3_3(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI3_4(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI3_5(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI3_6(%rip), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss .LCPI3_7(%rip), %xmm7 # xmm7 = mem[0],zero,zero,zero
movss .LCPI3_8(%rip), %xmm8 # xmm8 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB3_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
movss -32776(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm0, %xmm9
movss -16392(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm1, %xmm10
addss %xmm9, %xmm10
movss -8(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm2, %xmm9
addss %xmm10, %xmm9
movss -32772(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm3, %xmm10
addss %xmm9, %xmm10
movss -16388(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm4, %xmm9
addss %xmm10, %xmm9
movss -4(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm5, %xmm10
addss %xmm9, %xmm10
movss -32768(%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm6, %xmm9
addss %xmm10, %xmm9
movss -16384(%rdi,%rcx,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm7, %xmm10
addss %xmm9, %xmm10
movss (%rdi,%rcx,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm8, %xmm9
addss %xmm10, %xmm9
movss %xmm9, (%rsi,%rcx,4)
incq %rcx
cmpq $4094, %rcx # imm = 0xFFE
jne .LBB3_2
# %bb.3: # in Loop: Header=BB3_1 Depth=1
incq %rax
addq $16384, %rdi # imm = 0x4000
addq $16384, %rsi # imm = 0x4000
cmpq $4095, %rax # imm = 0xFFF
jne .LBB3_1
# %bb.4:
retq
.Lfunc_end3:
.size _Z6conv2DPfS_, .Lfunc_end3-_Z6conv2DPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4initPf
.LCPI4_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z4initPf
.p2align 4, 0x90
.type _Z4initPf,@function
_Z4initPf: # @_Z4initPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $4096, %r15 # imm = 0x1000
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r14
addq $16384, %rbx # imm = 0x4000
cmpq $4096, %r14 # imm = 0x1000
jne .LBB4_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z4initPf, .Lfunc_end4-_Z4initPf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14compareResultsPfS_
.LCPI5_0:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI5_4:
.quad 0x3fa999999999999a # double 0.050000000000000003
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI5_2:
.long 0x322bcc77 # float 9.99999993E-9
.LCPI5_3:
.long 0x42c80000 # float 100
.text
.globl _Z14compareResultsPfS_
.p2align 4, 0x90
.type _Z14compareResultsPfS_,@function
_Z14compareResultsPfS_: # @_Z14compareResultsPfS_
.cfi_startproc
# %bb.0:
addq $16388, %rsi # imm = 0x4004
addq $16388, %rdi # imm = 0x4004
xorl %eax, %eax
movl $1, %ecx
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI5_4(%rip), %xmm2 # xmm2 = mem[0],zero
movss .LCPI5_2(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI5_3(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_6: # in Loop: Header=BB5_1 Depth=1
incq %rcx
addq $16384, %rsi # imm = 0x4000
addq $16384, %rdi # imm = 0x4000
cmpq $4095, %rcx # imm = 0xFFF
je .LBB5_7
.LBB5_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_2 Depth 2
xorl %edx, %edx
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_4: # in Loop: Header=BB5_2 Depth=2
movaps %xmm5, %xmm7
subss %xmm6, %xmm7
movaps %xmm7, %xmm6
xorps %xmm0, %xmm6
maxss %xmm7, %xmm6
addss %xmm3, %xmm5
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
divss %xmm7, %xmm6
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
mulss %xmm4, %xmm7
.LBB5_5: # %_Z11percentDiffdd.exit
# in Loop: Header=BB5_2 Depth=2
xorps %xmm5, %xmm5
cvtss2sd %xmm7, %xmm5
xorl %r8d, %r8d
ucomisd %xmm2, %xmm5
seta %r8b
addl %r8d, %eax
incq %rdx
cmpq $4094, %rdx # imm = 0xFFE
je .LBB5_6
.LBB5_2: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rdx,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss (%rsi,%rdx,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
cvtss2sd %xmm7, %xmm7
ucomisd %xmm7, %xmm1
jbe .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=2
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
xorps %xmm8, %xmm8
cvtss2sd %xmm7, %xmm8
xorps %xmm7, %xmm7
ucomisd %xmm8, %xmm1
jbe .LBB5_4
jmp .LBB5_5
.LBB5_7:
movsd .LCPI5_4(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movl %eax, %esi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end5:
.size _Z14compareResultsPfS_, .Lfunc_end5-_Z14compareResultsPfS_
.cfi_endproc
# -- End function
.globl _Z13GPU_argv_initv # -- Begin function _Z13GPU_argv_initv
.p2align 4, 0x90
.type _Z13GPU_argv_initv,@function
_Z13GPU_argv_initv: # @_Z13GPU_argv_initv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 1488
.cfi_offset %rbx, -16
movq %rsp, %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
xorl %esi, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
addq $1472, %rsp # imm = 0x5C0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z13GPU_argv_initv, .Lfunc_end6-_Z13GPU_argv_initv
.cfi_endproc
# -- End function
.globl _Z35__device_stub__Convolution2D_kernelPfS_ # -- Begin function _Z35__device_stub__Convolution2D_kernelPfS_
.p2align 4, 0x90
.type _Z35__device_stub__Convolution2D_kernelPfS_,@function
_Z35__device_stub__Convolution2D_kernelPfS_: # @_Z35__device_stub__Convolution2D_kernelPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20Convolution2D_kernelPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end7:
.size _Z35__device_stub__Convolution2D_kernelPfS_, .Lfunc_end7-_Z35__device_stub__Convolution2D_kernelPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z17convolution2DCudaPfS_S_
.LCPI8_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z17convolution2DCudaPfS_S_
.p2align 4, 0x90
.type _Z17convolution2DCudaPfS_S_,@function
_Z17convolution2DCudaPfS_S_: # @_Z17convolution2DCudaPfS_S_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rdi, %r14
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB8_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB8_2: # %_Z7rtclockv.exit
movq (%rsp), %r14
movq 8(%rsp), %r15
movabsq $2199023255680, %rdi # imm = 0x20000000080
movabsq $34359738400, %rdx # imm = 0x800000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rax
movq %rax, 8(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movq %rsp, %r9
movl $_Z20Convolution2D_kernelPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_4:
callq hipDeviceSynchronize
movq %rsp, %rdi
leaq 32(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB8_6
# %bb.5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB8_6: # %_Z7rtclockv.exit11
cvtsi2sd %r15, %xmm0
movsd .LCPI8_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
cvtsi2sd %r14, %xmm2
addsd %xmm0, %xmm2
cvtsi2sdq (%rsp), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd %xmm1, %xmm0
addsd %xmm3, %xmm0
subsd %xmm2, %xmm0
movq stdout(%rip), %rdi
movl $.L.str.3, %esi
movb $1, %al
callq fprintf
movq 16(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z17convolution2DCudaPfS_S_, .Lfunc_end8-_Z17convolution2DCudaPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI9_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI9_2:
.long 0x3e4ccccd # float 0.200000003
.LCPI9_3:
.long 0xbe99999a # float -0.300000012
.LCPI9_4:
.long 0x3ecccccd # float 0.400000006
.LCPI9_5:
.long 0x3f000000 # float 0.5
.LCPI9_6:
.long 0x3f19999a # float 0.600000024
.LCPI9_7:
.long 0x3f333333 # float 0.699999988
.LCPI9_8:
.long 0xbf4ccccd # float -0.800000011
.LCPI9_9:
.long 0xbf666666 # float -0.899999976
.LCPI9_10:
.long 0x3dcccccd # float 0.100000001
.LCPI9_13:
.long 0x322bcc77 # float 9.99999993E-9
.LCPI9_14:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI9_1:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI9_12:
.quad 0x3f847ae147ae147b # double 0.01
.LCPI9_15:
.quad 0x3fa999999999999a # double 0.050000000000000003
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI9_11:
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.long 0x80000000 # float -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 1552
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB9_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB9_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB9_2: # Parent Loop BB9_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI9_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r13,%rbp,4)
incq %rbp
cmpq $4096, %rbp # imm = 0x1000
jne .LBB9_2
# %bb.3: # in Loop: Header=BB9_1 Depth=1
incq %r12
addq $16384, %r13 # imm = 0x4000
cmpq $4096, %r12 # imm = 0x1000
jne .LBB9_1
# %bb.4: # %_Z4initPf.exit
leaq 24(%rsp), %r12
movq %r12, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.2, %edi
xorl %esi, %esi
movq %r12, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movq %rbx, %rdi
movq %r15, %rdx
callq _Z17convolution2DCudaPfS_S_
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB9_6
# %bb.5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB9_6: # %_Z7rtclockv.exit
cvtsi2sdq 32(%rsp), %xmm11
movq 24(%rsp), %rax
mulsd .LCPI9_1(%rip), %xmm11
movq %rbx, %rcx
addq $32776, %rcx # imm = 0x8008
leaq 16388(%r14), %rdx
movl $1, %esi
movss .LCPI9_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI9_3(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI9_4(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss .LCPI9_5(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI9_6(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
movss .LCPI9_7(%rip), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss .LCPI9_8(%rip), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss .LCPI9_9(%rip), %xmm7 # xmm7 = mem[0],zero,zero,zero
movss .LCPI9_10(%rip), %xmm8 # xmm8 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB9_7: # %.preheader.i13
# =>This Loop Header: Depth=1
# Child Loop BB9_8 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB9_8: # Parent Loop BB9_7 Depth=1
# => This Inner Loop Header: Depth=2
movss -32776(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm0, %xmm9
movss -16392(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm1, %xmm10
addss %xmm9, %xmm10
movss -8(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm2, %xmm9
addss %xmm10, %xmm9
movss -32772(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm3, %xmm10
addss %xmm9, %xmm10
movss -16388(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm4, %xmm9
addss %xmm10, %xmm9
movss -4(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm5, %xmm10
addss %xmm9, %xmm10
movss -32768(%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm6, %xmm9
addss %xmm10, %xmm9
movss -16384(%rcx,%rdi,4), %xmm10 # xmm10 = mem[0],zero,zero,zero
mulss %xmm7, %xmm10
addss %xmm9, %xmm10
movss (%rcx,%rdi,4), %xmm9 # xmm9 = mem[0],zero,zero,zero
mulss %xmm8, %xmm9
addss %xmm10, %xmm9
movss %xmm9, (%rdx,%rdi,4)
incq %rdi
cmpq $4094, %rdi # imm = 0xFFE
jne .LBB9_8
# %bb.9: # in Loop: Header=BB9_7 Depth=1
incq %rsi
addq $16384, %rcx # imm = 0x4000
addq $16384, %rdx # imm = 0x4000
cmpq $4095, %rsi # imm = 0xFFF
jne .LBB9_7
# %bb.10: # %_Z6conv2DPfS_.exit
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
addsd %xmm0, %xmm11
movsd %xmm11, 8(%rsp) # 8-byte Spill
leaq 24(%rsp), %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB9_12
# %bb.11:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB9_12: # %_Z7rtclockv.exit18
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
mulsd .LCPI9_1(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movq %r15, %rax
addq $16388, %rax # imm = 0x4004
movq %r14, %rcx
addq $16388, %rcx # imm = 0x4004
xorl %esi, %esi
movl $1, %edx
movaps .LCPI9_11(%rip), %xmm0 # xmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
movsd .LCPI9_12(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI9_15(%rip), %xmm2 # xmm2 = mem[0],zero
movss .LCPI9_13(%rip), %xmm3 # xmm3 = mem[0],zero,zero,zero
movss .LCPI9_14(%rip), %xmm4 # xmm4 = mem[0],zero,zero,zero
jmp .LBB9_13
.p2align 4, 0x90
.LBB9_18: # in Loop: Header=BB9_13 Depth=1
incq %rdx
addq $16384, %rax # imm = 0x4000
addq $16384, %rcx # imm = 0x4000
cmpq $4095, %rdx # imm = 0xFFF
je .LBB9_19
.LBB9_13: # %.preheader.i19
# =>This Loop Header: Depth=1
# Child Loop BB9_14 Depth 2
xorl %edi, %edi
jmp .LBB9_14
.p2align 4, 0x90
.LBB9_16: # in Loop: Header=BB9_14 Depth=2
movaps %xmm5, %xmm7
subss %xmm6, %xmm7
movaps %xmm7, %xmm6
xorps %xmm0, %xmm6
maxss %xmm7, %xmm6
addss %xmm3, %xmm5
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
divss %xmm7, %xmm6
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
mulss %xmm4, %xmm7
.LBB9_17: # %_Z11percentDiffdd.exit.i
# in Loop: Header=BB9_14 Depth=2
xorps %xmm5, %xmm5
cvtss2sd %xmm7, %xmm5
xorl %r8d, %r8d
ucomisd %xmm2, %xmm5
seta %r8b
addl %r8d, %esi
incq %rdi
cmpq $4094, %rdi # imm = 0xFFE
je .LBB9_18
.LBB9_14: # Parent Loop BB9_13 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdi,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
movss (%rax,%rdi,4), %xmm6 # xmm6 = mem[0],zero,zero,zero
movaps %xmm5, %xmm7
xorps %xmm0, %xmm7
maxss %xmm5, %xmm7
cvtss2sd %xmm7, %xmm7
ucomisd %xmm7, %xmm1
jbe .LBB9_16
# %bb.15: # in Loop: Header=BB9_14 Depth=2
movaps %xmm6, %xmm7
xorps %xmm0, %xmm7
maxss %xmm6, %xmm7
xorps %xmm8, %xmm8
cvtss2sd %xmm7, %xmm8
xorps %xmm7, %xmm7
ucomisd %xmm8, %xmm1
jbe .LBB9_16
jmp .LBB9_17
.LBB9_19: # %_Z14compareResultsPfS_.exit
movsd .LCPI9_15(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1496, %rsp # imm = 0x5D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20Convolution2D_kernelPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.size .L.str.1, 74
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "setting device %d with name %s\n"
.size .L.str.2, 32
.type _Z20Convolution2D_kernelPfS_,@object # @_Z20Convolution2D_kernelPfS_
.section .rodata,"a",@progbits
.globl _Z20Convolution2D_kernelPfS_
.p2align 3, 0x0
_Z20Convolution2D_kernelPfS_:
.quad _Z35__device_stub__Convolution2D_kernelPfS_
.size _Z20Convolution2D_kernelPfS_, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "GPU Runtime: %0.6lfs\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU Runtime: %0.6lfs\n"
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20Convolution2D_kernelPfS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__Convolution2D_kernelPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20Convolution2D_kernelPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math_constants.h>
#define RADIUS_IN_KM 6372.8
extern "C"
// Computes the haversine distance betwwen two points on Earth
__global__ void haversine(int *size, double *in, double *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size ) {
const int lat1ix = 4*ix,lon1ix = (4*ix)+1,lat2ix = (4*ix)+2, lon2ix = (4*ix)+3;
const double dLat = (in[lat2ix] - in[lat1ix] ) * (CUDART_PI_F /180.0);
const double dLon = (in[lon2ix] - in[lon1ix] ) * (CUDART_PI_F /180.0);
const double a = pow(sin(dLat/2.0),2.0) + pow(sin(dLon/2.0),2.0) * cos(in[lat1ix] * (CUDART_PI_F/180.0)) * cos(in[lat2ix] * (CUDART_PI_F/180.0));
const double c = 2.0 * asin(sqrt(a));
out[ix] = RADIUS_IN_KM * c;
}
} | .file "tmpxft_000ee574_00000000-6_MatchEmergencyCalls.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_
.type _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_, @function
_Z33__device_stub__Z9haversinePiPdS0_PiPdS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq haversine(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_, .-_Z33__device_stub__Z9haversinePiPdS0_PiPdS0_
.globl haversine
.type haversine, @function
haversine:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size haversine, .-haversine
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "haversine"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq haversine(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math_constants.h>
#define RADIUS_IN_KM 6372.8
extern "C"
// Computes the haversine distance betwwen two points on Earth
__global__ void haversine(int *size, double *in, double *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size ) {
const int lat1ix = 4*ix,lon1ix = (4*ix)+1,lat2ix = (4*ix)+2, lon2ix = (4*ix)+3;
const double dLat = (in[lat2ix] - in[lat1ix] ) * (CUDART_PI_F /180.0);
const double dLon = (in[lon2ix] - in[lon1ix] ) * (CUDART_PI_F /180.0);
const double a = pow(sin(dLat/2.0),2.0) + pow(sin(dLon/2.0),2.0) * cos(in[lat1ix] * (CUDART_PI_F/180.0)) * cos(in[lat2ix] * (CUDART_PI_F/180.0));
const double c = 2.0 * asin(sqrt(a));
out[ix] = RADIUS_IN_KM * c;
}
} | #include <hip/hip_runtime.h>
#include <hip/hip_math_constants.h>
#define RADIUS_IN_KM 6372.8
extern "C"
// Computes the haversine distance betwwen two points on Earth
__global__ void haversine(int *size, double *in, double *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size ) {
const int lat1ix = 4*ix,lon1ix = (4*ix)+1,lat2ix = (4*ix)+2, lon2ix = (4*ix)+3;
const double dLat = (in[lat2ix] - in[lat1ix] ) * (HIP_PI_F /180.0);
const double dLon = (in[lon2ix] - in[lon1ix] ) * (HIP_PI_F /180.0);
const double a = pow(sin(dLat/2.0),2.0) + pow(sin(dLon/2.0),2.0) * cos(in[lat1ix] * (HIP_PI_F/180.0)) * cos(in[lat2ix] * (HIP_PI_F/180.0));
const double c = 2.0 * asin(sqrt(a));
out[ix] = RADIUS_IN_KM * c;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_math_constants.h>
#define RADIUS_IN_KM 6372.8
extern "C"
// Computes the haversine distance betwwen two points on Earth
__global__ void haversine(int *size, double *in, double *out) {
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
if (ix < *size ) {
const int lat1ix = 4*ix,lon1ix = (4*ix)+1,lat2ix = (4*ix)+2, lon2ix = (4*ix)+3;
const double dLat = (in[lat2ix] - in[lat1ix] ) * (HIP_PI_F /180.0);
const double dLon = (in[lon2ix] - in[lon1ix] ) * (HIP_PI_F /180.0);
const double a = pow(sin(dLat/2.0),2.0) + pow(sin(dLon/2.0),2.0) * cos(in[lat1ix] * (HIP_PI_F/180.0)) * cos(in[lat2ix] * (HIP_PI_F/180.0));
const double c = 2.0 * asin(sqrt(a));
out[ix] = RADIUS_IN_KM * c;
}
} | .text
.file "MatchEmergencyCalls.hip"
.globl __device_stub__haversine # -- Begin function __device_stub__haversine
.p2align 4, 0x90
.type __device_stub__haversine,@function
__device_stub__haversine: # @__device_stub__haversine
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $haversine, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__haversine, .Lfunc_end0-__device_stub__haversine
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $haversine, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type haversine,@object # @haversine
.section .rodata,"a",@progbits
.globl haversine
.p2align 3, 0x0
haversine:
.quad __device_stub__haversine
.size haversine, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "haversine"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__haversine
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym haversine
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ee574_00000000-6_MatchEmergencyCalls.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_
.type _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_, @function
_Z33__device_stub__Z9haversinePiPdS0_PiPdS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq haversine(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_, .-_Z33__device_stub__Z9haversinePiPdS0_PiPdS0_
.globl haversine
.type haversine, @function
haversine:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9haversinePiPdS0_PiPdS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size haversine, .-haversine
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "haversine"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq haversine(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatchEmergencyCalls.hip"
.globl __device_stub__haversine # -- Begin function __device_stub__haversine
.p2align 4, 0x90
.type __device_stub__haversine,@function
__device_stub__haversine: # @__device_stub__haversine
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $haversine, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__haversine, .Lfunc_end0-__device_stub__haversine
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $haversine, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type haversine,@object # @haversine
.section .rodata,"a",@progbits
.globl haversine
.p2align 3, 0x0
haversine:
.quad __device_stub__haversine
.size haversine, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "haversine"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__haversine
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym haversine
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /** @file
* Name: Parallel LU Decomposition - CUDA Version
* Authored by: Team Segfault
* Description: This program performs Lower/Upper decomposition on a square matrix and
* subsequently solves the associated system of equations with Forward and Backward substitution.
* Implementation Date: 11/23/2020
*/
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
bool GetUserInput(int, char *[], int&,int&);
void InitializeMatrices(float **&, float **&, float **&, int);
void InitializeVectors(float *&, float*&, float*&, int);
void PrintMatrix(float **, int);
void PrintVector(float*, int);
void DeleteMatrix(float**,int);
void DeleteVector(float *);
void LUDecomp(float *, float *, int);
__global__ void RowOperations(float *, float *, int, int);
__global__ void ForwardSubstitution(float *, float *, float* , int);
__global__ void BackwardSubstitution(float *, float *, float* , int);
//------------------------------------------------------------------
// Main Program
//------------------------------------------------------------------
int main(int argc, char *argv[]){
srand(time(NULL)); //set the seed
float **a, **lower, **upper; //Matrices
float *b, *x, *y; //Vectors
float *d_lower, *d_upper, *d_b, *d_x, *d_y; //Device pointers
int n,isPrint;
float runtime;
if (!GetUserInput(argc,argv,n,isPrint)) return 1;
// a == upper and lower -> 0
InitializeMatrices(a, lower, upper, n);
InitializeVectors(x, y, b, n);
//Get start time
runtime = clock()/(float)CLOCKS_PER_SEC;
// ######################### BEGIN LU Decomp ##############################3
cudaMalloc((void**)&d_lower, n*n*sizeof(float));
cudaMalloc((void**)&d_upper, n*n*sizeof(float));
cudaMemcpy(d_upper, upper[0], n*n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_lower, lower[0], n*n*sizeof(float), cudaMemcpyHostToDevice);
LUDecomp(d_lower, d_upper, n);
cudaDeviceSynchronize();
// ######################### END LU Decomp ##############################3
// ######################### BEGIN Substitution ##############################
cudaMalloc((void**)&d_b, n*sizeof(float));
cudaMalloc((void**)&d_x, n*sizeof(float));
cudaMalloc((void**)&d_y, n*sizeof(float));
cudaMemcpy(d_b, b, n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_x, x, n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, n*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimGrid(n,1);
dim3 dimBlock(n,1);
ForwardSubstitution<<<dimGrid, dimBlock>>>(d_lower, d_y, d_b, n);
BackwardSubstitution<<<dimGrid, dimBlock>>>(d_upper, d_x, d_y, n);
cudaThreadSynchronize();
// ######################### END Substitution ##############################3
// ######################### BEGIN Copy Back ##############################
cudaMemcpy(lower[0],d_lower, n*n*sizeof(float),cudaMemcpyDeviceToHost);
cudaMemcpy(upper[0],d_upper, n*n*sizeof(float),cudaMemcpyDeviceToHost);
cudaMemcpy(x,d_x, n*sizeof(float),cudaMemcpyDeviceToHost);
cudaMemcpy(y,d_y, n*sizeof(float),cudaMemcpyDeviceToHost);
// ######################### END Copy Back ##############################
runtime = clock() - runtime; //Make note of time
if(isPrint == 1){
printf("A:\n");
PrintMatrix(a,n);
printf("B:\n");
PrintVector(b,n);
printf("--------------------------------------------------\n");
printf("Lower:\n");
PrintMatrix(lower,n);
printf("Upper:\n");
PrintMatrix(upper,n);
printf("Y:\n");
PrintVector(y,n);
printf("X:\n");
PrintVector(x,n);
}
printf("LU Decomposition and Forward/Backward substitution to solve Ax=B ran in %.2f seconds\n", (runtime)/float(CLOCKS_PER_SEC));
cudaFree(d_lower);
cudaFree(d_upper);
cudaFree(d_b);
cudaFree(d_x);
cudaFree(d_y);
DeleteMatrix(upper,n);
DeleteMatrix(lower,n);
DeleteMatrix(a,n);
DeleteVector(x);
DeleteVector(y);
DeleteVector(b);
return 0;
}
//------------------------------------------------------------------
// KERNEL DRIVERS
//------------------------------------------------------------------
void LUDecomp(float *d_lower, float *d_upper, int thicness){
int i, numBlocks, numThreads;
for(i = 0; i < thicness; ++i){
// Since all of these are square these are the same.
numBlocks = numThreads = thicness-i;
dim3 dimGrid(numBlocks,1);
dim3 dimBlock(numThreads,1);
RowOperations<<<dimGrid,dimBlock>>>(d_lower, d_upper, i, thicness);
}
}
//------------------------------------------------------------------
// KERNELS
//------------------------------------------------------------------
__global__ void RowOperations(float *lower, float *upper, int i, int thicness){
// Let us get this diagonal thing out of the way
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
lower[ i*thicness + i ] = 1;
int k = blockIdx.x + i + 1;
int j = threadIdx.x + i;
if( !( k < thicness && j < thicness) ) return; // Whoops
__shared__ float pivot;
// And get one pivot per block
if(threadIdx.x == 0)
pivot = -1.0/upper[ i*thicness + i ];
// Hey guys! Wait up!
__syncthreads();
// It is worth noting that the matrices are column major here
lower[k + thicness*i] = upper[k + thicness*i]/upper[i + thicness*i];
upper[k + thicness*j] = upper[k + thicness*j] + pivot*upper[k + thicness*i] * upper[i + thicness*j];
}
__global__ void ForwardSubstitution(float *lower, float *y, float* b, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0) // Last Element
y[0] = b[0] / lower[0];
int i = blockIdx.x + 1;
int j = i - threadIdx.x;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = b[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - lower[ i + thicness*j] * y[j];
// Hey guys! Wait up!
__syncthreads();
y[i] = temp/lower[i + thicness*i];
}
__global__ void BackwardSubstitution(float *upper, float *x, float* y, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
x[thicness - 1] = y[thicness - 1] / upper[(thicness - 1) + thicness*(thicness-1)]; // Last Element
int i = thicness - blockIdx.x - 2;
int j = thicness - i - threadIdx.x - 1;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = y[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - upper[ i + thicness*j] * x[j];
// Hey guys! Wait up!
__syncthreads();
x[i] = temp/upper[i + thicness*i];
}
//------------------------------------------------------------------
// UTILITIES
//------------------------------------------------------------------
// Get user input of matrix dimension and printing option
bool GetUserInput(int argc, char *argv[],int& n,int& isPrint)
{
bool isOK = true;
if(argc < 2)
{
printf("Arguments:<X> [<Y>]");
printf("X : Matrix size [X x X]");
printf("Y = 1: print the input/output matrix if X < 10");
printf("Y <> 1 or missing: does not print the input/output matrix");
isOK = false;
}
else
{
//get matrix size
n = atoi(argv[1]);
if (n <=0)
{
printf("Matrix size must be larger than 0");
isOK = false;
}
//is print the input/output matrix
if (argc >=3)
isPrint = (atoi(argv[2])==1 && n <=9)?1:0;
else
isPrint = 0;
}
return isOK;
}
//delete matrix matrix a[n x n]
void DeleteMatrix(float **a,int n)
{
delete[] a[0];
delete[] a;
}
void DeleteVector(float* x)
{
delete[] x;
}
//Fills matrix A with random values, upper and lower is filled with 0's except for their diagonals
void InitializeMatrices(float **&a, float **&lower, float **&upper, int size){
a = new float*[size];
a[0] = new float[size*size];
for (int i = 1; i < size; i++)
a[i] = a[i-1] + size;
lower = new float*[size];
lower[0] = new float[size*size];
for (int i = 1; i < size; i++)
lower[i] = lower[i-1] + size;
upper = new float*[size];
upper[0] = new float[size*size];
for (int i = 1; i < size; i++)
upper[i] = upper[i-1] + size;
for(int i = 0; i < size; ++i){
for(int j = 0; j < size; ++j){
upper[i][j] = a[i][j] = (rand() % 11) + 1;
lower[i][j] = 0;
}
}
}
void InitializeVectors(float *&x, float *&y, float*& b, int n) {
// allocate square 2d matrix
x = new float[n];
y = new float[n];
b = new float[n];
for (int j = 0 ; j < n ; j++) {
b[j] = (float)(rand() % 11) + 1;
x[j] = y[j] = 0;
}
}
//Print the matrix that was passed to it
void PrintMatrix(float **matrix, int size)
{
for (int i = 0 ; i < size ; i++){
for (int j = 0 ; j < size ; j++){
printf("%.2f\t", matrix[j][i]);
}
printf("\n");
}
}
void PrintVector(float* x, int n)
{
for (int j = 0 ; j < n ; j++) {
printf("%.2f\n", x[j]);
}
} | .file "tmpxft_0005941c_00000000-6_LU-Decomp-CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Arguments:<X> [<Y>]"
.LC1:
.string "X : Matrix size [X x X]"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Y = 1: print the input/output matrix if X < 10"
.align 8
.LC3:
.string "Y <> 1 or missing: does not print the input/output matrix"
.align 8
.LC4:
.string "Matrix size must be larger than 0"
.text
.globl _Z12GetUserInputiPPcRiS1_
.type _Z12GetUserInputiPPcRiS1_, @function
_Z12GetUserInputiPPcRiS1_:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
cmpl $1, %edi
jle .L12
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%r12)
movl $1, %r14d
testl %eax, %eax
jle .L13
.L6:
cmpl $2, %ebx
jg .L14
movl $0, 0(%r13)
jmp .L3
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
.L3:
movl %r14d, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
jmp .L6
.L14:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rdx
movl $0, %eax
cmpl $1, %edx
je .L15
.L8:
movl %eax, 0(%r13)
jmp .L3
.L15:
cmpl $9, (%r12)
setle %al
movzbl %al, %eax
jmp .L8
.cfi_endproc
.LFE2059:
.size _Z12GetUserInputiPPcRiS1_, .-_Z12GetUserInputiPPcRiS1_
.globl _Z12DeleteMatrixPPfi
.type _Z12DeleteMatrixPPfi, @function
_Z12DeleteMatrixPPfi:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
testq %rdi, %rdi
je .L17
call _ZdaPv@PLT
.L17:
movq %rbx, %rdi
call _ZdaPv@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12DeleteMatrixPPfi, .-_Z12DeleteMatrixPPfi
.globl _Z12DeleteVectorPf
.type _Z12DeleteVectorPf, @function
_Z12DeleteVectorPf:
.LFB2061:
.cfi_startproc
endbr64
testq %rdi, %rdi
je .L22
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZdaPv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L22:
ret
.cfi_endproc
.LFE2061:
.size _Z12DeleteVectorPf, .-_Z12DeleteVectorPf
.globl _Z18InitializeMatricesRPPfS1_S1_i
.type _Z18InitializeMatricesRPPfS1_S1_i, @function
_Z18InitializeMatricesRPPfS1_S1_i:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movslq %ecx, %r15
movq %r15, %rax
shrq $60, %rax
jne .L26
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebx
leaq 0(,%r15,8), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %rax, (%r14)
movl %ebx, %eax
imull %ebx, %eax
cltq
salq $2, %rax
movq %rax, 16(%rsp)
movq %rax, %rdi
call _Znam@PLT
movq %rax, 0(%rbp)
cmpl $1, %ebx
jle .L42
leaq 0(,%r15,4), %rbp
leal -1(%rbx), %ebx
salq $3, %rbx
movl $0, %eax
.L29:
movq (%r14), %rdx
movq %rax, %rcx
addq $8, %rax
movq %rbp, %rsi
addq (%rdx,%rcx), %rsi
movq %rsi, (%rdx,%rax)
cmpq %rbx, %rax
jne .L29
movq 8(%rsp), %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movq %rax, 0(%r13)
movq 16(%rsp), %rdi
call _Znam@PLT
movq 24(%rsp), %rdi
movq %rax, (%rdi)
movl $0, %eax
.L30:
movq 0(%r13), %rdx
movq %rax, %rcx
addq $8, %rax
movq %rbp, %rdi
addq (%rdx,%rcx), %rdi
movq %rdi, (%rdx,%rax)
cmpq %rbx, %rax
jne .L30
movq 8(%rsp), %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movq %rax, (%r12)
movq 16(%rsp), %rdi
call _Znam@PLT
movq 24(%rsp), %rdi
movq %rax, (%rdi)
movl $0, %eax
.L31:
movq (%r12), %rdx
movq %rax, %rcx
addq $8, %rax
movq %rbp, %rsi
addq (%rdx,%rcx), %rsi
movq %rsi, (%rdx,%rax)
cmpq %rbx, %rax
jne .L31
.L35:
salq $2, %r15
movl $0, %ebp
.L32:
movl $0, %ebx
.L33:
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movq (%r14), %rax
movq (%rax,%rbp), %rax
movss %xmm0, (%rax,%rbx)
movq (%r12), %rax
movq (%rax,%rbp), %rax
movss %xmm0, (%rax,%rbx)
movq 0(%r13), %rax
movq (%rax,%rbp), %rax
movl $0x00000000, (%rax,%rbx)
addq $4, %rbx
cmpq %rbx, %r15
jne .L33
addq $8, %rbp
cmpq %rbp, 8(%rsp)
jne .L32
.L25:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.L42:
movq 8(%rsp), %rdi
call _Znam@PLT
movq %rax, %rbp
movq %rax, 0(%r13)
movq 16(%rsp), %rdi
call _Znam@PLT
movq %rax, 0(%rbp)
movq 8(%rsp), %rdi
call _Znam@PLT
movq %rax, %rbp
movq %rax, (%r12)
movq 16(%rsp), %rdi
call _Znam@PLT
movq %rax, 0(%rbp)
testl %ebx, %ebx
jle .L25
jmp .L35
.cfi_endproc
.LFE2062:
.size _Z18InitializeMatricesRPPfS1_S1_i, .-_Z18InitializeMatricesRPPfS1_S1_i
.globl _Z17InitializeVectorsRPfS0_S0_i
.type _Z17InitializeVectorsRPfS0_S0_i, @function
_Z17InitializeVectorsRPfS0_S0_i:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %ecx, %rbp
movabsq $2305843009213693950, %rax
cmpq %rbp, %rax
jb .L44
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %r15d
salq $2, %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, (%r14)
movq %rbp, %rdi
call _Znam@PLT
movq %rax, 0(%r13)
movq %rbp, %rdi
call _Znam@PLT
movq %rax, (%r12)
movl $0, %ebx
testl %r15d, %r15d
jle .L43
.L45:
call rand@PLT
movq (%r12), %rcx
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %esi
leal (%rdx,%rsi,2), %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss .LC6(%rip), %xmm0
movss %xmm0, (%rcx,%rbx)
movq 0(%r13), %rax
movl $0x00000000, (%rax,%rbx)
movq (%r14), %rax
movl $0x00000000, (%rax,%rbx)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L45
.L43:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE2063:
.size _Z17InitializeVectorsRPfS0_S0_i, .-_Z17InitializeVectorsRPfS0_S0_i
.section .rodata.str1.1
.LC7:
.string "%.2f\t"
.LC8:
.string "\n"
.text
.globl _Z11PrintMatrixPPfi
.type _Z11PrintMatrixPPfi, @function
_Z11PrintMatrixPPfi:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
testl %esi, %esi
jle .L51
movslq %esi, %rsi
leaq 0(,%rsi,4), %r15
leaq (%rdi,%rsi,8), %r13
movl $0, %ebp
leaq .LC7(%rip), %r12
leaq .LC8(%rip), %r14
.L53:
movq 8(%rsp), %rbx
.L54:
movq (%rbx), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L54
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r15, %rbp
jne .L53
.L51:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z11PrintMatrixPPfi, .-_Z11PrintMatrixPPfi
.section .rodata.str1.1
.LC9:
.string "%.2f\n"
.text
.globl _Z11PrintVectorPfi
.type _Z11PrintVectorPfi, @function
_Z11PrintVectorPfi:
.LFB2065:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L62
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r12
leaq .LC9(%rip), %rbp
.L59:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L59
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2065:
.size _Z11PrintVectorPfi, .-_Z11PrintVectorPfi
.globl _Z37__device_stub__Z13RowOperationsPfS_iiPfS_ii
.type _Z37__device_stub__Z13RowOperationsPfS_iiPfS_ii, @function
_Z37__device_stub__Z13RowOperationsPfS_iiPfS_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L69
.L65:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13RowOperationsPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L65
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z37__device_stub__Z13RowOperationsPfS_iiPfS_ii, .-_Z37__device_stub__Z13RowOperationsPfS_iiPfS_ii
.globl _Z13RowOperationsPfS_ii
.type _Z13RowOperationsPfS_ii, @function
_Z13RowOperationsPfS_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13RowOperationsPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z13RowOperationsPfS_ii, .-_Z13RowOperationsPfS_ii
.globl _Z8LUDecompPfS_i
.type _Z8LUDecompPfS_i, @function
_Z8LUDecompPfS_i:
.LFB2058:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L79
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebp
movl $0, %ebx
jmp .L76
.L75:
addl $1, %ebx
cmpl %ebx, %ebp
je .L82
.L76:
movl %ebp, %eax
subl %ebx, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L75
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z37__device_stub__Z13RowOperationsPfS_iiPfS_ii
jmp .L75
.L82:
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2058:
.size _Z8LUDecompPfS_i, .-_Z8LUDecompPfS_i
.globl _Z44__device_stub__Z19ForwardSubstitutionPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19ForwardSubstitutionPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19ForwardSubstitutionPfS_S_iPfS_S_i:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L87
.L83:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L88
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L87:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19ForwardSubstitutionPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L83
.L88:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z44__device_stub__Z19ForwardSubstitutionPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19ForwardSubstitutionPfS_S_iPfS_S_i
.globl _Z19ForwardSubstitutionPfS_S_i
.type _Z19ForwardSubstitutionPfS_S_i, @function
_Z19ForwardSubstitutionPfS_S_i:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19ForwardSubstitutionPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z19ForwardSubstitutionPfS_S_i, .-_Z19ForwardSubstitutionPfS_S_i
.globl _Z45__device_stub__Z20BackwardSubstitutionPfS_S_iPfS_S_i
.type _Z45__device_stub__Z20BackwardSubstitutionPfS_S_iPfS_S_i, @function
_Z45__device_stub__Z20BackwardSubstitutionPfS_S_iPfS_S_i:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L95
.L91:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L95:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20BackwardSubstitutionPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L91
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z45__device_stub__Z20BackwardSubstitutionPfS_S_iPfS_S_i, .-_Z45__device_stub__Z20BackwardSubstitutionPfS_S_iPfS_S_i
.globl _Z20BackwardSubstitutionPfS_S_i
.type _Z20BackwardSubstitutionPfS_S_i, @function
_Z20BackwardSubstitutionPfS_S_i:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20BackwardSubstitutionPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z20BackwardSubstitutionPfS_S_i, .-_Z20BackwardSubstitutionPfS_S_i
.section .rodata.str1.1
.LC11:
.string "A:\n"
.LC12:
.string "B:\n"
.section .rodata.str1.8
.align 8
.LC13:
.string "--------------------------------------------------\n"
.section .rodata.str1.1
.LC14:
.string "Lower:\n"
.LC15:
.string "Upper:\n"
.LC16:
.string "Y:\n"
.LC17:
.string "X:\n"
.section .rodata.str1.8
.align 8
.LC18:
.string "LU Decomposition and Forward/Backward substitution to solve Ax=B ran in %.2f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z12GetUserInputiPPcRiS1_
movl %eax, %edx
movl $1, %eax
testb %dl, %dl
jne .L107
.L99:
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L108
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L107:
.cfi_restore_state
movl 32(%rsp), %ebx
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdi
movl %ebx, %ecx
call _Z18InitializeMatricesRPPfS1_S1_i
leaq 64(%rsp), %rdx
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdi
movl %ebx, %ecx
call _Z17InitializeVectorsRPfS0_S0_i
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC10(%rip), %xmm0
movss %xmm0, 28(%rsp)
movl %ebx, %r12d
imull %ebx, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 88(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movq 56(%rsp), %r15
movl $1, %ecx
movq %r12, %rdx
movq (%r15), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %r14
movl $1, %ecx
movq %r12, %rdx
movq (%r14), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, %edx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z8LUDecompPfS_i
call cudaDeviceSynchronize@PLT
movslq %ebx, %rbp
salq $2, %rbp
leaq 104(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movq 64(%rsp), %rax
movq %rax, 16(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %rax, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %r13
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 112(%rsp), %rdi
call cudaMemcpy@PLT
movq 80(%rsp), %rax
movq %rax, 8(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %rax, %rsi
movq 120(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebx, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl %ebx, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movl $1, %ecx
movq 128(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L109
.L101:
movl 148(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 140(%rsp), %rdx
movq 128(%rsp), %rdi
movl 136(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L110
.L102:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movq %r12, %rdx
movq 88(%rsp), %rsi
movq (%r14), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq 96(%rsp), %rsi
movq (%r15), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 112(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 120(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
subss 28(%rsp), %xmm0
movd %xmm0, %ebp
cmpl $1, 36(%rsp)
je .L111
.L103:
movd %ebp, %xmm0
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movl %ebx, %esi
movq %r15, %rdi
call _Z12DeleteMatrixPPfi
movl %ebx, %esi
movq %r14, %rdi
call _Z12DeleteMatrixPPfi
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z12DeleteMatrixPPfi
movq %r13, %rdi
call _Z12DeleteVectorPf
movq 8(%rsp), %rdi
call _Z12DeleteVectorPf
movq 16(%rsp), %rdi
call _Z12DeleteVectorPf
movl $0, %eax
jmp .L99
.L109:
movl %ebx, %ecx
movq 104(%rsp), %rdx
movq 120(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z44__device_stub__Z19ForwardSubstitutionPfS_S_iPfS_S_i
jmp .L101
.L110:
movl %ebx, %ecx
movq 120(%rsp), %rdx
movq 112(%rsp), %rsi
movq 96(%rsp), %rdi
call _Z45__device_stub__Z20BackwardSubstitutionPfS_S_iPfS_S_i
jmp .L102
.L111:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq 40(%rsp), %rdi
call _Z11PrintMatrixPPfi
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq 16(%rsp), %rdi
call _Z11PrintVectorPfi
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq %r14, %rdi
call _Z11PrintMatrixPPfi
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq %r15, %rdi
call _Z11PrintMatrixPPfi
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z11PrintVectorPfi
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq %r13, %rdi
call _Z11PrintVectorPfi
jmp .L103
.L108:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC19:
.string "_Z20BackwardSubstitutionPfS_S_i"
.align 8
.LC20:
.string "_Z19ForwardSubstitutionPfS_S_i"
.section .rodata.str1.1
.LC21:
.string "_Z13RowOperationsPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z20BackwardSubstitutionPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z19ForwardSubstitutionPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z13RowOperationsPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.align 4
.LC10:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /** @file
* Name: Parallel LU Decomposition - CUDA Version
* Authored by: Team Segfault
* Description: This program performs Lower/Upper decomposition on a square matrix and
* subsequently solves the associated system of equations with Forward and Backward substitution.
* Implementation Date: 11/23/2020
*/
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
bool GetUserInput(int, char *[], int&,int&);
void InitializeMatrices(float **&, float **&, float **&, int);
void InitializeVectors(float *&, float*&, float*&, int);
void PrintMatrix(float **, int);
void PrintVector(float*, int);
void DeleteMatrix(float**,int);
void DeleteVector(float *);
void LUDecomp(float *, float *, int);
__global__ void RowOperations(float *, float *, int, int);
__global__ void ForwardSubstitution(float *, float *, float* , int);
__global__ void BackwardSubstitution(float *, float *, float* , int);
//------------------------------------------------------------------
// Main Program
//------------------------------------------------------------------
int main(int argc, char *argv[]){
srand(time(NULL)); //set the seed
float **a, **lower, **upper; //Matrices
float *b, *x, *y; //Vectors
float *d_lower, *d_upper, *d_b, *d_x, *d_y; //Device pointers
int n,isPrint;
float runtime;
if (!GetUserInput(argc,argv,n,isPrint)) return 1;
// a == upper and lower -> 0
InitializeMatrices(a, lower, upper, n);
InitializeVectors(x, y, b, n);
//Get start time
runtime = clock()/(float)CLOCKS_PER_SEC;
// ######################### BEGIN LU Decomp ##############################3
cudaMalloc((void**)&d_lower, n*n*sizeof(float));
cudaMalloc((void**)&d_upper, n*n*sizeof(float));
cudaMemcpy(d_upper, upper[0], n*n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_lower, lower[0], n*n*sizeof(float), cudaMemcpyHostToDevice);
LUDecomp(d_lower, d_upper, n);
cudaDeviceSynchronize();
// ######################### END LU Decomp ##############################3
// ######################### BEGIN Substitution ##############################
cudaMalloc((void**)&d_b, n*sizeof(float));
cudaMalloc((void**)&d_x, n*sizeof(float));
cudaMalloc((void**)&d_y, n*sizeof(float));
cudaMemcpy(d_b, b, n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_x, x, n*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, n*sizeof(float), cudaMemcpyHostToDevice);
dim3 dimGrid(n,1);
dim3 dimBlock(n,1);
ForwardSubstitution<<<dimGrid, dimBlock>>>(d_lower, d_y, d_b, n);
BackwardSubstitution<<<dimGrid, dimBlock>>>(d_upper, d_x, d_y, n);
cudaThreadSynchronize();
// ######################### END Substitution ##############################3
// ######################### BEGIN Copy Back ##############################
cudaMemcpy(lower[0],d_lower, n*n*sizeof(float),cudaMemcpyDeviceToHost);
cudaMemcpy(upper[0],d_upper, n*n*sizeof(float),cudaMemcpyDeviceToHost);
cudaMemcpy(x,d_x, n*sizeof(float),cudaMemcpyDeviceToHost);
cudaMemcpy(y,d_y, n*sizeof(float),cudaMemcpyDeviceToHost);
// ######################### END Copy Back ##############################
runtime = clock() - runtime; //Make note of time
if(isPrint == 1){
printf("A:\n");
PrintMatrix(a,n);
printf("B:\n");
PrintVector(b,n);
printf("--------------------------------------------------\n");
printf("Lower:\n");
PrintMatrix(lower,n);
printf("Upper:\n");
PrintMatrix(upper,n);
printf("Y:\n");
PrintVector(y,n);
printf("X:\n");
PrintVector(x,n);
}
printf("LU Decomposition and Forward/Backward substitution to solve Ax=B ran in %.2f seconds\n", (runtime)/float(CLOCKS_PER_SEC));
cudaFree(d_lower);
cudaFree(d_upper);
cudaFree(d_b);
cudaFree(d_x);
cudaFree(d_y);
DeleteMatrix(upper,n);
DeleteMatrix(lower,n);
DeleteMatrix(a,n);
DeleteVector(x);
DeleteVector(y);
DeleteVector(b);
return 0;
}
//------------------------------------------------------------------
// KERNEL DRIVERS
//------------------------------------------------------------------
void LUDecomp(float *d_lower, float *d_upper, int thicness){
int i, numBlocks, numThreads;
for(i = 0; i < thicness; ++i){
// Since all of these are square these are the same.
numBlocks = numThreads = thicness-i;
dim3 dimGrid(numBlocks,1);
dim3 dimBlock(numThreads,1);
RowOperations<<<dimGrid,dimBlock>>>(d_lower, d_upper, i, thicness);
}
}
//------------------------------------------------------------------
// KERNELS
//------------------------------------------------------------------
__global__ void RowOperations(float *lower, float *upper, int i, int thicness){
// Let us get this diagonal thing out of the way
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
lower[ i*thicness + i ] = 1;
int k = blockIdx.x + i + 1;
int j = threadIdx.x + i;
if( !( k < thicness && j < thicness) ) return; // Whoops
__shared__ float pivot;
// And get one pivot per block
if(threadIdx.x == 0)
pivot = -1.0/upper[ i*thicness + i ];
// Hey guys! Wait up!
__syncthreads();
// It is worth noting that the matrices are column major here
lower[k + thicness*i] = upper[k + thicness*i]/upper[i + thicness*i];
upper[k + thicness*j] = upper[k + thicness*j] + pivot*upper[k + thicness*i] * upper[i + thicness*j];
}
__global__ void ForwardSubstitution(float *lower, float *y, float* b, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0) // Last Element
y[0] = b[0] / lower[0];
int i = blockIdx.x + 1;
int j = i - threadIdx.x;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = b[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - lower[ i + thicness*j] * y[j];
// Hey guys! Wait up!
__syncthreads();
y[i] = temp/lower[i + thicness*i];
}
__global__ void BackwardSubstitution(float *upper, float *x, float* y, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
x[thicness - 1] = y[thicness - 1] / upper[(thicness - 1) + thicness*(thicness-1)]; // Last Element
int i = thicness - blockIdx.x - 2;
int j = thicness - i - threadIdx.x - 1;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = y[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - upper[ i + thicness*j] * x[j];
// Hey guys! Wait up!
__syncthreads();
x[i] = temp/upper[i + thicness*i];
}
//------------------------------------------------------------------
// UTILITIES
//------------------------------------------------------------------
// Get user input of matrix dimension and printing option
bool GetUserInput(int argc, char *argv[],int& n,int& isPrint)
{
bool isOK = true;
if(argc < 2)
{
printf("Arguments:<X> [<Y>]");
printf("X : Matrix size [X x X]");
printf("Y = 1: print the input/output matrix if X < 10");
printf("Y <> 1 or missing: does not print the input/output matrix");
isOK = false;
}
else
{
//get matrix size
n = atoi(argv[1]);
if (n <=0)
{
printf("Matrix size must be larger than 0");
isOK = false;
}
//is print the input/output matrix
if (argc >=3)
isPrint = (atoi(argv[2])==1 && n <=9)?1:0;
else
isPrint = 0;
}
return isOK;
}
//delete matrix matrix a[n x n]
void DeleteMatrix(float **a,int n)
{
delete[] a[0];
delete[] a;
}
void DeleteVector(float* x)
{
delete[] x;
}
//Fills matrix A with random values, upper and lower is filled with 0's except for their diagonals
void InitializeMatrices(float **&a, float **&lower, float **&upper, int size){
a = new float*[size];
a[0] = new float[size*size];
for (int i = 1; i < size; i++)
a[i] = a[i-1] + size;
lower = new float*[size];
lower[0] = new float[size*size];
for (int i = 1; i < size; i++)
lower[i] = lower[i-1] + size;
upper = new float*[size];
upper[0] = new float[size*size];
for (int i = 1; i < size; i++)
upper[i] = upper[i-1] + size;
for(int i = 0; i < size; ++i){
for(int j = 0; j < size; ++j){
upper[i][j] = a[i][j] = (rand() % 11) + 1;
lower[i][j] = 0;
}
}
}
void InitializeVectors(float *&x, float *&y, float*& b, int n) {
// allocate square 2d matrix
x = new float[n];
y = new float[n];
b = new float[n];
for (int j = 0 ; j < n ; j++) {
b[j] = (float)(rand() % 11) + 1;
x[j] = y[j] = 0;
}
}
//Print the matrix that was passed to it
void PrintMatrix(float **matrix, int size)
{
for (int i = 0 ; i < size ; i++){
for (int j = 0 ; j < size ; j++){
printf("%.2f\t", matrix[j][i]);
}
printf("\n");
}
}
void PrintVector(float* x, int n)
{
for (int j = 0 ; j < n ; j++) {
printf("%.2f\n", x[j]);
}
} | /** @file
* Name: Parallel LU Decomposition - CUDA Version
* Authored by: Team Segfault
* Description: This program performs Lower/Upper decomposition on a square matrix and
* subsequently solves the associated system of equations with Forward and Backward substitution.
* Implementation Date: 11/23/2020
*/
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
bool GetUserInput(int, char *[], int&,int&);
void InitializeMatrices(float **&, float **&, float **&, int);
void InitializeVectors(float *&, float*&, float*&, int);
void PrintMatrix(float **, int);
void PrintVector(float*, int);
void DeleteMatrix(float**,int);
void DeleteVector(float *);
void LUDecomp(float *, float *, int);
__global__ void RowOperations(float *, float *, int, int);
__global__ void ForwardSubstitution(float *, float *, float* , int);
__global__ void BackwardSubstitution(float *, float *, float* , int);
//------------------------------------------------------------------
// Main Program
//------------------------------------------------------------------
int main(int argc, char *argv[]){
srand(time(NULL)); //set the seed
float **a, **lower, **upper; //Matrices
float *b, *x, *y; //Vectors
float *d_lower, *d_upper, *d_b, *d_x, *d_y; //Device pointers
int n,isPrint;
float runtime;
if (!GetUserInput(argc,argv,n,isPrint)) return 1;
// a == upper and lower -> 0
InitializeMatrices(a, lower, upper, n);
InitializeVectors(x, y, b, n);
//Get start time
runtime = clock()/(float)CLOCKS_PER_SEC;
// ######################### BEGIN LU Decomp ##############################3
hipMalloc((void**)&d_lower, n*n*sizeof(float));
hipMalloc((void**)&d_upper, n*n*sizeof(float));
hipMemcpy(d_upper, upper[0], n*n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_lower, lower[0], n*n*sizeof(float), hipMemcpyHostToDevice);
LUDecomp(d_lower, d_upper, n);
hipDeviceSynchronize();
// ######################### END LU Decomp ##############################3
// ######################### BEGIN Substitution ##############################
hipMalloc((void**)&d_b, n*sizeof(float));
hipMalloc((void**)&d_x, n*sizeof(float));
hipMalloc((void**)&d_y, n*sizeof(float));
hipMemcpy(d_b, b, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x, x, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, n*sizeof(float), hipMemcpyHostToDevice);
dim3 dimGrid(n,1);
dim3 dimBlock(n,1);
ForwardSubstitution<<<dimGrid, dimBlock>>>(d_lower, d_y, d_b, n);
BackwardSubstitution<<<dimGrid, dimBlock>>>(d_upper, d_x, d_y, n);
hipDeviceSynchronize();
// ######################### END Substitution ##############################3
// ######################### BEGIN Copy Back ##############################
hipMemcpy(lower[0],d_lower, n*n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(upper[0],d_upper, n*n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(x,d_x, n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(y,d_y, n*sizeof(float),hipMemcpyDeviceToHost);
// ######################### END Copy Back ##############################
runtime = clock() - runtime; //Make note of time
if(isPrint == 1){
printf("A:\n");
PrintMatrix(a,n);
printf("B:\n");
PrintVector(b,n);
printf("--------------------------------------------------\n");
printf("Lower:\n");
PrintMatrix(lower,n);
printf("Upper:\n");
PrintMatrix(upper,n);
printf("Y:\n");
PrintVector(y,n);
printf("X:\n");
PrintVector(x,n);
}
printf("LU Decomposition and Forward/Backward substitution to solve Ax=B ran in %.2f seconds\n", (runtime)/float(CLOCKS_PER_SEC));
hipFree(d_lower);
hipFree(d_upper);
hipFree(d_b);
hipFree(d_x);
hipFree(d_y);
DeleteMatrix(upper,n);
DeleteMatrix(lower,n);
DeleteMatrix(a,n);
DeleteVector(x);
DeleteVector(y);
DeleteVector(b);
return 0;
}
//------------------------------------------------------------------
// KERNEL DRIVERS
//------------------------------------------------------------------
void LUDecomp(float *d_lower, float *d_upper, int thicness){
int i, numBlocks, numThreads;
for(i = 0; i < thicness; ++i){
// Since all of these are square these are the same.
numBlocks = numThreads = thicness-i;
dim3 dimGrid(numBlocks,1);
dim3 dimBlock(numThreads,1);
RowOperations<<<dimGrid,dimBlock>>>(d_lower, d_upper, i, thicness);
}
}
//------------------------------------------------------------------
// KERNELS
//------------------------------------------------------------------
__global__ void RowOperations(float *lower, float *upper, int i, int thicness){
// Let us get this diagonal thing out of the way
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
lower[ i*thicness + i ] = 1;
int k = blockIdx.x + i + 1;
int j = threadIdx.x + i;
if( !( k < thicness && j < thicness) ) return; // Whoops
__shared__ float pivot;
// And get one pivot per block
if(threadIdx.x == 0)
pivot = -1.0/upper[ i*thicness + i ];
// Hey guys! Wait up!
__syncthreads();
// It is worth noting that the matrices are column major here
lower[k + thicness*i] = upper[k + thicness*i]/upper[i + thicness*i];
upper[k + thicness*j] = upper[k + thicness*j] + pivot*upper[k + thicness*i] * upper[i + thicness*j];
}
__global__ void ForwardSubstitution(float *lower, float *y, float* b, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0) // Last Element
y[0] = b[0] / lower[0];
int i = blockIdx.x + 1;
int j = i - threadIdx.x;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = b[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - lower[ i + thicness*j] * y[j];
// Hey guys! Wait up!
__syncthreads();
y[i] = temp/lower[i + thicness*i];
}
__global__ void BackwardSubstitution(float *upper, float *x, float* y, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
x[thicness - 1] = y[thicness - 1] / upper[(thicness - 1) + thicness*(thicness-1)]; // Last Element
int i = thicness - blockIdx.x - 2;
int j = thicness - i - threadIdx.x - 1;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = y[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - upper[ i + thicness*j] * x[j];
// Hey guys! Wait up!
__syncthreads();
x[i] = temp/upper[i + thicness*i];
}
//------------------------------------------------------------------
// UTILITIES
//------------------------------------------------------------------
// Get user input of matrix dimension and printing option
bool GetUserInput(int argc, char *argv[],int& n,int& isPrint)
{
bool isOK = true;
if(argc < 2)
{
printf("Arguments:<X> [<Y>]");
printf("X : Matrix size [X x X]");
printf("Y = 1: print the input/output matrix if X < 10");
printf("Y <> 1 or missing: does not print the input/output matrix");
isOK = false;
}
else
{
//get matrix size
n = atoi(argv[1]);
if (n <=0)
{
printf("Matrix size must be larger than 0");
isOK = false;
}
//is print the input/output matrix
if (argc >=3)
isPrint = (atoi(argv[2])==1 && n <=9)?1:0;
else
isPrint = 0;
}
return isOK;
}
//delete matrix matrix a[n x n]
void DeleteMatrix(float **a,int n)
{
delete[] a[0];
delete[] a;
}
void DeleteVector(float* x)
{
delete[] x;
}
//Fills matrix A with random values, upper and lower is filled with 0's except for their diagonals
void InitializeMatrices(float **&a, float **&lower, float **&upper, int size){
a = new float*[size];
a[0] = new float[size*size];
for (int i = 1; i < size; i++)
a[i] = a[i-1] + size;
lower = new float*[size];
lower[0] = new float[size*size];
for (int i = 1; i < size; i++)
lower[i] = lower[i-1] + size;
upper = new float*[size];
upper[0] = new float[size*size];
for (int i = 1; i < size; i++)
upper[i] = upper[i-1] + size;
for(int i = 0; i < size; ++i){
for(int j = 0; j < size; ++j){
upper[i][j] = a[i][j] = (rand() % 11) + 1;
lower[i][j] = 0;
}
}
}
void InitializeVectors(float *&x, float *&y, float*& b, int n) {
// allocate square 2d matrix
x = new float[n];
y = new float[n];
b = new float[n];
for (int j = 0 ; j < n ; j++) {
b[j] = (float)(rand() % 11) + 1;
x[j] = y[j] = 0;
}
}
//Print the matrix that was passed to it
void PrintMatrix(float **matrix, int size)
{
for (int i = 0 ; i < size ; i++){
for (int j = 0 ; j < size ; j++){
printf("%.2f\t", matrix[j][i]);
}
printf("\n");
}
}
void PrintVector(float* x, int n)
{
for (int j = 0 ; j < n ; j++) {
printf("%.2f\n", x[j]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /** @file
* Name: Parallel LU Decomposition - CUDA Version
* Authored by: Team Segfault
* Description: This program performs Lower/Upper decomposition on a square matrix and
* subsequently solves the associated system of equations with Forward and Backward substitution.
* Implementation Date: 11/23/2020
*/
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
bool GetUserInput(int, char *[], int&,int&);
void InitializeMatrices(float **&, float **&, float **&, int);
void InitializeVectors(float *&, float*&, float*&, int);
void PrintMatrix(float **, int);
void PrintVector(float*, int);
void DeleteMatrix(float**,int);
void DeleteVector(float *);
void LUDecomp(float *, float *, int);
__global__ void RowOperations(float *, float *, int, int);
__global__ void ForwardSubstitution(float *, float *, float* , int);
__global__ void BackwardSubstitution(float *, float *, float* , int);
//------------------------------------------------------------------
// Main Program
//------------------------------------------------------------------
int main(int argc, char *argv[]){
srand(time(NULL)); //set the seed
float **a, **lower, **upper; //Matrices
float *b, *x, *y; //Vectors
float *d_lower, *d_upper, *d_b, *d_x, *d_y; //Device pointers
int n,isPrint;
float runtime;
if (!GetUserInput(argc,argv,n,isPrint)) return 1;
// a == upper and lower -> 0
InitializeMatrices(a, lower, upper, n);
InitializeVectors(x, y, b, n);
//Get start time
runtime = clock()/(float)CLOCKS_PER_SEC;
// ######################### BEGIN LU Decomp ##############################3
hipMalloc((void**)&d_lower, n*n*sizeof(float));
hipMalloc((void**)&d_upper, n*n*sizeof(float));
hipMemcpy(d_upper, upper[0], n*n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_lower, lower[0], n*n*sizeof(float), hipMemcpyHostToDevice);
LUDecomp(d_lower, d_upper, n);
hipDeviceSynchronize();
// ######################### END LU Decomp ##############################3
// ######################### BEGIN Substitution ##############################
hipMalloc((void**)&d_b, n*sizeof(float));
hipMalloc((void**)&d_x, n*sizeof(float));
hipMalloc((void**)&d_y, n*sizeof(float));
hipMemcpy(d_b, b, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x, x, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, n*sizeof(float), hipMemcpyHostToDevice);
dim3 dimGrid(n,1);
dim3 dimBlock(n,1);
ForwardSubstitution<<<dimGrid, dimBlock>>>(d_lower, d_y, d_b, n);
BackwardSubstitution<<<dimGrid, dimBlock>>>(d_upper, d_x, d_y, n);
hipDeviceSynchronize();
// ######################### END Substitution ##############################3
// ######################### BEGIN Copy Back ##############################
hipMemcpy(lower[0],d_lower, n*n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(upper[0],d_upper, n*n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(x,d_x, n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(y,d_y, n*sizeof(float),hipMemcpyDeviceToHost);
// ######################### END Copy Back ##############################
runtime = clock() - runtime; //Make note of time
if(isPrint == 1){
printf("A:\n");
PrintMatrix(a,n);
printf("B:\n");
PrintVector(b,n);
printf("--------------------------------------------------\n");
printf("Lower:\n");
PrintMatrix(lower,n);
printf("Upper:\n");
PrintMatrix(upper,n);
printf("Y:\n");
PrintVector(y,n);
printf("X:\n");
PrintVector(x,n);
}
printf("LU Decomposition and Forward/Backward substitution to solve Ax=B ran in %.2f seconds\n", (runtime)/float(CLOCKS_PER_SEC));
hipFree(d_lower);
hipFree(d_upper);
hipFree(d_b);
hipFree(d_x);
hipFree(d_y);
DeleteMatrix(upper,n);
DeleteMatrix(lower,n);
DeleteMatrix(a,n);
DeleteVector(x);
DeleteVector(y);
DeleteVector(b);
return 0;
}
//------------------------------------------------------------------
// KERNEL DRIVERS
//------------------------------------------------------------------
void LUDecomp(float *d_lower, float *d_upper, int thicness){
int i, numBlocks, numThreads;
for(i = 0; i < thicness; ++i){
// Since all of these are square these are the same.
numBlocks = numThreads = thicness-i;
dim3 dimGrid(numBlocks,1);
dim3 dimBlock(numThreads,1);
RowOperations<<<dimGrid,dimBlock>>>(d_lower, d_upper, i, thicness);
}
}
//------------------------------------------------------------------
// KERNELS
//------------------------------------------------------------------
__global__ void RowOperations(float *lower, float *upper, int i, int thicness){
// Let us get this diagonal thing out of the way
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
lower[ i*thicness + i ] = 1;
int k = blockIdx.x + i + 1;
int j = threadIdx.x + i;
if( !( k < thicness && j < thicness) ) return; // Whoops
__shared__ float pivot;
// And get one pivot per block
if(threadIdx.x == 0)
pivot = -1.0/upper[ i*thicness + i ];
// Hey guys! Wait up!
__syncthreads();
// It is worth noting that the matrices are column major here
lower[k + thicness*i] = upper[k + thicness*i]/upper[i + thicness*i];
upper[k + thicness*j] = upper[k + thicness*j] + pivot*upper[k + thicness*i] * upper[i + thicness*j];
}
__global__ void ForwardSubstitution(float *lower, float *y, float* b, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0) // Last Element
y[0] = b[0] / lower[0];
int i = blockIdx.x + 1;
int j = i - threadIdx.x;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = b[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - lower[ i + thicness*j] * y[j];
// Hey guys! Wait up!
__syncthreads();
y[i] = temp/lower[i + thicness*i];
}
__global__ void BackwardSubstitution(float *upper, float *x, float* y, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
x[thicness - 1] = y[thicness - 1] / upper[(thicness - 1) + thicness*(thicness-1)]; // Last Element
int i = thicness - blockIdx.x - 2;
int j = thicness - i - threadIdx.x - 1;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = y[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - upper[ i + thicness*j] * x[j];
// Hey guys! Wait up!
__syncthreads();
x[i] = temp/upper[i + thicness*i];
}
//------------------------------------------------------------------
// UTILITIES
//------------------------------------------------------------------
// Get user input of matrix dimension and printing option
bool GetUserInput(int argc, char *argv[],int& n,int& isPrint)
{
bool isOK = true;
if(argc < 2)
{
printf("Arguments:<X> [<Y>]");
printf("X : Matrix size [X x X]");
printf("Y = 1: print the input/output matrix if X < 10");
printf("Y <> 1 or missing: does not print the input/output matrix");
isOK = false;
}
else
{
//get matrix size
n = atoi(argv[1]);
if (n <=0)
{
printf("Matrix size must be larger than 0");
isOK = false;
}
//is print the input/output matrix
if (argc >=3)
isPrint = (atoi(argv[2])==1 && n <=9)?1:0;
else
isPrint = 0;
}
return isOK;
}
//delete matrix matrix a[n x n]
void DeleteMatrix(float **a,int n)
{
delete[] a[0];
delete[] a;
}
void DeleteVector(float* x)
{
delete[] x;
}
//Fills matrix A with random values, upper and lower is filled with 0's except for their diagonals
void InitializeMatrices(float **&a, float **&lower, float **&upper, int size){
a = new float*[size];
a[0] = new float[size*size];
for (int i = 1; i < size; i++)
a[i] = a[i-1] + size;
lower = new float*[size];
lower[0] = new float[size*size];
for (int i = 1; i < size; i++)
lower[i] = lower[i-1] + size;
upper = new float*[size];
upper[0] = new float[size*size];
for (int i = 1; i < size; i++)
upper[i] = upper[i-1] + size;
for(int i = 0; i < size; ++i){
for(int j = 0; j < size; ++j){
upper[i][j] = a[i][j] = (rand() % 11) + 1;
lower[i][j] = 0;
}
}
}
void InitializeVectors(float *&x, float *&y, float*& b, int n) {
// allocate square 2d matrix
x = new float[n];
y = new float[n];
b = new float[n];
for (int j = 0 ; j < n ; j++) {
b[j] = (float)(rand() % 11) + 1;
x[j] = y[j] = 0;
}
}
//Print the matrix that was passed to it
void PrintMatrix(float **matrix, int size)
{
for (int i = 0 ; i < size ; i++){
for (int j = 0 ; j < size ; j++){
printf("%.2f\t", matrix[j][i]);
}
printf("\n");
}
}
void PrintVector(float* x, int n)
{
for (int j = 0 ; j < n ; j++) {
printf("%.2f\n", x[j]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13RowOperationsPfS_ii
.globl _Z13RowOperationsPfS_ii
.p2align 8
.type _Z13RowOperationsPfS_ii,@function
_Z13RowOperationsPfS_ii:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s6, s15, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
s_add_i32 s7, s5, 1
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1.0
s_mul_i32 s8, s7, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s2, s8
s_addc_u32 s9, s3, s9
global_store_b32 v1, v2, s[8:9]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v1, s4, v0
s_add_i32 s6, s15, s4
s_mov_b32 s7, exec_lo
s_add_i32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_max_i32_e32 v2, s6, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v2
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
s_add_i32 s8, s5, 1
v_mov_b32_e32 v0, 0
s_mul_i32 s8, s8, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s9, s8, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
global_load_b32 v2, v0, s[8:9]
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, v2, v2, -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, -1.0, v2, -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v3, -v3, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v6
v_div_fixup_f32 v2, v3, v2, -1.0
ds_store_b32 v0, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_mul_i32 s7, s5, s4
v_mov_b32_e32 v4, 0
s_add_i32 s8, s7, s6
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_ashr_i32 s9, s8, 31
s_barrier
s_lshl_b64 s[8:9], s[8:9], 2
buffer_gl0_inv
s_add_u32 s10, s0, s8
s_addc_u32 s11, s1, s9
s_add_i32 s12, s7, s4
v_mul_lo_u32 v1, v1, s5
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
s_add_u32 s12, s0, s12
s_addc_u32 s13, s1, s13
s_clause 0x1
global_load_b32 v5, v4, s[12:13]
global_load_b32 v6, v4, s[10:11]
v_add_nc_u32_e32 v2, s6, v1
s_add_u32 s2, s2, s8
s_addc_u32 s3, s3, s9
s_waitcnt vmcnt(0)
v_div_scale_f32 v8, null, v5, v5, v6
v_div_scale_f32 v10, vcc_lo, v6, v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v0, -v8, v9, 1.0
v_fmac_f32_e32 v9, v0, v9
v_add_nc_u32_e32 v0, s4, v1
ds_load_b32 v7, v4
v_mul_f32_e32 v11, v10, v9
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, -v8, v11, v10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v3, v9
v_ashrrev_i32_e32 v3, 31, v2
v_fma_f32 v8, -v8, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_div_fmas_f32 v8, v8, v9, v11
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v5, v8, v5, v6
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v4, v5, s[2:3]
s_clause 0x2
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v4, s[10:11]
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_f32_e32 v1, v7, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v1, v0
global_store_b32 v[2:3], v4, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13RowOperationsPfS_ii
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13RowOperationsPfS_ii, .Lfunc_end0-_Z13RowOperationsPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19ForwardSubstitutionPfS_S_i
.globl _Z19ForwardSubstitutionPfS_S_i
.p2align 8
.type _Z19ForwardSubstitutionPfS_S_i,@function
_Z19ForwardSubstitutionPfS_S_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s2, s15, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b32 s3, s[8:9], 0x0
s_load_b32 s10, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v1, null, s10, s10, s3
v_div_scale_f32 v4, vcc_lo, s3, s10, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v4, v2
v_fma_f32 v5, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v2
v_fma_f32 v1, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v1, v1, v2, v3
v_mov_b32_e32 v2, 0
v_div_fixup_f32 v1, v1, s10, s3
global_store_b32 v2, v1, s[6:7]
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s1, s[0:1], 0x18
s_add_i32 s2, s15, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s2, s1
s_cbranch_scc1 .LBB1_7
v_sub_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s1, v1
v_cmp_lt_i32_e64 s0, -1, v1
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s0
s_cbranch_execz .LBB1_7
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_6
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[10:11], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
global_load_b32 v2, v0, s[8:9]
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s0
v_mad_u64_u32 v[3:4], null, v1, s1, s[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_add_i32 s0, s1, 1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_mul_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_ashr_i32 s1, s0, 31
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s4, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
ds_load_b32 v3, v2
s_addc_u32 s1, s5, s1
s_ashr_i32 s3, s2, 31
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v0, -v1, v0, v3
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v0, v2, s[0:1]
ds_load_b32 v1, v2
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v3, null, v0, v0, v1
v_div_scale_f32 v6, vcc_lo, v1, v0, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19ForwardSubstitutionPfS_S_i
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19ForwardSubstitutionPfS_S_i, .Lfunc_end1-_Z19ForwardSubstitutionPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20BackwardSubstitutionPfS_S_i
.globl _Z20BackwardSubstitutionPfS_S_i
.p2align 8
.type _Z20BackwardSubstitutionPfS_S_i,@function
_Z20BackwardSubstitutionPfS_S_i:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s10, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_sub_nc_u32_e32 v1, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s0, s15, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s0, v1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB2_2
s_add_i32 s2, s10, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[12:13], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_u32 s16, s8, s12
s_addc_u32 s17, s9, s13
s_add_i32 s1, s10, 1
s_mul_i32 s2, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b32 s1, s[16:17], 0x0
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v1, null, s2, s2, s1
v_div_scale_f32 v4, vcc_lo, s1, s2, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v4, v2
v_fma_f32 v5, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v5, v2
v_fma_f32 v1, -v1, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v1, v1, v2, v3
v_mov_b32_e32 v2, 0
v_div_fixup_f32 v1, v1, s2, s1
s_add_u32 s2, s6, s12
s_addc_u32 s3, s7, s13
global_store_b32 v2, v1, s[2:3]
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
s_sub_i32 s0, s10, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s0, -2
s_cmp_ge_i32 s2, s10
s_cbranch_scc1 .LBB2_7
v_add_nc_u32_e32 v1, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v1, v1, -1, s10
v_cmp_gt_i32_e32 vcc_lo, s10, v1
v_cmp_lt_i32_e64 s0, -1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB2_7
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_6
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[12:13], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s8, s12
s_addc_u32 s9, s9, s13
global_load_b32 v2, v0, s[8:9]
s_waitcnt vmcnt(0)
ds_store_b32 v0, v2
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s0
v_mad_u64_u32 v[3:4], null, v1, s10, s[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_add_i32 s10, s10, 1
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_mul_i32 s0, s2, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_ashr_i32 s1, s0, 31
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s4, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
ds_load_b32 v3, v2
s_addc_u32 s1, s5, s1
s_ashr_i32 s3, s2, 31
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f32 v0, -v1, v0, v3
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_b32 v0, v2, s[0:1]
ds_load_b32 v1, v2
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v3, null, v0, v0, v1
v_div_scale_f32 v6, vcc_lo, v1, v0, v1
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v3, v0, v1
global_store_b32 v2, v0, s[0:1]
.LBB2_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20BackwardSubstitutionPfS_S_i
.amdhsa_group_segment_fixed_size 4
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20BackwardSubstitutionPfS_S_i, .Lfunc_end2-_Z20BackwardSubstitutionPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13RowOperationsPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13RowOperationsPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19ForwardSubstitutionPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19ForwardSubstitutionPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20BackwardSubstitutionPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z20BackwardSubstitutionPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /** @file
* Name: Parallel LU Decomposition - CUDA Version
* Authored by: Team Segfault
* Description: This program performs Lower/Upper decomposition on a square matrix and
* subsequently solves the associated system of equations with Forward and Backward substitution.
* Implementation Date: 11/23/2020
*/
#include <time.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
bool GetUserInput(int, char *[], int&,int&);
void InitializeMatrices(float **&, float **&, float **&, int);
void InitializeVectors(float *&, float*&, float*&, int);
void PrintMatrix(float **, int);
void PrintVector(float*, int);
void DeleteMatrix(float**,int);
void DeleteVector(float *);
void LUDecomp(float *, float *, int);
__global__ void RowOperations(float *, float *, int, int);
__global__ void ForwardSubstitution(float *, float *, float* , int);
__global__ void BackwardSubstitution(float *, float *, float* , int);
//------------------------------------------------------------------
// Main Program
//------------------------------------------------------------------
int main(int argc, char *argv[]){
srand(time(NULL)); //set the seed
float **a, **lower, **upper; //Matrices
float *b, *x, *y; //Vectors
float *d_lower, *d_upper, *d_b, *d_x, *d_y; //Device pointers
int n,isPrint;
float runtime;
if (!GetUserInput(argc,argv,n,isPrint)) return 1;
// a == upper and lower -> 0
InitializeMatrices(a, lower, upper, n);
InitializeVectors(x, y, b, n);
//Get start time
runtime = clock()/(float)CLOCKS_PER_SEC;
// ######################### BEGIN LU Decomp ##############################3
hipMalloc((void**)&d_lower, n*n*sizeof(float));
hipMalloc((void**)&d_upper, n*n*sizeof(float));
hipMemcpy(d_upper, upper[0], n*n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_lower, lower[0], n*n*sizeof(float), hipMemcpyHostToDevice);
LUDecomp(d_lower, d_upper, n);
hipDeviceSynchronize();
// ######################### END LU Decomp ##############################3
// ######################### BEGIN Substitution ##############################
hipMalloc((void**)&d_b, n*sizeof(float));
hipMalloc((void**)&d_x, n*sizeof(float));
hipMalloc((void**)&d_y, n*sizeof(float));
hipMemcpy(d_b, b, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_x, x, n*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_y, y, n*sizeof(float), hipMemcpyHostToDevice);
dim3 dimGrid(n,1);
dim3 dimBlock(n,1);
ForwardSubstitution<<<dimGrid, dimBlock>>>(d_lower, d_y, d_b, n);
BackwardSubstitution<<<dimGrid, dimBlock>>>(d_upper, d_x, d_y, n);
hipDeviceSynchronize();
// ######################### END Substitution ##############################3
// ######################### BEGIN Copy Back ##############################
hipMemcpy(lower[0],d_lower, n*n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(upper[0],d_upper, n*n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(x,d_x, n*sizeof(float),hipMemcpyDeviceToHost);
hipMemcpy(y,d_y, n*sizeof(float),hipMemcpyDeviceToHost);
// ######################### END Copy Back ##############################
runtime = clock() - runtime; //Make note of time
if(isPrint == 1){
printf("A:\n");
PrintMatrix(a,n);
printf("B:\n");
PrintVector(b,n);
printf("--------------------------------------------------\n");
printf("Lower:\n");
PrintMatrix(lower,n);
printf("Upper:\n");
PrintMatrix(upper,n);
printf("Y:\n");
PrintVector(y,n);
printf("X:\n");
PrintVector(x,n);
}
printf("LU Decomposition and Forward/Backward substitution to solve Ax=B ran in %.2f seconds\n", (runtime)/float(CLOCKS_PER_SEC));
hipFree(d_lower);
hipFree(d_upper);
hipFree(d_b);
hipFree(d_x);
hipFree(d_y);
DeleteMatrix(upper,n);
DeleteMatrix(lower,n);
DeleteMatrix(a,n);
DeleteVector(x);
DeleteVector(y);
DeleteVector(b);
return 0;
}
//------------------------------------------------------------------
// KERNEL DRIVERS
//------------------------------------------------------------------
void LUDecomp(float *d_lower, float *d_upper, int thicness){
int i, numBlocks, numThreads;
for(i = 0; i < thicness; ++i){
// Since all of these are square these are the same.
numBlocks = numThreads = thicness-i;
dim3 dimGrid(numBlocks,1);
dim3 dimBlock(numThreads,1);
RowOperations<<<dimGrid,dimBlock>>>(d_lower, d_upper, i, thicness);
}
}
//------------------------------------------------------------------
// KERNELS
//------------------------------------------------------------------
__global__ void RowOperations(float *lower, float *upper, int i, int thicness){
// Let us get this diagonal thing out of the way
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
lower[ i*thicness + i ] = 1;
int k = blockIdx.x + i + 1;
int j = threadIdx.x + i;
if( !( k < thicness && j < thicness) ) return; // Whoops
__shared__ float pivot;
// And get one pivot per block
if(threadIdx.x == 0)
pivot = -1.0/upper[ i*thicness + i ];
// Hey guys! Wait up!
__syncthreads();
// It is worth noting that the matrices are column major here
lower[k + thicness*i] = upper[k + thicness*i]/upper[i + thicness*i];
upper[k + thicness*j] = upper[k + thicness*j] + pivot*upper[k + thicness*i] * upper[i + thicness*j];
}
__global__ void ForwardSubstitution(float *lower, float *y, float* b, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0) // Last Element
y[0] = b[0] / lower[0];
int i = blockIdx.x + 1;
int j = i - threadIdx.x;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = b[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - lower[ i + thicness*j] * y[j];
// Hey guys! Wait up!
__syncthreads();
y[i] = temp/lower[i + thicness*i];
}
__global__ void BackwardSubstitution(float *upper, float *x, float* y, int thicness){
if(blockIdx.x * blockDim.x + threadIdx.x == 0)
x[thicness - 1] = y[thicness - 1] / upper[(thicness - 1) + thicness*(thicness-1)]; // Last Element
int i = thicness - blockIdx.x - 2;
int j = thicness - i - threadIdx.x - 1;
if( !( i < thicness && j < thicness) || ( j < 0 ) ) return; // Whoops
__shared__ float temp;
if(threadIdx.x == 0)
temp = y[i];
// Hey guys! Wait up!
__syncthreads();
temp = temp - upper[ i + thicness*j] * x[j];
// Hey guys! Wait up!
__syncthreads();
x[i] = temp/upper[i + thicness*i];
}
//------------------------------------------------------------------
// UTILITIES
//------------------------------------------------------------------
// Get user input of matrix dimension and printing option
bool GetUserInput(int argc, char *argv[],int& n,int& isPrint)
{
bool isOK = true;
if(argc < 2)
{
printf("Arguments:<X> [<Y>]");
printf("X : Matrix size [X x X]");
printf("Y = 1: print the input/output matrix if X < 10");
printf("Y <> 1 or missing: does not print the input/output matrix");
isOK = false;
}
else
{
//get matrix size
n = atoi(argv[1]);
if (n <=0)
{
printf("Matrix size must be larger than 0");
isOK = false;
}
//is print the input/output matrix
if (argc >=3)
isPrint = (atoi(argv[2])==1 && n <=9)?1:0;
else
isPrint = 0;
}
return isOK;
}
//delete matrix matrix a[n x n]
void DeleteMatrix(float **a,int n)
{
delete[] a[0];
delete[] a;
}
void DeleteVector(float* x)
{
delete[] x;
}
//Fills matrix A with random values, upper and lower is filled with 0's except for their diagonals
void InitializeMatrices(float **&a, float **&lower, float **&upper, int size){
a = new float*[size];
a[0] = new float[size*size];
for (int i = 1; i < size; i++)
a[i] = a[i-1] + size;
lower = new float*[size];
lower[0] = new float[size*size];
for (int i = 1; i < size; i++)
lower[i] = lower[i-1] + size;
upper = new float*[size];
upper[0] = new float[size*size];
for (int i = 1; i < size; i++)
upper[i] = upper[i-1] + size;
for(int i = 0; i < size; ++i){
for(int j = 0; j < size; ++j){
upper[i][j] = a[i][j] = (rand() % 11) + 1;
lower[i][j] = 0;
}
}
}
void InitializeVectors(float *&x, float *&y, float*& b, int n) {
// allocate square 2d matrix
x = new float[n];
y = new float[n];
b = new float[n];
for (int j = 0 ; j < n ; j++) {
b[j] = (float)(rand() % 11) + 1;
x[j] = y[j] = 0;
}
}
//Print the matrix that was passed to it
void PrintMatrix(float **matrix, int size)
{
for (int i = 0 ; i < size ; i++){
for (int j = 0 ; j < size ; j++){
printf("%.2f\t", matrix[j][i]);
}
printf("\n");
}
}
void PrintVector(float* x, int n)
{
for (int j = 0 ; j < n ; j++) {
printf("%.2f\n", x[j]);
}
} | .text
.file "LU-Decomp-CUDA.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3f800000 # float 1
.LCPI0_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 52(%rsp), %rdx
leaq 172(%rsp), %rcx
movl %ebp, %edi
movq %rbx, %rsi
callq _Z12GetUserInputiPPcRiS1_
movl %eax, %ecx
movl $1, %eax
testb %cl, %cl
je .LBB0_44
# %bb.1:
movslq 52(%rsp), %r13
leaq 184(%rsp), %rdi
leaq 176(%rsp), %rsi
leaq 88(%rsp), %rdx
movl %r13d, %ecx
callq _Z18InitializeMatricesRPPfS1_S1_i
leaq (,%r13,4), %rax
testq %r13, %r13
movq $-1, %r15
movq %rax, 16(%rsp) # 8-byte Spill
cmovnsq %rax, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
movl %r13d, %r12d
movq %r13, 64(%rsp) # 8-byte Spill
testq %r13, %r13
jle .LBB0_4
# %bb.2: # %.lr.ph.preheader.i
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%r15,%r13,4)
movl $0, (%r14,%r13,4)
movl $0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB0_3
.LBB0_4: # %_Z17InitializeVectorsRPfS0_S0_i.exit
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
movq %r15, 72(%rsp) # 8-byte Spill
movq 64(%rsp), %r15 # 8-byte Reload
movl %r15d, %ebp
imull %ebp, %ebp
shlq $2, %rbp
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 88(%rsp), %rax
movq %rax, 224(%rsp) # 8-byte Spill
movq (%rax), %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 176(%rsp), %r13
movq (%r13), %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 32(%rsp), %rsi
movl %r15d, %edx
callq _Z8LUDecompPfS_i
callq hipDeviceSynchronize
leaq 80(%rsp), %rdi
movq 16(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 80(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 160(%rsp), %rax
movq %rax, 192(%rsp)
leaq 152(%rsp), %rax
movq %rax, 200(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z19ForwardSubstitutionPfS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI0_1(%rip), %xmm0
movss %xmm0, 8(%rsp) # 4-byte Spill
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movq 32(%rsp), %rax
movq 56(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
movq 64(%rsp), %rax # 8-byte Reload
movl %eax, 12(%rsp)
leaq 160(%rsp), %rax
movq %rax, 192(%rsp)
leaq 152(%rsp), %rax
movq %rax, 200(%rsp)
leaq 144(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z20BackwardSubstitutionPfS_S_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
callq hipDeviceSynchronize
movq (%r13), %rdi
movq 40(%rsp), %rsi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 224(%rsp), %rax # 8-byte Reload
movq (%rax), %rdi
movq 32(%rsp), %rsi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 56(%rsp), %rsi
movq %rbx, %rdi
movq 16(%rsp), %r15 # 8-byte Reload
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
subss 8(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 8(%rsp) # 4-byte Spill
cmpl $1, 172(%rsp)
jne .LBB0_37
# %bb.9:
movq %r14, 16(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movl 52(%rsp), %r12d
testl %r12d, %r12d
jle .LBB0_17
# %bb.10: # %.preheader.lr.ph.i
movq 184(%rsp), %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_11: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_12 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_12: # Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbp,%r14,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB0_12
# %bb.13: # %._crit_edge.i
# in Loop: Header=BB0_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
cmpq %r12, %r15
jne .LBB0_11
# %bb.14: # %_Z11PrintMatrixPPfi.exit
movl $.Lstr.1, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB0_23
# %bb.15: # %.lr.ph.preheader.i36
xorl %r15d, %r15d
movq 72(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB0_16: # %.lr.ph.i38
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_16
jmp .LBB0_18
.LBB0_17: # %_Z11PrintVectorPfi.exit.critedge
movl $.Lstr.1, %edi
callq puts@PLT
.LBB0_18: # %_Z11PrintVectorPfi.exit
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB0_24
# %bb.19: # %.preheader.lr.ph.i42
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_20: # %.preheader.i44
# =>This Loop Header: Depth=1
# Child Loop BB0_21 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_21: # Parent Loop BB0_20 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r13,%r14,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB0_21
# %bb.22: # %._crit_edge.i50
# in Loop: Header=BB0_20 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
cmpq %r12, %r15
jne .LBB0_20
jmp .LBB0_24
.LBB0_23: # %_Z11PrintMatrixPPfi.exit54.critedge
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
.LBB0_24: # %_Z11PrintMatrixPPfi.exit54
movl $.Lstr.4, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB0_32
# %bb.25: # %.preheader.lr.ph.i55
movq 88(%rsp), %r13
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_26: # %.preheader.i57
# =>This Loop Header: Depth=1
# Child Loop BB0_27 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_27: # Parent Loop BB0_26 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r13,%r14,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB0_27
# %bb.28: # %._crit_edge.i63
# in Loop: Header=BB0_26 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
cmpq %r12, %r15
jne .LBB0_26
# %bb.29: # %_Z11PrintMatrixPPfi.exit67
movl $.Lstr.5, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB0_36
# %bb.30: # %.lr.ph.preheader.i69
xorl %r15d, %r15d
movq 16(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB0_31: # %.lr.ph.i71
# =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_31
jmp .LBB0_33
.LBB0_32: # %_Z11PrintVectorPfi.exit75.critedge
movl $.Lstr.5, %edi
callq puts@PLT
movq 16(%rsp), %r14 # 8-byte Reload
.LBB0_33: # %_Z11PrintVectorPfi.exit75
movl $.Lstr.6, %edi
callq puts@PLT
testl %r12d, %r12d
jle .LBB0_37
# %bb.34: # %.lr.ph.preheader.i77
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_35: # %.lr.ph.i79
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_35
jmp .LBB0_37
.LBB0_36: # %_Z11PrintVectorPfi.exit83.critedge
movl $.Lstr.6, %edi
callq puts@PLT
movq 16(%rsp), %r14 # 8-byte Reload
.LBB0_37: # %_Z11PrintVectorPfi.exit83
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
divss .LCPI0_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 80(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 88(%rsp), %r12
movq (%r12), %rdi
testq %rdi, %rdi
je .LBB0_39
# %bb.38:
callq _ZdaPv
.LBB0_39: # %_Z12DeleteMatrixPPfi.exit
movq %r12, %rdi
callq _ZdaPv
movq 176(%rsp), %r12
movq (%r12), %rdi
testq %rdi, %rdi
movq 72(%rsp), %r15 # 8-byte Reload
je .LBB0_41
# %bb.40:
callq _ZdaPv
.LBB0_41: # %_Z12DeleteMatrixPPfi.exit84
movq %r12, %rdi
callq _ZdaPv
movq 184(%rsp), %r12
movq (%r12), %rdi
testq %rdi, %rdi
je .LBB0_43
# %bb.42:
callq _ZdaPv
.LBB0_43: # %_Z12DeleteMatrixPPfi.exit85
movq %r12, %rdi
callq _ZdaPv
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
.LBB0_44:
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z12GetUserInputiPPcRiS1_ # -- Begin function _Z12GetUserInputiPPcRiS1_
.p2align 4, 0x90
.type _Z12GetUserInputiPPcRiS1_,@function
_Z12GetUserInputiPPcRiS1_: # @_Z12GetUserInputiPPcRiS1_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jg .LBB1_2
# %bb.1:
xorl %ebx, %ebx
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_7
.LBB1_2:
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movl %edi, %ebp
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%r15)
movb $1, %bl
testl %eax, %eax
jle .LBB1_3
# %bb.4:
cmpl $2, %ebp
jne .LBB1_5
.LBB1_6:
movl $0, (%r14)
jmp .LBB1_7
.LBB1_3:
xorl %ebx, %ebx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
cmpl $2, %ebp
je .LBB1_6
.LBB1_5:
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpl $1, %eax
sete %al
cmpl $10, (%r15)
setl %cl
andb %al, %cl
movzbl %cl, %eax
movl %eax, (%r14)
.LBB1_7:
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12GetUserInputiPPcRiS1_, .Lfunc_end1-_Z12GetUserInputiPPcRiS1_
.cfi_endproc
# -- End function
.globl _Z18InitializeMatricesRPPfS1_S1_i # -- Begin function _Z18InitializeMatricesRPPfS1_S1_i
.p2align 4, 0x90
.type _Z18InitializeMatricesRPPfS1_S1_i,@function
_Z18InitializeMatricesRPPfS1_S1_i: # @_Z18InitializeMatricesRPPfS1_S1_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r13d
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movslq %ecx, %r12
leaq (,%r12,8), %rax
testl %r12d, %r12d
movq $-1, %rdi
cmovnsq %rax, %rdi
movq %rdi, 16(%rsp) # 8-byte Spill
callq _Znam
movq %rax, %rbp
movq %rax, (%r15)
movl %r12d, %edi
imull %edi, %edi
shlq $2, %rdi
movq %rdi, 8(%rsp) # 8-byte Spill
callq _Znam
movq %rax, (%rbp)
movl %r13d, 4(%rsp) # 4-byte Spill
movl %r13d, %r13d
cmpl $2, %r12d
jl .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl $1, %eax
leaq (,%r12,4), %rcx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r15), %rdx
movq -8(%rdx,%rax,8), %rsi
addq %rcx, %rsi
movq %rsi, (%rdx,%rax,8)
incq %rax
cmpq %rax, %r13
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq 16(%rsp), %rdi # 8-byte Reload
callq _Znam
movq %rax, %rbp
movq %rax, (%r14)
movq 8(%rsp), %rdi # 8-byte Reload
callq _Znam
movq %rax, (%rbp)
cmpl $2, 4(%rsp) # 4-byte Folded Reload
jl .LBB2_6
# %bb.4: # %.lr.ph62.preheader
movl $1, %eax
leaq (,%r12,4), %rcx
.p2align 4, 0x90
.LBB2_5: # %.lr.ph62
# =>This Inner Loop Header: Depth=1
movq (%r14), %rdx
movq -8(%rdx,%rax,8), %rsi
addq %rcx, %rsi
movq %rsi, (%rdx,%rax,8)
incq %rax
cmpq %rax, %r13
jne .LBB2_5
.LBB2_6: # %._crit_edge63
movq 16(%rsp), %rdi # 8-byte Reload
callq _Znam
movq %rax, %rbp
movq %rax, (%rbx)
movq 8(%rsp), %rdi # 8-byte Reload
callq _Znam
movq %rax, (%rbp)
cmpl $2, 4(%rsp) # 4-byte Folded Reload
jl .LBB2_9
# %bb.7: # %.lr.ph66.preheader
movl $1, %eax
shlq $2, %r12
.p2align 4, 0x90
.LBB2_8: # %.lr.ph66
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rcx
movq -8(%rcx,%rax,8), %rdx
addq %r12, %rdx
movq %rdx, (%rcx,%rax,8)
incq %rax
cmpq %rax, %r13
jne .LBB2_8
.LBB2_9: # %.preheader58
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB2_14
# %bb.10: # %.preheader.lr.ph
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_12 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_12: # Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%r15), %rax
movq (%rax,%r12,8), %rax
movss %xmm0, (%rax,%rbp,4)
movq (%rbx), %rax
movq (%rax,%r12,8), %rax
movss %xmm0, (%rax,%rbp,4)
movq (%r14), %rax
movq (%rax,%r12,8), %rax
movl $0, (%rax,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB2_12
# %bb.13: # %._crit_edge69
# in Loop: Header=BB2_11 Depth=1
incq %r12
cmpq %r13, %r12
jne .LBB2_11
.LBB2_14: # %._crit_edge71
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z18InitializeMatricesRPPfS1_S1_i, .Lfunc_end2-_Z18InitializeMatricesRPPfS1_S1_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17InitializeVectorsRPfS0_S0_i
.LCPI3_0:
.long 0x3f800000 # float 1
.text
.globl _Z17InitializeVectorsRPfS0_S0_i
.p2align 4, 0x90
.type _Z17InitializeVectorsRPfS0_S0_i,@function
_Z17InitializeVectorsRPfS0_S0_i: # @_Z17InitializeVectorsRPfS0_S0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movslq %ecx, %r13
leaq (,%r13,4), %rax
testl %r13d, %r13d
movq $-1, %r12
cmovnsq %rax, %r12
movq %r12, %rdi
callq _Znam
movq %rax, (%r15)
movq %r12, %rdi
callq _Znam
movq %rax, (%r14)
movq %r12, %rdi
callq _Znam
movq %rax, (%rbx)
testl %r13d, %r13d
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
addss .LCPI3_0(%rip), %xmm0
movq (%rbx), %rax
movss %xmm0, (%rax,%r13,4)
movq (%r14), %rax
movl $0, (%rax,%r13,4)
movq (%r15), %rax
movl $0, (%rax,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB3_2
.LBB3_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17InitializeVectorsRPfS0_S0_i, .Lfunc_end3-_Z17InitializeVectorsRPfS0_S0_i
.cfi_endproc
# -- End function
.globl _Z8LUDecompPfS_i # -- Begin function _Z8LUDecompPfS_i
.p2align 4, 0x90
.type _Z8LUDecompPfS_i,@function
_Z8LUDecompPfS_i: # @_Z8LUDecompPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
movl %edx, %ebp
movabsq $4294967296, %r12 # imm = 0x100000000
xorl %r13d, %r13d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
incq %r13
decl %ebx
cmpq %r13, %rbp
je .LBB4_5
.LBB4_2: # =>This Inner Loop Header: Depth=1
movl %ebx, %edi
orq %r12, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %r13d, 12(%rsp)
movl %ebp, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z13RowOperationsPfS_ii, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_4
.LBB4_5:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_6: # %._crit_edge
retq
.Lfunc_end4:
.size _Z8LUDecompPfS_i, .Lfunc_end4-_Z8LUDecompPfS_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__ForwardSubstitutionPfS_S_i # -- Begin function _Z34__device_stub__ForwardSubstitutionPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__ForwardSubstitutionPfS_S_i,@function
_Z34__device_stub__ForwardSubstitutionPfS_S_i: # @_Z34__device_stub__ForwardSubstitutionPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19ForwardSubstitutionPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z34__device_stub__ForwardSubstitutionPfS_S_i, .Lfunc_end5-_Z34__device_stub__ForwardSubstitutionPfS_S_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__BackwardSubstitutionPfS_S_i # -- Begin function _Z35__device_stub__BackwardSubstitutionPfS_S_i
.p2align 4, 0x90
.type _Z35__device_stub__BackwardSubstitutionPfS_S_i,@function
_Z35__device_stub__BackwardSubstitutionPfS_S_i: # @_Z35__device_stub__BackwardSubstitutionPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20BackwardSubstitutionPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z35__device_stub__BackwardSubstitutionPfS_S_i, .Lfunc_end6-_Z35__device_stub__BackwardSubstitutionPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11PrintMatrixPPfi # -- Begin function _Z11PrintMatrixPPfi
.p2align 4, 0x90
.type _Z11PrintMatrixPPfi,@function
_Z11PrintMatrixPPfi: # @_Z11PrintMatrixPPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB7_6
# %bb.1: # %.preheader.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB7_3 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_3: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r12,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %r14
jne .LBB7_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
cmpq %r14, %r15
jne .LBB7_2
# %bb.5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB7_6: # %._crit_edge12
retq
.Lfunc_end7:
.size _Z11PrintMatrixPPfi, .Lfunc_end7-_Z11PrintMatrixPPfi
.cfi_endproc
# -- End function
.globl _Z11PrintVectorPfi # -- Begin function _Z11PrintVectorPfi
.p2align 4, 0x90
.type _Z11PrintVectorPfi,@function
_Z11PrintVectorPfi: # @_Z11PrintVectorPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB8_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB8_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB8_4: # %._crit_edge
retq
.Lfunc_end8:
.size _Z11PrintVectorPfi, .Lfunc_end8-_Z11PrintVectorPfi
.cfi_endproc
# -- End function
.globl _Z12DeleteMatrixPPfi # -- Begin function _Z12DeleteMatrixPPfi
.p2align 4, 0x90
.type _Z12DeleteMatrixPPfi,@function
_Z12DeleteMatrixPPfi: # @_Z12DeleteMatrixPPfi
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
testq %rax, %rax
je _ZdaPv # TAILCALL
# %bb.1:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq %rax, %rdi
callq _ZdaPv
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
jmp _ZdaPv # TAILCALL
.Lfunc_end9:
.size _Z12DeleteMatrixPPfi, .Lfunc_end9-_Z12DeleteMatrixPPfi
.cfi_endproc
# -- End function
.globl _Z12DeleteVectorPf # -- Begin function _Z12DeleteVectorPf
.p2align 4, 0x90
.type _Z12DeleteVectorPf,@function
_Z12DeleteVectorPf: # @_Z12DeleteVectorPf
.cfi_startproc
# %bb.0:
testq %rdi, %rdi
jne _ZdaPv # TAILCALL
# %bb.1:
retq
.Lfunc_end10:
.size _Z12DeleteVectorPf, .Lfunc_end10-_Z12DeleteVectorPf
.cfi_endproc
# -- End function
.globl _Z28__device_stub__RowOperationsPfS_ii # -- Begin function _Z28__device_stub__RowOperationsPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__RowOperationsPfS_ii,@function
_Z28__device_stub__RowOperationsPfS_ii: # @_Z28__device_stub__RowOperationsPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13RowOperationsPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end11:
.size _Z28__device_stub__RowOperationsPfS_ii, .Lfunc_end11-_Z28__device_stub__RowOperationsPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB12_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB12_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13RowOperationsPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19ForwardSubstitutionPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20BackwardSubstitutionPfS_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end12:
.size __hip_module_ctor, .Lfunc_end12-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB13_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB13_2:
retq
.Lfunc_end13:
.size __hip_module_dtor, .Lfunc_end13-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19ForwardSubstitutionPfS_S_i,@object # @_Z19ForwardSubstitutionPfS_S_i
.section .rodata,"a",@progbits
.globl _Z19ForwardSubstitutionPfS_S_i
.p2align 3, 0x0
_Z19ForwardSubstitutionPfS_S_i:
.quad _Z34__device_stub__ForwardSubstitutionPfS_S_i
.size _Z19ForwardSubstitutionPfS_S_i, 8
.type _Z20BackwardSubstitutionPfS_S_i,@object # @_Z20BackwardSubstitutionPfS_S_i
.globl _Z20BackwardSubstitutionPfS_S_i
.p2align 3, 0x0
_Z20BackwardSubstitutionPfS_S_i:
.quad _Z35__device_stub__BackwardSubstitutionPfS_S_i
.size _Z20BackwardSubstitutionPfS_S_i, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "LU Decomposition and Forward/Backward substitution to solve Ax=B ran in %.2f seconds\n"
.size .L.str.7, 86
.type _Z13RowOperationsPfS_ii,@object # @_Z13RowOperationsPfS_ii
.section .rodata,"a",@progbits
.globl _Z13RowOperationsPfS_ii
.p2align 3, 0x0
_Z13RowOperationsPfS_ii:
.quad _Z28__device_stub__RowOperationsPfS_ii
.size _Z13RowOperationsPfS_ii, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "Arguments:<X> [<Y>]"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "X : Matrix size [X x X]"
.size .L.str.9, 24
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Y = 1: print the input/output matrix if X < 10"
.size .L.str.10, 47
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Y <> 1 or missing: does not print the input/output matrix"
.size .L.str.11, 58
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Matrix size must be larger than 0"
.size .L.str.12, 34
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "%.2f\t"
.size .L.str.13, 6
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "%.2f\n"
.size .L.str.15, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13RowOperationsPfS_ii"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19ForwardSubstitutionPfS_S_i"
.size .L__unnamed_2, 31
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20BackwardSubstitutionPfS_S_i"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "A:"
.size .Lstr, 3
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "B:"
.size .Lstr.1, 3
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "--------------------------------------------------"
.size .Lstr.2, 51
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Lower:"
.size .Lstr.3, 7
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Upper:"
.size .Lstr.4, 7
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Y:"
.size .Lstr.5, 3
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "X:"
.size .Lstr.6, 3
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__ForwardSubstitutionPfS_S_i
.addrsig_sym _Z35__device_stub__BackwardSubstitutionPfS_S_i
.addrsig_sym _Z28__device_stub__RowOperationsPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19ForwardSubstitutionPfS_S_i
.addrsig_sym _Z20BackwardSubstitutionPfS_S_i
.addrsig_sym _Z13RowOperationsPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <vector>
#include <thrust/device_vector.h>
#include <thrust/sequence.h>
#include <thrust/sort.h>
// #define SIGN(x) ((x) > 0 ? 1 : ((x) ? -1 : 0))
#define CSC(call) \
do { \
cudaError_t res = call; \
if (res != cudaSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, cudaGetErrorString(res)); \
exit(0); \
} \
} while(0)
using namespace std;
#define co1 1.8
#define co2 2.8
__host__ __device__ double fun(double x) {
return tan(co1 * x) - co2 * x;
}
__host__ __device__ double pi(void) {
return M_PI / co1;
}
__device__ double bisection(double left, double right, double eps, int limit = 1000000) {
double mid = 0;
double fl = fun(left);
double fr = fun(right);
while (right - left > eps && abs(right - left) > abs(eps) && limit) {
double fm;
limit--;
mid = (left + right) / 2;
fm = fun(mid);
// cout << left << "' '" << mid << " " << right << endl;
// cout << fl << " " << fm << " " << fr << endl;
// cout << endl;
if (fm) {
// если одинак знак с левого края и по середине
if (fm * fl > 0) {
fl = fm;
left = mid;
}
// если одинак знак с правого края и по середине
if (fm * fr > 0) {
fr = fm;
right = mid;
}
}
else
break;
}
return mid;
}
__global__
void caller(double *borders, double *results, double eps) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
results[idx] = bisection(borders[idx] + eps, borders[idx + 1] - eps, eps);
}
int main(void) {
double left, right, eps;
cout << "l, r, e: ";
cin >> left >> right >> eps;
cudaEvent_t start, end;
bool has_zero = false;
if (eps > 0.0001)
cout << "Epsilon is too big" << endl;
// next, we kinda wanna to find all the tear points, don't we?
double tear = floor(left / pi()) * pi() - pi() / 2;
has_zero = left < 0 && right > 0;
int size = (right + pi() - left) / pi() + 2;
if (has_zero)
size += 2;
thrust::device_vector<double> tear_points(size);
thrust::device_vector<double> results (size - 1);
thrust::sequence(tear_points.begin(), tear_points.end(), tear, pi());
if (has_zero) {
tear_points[size - 1] = 0 - 100 * eps;
tear_points[size - 2] = 0 + 100 * eps;
thrust::sort(tear_points.begin(), tear_points.end());
}
// we should add 0 as break point, otherwise there are 3 roots in there
cout << "Size: " << size << endl;
cout << "Called the kernel" << endl;
//~ for (int i = 0; i < tear_points.size(); ++i)
//~ cout << tear_points[i] << endl;
CSC(cudaEventCreate(&start));
CSC(cudaEventCreate(&end ));
CSC(cudaEventRecord( start));
caller<<<1, size - 1>>>(
thrust::raw_pointer_cast(tear_points.data()),
thrust::raw_pointer_cast(results.data()),
eps
);
CSC(cudaGetLastError());
CSC(cudaEventRecord (end));
CSC(cudaEventSynchronize(end));
float t;
CSC(cudaEventElapsedTime(&t, start, end));
CSC(cudaEventDestroy(start));
CSC(cudaEventDestroy(end));
cout << "Results: " << endl;
for (int i = 1; i < results.size(); ++i) {
double m = results[i];
if (m > left && m < right) {
cout << "Interval: [" << tear_points[i] << ", " << tear_points[i + 1] << "]" << endl;
cout << "fun(" << m << ") = " << fun(m) << "\t (" << (int)fun(m) << ")" << endl;
cout << endl;
}
}
cout << "Time: " << t << endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <vector>
#include <thrust/device_vector.h>
#include <thrust/sequence.h>
#include <thrust/sort.h>
// #define SIGN(x) ((x) > 0 ? 1 : ((x) ? -1 : 0))
#define CSC(call) \
do { \
hipError_t res = call; \
if (res != hipSuccess) { \
fprintf(stderr, "ERROR in %s:%d. Message: %s\n", \
__FILE__, __LINE__, hipGetErrorString(res)); \
exit(0); \
} \
} while(0)
using namespace std;
#define co1 1.8
#define co2 2.8
__host__ __device__ double fun(double x) {
return tan(co1 * x) - co2 * x;
}
__host__ __device__ double pi(void) {
return M_PI / co1;
}
__device__ double bisection(double left, double right, double eps, int limit = 1000000) {
double mid = 0;
double fl = fun(left);
double fr = fun(right);
while (right - left > eps && abs(right - left) > abs(eps) && limit) {
double fm;
limit--;
mid = (left + right) / 2;
fm = fun(mid);
// cout << left << "' '" << mid << " " << right << endl;
// cout << fl << " " << fm << " " << fr << endl;
// cout << endl;
if (fm) {
// если одинак знак с левого края и по середине
if (fm * fl > 0) {
fl = fm;
left = mid;
}
// если одинак знак с правого края и по середине
if (fm * fr > 0) {
fr = fm;
right = mid;
}
}
else
break;
}
return mid;
}
__global__
void caller(double *borders, double *results, double eps) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
results[idx] = bisection(borders[idx] + eps, borders[idx + 1] - eps, eps);
}
int main(void) {
double left, right, eps;
cout << "l, r, e: ";
cin >> left >> right >> eps;
hipEvent_t start, end;
bool has_zero = false;
if (eps > 0.0001)
cout << "Epsilon is too big" << endl;
// next, we kinda wanna to find all the tear points, don't we?
double tear = floor(left / pi()) * pi() - pi() / 2;
has_zero = left < 0 && right > 0;
int size = (right + pi() - left) / pi() + 2;
if (has_zero)
size += 2;
thrust::device_vector<double> tear_points(size);
thrust::device_vector<double> results (size - 1);
thrust::sequence(tear_points.begin(), tear_points.end(), tear, pi());
if (has_zero) {
tear_points[size - 1] = 0 - 100 * eps;
tear_points[size - 2] = 0 + 100 * eps;
thrust::sort(tear_points.begin(), tear_points.end());
}
// we should add 0 as break point, otherwise there are 3 roots in there
cout << "Size: " << size << endl;
cout << "Called the kernel" << endl;
//~ for (int i = 0; i < tear_points.size(); ++i)
//~ cout << tear_points[i] << endl;
CSC(hipEventCreate(&start));
CSC(hipEventCreate(&end ));
CSC(hipEventRecord( start));
caller<<<1, size - 1>>>(
thrust::raw_pointer_cast(tear_points.data()),
thrust::raw_pointer_cast(results.data()),
eps
);
CSC(hipGetLastError());
CSC(hipEventRecord (end));
CSC(hipEventSynchronize(end));
float t;
CSC(hipEventElapsedTime(&t, start, end));
CSC(hipEventDestroy(start));
CSC(hipEventDestroy(end));
cout << "Results: " << endl;
for (int i = 1; i < results.size(); ++i) {
double m = results[i];
if (m > left && m < right) {
cout << "Interval: [" << tear_points[i] << ", " << tear_points[i + 1] << "]" << endl;
cout << "fun(" << m << ") = " << fun(m) << "\t (" << (int)fun(m) << ")" << endl;
cout << endl;
}
}
cout << "Time: " << t << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define THREADS_PER_BLOCK 256
#define CHUNK_SIZE 16
// flag if the prng has been seeded
int randNotSeeded = 1;
// tests the gpu merge sort
__device__ void insertionSort(int *array, int a, int b)
{
int current;
for (int i = a + 1; i < b; i++)
{
current = array[i];
for (int j = i - 1; j >= a - 1; j--)
{
if (j == a - 1 || current > array[j])
{
array[j + 1] = current;
break;
}
else
{
array[j + 1] = array[j];
}
}
}
}
__global__ void gpu_sort(int *d_array, int size, int chunkSize)
{
// Figure out left and right for this thread
int a = (threadIdx.x + blockDim.x * blockIdx.x) * chunkSize;
if (a >= size) return;
int b = a + chunkSize;
if (b > size) b = size;
insertionSort(d_array, a, b);
} | code for sm_80
Function : _Z8gpu_sortPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R2, R0.reuse, c[0x0][0x16c], RZ ; /* 0x00005b0000027a10 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R3, R0, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x000fe40007ffe0ff */
/*0090*/ IMNMX R6, R2, c[0x0][0x168], PT ; /* 0x00005a0002067a17 */
/* 0x000fc80003800200 */
/*00a0*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R7, R0, -0x1, RZ ; /* 0xffffffff00077810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0000 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00f0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe20003f06270 */
/*0100*/ BSSY B0, 0x270 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fd200078e0003 */
/*0130*/ @!P0 BRA 0x260 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*0160*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000162000c1e1900 */
/*0170*/ ISETP.NE.AND P0, PT, R10.reuse, R7, PT ; /* 0x000000070a00720c */
/* 0x040fe20003f05270 */
/*0180*/ IMAD.WIDE R4, R10, R4, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fd800078e0204 */
/*0190*/ @!P0 BRA 0x250 ; /* 0x000000b000008947 */
/* 0x001fea0003800000 */
/*01a0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x024fda0003f04270 */
/*01c0*/ @P0 BRA 0x250 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*01d0*/ STG.E [R4.64+0x4], R2 ; /* 0x0000040204007986 */
/* 0x0001e2000c101904 */
/*01e0*/ ISETP.GE.AND P0, PT, R10, R0, PT ; /* 0x000000000a00720c */
/* 0x000fda0003f06270 */
/*01f0*/ @!P0 BRA 0x260 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x001fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0220*/ ISETP.NE.AND P0, PT, R10.reuse, R7, PT ; /* 0x000000070a00720c */
/* 0x040fe20003f05270 */
/*0230*/ IMAD.WIDE R4, R10, R5, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fd800078e0205 */
/*0240*/ @P0 BRA 0x1a0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0250*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x0201e4000c101904 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0270*/ IADD3 R3, R8, 0x1, RZ ; /* 0x0000000108037810 */
/* 0x000fc80007ffe0ff */
/*0280*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0290*/ @!P0 BRA 0xf0 ; /* 0xfffffe5000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define THREADS_PER_BLOCK 256
#define CHUNK_SIZE 16
// flag if the prng has been seeded
int randNotSeeded = 1;
// tests the gpu merge sort
__device__ void insertionSort(int *array, int a, int b)
{
int current;
for (int i = a + 1; i < b; i++)
{
current = array[i];
for (int j = i - 1; j >= a - 1; j--)
{
if (j == a - 1 || current > array[j])
{
array[j + 1] = current;
break;
}
else
{
array[j + 1] = array[j];
}
}
}
}
__global__ void gpu_sort(int *d_array, int size, int chunkSize)
{
// Figure out left and right for this thread
int a = (threadIdx.x + blockDim.x * blockIdx.x) * chunkSize;
if (a >= size) return;
int b = a + chunkSize;
if (b > size) b = size;
insertionSort(d_array, a, b);
} | .file "tmpxft_000a9d24_00000000-6_gpu_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13insertionSortPiii
.type _Z13insertionSortPiii, @function
_Z13insertionSortPiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13insertionSortPiii, .-_Z13insertionSortPiii
.globl _Z29__device_stub__Z8gpu_sortPiiiPiii
.type _Z29__device_stub__Z8gpu_sortPiiiPiii, @function
_Z29__device_stub__Z8gpu_sortPiiiPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_sortPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z29__device_stub__Z8gpu_sortPiiiPiii, .-_Z29__device_stub__Z8gpu_sortPiiiPiii
.globl _Z8gpu_sortPiii
.type _Z8gpu_sortPiii, @function
_Z8gpu_sortPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpu_sortPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8gpu_sortPiii, .-_Z8gpu_sortPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8gpu_sortPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_sortPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl randNotSeeded
.data
.align 4
.type randNotSeeded, @object
.size randNotSeeded, 4
randNotSeeded:
.long 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define THREADS_PER_BLOCK 256
#define CHUNK_SIZE 16
// flag if the prng has been seeded
int randNotSeeded = 1;
// tests the gpu merge sort
__device__ void insertionSort(int *array, int a, int b)
{
int current;
for (int i = a + 1; i < b; i++)
{
current = array[i];
for (int j = i - 1; j >= a - 1; j--)
{
if (j == a - 1 || current > array[j])
{
array[j + 1] = current;
break;
}
else
{
array[j + 1] = array[j];
}
}
}
}
__global__ void gpu_sort(int *d_array, int size, int chunkSize)
{
// Figure out left and right for this thread
int a = (threadIdx.x + blockDim.x * blockIdx.x) * chunkSize;
if (a >= size) return;
int b = a + chunkSize;
if (b > size) b = size;
insertionSort(d_array, a, b);
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define THREADS_PER_BLOCK 256
#define CHUNK_SIZE 16
// flag if the prng has been seeded
int randNotSeeded = 1;
// tests the gpu merge sort
__device__ void insertionSort(int *array, int a, int b)
{
int current;
for (int i = a + 1; i < b; i++)
{
current = array[i];
for (int j = i - 1; j >= a - 1; j--)
{
if (j == a - 1 || current > array[j])
{
array[j + 1] = current;
break;
}
else
{
array[j + 1] = array[j];
}
}
}
}
__global__ void gpu_sort(int *d_array, int size, int chunkSize)
{
// Figure out left and right for this thread
int a = (threadIdx.x + blockDim.x * blockIdx.x) * chunkSize;
if (a >= size) return;
int b = a + chunkSize;
if (b > size) b = size;
insertionSort(d_array, a, b);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define THREADS_PER_BLOCK 256
#define CHUNK_SIZE 16
// flag if the prng has been seeded
int randNotSeeded = 1;
// tests the gpu merge sort
__device__ void insertionSort(int *array, int a, int b)
{
int current;
for (int i = a + 1; i < b; i++)
{
current = array[i];
for (int j = i - 1; j >= a - 1; j--)
{
if (j == a - 1 || current > array[j])
{
array[j + 1] = current;
break;
}
else
{
array[j + 1] = array[j];
}
}
}
}
__global__ void gpu_sort(int *d_array, int size, int chunkSize)
{
// Figure out left and right for this thread
int a = (threadIdx.x + blockDim.x * blockIdx.x) * chunkSize;
if (a >= size) return;
int b = a + chunkSize;
if (b > size) b = size;
insertionSort(d_array, a, b);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_sortPiii
.globl _Z8gpu_sortPiii
.p2align 8
.type _Z8gpu_sortPiii,@function
_Z8gpu_sortPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_mul_lo_u32 v7, v1, s3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v7
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v0, s3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_min_i32_e32 v8, s2, v0
v_add_nc_u32_e32 v0, 1, v7
v_cmp_lt_i32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, v7 :: v_dual_add_nc_u32 v9, -1, v7
s_mov_b32 s1, -1
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, 4
s_addc_u32 s5, s3, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v0, 1, v0
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s1, s1, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_14
.LBB0_4:
s_mov_b32 s7, exec_lo
v_cmpx_ge_i32_e64 v2, v9
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s8, 0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v1, v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_6:
.LBB0_7:
s_and_b32 s12, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s12, s8
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s12, s11, exec_lo
s_or_b32 s9, s9, s12
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_12
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
s_or_b32 s11, s11, exec_lo
s_or_b32 s0, s0, exec_lo
s_cmp_eq_u32 s1, s10
s_cbranch_scc1 .LBB0_6
global_load_b32 v10, v[3:4], off offset:-4
s_mov_b32 s0, -1
s_mov_b32 s13, -1
s_mov_b32 s12, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 v1, v10
s_cbranch_execz .LBB0_11
s_add_i32 s10, s10, -1
s_xor_b32 s13, exec_lo, -1
v_add_nc_u32_e32 v5, s10, v0
global_store_b32 v[3:4], v10, off
v_cmp_lt_i32_e32 vcc_lo, v5, v7
v_add_co_u32 v5, s0, v3, -4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, -1, v4, s0
s_or_not1_b32 s0, vcc_lo, exec_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s12, s13, exec_lo
s_or_b32 s11, s11, s12
s_branch .LBB0_7
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s0, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v1, off
s_branch .LBB0_3
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_sortPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_sortPiii, .Lfunc_end0-_Z8gpu_sortPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_sortPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8gpu_sortPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define THREADS_PER_BLOCK 256
#define CHUNK_SIZE 16
// flag if the prng has been seeded
int randNotSeeded = 1;
// tests the gpu merge sort
__device__ void insertionSort(int *array, int a, int b)
{
int current;
for (int i = a + 1; i < b; i++)
{
current = array[i];
for (int j = i - 1; j >= a - 1; j--)
{
if (j == a - 1 || current > array[j])
{
array[j + 1] = current;
break;
}
else
{
array[j + 1] = array[j];
}
}
}
}
__global__ void gpu_sort(int *d_array, int size, int chunkSize)
{
// Figure out left and right for this thread
int a = (threadIdx.x + blockDim.x * blockIdx.x) * chunkSize;
if (a >= size) return;
int b = a + chunkSize;
if (b > size) b = size;
insertionSort(d_array, a, b);
} | .text
.file "gpu_sort.hip"
.globl _Z23__device_stub__gpu_sortPiii # -- Begin function _Z23__device_stub__gpu_sortPiii
.p2align 4, 0x90
.type _Z23__device_stub__gpu_sortPiii,@function
_Z23__device_stub__gpu_sortPiii: # @_Z23__device_stub__gpu_sortPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_sortPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_sortPiii, .Lfunc_end0-_Z23__device_stub__gpu_sortPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_sortPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type randNotSeeded,@object # @randNotSeeded
.data
.globl randNotSeeded
.p2align 2, 0x0
randNotSeeded:
.long 1 # 0x1
.size randNotSeeded, 4
.type _Z8gpu_sortPiii,@object # @_Z8gpu_sortPiii
.section .rodata,"a",@progbits
.globl _Z8gpu_sortPiii
.p2align 3, 0x0
_Z8gpu_sortPiii:
.quad _Z23__device_stub__gpu_sortPiii
.size _Z8gpu_sortPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8gpu_sortPiii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_sortPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_sortPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8gpu_sortPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0040*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x000fca00078e02ff */
/*0050*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R2, R0.reuse, c[0x0][0x16c], RZ ; /* 0x00005b0000027a10 */
/* 0x040fe40007ffe0ff */
/*0080*/ IADD3 R3, R0, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x000fe40007ffe0ff */
/*0090*/ IMNMX R6, R2, c[0x0][0x168], PT ; /* 0x00005a0002067a17 */
/* 0x000fc80003800200 */
/*00a0*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R7, R0, -0x1, RZ ; /* 0xffffffff00077810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0000 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00f0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe20003f06270 */
/*0100*/ BSSY B0, 0x270 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R10, RZ, RZ, R8 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0008 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fd200078e0003 */
/*0130*/ @!P0 BRA 0x260 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0204 */
/*0160*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000162000c1e1900 */
/*0170*/ ISETP.NE.AND P0, PT, R10.reuse, R7, PT ; /* 0x000000070a00720c */
/* 0x040fe20003f05270 */
/*0180*/ IMAD.WIDE R4, R10, R4, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fd800078e0204 */
/*0190*/ @!P0 BRA 0x250 ; /* 0x000000b000008947 */
/* 0x001fea0003800000 */
/*01a0*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ ISETP.GT.AND P0, PT, R3, R2, PT ; /* 0x000000020300720c */
/* 0x024fda0003f04270 */
/*01c0*/ @P0 BRA 0x250 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*01d0*/ STG.E [R4.64+0x4], R2 ; /* 0x0000040204007986 */
/* 0x0001e2000c101904 */
/*01e0*/ ISETP.GE.AND P0, PT, R10, R0, PT ; /* 0x000000000a00720c */
/* 0x000fda0003f06270 */
/*01f0*/ @!P0 BRA 0x260 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0200*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x001fe20007ffe0ff */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0220*/ ISETP.NE.AND P0, PT, R10.reuse, R7, PT ; /* 0x000000070a00720c */
/* 0x040fe20003f05270 */
/*0230*/ IMAD.WIDE R4, R10, R5, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fd800078e0205 */
/*0240*/ @P0 BRA 0x1a0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0250*/ STG.E [R4.64+0x4], R3 ; /* 0x0000040304007986 */
/* 0x0201e4000c101904 */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0270*/ IADD3 R3, R8, 0x1, RZ ; /* 0x0000000108037810 */
/* 0x000fc80007ffe0ff */
/*0280*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0290*/ @!P0 BRA 0xf0 ; /* 0xfffffe5000008947 */
/* 0x000fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_sortPiii
.globl _Z8gpu_sortPiii
.p2align 8
.type _Z8gpu_sortPiii,@function
_Z8gpu_sortPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_mul_lo_u32 v7, v1, s3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v7
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v0, s3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_min_i32_e32 v8, s2, v0
v_add_nc_u32_e32 v0, 1, v7
v_cmp_lt_i32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_14
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, v7 :: v_dual_add_nc_u32 v9, -1, v7
s_mov_b32 s1, -1
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, 4
s_addc_u32 s5, s3, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v0, 1, v0
v_add_nc_u32_e32 v2, 1, v2
s_add_i32 s1, s1, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_14
.LBB0_4:
s_mov_b32 s7, exec_lo
v_cmpx_ge_i32_e64 v2, v9
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s8, 0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v1, v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_6:
.LBB0_7:
s_and_b32 s12, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s8, s12, s8
s_and_not1_b32 s9, s9, exec_lo
s_and_b32 s12, s11, exec_lo
s_or_b32 s9, s9, s12
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_12
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, v5 :: v_dual_mov_b32 v4, v6
s_or_b32 s11, s11, exec_lo
s_or_b32 s0, s0, exec_lo
s_cmp_eq_u32 s1, s10
s_cbranch_scc1 .LBB0_6
global_load_b32 v10, v[3:4], off offset:-4
s_mov_b32 s0, -1
s_mov_b32 s13, -1
s_mov_b32 s12, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 v1, v10
s_cbranch_execz .LBB0_11
s_add_i32 s10, s10, -1
s_xor_b32 s13, exec_lo, -1
v_add_nc_u32_e32 v5, s10, v0
global_store_b32 v[3:4], v10, off
v_cmp_lt_i32_e32 vcc_lo, v5, v7
v_add_co_u32 v5, s0, v3, -4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, -1, v4, s0
s_or_not1_b32 s0, vcc_lo, exec_lo
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s12, s13, exec_lo
s_or_b32 s11, s11, s12
s_branch .LBB0_7
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
s_and_saveexec_b32 s0, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_3
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v1, off
s_branch .LBB0_3
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_sortPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_sortPiii, .Lfunc_end0-_Z8gpu_sortPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_sortPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8gpu_sortPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a9d24_00000000-6_gpu_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13insertionSortPiii
.type _Z13insertionSortPiii, @function
_Z13insertionSortPiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13insertionSortPiii, .-_Z13insertionSortPiii
.globl _Z29__device_stub__Z8gpu_sortPiiiPiii
.type _Z29__device_stub__Z8gpu_sortPiiiPiii, @function
_Z29__device_stub__Z8gpu_sortPiiiPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_sortPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z29__device_stub__Z8gpu_sortPiiiPiii, .-_Z29__device_stub__Z8gpu_sortPiiiPiii
.globl _Z8gpu_sortPiii
.type _Z8gpu_sortPiii, @function
_Z8gpu_sortPiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpu_sortPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8gpu_sortPiii, .-_Z8gpu_sortPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8gpu_sortPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_sortPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl randNotSeeded
.data
.align 4
.type randNotSeeded, @object
.size randNotSeeded, 4
randNotSeeded:
.long 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_sort.hip"
.globl _Z23__device_stub__gpu_sortPiii # -- Begin function _Z23__device_stub__gpu_sortPiii
.p2align 4, 0x90
.type _Z23__device_stub__gpu_sortPiii,@function
_Z23__device_stub__gpu_sortPiii: # @_Z23__device_stub__gpu_sortPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_sortPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_sortPiii, .Lfunc_end0-_Z23__device_stub__gpu_sortPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_sortPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type randNotSeeded,@object # @randNotSeeded
.data
.globl randNotSeeded
.p2align 2, 0x0
randNotSeeded:
.long 1 # 0x1
.size randNotSeeded, 4
.type _Z8gpu_sortPiii,@object # @_Z8gpu_sortPiii
.section .rodata,"a",@progbits
.globl _Z8gpu_sortPiii
.p2align 3, 0x0
_Z8gpu_sortPiii:
.quad _Z23__device_stub__gpu_sortPiii
.size _Z8gpu_sortPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8gpu_sortPiii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_sortPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_sortPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
// Host input vectors.
float *uva_a;
float *uva_b;
// Host output vector.
float *uva_c;
// Size of arrays.
int n = 0;
/* CUDA kernel. Each thread takes care of one element of c. */
__global__ void vecAdd(float *a, float *b, float *c, int n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
void init_array() {
fprintf(stdout, "Inicializando os arrays.\n");
int i;
// Initialize vectors on host.
for (i = 0; i < n; i++) {
uva_a[i] = sinf(i) * sinf(i);
uva_b[i] = cosf(i) * cosf(i);
}
}
void print_array() {
int i;
printf("Imprimindo o Resultado.\n");
for (i = 0; i < n; i++) {
fprintf(stdout, "uva_c[%07d]: %f\n", i, uva_c[i]);
}
}
void check_result(){
// Soma dos elementos do array C e divide por N, o valor deve ser igual a 1.
int i;
float sum = 0;
fprintf(stdout, "Verificando o Resultado.\n");
for (i = 0; i < n; i++) {
sum += uva_c[i];
}
fprintf(stdout, "Resultado Final: (%f, %f)\n", sum, (float)(sum / (float)n));
}
/* Main code */
int main(int argc, char *argv[]) {
// Size of vectors
n = atoi(argv[1]);
printf("Número de Elementos: %d\n", n);
// Size, in bytes, of each vector
size_t bytes = n * sizeof(float);
printf("Memória que será alocada para os 3 arrays: %d\n", 3 * bytes);
printf("Allocate memory for each vector on host\n");
// Allocate memory for each vector on host
cudaMallocManaged(&uva_a, bytes);
cudaMallocManaged(&uva_b, bytes);
cudaMallocManaged(&uva_c, bytes);
printf("Initialize vectors on host\n");
init_array();
// Number of threads in each thread block.
int threadsPerBlock = 256;
// Number of thread blocks in grid.
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("Execute the kernel\n");
cudaEvent_t start_event, stop_event;
float time_kernel_execution;
int eventflags = cudaEventBlockingSync;
cudaEventCreateWithFlags(&start_event, eventflags);
cudaEventCreateWithFlags(&stop_event, eventflags);
/* Recording the time to kernel execution */
cudaEventRecord(start_event, 0);
/* Execute the kernel. */
vecAdd <<< blocksPerGrid, threadsPerBlock >>> (uva_a, uva_b, uva_c, n);
/* Synchronize */
cudaDeviceSynchronize();
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time_kernel_execution, start_event, stop_event);
printf("Time Kernel Execution: %f s\n", (time_kernel_execution / 1000.0f));
print_array();
check_result();
printf("Time Kernel Execution: %f ms\n", (time_kernel_execution));
// Release device memory
cudaFree(uva_a);
cudaFree(uva_b);
cudaFree(uva_c);
return 0;
} | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
// Host input vectors.
float *uva_a;
float *uva_b;
// Host output vector.
float *uva_c;
// Size of arrays.
int n = 0;
/* CUDA kernel. Each thread takes care of one element of c. */
__global__ void vecAdd(float *a, float *b, float *c, int n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
void init_array() {
fprintf(stdout, "Inicializando os arrays.\n");
int i;
// Initialize vectors on host.
for (i = 0; i < n; i++) {
uva_a[i] = sinf(i) * sinf(i);
uva_b[i] = cosf(i) * cosf(i);
}
}
void print_array() {
int i;
printf("Imprimindo o Resultado.\n");
for (i = 0; i < n; i++) {
fprintf(stdout, "uva_c[%07d]: %f\n", i, uva_c[i]);
}
}
void check_result(){
// Soma dos elementos do array C e divide por N, o valor deve ser igual a 1.
int i;
float sum = 0;
fprintf(stdout, "Verificando o Resultado.\n");
for (i = 0; i < n; i++) {
sum += uva_c[i];
}
fprintf(stdout, "Resultado Final: (%f, %f)\n", sum, (float)(sum / (float)n));
}
/* Main code */
int main(int argc, char *argv[]) {
// Size of vectors
n = atoi(argv[1]);
printf("Número de Elementos: %d\n", n);
// Size, in bytes, of each vector
size_t bytes = n * sizeof(float);
printf("Memória que será alocada para os 3 arrays: %d\n", 3 * bytes);
printf("Allocate memory for each vector on host\n");
// Allocate memory for each vector on host
cudaMallocManaged(&uva_a, bytes);
cudaMallocManaged(&uva_b, bytes);
cudaMallocManaged(&uva_c, bytes);
printf("Initialize vectors on host\n");
init_array();
// Number of threads in each thread block.
int threadsPerBlock = 256;
// Number of thread blocks in grid.
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("Execute the kernel\n");
cudaEvent_t start_event, stop_event;
float time_kernel_execution;
int eventflags = cudaEventBlockingSync;
cudaEventCreateWithFlags(&start_event, eventflags);
cudaEventCreateWithFlags(&stop_event, eventflags);
/* Recording the time to kernel execution */
cudaEventRecord(start_event, 0);
/* Execute the kernel. */
vecAdd <<< blocksPerGrid, threadsPerBlock >>> (uva_a, uva_b, uva_c, n);
/* Synchronize */
cudaDeviceSynchronize();
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time_kernel_execution, start_event, stop_event);
printf("Time Kernel Execution: %f s\n", (time_kernel_execution / 1000.0f));
print_array();
check_result();
printf("Time Kernel Execution: %f ms\n", (time_kernel_execution));
// Release device memory
cudaFree(uva_a);
cudaFree(uva_b);
cudaFree(uva_c);
return 0;
} | .file "tmpxft_000259a3_00000000-6_vectoradd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Inicializando os arrays.\n"
.text
.globl _Z10init_arrayv
.type _Z10init_arrayv, @function
_Z10init_arrayv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $0, n(%rip)
jle .L3
movl $0, %ebx
leaq 12(%rsp), %rbp
.L5:
leaq 8(%rsp), %rsi
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movq %rbp, %rdi
call sincosf@PLT
movss 8(%rsp), %xmm0
movss 12(%rsp), %xmm1
mulss %xmm1, %xmm1
movq uva_a(%rip), %rax
movss %xmm1, (%rax,%rbx,4)
mulss %xmm0, %xmm0
movq uva_b(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, n(%rip)
jg .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10init_arrayv, .-_Z10init_arrayv
.section .rodata.str1.1
.LC1:
.string "Imprimindo o Resultado.\n"
.LC2:
.string "uva_c[%07d]: %f\n"
.text
.globl _Z11print_arrayv
.type _Z11print_arrayv, @function
_Z11print_arrayv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, n(%rip)
jle .L8
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L10:
movq uva_c(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %ecx
movq %rbp, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, n(%rip)
jg .L10
.L8:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11print_arrayv, .-_Z11print_arrayv
.section .rodata.str1.1
.LC4:
.string "Verificando o Resultado.\n"
.LC5:
.string "Resultado Final: (%f, %f)\n"
.text
.globl _Z12check_resultv
.type _Z12check_resultv, @function
_Z12check_resultv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl n(%rip), %ecx
testl %ecx, %ecx
jle .L16
movq uva_c(%rip), %rax
movslq %ecx, %rdx
leaq (%rax,%rdx,4), %rdx
pxor %xmm0, %xmm0
.L15:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L15
.L14:
pxor %xmm2, %xmm2
cvtsi2ssl %ecx, %xmm2
movaps %xmm0, %xmm1
divss %xmm2, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $2, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pxor %xmm0, %xmm0
jmp .L14
.cfi_endproc
.LFE2059:
.size _Z12check_resultv, .-_Z12check_resultv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1
.LC6:
.string "N\303\272mero de Elementos: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Mem\303\263ria que ser\303\241 alocada para os 3 arrays: %d\n"
.align 8
.LC8:
.string "Allocate memory for each vector on host\n"
.section .rodata.str1.1
.LC9:
.string "Initialize vectors on host\n"
.LC10:
.string "Execute the kernel\n"
.LC12:
.string "Time Kernel Execution: %f s\n"
.LC13:
.string "Time Kernel Execution: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
movl %eax, n(%rip)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq n(%rip), %rax
leaq 0(,%rax,4), %rbx
leaq (%rax,%rax,2), %rdx
salq $2, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edx
movq %rbx, %rsi
leaq uva_a(%rip), %rdi
call cudaMallocManaged@PLT
movl $1, %edx
movq %rbx, %rsi
leaq uva_b(%rip), %rdi
call cudaMallocManaged@PLT
movl $1, %edx
movq %rbx, %rsi
leaq uva_c(%rip), %rdi
call cudaMallocManaged@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10init_arrayv
movl n(%rip), %eax
leal 510(%rax), %ebx
addl $255, %eax
cmovns %eax, %ebx
sarl $8, %ebx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
leaq 8(%rsp), %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 28(%rsp), %xmm0
divss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z11print_arrayv
call _Z12check_resultv
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq uva_a(%rip), %rdi
call cudaFree@PLT
movq uva_b(%rip), %rdi
call cudaFree@PLT
movq uva_c(%rip), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl n(%rip), %ecx
movq uva_c(%rip), %rdx
movq uva_b(%rip), %rsi
movq uva_a(%rip), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L28
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl n
.bss
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl uva_c
.align 8
.type uva_c, @object
.size uva_c, 8
uva_c:
.zero 8
.globl uva_b
.align 8
.type uva_b, @object
.size uva_b, 8
uva_b:
.zero 8
.globl uva_a
.align 8
.type uva_a, @object
.size uva_a, 8
uva_a:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <cuda_runtime.h>
// Host input vectors.
float *uva_a;
float *uva_b;
// Host output vector.
float *uva_c;
// Size of arrays.
int n = 0;
/* CUDA kernel. Each thread takes care of one element of c. */
__global__ void vecAdd(float *a, float *b, float *c, int n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
void init_array() {
fprintf(stdout, "Inicializando os arrays.\n");
int i;
// Initialize vectors on host.
for (i = 0; i < n; i++) {
uva_a[i] = sinf(i) * sinf(i);
uva_b[i] = cosf(i) * cosf(i);
}
}
void print_array() {
int i;
printf("Imprimindo o Resultado.\n");
for (i = 0; i < n; i++) {
fprintf(stdout, "uva_c[%07d]: %f\n", i, uva_c[i]);
}
}
void check_result(){
// Soma dos elementos do array C e divide por N, o valor deve ser igual a 1.
int i;
float sum = 0;
fprintf(stdout, "Verificando o Resultado.\n");
for (i = 0; i < n; i++) {
sum += uva_c[i];
}
fprintf(stdout, "Resultado Final: (%f, %f)\n", sum, (float)(sum / (float)n));
}
/* Main code */
int main(int argc, char *argv[]) {
// Size of vectors
n = atoi(argv[1]);
printf("Número de Elementos: %d\n", n);
// Size, in bytes, of each vector
size_t bytes = n * sizeof(float);
printf("Memória que será alocada para os 3 arrays: %d\n", 3 * bytes);
printf("Allocate memory for each vector on host\n");
// Allocate memory for each vector on host
cudaMallocManaged(&uva_a, bytes);
cudaMallocManaged(&uva_b, bytes);
cudaMallocManaged(&uva_c, bytes);
printf("Initialize vectors on host\n");
init_array();
// Number of threads in each thread block.
int threadsPerBlock = 256;
// Number of thread blocks in grid.
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("Execute the kernel\n");
cudaEvent_t start_event, stop_event;
float time_kernel_execution;
int eventflags = cudaEventBlockingSync;
cudaEventCreateWithFlags(&start_event, eventflags);
cudaEventCreateWithFlags(&stop_event, eventflags);
/* Recording the time to kernel execution */
cudaEventRecord(start_event, 0);
/* Execute the kernel. */
vecAdd <<< blocksPerGrid, threadsPerBlock >>> (uva_a, uva_b, uva_c, n);
/* Synchronize */
cudaDeviceSynchronize();
cudaEventRecord(stop_event, 0);
cudaEventSynchronize(stop_event);
cudaEventElapsedTime(&time_kernel_execution, start_event, stop_event);
printf("Time Kernel Execution: %f s\n", (time_kernel_execution / 1000.0f));
print_array();
check_result();
printf("Time Kernel Execution: %f ms\n", (time_kernel_execution));
// Release device memory
cudaFree(uva_a);
cudaFree(uva_b);
cudaFree(uva_c);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
// Host input vectors.
float *uva_a;
float *uva_b;
// Host output vector.
float *uva_c;
// Size of arrays.
int n = 0;
/* CUDA kernel. Each thread takes care of one element of c. */
__global__ void vecAdd(float *a, float *b, float *c, int n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
void init_array() {
fprintf(stdout, "Inicializando os arrays.\n");
int i;
// Initialize vectors on host.
for (i = 0; i < n; i++) {
uva_a[i] = sinf(i) * sinf(i);
uva_b[i] = cosf(i) * cosf(i);
}
}
void print_array() {
int i;
printf("Imprimindo o Resultado.\n");
for (i = 0; i < n; i++) {
fprintf(stdout, "uva_c[%07d]: %f\n", i, uva_c[i]);
}
}
void check_result(){
// Soma dos elementos do array C e divide por N, o valor deve ser igual a 1.
int i;
float sum = 0;
fprintf(stdout, "Verificando o Resultado.\n");
for (i = 0; i < n; i++) {
sum += uva_c[i];
}
fprintf(stdout, "Resultado Final: (%f, %f)\n", sum, (float)(sum / (float)n));
}
/* Main code */
int main(int argc, char *argv[]) {
// Size of vectors
n = atoi(argv[1]);
printf("Número de Elementos: %d\n", n);
// Size, in bytes, of each vector
size_t bytes = n * sizeof(float);
printf("Memória que será alocada para os 3 arrays: %d\n", 3 * bytes);
printf("Allocate memory for each vector on host\n");
// Allocate memory for each vector on host
hipMallocManaged(&uva_a, bytes);
hipMallocManaged(&uva_b, bytes);
hipMallocManaged(&uva_c, bytes);
printf("Initialize vectors on host\n");
init_array();
// Number of threads in each thread block.
int threadsPerBlock = 256;
// Number of thread blocks in grid.
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("Execute the kernel\n");
hipEvent_t start_event, stop_event;
float time_kernel_execution;
int eventflags = hipEventBlockingSync;
hipEventCreateWithFlags(&start_event, eventflags);
hipEventCreateWithFlags(&stop_event, eventflags);
/* Recording the time to kernel execution */
hipEventRecord(start_event, 0);
/* Execute the kernel. */
vecAdd <<< blocksPerGrid, threadsPerBlock >>> (uva_a, uva_b, uva_c, n);
/* Synchronize */
hipDeviceSynchronize();
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time_kernel_execution, start_event, stop_event);
printf("Time Kernel Execution: %f s\n", (time_kernel_execution / 1000.0f));
print_array();
check_result();
printf("Time Kernel Execution: %f ms\n", (time_kernel_execution));
// Release device memory
hipFree(uva_a);
hipFree(uva_b);
hipFree(uva_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
// Host input vectors.
float *uva_a;
float *uva_b;
// Host output vector.
float *uva_c;
// Size of arrays.
int n = 0;
/* CUDA kernel. Each thread takes care of one element of c. */
__global__ void vecAdd(float *a, float *b, float *c, int n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
void init_array() {
fprintf(stdout, "Inicializando os arrays.\n");
int i;
// Initialize vectors on host.
for (i = 0; i < n; i++) {
uva_a[i] = sinf(i) * sinf(i);
uva_b[i] = cosf(i) * cosf(i);
}
}
void print_array() {
int i;
printf("Imprimindo o Resultado.\n");
for (i = 0; i < n; i++) {
fprintf(stdout, "uva_c[%07d]: %f\n", i, uva_c[i]);
}
}
void check_result(){
// Soma dos elementos do array C e divide por N, o valor deve ser igual a 1.
int i;
float sum = 0;
fprintf(stdout, "Verificando o Resultado.\n");
for (i = 0; i < n; i++) {
sum += uva_c[i];
}
fprintf(stdout, "Resultado Final: (%f, %f)\n", sum, (float)(sum / (float)n));
}
/* Main code */
int main(int argc, char *argv[]) {
// Size of vectors
n = atoi(argv[1]);
printf("Número de Elementos: %d\n", n);
// Size, in bytes, of each vector
size_t bytes = n * sizeof(float);
printf("Memória que será alocada para os 3 arrays: %d\n", 3 * bytes);
printf("Allocate memory for each vector on host\n");
// Allocate memory for each vector on host
hipMallocManaged(&uva_a, bytes);
hipMallocManaged(&uva_b, bytes);
hipMallocManaged(&uva_c, bytes);
printf("Initialize vectors on host\n");
init_array();
// Number of threads in each thread block.
int threadsPerBlock = 256;
// Number of thread blocks in grid.
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("Execute the kernel\n");
hipEvent_t start_event, stop_event;
float time_kernel_execution;
int eventflags = hipEventBlockingSync;
hipEventCreateWithFlags(&start_event, eventflags);
hipEventCreateWithFlags(&stop_event, eventflags);
/* Recording the time to kernel execution */
hipEventRecord(start_event, 0);
/* Execute the kernel. */
vecAdd <<< blocksPerGrid, threadsPerBlock >>> (uva_a, uva_b, uva_c, n);
/* Synchronize */
hipDeviceSynchronize();
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time_kernel_execution, start_event, stop_event);
printf("Time Kernel Execution: %f s\n", (time_kernel_execution / 1000.0f));
print_array();
check_result();
printf("Time Kernel Execution: %f ms\n", (time_kernel_execution));
// Release device memory
hipFree(uva_a);
hipFree(uva_b);
hipFree(uva_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime.h>
// Host input vectors.
float *uva_a;
float *uva_b;
// Host output vector.
float *uva_c;
// Size of arrays.
int n = 0;
/* CUDA kernel. Each thread takes care of one element of c. */
__global__ void vecAdd(float *a, float *b, float *c, int n) {
// Get our global thread ID
int id = blockIdx.x * blockDim.x + threadIdx.x;
// Make sure we do not go out of bounds
if (id < n)
c[id] = a[id] + b[id];
}
void init_array() {
fprintf(stdout, "Inicializando os arrays.\n");
int i;
// Initialize vectors on host.
for (i = 0; i < n; i++) {
uva_a[i] = sinf(i) * sinf(i);
uva_b[i] = cosf(i) * cosf(i);
}
}
void print_array() {
int i;
printf("Imprimindo o Resultado.\n");
for (i = 0; i < n; i++) {
fprintf(stdout, "uva_c[%07d]: %f\n", i, uva_c[i]);
}
}
void check_result(){
// Soma dos elementos do array C e divide por N, o valor deve ser igual a 1.
int i;
float sum = 0;
fprintf(stdout, "Verificando o Resultado.\n");
for (i = 0; i < n; i++) {
sum += uva_c[i];
}
fprintf(stdout, "Resultado Final: (%f, %f)\n", sum, (float)(sum / (float)n));
}
/* Main code */
int main(int argc, char *argv[]) {
// Size of vectors
n = atoi(argv[1]);
printf("Número de Elementos: %d\n", n);
// Size, in bytes, of each vector
size_t bytes = n * sizeof(float);
printf("Memória que será alocada para os 3 arrays: %d\n", 3 * bytes);
printf("Allocate memory for each vector on host\n");
// Allocate memory for each vector on host
hipMallocManaged(&uva_a, bytes);
hipMallocManaged(&uva_b, bytes);
hipMallocManaged(&uva_c, bytes);
printf("Initialize vectors on host\n");
init_array();
// Number of threads in each thread block.
int threadsPerBlock = 256;
// Number of thread blocks in grid.
int blocksPerGrid = (n + threadsPerBlock - 1) / threadsPerBlock;
printf("Execute the kernel\n");
hipEvent_t start_event, stop_event;
float time_kernel_execution;
int eventflags = hipEventBlockingSync;
hipEventCreateWithFlags(&start_event, eventflags);
hipEventCreateWithFlags(&stop_event, eventflags);
/* Recording the time to kernel execution */
hipEventRecord(start_event, 0);
/* Execute the kernel. */
vecAdd <<< blocksPerGrid, threadsPerBlock >>> (uva_a, uva_b, uva_c, n);
/* Synchronize */
hipDeviceSynchronize();
hipEventRecord(stop_event, 0);
hipEventSynchronize(stop_event);
hipEventElapsedTime(&time_kernel_execution, start_event, stop_event);
printf("Time Kernel Execution: %f s\n", (time_kernel_execution / 1000.0f));
print_array();
check_result();
printf("Time Kernel Execution: %f ms\n", (time_kernel_execution));
// Release device memory
hipFree(uva_a);
hipFree(uva_b);
hipFree(uva_c);
return 0;
} | .text
.file "vectoradd.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z10init_arrayv # -- Begin function _Z10init_arrayv
.p2align 4, 0x90
.type _Z10init_arrayv,@function
_Z10init_arrayv: # @_Z10init_arrayv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, n(%rip)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq sinf
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
mulss 8(%rsp), %xmm0 # 4-byte Folded Reload
movq uva_a(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
mulss 8(%rsp), %xmm0 # 4-byte Folded Reload
movq uva_b(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB1_2
.LBB1_3: # %._crit_edge
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10init_arrayv, .Lfunc_end1-_Z10init_arrayv
.cfi_endproc
# -- End function
.globl _Z11print_arrayv # -- Begin function _Z11print_arrayv
.p2align 4, 0x90
.type _Z11print_arrayv,@function
_Z11print_arrayv: # @_Z11print_arrayv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, n(%rip)
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movq uva_c(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movl %ebx, %edx
movb $1, %al
callq fprintf
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB2_2
.LBB2_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11print_arrayv, .Lfunc_end2-_Z11print_arrayv
.cfi_endproc
# -- End function
.globl _Z12check_resultv # -- Begin function _Z12check_resultv
.p2align 4, 0x90
.type _Z12check_resultv,@function
_Z12check_resultv: # @_Z12check_resultv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stdout(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl n(%rip), %eax
xorps %xmm1, %xmm1
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph
movq uva_c(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
addss (%rcx,%rdx,4), %xmm1
incq %rdx
cmpq %rdx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq stdout(%rip), %rdi
cvtsi2ss %eax, %xmm2
cvtss2sd %xmm1, %xmm0
divss %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %esi
movb $2, %al
popq %rcx
.cfi_def_cfa_offset 8
jmp fprintf # TAILCALL
.Lfunc_end3:
.size _Z12check_resultv, .Lfunc_end3-_Z12check_resultv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, n(%rip)
movl $.L.str.5, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movslq n(%rip), %rbx
shlq $2, %rbx
leaq (%rbx,%rbx,2), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movl $uva_a, %edi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movl $uva_b, %edi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movl $uva_c, %edi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movl $.Lstr.2, %edi
callq puts@PLT
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, n(%rip)
jle .LBB4_3
# %bb.1: # %.lr.ph.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
callq sinf
movss %xmm0, (%rsp) # 4-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
movq uva_a(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
movss %xmm0, (%rsp) # 4-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
movq uva_b(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB4_2
.LBB4_3: # %_Z10init_arrayv.exit
movl n(%rip), %ebx
leal 255(%rbx), %eax
addl $510, %ebx # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %ebx
sarl $8, %ebx
movl $.Lstr.3, %edi
callq puts@PLT
leaq 24(%rsp), %rdi
movl $1, %esi
callq hipEventCreateWithFlags
leaq 8(%rsp), %rdi
movl $1, %esi
callq hipEventCreateWithFlags
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rbx
orq $256, %rdx # imm = 0x100
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4:
movq uva_a(%rip), %rax
movq uva_b(%rip), %rcx
movq uva_c(%rip), %rdx
movl n(%rip), %esi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 20(%rsp)
leaq 136(%rsp), %rax
movq %rax, 32(%rsp)
leaq 128(%rsp), %rax
movq %rax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 20(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_5:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, n(%rip)
jle .LBB4_8
# %bb.6: # %.lr.ph.i14.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movq uva_c(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movl %ebx, %edx
movb $1, %al
callq fprintf
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB4_7
.LBB4_8: # %_Z11print_arrayv.exit
movq stdout(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl n(%rip), %eax
xorps %xmm1, %xmm1
testl %eax, %eax
jle .LBB4_11
# %bb.9: # %.lr.ph.i17
movq uva_c(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_10: # =>This Inner Loop Header: Depth=1
addss (%rcx,%rdx,4), %xmm1
incq %rdx
cmpq %rdx, %rax
jne .LBB4_10
.LBB4_11: # %_Z12check_resultv.exit
cvtsi2ss %eax, %xmm2
movq stdout(%rip), %rdi
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
divss %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %esi
movb $2, %al
callq fprintf
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movq uva_a(%rip), %rdi
callq hipFree
movq uva_b(%rip), %rdi
callq hipFree
movq uva_c(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type uva_a,@object # @uva_a
.bss
.globl uva_a
.p2align 3, 0x0
uva_a:
.quad 0
.size uva_a, 8
.type uva_b,@object # @uva_b
.globl uva_b
.p2align 3, 0x0
uva_b:
.quad 0
.size uva_b, 8
.type uva_c,@object # @uva_c
.globl uva_c
.p2align 3, 0x0
uva_c:
.quad 0
.size uva_c, 8
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Inicializando os arrays.\n"
.size .L.str, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "uva_c[%07d]: %f\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Verificando o Resultado.\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Resultado Final: (%f, %f)\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "N\303\272mero de Elementos: %d\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Mem\303\263ria que ser\303\241 alocada para os 3 arrays: %d\n"
.size .L.str.6, 49
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Time Kernel Execution: %f s\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Time Kernel Execution: %f ms\n"
.size .L.str.11, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Imprimindo o Resultado."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Allocate memory for each vector on host"
.size .Lstr.1, 40
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Initialize vectors on host"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Execute the kernel"
.size .Lstr.3, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym uva_a
.addrsig_sym uva_b
.addrsig_sym uva_c
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000259a3_00000000-6_vectoradd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Inicializando os arrays.\n"
.text
.globl _Z10init_arrayv
.type _Z10init_arrayv, @function
_Z10init_arrayv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
cmpl $0, n(%rip)
jle .L3
movl $0, %ebx
leaq 12(%rsp), %rbp
.L5:
leaq 8(%rsp), %rsi
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movq %rbp, %rdi
call sincosf@PLT
movss 8(%rsp), %xmm0
movss 12(%rsp), %xmm1
mulss %xmm1, %xmm1
movq uva_a(%rip), %rax
movss %xmm1, (%rax,%rbx,4)
mulss %xmm0, %xmm0
movq uva_b(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, n(%rip)
jg .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10init_arrayv, .-_Z10init_arrayv
.section .rodata.str1.1
.LC1:
.string "Imprimindo o Resultado.\n"
.LC2:
.string "uva_c[%07d]: %f\n"
.text
.globl _Z11print_arrayv
.type _Z11print_arrayv, @function
_Z11print_arrayv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, n(%rip)
jle .L8
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L10:
movq uva_c(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %ecx
movq %rbp, %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, n(%rip)
jg .L10
.L8:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11print_arrayv, .-_Z11print_arrayv
.section .rodata.str1.1
.LC4:
.string "Verificando o Resultado.\n"
.LC5:
.string "Resultado Final: (%f, %f)\n"
.text
.globl _Z12check_resultv
.type _Z12check_resultv, @function
_Z12check_resultv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl n(%rip), %ecx
testl %ecx, %ecx
jle .L16
movq uva_c(%rip), %rax
movslq %ecx, %rdx
leaq (%rax,%rdx,4), %rdx
pxor %xmm0, %xmm0
.L15:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L15
.L14:
pxor %xmm2, %xmm2
cvtsi2ssl %ecx, %xmm2
movaps %xmm0, %xmm1
divss %xmm2, %xmm1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $2, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pxor %xmm0, %xmm0
jmp .L14
.cfi_endproc
.LFE2059:
.size _Z12check_resultv, .-_Z12check_resultv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.1
.LC6:
.string "N\303\272mero de Elementos: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Mem\303\263ria que ser\303\241 alocada para os 3 arrays: %d\n"
.align 8
.LC8:
.string "Allocate memory for each vector on host\n"
.section .rodata.str1.1
.LC9:
.string "Initialize vectors on host\n"
.LC10:
.string "Execute the kernel\n"
.LC12:
.string "Time Kernel Execution: %f s\n"
.LC13:
.string "Time Kernel Execution: %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
movl %eax, n(%rip)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq n(%rip), %rax
leaq 0(,%rax,4), %rbx
leaq (%rax,%rax,2), %rdx
salq $2, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edx
movq %rbx, %rsi
leaq uva_a(%rip), %rdi
call cudaMallocManaged@PLT
movl $1, %edx
movq %rbx, %rsi
leaq uva_b(%rip), %rdi
call cudaMallocManaged@PLT
movl $1, %edx
movq %rbx, %rsi
leaq uva_c(%rip), %rdi
call cudaMallocManaged@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10init_arrayv
movl n(%rip), %eax
leal 510(%rax), %ebx
addl $255, %eax
cmovns %eax, %ebx
sarl $8, %ebx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
leaq 8(%rsp), %rdi
movl $1, %esi
call cudaEventCreateWithFlags@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 28(%rsp), %xmm0
divss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z11print_arrayv
call _Z12check_resultv
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq uva_a(%rip), %rdi
call cudaFree@PLT
movq uva_b(%rip), %rdi
call cudaFree@PLT
movq uva_c(%rip), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl n(%rip), %ecx
movq uva_c(%rip), %rdx
movq uva_b(%rip), %rsi
movq uva_a(%rip), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L28
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl n
.bss
.align 4
.type n, @object
.size n, 4
n:
.zero 4
.globl uva_c
.align 8
.type uva_c, @object
.size uva_c, 8
uva_c:
.zero 8
.globl uva_b
.align 8
.type uva_b, @object
.size uva_b, 8
uva_b:
.zero 8
.globl uva_a
.align 8
.type uva_a, @object
.size uva_a, 8
uva_a:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectoradd.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.globl _Z10init_arrayv # -- Begin function _Z10init_arrayv
.p2align 4, 0x90
.type _Z10init_arrayv,@function
_Z10init_arrayv: # @_Z10init_arrayv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, n(%rip)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 12(%rsp) # 4-byte Spill
callq sinf
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
mulss 8(%rsp), %xmm0 # 4-byte Folded Reload
movq uva_a(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
movss %xmm0, 8(%rsp) # 4-byte Spill
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
mulss 8(%rsp), %xmm0 # 4-byte Folded Reload
movq uva_b(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB1_2
.LBB1_3: # %._crit_edge
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10init_arrayv, .Lfunc_end1-_Z10init_arrayv
.cfi_endproc
# -- End function
.globl _Z11print_arrayv # -- Begin function _Z11print_arrayv
.p2align 4, 0x90
.type _Z11print_arrayv,@function
_Z11print_arrayv: # @_Z11print_arrayv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, n(%rip)
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movq uva_c(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movl %ebx, %edx
movb $1, %al
callq fprintf
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB2_2
.LBB2_3: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z11print_arrayv, .Lfunc_end2-_Z11print_arrayv
.cfi_endproc
# -- End function
.globl _Z12check_resultv # -- Begin function _Z12check_resultv
.p2align 4, 0x90
.type _Z12check_resultv,@function
_Z12check_resultv: # @_Z12check_resultv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stdout(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl n(%rip), %eax
xorps %xmm1, %xmm1
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph
movq uva_c(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
addss (%rcx,%rdx,4), %xmm1
incq %rdx
cmpq %rdx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq stdout(%rip), %rdi
cvtsi2ss %eax, %xmm2
cvtss2sd %xmm1, %xmm0
divss %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %esi
movb $2, %al
popq %rcx
.cfi_def_cfa_offset 8
jmp fprintf # TAILCALL
.Lfunc_end3:
.size _Z12check_resultv, .Lfunc_end3-_Z12check_resultv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, n(%rip)
movl $.L.str.5, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movslq n(%rip), %rbx
shlq $2, %rbx
leaq (%rbx,%rbx,2), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
movl $uva_a, %edi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movl $uva_b, %edi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movl $uva_c, %edi
movq %rbx, %rsi
movl $1, %edx
callq hipMallocManaged
movl $.Lstr.2, %edi
callq puts@PLT
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
cmpl $0, n(%rip)
jle .LBB4_3
# %bb.1: # %.lr.ph.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 4(%rsp) # 4-byte Spill
callq sinf
movss %xmm0, (%rsp) # 4-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq sinf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
movq uva_a(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
movss %xmm0, (%rsp) # 4-byte Spill
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
callq cosf
mulss (%rsp), %xmm0 # 4-byte Folded Reload
movq uva_b(%rip), %rax
movss %xmm0, (%rax,%rbx,4)
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB4_2
.LBB4_3: # %_Z10init_arrayv.exit
movl n(%rip), %ebx
leal 255(%rbx), %eax
addl $510, %ebx # imm = 0x1FE
testl %eax, %eax
cmovnsl %eax, %ebx
sarl $8, %ebx
movl $.Lstr.3, %edi
callq puts@PLT
leaq 24(%rsp), %rdi
movl $1, %esi
callq hipEventCreateWithFlags
leaq 8(%rsp), %rdi
movl $1, %esi
callq hipEventCreateWithFlags
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rbx
orq $256, %rdx # imm = 0x100
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4:
movq uva_a(%rip), %rax
movq uva_b(%rip), %rcx
movq uva_c(%rip), %rdx
movl n(%rip), %esi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %esi, 20(%rsp)
leaq 136(%rsp), %rax
movq %rax, 32(%rsp)
leaq 128(%rsp), %rax
movq %rax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 20(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_5:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, n(%rip)
jle .LBB4_8
# %bb.6: # %.lr.ph.i14.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i14
# =>This Inner Loop Header: Depth=1
movq stdout(%rip), %rdi
movq uva_c(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %esi
movl %ebx, %edx
movb $1, %al
callq fprintf
incq %rbx
movslq n(%rip), %rax
cmpq %rax, %rbx
jl .LBB4_7
.LBB4_8: # %_Z11print_arrayv.exit
movq stdout(%rip), %rcx
movl $.L.str.3, %edi
movl $25, %esi
movl $1, %edx
callq fwrite@PLT
movl n(%rip), %eax
xorps %xmm1, %xmm1
testl %eax, %eax
jle .LBB4_11
# %bb.9: # %.lr.ph.i17
movq uva_c(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_10: # =>This Inner Loop Header: Depth=1
addss (%rcx,%rdx,4), %xmm1
incq %rdx
cmpq %rdx, %rax
jne .LBB4_10
.LBB4_11: # %_Z12check_resultv.exit
cvtsi2ss %eax, %xmm2
movq stdout(%rip), %rdi
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
divss %xmm2, %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.4, %esi
movb $2, %al
callq fprintf
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movq uva_a(%rip), %rdi
callq hipFree
movq uva_b(%rip), %rdi
callq hipFree
movq uva_c(%rip), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type uva_a,@object # @uva_a
.bss
.globl uva_a
.p2align 3, 0x0
uva_a:
.quad 0
.size uva_a, 8
.type uva_b,@object # @uva_b
.globl uva_b
.p2align 3, 0x0
uva_b:
.quad 0
.size uva_b, 8
.type uva_c,@object # @uva_c
.globl uva_c
.p2align 3, 0x0
uva_c:
.quad 0
.size uva_c, 8
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Inicializando os arrays.\n"
.size .L.str, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "uva_c[%07d]: %f\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Verificando o Resultado.\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Resultado Final: (%f, %f)\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "N\303\272mero de Elementos: %d\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Mem\303\263ria que ser\303\241 alocada para os 3 arrays: %d\n"
.size .L.str.6, 49
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Time Kernel Execution: %f s\n"
.size .L.str.10, 29
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Time Kernel Execution: %f ms\n"
.size .L.str.11, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Imprimindo o Resultado."
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Allocate memory for each vector on host"
.size .Lstr.1, 40
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Initialize vectors on host"
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Execute the kernel"
.size .Lstr.3, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym uva_a
.addrsig_sym uva_b
.addrsig_sym uva_c
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
#include <cuda_runtime.h>
namespace computation_playground {
__global__ void transpose2d_naive_kernel(float* in, float* out, int m, int n) {
int in_row_offet = blockIdx.x * blockDim.x + threadIdx.x;
if(in_row_offet < m) {
int in_global_offset = blockIdx.y * m + in_row_offet;
int out_global_offset = in_row_offet * n + blockIdx.y;
*(out + out_global_offset) = *(in + in_global_offset);
}
}
void transpose2d_naive(float* in, float* out, int m, int n, cudaStream_t stream) {
int threads_per_block = 32;
int blocks_per_row = std::ceil(m / float(threads_per_block));
dim3 grid(blocks_per_row, n);
transpose2d_naive_kernel<<<grid, threads_per_block, 0, stream>>>(in, out, m, n);
}
__global__ void transpose2d_tile_kernel(float* in, float* out, int m, int n,
int m_direction_iteration, int n_direction_iteration) {
for(int j = 0; j < n_direction_iteration; j++) {
for(int i = 0; i < m_direction_iteration; i++) {
int x = blockIdx.x * blockDim.x * m_direction_iteration + i * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y * n_direction_iteration + j * blockDim.y + threadIdx.y;
if(x < m && y < n) {
out[x * n + y] = in[y * m + x];
}
}
}
}
void transpose2d_tile(float* in, float* out, int m, int n, int tile_m_dim, int tile_n_dim,
int m_direction_iteration, int n_direction_iteration, cudaStream_t stream) {
dim3 grid(std::ceil(m / (tile_m_dim * m_direction_iteration)), std::ceil(n / (tile_n_dim * n_direction_iteration)));
dim3 block(tile_m_dim, tile_n_dim);
transpose2d_tile_kernel<<<grid, block, 0, stream>>>(in, out, m, n, m_direction_iteration, n_direction_iteration);
}
} // namespace computation_playground | code for sm_80
Function : _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*0020*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f03270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ S2UR UR12, SR_CTAID.X ; /* 0x00000000000c79c3 */
/* 0x000e220000002500 */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000ea20000002200 */
/*00b0*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe40000000800 */
/*00c0*/ S2UR UR13, SR_CTAID.Y ; /* 0x00000000000d79c3 */
/* 0x000ee20000002600 */
/*00d0*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fe40000000800 */
/*00e0*/ UIMAD UR6, UR5, UR6, URZ ; /* 0x00000006050672a4 */
/* 0x000fe2000f8e023f */
/*00f0*/ IADD3 R3, -R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ ULOP3.LUT UR11, UR7, 0x3, URZ, 0xc0, !UPT ; /* 0x00000003070b7892 */
/* 0x000fc4000f8ec03f */
/*0110*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0130*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fe40000000a00 */
/*0140*/ UIMAD UR9, UR12, UR7, 0x2 ; /* 0x000000020c0974a4 */
/* 0x001fe4000f8e0207 */
/*0150*/ UIMAD UR10, UR12, UR7, 0x1 ; /* 0x000000010c0a74a4 */
/* 0x000fe4000f8e0207 */
/*0160*/ UIMAD UR5, UR12, UR5, URZ ; /* 0x000000050c0572a4 */
/* 0x000fe4000f8e023f */
/*0170*/ UIMAD UR8, UR12, UR7, 0x3 ; /* 0x000000030c0874a4 */
/* 0x000fe2000f8e0207 */
/*0180*/ MOV R5, UR9 ; /* 0x0000000900057c02 */
/* 0x000fe20008000f00 */
/*0190*/ UIADD3 UR7, UR11, -UR7, URZ ; /* 0x800000070b077290 */
/* 0x000fe2000fffe03f */
/*01a0*/ MOV R7, UR10 ; /* 0x0000000a00077c02 */
/* 0x000fc40008000f00 */
/*01b0*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x000fe20008000f00 */
/*01c0*/ IMAD.U32 R3, RZ, RZ, UR8 ; /* 0x00000008ff037e24 */
/* 0x000fe4000f8e00ff */
/*01d0*/ IMAD R5, R5, c[0x0][0x0], R0.reuse ; /* 0x0000000005057a24 */
/* 0x102fe400078e0200 */
/*01e0*/ IMAD R3, R3, c[0x0][0x0], R0.reuse ; /* 0x0000000003037a24 */
/* 0x100fe400078e0200 */
/*01f0*/ IMAD R7, R7, c[0x0][0x0], R0.reuse ; /* 0x0000000007077a24 */
/* 0x100fe400078e0200 */
/*0200*/ IMAD R9, R9, c[0x0][0x178], R0 ; /* 0x00005e0009097a24 */
/* 0x000fe400078e0200 */
/*0210*/ IMAD R4, R3, c[0x0][0x174], R2 ; /* 0x00005d0003047a24 */
/* 0x004fc400078e0202 */
/*0220*/ IMAD R6, R5, c[0x0][0x174], R2.reuse ; /* 0x00005d0005067a24 */
/* 0x100fe400078e0202 */
/*0230*/ IMAD R8, R7, c[0x0][0x174], R2.reuse ; /* 0x00005d0007087a24 */
/* 0x100fe400078e0202 */
/*0240*/ IMAD R10, R9, c[0x0][0x174], R2 ; /* 0x00005d00090a7a24 */
/* 0x008fe400078e0202 */
/*0250*/ ULDC UR9, c[0x0][0x17c] ; /* 0x00005f0000097ab9 */
/* 0x000fe40000000800 */
/*0260*/ UIMAD UR8, UR13, UR9, UR4 ; /* 0x000000090d0872a4 */
/* 0x000fe4000f8e0204 */
/*0270*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0280*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*0290*/ IMAD.U32 R11, RZ, RZ, UR8 ; /* 0x00000008ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*02a0*/ UISETP.GE.AND UP0, UPT, UR4, UR9, UPT ; /* 0x000000090400728c */
/* 0x000fc6000bf06270 */
/*02b0*/ IMAD R12, R11, c[0x0][0x4], R2 ; /* 0x000001000b0c7a24 */
/* 0x001fe200078e0202 */
/*02c0*/ @!P1 BRA 0x6a0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*02d0*/ MOV R21, UR8 ; /* 0x0000000800157c02 */
/* 0x000fe20008000f00 */
/*02e0*/ IMAD.U32 R17, RZ, RZ, UR8 ; /* 0x00000008ff117e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ MOV R15, UR8 ; /* 0x00000008000f7c02 */
/* 0x000fe20008000f00 */
/*0300*/ IMAD R22, R12.reuse, c[0x0][0x170], R3 ; /* 0x00005c000c167a24 */
/* 0x040fe200078e0203 */
/*0310*/ MOV R27, UR8 ; /* 0x00000008001b7c02 */
/* 0x000fe20008000f00 */
/*0320*/ IMAD R11, R12.reuse, c[0x0][0x170], R5 ; /* 0x00005c000c0b7a24 */
/* 0x040fe200078e0205 */
/*0330*/ ISETP.GE.AND P0, PT, R12.reuse, c[0x0][0x174], PT ; /* 0x00005d000c007a0c */
/* 0x040fe20003f06270 */
/*0340*/ IMAD R13, R12.reuse, c[0x0][0x170], R7 ; /* 0x00005c000c0d7a24 */
/* 0x040fe200078e0207 */
/*0350*/ MOV R23, R9 ; /* 0x0000000900177202 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD R20, R12, c[0x0][0x170], R9 ; /* 0x00005c000c147a24 */
/* 0x000fe200078e0209 */
/*0370*/ MOV R24, R7 ; /* 0x0000000700187202 */
/* 0x000fe20000000f00 */
/*0380*/ IMAD.MOV.U32 R29, RZ, RZ, R3 ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e0003 */
/*0390*/ MOV R25, R5 ; /* 0x0000000500197202 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD R21, R21, c[0x0][0x4], R4 ; /* 0x0000010015157a24 */
/* 0x000fe200078e0204 */
/*03b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*03c0*/ IMAD R26, R15, c[0x0][0x4], R6 ; /* 0x000001000f1a7a24 */
/* 0x000fc400078e0206 */
/*03d0*/ IMAD R27, R27, c[0x0][0x4], R8 ; /* 0x000001001b1b7a24 */
/* 0x000fe400078e0208 */
/*03e0*/ IMAD R28, R17, c[0x0][0x4], R10 ; /* 0x00000100111c7a24 */
/* 0x000fe400078e020a */
/*03f0*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x170], P0 ; /* 0x00005c0017007a0c */
/* 0x000fda0000766670 */
/*0400*/ @!P3 MOV R19, 0x4 ; /* 0x000000040013b802 */
/* 0x000fca0000000f00 */
/*0410*/ @!P3 IMAD.WIDE R14, R20, R19, c[0x0][0x160] ; /* 0x00005800140eb625 */
/* 0x000fca00078e0213 */
/*0420*/ @!P3 LDG.E R17, [R14.64] ; /* 0x0000000e0e11b981 */
/* 0x0000a2000c1e1900 */
/*0430*/ ISETP.GE.OR P2, PT, R24, c[0x0][0x170], P0 ; /* 0x00005c0018007a0c */
/* 0x000fe20000746670 */
/*0440*/ @!P3 IMAD.WIDE R14, R28, R19, c[0x0][0x168] ; /* 0x00005a001c0eb625 */
/* 0x001fd800078e0213 */
/*0450*/ @!P2 MOV R16, 0x4 ; /* 0x000000040010a802 */
/* 0x000fca0000000f00 */
/*0460*/ @!P2 IMAD.WIDE R18, R13, R16.reuse, c[0x0][0x160] ; /* 0x000058000d12a625 */
/* 0x080fe200078e0210 */
/*0470*/ @!P3 STG.E [R14.64], R17 ; /* 0x000000110e00b986 */
/* 0x0041ea000c10190e */
/*0480*/ @!P2 LDG.E R19, [R18.64] ; /* 0x0000000e1213a981 */
/* 0x000ea2000c1e1900 */
/*0490*/ ISETP.GE.OR P3, PT, R25, c[0x0][0x170], P0 ; /* 0x00005c0019007a0c */
/* 0x000fe20000766670 */
/*04a0*/ @!P2 IMAD.WIDE R16, R27, R16, c[0x0][0x168] ; /* 0x00005a001b10a625 */
/* 0x001fca00078e0210 */
/*04b0*/ @!P2 STG.E [R16.64], R19 ; /* 0x000000131000a986 */
/* 0x0041ee000c10190e */
/*04c0*/ @!P3 MOV R16, 0x4 ; /* 0x000000040010b802 */
/* 0x001fca0000000f00 */
/*04d0*/ @!P3 IMAD.WIDE R14, R11, R16, c[0x0][0x160] ; /* 0x000058000b0eb625 */
/* 0x000fca00078e0210 */
/*04e0*/ @!P3 LDG.E R18, [R14.64] ; /* 0x0000000e0e12b981 */
/* 0x0000a2000c1e1900 */
/*04f0*/ ISETP.GE.OR P2, PT, R29, c[0x0][0x170], P0 ; /* 0x00005c001d007a0c */
/* 0x000fe20000746670 */
/*0500*/ @!P3 IMAD.WIDE R14, R26, R16, c[0x0][0x168] ; /* 0x00005a001a0eb625 */
/* 0x001fca00078e0210 */
/*0510*/ @!P3 STG.E [R14.64], R18 ; /* 0x000000120e00b986 */
/* 0x0041ee000c10190e */
/*0520*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff12a424 */
/* 0x001fc800078e00ff */
/*0530*/ @!P2 IMAD.WIDE R16, R22, R18, c[0x0][0x160] ; /* 0x000058001610a625 */
/* 0x000fcc00078e0212 */
/*0540*/ @!P2 LDG.E R17, [R16.64] ; /* 0x0000000e1011a981 */
/* 0x0000a2000c1e1900 */
/*0550*/ UIADD3 UR5, UR5, 0x4, URZ ; /* 0x0000000405057890 */
/* 0x000fe2000fffe03f */
/*0560*/ @!P2 IMAD.WIDE R18, R21, R18, c[0x0][0x168] ; /* 0x00005a001512a625 */
/* 0x000fe200078e0212 */
/*0570*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe40008000f00 */
/*0580*/ UIADD3 UR8, UR7, UR5, URZ ; /* 0x0000000507087290 */
/* 0x000fe2000fffe03f */
/*0590*/ MOV R15, UR6 ; /* 0x00000006000f7c02 */
/* 0x000fe40008000f00 */
/*05a0*/ IMAD R21, R14.reuse, 0x4, R21 ; /* 0x000000040e157824 */
/* 0x040fe200078e0215 */
/*05b0*/ LEA R27, R14, R27, 0x2 ; /* 0x0000001b0e1b7211 */
/* 0x000fe400078e10ff */
/*05c0*/ MOV R16, c[0x0][0x0] ; /* 0x0000000000107a02 */
/* 0x001fc40000000f00 */
/*05d0*/ LEA R26, R15, R26, 0x2 ; /* 0x0000001a0f1a7211 */
/* 0x000fe400078e10ff */
/*05e0*/ LEA R29, R16.reuse, R29, 0x2 ; /* 0x0000001d101d7211 */
/* 0x040fe200078e10ff */
/*05f0*/ IMAD R24, R16.reuse, 0x4, R24 ; /* 0x0000000410187824 */
/* 0x040fe200078e0218 */
/*0600*/ LEA R25, R16.reuse, R25, 0x2 ; /* 0x0000001910197211 */
/* 0x040fe200078e10ff */
/*0610*/ IMAD R13, R16.reuse, 0x4, R13 ; /* 0x00000004100d7824 */
/* 0x040fe200078e020d */
/*0620*/ LEA R23, R16.reuse, R23, 0x2 ; /* 0x0000001710177211 */
/* 0x040fe400078e10ff */
/*0630*/ LEA R22, R16.reuse, R22, 0x2 ; /* 0x0000001610167211 */
/* 0x040fe400078e10ff */
/*0640*/ LEA R11, R16, R11, 0x2 ; /* 0x0000000b100b7211 */
/* 0x000fc400078e10ff */
/*0650*/ LEA R20, R16, R20, 0x2 ; /* 0x0000001410147211 */
/* 0x000fe400078e10ff */
/*0660*/ LEA R28, R15, R28, 0x2 ; /* 0x0000001c0f1c7211 */
/* 0x000fe200078e10ff */
/*0670*/ @!P2 STG.E [R18.64], R17 ; /* 0x000000111200a986 */
/* 0x0041e2000c10190e */
/*0680*/ ISETP.NE.AND P2, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fda000bf45270 */
/*0690*/ @P2 BRA 0x3f0 ; /* 0xfffffd5000002947 */
/* 0x001fea000383ffff */
/*06a0*/ ISETP.NE.AND P0, PT, RZ, UR11, PT ; /* 0x0000000bff007c0c */
/* 0x000fda000bf05270 */
/*06b0*/ @!P0 BRA 0x9e0 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*06c0*/ ULDC UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000800 */
/*06d0*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x174], PT ; /* 0x00005d000c007a0c */
/* 0x000fe20003f06270 */
/*06e0*/ UIMAD UR5, UR12, UR8, UR5 ; /* 0x000000080c0572a4 */
/* 0x000fe2000f8e0205 */
/*06f0*/ BSSY B0, 0x7c0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0700*/ MOV R11, UR5 ; /* 0x00000005000b7c02 */
/* 0x000fca0008000f00 */
/*0710*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x000fca00078e0200 */
/*0720*/ ISETP.GE.OR P2, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000746670 */
/*0730*/ @P2 BRA 0x7b0 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*0740*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe400078e00ff */
/*0750*/ IMAD R14, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0e7a24 */
/* 0x000fc800078e020b */
/*0760*/ IMAD.WIDE R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e0211 */
/*0770*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*0780*/ IMAD R16, R11, c[0x0][0x174], R12 ; /* 0x00005d000b107a24 */
/* 0x000fc800078e020c */
/*0790*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fca00078e0211 */
/*07a0*/ STG.E [R16.64], R15 ; /* 0x0000000f10007986 */
/* 0x0041e4000c10190e */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ UISETP.NE.AND UP1, UPT, UR11, 0x1, UPT ; /* 0x000000010b00788c */
/* 0x000fcc000bf25270 */
/*07d0*/ PLOP3.LUT P2, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f4f018 */
/*07e0*/ @!P2 BRA 0x9e0 ; /* 0x000001f00000a947 */
/* 0x000fea0003800000 */
/*07f0*/ UIADD3 UR8, UR5, 0x1, URZ ; /* 0x0000000105087890 */
/* 0x000fe2000fffe03f */
/*0800*/ BSSY B0, 0x8d0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0810*/ MOV R11, UR8 ; /* 0x00000008000b7c02 */
/* 0x000fca0008000f00 */
/*0820*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x000fca00078e0200 */
/*0830*/ ISETP.GE.OR P2, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000746670 */
/*0840*/ @P2 BRA 0x8c0 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*0850*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x001fe200000001ff */
/*0860*/ IMAD R14, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0e7a24 */
/* 0x000fd200078e020b */
/*0870*/ IMAD.WIDE R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e0211 */
/*0880*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*0890*/ IMAD R16, R11, c[0x0][0x174], R12 ; /* 0x00005d000b107a24 */
/* 0x000fc800078e020c */
/*08a0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fca00078e0211 */
/*08b0*/ STG.E [R16.64], R15 ; /* 0x0000000f10007986 */
/* 0x0041e4000c10190e */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ UISETP.NE.AND UP1, UPT, UR11, 0x2, UPT ; /* 0x000000020b00788c */
/* 0x000fcc000bf25270 */
/*08e0*/ PLOP3.LUT P2, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f4f018 */
/*08f0*/ @!P2 BRA 0x9e0 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0900*/ UIADD3 UR5, UR5, 0x2, URZ ; /* 0x0000000205057890 */
/* 0x000fe2000fffe03f */
/*0910*/ BSSY B0, 0x9e0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0920*/ MOV R11, UR5 ; /* 0x00000005000b7c02 */
/* 0x000fca0008000f00 */
/*0930*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x000fca00078e0200 */
/*0940*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000706670 */
/*0950*/ @P0 BRA 0x9d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0970*/ IMAD R14, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0e7a24 */
/* 0x000fc800078e020b */
/*0980*/ IMAD.WIDE R14, R14, R13, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x001fcc00078e020d */
/*0990*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*09a0*/ IMAD R12, R11, c[0x0][0x174], R12 ; /* 0x00005d000b0c7a24 */
/* 0x000fc800078e020c */
/*09b0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fca00078e020d */
/*09c0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0041e4000c10190e */
/*09d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09e0*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*09f0*/ @!P0 BRA 0x250 ; /* 0xfffff85000008947 */
/* 0x000fea000383ffff */
/*0a00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a10*/ BRA 0xa10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x001fd000078e0200 */
/*00a0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R4, R0, c[0x0][0x174], R5 ; /* 0x00005d0000047a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <cuda_runtime.h>
namespace computation_playground {
__global__ void transpose2d_naive_kernel(float* in, float* out, int m, int n) {
int in_row_offet = blockIdx.x * blockDim.x + threadIdx.x;
if(in_row_offet < m) {
int in_global_offset = blockIdx.y * m + in_row_offet;
int out_global_offset = in_row_offet * n + blockIdx.y;
*(out + out_global_offset) = *(in + in_global_offset);
}
}
void transpose2d_naive(float* in, float* out, int m, int n, cudaStream_t stream) {
int threads_per_block = 32;
int blocks_per_row = std::ceil(m / float(threads_per_block));
dim3 grid(blocks_per_row, n);
transpose2d_naive_kernel<<<grid, threads_per_block, 0, stream>>>(in, out, m, n);
}
__global__ void transpose2d_tile_kernel(float* in, float* out, int m, int n,
int m_direction_iteration, int n_direction_iteration) {
for(int j = 0; j < n_direction_iteration; j++) {
for(int i = 0; i < m_direction_iteration; i++) {
int x = blockIdx.x * blockDim.x * m_direction_iteration + i * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y * n_direction_iteration + j * blockDim.y + threadIdx.y;
if(x < m && y < n) {
out[x * n + y] = in[y * m + x];
}
}
}
}
void transpose2d_tile(float* in, float* out, int m, int n, int tile_m_dim, int tile_n_dim,
int m_direction_iteration, int n_direction_iteration, cudaStream_t stream) {
dim3 grid(std::ceil(m / (tile_m_dim * m_direction_iteration)), std::ceil(n / (tile_n_dim * n_direction_iteration)));
dim3 block(tile_m_dim, tile_n_dim);
transpose2d_tile_kernel<<<grid, block, 0, stream>>>(in, out, m, n, m_direction_iteration, n_direction_iteration);
}
} // namespace computation_playground | .file "tmpxft_000a1a50_00000000-6_tranpose2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
.type _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii, @function
_Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii, .-_Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
.globl _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.type _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, @function
_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, .-_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.globl _ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st
.type _ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st, @function
_ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movq %r8, %r9
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %ebp, 12(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
jmp .L11
.cfi_endproc
.LFE2027:
.size _ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st, .-_ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st
.globl _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
.type _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii, @function
_Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii, .-_Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
.globl _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.type _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, @function
_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, .-_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.globl _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st
.type _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st, @function
_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movl 96(%rsp), %r14d
movl 104(%rsp), %r15d
movl %r8d, %ecx
imull %r14d, %ecx
movl %edx, %eax
cltd
idivl %ecx
movl %eax, 8(%rsp)
movl %r9d, %ecx
imull %r15d, %ecx
movl %ebp, %eax
cltd
idivl %ecx
movl %eax, 12(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 24(%rsp)
movq 112(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
jmp .L24
.cfi_endproc
.LFE2028:
.size _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st, .-_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii"
.align 8
.LC6:
.string "_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1023410176
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <cuda_runtime.h>
namespace computation_playground {
__global__ void transpose2d_naive_kernel(float* in, float* out, int m, int n) {
int in_row_offet = blockIdx.x * blockDim.x + threadIdx.x;
if(in_row_offet < m) {
int in_global_offset = blockIdx.y * m + in_row_offet;
int out_global_offset = in_row_offet * n + blockIdx.y;
*(out + out_global_offset) = *(in + in_global_offset);
}
}
void transpose2d_naive(float* in, float* out, int m, int n, cudaStream_t stream) {
int threads_per_block = 32;
int blocks_per_row = std::ceil(m / float(threads_per_block));
dim3 grid(blocks_per_row, n);
transpose2d_naive_kernel<<<grid, threads_per_block, 0, stream>>>(in, out, m, n);
}
__global__ void transpose2d_tile_kernel(float* in, float* out, int m, int n,
int m_direction_iteration, int n_direction_iteration) {
for(int j = 0; j < n_direction_iteration; j++) {
for(int i = 0; i < m_direction_iteration; i++) {
int x = blockIdx.x * blockDim.x * m_direction_iteration + i * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y * n_direction_iteration + j * blockDim.y + threadIdx.y;
if(x < m && y < n) {
out[x * n + y] = in[y * m + x];
}
}
}
}
void transpose2d_tile(float* in, float* out, int m, int n, int tile_m_dim, int tile_n_dim,
int m_direction_iteration, int n_direction_iteration, cudaStream_t stream) {
dim3 grid(std::ceil(m / (tile_m_dim * m_direction_iteration)), std::ceil(n / (tile_n_dim * n_direction_iteration)));
dim3 block(tile_m_dim, tile_n_dim);
transpose2d_tile_kernel<<<grid, block, 0, stream>>>(in, out, m, n, m_direction_iteration, n_direction_iteration);
}
} // namespace computation_playground | #include <cmath>
#include <hip/hip_runtime.h>
namespace computation_playground {
__global__ void transpose2d_naive_kernel(float* in, float* out, int m, int n) {
int in_row_offet = blockIdx.x * blockDim.x + threadIdx.x;
if(in_row_offet < m) {
int in_global_offset = blockIdx.y * m + in_row_offet;
int out_global_offset = in_row_offet * n + blockIdx.y;
*(out + out_global_offset) = *(in + in_global_offset);
}
}
void transpose2d_naive(float* in, float* out, int m, int n, hipStream_t stream) {
int threads_per_block = 32;
int blocks_per_row = std::ceil(m / float(threads_per_block));
dim3 grid(blocks_per_row, n);
transpose2d_naive_kernel<<<grid, threads_per_block, 0, stream>>>(in, out, m, n);
}
__global__ void transpose2d_tile_kernel(float* in, float* out, int m, int n,
int m_direction_iteration, int n_direction_iteration) {
for(int j = 0; j < n_direction_iteration; j++) {
for(int i = 0; i < m_direction_iteration; i++) {
int x = blockIdx.x * blockDim.x * m_direction_iteration + i * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y * n_direction_iteration + j * blockDim.y + threadIdx.y;
if(x < m && y < n) {
out[x * n + y] = in[y * m + x];
}
}
}
}
void transpose2d_tile(float* in, float* out, int m, int n, int tile_m_dim, int tile_n_dim,
int m_direction_iteration, int n_direction_iteration, hipStream_t stream) {
dim3 grid(std::ceil(m / (tile_m_dim * m_direction_iteration)), std::ceil(n / (tile_n_dim * n_direction_iteration)));
dim3 block(tile_m_dim, tile_n_dim);
transpose2d_tile_kernel<<<grid, block, 0, stream>>>(in, out, m, n, m_direction_iteration, n_direction_iteration);
}
} // namespace computation_playground |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <cmath>
#include <hip/hip_runtime.h>
namespace computation_playground {
__global__ void transpose2d_naive_kernel(float* in, float* out, int m, int n) {
int in_row_offet = blockIdx.x * blockDim.x + threadIdx.x;
if(in_row_offet < m) {
int in_global_offset = blockIdx.y * m + in_row_offet;
int out_global_offset = in_row_offet * n + blockIdx.y;
*(out + out_global_offset) = *(in + in_global_offset);
}
}
void transpose2d_naive(float* in, float* out, int m, int n, hipStream_t stream) {
int threads_per_block = 32;
int blocks_per_row = std::ceil(m / float(threads_per_block));
dim3 grid(blocks_per_row, n);
transpose2d_naive_kernel<<<grid, threads_per_block, 0, stream>>>(in, out, m, n);
}
__global__ void transpose2d_tile_kernel(float* in, float* out, int m, int n,
int m_direction_iteration, int n_direction_iteration) {
for(int j = 0; j < n_direction_iteration; j++) {
for(int i = 0; i < m_direction_iteration; i++) {
int x = blockIdx.x * blockDim.x * m_direction_iteration + i * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y * n_direction_iteration + j * blockDim.y + threadIdx.y;
if(x < m && y < n) {
out[x * n + y] = in[y * m + x];
}
}
}
}
void transpose2d_tile(float* in, float* out, int m, int n, int tile_m_dim, int tile_n_dim,
int m_direction_iteration, int n_direction_iteration, hipStream_t stream) {
dim3 grid(std::ceil(m / (tile_m_dim * m_direction_iteration)), std::ceil(n / (tile_n_dim * n_direction_iteration)));
dim3 block(tile_m_dim, tile_n_dim);
transpose2d_tile_kernel<<<grid, block, 0, stream>>>(in, out, m, n, m_direction_iteration, n_direction_iteration);
}
} // namespace computation_playground | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.globl _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.p2align 8
.type _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii,@function
_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_mov_b32 s2, s15
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b32 s0, s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s0, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, .Lfunc_end0-_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.globl _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.p2align 8
.type _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii,@function
_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii:
s_load_b32 s10, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB1_8
s_clause 0x2
s_load_b32 s11, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s11, 0
s_mul_i32 s14, s14, s11
s_cselect_b32 s13, -1, 0
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
s_mul_i32 s1, s15, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s15, s1
s_branch .LBB1_3
.LBB1_2:
s_set_inst_prefetch_distance 0x2
s_add_i32 s12, s12, 1
s_add_i32 s15, s15, 1
s_cmp_eq_u32 s12, s10
s_cbranch_scc1 .LBB1_8
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB1_2
s_load_b32 s0, s[8:9], 0xc
s_add_i32 s17, s1, s12
s_mov_b32 s18, s11
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s0, 0xffff
s_lshr_b32 s0, s0, 16
v_mad_u64_u32 v[2:3], null, s14, s16, v[1:2]
v_mad_u64_u32 v[6:7], null, s15, s0, v[0:1]
v_mad_u64_u32 v[7:8], null, s17, s0, v[0:1]
s_mul_i32 s17, s3, s16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, s2, v6
v_mad_u64_u32 v[3:4], null, s3, v2, v[6:7]
v_cmp_gt_i32_e32 vcc_lo, s3, v7
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v2, s16, v2
v_add_nc_u32_e32 v3, s17, v3
s_add_i32 s18, s18, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, 0
s_cbranch_scc1 .LBB1_2
.LBB1_6:
v_cmp_gt_i32_e64 s0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s19, s0
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v6, v5, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s6, v6
v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
s_branch .LBB1_5
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, .Lfunc_end1-_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <cmath>
#include <hip/hip_runtime.h>
namespace computation_playground {
__global__ void transpose2d_naive_kernel(float* in, float* out, int m, int n) {
int in_row_offet = blockIdx.x * blockDim.x + threadIdx.x;
if(in_row_offet < m) {
int in_global_offset = blockIdx.y * m + in_row_offet;
int out_global_offset = in_row_offet * n + blockIdx.y;
*(out + out_global_offset) = *(in + in_global_offset);
}
}
void transpose2d_naive(float* in, float* out, int m, int n, hipStream_t stream) {
int threads_per_block = 32;
int blocks_per_row = std::ceil(m / float(threads_per_block));
dim3 grid(blocks_per_row, n);
transpose2d_naive_kernel<<<grid, threads_per_block, 0, stream>>>(in, out, m, n);
}
__global__ void transpose2d_tile_kernel(float* in, float* out, int m, int n,
int m_direction_iteration, int n_direction_iteration) {
for(int j = 0; j < n_direction_iteration; j++) {
for(int i = 0; i < m_direction_iteration; i++) {
int x = blockIdx.x * blockDim.x * m_direction_iteration + i * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y * n_direction_iteration + j * blockDim.y + threadIdx.y;
if(x < m && y < n) {
out[x * n + y] = in[y * m + x];
}
}
}
}
void transpose2d_tile(float* in, float* out, int m, int n, int tile_m_dim, int tile_n_dim,
int m_direction_iteration, int n_direction_iteration, hipStream_t stream) {
dim3 grid(std::ceil(m / (tile_m_dim * m_direction_iteration)), std::ceil(n / (tile_n_dim * n_direction_iteration)));
dim3 block(tile_m_dim, tile_n_dim);
transpose2d_tile_kernel<<<grid, block, 0, stream>>>(in, out, m, n, m_direction_iteration, n_direction_iteration);
}
} // namespace computation_playground | .text
.file "tranpose2d.hip"
.globl _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii # -- Begin function _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.p2align 4, 0x90
.type _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii,@function
_ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii: # @_ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii, .Lfunc_end0-_ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.p2align 4, 0x90
.type _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t,@function
_ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t: # @_ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r12
movl %ecx, %ebx
movl %edx, %ebp
cvtsi2ss %edx, %xmm0
movq %rsi, %r14
movq %rdi, %r15
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rbx, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $4294967328, %rdx # imm = 0x100000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq %r12, %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t, .Lfunc_end1-_ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.cfi_endproc
# -- End function
.globl _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii # -- Begin function _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.p2align 4, 0x90
.type _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii,@function
_ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii: # @_ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii, .Lfunc_end2-_ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.cfi_endproc
# -- End function
.globl _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t # -- Begin function _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t
.p2align 4, 0x90
.type _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t,@function
_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t: # @_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r10d
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movl 200(%rsp), %r12d
movl 192(%rsp), %r13d
movq 208(%rsp), %r9
movl %r13d, %ecx
imull %r8d, %ecx
movl %edx, %eax
cltd
idivl %ecx
movl %eax, %edi
movl %r12d, %ecx
imull %r10d, %ecx
movl %ebx, %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
shlq $32, %rax
orq %rax, %rdi
movl %r8d, %edx
shlq $32, %r10
orq %r10, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movl %r13d, 4(%rsp)
movl %r12d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t, .Lfunc_end3-_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii,@object # @_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.section .rodata,"a",@progbits
.globl _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.p2align 3, 0x0
_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii:
.quad _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.size _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, 8
.type _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii,@object # @_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.globl _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.p2align 3, 0x0
_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii:
.quad _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.size _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii"
.size .L__unnamed_1, 62
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii"
.size .L__unnamed_2, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.addrsig_sym _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.addrsig_sym _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x000fd400000001ff */
/*0020*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f03270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f03270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ S2UR UR12, SR_CTAID.X ; /* 0x00000000000c79c3 */
/* 0x000e220000002500 */
/*0070*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*00a0*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000ea20000002200 */
/*00b0*/ ULDC UR6, c[0x0][0x174] ; /* 0x00005d0000067ab9 */
/* 0x000fe40000000800 */
/*00c0*/ S2UR UR13, SR_CTAID.Y ; /* 0x00000000000d79c3 */
/* 0x000ee20000002600 */
/*00d0*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fe40000000800 */
/*00e0*/ UIMAD UR6, UR5, UR6, URZ ; /* 0x00000006050672a4 */
/* 0x000fe2000f8e023f */
/*00f0*/ IADD3 R3, -R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ ULOP3.LUT UR11, UR7, 0x3, URZ, 0xc0, !UPT ; /* 0x00000003070b7892 */
/* 0x000fc4000f8ec03f */
/*0110*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0130*/ ULDC.64 UR14, c[0x0][0x118] ; /* 0x00004600000e7ab9 */
/* 0x000fe40000000a00 */
/*0140*/ UIMAD UR9, UR12, UR7, 0x2 ; /* 0x000000020c0974a4 */
/* 0x001fe4000f8e0207 */
/*0150*/ UIMAD UR10, UR12, UR7, 0x1 ; /* 0x000000010c0a74a4 */
/* 0x000fe4000f8e0207 */
/*0160*/ UIMAD UR5, UR12, UR5, URZ ; /* 0x000000050c0572a4 */
/* 0x000fe4000f8e023f */
/*0170*/ UIMAD UR8, UR12, UR7, 0x3 ; /* 0x000000030c0874a4 */
/* 0x000fe2000f8e0207 */
/*0180*/ MOV R5, UR9 ; /* 0x0000000900057c02 */
/* 0x000fe20008000f00 */
/*0190*/ UIADD3 UR7, UR11, -UR7, URZ ; /* 0x800000070b077290 */
/* 0x000fe2000fffe03f */
/*01a0*/ MOV R7, UR10 ; /* 0x0000000a00077c02 */
/* 0x000fc40008000f00 */
/*01b0*/ MOV R9, UR5 ; /* 0x0000000500097c02 */
/* 0x000fe20008000f00 */
/*01c0*/ IMAD.U32 R3, RZ, RZ, UR8 ; /* 0x00000008ff037e24 */
/* 0x000fe4000f8e00ff */
/*01d0*/ IMAD R5, R5, c[0x0][0x0], R0.reuse ; /* 0x0000000005057a24 */
/* 0x102fe400078e0200 */
/*01e0*/ IMAD R3, R3, c[0x0][0x0], R0.reuse ; /* 0x0000000003037a24 */
/* 0x100fe400078e0200 */
/*01f0*/ IMAD R7, R7, c[0x0][0x0], R0.reuse ; /* 0x0000000007077a24 */
/* 0x100fe400078e0200 */
/*0200*/ IMAD R9, R9, c[0x0][0x178], R0 ; /* 0x00005e0009097a24 */
/* 0x000fe400078e0200 */
/*0210*/ IMAD R4, R3, c[0x0][0x174], R2 ; /* 0x00005d0003047a24 */
/* 0x004fc400078e0202 */
/*0220*/ IMAD R6, R5, c[0x0][0x174], R2.reuse ; /* 0x00005d0005067a24 */
/* 0x100fe400078e0202 */
/*0230*/ IMAD R8, R7, c[0x0][0x174], R2.reuse ; /* 0x00005d0007087a24 */
/* 0x100fe400078e0202 */
/*0240*/ IMAD R10, R9, c[0x0][0x174], R2 ; /* 0x00005d00090a7a24 */
/* 0x008fe400078e0202 */
/*0250*/ ULDC UR9, c[0x0][0x17c] ; /* 0x00005f0000097ab9 */
/* 0x000fe40000000800 */
/*0260*/ UIMAD UR8, UR13, UR9, UR4 ; /* 0x000000090d0872a4 */
/* 0x000fe4000f8e0204 */
/*0270*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe4000fffe03f */
/*0280*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc40008000000 */
/*0290*/ IMAD.U32 R11, RZ, RZ, UR8 ; /* 0x00000008ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*02a0*/ UISETP.GE.AND UP0, UPT, UR4, UR9, UPT ; /* 0x000000090400728c */
/* 0x000fc6000bf06270 */
/*02b0*/ IMAD R12, R11, c[0x0][0x4], R2 ; /* 0x000001000b0c7a24 */
/* 0x001fe200078e0202 */
/*02c0*/ @!P1 BRA 0x6a0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*02d0*/ MOV R21, UR8 ; /* 0x0000000800157c02 */
/* 0x000fe20008000f00 */
/*02e0*/ IMAD.U32 R17, RZ, RZ, UR8 ; /* 0x00000008ff117e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ MOV R15, UR8 ; /* 0x00000008000f7c02 */
/* 0x000fe20008000f00 */
/*0300*/ IMAD R22, R12.reuse, c[0x0][0x170], R3 ; /* 0x00005c000c167a24 */
/* 0x040fe200078e0203 */
/*0310*/ MOV R27, UR8 ; /* 0x00000008001b7c02 */
/* 0x000fe20008000f00 */
/*0320*/ IMAD R11, R12.reuse, c[0x0][0x170], R5 ; /* 0x00005c000c0b7a24 */
/* 0x040fe200078e0205 */
/*0330*/ ISETP.GE.AND P0, PT, R12.reuse, c[0x0][0x174], PT ; /* 0x00005d000c007a0c */
/* 0x040fe20003f06270 */
/*0340*/ IMAD R13, R12.reuse, c[0x0][0x170], R7 ; /* 0x00005c000c0d7a24 */
/* 0x040fe200078e0207 */
/*0350*/ MOV R23, R9 ; /* 0x0000000900177202 */
/* 0x000fe20000000f00 */
/*0360*/ IMAD R20, R12, c[0x0][0x170], R9 ; /* 0x00005c000c147a24 */
/* 0x000fe200078e0209 */
/*0370*/ MOV R24, R7 ; /* 0x0000000700187202 */
/* 0x000fe20000000f00 */
/*0380*/ IMAD.MOV.U32 R29, RZ, RZ, R3 ; /* 0x000000ffff1d7224 */
/* 0x000fe200078e0003 */
/*0390*/ MOV R25, R5 ; /* 0x0000000500197202 */
/* 0x000fe20000000f00 */
/*03a0*/ IMAD R21, R21, c[0x0][0x4], R4 ; /* 0x0000010015157a24 */
/* 0x000fe200078e0204 */
/*03b0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*03c0*/ IMAD R26, R15, c[0x0][0x4], R6 ; /* 0x000001000f1a7a24 */
/* 0x000fc400078e0206 */
/*03d0*/ IMAD R27, R27, c[0x0][0x4], R8 ; /* 0x000001001b1b7a24 */
/* 0x000fe400078e0208 */
/*03e0*/ IMAD R28, R17, c[0x0][0x4], R10 ; /* 0x00000100111c7a24 */
/* 0x000fe400078e020a */
/*03f0*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x170], P0 ; /* 0x00005c0017007a0c */
/* 0x000fda0000766670 */
/*0400*/ @!P3 MOV R19, 0x4 ; /* 0x000000040013b802 */
/* 0x000fca0000000f00 */
/*0410*/ @!P3 IMAD.WIDE R14, R20, R19, c[0x0][0x160] ; /* 0x00005800140eb625 */
/* 0x000fca00078e0213 */
/*0420*/ @!P3 LDG.E R17, [R14.64] ; /* 0x0000000e0e11b981 */
/* 0x0000a2000c1e1900 */
/*0430*/ ISETP.GE.OR P2, PT, R24, c[0x0][0x170], P0 ; /* 0x00005c0018007a0c */
/* 0x000fe20000746670 */
/*0440*/ @!P3 IMAD.WIDE R14, R28, R19, c[0x0][0x168] ; /* 0x00005a001c0eb625 */
/* 0x001fd800078e0213 */
/*0450*/ @!P2 MOV R16, 0x4 ; /* 0x000000040010a802 */
/* 0x000fca0000000f00 */
/*0460*/ @!P2 IMAD.WIDE R18, R13, R16.reuse, c[0x0][0x160] ; /* 0x000058000d12a625 */
/* 0x080fe200078e0210 */
/*0470*/ @!P3 STG.E [R14.64], R17 ; /* 0x000000110e00b986 */
/* 0x0041ea000c10190e */
/*0480*/ @!P2 LDG.E R19, [R18.64] ; /* 0x0000000e1213a981 */
/* 0x000ea2000c1e1900 */
/*0490*/ ISETP.GE.OR P3, PT, R25, c[0x0][0x170], P0 ; /* 0x00005c0019007a0c */
/* 0x000fe20000766670 */
/*04a0*/ @!P2 IMAD.WIDE R16, R27, R16, c[0x0][0x168] ; /* 0x00005a001b10a625 */
/* 0x001fca00078e0210 */
/*04b0*/ @!P2 STG.E [R16.64], R19 ; /* 0x000000131000a986 */
/* 0x0041ee000c10190e */
/*04c0*/ @!P3 MOV R16, 0x4 ; /* 0x000000040010b802 */
/* 0x001fca0000000f00 */
/*04d0*/ @!P3 IMAD.WIDE R14, R11, R16, c[0x0][0x160] ; /* 0x000058000b0eb625 */
/* 0x000fca00078e0210 */
/*04e0*/ @!P3 LDG.E R18, [R14.64] ; /* 0x0000000e0e12b981 */
/* 0x0000a2000c1e1900 */
/*04f0*/ ISETP.GE.OR P2, PT, R29, c[0x0][0x170], P0 ; /* 0x00005c001d007a0c */
/* 0x000fe20000746670 */
/*0500*/ @!P3 IMAD.WIDE R14, R26, R16, c[0x0][0x168] ; /* 0x00005a001a0eb625 */
/* 0x001fca00078e0210 */
/*0510*/ @!P3 STG.E [R14.64], R18 ; /* 0x000000120e00b986 */
/* 0x0041ee000c10190e */
/*0520*/ @!P2 IMAD.MOV.U32 R18, RZ, RZ, 0x4 ; /* 0x00000004ff12a424 */
/* 0x001fc800078e00ff */
/*0530*/ @!P2 IMAD.WIDE R16, R22, R18, c[0x0][0x160] ; /* 0x000058001610a625 */
/* 0x000fcc00078e0212 */
/*0540*/ @!P2 LDG.E R17, [R16.64] ; /* 0x0000000e1011a981 */
/* 0x0000a2000c1e1900 */
/*0550*/ UIADD3 UR5, UR5, 0x4, URZ ; /* 0x0000000405057890 */
/* 0x000fe2000fffe03f */
/*0560*/ @!P2 IMAD.WIDE R18, R21, R18, c[0x0][0x168] ; /* 0x00005a001512a625 */
/* 0x000fe200078e0212 */
/*0570*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe40008000f00 */
/*0580*/ UIADD3 UR8, UR7, UR5, URZ ; /* 0x0000000507087290 */
/* 0x000fe2000fffe03f */
/*0590*/ MOV R15, UR6 ; /* 0x00000006000f7c02 */
/* 0x000fe40008000f00 */
/*05a0*/ IMAD R21, R14.reuse, 0x4, R21 ; /* 0x000000040e157824 */
/* 0x040fe200078e0215 */
/*05b0*/ LEA R27, R14, R27, 0x2 ; /* 0x0000001b0e1b7211 */
/* 0x000fe400078e10ff */
/*05c0*/ MOV R16, c[0x0][0x0] ; /* 0x0000000000107a02 */
/* 0x001fc40000000f00 */
/*05d0*/ LEA R26, R15, R26, 0x2 ; /* 0x0000001a0f1a7211 */
/* 0x000fe400078e10ff */
/*05e0*/ LEA R29, R16.reuse, R29, 0x2 ; /* 0x0000001d101d7211 */
/* 0x040fe200078e10ff */
/*05f0*/ IMAD R24, R16.reuse, 0x4, R24 ; /* 0x0000000410187824 */
/* 0x040fe200078e0218 */
/*0600*/ LEA R25, R16.reuse, R25, 0x2 ; /* 0x0000001910197211 */
/* 0x040fe200078e10ff */
/*0610*/ IMAD R13, R16.reuse, 0x4, R13 ; /* 0x00000004100d7824 */
/* 0x040fe200078e020d */
/*0620*/ LEA R23, R16.reuse, R23, 0x2 ; /* 0x0000001710177211 */
/* 0x040fe400078e10ff */
/*0630*/ LEA R22, R16.reuse, R22, 0x2 ; /* 0x0000001610167211 */
/* 0x040fe400078e10ff */
/*0640*/ LEA R11, R16, R11, 0x2 ; /* 0x0000000b100b7211 */
/* 0x000fc400078e10ff */
/*0650*/ LEA R20, R16, R20, 0x2 ; /* 0x0000001410147211 */
/* 0x000fe400078e10ff */
/*0660*/ LEA R28, R15, R28, 0x2 ; /* 0x0000001c0f1c7211 */
/* 0x000fe200078e10ff */
/*0670*/ @!P2 STG.E [R18.64], R17 ; /* 0x000000111200a986 */
/* 0x0041e2000c10190e */
/*0680*/ ISETP.NE.AND P2, PT, RZ, UR8, PT ; /* 0x00000008ff007c0c */
/* 0x000fda000bf45270 */
/*0690*/ @P2 BRA 0x3f0 ; /* 0xfffffd5000002947 */
/* 0x001fea000383ffff */
/*06a0*/ ISETP.NE.AND P0, PT, RZ, UR11, PT ; /* 0x0000000bff007c0c */
/* 0x000fda000bf05270 */
/*06b0*/ @!P0 BRA 0x9e0 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*06c0*/ ULDC UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fe20000000800 */
/*06d0*/ ISETP.GE.AND P0, PT, R12, c[0x0][0x174], PT ; /* 0x00005d000c007a0c */
/* 0x000fe20003f06270 */
/*06e0*/ UIMAD UR5, UR12, UR8, UR5 ; /* 0x000000080c0572a4 */
/* 0x000fe2000f8e0205 */
/*06f0*/ BSSY B0, 0x7c0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0700*/ MOV R11, UR5 ; /* 0x00000005000b7c02 */
/* 0x000fca0008000f00 */
/*0710*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x000fca00078e0200 */
/*0720*/ ISETP.GE.OR P2, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000746670 */
/*0730*/ @P2 BRA 0x7b0 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*0740*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe400078e00ff */
/*0750*/ IMAD R14, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0e7a24 */
/* 0x000fc800078e020b */
/*0760*/ IMAD.WIDE R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e0211 */
/*0770*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*0780*/ IMAD R16, R11, c[0x0][0x174], R12 ; /* 0x00005d000b107a24 */
/* 0x000fc800078e020c */
/*0790*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fca00078e0211 */
/*07a0*/ STG.E [R16.64], R15 ; /* 0x0000000f10007986 */
/* 0x0041e4000c10190e */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ UISETP.NE.AND UP1, UPT, UR11, 0x1, UPT ; /* 0x000000010b00788c */
/* 0x000fcc000bf25270 */
/*07d0*/ PLOP3.LUT P2, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f4f018 */
/*07e0*/ @!P2 BRA 0x9e0 ; /* 0x000001f00000a947 */
/* 0x000fea0003800000 */
/*07f0*/ UIADD3 UR8, UR5, 0x1, URZ ; /* 0x0000000105087890 */
/* 0x000fe2000fffe03f */
/*0800*/ BSSY B0, 0x8d0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0810*/ MOV R11, UR8 ; /* 0x00000008000b7c02 */
/* 0x000fca0008000f00 */
/*0820*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x000fca00078e0200 */
/*0830*/ ISETP.GE.OR P2, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000746670 */
/*0840*/ @P2 BRA 0x8c0 ; /* 0x0000007000002947 */
/* 0x000fea0003800000 */
/*0850*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x001fe200000001ff */
/*0860*/ IMAD R14, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0e7a24 */
/* 0x000fd200078e020b */
/*0870*/ IMAD.WIDE R14, R14, R17, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e0211 */
/*0880*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*0890*/ IMAD R16, R11, c[0x0][0x174], R12 ; /* 0x00005d000b107a24 */
/* 0x000fc800078e020c */
/*08a0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x000fca00078e0211 */
/*08b0*/ STG.E [R16.64], R15 ; /* 0x0000000f10007986 */
/* 0x0041e4000c10190e */
/*08c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08d0*/ UISETP.NE.AND UP1, UPT, UR11, 0x2, UPT ; /* 0x000000020b00788c */
/* 0x000fcc000bf25270 */
/*08e0*/ PLOP3.LUT P2, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f4f018 */
/*08f0*/ @!P2 BRA 0x9e0 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0900*/ UIADD3 UR5, UR5, 0x2, URZ ; /* 0x0000000205057890 */
/* 0x000fe2000fffe03f */
/*0910*/ BSSY B0, 0x9e0 ; /* 0x000000c000007945 */
/* 0x000fea0003800000 */
/*0920*/ MOV R11, UR5 ; /* 0x00000005000b7c02 */
/* 0x000fca0008000f00 */
/*0930*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x000fca00078e0200 */
/*0940*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x170], P0 ; /* 0x00005c000b007a0c */
/* 0x000fda0000706670 */
/*0950*/ @P0 BRA 0x9d0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fe20000000f00 */
/*0970*/ IMAD R14, R12, c[0x0][0x170], R11 ; /* 0x00005c000c0e7a24 */
/* 0x000fc800078e020b */
/*0980*/ IMAD.WIDE R14, R14, R13, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x001fcc00078e020d */
/*0990*/ LDG.E R15, [R14.64] ; /* 0x0000000e0e0f7981 */
/* 0x000ea2000c1e1900 */
/*09a0*/ IMAD R12, R11, c[0x0][0x174], R12 ; /* 0x00005d000b0c7a24 */
/* 0x000fc800078e020c */
/*09b0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fca00078e020d */
/*09c0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0041e4000c10190e */
/*09d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*09e0*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*09f0*/ @!P0 BRA 0x250 ; /* 0xfffff85000008947 */
/* 0x000fea000383ffff */
/*0a00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a10*/ BRA 0xa10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x001fd000078e0200 */
/*00a0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD R4, R0, c[0x0][0x174], R5 ; /* 0x00005d0000047a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.globl _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.p2align 8
.type _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii,@function
_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_mov_b32 s2, s15
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
s_load_b32 s0, s[0:1], 0x14
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v1, s0, s[2:3]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, .Lfunc_end0-_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.globl _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.p2align 8
.type _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii,@function
_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii:
s_load_b32 s10, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB1_8
s_clause 0x2
s_load_b32 s11, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s11, 0
s_mul_i32 s14, s14, s11
s_cselect_b32 s13, -1, 0
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
s_mul_i32 s1, s15, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s15, s1
s_branch .LBB1_3
.LBB1_2:
s_set_inst_prefetch_distance 0x2
s_add_i32 s12, s12, 1
s_add_i32 s15, s15, 1
s_cmp_eq_u32 s12, s10
s_cbranch_scc1 .LBB1_8
.LBB1_3:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB1_2
s_load_b32 s0, s[8:9], 0xc
s_add_i32 s17, s1, s12
s_mov_b32 s18, s11
s_waitcnt lgkmcnt(0)
s_and_b32 s16, s0, 0xffff
s_lshr_b32 s0, s0, 16
v_mad_u64_u32 v[2:3], null, s14, s16, v[1:2]
v_mad_u64_u32 v[6:7], null, s15, s0, v[0:1]
v_mad_u64_u32 v[7:8], null, s17, s0, v[0:1]
s_mul_i32 s17, s3, s16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, s2, v6
v_mad_u64_u32 v[3:4], null, s3, v2, v[6:7]
v_cmp_gt_i32_e32 vcc_lo, s3, v7
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v2, s16, v2
v_add_nc_u32_e32 v3, s17, v3
s_add_i32 s18, s18, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, 0
s_cbranch_scc1 .LBB1_2
.LBB1_6:
v_cmp_gt_i32_e64 s0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s19, s0
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v6, v5, v2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
global_load_b32 v8, v[6:7], off
v_lshlrev_b64 v[6:7], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s6, v6
v_add_co_ci_u32_e64 v7, s0, s7, v7, s0
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
s_branch .LBB1_5
.LBB1_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, .Lfunc_end1-_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a1a50_00000000-6_tranpose2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
.type _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii, @function
_Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii, .-_Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
.globl _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.type _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, @function
_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, .-_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.globl _ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st
.type _ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st, @function
_ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movq %r8, %r9
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2sil %xmm3, %eax
movl %eax, 8(%rsp)
movl %ebp, 12(%rsp)
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z75__device_stub__ZN22computation_playground24transpose2d_naive_kernelEPfS0_iiPfS_ii
jmp .L11
.cfi_endproc
.LFE2027:
.size _ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st, .-_ZN22computation_playground17transpose2d_naiveEPfS0_iiP11CUstream_st
.globl _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
.type _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii, @function
_Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii, .-_Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
.globl _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.type _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, @function
_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, .-_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.globl _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st
.type _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st, @function
_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st:
.LFB2028:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebx
movl %ecx, %ebp
movl 96(%rsp), %r14d
movl 104(%rsp), %r15d
movl %r8d, %ecx
imull %r14d, %ecx
movl %edx, %eax
cltd
idivl %ecx
movl %eax, 8(%rsp)
movl %r9d, %ecx
imull %r15d, %ecx
movl %ebp, %eax
cltd
idivl %ecx
movl %eax, 12(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 24(%rsp)
movq 112(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L24:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl %r15d, %r9d
movl %r14d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z76__device_stub__ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiiiPfS_iiii
jmp .L24
.cfi_endproc
.LFE2028:
.size _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st, .-_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii"
.align 8
.LC6:
.string "_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1023410176
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tranpose2d.hip"
.globl _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii # -- Begin function _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.p2align 4, 0x90
.type _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii,@function
_ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii: # @_ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii, .Lfunc_end0-_ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.p2align 4, 0x90
.type _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t,@function
_ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t: # @_ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r12
movl %ecx, %ebx
movl %edx, %ebp
cvtsi2ss %edx, %xmm0
movq %rsi, %r14
movq %rdi, %r15
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %eax
movq %rbx, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $4294967328, %rdx # imm = 0x100000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
movq %r12, %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t, .Lfunc_end1-_ZN22computation_playground17transpose2d_naiveEPfS0_iiP12ihipStream_t
.cfi_endproc
# -- End function
.globl _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii # -- Begin function _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.p2align 4, 0x90
.type _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii,@function
_ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii: # @_ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii, .Lfunc_end2-_ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.cfi_endproc
# -- End function
.globl _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t # -- Begin function _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t
.p2align 4, 0x90
.type _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t,@function
_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t: # @_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r10d
movl %ecx, %ebx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movl 200(%rsp), %r12d
movl 192(%rsp), %r13d
movq 208(%rsp), %r9
movl %r13d, %ecx
imull %r8d, %ecx
movl %edx, %eax
cltd
idivl %ecx
movl %eax, %edi
movl %r12d, %ecx
imull %r10d, %ecx
movl %ebx, %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
shlq $32, %rax
orq %rax, %rdi
movl %r8d, %edx
shlq $32, %r10
orq %r10, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
movl %ebx, 8(%rsp)
movl %r13d, 4(%rsp)
movl %r12d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t, .Lfunc_end3-_ZN22computation_playground16transpose2d_tileEPfS0_iiiiiiP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii,@object # @_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.section .rodata,"a",@progbits
.globl _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.p2align 3, 0x0
_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii:
.quad _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.size _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii, 8
.type _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii,@object # @_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.globl _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.p2align 3, 0x0
_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii:
.quad _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.size _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii"
.size .L__unnamed_1, 62
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii"
.size .L__unnamed_2, 63
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZN22computation_playground39__device_stub__transpose2d_naive_kernelEPfS0_ii
.addrsig_sym _ZN22computation_playground38__device_stub__transpose2d_tile_kernelEPfS0_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZN22computation_playground24transpose2d_naive_kernelEPfS0_ii
.addrsig_sym _ZN22computation_playground23transpose2d_tile_kernelEPfS0_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*******************************************************************************
* serveral useful gpu functions will be defined in this file to facilitate
* the surface redistance scheme
******************************************************************************/
typedef struct
{
double sR;
double sL;
} double_eno_derivative;
__device__ inline
double max2(double x, double y)
{
return (x<y) ? y : x;
}
__device__ inline
double min2(double x, double y)
{
return (x<y) ? x : y;
}
__device__ inline
double min_mod(double x, double y)
{
return (x*y<0) ? 0.0 : (fabs(x)<fabs(y) ? x : y);
}
__device__ inline
double sign(double x)
{
return (x>0) ? 1.0 : -1.0;
}
__device__ inline
void advection_velocity(double & H1, double & H2, double & H3, double & normal_d, double sign, double Dx, double Dy, double Dz, double nx, double ny, double nz)
{
normal_d = nx * Dx + ny * Dy + nz * Dz;
H1 = sign * (Dx - nx * normal_d);
H2 = sign * (Dy - ny * normal_d);
H3 = sign * (Dz - nz * normal_d);
double H_mag = sqrt(H1*H1+H2*H2+H3*H3);
H1 = H1/H_mag;
H2 = H2/H_mag;
H3 = H3/H_mag;
}
__device__ inline
void Upwind_Hamiltonian(double & Hamil, double normal_d, double sign, double Dx, double Dy, double Dz)
{
// numerical error can lead to negative value inside sqrt()
// the following code is needed to avoid NAN due to sqrt of a negative number
Hamil = sign* ( sqrt( max2(0,Dx*Dx+Dy*Dy+Dz*Dz-normal_d*normal_d) ) - 1);
}
// convert subindex to linear index
// periodic boundary conditions are assumed
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{
int row_idxn = min2(rows-1, max2(0, row_idx));
int col_idxn = min2(cols-1, max2(0, col_idx));
int pge_idxn = min2(pges-1, max2(0, pge_idx));
int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;
return ind;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
double vr = (pr==ds) ? v2 : 0;
eno_d.sR = (vr - v0) / pr - pr * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
double vl = (pl==ds) ? v1 : 0;
eno_d.sL = (v0 - vl) / pl + pl * p2m;
return eno_d;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
* without boundary correction
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative_field( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
eno_d.sR = (v2 - v0) / ds - ds * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
eno_d.sL = (v0 - v1) / ds + ds * p2m;
return eno_d;
}
// calculate surface redistance step with central upwind scheme without higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_1st(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// AND WITHOUT boundary correction
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_noboundaryfix(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative_field( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative_field( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative_field( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
} | .file "tmpxft_0017ccda_00000000-6_enork2_surface_redistance.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2060:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq 384(%rsp), %rax
movq %rax, 72(%rsp)
movq 392(%rsp), %rax
movq %rax, 64(%rsp)
movq 400(%rsp), %rax
movq %rax, 56(%rsp)
movq 408(%rsp), %rax
movq %rax, 48(%rsp)
movq 416(%rsp), %rax
movq %rax, 40(%rsp)
movq 424(%rsp), %rax
movq %rax, 32(%rsp)
movq 432(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 40(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 440(%rsp), %rax
movq %rax, 296(%rsp)
leaq 448(%rsp), %rax
movq %rax, 304(%rsp)
leaq 456(%rsp), %rax
movq %rax, 312(%rsp)
leaq 16(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
movq %rsp, %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
leaq 136(%rsp), %rcx
leaq 128(%rsp), %rdx
leaq 156(%rsp), %rsi
leaq 144(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 136(%rsp)
.cfi_def_cfa_offset 392
pushq 136(%rsp)
.cfi_def_cfa_offset 400
leaq 208(%rsp), %r9
movq 172(%rsp), %rcx
movl 180(%rsp), %r8d
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
leaq _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2061:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2062:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq 384(%rsp), %rax
movq %rax, 72(%rsp)
movq 392(%rsp), %rax
movq %rax, 64(%rsp)
movq 400(%rsp), %rax
movq %rax, 56(%rsp)
movq 408(%rsp), %rax
movq %rax, 48(%rsp)
movq 416(%rsp), %rax
movq %rax, 40(%rsp)
movq 424(%rsp), %rax
movq %rax, 32(%rsp)
movq 432(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 40(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 440(%rsp), %rax
movq %rax, 296(%rsp)
leaq 448(%rsp), %rax
movq %rax, 304(%rsp)
leaq 456(%rsp), %rax
movq %rax, 312(%rsp)
leaq 16(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
movq %rsp, %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
leaq 136(%rsp), %rcx
leaq 128(%rsp), %rdx
leaq 156(%rsp), %rsi
leaq 144(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 136(%rsp)
.cfi_def_cfa_offset 392
pushq 136(%rsp)
.cfi_def_cfa_offset 400
leaq 208(%rsp), %r9
movq 172(%rsp), %rcx
movl 180(%rsp), %r8d
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
leaq _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2063:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2064:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq 384(%rsp), %rax
movq %rax, 72(%rsp)
movq 392(%rsp), %rax
movq %rax, 64(%rsp)
movq 400(%rsp), %rax
movq %rax, 56(%rsp)
movq 408(%rsp), %rax
movq %rax, 48(%rsp)
movq 416(%rsp), %rax
movq %rax, 40(%rsp)
movq 424(%rsp), %rax
movq %rax, 32(%rsp)
movq 432(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 40(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 440(%rsp), %rax
movq %rax, 296(%rsp)
leaq 448(%rsp), %rax
movq %rax, 304(%rsp)
leaq 456(%rsp), %rax
movq %rax, 312(%rsp)
leaq 16(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
movq %rsp, %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
leaq 136(%rsp), %rcx
leaq 128(%rsp), %rdx
leaq 156(%rsp), %rsi
leaq 144(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 136(%rsp)
.cfi_def_cfa_offset 392
pushq 136(%rsp)
.cfi_def_cfa_offset 400
leaq 208(%rsp), %r9
movq 172(%rsp), %rcx
movl 180(%rsp), %r8d
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
leaq _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2065:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.align 8
.LC1:
.string "_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.align 8
.LC2:
.string "_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*******************************************************************************
* serveral useful gpu functions will be defined in this file to facilitate
* the surface redistance scheme
******************************************************************************/
typedef struct
{
double sR;
double sL;
} double_eno_derivative;
__device__ inline
double max2(double x, double y)
{
return (x<y) ? y : x;
}
__device__ inline
double min2(double x, double y)
{
return (x<y) ? x : y;
}
__device__ inline
double min_mod(double x, double y)
{
return (x*y<0) ? 0.0 : (fabs(x)<fabs(y) ? x : y);
}
__device__ inline
double sign(double x)
{
return (x>0) ? 1.0 : -1.0;
}
__device__ inline
void advection_velocity(double & H1, double & H2, double & H3, double & normal_d, double sign, double Dx, double Dy, double Dz, double nx, double ny, double nz)
{
normal_d = nx * Dx + ny * Dy + nz * Dz;
H1 = sign * (Dx - nx * normal_d);
H2 = sign * (Dy - ny * normal_d);
H3 = sign * (Dz - nz * normal_d);
double H_mag = sqrt(H1*H1+H2*H2+H3*H3);
H1 = H1/H_mag;
H2 = H2/H_mag;
H3 = H3/H_mag;
}
__device__ inline
void Upwind_Hamiltonian(double & Hamil, double normal_d, double sign, double Dx, double Dy, double Dz)
{
// numerical error can lead to negative value inside sqrt()
// the following code is needed to avoid NAN due to sqrt of a negative number
Hamil = sign* ( sqrt( max2(0,Dx*Dx+Dy*Dy+Dz*Dz-normal_d*normal_d) ) - 1);
}
// convert subindex to linear index
// periodic boundary conditions are assumed
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{
int row_idxn = min2(rows-1, max2(0, row_idx));
int col_idxn = min2(cols-1, max2(0, col_idx));
int pge_idxn = min2(pges-1, max2(0, pge_idx));
int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;
return ind;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
double vr = (pr==ds) ? v2 : 0;
eno_d.sR = (vr - v0) / pr - pr * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
double vl = (pl==ds) ? v1 : 0;
eno_d.sL = (v0 - vl) / pl + pl * p2m;
return eno_d;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
* without boundary correction
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative_field( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
eno_d.sR = (v2 - v0) / ds - ds * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
eno_d.sL = (v0 - v1) / ds + ds * p2m;
return eno_d;
}
// calculate surface redistance step with central upwind scheme without higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_1st(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// AND WITHOUT boundary correction
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_noboundaryfix(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative_field( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative_field( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative_field( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
} | #include <hip/hip_runtime.h>
/*******************************************************************************
* serveral useful gpu functions will be defined in this file to facilitate
* the surface redistance scheme
******************************************************************************/
typedef struct
{
double sR;
double sL;
} double_eno_derivative;
__device__ inline
double max2(double x, double y)
{
return (x<y) ? y : x;
}
__device__ inline
double min2(double x, double y)
{
return (x<y) ? x : y;
}
__device__ inline
double min_mod(double x, double y)
{
return (x*y<0) ? 0.0 : (fabs(x)<fabs(y) ? x : y);
}
__device__ inline
double sign(double x)
{
return (x>0) ? 1.0 : -1.0;
}
__device__ inline
void advection_velocity(double & H1, double & H2, double & H3, double & normal_d, double sign, double Dx, double Dy, double Dz, double nx, double ny, double nz)
{
normal_d = nx * Dx + ny * Dy + nz * Dz;
H1 = sign * (Dx - nx * normal_d);
H2 = sign * (Dy - ny * normal_d);
H3 = sign * (Dz - nz * normal_d);
double H_mag = sqrt(H1*H1+H2*H2+H3*H3);
H1 = H1/H_mag;
H2 = H2/H_mag;
H3 = H3/H_mag;
}
__device__ inline
void Upwind_Hamiltonian(double & Hamil, double normal_d, double sign, double Dx, double Dy, double Dz)
{
// numerical error can lead to negative value inside sqrt()
// the following code is needed to avoid NAN due to sqrt of a negative number
Hamil = sign* ( sqrt( max2(0,Dx*Dx+Dy*Dy+Dz*Dz-normal_d*normal_d) ) - 1);
}
// convert subindex to linear index
// periodic boundary conditions are assumed
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{
int row_idxn = min2(rows-1, max2(0, row_idx));
int col_idxn = min2(cols-1, max2(0, col_idx));
int pge_idxn = min2(pges-1, max2(0, pge_idx));
int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;
return ind;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
double vr = (pr==ds) ? v2 : 0;
eno_d.sR = (vr - v0) / pr - pr * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
double vl = (pl==ds) ? v1 : 0;
eno_d.sL = (v0 - vl) / pl + pl * p2m;
return eno_d;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
* without boundary correction
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative_field( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
eno_d.sR = (v2 - v0) / ds - ds * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
eno_d.sL = (v0 - v1) / ds + ds * p2m;
return eno_d;
}
// calculate surface redistance step with central upwind scheme without higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_1st(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// AND WITHOUT boundary correction
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_noboundaryfix(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative_field( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative_field( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative_field( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*******************************************************************************
* serveral useful gpu functions will be defined in this file to facilitate
* the surface redistance scheme
******************************************************************************/
typedef struct
{
double sR;
double sL;
} double_eno_derivative;
__device__ inline
double max2(double x, double y)
{
return (x<y) ? y : x;
}
__device__ inline
double min2(double x, double y)
{
return (x<y) ? x : y;
}
__device__ inline
double min_mod(double x, double y)
{
return (x*y<0) ? 0.0 : (fabs(x)<fabs(y) ? x : y);
}
__device__ inline
double sign(double x)
{
return (x>0) ? 1.0 : -1.0;
}
__device__ inline
void advection_velocity(double & H1, double & H2, double & H3, double & normal_d, double sign, double Dx, double Dy, double Dz, double nx, double ny, double nz)
{
normal_d = nx * Dx + ny * Dy + nz * Dz;
H1 = sign * (Dx - nx * normal_d);
H2 = sign * (Dy - ny * normal_d);
H3 = sign * (Dz - nz * normal_d);
double H_mag = sqrt(H1*H1+H2*H2+H3*H3);
H1 = H1/H_mag;
H2 = H2/H_mag;
H3 = H3/H_mag;
}
__device__ inline
void Upwind_Hamiltonian(double & Hamil, double normal_d, double sign, double Dx, double Dy, double Dz)
{
// numerical error can lead to negative value inside sqrt()
// the following code is needed to avoid NAN due to sqrt of a negative number
Hamil = sign* ( sqrt( max2(0,Dx*Dx+Dy*Dy+Dz*Dz-normal_d*normal_d) ) - 1);
}
// convert subindex to linear index
// periodic boundary conditions are assumed
__device__ inline
int sub2ind(int row_idx, int col_idx, int pge_idx, int rows, int cols, int pges)
{
int row_idxn = min2(rows-1, max2(0, row_idx));
int col_idxn = min2(cols-1, max2(0, col_idx));
int pge_idxn = min2(pges-1, max2(0, pge_idx));
int ind = pge_idxn * rows * cols + col_idxn * rows + row_idxn;
return ind;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
double vr = (pr==ds) ? v2 : 0;
eno_d.sR = (vr - v0) / pr - pr * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
double vl = (pl==ds) ? v1 : 0;
eno_d.sL = (v0 - vl) / pl + pl * p2m;
return eno_d;
}
/******************************************************************************
* calculate Eno derivatives at node v0: [v4,v1,v0,v2,v3]
* without boundary correction
******************************************************************************/
__device__ inline
double_eno_derivative eno_derivative_field( double v4, double v1, double v0, double v2, double v3, double pr, double pl, double ds)
{
double p2m;
double_eno_derivative eno_d;
double p2 = v1 - 2.0 * v0 + v2;
double p2r = v0 - 2.0 * v2 + v3;
p2m = 0.5 * min_mod(p2, p2r) / pow(ds, 2);
eno_d.sR = (v2 - v0) / ds - ds * p2m;
double p2l = v0 - 2.0 * v1 + v4;
p2m = 0.5 * min_mod(p2, p2l) / pow(ds, 2);
eno_d.sL = (v0 - v1) / ds + ds * p2m;
return eno_d;
}
// calculate surface redistance step with central upwind scheme without higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_1st(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
}
// calculate surface redistance step with central upwind scheme with higher order term
// AND WITHOUT boundary correction
// now lsf represents the auxilary level set function(not the level set function)
// inputs : the auxilary level set function, sign of the initial level set function, distance to the interface, normal vectors
__global__
void surface_redistance_step_noboundaryfix(double * step, double const * lsf, double const * sign, double const * deltat, double const * nx, double const * ny, double const * nz, double const * xpr, double const * xpl, double const * ypf, double const * ypb, double const * zpu, double const * zpd, int rows, int cols, int pges, double dx, double dy, double dz, int num_ele)
{
int row_idx = blockIdx.x * blockDim.x + threadIdx.x;
int col_idx = blockIdx.y * blockDim.y + threadIdx.y;
int pge_idx = blockIdx.z * blockDim.z + threadIdx.z;
if(row_idx >= rows || col_idx >= cols || pge_idx >= pges){
return;
}
int ind = sub2ind(row_idx, col_idx, pge_idx, rows, cols, pges);
int right = sub2ind(row_idx, col_idx+1, pge_idx, rows, cols, pges);
int right2 = sub2ind(row_idx, col_idx+2, pge_idx, rows, cols, pges);
int left = sub2ind(row_idx, col_idx-1, pge_idx, rows, cols, pges);
int left2 = sub2ind(row_idx, col_idx-2, pge_idx, rows, cols, pges);
double_eno_derivative eno_dx = eno_derivative_field( lsf[left2], lsf[left], lsf[ind], lsf[right], lsf[right2], xpr[ind], xpl[ind], dx);
double Dx[2] = {eno_dx.sR, eno_dx.sL};
int front = sub2ind(row_idx+1, col_idx, pge_idx, rows, cols, pges);
int front2 = sub2ind(row_idx+2, col_idx, pge_idx, rows, cols, pges);
int back = sub2ind(row_idx-1, col_idx, pge_idx, rows, cols, pges);
int back2 = sub2ind(row_idx-2, col_idx, pge_idx, rows, cols, pges);
double_eno_derivative eno_dy = eno_derivative_field( lsf[back2], lsf[back], lsf[ind], lsf[front], lsf[front2], ypf[ind], ypb[ind], dy); double Dy[2] = {eno_dy.sR, eno_dy.sL};
int up = sub2ind(row_idx, col_idx, pge_idx+1, rows, cols, pges);
int up2 = sub2ind(row_idx, col_idx, pge_idx+2, rows, cols, pges);
int down = sub2ind(row_idx, col_idx, pge_idx-1, rows, cols, pges);
int down2 = sub2ind(row_idx, col_idx, pge_idx-2, rows, cols, pges);
double_eno_derivative eno_dz = eno_derivative_field( lsf[down2], lsf[down], lsf[ind], lsf[up], lsf[up2], zpu[ind], zpd[ind], dz);
double Dz[2] = {eno_dz.sR, eno_dz.sL};
double Nx = nx[ind];
double Ny = ny[ind];
double Nz = nz[ind];
double Sign = sign[ind];
// different choices yield different upwind direction
int const choice_x[8]={0,0,0,0,1,1,1,1};
int const choice_y[8]={0,0,1,1,0,0,1,1};
int const choice_z[8]={0,1,0,1,0,1,0,1};
double Hamiltonian[8]={0,0,0,0,0,0,0,0};
// a[0],a[1] is the magnitude of the maximum forward and backward
// information propagation speed in the x direction. b for y and c for z direction
double a[2]={0,0};
double b[2]={0,0};
double c[2]={0,0};
for(int i=0;i<8;i++){
double dr_x = Dx[choice_x[i]];
double dr_y = Dy[choice_y[i]];
double dr_z = Dz[choice_z[i]];
double H1,H2,H3, normal_d;
advection_velocity(H1,H2,H3,normal_d,Sign,dr_x,dr_y,dr_z,Nx,Ny,Nz);
Upwind_Hamiltonian(Hamiltonian[i],normal_d,Sign,dr_x,dr_y,dr_z);
a[0] = max2(a[0],max2(H1,0));
b[0] = max2(b[0],max2(H2,0));
c[0] = max2(c[0],max2(H3,0));
a[1] = fabs(min2(-a[1],min2(H1,0)));
b[1] = fabs(min2(-b[1],min2(H2,0)));
c[1] = fabs(min2(-c[1],min2(H3,0)));
}
// calculate the numerical Hamiltonian
//double epsilon=1e-6;
double numerical_Hamiltonian = 0;
double denominator = (a[0]+a[1])*(b[0]+b[1])*(c[0]+c[1]);
int const choice_a[8]={1,1,1,1,0,0,0,0};
int const choice_b[8]={1,1,0,0,1,1,0,0};
int const choice_c[8]={1,0,1,0,1,0,1,0};
for(int i=0;i<8;i++){
double H_a = a[choice_a[i]];
double H_b = b[choice_b[i]];
double H_c = c[choice_c[i]];
numerical_Hamiltonian += H_a * H_b * H_c * Hamiltonian[i];
}
numerical_Hamiltonian = numerical_Hamiltonian/denominator;
numerical_Hamiltonian += - a[0]*a[1]*(Dx[0]-Dx[1])/(a[0]+a[1]) - b[0]*b[1]*(Dy[0]-Dy[1])/(b[0]+b[1]) - c[0]*c[1]*(Dz[0]-Dz[1])/(c[0]+c[1]);
//
// calculate higher order terms
double psi_x_int_pp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[0]-Hamiltonian[4]) ) / (a[0]+a[1]) ;
double psi_x_int_mm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[3]-Hamiltonian[7]) ) / (a[0]+a[1]) ;
double psi_x_int_pm = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[1]-Hamiltonian[5]) ) / (a[0]+a[1]) ;
double psi_x_int_mp = ( (a[0]*Dx[0]+a[1]*Dx[1]) - (Hamiltonian[2]-Hamiltonian[6]) ) / (a[0]+a[1]) ;
double dx_pp = min_mod(Dx[0]-psi_x_int_pp,psi_x_int_pp-Dx[1]);
double dx_mm = min_mod(Dx[0]-psi_x_int_mm,psi_x_int_mm-Dx[1]);
double dx_pm = min_mod(Dx[0]-psi_x_int_pm,psi_x_int_pm-Dx[1]);
double dx_mp = min_mod(Dx[0]-psi_x_int_mp,psi_x_int_mp-Dx[1]);
double x_c = b[0]*c[0]*dx_mm + b[1]*c[1]*dx_pp + b[0]*c[1]*dx_mp + b[1]*c[0]*dx_pm;
double psi_y_int_pp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[0]-Hamiltonian[2]) ) / (b[0]+b[1]) ;
double psi_y_int_mm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[5]-Hamiltonian[7]) ) / (b[0]+b[1]) ;
double psi_y_int_pm = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[1]-Hamiltonian[3]) ) / (b[0]+b[1]) ;
double psi_y_int_mp = ( (b[0]*Dy[0]+b[1]*Dy[1]) - (Hamiltonian[4]-Hamiltonian[6]) ) / (b[0]+b[1]) ;
double dy_pp = min_mod(Dy[0]-psi_y_int_pp,psi_y_int_pp-Dy[1]);
double dy_mm = min_mod(Dy[0]-psi_y_int_mm,psi_y_int_mm-Dy[1]);
double dy_pm = min_mod(Dy[0]-psi_y_int_pm,psi_y_int_pm-Dy[1]);
double dy_mp = min_mod(Dy[0]-psi_y_int_mp,psi_y_int_mp-Dy[1]);
double y_c = a[0]*c[0]*dy_mm + a[1]*c[1]*dy_pp + a[0]*c[1]*dy_mp + a[1]*c[0]*dy_pm;
double psi_z_int_pp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[0]-Hamiltonian[1]) ) / (c[0]+c[1]) ;
double psi_z_int_mm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[6]-Hamiltonian[7]) ) / (c[0]+c[1]) ;
double psi_z_int_pm = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[2]-Hamiltonian[3]) ) / (c[0]+c[1]) ;
double psi_z_int_mp = ( (c[0]*Dz[0]+c[1]*Dz[1]) - (Hamiltonian[4]-Hamiltonian[5]) ) / (c[0]+c[1]) ;
double dz_pp = min_mod(Dz[0]-psi_z_int_pp,psi_z_int_pp-Dz[1]);
double dz_mm = min_mod(Dz[0]-psi_z_int_mm,psi_z_int_mm-Dz[1]);
double dz_pm = min_mod(Dz[0]-psi_z_int_pm,psi_z_int_pm-Dz[1]);
double dz_mp = min_mod(Dz[0]-psi_z_int_mp,psi_z_int_mp-Dz[1]);
double z_c = a[0]*b[0]*dz_mm + a[1]*b[1]*dz_pp + a[0]*b[1]*dz_mp + a[1]*b[0]*dz_pm;
numerical_Hamiltonian += (a[0]*a[1]*x_c + b[0]*b[1]*y_c + c[0]*c[1]*z_c) / denominator;
//
step[ind] = numerical_Hamiltonian * deltat[ind];
} | .text
.file "enork2_surface_redistance.hip"
.globl _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 4, 0x90
.type _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end0-_Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_endproc
# -- End function
.globl _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 4, 0x90
.type _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end1:
.size _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end1-_Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_endproc
# -- End function
.globl _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 4, 0x90
.type _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end2:
.size _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end2-_Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.section .rodata,"a",@progbits
.globl _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 3, 0x0
_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.quad _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.size _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8
.type _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 3, 0x0
_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.quad _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.size _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8
.type _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 3, 0x0
_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.quad _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.size _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.size .L__unnamed_1, 77
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.size .L__unnamed_2, 73
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.size .L__unnamed_3, 87
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017ccda_00000000-6_enork2_surface_redistance.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2060:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq 384(%rsp), %rax
movq %rax, 72(%rsp)
movq 392(%rsp), %rax
movq %rax, 64(%rsp)
movq 400(%rsp), %rax
movq %rax, 56(%rsp)
movq 408(%rsp), %rax
movq %rax, 48(%rsp)
movq 416(%rsp), %rax
movq %rax, 40(%rsp)
movq 424(%rsp), %rax
movq %rax, 32(%rsp)
movq 432(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 40(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 440(%rsp), %rax
movq %rax, 296(%rsp)
leaq 448(%rsp), %rax
movq %rax, 304(%rsp)
leaq 456(%rsp), %rax
movq %rax, 312(%rsp)
leaq 16(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
movq %rsp, %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
leaq 136(%rsp), %rcx
leaq 128(%rsp), %rdx
leaq 156(%rsp), %rsi
leaq 144(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 136(%rsp)
.cfi_def_cfa_offset 392
pushq 136(%rsp)
.cfi_def_cfa_offset 400
leaq 208(%rsp), %r9
movq 172(%rsp), %rcx
movl 180(%rsp), %r8d
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
leaq _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2061:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z90__device_stub__Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2062:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq 384(%rsp), %rax
movq %rax, 72(%rsp)
movq 392(%rsp), %rax
movq %rax, 64(%rsp)
movq 400(%rsp), %rax
movq %rax, 56(%rsp)
movq 408(%rsp), %rax
movq %rax, 48(%rsp)
movq 416(%rsp), %rax
movq %rax, 40(%rsp)
movq 424(%rsp), %rax
movq %rax, 32(%rsp)
movq 432(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 40(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 440(%rsp), %rax
movq %rax, 296(%rsp)
leaq 448(%rsp), %rax
movq %rax, 304(%rsp)
leaq 456(%rsp), %rax
movq %rax, 312(%rsp)
leaq 16(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
movq %rsp, %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
leaq 136(%rsp), %rcx
leaq 128(%rsp), %rdx
leaq 156(%rsp), %rsi
leaq 144(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 136(%rsp)
.cfi_def_cfa_offset 392
pushq 136(%rsp)
.cfi_def_cfa_offset 400
leaq 208(%rsp), %r9
movq 172(%rsp), %rcx
movl 180(%rsp), %r8d
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
leaq _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2063:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z86__device_stub__Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2064:
.cfi_startproc
endbr64
subq $376, %rsp
.cfi_def_cfa_offset 384
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 16(%rsp)
movsd %xmm1, 8(%rsp)
movsd %xmm2, (%rsp)
movq 384(%rsp), %rax
movq %rax, 72(%rsp)
movq 392(%rsp), %rax
movq %rax, 64(%rsp)
movq 400(%rsp), %rax
movq %rax, 56(%rsp)
movq 408(%rsp), %rax
movq %rax, 48(%rsp)
movq 416(%rsp), %rax
movq %rax, 40(%rsp)
movq 424(%rsp), %rax
movq %rax, 32(%rsp)
movq 432(%rsp), %rax
movq %rax, 24(%rsp)
movq %fs:40, %rax
movq %rax, 360(%rsp)
xorl %eax, %eax
leaq 120(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 96(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 80(%rsp), %rax
movq %rax, 232(%rsp)
leaq 72(%rsp), %rax
movq %rax, 240(%rsp)
leaq 64(%rsp), %rax
movq %rax, 248(%rsp)
leaq 56(%rsp), %rax
movq %rax, 256(%rsp)
leaq 48(%rsp), %rax
movq %rax, 264(%rsp)
leaq 40(%rsp), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rax
movq %rax, 280(%rsp)
leaq 24(%rsp), %rax
movq %rax, 288(%rsp)
leaq 440(%rsp), %rax
movq %rax, 296(%rsp)
leaq 448(%rsp), %rax
movq %rax, 304(%rsp)
leaq 456(%rsp), %rax
movq %rax, 312(%rsp)
leaq 16(%rsp), %rax
movq %rax, 320(%rsp)
leaq 8(%rsp), %rax
movq %rax, 328(%rsp)
movq %rsp, %rax
movq %rax, 336(%rsp)
leaq 464(%rsp), %rax
movq %rax, 344(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
leaq 136(%rsp), %rcx
leaq 128(%rsp), %rdx
leaq 156(%rsp), %rsi
leaq 144(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 360(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $376, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 136(%rsp)
.cfi_def_cfa_offset 392
pushq 136(%rsp)
.cfi_def_cfa_offset 400
leaq 208(%rsp), %r9
movq 172(%rsp), %rcx
movl 180(%rsp), %r8d
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
leaq _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 384
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.type _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, @function
_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.LFB2065:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 104(%rsp)
.cfi_def_cfa_offset 64
pushq 104(%rsp)
.cfi_def_cfa_offset 72
pushq 104(%rsp)
.cfi_def_cfa_offset 80
pushq 104(%rsp)
.cfi_def_cfa_offset 88
pushq 104(%rsp)
.cfi_def_cfa_offset 96
pushq 104(%rsp)
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
call _Z100__device_stub__Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddiPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
addq $104, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .-_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.align 8
.LC1:
.string "_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.align 8
.LC2:
.string "_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "enork2_surface_redistance.hip"
.globl _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 4, 0x90
.type _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end0-_Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_endproc
# -- End function
.globl _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 4, 0x90
.type _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end1:
.size _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end1-_Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_endproc
# -- End function
.globl _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi # -- Begin function _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 4, 0x90
.type _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@function
_Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi: # @_Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movq %rdi, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
movsd %xmm0, 72(%rsp)
movsd %xmm1, 64(%rsp)
movsd %xmm2, 56(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 304(%rsp), %rax
movq %rax, 176(%rsp)
leaq 312(%rsp), %rax
movq %rax, 184(%rsp)
leaq 320(%rsp), %rax
movq %rax, 192(%rsp)
leaq 328(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 360(%rsp), %rax
movq %rax, 232(%rsp)
leaq 368(%rsp), %rax
movq %rax, 240(%rsp)
leaq 376(%rsp), %rax
movq %rax, 248(%rsp)
leaq 72(%rsp), %rax
movq %rax, 256(%rsp)
leaq 64(%rsp), %rax
movq %rax, 264(%rsp)
leaq 56(%rsp), %rax
movq %rax, 272(%rsp)
leaq 384(%rsp), %rax
movq %rax, 280(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end2:
.size _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, .Lfunc_end2-_Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.section .rodata,"a",@progbits
.globl _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 3, 0x0
_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.quad _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.size _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8
.type _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 3, 0x0
_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.quad _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.size _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8
.type _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi,@object # @_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.globl _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.p2align 3, 0x0
_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi:
.quad _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.size _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.size .L__unnamed_1, 77
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.size .L__unnamed_2, 73
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi"
.size .L__unnamed_3, 87
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z38__device_stub__surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z52__device_stub__surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27surface_redistance_step_1stPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z23surface_redistance_stepPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym _Z37surface_redistance_step_noboundaryfixPdPKdS1_S1_S1_S1_S1_S1_S1_S1_S1_S1_S1_iiidddi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gMaxPoolingForward(float* out, int outRows, int outCols, float* in, int inRows, int inCols, float* mask, int numKernels, int maskCols, int width, int lastWidth) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid >= outRows * outCols)
return;
int rowId = tid / outRows;
int colId = tid % outRows;
float* b = in + (rowId * inCols) + (colId * width);
float* localMask = mask + (rowId / numKernels) * maskCols + colId * width;
if(colId == outRows - 1) {
width = lastWidth;
}
float currentMax = b[0] * localMask[0];
for(int i = 1; i < width; ++i) {
if(b[i] * localMask[i] > currentMax) {
currentMax = b[i] * localMask[i];
}
}
out[rowId + (colId * outCols)] = currentMax;
} | code for sm_80
Function : _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x168] ; /* 0x00005a0000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R9, c[0x0][0x188] ; /* 0x0000620000097a13 */
/* 0x000fe40000000000 */
/*00b0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*00c0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fc40007ffe0ff */
/*00e0*/ IABS R0, R11 ; /* 0x0000000b00007213 */
/* 0x000fc80000000000 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0120*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe400078e02ff */
/*0130*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e240000209400 */
/*0140*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0150*/ IMAD.HI.U32 R12, R3, R0, RZ ; /* 0x00000000030c7227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R2, RZ, RZ, -R12 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a0c */
/*0170*/ IMAD R0, R5.reuse, R2, R0 ; /* 0x0000000205007224 */
/* 0x040fe200078e0200 */
/*0180*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e280000001000 */
/*0190*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fe40003f24070 */
/*01a0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fd60007ffe0ff */
/*01b0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a05 */
/*01c0*/ @!P1 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c9810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000062000021f000 */
/*01e0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f25270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R0, R11, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000b007a12 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fcc00078e00ff */
/*0230*/ @P0 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c0810 */
/* 0x000fe20007ffe0ff */
/*0240*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x002fc800078e0a03 */
/*0250*/ IMAD R5, R0, R9, RZ ; /* 0x0000000900057224 */
/* 0x000fe400078e02ff */
/*0260*/ @!P2 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0ca224 */
/* 0x000fe200078e0a0c */
/*0270*/ @!P1 LOP3.LUT R12, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff0c9a12 */
/* 0x000fe200078e33ff */
/*0280*/ IMAD.HI.U32 R2, R3, R5, R2 ; /* 0x0000000503027227 */
/* 0x000fc600078e0002 */
/*0290*/ IABS R0, R12 ; /* 0x0000000c00007213 */
/* 0x000fe20000000000 */
/*02a0*/ IMAD R10, R12, c[0x0][0x17c], RZ ; /* 0x00005f000c0a7a24 */
/* 0x000fc800078e02ff */
/*02b0*/ IMAD.HI.U32 R2, R2, R0, RZ ; /* 0x0000000002027227 */
/* 0x000fe200078e00ff */
/*02c0*/ SHF.R.S32.HI R6, RZ, 0x1f, R10 ; /* 0x0000001fff067819 */
/* 0x000fc6000001140a */
/*02d0*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*02e0*/ IMAD R0, R9, R3, R0 ; /* 0x0000000309007224 */
/* 0x000fca00078e0200 */
/*02f0*/ ISETP.GT.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f24070 */
/*0300*/ @!P1 IMAD.IADD R0, R0, 0x1, -R9 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a09 */
/*0310*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fe40007ffe0ff */
/*0320*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe40003f25270 */
/*0330*/ ISETP.GE.U32.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x000fe40003f06070 */
/*0340*/ LOP3.LUT R0, R12, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x000062000c007a12 */
/* 0x000fc800078e3cff */
/*0350*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0360*/ IMAD.MOV R0, RZ, RZ, -R12 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a0c */
/*0370*/ IMAD R11, R0, c[0x0][0x168], R11 ; /* 0x00005a00000b7a24 */
/* 0x000fe400078e020b */
/*0380*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0390*/ IMAD R9, R11, c[0x0][0x190], RZ ; /* 0x000064000b097a24 */
/* 0x000fc800078e02ff */
/*03a0*/ @!P2 IMAD.MOV R2, RZ, RZ, -R2 ; /* 0x000000ffff02a224 */
/* 0x000fe200078e0a02 */
/*03b0*/ @!P1 LOP3.LUT R2, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff029a12 */
/* 0x000fe400078e33ff */
/*03c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R9 ; /* 0x0000001fff077819 */
/* 0x000fe40000011409 */
/*03d0*/ IADD3 R3, P0, R10, R9, RZ ; /* 0x000000090a037210 */
/* 0x000fe20007f1e0ff */
/*03e0*/ IMAD R8, R2, c[0x0][0x18c], RZ ; /* 0x0000630002087a24 */
/* 0x000fc800078e02ff */
/*03f0*/ IMAD.X R16, R6, 0x1, R7, P0 ; /* 0x0000000106107824 */
/* 0x000fe200000e0607 */
/*0400*/ SHF.R.S32.HI R0, RZ, 0x1f, R8 ; /* 0x0000001fff007819 */
/* 0x000fe40000011408 */
/*0410*/ IADD3 R5, P1, R9, R8, RZ ; /* 0x0000000809057210 */
/* 0x000fe40007f3e0ff */
/*0420*/ LEA R2, P0, R3, c[0x0][0x170], 0x2 ; /* 0x00005c0003027a11 */
/* 0x000fc600078010ff */
/*0430*/ IMAD.X R14, R7, 0x1, R0, P1 ; /* 0x00000001070e7824 */
/* 0x000fe200008e0600 */
/*0440*/ LEA R4, P1, R5, c[0x0][0x180], 0x2 ; /* 0x0000600005047a11 */
/* 0x000fe400078210ff */
/*0450*/ LEA.HI.X R3, R3, c[0x0][0x174], R16, 0x2, P0 ; /* 0x00005d0003037a11 */
/* 0x000fe400000f1410 */
/*0460*/ LEA.HI.X R5, R5, c[0x0][0x184], R14, 0x2, P1 ; /* 0x0000610005057a11 */
/* 0x000fc600008f140e */
/*0470*/ LDG.E R13, [R2.64] ; /* 0x00000006020d7981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x000ea2000c1e1900 */
/*0490*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*04a0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0e7624 */
/* 0x000fe200078e00ff */
/*04b0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*04c0*/ BSSY B2, 0x12f0 ; /* 0x00000e2000027945 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.NE.AND P0, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x000fc8000bf05270 */
/*04e0*/ SEL R15, R14, c[0x0][0x190], !P0 ; /* 0x000064000e0f7a07 */
/* 0x000fc80004000000 */
/*04f0*/ ISETP.GE.AND P0, PT, R15, 0x2, PT ; /* 0x000000020f00780c */
/* 0x000fe20003f06270 */
/*0500*/ FMUL R16, R16, R13 ; /* 0x0000000d10107220 */
/* 0x004fd80000400000 */
/*0510*/ @!P0 BRA 0x12e0 ; /* 0x00000dc000008947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R13, R15.reuse, -0x2, RZ ; /* 0xfffffffe0f0d7810 */
/* 0x040fe20007ffe0ff */
/*0530*/ BSSY B1, 0x1160 ; /* 0x00000c2000017945 */
/* 0x000fe20003800000 */
/*0540*/ IADD3 R14, R15, -0x1, RZ ; /* 0xffffffff0f0e7810 */
/* 0x000fe40007ffe0ff */
/*0550*/ ISETP.GE.U32.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */
/* 0x000fe20003f06070 */
/*0560*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe200078e00ff */
/*0570*/ LOP3.LUT R14, R14, 0x3, RZ, 0xc0, !PT ; /* 0x000000030e0e7812 */
/* 0x000fd600078ec0ff */
/*0580*/ @!P0 BRA 0x1150 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*0590*/ IMAD.IADD R15, R15, 0x1, -R14 ; /* 0x000000010f0f7824 */
/* 0x000fe200078e0a0e */
/*05a0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007f3e0ff */
/*05b0*/ BSSY B0, 0xf90 ; /* 0x000009d000007945 */
/* 0x000fe20003800000 */
/*05c0*/ IADD3 R4, P2, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007f5e0ff */
/*05d0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fe200078e00ff */
/*05e0*/ ISETP.GT.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe20003f04270 */
/*05f0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0600*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fd400010e0605 */
/*0610*/ @!P0 BRA 0xf80 ; /* 0x0000096000008947 */
/* 0x000fea0003800000 */
/*0620*/ IADD3 R17, R15, -0x1, RZ ; /* 0xffffffff0f117810 */
/* 0x000fe20007ffe0ff */
/*0630*/ BSSY B3, 0xc10 ; /* 0x000005d000037945 */
/* 0x000fe20003800000 */
/*0640*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0650*/ ISETP.GT.AND P1, PT, R17, 0xc, PT ; /* 0x0000000c1100780c */
/* 0x000fda0003f24270 */
/*0660*/ @!P1 BRA 0xc00 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*0670*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0680*/ LDG.E R17, [R4.64+-0x4] ; /* 0xfffffc0604117981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R18, [R2.64+-0xc] ; /* 0xfffff40602127981 */
/* 0x000ea8000c1e1900 */
/*06a0*/ LDG.E R25, [R4.64] ; /* 0x0000000604197981 */
/* 0x000ee8000c1e1900 */
/*06b0*/ LDG.E R26, [R2.64+-0x8] ; /* 0xfffff806021a7981 */
/* 0x000ee8000c1e1900 */
/*06c0*/ LDG.E R20, [R4.64+0x4] ; /* 0x0000040604147981 */
/* 0x000f28000c1e1900 */
/*06d0*/ LDG.E R21, [R2.64+-0x4] ; /* 0xfffffc0602157981 */
/* 0x000f28000c1e1900 */
/*06e0*/ LDG.E R22, [R4.64+0x8] ; /* 0x0000080604167981 */
/* 0x000f68000c1e1900 */
/*06f0*/ LDG.E R23, [R2.64] ; /* 0x0000000602177981 */
/* 0x000f68000c1e1900 */
/*0700*/ LDG.E R19, [R2.64+0x4] ; /* 0x0000040602137981 */
/* 0x000f22000c1e1900 */
/*0710*/ FMUL R17, R17, R18 ; /* 0x0000001211117220 */
/* 0x004fc60000400000 */
/*0720*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0604127981 */
/* 0x000ea4000c1e1900 */
/*0730*/ FSETP.GT.AND P1, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fc80003f24000 */
/*0740*/ FSEL R24, R17, R16, P1 ; /* 0x0000001011187208 */
/* 0x000fe40000800000 */
/*0750*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100604107981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080602117981 */
/* 0x000ea2000c1e1900 */
/*0770*/ FMUL R25, R25, R26 ; /* 0x0000001a19197220 */
/* 0x008fca0000400000 */
/*0780*/ FSETP.GT.AND P1, PT, R25, R24, PT ; /* 0x000000181900720b */
/* 0x000fe20003f24000 */
/*0790*/ FMUL R27, R22, R23 ; /* 0x00000017161b7220 */
/* 0x020fc60000400000 */
/*07a0*/ FSEL R24, R25, R24, P1 ; /* 0x0000001819187208 */
/* 0x000fe20000800000 */
/*07b0*/ FMUL R25, R20, R21 ; /* 0x0000001514197220 */
/* 0x010fe20000400000 */
/*07c0*/ LDG.E R22, [R4.64+0x18] ; /* 0x0000180604167981 */
/* 0x000ee8000c1e1900 */
/*07d0*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140604147981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0602157981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100602177981 */
/* 0x000ee2000c1e1900 */
/*0800*/ FSETP.GT.AND P1, PT, R25, R24, PT ; /* 0x000000181900720b */
/* 0x000fc80003f24000 */
/*0810*/ FSEL R24, R25, R24, P1 ; /* 0x0000001819187208 */
/* 0x000fc80000800000 */
/*0820*/ FSETP.GT.AND P1, PT, R27, R24, PT ; /* 0x000000181b00720b */
/* 0x000fc80003f24000 */
/*0830*/ FSEL R24, R27, R24, P1 ; /* 0x000000181b187208 */
/* 0x000fe20000800000 */
/*0840*/ FMUL R25, R18, R19 ; /* 0x0000001312197220 */
/* 0x004fe40000400000 */
/*0850*/ LDG.E R18, [R4.64+0x1c] ; /* 0x00001c0604127981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R19, [R2.64+0x14] ; /* 0x0000140602137981 */
/* 0x000ea2000c1e1900 */
/*0870*/ FSETP.GT.AND P1, PT, R25, R24, PT ; /* 0x000000181900720b */
/* 0x000fc80003f24000 */
/*0880*/ FSEL R24, R25, R24, P1 ; /* 0x0000001819187208 */
/* 0x000fe20000800000 */
/*0890*/ FMUL R25, R16, R17 ; /* 0x0000001110197220 */
/* 0x000fe40000400000 */
/*08a0*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200604107981 */
/* 0x000f68000c1e1900 */
/*08b0*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180602117981 */
/* 0x000f62000c1e1900 */
/*08c0*/ FSETP.GT.AND P1, PT, R25, R24, PT ; /* 0x000000181900720b */
/* 0x000fc80003f24000 */
/*08d0*/ FSEL R24, R25, R24, P1 ; /* 0x0000001819187208 */
/* 0x000fe20000800000 */
/*08e0*/ FMUL R25, R20, R21 ; /* 0x0000001514197220 */
/* 0x010fe40000400000 */
/*08f0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0602147981 */
/* 0x000f22000c1e1900 */
/*0900*/ FMUL R27, R22, R23 ; /* 0x00000017161b7220 */
/* 0x008fc60000400000 */
/*0910*/ LDG.E R23, [R4.64+0x24] ; /* 0x0000240604177981 */
/* 0x000f28000c1e1900 */
/*0920*/ LDG.E R22, [R4.64+0x28] ; /* 0x0000280604167981 */
/* 0x000ee8000c1e1900 */
/*0930*/ LDG.E R21, [R2.64+0x20] ; /* 0x0000200602157981 */
/* 0x000ee2000c1e1900 */
/*0940*/ FSETP.GT.AND P1, PT, R25, R24, PT ; /* 0x000000181900720b */
/* 0x000fc80003f24000 */
/*0950*/ FSEL R24, R25, R24, P1 ; /* 0x0000001819187208 */
/* 0x000fc80000800000 */
/*0960*/ FSETP.GT.AND P1, PT, R27, R24, PT ; /* 0x000000181b00720b */
/* 0x000fc80003f24000 */
/*0970*/ FSEL R24, R27, R24, P1 ; /* 0x000000181b187208 */
/* 0x000fe20000800000 */
/*0980*/ FMUL R25, R18, R19 ; /* 0x0000001312197220 */
/* 0x004fe40000400000 */
/*0990*/ LDG.E R19, [R4.64+0x2c] ; /* 0x00002c0604137981 */
/* 0x0000a8000c1e1900 */
/*09a0*/ LDG.E R18, [R2.64+0x24] ; /* 0x0000240602127981 */
/* 0x0002a2000c1e1900 */
/*09b0*/ FSETP.GT.AND P1, PT, R25, R24, PT ; /* 0x000000181900720b */
/* 0x000fc80003f24000 */
/*09c0*/ FSEL R24, R25, R24, P1 ; /* 0x0000001819187208 */
/* 0x000fe20000800000 */
/*09d0*/ FMUL R27, R16, R17 ; /* 0x00000011101b7220 */
/* 0x020fe20000400000 */
/*09e0*/ LDG.E R25, [R4.64+0x34] ; /* 0x0000340604197981 */
/* 0x000168000c1e1900 */
/*09f0*/ LDG.E R16, [R4.64+0x30] ; /* 0x0000300604107981 */
/* 0x000162000c1e1900 */
/*0a00*/ FSETP.GT.AND P1, PT, R27, R24, PT ; /* 0x000000181b00720b */
/* 0x000fc60003f24000 */
/*0a10*/ LDG.E R17, [R2.64+0x28] ; /* 0x0000280602117981 */
/* 0x000362000c1e1900 */
/*0a20*/ FSEL R26, R27, R24, P1 ; /* 0x000000181b1a7208 */
/* 0x000fc60000800000 */
/*0a30*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0602187981 */
/* 0x000362000c1e1900 */
/*0a40*/ FMUL R23, R23, R20 ; /* 0x0000001417177220 */
/* 0x010fc60000400000 */
/*0a50*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300602147981 */
/* 0x000322000c1e1900 */
/*0a60*/ FMUL R22, R22, R21 ; /* 0x0000001516167220 */
/* 0x008fc60000400000 */
/*0a70*/ LDG.E R21, [R4.64+0x38] ; /* 0x0000380604157981 */
/* 0x000122000c1e1900 */
/*0a80*/ FSETP.GT.AND P1, PT, R23, R26, PT ; /* 0x0000001a1700720b */
/* 0x000fc80003f24000 */
/*0a90*/ FSEL R23, R23, R26, P1 ; /* 0x0000001a17177208 */
/* 0x000fc80000800000 */
/*0aa0*/ FSETP.GT.AND P1, PT, R22, R23, PT ; /* 0x000000171600720b */
/* 0x000fc80003f24000 */
/*0ab0*/ FSEL R22, R22, R23, P1 ; /* 0x0000001716167208 */
/* 0x000fe40000800000 */
/*0ac0*/ IADD3 R15, R15, -0x10, RZ ; /* 0xfffffff00f0f7810 */
/* 0x000fc80007ffe0ff */
/*0ad0*/ ISETP.GT.AND P2, PT, R15, 0xd, PT ; /* 0x0000000d0f00780c */
/* 0x000fe40003f44270 */
/*0ae0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fe40007f7e0ff */
/*0af0*/ IADD3 R4, P4, R4, 0x40, RZ ; /* 0x0000004004047810 */
/* 0x001fe40007f9e0ff */
/*0b00*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe20007ffe0ff */
/*0b10*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fe400018e0603 */
/*0b20*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe400020e0605 */
/*0b30*/ FMUL R19, R19, R18 ; /* 0x0000001213137220 */
/* 0x004fca0000400000 */
/*0b40*/ FSETP.GT.AND P1, PT, R19, R22, PT ; /* 0x000000161300720b */
/* 0x000fc80003f24000 */
/*0b50*/ FSEL R19, R19, R22, P1 ; /* 0x0000001613137208 */
/* 0x000fe20000800000 */
/*0b60*/ FMUL R16, R16, R17 ; /* 0x0000001110107220 */
/* 0x020fca0000400000 */
/*0b70*/ FSETP.GT.AND P1, PT, R16, R19, PT ; /* 0x000000131000720b */
/* 0x000fe20003f24000 */
/*0b80*/ FMUL R25, R25, R24 ; /* 0x0000001819197220 */
/* 0x000fc60000400000 */
/*0b90*/ FSEL R16, R16, R19, P1 ; /* 0x0000001310107208 */
/* 0x000fc80000800000 */
/*0ba0*/ FSETP.GT.AND P1, PT, R25, R16, PT ; /* 0x000000101900720b */
/* 0x000fc80003f24000 */
/*0bb0*/ FSEL R16, R25, R16, P1 ; /* 0x0000001019107208 */
/* 0x000fe20000800000 */
/*0bc0*/ FMUL R21, R21, R20 ; /* 0x0000001415157220 */
/* 0x010fca0000400000 */
/*0bd0*/ FSETP.GT.AND P1, PT, R21, R16, PT ; /* 0x000000101500720b */
/* 0x000fc80003f24000 */
/*0be0*/ FSEL R16, R21, R16, P1 ; /* 0x0000001015107208 */
/* 0x000fe20000800000 */
/*0bf0*/ @P2 BRA 0x680 ; /* 0xfffffa8000002947 */
/* 0x000fea000383ffff */
/*0c00*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0c10*/ IADD3 R17, R15, -0x1, RZ ; /* 0xffffffff0f117810 */
/* 0x000fe20007ffe0ff */
/*0c20*/ BSSY B3, 0xf50 ; /* 0x0000032000037945 */
/* 0x000fe60003800000 */
/*0c30*/ ISETP.GT.AND P1, PT, R17, 0x4, PT ; /* 0x000000041100780c */
/* 0x000fda0003f24270 */
/*0c40*/ @!P1 BRA 0xf40 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0c50*/ LDG.E R21, [R4.64+-0x4] ; /* 0xfffffc0604157981 */
/* 0x000ea8000c1e1900 */
/*0c60*/ LDG.E R22, [R2.64+-0xc] ; /* 0xfffff40602167981 */
/* 0x000ea8000c1e1900 */
/*0c70*/ LDG.E R24, [R4.64] ; /* 0x0000000604187981 */
/* 0x000ee8000c1e1900 */
/*0c80*/ LDG.E R25, [R2.64+-0x8] ; /* 0xfffff80602197981 */
/* 0x000ee8000c1e1900 */
/*0c90*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040604137981 */
/* 0x000f28000c1e1900 */
/*0ca0*/ LDG.E R18, [R2.64+-0x4] ; /* 0xfffffc0602127981 */
/* 0x000f28000c1e1900 */
/*0cb0*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080604117981 */
/* 0x000f68000c1e1900 */
/*0cc0*/ LDG.E R20, [R2.64] ; /* 0x0000000602147981 */
/* 0x000f62000c1e1900 */
/*0cd0*/ FMUL R23, R21, R22 ; /* 0x0000001615177220 */
/* 0x004fc60000400000 */
/*0ce0*/ LDG.E R21, [R4.64+0xc] ; /* 0x00000c0604157981 */
/* 0x0000a8000c1e1900 */
/*0cf0*/ LDG.E R22, [R2.64+0x4] ; /* 0x0000040602167981 */
/* 0x0002a2000c1e1900 */
/*0d00*/ FSETP.GT.AND P0, PT, R23.reuse, R16.reuse, PT ; /* 0x000000101700720b */
/* 0x0c0fe20003f04000 */
/*0d10*/ FMUL R25, R24, R25 ; /* 0x0000001918197220 */
/* 0x008fe40000400000 */
/*0d20*/ LDG.E R24, [R2.64+0xc] ; /* 0x00000c0602187981 */
/* 0x0002e2000c1e1900 */
/*0d30*/ FSEL R26, R23, R16, P0 ; /* 0x00000010171a7208 */
/* 0x000fc60000000000 */
/*0d40*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100604107981 */
/* 0x0000e2000c1e1900 */
/*0d50*/ FSETP.GT.AND P0, PT, R25, R26, PT ; /* 0x0000001a1900720b */
/* 0x000fc60003f04000 */
/*0d60*/ LDG.E R23, [R2.64+0x8] ; /* 0x0000080602177981 */
/* 0x0002e2000c1e1900 */
/*0d70*/ FSEL R26, R25, R26, P0 ; /* 0x0000001a191a7208 */
/* 0x000fc60000000000 */
/*0d80*/ LDG.E R25, [R4.64+0x14] ; /* 0x0000140604197981 */
/* 0x0000e2000c1e1900 */
/*0d90*/ FMUL R19, R19, R18 ; /* 0x0000001213137220 */
/* 0x010fe40000400000 */
/*0da0*/ FMUL R20, R17, R20 ; /* 0x0000001411147220 */
/* 0x020fe20000400000 */
/*0db0*/ LDG.E R18, [R4.64+0x18] ; /* 0x0000180604127981 */
/* 0x000128000c1e1900 */
/*0dc0*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100602117981 */
/* 0x000322000c1e1900 */
/*0dd0*/ FSETP.GT.AND P0, PT, R19, R26, PT ; /* 0x0000001a1300720b */
/* 0x000fc80003f04000 */
/*0de0*/ FSEL R19, R19, R26, P0 ; /* 0x0000001a13137208 */
/* 0x000fc80000000000 */
/*0df0*/ FSETP.GT.AND P0, PT, R20, R19, PT ; /* 0x000000131400720b */
/* 0x000fc80003f04000 */
/*0e00*/ FSEL R19, R20, R19, P0 ; /* 0x0000001314137208 */
/* 0x000fe40000000000 */
/*0e10*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x002fe40007f5e0ff */
/*0e20*/ IADD3 R4, P3, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x001fe40007f7e0ff */
/*0e30*/ IADD3 R13, R13, 0x8, RZ ; /* 0x000000080d0d7810 */
/* 0x000fe20007ffe0ff */
/*0e40*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*0e50*/ IADD3 R15, R15, -0x8, RZ ; /* 0xfffffff80f0f7810 */
/* 0x000fe20007ffe0ff */
/*0e60*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe400018e0605 */
/*0e70*/ FMUL R22, R21, R22 ; /* 0x0000001615167220 */
/* 0x004fca0000400000 */
/*0e80*/ FSETP.GT.AND P0, PT, R22, R19, PT ; /* 0x000000131600720b */
/* 0x000fc80003f04000 */
/*0e90*/ FSEL R19, R22, R19, P0 ; /* 0x0000001316137208 */
/* 0x000fe20000000000 */
/*0ea0*/ FMUL R16, R16, R23 ; /* 0x0000001710107220 */
/* 0x008fca0000400000 */
/*0eb0*/ FSETP.GT.AND P0, PT, R16, R19, PT ; /* 0x000000131000720b */
/* 0x000fe20003f04000 */
/*0ec0*/ FMUL R25, R25, R24 ; /* 0x0000001819197220 */
/* 0x000fc60000400000 */
/*0ed0*/ FSEL R16, R16, R19, P0 ; /* 0x0000001310107208 */
/* 0x000fc80000000000 */
/*0ee0*/ FSETP.GT.AND P0, PT, R25, R16, PT ; /* 0x000000101900720b */
/* 0x000fe20003f04000 */
/*0ef0*/ FMUL R17, R18, R17 ; /* 0x0000001112117220 */
/* 0x010fc60000400000 */
/*0f00*/ FSEL R16, R25, R16, P0 ; /* 0x0000001019107208 */
/* 0x000fc80000000000 */
/*0f10*/ FSETP.GT.AND P1, PT, R17.reuse, R16.reuse, PT ; /* 0x000000101100720b */
/* 0x0c0fe40003f24000 */
/*0f20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0f30*/ FSEL R16, R17, R16, P1 ; /* 0x0000001011107208 */
/* 0x000fcc0000800000 */
/*0f40*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0f50*/ ISETP.NE.OR P0, PT, R15, 0x1, P0 ; /* 0x000000010f00780c */
/* 0x000fda0000705670 */
/*0f60*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0f70*/ @!P0 BRA 0x1150 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0f80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f90*/ LDG.E R17, [R4.64+-0x4] ; /* 0xfffffc0604117981 */
/* 0x0000a8000c1e1900 */
/*0fa0*/ LDG.E R18, [R2.64+-0xc] ; /* 0xfffff40602127981 */
/* 0x0002a8000c1e1900 */
/*0fb0*/ LDG.E R19, [R4.64] ; /* 0x0000000604137981 */
/* 0x0000e8000c1e1900 */
/*0fc0*/ LDG.E R20, [R2.64+-0x8] ; /* 0xfffff80602147981 */
/* 0x0002e8000c1e1900 */
/*0fd0*/ LDG.E R21, [R4.64+0x4] ; /* 0x0000040604157981 */
/* 0x000128000c1e1900 */
/*0fe0*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0602167981 */
/* 0x000328000c1e1900 */
/*0ff0*/ LDG.E R23, [R4.64+0x8] ; /* 0x0000080604177981 */
/* 0x000168000c1e1900 */
/*1000*/ LDG.E R24, [R2.64] ; /* 0x0000000602187981 */
/* 0x000362000c1e1900 */
/*1010*/ IADD3 R15, R15, -0x4, RZ ; /* 0xfffffffc0f0f7810 */
/* 0x000fc40007ffe0ff */
/*1020*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007ffe0ff */
/*1030*/ ISETP.NE.AND P1, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fe40003f25270 */
/*1040*/ IADD3 R4, P3, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x001fe40007f7e0ff */
/*1050*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x002fc60007f5e0ff */
/*1060*/ IMAD.X R5, RZ, RZ, R5, P3 ; /* 0x000000ffff057224 */
/* 0x000fe400018e0605 */
/*1070*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*1080*/ FMUL R17, R17, R18 ; /* 0x0000001211117220 */
/* 0x004fca0000400000 */
/*1090*/ FSETP.GT.AND P0, PT, R17, R16, PT ; /* 0x000000101100720b */
/* 0x000fe20003f04000 */
/*10a0*/ FMUL R19, R19, R20 ; /* 0x0000001413137220 */
/* 0x008fc60000400000 */
/*10b0*/ FSEL R16, R17, R16, P0 ; /* 0x0000001011107208 */
/* 0x000fc80000000000 */
/*10c0*/ FSETP.GT.AND P0, PT, R19, R16, PT ; /* 0x000000101300720b */
/* 0x000fe20003f04000 */
/*10d0*/ FMUL R21, R21, R22 ; /* 0x0000001615157220 */
/* 0x010fc60000400000 */
/*10e0*/ FSEL R16, R19, R16, P0 ; /* 0x0000001013107208 */
/* 0x000fc80000000000 */
/*10f0*/ FSETP.GT.AND P0, PT, R21, R16, PT ; /* 0x000000101500720b */
/* 0x000fe20003f04000 */
/*1100*/ FMUL R23, R23, R24 ; /* 0x0000001817177220 */
/* 0x020fc60000400000 */
/*1110*/ FSEL R16, R21, R16, P0 ; /* 0x0000001015107208 */
/* 0x000fc80000000000 */
/*1120*/ FSETP.GT.AND P0, PT, R23, R16, PT ; /* 0x000000101700720b */
/* 0x000fc80003f04000 */
/*1130*/ FSEL R16, R23, R16, P0 ; /* 0x0000001017107208 */
/* 0x000fe20000000000 */
/*1140*/ @P1 BRA 0xf90 ; /* 0xfffffe4000001947 */
/* 0x000fea000383ffff */
/*1150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1160*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fda0003f05270 */
/*1170*/ @!P0 BRA 0x12e0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*1180*/ IADD3 R3, P0, P1, R9, R13.reuse, R8 ; /* 0x0000000d09037210 */
/* 0x080fe4000791e008 */
/*1190*/ IADD3 R9, P3, P4, R10, R13, R9 ; /* 0x0000000d0a097210 */
/* 0x000fe40007c7e009 */
/*11a0*/ SHF.R.S32.HI R13, RZ, 0x1f, R13 ; /* 0x0000001fff0d7819 */
/* 0x000fe4000001140d */
/*11b0*/ LEA R2, P2, R3, c[0x0][0x180], 0x2 ; /* 0x0000600003027a11 */
/* 0x000fe400078410ff */
/*11c0*/ LEA R4, P5, R9, c[0x0][0x170], 0x2 ; /* 0x00005c0009047a11 */
/* 0x000fe400078a10ff */
/*11d0*/ IADD3.X R0, R7, R13, R0, P0, P1 ; /* 0x0000000d07007210 */
/* 0x000fc400007e2400 */
/*11e0*/ IADD3.X R6, R6, R13, R7, P3, P4 ; /* 0x0000000d06067210 */
/* 0x000fe40001fe8407 */
/*11f0*/ LEA.HI.X R3, R3, c[0x0][0x184], R0, 0x2, P2 ; /* 0x0000610003037a11 */
/* 0x000fe400010f1400 */
/*1200*/ LEA.HI.X R9, R9, c[0x0][0x174], R6, 0x2, P5 ; /* 0x00005d0009097a11 */
/* 0x000fca00028f1406 */
/*1210*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*1220*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x0000aa000c1e1900 */
/*1230*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x0002a2000c1e1900 */
/*1240*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fc80007ffe0ff */
/*1250*/ ISETP.NE.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f25270 */
/*1260*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fe40007f5e0ff */
/*1270*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x002fc60007f7e0ff */
/*1280*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*1290*/ IMAD.X R9, RZ, RZ, R9, P3 ; /* 0x000000ffff097224 */
/* 0x000fe400018e0609 */
/*12a0*/ FMUL R7, R0, R5 ; /* 0x0000000500077220 */
/* 0x004fca0000400000 */
/*12b0*/ FSETP.GT.AND P0, PT, R7, R16, PT ; /* 0x000000100700720b */
/* 0x000fc80003f04000 */
/*12c0*/ FSEL R16, R7, R16, P0 ; /* 0x0000001007107208 */
/* 0x000fe20000000000 */
/*12d0*/ @P1 BRA 0x1210 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*12e0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*12f0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*1300*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*1310*/ IMAD R2, R11, c[0x0][0x16c], R12 ; /* 0x00005b000b027a24 */
/* 0x000fc800078e020c */
/*1320*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*1330*/ STG.E [R2.64], R16 ; /* 0x0000001002007986 */
/* 0x000fe2000c101906 */
/*1340*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1350*/ BRA 0x1350; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gMaxPoolingForward(float* out, int outRows, int outCols, float* in, int inRows, int inCols, float* mask, int numKernels, int maskCols, int width, int lastWidth) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid >= outRows * outCols)
return;
int rowId = tid / outRows;
int colId = tid % outRows;
float* b = in + (rowId * inCols) + (colId * width);
float* localMask = mask + (rowId / numKernels) * maskCols + colId * width;
if(colId == outRows - 1) {
width = lastWidth;
}
float currentMax = b[0] * localMask[0];
for(int i = 1; i < width; ++i) {
if(b[i] * localMask[i] > currentMax) {
currentMax = b[i] * localMask[i];
}
}
out[rowId + (colId * outCols)] = currentMax;
} | .file "tmpxft_00074b6b_00000000-6_gMaxPoolingForward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii
.type _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii, @function
_Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18gMaxPoolingForwardPfiiS_iiS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii, .-_Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii
.globl _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.type _Z18gMaxPoolingForwardPfiiS_iiS_iiii, @function
_Z18gMaxPoolingForwardPfiiS_iiS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18gMaxPoolingForwardPfiiS_iiS_iiii, .-_Z18gMaxPoolingForwardPfiiS_iiS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18gMaxPoolingForwardPfiiS_iiS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18gMaxPoolingForwardPfiiS_iiS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gMaxPoolingForward(float* out, int outRows, int outCols, float* in, int inRows, int inCols, float* mask, int numKernels, int maskCols, int width, int lastWidth) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid >= outRows * outCols)
return;
int rowId = tid / outRows;
int colId = tid % outRows;
float* b = in + (rowId * inCols) + (colId * width);
float* localMask = mask + (rowId / numKernels) * maskCols + colId * width;
if(colId == outRows - 1) {
width = lastWidth;
}
float currentMax = b[0] * localMask[0];
for(int i = 1; i < width; ++i) {
if(b[i] * localMask[i] > currentMax) {
currentMax = b[i] * localMask[i];
}
}
out[rowId + (colId * outCols)] = currentMax;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gMaxPoolingForward(float* out, int outRows, int outCols, float* in, int inRows, int inCols, float* mask, int numKernels, int maskCols, int width, int lastWidth) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid >= outRows * outCols)
return;
int rowId = tid / outRows;
int colId = tid % outRows;
float* b = in + (rowId * inCols) + (colId * width);
float* localMask = mask + (rowId / numKernels) * maskCols + colId * width;
if(colId == outRows - 1) {
width = lastWidth;
}
float currentMax = b[0] * localMask[0];
for(int i = 1; i < width; ++i) {
if(b[i] * localMask[i] > currentMax) {
currentMax = b[i] * localMask[i];
}
}
out[rowId + (colId * outCols)] = currentMax;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gMaxPoolingForward(float* out, int outRows, int outCols, float* in, int inRows, int inCols, float* mask, int numKernels, int maskCols, int width, int lastWidth) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid >= outRows * outCols)
return;
int rowId = tid / outRows;
int colId = tid % outRows;
float* b = in + (rowId * inCols) + (colId * width);
float* localMask = mask + (rowId / numKernels) * maskCols + colId * width;
if(colId == outRows - 1) {
width = lastWidth;
}
float currentMax = b[0] * localMask[0];
for(int i = 1; i < width; ++i) {
if(b[i] * localMask[i] > currentMax) {
currentMax = b[i] * localMask[i];
}
}
out[rowId + (colId * outCols)] = currentMax;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.globl _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.p2align 8
.type _Z18gMaxPoolingForwardPfiiS_iiS_iiii,@function
_Z18gMaxPoolingForwardPfiiS_iiS_iiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s10, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s10
s_load_b32 s13, s[0:1], 0x1c
s_xor_b32 s11, s4, s10
s_load_b64 s[8:9], s[0:1], 0x30
v_cvt_f32_u32_e32 v0, s11
s_sub_i32 s4, 0, s11
v_add_nc_u32_e32 v4, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s10, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_load_b128 s[4:7], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_waitcnt lgkmcnt(0)
s_ashr_i32 s12, s6, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_hi_u32 v0, v4, v0
s_add_i32 s6, s6, s12
s_xor_b32 s6, s6, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v5, s6
s_sub_i32 s10, 0, s6
v_mul_lo_u32 v2, v0, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_sub_nc_u32_e32 v2, v4, v2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_add_nc_u32 v4, 1, v0
v_subrev_nc_u32_e32 v6, s11, v2
v_cmp_le_u32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s11, v2
v_cvt_u32_f32_e32 v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_lo_u32 v4, s10, v2
s_load_b64 s[10:11], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_hi_u32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_ashrrev_i32_e32 v3, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v5, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v5, v3
v_xor_b32_e32 v3, s12, v3
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s6
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v6, s6, v4
v_cmp_le_u32_e32 vcc_lo, s6, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v4
s_mov_b32 s6, exec_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_mul_lo_u32 v5, v0, s2
s_add_i32 s2, s2, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v2, v3
v_mul_lo_u32 v2, v0, s13
v_sub_nc_u32_e32 v7, v1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_mul_lo_u32 v10, v7, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v3, s7
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s7, 0
v_lshlrev_b64 v[5:6], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[10:11]
v_lshlrev_b64 v[1:2], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, v8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, v9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, v10, v3
v_add_co_ci_u32_e32 v11, vcc_lo, v11, v4, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v10, v[10:11], off
v_mov_b32_e32 v9, s9
v_cmp_eq_u32_e32 vcc_lo, s2, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, s8, v9 :: v_dual_mul_f32 v8, v8, v10
v_cmpx_lt_i32_e32 1, v9
s_cbranch_execz .LBB0_5
v_add_co_u32 v5, vcc_lo, v3, v5
v_add_co_ci_u32_e32 v6, vcc_lo, v4, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, v3, v1
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, v5, s10
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, v1, s4
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, v5, 4
v_add_nc_u32_e32 v9, -1, v9
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v6, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v5, v[1:2], off
global_load_b32 v6, v[3:4], off
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_nc_u32_e32 v9, -1, v9
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 0, v9
s_or_b32 s7, s2, s7
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, v5, v8
v_cndmask_b32_e32 v8, v8, v5, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s7
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v7, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v8, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18gMaxPoolingForwardPfiiS_iiS_iiii, .Lfunc_end0-_Z18gMaxPoolingForwardPfiiS_iiS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18gMaxPoolingForwardPfiiS_iiS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gMaxPoolingForward(float* out, int outRows, int outCols, float* in, int inRows, int inCols, float* mask, int numKernels, int maskCols, int width, int lastWidth) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid >= outRows * outCols)
return;
int rowId = tid / outRows;
int colId = tid % outRows;
float* b = in + (rowId * inCols) + (colId * width);
float* localMask = mask + (rowId / numKernels) * maskCols + colId * width;
if(colId == outRows - 1) {
width = lastWidth;
}
float currentMax = b[0] * localMask[0];
for(int i = 1; i < width; ++i) {
if(b[i] * localMask[i] > currentMax) {
currentMax = b[i] * localMask[i];
}
}
out[rowId + (colId * outCols)] = currentMax;
} | .text
.file "gMaxPoolingForward.hip"
.globl _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii # -- Begin function _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.p2align 4, 0x90
.type _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii,@function
_Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii: # @_Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18gMaxPoolingForwardPfiiS_iiS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii, .Lfunc_end0-_Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18gMaxPoolingForwardPfiiS_iiS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18gMaxPoolingForwardPfiiS_iiS_iiii,@object # @_Z18gMaxPoolingForwardPfiiS_iiS_iiii
.section .rodata,"a",@progbits
.globl _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.p2align 3, 0x0
_Z18gMaxPoolingForwardPfiiS_iiS_iiii:
.quad _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.size _Z18gMaxPoolingForwardPfiiS_iiS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18gMaxPoolingForwardPfiiS_iiS_iiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074b6b_00000000-6_gMaxPoolingForward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii
.type _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii, @function
_Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18gMaxPoolingForwardPfiiS_iiS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii, .-_Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii
.globl _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.type _Z18gMaxPoolingForwardPfiiS_iiS_iiii, @function
_Z18gMaxPoolingForwardPfiiS_iiS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z50__device_stub__Z18gMaxPoolingForwardPfiiS_iiS_iiiiPfiiS_iiS_iiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18gMaxPoolingForwardPfiiS_iiS_iiii, .-_Z18gMaxPoolingForwardPfiiS_iiS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18gMaxPoolingForwardPfiiS_iiS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18gMaxPoolingForwardPfiiS_iiS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gMaxPoolingForward.hip"
.globl _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii # -- Begin function _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.p2align 4, 0x90
.type _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii,@function
_Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii: # @_Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18gMaxPoolingForwardPfiiS_iiS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii, .Lfunc_end0-_Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18gMaxPoolingForwardPfiiS_iiS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18gMaxPoolingForwardPfiiS_iiS_iiii,@object # @_Z18gMaxPoolingForwardPfiiS_iiS_iiii
.section .rodata,"a",@progbits
.globl _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.p2align 3, 0x0
_Z18gMaxPoolingForwardPfiiS_iiS_iiii:
.quad _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.size _Z18gMaxPoolingForwardPfiiS_iiS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18gMaxPoolingForwardPfiiS_iiS_iiii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__gMaxPoolingForwardPfiiS_iiS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18gMaxPoolingForwardPfiiS_iiS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Erik Palmer
* March 1, 2017
*
* This is stripped down version for public sharing. This code
* simulates elastic dumbbells based on the
* Upper Convective Maxwell (UCM) model.
*
* Global variables are used for important parameters, and
* computations are transferred between the CPU (host) and
* GPU (device) as needed for optimal efficiency.
*
* Species switching dynamics have been removed so this
* will only simulate the evolution of "active" dumbbells.
*
* To Compile:
* nvcc CUDA_FILENAME -lcurand -o EXECUTABLE_NAME
*
*/
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <errno.h>
#include <ctype.h>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
//#include <math_functions.h>
//Define Macros for Error handling
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n", __FILE__,__LINE__); \
return EXIT_FAILURE; }} while(0)
#define CURAND_CALL(x) do { if((x)!= CURAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n", __FILE__, __LINE__); \
return EXIT_FAILURE; }} while(0)
//Define Macro for Histogram debugging
#define PRINT_VAR(x) printf("" #x "\n ")
//Debugging Macros
#define PRINT_VAR_FLOAT_VALUE(x) printf("" #x "=%f\n", x)
#define PRINT_VAR_INT_VALUE(x) printf("" #x "=%d\n", x)
//* Also useful: printf("DEBUG LINE %d\n", __LINE__);
//___velocity field on-off matrix ____
// note that this matrix is multiplied by the inputted flowrate value
#define U11 0.0
#define U12 0.0
#define U21 1.0
#define U22 0.0
// | /*
* Erik Palmer
* March 1, 2017
*
* This is stripped down version for public sharing. This code
* simulates elastic dumbbells based on the
* Upper Convective Maxwell (UCM) model.
*
* Global variables are used for important parameters, and
* computations are transferred between the CPU (host) and
* GPU (device) as needed for optimal efficiency.
*
* Species switching dynamics have been removed so this
* will only simulate the evolution of "active" dumbbells.
*
* To Compile:
* nvcc CUDA_FILENAME -lcurand -o EXECUTABLE_NAME
*
*/
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
#include <time.h>
#include <string.h>
#include <errno.h>
#include <ctype.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
//#include <math_functions.h>
//Define Macros for Error handling
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n", __FILE__,__LINE__); \
return EXIT_FAILURE; }} while(0)
#define CURAND_CALL(x) do { if((x)!= HIPRAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n", __FILE__, __LINE__); \
return EXIT_FAILURE; }} while(0)
//Define Macro for Histogram debugging
#define PRINT_VAR(x) printf("" #x "\n ")
//Debugging Macros
#define PRINT_VAR_FLOAT_VALUE(x) printf("" #x "=%f\n", x)
#define PRINT_VAR_INT_VALUE(x) printf("" #x "=%d\n", x)
//* Also useful: printf("DEBUG LINE %d\n", __LINE__);
//___velocity field on-off matrix ____
// note that this matrix is multiplied by the inputted flowrate value
#define U11 0.0
#define U12 0.0
#define U21 1.0
#define U22 0.0
// |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#define N 512
__global__ void dot(int *a, int *b, int *c) {
__shared__ int temp[N];
temp[threadIdx.x] = a[threadIdx.x] * b[threadIdx.x];
__syncthreads();
if (0 == threadIdx.x) {
int sum = 0;
for(int i = 0; i < N; i++)
sum += temp[i];
*c = sum;
}
}
void random_ints(int *a, int size) {
for (int i = 0; i < size; i++) {
a[i] = rand() % 10;
}
}
int main( void ) {
srand(10);
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size = N * sizeof(int);
cudaMalloc((void**)&dev_a, size);
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, sizeof(int));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
random_ints(a, N);
random_ints(b, N);
// копируем ввод на device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
//запускаем на выполнение dot() kernel с 1 блоком и N тредами
dot<<<1, N>>>(dev_a, dev_b, dev_c);
//копируем результат работы device на host копией c
cudaMemcpy(c, dev_c, sizeof(int) , cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++) {
std::cout << a[i] << " " << b[i]<< "\n";
}
std::cout << *c << "\n";
free(a); free(b); free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_00076b95_00000000-6_task6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11random_intsPii
.type _Z11random_intsPii, @function
_Z11random_intsPii:
.LFB3669:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z11random_intsPii, .-_Z11random_intsPii
.globl _Z26__device_stub__Z3dotPiS_S_PiS_S_
.type _Z26__device_stub__Z3dotPiS_S_PiS_S_, @function
_Z26__device_stub__Z3dotPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z3dotPiS_S_PiS_S_, .-_Z26__device_stub__Z3dotPiS_S_PiS_S_
.globl _Z3dotPiS_S_
.type _Z3dotPiS_S_, @function
_Z3dotPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z3dotPiS_S_, .-_Z3dotPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $10, %edi
call srand@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $2048, %edi
call malloc@PLT
movq %rax, %r13
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $4, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $512, %esi
movq %r13, %rdi
call _Z11random_intsPii
movl $512, %esi
movq %r12, %rdi
call _Z11random_intsPii
movl $1, %ecx
movl $2048, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2048, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r15
leaq .LC0(%rip), %r14
.L21:
movl 0(%r13,%rbx), %esi
movq %r15, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl (%r12,%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC1(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq $2048, %rbx
jne .L21
movq 8(%rsp), %rbx
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3dotPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#define N 512
__global__ void dot(int *a, int *b, int *c) {
__shared__ int temp[N];
temp[threadIdx.x] = a[threadIdx.x] * b[threadIdx.x];
__syncthreads();
if (0 == threadIdx.x) {
int sum = 0;
for(int i = 0; i < N; i++)
sum += temp[i];
*c = sum;
}
}
void random_ints(int *a, int size) {
for (int i = 0; i < size; i++) {
a[i] = rand() % 10;
}
}
int main( void ) {
srand(10);
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size = N * sizeof(int);
cudaMalloc((void**)&dev_a, size);
cudaMalloc((void**)&dev_b, size);
cudaMalloc((void**)&dev_c, sizeof(int));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
random_ints(a, N);
random_ints(b, N);
// копируем ввод на device
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
//запускаем на выполнение dot() kernel с 1 блоком и N тредами
dot<<<1, N>>>(dev_a, dev_b, dev_c);
//копируем результат работы device на host копией c
cudaMemcpy(c, dev_c, sizeof(int) , cudaMemcpyDeviceToHost);
for (int i = 0; i < N; i++) {
std::cout << a[i] << " " << b[i]<< "\n";
}
std::cout << *c << "\n";
free(a); free(b); free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#define N 512
__global__ void dot(int *a, int *b, int *c) {
__shared__ int temp[N];
temp[threadIdx.x] = a[threadIdx.x] * b[threadIdx.x];
__syncthreads();
if (0 == threadIdx.x) {
int sum = 0;
for(int i = 0; i < N; i++)
sum += temp[i];
*c = sum;
}
}
void random_ints(int *a, int size) {
for (int i = 0; i < size; i++) {
a[i] = rand() % 10;
}
}
int main( void ) {
srand(10);
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size = N * sizeof(int);
hipMalloc((void**)&dev_a, size);
hipMalloc((void**)&dev_b, size);
hipMalloc((void**)&dev_c, sizeof(int));
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(sizeof(int));
random_ints(a, N);
random_ints(b, N);
// копируем ввод на device
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
//запускаем на выполнение dot() kernel с 1 блоком и N тредами
dot<<<1, N>>>(dev_a, dev_b, dev_c);
//копируем результат работы device на host копией c
hipMemcpy(c, dev_c, sizeof(int) , hipMemcpyDeviceToHost);
for (int i = 0; i < N; i++) {
std::cout << a[i] << " " << b[i]<< "\n";
}
std::cout << *c << "\n";
free(a); free(b); free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
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